; --------------------------------------------------------------------------------
; @Title: AM273x On-Chip Peripherals
; @Props: Released
; @Author: ADR, PIW
; @Changelog: 2022-01-25 ADR
;             2022-04-26 PIW
; @Manufacturer: TI - Texas Instruments
; @Doc: XML generated (TIXML2PER 2.0.4), based on: am273x.xml (Rev. 1)
; @Core: Cortex-R5F, Cortex-M4, C66X
; @Chip: AM2732, AM2732-HSM, AM2732-HWA, AM2732DSP
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: peram273x.per 17736 2024-04-08 09:26:07Z kwisniewski $

sif (CORENAME()=="CORTEXM4")
tree.close "Core Registers (Cortex-M4)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "System Control"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 12.
group.long 0x08++0x03
line.long 0x00 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 9. " DISFPCA        ,Disables lazy stacking of floating point context" "No,Yes"
bitfld.long 0x00 8. "                   DISOOFP        ,Disables floating point instructions completing" "No,Yes"
bitfld.long 0x00 2. "              DISFOLD         ,Disables folding of IT instructions" "No,Yes"
textline "                     "
bitfld.long 0x00 1. " DISDEFWBUF     ,Disables write buffer use during default memory map accesses" "No,Yes"
bitfld.long 0x00 0. "                   DISMCYCINT     ,Disables interruption of multi-cycle instructions" "No,Yes"
group.long 0x10++0x0B
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
rbitfld.long 0x00 16. " COUNTFLAG      ,Counter Flag" "Not counted,Counted"
bitfld.long 0x00 2. "           CLKSOURCE      ,SysTick clock source" "External,Core"
bitfld.long 0x00 1. "         TICKINT         ,SysTick Handler" "No SysTick,SysTick"
textline "                     "
bitfld.long 0x00 0. " ENABLE         ,Counter Enable" "Disabled,Enabled"
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD         ,The value to load into the SYST_CVR when the counter reaches 0"
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
rgroup.long 0x1C++0x03
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
bitfld.long 0x00 31. " NOREF          ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
bitfld.long 0x00 30. "       SKEW           ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
hexmask.long.tbyte 0x00 0.--23. 1. "          TENMS           ,Holds a reload value to be used for 10ms (100Hz) timing"
rgroup.long 0xD00++0x03
line.long 0x00 "CPUID,CPU ID Base Register"
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER    ,Implementer Code"
bitfld.long 0x00 20.--23. "                    VARIANT        ,Indicates processor revision" "Revision 0,?..."
bitfld.long 0x00 16.--19. "       ARCHITECTURE    ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                     "
hexmask.long.word 0x00 4.--15. 1. " PARTNO         ,Indicates part number"
bitfld.long 0x00 0.--3. "                  REVISION       ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xD04++0x23
line.long 0x00 "ICSR,Interrupt Control State Register"
bitfld.long 0x00 31. " NMIPENDSET     ,Set Pending NMI Bit" "Inactive,Active"
bitfld.long 0x00 28. "              PENDSVSET      ,Set Pending pendSV Bit" "Not pending,Pending"
bitfld.long 0x00 27. "      PENDSVCLR       ,Removes the pending status of the PendSV exception" "No effect,Removed"
textline "                     "
bitfld.long 0x00 26. " PENDSTSET      ,Set Pending SysTick Bit" "Not pending,Pending"
bitfld.long 0x00 25. "           PENDSTCLR      ,Clear Pending SysTick Bit" "No effect,Removed"
bitfld.long 0x00 23. "        ISRPREEMPT      ,Use Only at Debug Time" "Not active,Active"
textline "                     "
bitfld.long 0x00 22. " ISRPENDING     ,Indicates whether an external interrupt" "Not pending,Pending"
hexmask.long.word 0x00 12.--20. 1. "           VECTPENDING    ,Pending ISR Number Field"
bitfld.long 0x00 11. "             RETTOBASE       ,Interrupt Exception" "Active,Not active"
textline "                     "
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE     ,The exception number of the current executing exception"
line.long 0x04 "VTOR,Vector Table Offset Register"
hexmask.long 0x04 7.--31. 0x80 " TBLOFF         ,Vector table address"
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
hexmask.long.word 0x08 16.--31. 1. " VECTKEY        ,Register Key"
rbitfld.long 0x08 15. "                  ENDIANESS      ,Data endianness Bit" "Little,Big"
bitfld.long 0x08 8.--10. "           PRIGROUP        ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
textline "                     "
bitfld.long 0x08 2. " SYSRESETREQ    ,System Reset Request" "Not requested,Requested"
bitfld.long 0x08 1. "         VECTCLRACTIVE  ,Clear Active Vector Bit" "No effect,Clear"
bitfld.long 0x08 0. "        VECTRESET       ,System Reset" "No effect,Reset"
line.long 0x0C "SCR,System Control Register"
bitfld.long 0x0C 4. " SEVONPEND      ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
bitfld.long 0x0C 2. "            SLEEPDEEP      ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
bitfld.long 0x0C 1. "   SLEEPONEXIT     ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
line.long 0x10 "CCR,Configuration Control Register"
bitfld.long 0x10 18. " BP             ,Branch prediction enable bit" "Disabled,Enabled"
bitfld.long 0x10 17. "              IC             ,Instruction cache enable bit" "Disabled,Enabled"
bitfld.long 0x10 16. "         DC              ,Cache enable bit" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 9. " STKALIGN       ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
bitfld.long 0x10 8. "  BFHFNMIGN      ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
bitfld.long 0x10 4. "         DIV_0_TRP       ,Trap Divide by Zero" "Disabled,Enabled"
textline "                     "
bitfld.long 0x10 3. " UNALIGN_TRP    ,Trap for Unaligned Access" "Disabled,Enabled"
bitfld.long 0x10 1. "              USERSETMPEND   ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
bitfld.long 0x10 0. "          NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
hexmask.long.byte 0x14 24.--31. 1. " PRI_7          ,Priority of System Handler 7"
hexmask.long.byte 0x14 16.--23. 1. "                    PRI_6          ,Priority of system handler 6(UsageFault)"
hexmask.long.byte 0x14 8.--15. 1. "               PRI_5           ,Priority of system handler 5(BusFault)"
textline "                     "
hexmask.long.byte 0x14 0.--7. 1. " PRI_4          ,Priority of system handler 4(MemManage)"
line.long 0x18 "SHPR2,System Handler Priority Register 2"
hexmask.long.byte 0x18 24.--31. 1. " PRI_11         ,Priority of system handler 11(SVCall)"
hexmask.long.byte 0x18 16.--23. 1. "                    PRI_10         ,Priority of System Handler 10"
hexmask.long.byte 0x18 8.--15. 1. "               PRI_9           ,Priority of System Handler 9"
textline "                     "
hexmask.long.byte 0x18 0.--7. 1. " PRI_8          ,Priority of System Handler 8"
line.long 0x1C "SHPR3,System Handler Priority Register 3"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15         ,Priority of System Handler 15(SysTick)"
hexmask.long.byte 0x1C 16.--23. 1. "                    PRI_14         ,Priority of System Handler 14(PendSV)"
hexmask.long.byte 0x1C 8.--15. 1. "               PRI_13          ,Priority of System Handler 13"
textline "                     "
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12         ,Priority of System Handler 12(DebugMonitor)"
line.long 0x20 "SHCSR,System Handler Control and State Register"
bitfld.long 0x20 18. " USGFAULTENA    ,Enable UsageFault" "Disabled,Enabled"
bitfld.long 0x20 17. "              BUSFAULTENA    ,Enable BusFault" "Disabled,Enabled"
bitfld.long 0x20 16. "         MEMFAULTENA     ,Enable MemManage fault" "Disabled,Enabled"
textline "                     "
bitfld.long 0x20 15. " SVCALLPENDED   ,SVCall is pending" "Not pending,Pending"
bitfld.long 0x20 14. "           BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
bitfld.long 0x20 13. "      MEMFAULTPENDED  ,MemManage is pending" "Not pending,Pending"
textline "                     "
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
bitfld.long 0x20 11. "           SYSTICKACT     ,SysTick is Active" "Not active,Active"
bitfld.long 0x20 10. "       PENDSVACT       ,PendSV is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 8. " MONITORACT     ,Monitor is Active" "Not active,Active"
bitfld.long 0x20 7. "            SVCALLACT      ,SVCall is Active" "Not active,Active"
bitfld.long 0x20 3. "       USGFAULTACT     ,UsageFault is Active" "Not active,Active"
textline "                     "
bitfld.long 0x20 1. " BUSFAULTACT    ,BusFault is Active" "Not active,Active"
bitfld.long 0x20 0. "            MEMFAULTACT    ,MemManage is Active" "Not active,Active"
group.byte 0xD28++0x1
line.byte 0x00 "MMFSR,MemManage Status Register"
bitfld.byte 0x00 7. "       MMARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x00 5. "             MLSPERR        ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x00 4. "     MSTKERR         ,tacking Access Violations" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x00 3. " MUNSTKERR      ,Unstack Access Violations" "Not occurred,Occurred"
bitfld.byte 0x00 1. "          DACCVIOL       ,Data Access Violation" "Not occurred,Occurred"
bitfld.byte 0x00 0. "     IACCVIOL        ,Instruction Access Violation" "Not occurred,Occurred"
line.byte 0x01 "BFSR,Bus Fault Status Register"
bitfld.byte 0x01 7. "       BFARVALID      ,Address Valid Flag" "Not valid,Valid"
bitfld.byte 0x01 5. "             LSPERR         ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
bitfld.byte 0x01 4. "     STKERR          ,Derived bus fault(exception entry)" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 3. " UNSTKERR       ,Derived bus fault(exception return)" "Not occurred,Occurred"
bitfld.byte 0x01 2. "          IMPRECISERR    ,Imprecise data access error" "Not occurred,Occurred"
bitfld.byte 0x01 1. "     PRECISERR       ,Precise data access error" "Not occurred,Occurred"
textline "                     "
bitfld.byte 0x01 0. " IBUSERR        ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
group.word 0xD2A++0x1
line.word 0x00 "USAFAULT,Usage Fault Status Register"
bitfld.word 0x00 9. "     DIVBYZERO      ,Divide by zero error" "No error,Error"
bitfld.word 0x00 8. "              UNALIGNED      ,Unaligned access error" "No error,Error"
bitfld.word 0x00 3. "         NOCP            ,A coprocessor access error" "No error,Error"
textline "                     "
bitfld.word 0x00 2. " INVPC          ,An integrity check error" "No error,Error"
bitfld.word 0x00 1. "              INVSTATE       ,Invalid Combination of EPSR and Instruction" "No error,Error"
bitfld.word 0x00 0. "         UNDEFINSTR      ,Undefined instruction error" "No error,Error"
group.long 0xD2C++0x07
line.long 0x00 "HFSR,Hard Fault Status Register"
bitfld.long 0x00 31. " DEBUGEVT       ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
bitfld.long 0x00 30. "          FORCED         ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
bitfld.long 0x00 1. "     VECTTBL         ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
line.long 0x04 "DFSR,Debug Fault Status Register"
bitfld.long 0x04 4. " EXTERNAL       ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
bitfld.long 0x04 3. "          VCATCH         ,Vector Catch Flag" "Not occurred,Occurred"
bitfld.long 0x04 2. "     DWTTRAP         ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
textline "                     "
bitfld.long 0x04 1. " BKPT           ,BKPT Flag" "Not executed,Executed"
bitfld.long 0x04 0. "          HALTED         ,Indicates a debug event generated by either" "Not requested,Requested"
group.long 0xD34++0x0B
line.long 0x00 "MMFAR,MemManage Fault Address Register"
line.long 0x04 "BFAR,BusFault Address Register"
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
group.long 0xD88++0x03
line.long 0x00 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x00 22.--23. " CP11           ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 20.--21. "       CP10           ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 14.--15. "  CP7             ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 12.--13. " CP6            ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 10.--11. "       CP5            ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 8.--9. "  CP4             ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 6.--7. " CP3            ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 4.--5. "       CP2            ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
bitfld.long 0x00 2.--3. "  CP1             ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
textline "                     "
bitfld.long 0x00 0.--1. " CP0            ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
wgroup.long 0xF00++0x03
line.long 0x00 "STIR,Software Trigger Interrupt Register"
hexmask.long.word 0x00 0.--8. 1. " INTID          ,Indicates the interrupt to be triggered"
width 10.
tree "Feature Registers"
rgroup.long 0xD40++0x0B
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 4.--7. " STATE1    ,Thumb instruction set support" ",,,Supported,?..."
bitfld.long 0x00 0.--3. "              STATE0         ,ARM instruction set support" "Not supported,?..."
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x04 8.--11. " MPROF     ,M profile programmers' model" ",,2-stack,?..."
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x08 20.--23. " DBGMOD    ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
hgroup.long 0xD4C++0x03
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long 0xD50++0x03
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 20.--23. " AUXREG    ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
bitfld.long 0x00 16.--19. "          TCMSUP         ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
bitfld.long 0x00 12.--15. "        SHRLEV    ,Indicates the number of shareability levels implemented" "Level 1,?..."
textline "                   "
bitfld.long 0x00 8.--11. " OUTMSHR   ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
bitfld.long 0x00 4.--7. "          PMSASUP        ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
hgroup.long 0xD54++0x03
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
rgroup.long 0xD58++0x03
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 24.--27. " WFISTALL  ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
rgroup.long 0xD60++0x13
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVIDE    ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
bitfld.long 0x00 20.--23. "          DEBUG          ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
bitfld.long 0x00 16.--19. "        COPROC    ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
textline "                   "
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
bitfld.long 0x00 8.--11. "          BITFIELD       ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
bitfld.long 0x00 4.--7. "    BITCOUNT  ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
bitfld.long 0x04 20.--23. "          IMMEDIATE      ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
bitfld.long 0x04 16.--19. "  IFTHEN    ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
textline "                   "
bitfld.long 0x04 12.--15. " EXTEND    ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x08 24.--27. " REVERSAL  ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
bitfld.long 0x08 20.--23. "   MULTU          ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
bitfld.long 0x08 16.--19. "    MULTS     ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
textline "                   "
bitfld.long 0x08 12.--15. " MULT      ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
bitfld.long 0x08 8.--11. "          MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
bitfld.long 0x08 4.--7. "  MEMHINT   ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
textline "                   "
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x0C 24.--27. " TRUENOP   ,Indicates the support for a true  NOP instruction" "Not supported,Supported,?..."
bitfld.long 0x0C 20.--23. "          THUMBCOPY      ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
bitfld.long 0x0C 16.--19. "        TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
textline "                   "
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x0C 8.--11. "          SVC            ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
bitfld.long 0x0C 4.--7. "        SIMD      ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
textline "                   "
bitfld.long 0x0C 0.--3. " SATURATE  ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x10 24.--27. " PSR_M     ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
bitfld.long 0x10 20.--23. "          SYNCHPRIMFRAC  ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
bitfld.long 0x10 16.--19. "        BARRIER   ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
textline "                   "
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
bitfld.long 0x10 4.--7. "          WITHSHIFTS     ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
bitfld.long 0x10 0.--3. "        UNPRIV    ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
tree.end
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0C "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0C "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Memory Protection Unit"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 15.
rgroup.long 0xD90++0x03
line.long 0x00 "MPU_TYPE,MPU Type Register"
bitfld.long 0x00 16.--23. " IREGION    ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 8.--15. "               DREGION   ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
bitfld.long 0x00 0. "                    SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
group.long 0xD94++0x03
line.long 0x00 "MPU_CTRL,MPU Control Register"
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
bitfld.long 0x00 1. "         HFNMIENA  ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
bitfld.long 0x00 0. "          ENABLE   ,Enables the MPU" "Disabled,Enabled"
group.long 0xD98++0x03
line.long 0x00 "MPU_RNR,MPU Region Number Register"
hexmask.long.byte 0x00 0.--7. 1. " REGION     ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
tree.close "MPU regions"
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
group.long 0xD9C++0x03 "Region 0"
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x0
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x0
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
group.long 0xD9C++0x03 "Region 1"
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x1
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x1
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
group.long 0xD9C++0x03 "Region 2"
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x2
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x2
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
group.long 0xD9C++0x03 "Region 3"
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x3
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x3
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
group.long 0xD9C++0x03 "Region 4"
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x4
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x4
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
group.long 0xD9C++0x03 "Region 5"
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x5
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x5
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
group.long 0xD9C++0x03 "Region 6"
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x6
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x6
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
group.long 0xD9C++0x03 "Region 7"
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x7
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x7
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
group.long 0xD9C++0x03 "Region 8"
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x8
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x8
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
group.long 0xD9C++0x03 "Region 9"
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0x9
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0x9
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
group.long 0xD9C++0x03 "Region 10"
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xA
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xA
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
group.long 0xD9C++0x03 "Region 11"
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xB
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xB
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
group.long 0xD9C++0x03 "Region 12"
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xC
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xC
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
group.long 0xD9C++0x03 "Region 13"
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xD
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xD
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
group.long 0xD9C++0x03 "Region 14"
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xE
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xE
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
textline "                        "
textline "                        "
endif
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
group.long 0xD9C++0x03 "Region 15"
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " ADDR       ,Base address of the region"
group.long 0xDA0++0x03
saveout 0xD98 %l 0xF
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
bitfld.long 0x00 28. " XN         ,eXecute Never" "Execute,Not execute"
bitfld.long 0x00 24.--26. "      AP        ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
bitfld.long 0x00 19.--21. "             TEX      ,Type Extension Field" "0,1,2,3,4,5,6,7"
textline "                        "
bitfld.long 0x00 18. " S          ,Shareable Bit" "Not shareable,Shareable"
bitfld.long 0x00 17. "    C         ,Cacheable Bit" "Not cacheable,Cacheable"
bitfld.long 0x00 16. "         B        ,Bufferable Bit" "Not bufferable,Bufferable"
textline "                        "
bitfld.long 0x00 15. " SRD[7..0]  ,Subregion 7 Disable" "0,1"
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
bitfld.long 0x00 1.--5. "         SIZE      ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
bitfld.long 0x00 0. "                ENABLE   ,Enables this region" "Disabled,Enabled"
else
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
hgroup.long 0xDA0++0x03
saveout 0xD98 %l 0xF
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
textline "                        "
textline "                        "
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Nested Vectored Interrupt Controller"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 6.
rgroup.long 0x04++0x03
line.long 0x00 "ICTR,Interrupt Controller Type Register"
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
tree "Interrupt Enable Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x100++0x03
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x100++0x7
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x100++0x0B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x100++0x0F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x100++0x13
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x100++0x17
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x100++0x1B
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x100++0x1F
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  ENA30  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  ENA29  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  ENA28  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  ENA27  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  ENA26  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  ENA24  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  ENA23  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  ENA22  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  ENA21  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  ENA20  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  ENA18  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  ENA17  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  ENA16  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  ENA15  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  ENA14  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  ENA12  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  ENA11  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  ENA10  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  ENA9   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  ENA8   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  ENA6   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  ENA5   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  ENA4   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  ENA3   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  ENA2   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  ENA0   ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  ENA62  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  ENA61  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  ENA60  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  ENA59  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  ENA58  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  ENA56  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  ENA55  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  ENA54  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  ENA53  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  ENA52  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  ENA50  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  ENA49  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  ENA48  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  ENA47  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  ENA46  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  ENA44  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  ENA43  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  ENA42  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  ENA41  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  ENA40  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  ENA38  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  ENA37  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  ENA36  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  ENA35  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  ENA34  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  ENA32  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  ENA94  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  ENA93  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  ENA92  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  ENA91  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  ENA90  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  ENA88  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  ENA87  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  ENA86  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  ENA85  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  ENA84  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  ENA82  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  ENA81  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  ENA80  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  ENA79  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  ENA78  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  ENA76  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  ENA75  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  ENA74  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  ENA73  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  ENA72  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  ENA70  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  ENA69  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  ENA68  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  ENA67  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  ENA66  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  ENA64  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  ENA99  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  ENA98  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  ENA96  ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
else
hgroup.long 0x100++0x1F
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
endif
tree.end
tree "Interrupt Pending Registers"
width 23.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x200++0x03
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x200++0x07
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x200++0x0B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x200++0x0F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x200++0x13
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x200++0x17
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x200++0x1B
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x200++0x1F
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 30. 0x00 30. 0x80 30. "  PEN30  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 29. 0x00 29. 0x80 29. "  PEN29  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 28. 0x00 28. 0x80 28. "  PEN28  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 27. 0x00 27. 0x80 27. "  PEN27  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 26. 0x00 26. 0x80 26. "  PEN26  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 24. 0x00 24. 0x80 24. "  PEN24  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 23. 0x00 23. 0x80 23. "  PEN23  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 22. 0x00 22. 0x80 22. "  PEN22  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 21. 0x00 21. 0x80 21. "  PEN21  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 20. 0x00 20. 0x80 20. "  PEN20  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 18. 0x00 18. 0x80 18. "  PEN18  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 17. 0x00 17. 0x80 17. "  PEN17  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 16. 0x00 16. 0x80 16. "  PEN16  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 15. 0x00 15. 0x80 15. "  PEN15  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 14. 0x00 14. 0x80 14. "  PEN14  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 12. 0x00 12. 0x80 12. "  PEN12  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 11. 0x00 11. 0x80 11. "  PEN11  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 10. 0x00 10. 0x80 10. "  PEN10  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 9. 0x00 9. 0x80 9. "  PEN9   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 8. 0x00 8. 0x80 8. "  PEN8   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 6. 0x00 6. 0x80 6. "  PEN6   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 5. 0x00 5. 0x80 5. "  PEN5   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 4. 0x00 4. 0x80 4. "  PEN4   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 3. 0x00 3. 0x80 3. "  PEN3   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 2. 0x00 2. 0x80 2. "  PEN2   ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1   ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x00 0. 0x00 0. 0x80 0. "  PEN0   ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 30. 0x04 30. 0x84 30. "  PEN62  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 29. 0x04 29. 0x84 29. "  PEN61  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 28. 0x04 28. 0x84 28. "  PEN60  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 27. 0x04 27. 0x84 27. "  PEN59  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 26. 0x04 26. 0x84 26. "  PEN58  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 24. 0x04 24. 0x84 24. "  PEN56  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 23. 0x04 23. 0x84 23. "  PEN55  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 22. 0x04 22. 0x84 22. "  PEN54  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 21. 0x04 21. 0x84 21. "  PEN53  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 20. 0x04 20. 0x84 20. "  PEN52  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 18. 0x04 18. 0x84 18. "  PEN50  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 17. 0x04 17. 0x84 17. "  PEN49  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 16. 0x04 16. 0x84 16. "  PEN48  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 15. 0x04 15. 0x84 15. "  PEN47  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 14. 0x04 14. 0x84 14. "  PEN46  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 12. 0x04 12. 0x84 12. "  PEN44  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 11. 0x04 11. 0x84 11. "  PEN43  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 10. 0x04 10. 0x84 10. "  PEN42  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 9. 0x04 9. 0x84 9. "  PEN41  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 8. 0x04 8. 0x84 8. "  PEN40  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 6. 0x04 6. 0x84 6. "  PEN38  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 5. 0x04 5. 0x84 5. "  PEN37  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 4. 0x04 4. 0x84 4. "  PEN36  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 3. 0x04 3. 0x84 3. "  PEN35  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 2. 0x04 2. 0x84 2. "  PEN34  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x04 0. 0x04 0. 0x84 0. "  PEN32  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 30. 0x08 30. 0x88 30. "  PEN94  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 29. 0x08 29. 0x88 29. "  PEN93  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 28. 0x08 28. 0x88 28. "  PEN92  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 27. 0x08 27. 0x88 27. "  PEN91  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 26. 0x08 26. 0x88 26. "  PEN90  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 24. 0x08 24. 0x88 24. "  PEN88  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 23. 0x08 23. 0x88 23. "  PEN87  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 22. 0x08 22. 0x88 22. "  PEN86  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 21. 0x08 21. 0x88 21. "  PEN85  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 20. 0x08 20. 0x88 20. "  PEN84  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 18. 0x08 18. 0x88 18. "  PEN82  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 17. 0x08 17. 0x88 17. "  PEN81  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 16. 0x08 16. 0x88 16. "  PEN80  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 15. 0x08 15. 0x88 15. "  PEN79  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 14. 0x08 14. 0x88 14. "  PEN78  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 12. 0x08 12. 0x88 12. "  PEN76  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 11. 0x08 11. 0x88 11. "  PEN75  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 10. 0x08 10. 0x88 10. "  PEN74  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 9. 0x08 9. 0x88 9. "  PEN73  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 8. 0x08 8. 0x88 8. "  PEN72  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 6. 0x08 6. 0x88 6. "  PEN70  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 5. 0x08 5. 0x88 5. "  PEN69  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 4. 0x08 4. 0x88 4. "  PEN68  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 3. 0x08 3. 0x88 3. "  PEN67  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 2. 0x08 2. 0x88 2. "  PEN66  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x08 0. 0x08 0. 0x88 0. "  PEN64  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. "  PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. "  PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. "  PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. "  PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. "  PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. "  PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. "  PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. "  PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. "  PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. "  PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. "  PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. "  PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. "  PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. "  PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. "  PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. "  PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. "  PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. "  PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. "  PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. "  PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. "  PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. "  PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. "  PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. "  PEN99  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. "  PEN98  ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97  ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. "  PEN96  ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 30. 0x10 30. 0x90 30. "  PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 29. 0x10 29. 0x90 29. "  PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 28. 0x10 28. 0x90 28. "  PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 27. 0x10 27. 0x90 27. "  PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 26. 0x10 26. 0x90 26. "  PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 24. 0x10 24. 0x90 24. "  PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 23. 0x10 23. 0x90 23. "  PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 22. 0x10 22. 0x90 22. "  PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 21. 0x10 21. 0x90 21. "  PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 20. 0x10 20. 0x90 20. "  PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 18. 0x10 18. 0x90 18. "  PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 17. 0x10 17. 0x90 17. "  PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 16. 0x10 16. 0x90 16. "  PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 15. 0x10 15. 0x90 15. "  PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 14. 0x10 14. 0x90 14. "  PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 12. 0x10 12. 0x90 12. "  PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 11. 0x10 11. 0x90 11. "  PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 10. 0x10 10. 0x90 10. "  PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 9. 0x10 9. 0x90 9. "  PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 8. 0x10 8. 0x90 8. "  PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 6. 0x10 6. 0x90 6. "  PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 5. 0x10 5. 0x90 5. "  PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 4. 0x10 4. 0x90 4. "  PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 3. 0x10 3. 0x90 3. "  PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 2. 0x10 2. 0x90 2. "  PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x10 0. 0x10 0. 0x90 0. "  PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 30. 0x14 30. 0x94 30. "  PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 29. 0x14 29. 0x94 29. "  PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 28. 0x14 28. 0x94 28. "  PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 27. 0x14 27. 0x94 27. "  PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 26. 0x14 26. 0x94 26. "  PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 24. 0x14 24. 0x94 24. "  PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 23. 0x14 23. 0x94 23. "  PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 22. 0x14 22. 0x94 22. "  PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 21. 0x14 21. 0x94 21. "  PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 20. 0x14 20. 0x94 20. "  PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 18. 0x14 18. 0x94 18. "  PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 17. 0x14 17. 0x94 17. "  PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 16. 0x14 16. 0x94 16. "  PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 15. 0x14 15. 0x94 15. "  PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 14. 0x14 14. 0x94 14. "  PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 12. 0x14 12. 0x94 12. "  PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 11. 0x14 11. 0x94 11. "  PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 10. 0x14 10. 0x94 10. "  PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 9. 0x14 9. 0x94 9. "  PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 8. 0x14 8. 0x94 8. "  PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 6. 0x14 6. 0x94 6. "  PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 5. 0x14 5. 0x94 5. "  PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 4. 0x14 4. 0x94 4. "  PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 3. 0x14 3. 0x94 3. "  PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 2. 0x14 2. 0x94 2. "  PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x14 0. 0x14 0. 0x94 0. "  PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 30. 0x18 30. 0x98 30. "  PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 29. 0x18 29. 0x98 29. "  PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 28. 0x18 28. 0x98 28. "  PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 27. 0x18 27. 0x98 27. "  PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 26. 0x18 26. 0x98 26. "  PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 24. 0x18 24. 0x98 24. "  PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 23. 0x18 23. 0x98 23. "  PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 22. 0x18 22. 0x98 22. "  PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 21. 0x18 21. 0x98 21. "  PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 20. 0x18 20. 0x98 20. "  PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 18. 0x18 18. 0x98 18. "  PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 17. 0x18 17. 0x98 17. "  PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 16. 0x18 16. 0x98 16. "  PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 15. 0x18 15. 0x98 15. "  PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 14. 0x18 14. 0x98 14. "  PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 12. 0x18 12. 0x98 12. "  PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 11. 0x18 11. 0x98 11. "  PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 10. 0x18 10. 0x98 10. "  PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 9. 0x18 9. 0x98 9. "  PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 8. 0x18 8. 0x98 8. "  PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 6. 0x18 6. 0x98 6. "  PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 5. 0x18 5. 0x98 5. "  PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 4. 0x18 4. 0x98 4. "  PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 3. 0x18 3. 0x98 3. "  PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 2. 0x18 2. 0x98 2. "  PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x18 0. 0x18 0. 0x98 0. "  PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. "  PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. "  PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. "  PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. "  PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. "  PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. "  PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. "  PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. "  PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. "  PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. "  PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
textline "                                "
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. "  PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. "  PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. "  PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
else
hgroup.long 0x200++0x1F
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
endif
tree.end
tree "Interrupt Active Bit Registers"
width 9.
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
rgroup.long 0x300++0x03
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
rgroup.long 0x300++0x07
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
rgroup.long 0x300++0x0B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
rgroup.long 0x300++0x0F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
rgroup.long 0x300++0x13
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
rgroup.long 0x300++0x17
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
rgroup.long 0x300++0x1B
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
rgroup.long 0x300++0x1F
line.long 0x00 "ACTIVE1,Active Bit Register 1"
bitfld.long 0x00 31. " ACTIVE31  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 30. "  ACTIVE30  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 29. "  ACTIVE29  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 28. "  ACTIVE28  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 27. "  ACTIVE27  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 26. "  ACTIVE26  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 25. " ACTIVE25  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 24. "  ACTIVE24  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 23. "  ACTIVE23  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 22. "  ACTIVE22  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 21. "  ACTIVE21  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 20. "  ACTIVE20  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 19. " ACTIVE19  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 18. "  ACTIVE18  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 17. "  ACTIVE17  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 16. "  ACTIVE16  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 15. "  ACTIVE15  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 14. "  ACTIVE14  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 13. " ACTIVE13  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 12. "  ACTIVE12  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 11. "  ACTIVE11  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 10. "  ACTIVE10  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 9. "  ACTIVE9   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 8. "  ACTIVE8   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 7. " ACTIVE7   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 6. "  ACTIVE6   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 5. "  ACTIVE5   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 4. "  ACTIVE4   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 3. "  ACTIVE3   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 2. "  ACTIVE2   ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x00 1. " ACTIVE1   ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x00 0. "  ACTIVE0   ,Interrupt Active Flag" "Not active,Active"
line.long 0x04 "ACTIVE2,Active Bit Register 2"
bitfld.long 0x04 31. " ACTIVE63  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 30. "  ACTIVE62  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 29. "  ACTIVE61  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 28. "  ACTIVE60  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 27. "  ACTIVE59  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 26. "  ACTIVE58  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 25. " ACTIVE57  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 24. "  ACTIVE56  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 23. "  ACTIVE55  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 22. "  ACTIVE54  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 21. "  ACTIVE53  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 20. "  ACTIVE52  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 19. " ACTIVE51  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 18. "  ACTIVE50  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 17. "  ACTIVE49  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 16. "  ACTIVE48  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 15. "  ACTIVE47  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 14. "  ACTIVE46  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 13. " ACTIVE45  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 12. "  ACTIVE44  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 11. "  ACTIVE43  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 10. "  ACTIVE42  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 9. "  ACTIVE41  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 8. "  ACTIVE40  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 7. " ACTIVE39  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 6. "  ACTIVE38  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 5. "  ACTIVE37  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 4. "  ACTIVE36  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 3. "  ACTIVE35  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 2. "  ACTIVE34  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x04 1. " ACTIVE33  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x04 0. "  ACTIVE32  ,Interrupt Active Flag" "Not active,Active"
line.long 0x08 "ACTIVE3,Active Bit Register 3"
bitfld.long 0x08 31. " ACTIVE95  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 30. "  ACTIVE94  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 29. "  ACTIVE93  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 28. "  ACTIVE92  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 27. "  ACTIVE91  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 26. "  ACTIVE90  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 25. " ACTIVE89  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 24. "  ACTIVE88  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 23. "  ACTIVE87  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 22. "  ACTIVE86  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 21. "  ACTIVE85  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 20. "  ACTIVE84  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 19. " ACTIVE83  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 18. "  ACTIVE82  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 17. "  ACTIVE81  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 16. "  ACTIVE80  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 15. "  ACTIVE79  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 14. "  ACTIVE78  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 13. " ACTIVE77  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 12. "  ACTIVE76  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 11. "  ACTIVE75  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 10. "  ACTIVE74  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 9. "  ACTIVE73  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 8. "  ACTIVE72  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 7. " ACTIVE71  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 6. "  ACTIVE70  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 5. "  ACTIVE69  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 4. "  ACTIVE68  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 3. "  ACTIVE67  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 2. "  ACTIVE66  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x08 1. " ACTIVE65  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x08 0. "  ACTIVE64  ,Interrupt Active Flag" "Not active,Active"
line.long 0x0c "ACTIVE4,Active Bit Register 4"
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 30. "  ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 29. "  ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 28. "  ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 27. "  ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 26. "  ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 24. "  ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 23. "  ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 22. "  ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 21. "  ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 20. "  ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 18. "  ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 17. "  ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 16. "  ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 15. "  ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 14. "  ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 12. "  ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 11. "  ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 10. "  ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 9. "  ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 8. "  ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 6. "  ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 5. "  ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 4. "  ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 3. "  ACTIVE99  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 2. "  ACTIVE98  ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x0c 1. " ACTIVE97  ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x0c 0. "  ACTIVE96  ,Interrupt Active Flag" "Not active,Active"
line.long 0x10 "ACTIVE5,Active Bit Register 5"
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 30. "  ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 29. "  ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 28. "  ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 27. "  ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 26. "  ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 24. "  ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 23. "  ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 22. "  ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 21. "  ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 20. "  ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 18. "  ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 17. "  ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 16. "  ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 15. "  ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 14. "  ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 12. "  ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 11. "  ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 10. "  ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 9. "  ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 8. "  ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 6. "  ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 5. "  ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 4. "  ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 3. "  ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 2. "  ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x10 0. "  ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
line.long 0x14 "ACTIVE6,Active Bit Register 6"
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 30. "  ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 29. "  ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 28. "  ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 27. "  ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 26. "  ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 24. "  ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 23. "  ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 22. "  ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 21. "  ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 20. "  ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 18. "  ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 17. "  ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 16. "  ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 15. "  ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 14. "  ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 12. "  ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 11. "  ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 10. "  ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 9. "  ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 8. "  ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 6. "  ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 5. "  ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 4. "  ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 3. "  ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 2. "  ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x14 0. "  ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
line.long 0x18 "ACTIVE7,Active Bit Register 7"
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 30. "  ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 29. "  ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 28. "  ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 27. "  ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 26. "  ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 24. "  ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 23. "  ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 22. "  ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 21. "  ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 20. "  ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 18. "  ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 17. "  ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 16. "  ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 15. "  ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 14. "  ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 12. "  ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 11. "  ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 10. "  ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 9. "  ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 8. "  ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 6. "  ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 5. "  ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 4. "  ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 3. "  ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 2. "  ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x18 0. "  ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
line.long 0x1c "ACTIVE8,Active Bit Register 8"
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 14. "  ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 13. "  ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 12. "  ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 11. "  ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 10. "  ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 8. "  ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 7. "  ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 6. "  ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 5. "  ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 4. "  ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
textline "                  "
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 2. "  ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 1. "  ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
bitfld.long 0x1c 0. "  ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
else
hgroup.long 0x300++0x1F
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
endif
tree.end
tree "Interrupt Priority Registers"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
group.long 0x400++0x1F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
group.long 0x400++0x3F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
group.long 0x400++0x5F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
group.long 0x400++0x7F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
group.long 0x400++0x9F
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
group.long 0x400++0xBF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
group.long 0x400++0xDF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3   ,Interrupt 3   Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2   ,Interrupt 2   Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1   ,Interrupt 1   Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0   ,Interrupt 0   Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7   ,Interrupt 7   Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6   ,Interrupt 6   Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5   ,Interrupt 5   Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4   ,Interrupt 4   Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11  ,Interrupt 11  Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10  ,Interrupt 10  Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9   ,Interrupt 9   Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8   ,Interrupt 8   Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15  ,Interrupt 15  Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14  ,Interrupt 14  Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13  ,Interrupt 13  Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12  ,Interrupt 12  Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19  ,Interrupt 19  Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18  ,Interrupt 18  Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17  ,Interrupt 17  Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16  ,Interrupt 16  Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23  ,Interrupt 23  Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22  ,Interrupt 22  Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21  ,Interrupt 21  Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20  ,Interrupt 20  Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27  ,Interrupt 27  Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26  ,Interrupt 26  Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25  ,Interrupt 25  Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24  ,Interrupt 24  Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31  ,Interrupt 31  Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30  ,Interrupt 30  Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29  ,Interrupt 29  Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28  ,Interrupt 28  Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35  ,Interrupt 35  Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34  ,Interrupt 34  Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33  ,Interrupt 33  Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32  ,Interrupt 32  Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39  ,Interrupt 39  Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38  ,Interrupt 38  Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37  ,Interrupt 37  Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36  ,Interrupt 36  Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43  ,Interrupt 43  Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42  ,Interrupt 42  Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41  ,Interrupt 41  Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40  ,Interrupt 40  Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47  ,Interrupt 47  Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46  ,Interrupt 46  Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45  ,Interrupt 45  Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44  ,Interrupt 44  Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51  ,Interrupt 51  Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50  ,Interrupt 50  Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49  ,Interrupt 49  Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48  ,Interrupt 48  Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55  ,Interrupt 55  Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54  ,Interrupt 54  Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53  ,Interrupt 53  Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52  ,Interrupt 52  Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59  ,Interrupt 59  Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58  ,Interrupt 58  Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57  ,Interrupt 57  Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56  ,Interrupt 56  Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63  ,Interrupt 63  Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62  ,Interrupt 62  Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61  ,Interrupt 61  Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60  ,Interrupt 60  Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67  ,Interrupt 67  Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66  ,Interrupt 66  Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65  ,Interrupt 65  Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64  ,Interrupt 64  Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71  ,Interrupt 71  Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70  ,Interrupt 70  Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69  ,Interrupt 69  Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68  ,Interrupt 68  Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75  ,Interrupt 75  Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74  ,Interrupt 74  Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73  ,Interrupt 73  Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72  ,Interrupt 72  Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79  ,Interrupt 79  Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78  ,Interrupt 78  Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77  ,Interrupt 77  Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76  ,Interrupt 76  Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83  ,Interrupt 83  Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82  ,Interrupt 82  Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81  ,Interrupt 81  Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80  ,Interrupt 80  Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87  ,Interrupt 87  Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86  ,Interrupt 86  Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85  ,Interrupt 85  Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84  ,Interrupt 84  Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91  ,Interrupt 91  Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90  ,Interrupt 90  Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89  ,Interrupt 89  Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88  ,Interrupt 88  Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95  ,Interrupt 95  Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94  ,Interrupt 94  Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93  ,Interrupt 93  Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92  ,Interrupt 92  Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99  ,Interrupt 99  Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98  ,Interrupt 98  Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97  ,Interrupt 97  Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96  ,Interrupt 96  Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
group.long 0x400++0xEF
line.long 0x0 "IPR0,Interrupt Priority Register"
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
hexmask.long.byte 0x0 16.--23. 1. "  PRI_2 ,Interrupt 2 Priority"
hexmask.long.byte 0x0 8.--15. 1. "  PRI_1 ,Interrupt 1 Priority"
hexmask.long.byte 0x0 0.--7. 1. "  PRI_0 ,Interrupt 0 Priority"
line.long 0x4 "IPR1,Interrupt Priority Register"
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
hexmask.long.byte 0x4 16.--23. 1. "  PRI_6 ,Interrupt 6 Priority"
hexmask.long.byte 0x4 8.--15. 1. "  PRI_5 ,Interrupt 5 Priority"
hexmask.long.byte 0x4 0.--7. 1. "  PRI_4 ,Interrupt 4 Priority"
line.long 0x8 "IPR2,Interrupt Priority Register"
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
hexmask.long.byte 0x8 16.--23. 1. "  PRI_10 ,Interrupt 10 Priority"
hexmask.long.byte 0x8 8.--15. 1. "  PRI_9 ,Interrupt 9 Priority"
hexmask.long.byte 0x8 0.--7. 1. "  PRI_8 ,Interrupt 8 Priority"
line.long 0xC "IPR3,Interrupt Priority Register"
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
hexmask.long.byte 0xC 16.--23. 1. "  PRI_14 ,Interrupt 14 Priority"
hexmask.long.byte 0xC 8.--15. 1. "  PRI_13 ,Interrupt 13 Priority"
hexmask.long.byte 0xC 0.--7. 1. "  PRI_12 ,Interrupt 12 Priority"
line.long 0x10 "IPR4,Interrupt Priority Register"
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
hexmask.long.byte 0x10 16.--23. 1. "  PRI_18 ,Interrupt 18 Priority"
hexmask.long.byte 0x10 8.--15. 1. "  PRI_17 ,Interrupt 17 Priority"
hexmask.long.byte 0x10 0.--7. 1. "  PRI_16 ,Interrupt 16 Priority"
line.long 0x14 "IPR5,Interrupt Priority Register"
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
hexmask.long.byte 0x14 16.--23. 1. "  PRI_22 ,Interrupt 22 Priority"
hexmask.long.byte 0x14 8.--15. 1. "  PRI_21 ,Interrupt 21 Priority"
hexmask.long.byte 0x14 0.--7. 1. "  PRI_20 ,Interrupt 20 Priority"
line.long 0x18 "IPR6,Interrupt Priority Register"
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
hexmask.long.byte 0x18 16.--23. 1. "  PRI_26 ,Interrupt 26 Priority"
hexmask.long.byte 0x18 8.--15. 1. "  PRI_25 ,Interrupt 25 Priority"
hexmask.long.byte 0x18 0.--7. 1. "  PRI_24 ,Interrupt 24 Priority"
line.long 0x1C "IPR7,Interrupt Priority Register"
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
hexmask.long.byte 0x1C 16.--23. 1. "  PRI_30 ,Interrupt 30 Priority"
hexmask.long.byte 0x1C 8.--15. 1. "  PRI_29 ,Interrupt 29 Priority"
hexmask.long.byte 0x1C 0.--7. 1. "  PRI_28 ,Interrupt 28 Priority"
line.long 0x20 "IPR8,Interrupt Priority Register"
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
hexmask.long.byte 0x20 16.--23. 1. "  PRI_34 ,Interrupt 34 Priority"
hexmask.long.byte 0x20 8.--15. 1. "  PRI_33 ,Interrupt 33 Priority"
hexmask.long.byte 0x20 0.--7. 1. "  PRI_32 ,Interrupt 32 Priority"
line.long 0x24 "IPR9,Interrupt Priority Register"
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
hexmask.long.byte 0x24 16.--23. 1. "  PRI_38 ,Interrupt 38 Priority"
hexmask.long.byte 0x24 8.--15. 1. "  PRI_37 ,Interrupt 37 Priority"
hexmask.long.byte 0x24 0.--7. 1. "  PRI_36 ,Interrupt 36 Priority"
line.long 0x28 "IPR10,Interrupt Priority Register"
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
hexmask.long.byte 0x28 16.--23. 1. "  PRI_42 ,Interrupt 42 Priority"
hexmask.long.byte 0x28 8.--15. 1. "  PRI_41 ,Interrupt 41 Priority"
hexmask.long.byte 0x28 0.--7. 1. "  PRI_40 ,Interrupt 40 Priority"
line.long 0x2C "IPR11,Interrupt Priority Register"
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
hexmask.long.byte 0x2C 16.--23. 1. "  PRI_46 ,Interrupt 46 Priority"
hexmask.long.byte 0x2C 8.--15. 1. "  PRI_45 ,Interrupt 45 Priority"
hexmask.long.byte 0x2C 0.--7. 1. "  PRI_44 ,Interrupt 44 Priority"
line.long 0x30 "IPR12,Interrupt Priority Register"
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
hexmask.long.byte 0x30 16.--23. 1. "  PRI_50 ,Interrupt 50 Priority"
hexmask.long.byte 0x30 8.--15. 1. "  PRI_49 ,Interrupt 49 Priority"
hexmask.long.byte 0x30 0.--7. 1. "  PRI_48 ,Interrupt 48 Priority"
line.long 0x34 "IPR13,Interrupt Priority Register"
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
hexmask.long.byte 0x34 16.--23. 1. "  PRI_54 ,Interrupt 54 Priority"
hexmask.long.byte 0x34 8.--15. 1. "  PRI_53 ,Interrupt 53 Priority"
hexmask.long.byte 0x34 0.--7. 1. "  PRI_52 ,Interrupt 52 Priority"
line.long 0x38 "IPR14,Interrupt Priority Register"
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
hexmask.long.byte 0x38 16.--23. 1. "  PRI_58 ,Interrupt 58 Priority"
hexmask.long.byte 0x38 8.--15. 1. "  PRI_57 ,Interrupt 57 Priority"
hexmask.long.byte 0x38 0.--7. 1. "  PRI_56 ,Interrupt 56 Priority"
line.long 0x3C "IPR15,Interrupt Priority Register"
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
hexmask.long.byte 0x3C 16.--23. 1. "  PRI_62 ,Interrupt 62 Priority"
hexmask.long.byte 0x3C 8.--15. 1. "  PRI_61 ,Interrupt 61 Priority"
hexmask.long.byte 0x3C 0.--7. 1. "  PRI_60 ,Interrupt 60 Priority"
line.long 0x40 "IPR16,Interrupt Priority Register"
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
hexmask.long.byte 0x40 16.--23. 1. "  PRI_66 ,Interrupt 66 Priority"
hexmask.long.byte 0x40 8.--15. 1. "  PRI_65 ,Interrupt 65 Priority"
hexmask.long.byte 0x40 0.--7. 1. "  PRI_64 ,Interrupt 64 Priority"
line.long 0x44 "IPR17,Interrupt Priority Register"
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
hexmask.long.byte 0x44 16.--23. 1. "  PRI_70 ,Interrupt 70 Priority"
hexmask.long.byte 0x44 8.--15. 1. "  PRI_69 ,Interrupt 69 Priority"
hexmask.long.byte 0x44 0.--7. 1. "  PRI_68 ,Interrupt 68 Priority"
line.long 0x48 "IPR18,Interrupt Priority Register"
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
hexmask.long.byte 0x48 16.--23. 1. "  PRI_74 ,Interrupt 74 Priority"
hexmask.long.byte 0x48 8.--15. 1. "  PRI_73 ,Interrupt 73 Priority"
hexmask.long.byte 0x48 0.--7. 1. "  PRI_72 ,Interrupt 72 Priority"
line.long 0x4C "IPR19,Interrupt Priority Register"
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
hexmask.long.byte 0x4C 16.--23. 1. "  PRI_78 ,Interrupt 78 Priority"
hexmask.long.byte 0x4C 8.--15. 1. "  PRI_77 ,Interrupt 77 Priority"
hexmask.long.byte 0x4C 0.--7. 1. "  PRI_76 ,Interrupt 76 Priority"
line.long 0x50 "IPR20,Interrupt Priority Register"
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
hexmask.long.byte 0x50 16.--23. 1. "  PRI_82 ,Interrupt 82 Priority"
hexmask.long.byte 0x50 8.--15. 1. "  PRI_81 ,Interrupt 81 Priority"
hexmask.long.byte 0x50 0.--7. 1. "  PRI_80 ,Interrupt 80 Priority"
line.long 0x54 "IPR21,Interrupt Priority Register"
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
hexmask.long.byte 0x54 16.--23. 1. "  PRI_86 ,Interrupt 86 Priority"
hexmask.long.byte 0x54 8.--15. 1. "  PRI_85 ,Interrupt 85 Priority"
hexmask.long.byte 0x54 0.--7. 1. "  PRI_84 ,Interrupt 84 Priority"
line.long 0x58 "IPR22,Interrupt Priority Register"
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
hexmask.long.byte 0x58 16.--23. 1. "  PRI_90 ,Interrupt 90 Priority"
hexmask.long.byte 0x58 8.--15. 1. "  PRI_89 ,Interrupt 89 Priority"
hexmask.long.byte 0x58 0.--7. 1. "  PRI_88 ,Interrupt 88 Priority"
line.long 0x5C "IPR23,Interrupt Priority Register"
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
hexmask.long.byte 0x5C 16.--23. 1. "  PRI_94 ,Interrupt 94 Priority"
hexmask.long.byte 0x5C 8.--15. 1. "  PRI_93 ,Interrupt 93 Priority"
hexmask.long.byte 0x5C 0.--7. 1. "  PRI_92 ,Interrupt 92 Priority"
line.long 0x60 "IPR24,Interrupt Priority Register"
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
hexmask.long.byte 0x60 16.--23. 1. "  PRI_98 ,Interrupt 98 Priority"
hexmask.long.byte 0x60 8.--15. 1. "  PRI_97 ,Interrupt 97 Priority"
hexmask.long.byte 0x60 0.--7. 1. "  PRI_96 ,Interrupt 96 Priority"
line.long 0x64 "IPR25,Interrupt Priority Register"
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
hexmask.long.byte 0x64 16.--23. 1. "  PRI_102 ,Interrupt 102 Priority"
hexmask.long.byte 0x64 8.--15. 1. "  PRI_101 ,Interrupt 101 Priority"
hexmask.long.byte 0x64 0.--7. 1. "  PRI_100 ,Interrupt 100 Priority"
line.long 0x68 "IPR26,Interrupt Priority Register"
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
hexmask.long.byte 0x68 16.--23. 1. "  PRI_106 ,Interrupt 106 Priority"
hexmask.long.byte 0x68 8.--15. 1. "  PRI_105 ,Interrupt 105 Priority"
hexmask.long.byte 0x68 0.--7. 1. "  PRI_104 ,Interrupt 104 Priority"
line.long 0x6C "IPR27,Interrupt Priority Register"
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
hexmask.long.byte 0x6C 16.--23. 1. "  PRI_110 ,Interrupt 110 Priority"
hexmask.long.byte 0x6C 8.--15. 1. "  PRI_109 ,Interrupt 109 Priority"
hexmask.long.byte 0x6C 0.--7. 1. "  PRI_108 ,Interrupt 108 Priority"
line.long 0x70 "IPR28,Interrupt Priority Register"
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
hexmask.long.byte 0x70 16.--23. 1. "  PRI_114 ,Interrupt 114 Priority"
hexmask.long.byte 0x70 8.--15. 1. "  PRI_113 ,Interrupt 113 Priority"
hexmask.long.byte 0x70 0.--7. 1. "  PRI_112 ,Interrupt 112 Priority"
line.long 0x74 "IPR29,Interrupt Priority Register"
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
hexmask.long.byte 0x74 16.--23. 1. "  PRI_118 ,Interrupt 118 Priority"
hexmask.long.byte 0x74 8.--15. 1. "  PRI_117 ,Interrupt 117 Priority"
hexmask.long.byte 0x74 0.--7. 1. "  PRI_116 ,Interrupt 116 Priority"
line.long 0x78 "IPR30,Interrupt Priority Register"
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
hexmask.long.byte 0x78 16.--23. 1. "  PRI_122 ,Interrupt 122 Priority"
hexmask.long.byte 0x78 8.--15. 1. "  PRI_121 ,Interrupt 121 Priority"
hexmask.long.byte 0x78 0.--7. 1. "  PRI_120 ,Interrupt 120 Priority"
line.long 0x7C "IPR31,Interrupt Priority Register"
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
hexmask.long.byte 0x7C 16.--23. 1. "  PRI_126 ,Interrupt 126 Priority"
hexmask.long.byte 0x7C 8.--15. 1. "  PRI_125 ,Interrupt 125 Priority"
hexmask.long.byte 0x7C 0.--7. 1. "  PRI_124 ,Interrupt 124 Priority"
line.long 0x80 "IPR32,Interrupt Priority Register"
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
hexmask.long.byte 0x80 16.--23. 1. "  PRI_130 ,Interrupt 130 Priority"
hexmask.long.byte 0x80 8.--15. 1. "  PRI_129 ,Interrupt 129 Priority"
hexmask.long.byte 0x80 0.--7. 1. "  PRI_128 ,Interrupt 128 Priority"
line.long 0x84 "IPR33,Interrupt Priority Register"
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
hexmask.long.byte 0x84 16.--23. 1. "  PRI_134 ,Interrupt 134 Priority"
hexmask.long.byte 0x84 8.--15. 1. "  PRI_133 ,Interrupt 133 Priority"
hexmask.long.byte 0x84 0.--7. 1. "  PRI_132 ,Interrupt 132 Priority"
line.long 0x88 "IPR34,Interrupt Priority Register"
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
hexmask.long.byte 0x88 16.--23. 1. "  PRI_138 ,Interrupt 138 Priority"
hexmask.long.byte 0x88 8.--15. 1. "  PRI_137 ,Interrupt 137 Priority"
hexmask.long.byte 0x88 0.--7. 1. "  PRI_136 ,Interrupt 136 Priority"
line.long 0x8C "IPR35,Interrupt Priority Register"
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
hexmask.long.byte 0x8C 16.--23. 1. "  PRI_142 ,Interrupt 142 Priority"
hexmask.long.byte 0x8C 8.--15. 1. "  PRI_141 ,Interrupt 141 Priority"
hexmask.long.byte 0x8C 0.--7. 1. "  PRI_140 ,Interrupt 140 Priority"
line.long 0x90 "IPR36,Interrupt Priority Register"
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
hexmask.long.byte 0x90 16.--23. 1. "  PRI_146 ,Interrupt 146 Priority"
hexmask.long.byte 0x90 8.--15. 1. "  PRI_145 ,Interrupt 145 Priority"
hexmask.long.byte 0x90 0.--7. 1. "  PRI_144 ,Interrupt 144 Priority"
line.long 0x94 "IPR37,Interrupt Priority Register"
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
hexmask.long.byte 0x94 16.--23. 1. "  PRI_150 ,Interrupt 150 Priority"
hexmask.long.byte 0x94 8.--15. 1. "  PRI_149 ,Interrupt 149 Priority"
hexmask.long.byte 0x94 0.--7. 1. "  PRI_148 ,Interrupt 148 Priority"
line.long 0x98 "IPR38,Interrupt Priority Register"
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
hexmask.long.byte 0x98 16.--23. 1. "  PRI_154 ,Interrupt 154 Priority"
hexmask.long.byte 0x98 8.--15. 1. "  PRI_153 ,Interrupt 153 Priority"
hexmask.long.byte 0x98 0.--7. 1. "  PRI_152 ,Interrupt 152 Priority"
line.long 0x9C "IPR39,Interrupt Priority Register"
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
hexmask.long.byte 0x9C 16.--23. 1. "  PRI_158 ,Interrupt 158 Priority"
hexmask.long.byte 0x9C 8.--15. 1. "  PRI_157 ,Interrupt 157 Priority"
hexmask.long.byte 0x9C 0.--7. 1. "  PRI_156 ,Interrupt 156 Priority"
line.long 0xA0 "IPR40,Interrupt Priority Register"
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
hexmask.long.byte 0xA0 16.--23. 1. "  PRI_162 ,Interrupt 162 Priority"
hexmask.long.byte 0xA0 8.--15. 1. "  PRI_161 ,Interrupt 161 Priority"
hexmask.long.byte 0xA0 0.--7. 1. "  PRI_160 ,Interrupt 160 Priority"
line.long 0xA4 "IPR41,Interrupt Priority Register"
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
hexmask.long.byte 0xA4 16.--23. 1. "  PRI_166 ,Interrupt 166 Priority"
hexmask.long.byte 0xA4 8.--15. 1. "  PRI_165 ,Interrupt 165 Priority"
hexmask.long.byte 0xA4 0.--7. 1. "  PRI_164 ,Interrupt 164 Priority"
line.long 0xA8 "IPR42,Interrupt Priority Register"
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
hexmask.long.byte 0xA8 16.--23. 1. "  PRI_170 ,Interrupt 170 Priority"
hexmask.long.byte 0xA8 8.--15. 1. "  PRI_169 ,Interrupt 169 Priority"
hexmask.long.byte 0xA8 0.--7. 1. "  PRI_168 ,Interrupt 168 Priority"
line.long 0xAC "IPR43,Interrupt Priority Register"
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
hexmask.long.byte 0xAC 16.--23. 1. "  PRI_174 ,Interrupt 174 Priority"
hexmask.long.byte 0xAC 8.--15. 1. "  PRI_173 ,Interrupt 173 Priority"
hexmask.long.byte 0xAC 0.--7. 1. "  PRI_172 ,Interrupt 172 Priority"
line.long 0xB0 "IPR44,Interrupt Priority Register"
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
hexmask.long.byte 0xB0 16.--23. 1. "  PRI_178 ,Interrupt 178 Priority"
hexmask.long.byte 0xB0 8.--15. 1. "  PRI_177 ,Interrupt 177 Priority"
hexmask.long.byte 0xB0 0.--7. 1. "  PRI_176 ,Interrupt 176 Priority"
line.long 0xB4 "IPR45,Interrupt Priority Register"
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
hexmask.long.byte 0xB4 16.--23. 1. "  PRI_182 ,Interrupt 182 Priority"
hexmask.long.byte 0xB4 8.--15. 1. "  PRI_181 ,Interrupt 181 Priority"
hexmask.long.byte 0xB4 0.--7. 1. "  PRI_180 ,Interrupt 180 Priority"
line.long 0xB8 "IPR46,Interrupt Priority Register"
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
hexmask.long.byte 0xB8 16.--23. 1. "  PRI_186 ,Interrupt 186 Priority"
hexmask.long.byte 0xB8 8.--15. 1. "  PRI_185 ,Interrupt 185 Priority"
hexmask.long.byte 0xB8 0.--7. 1. "  PRI_184 ,Interrupt 184 Priority"
line.long 0xBC "IPR47,Interrupt Priority Register"
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
hexmask.long.byte 0xBC 16.--23. 1. "  PRI_190 ,Interrupt 190 Priority"
hexmask.long.byte 0xBC 8.--15. 1. "  PRI_189 ,Interrupt 189 Priority"
hexmask.long.byte 0xBC 0.--7. 1. "  PRI_188 ,Interrupt 188 Priority"
line.long 0xC0 "IPR48,Interrupt Priority Register"
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
hexmask.long.byte 0xC0 16.--23. 1. "  PRI_194 ,Interrupt 194 Priority"
hexmask.long.byte 0xC0 8.--15. 1. "  PRI_193 ,Interrupt 193 Priority"
hexmask.long.byte 0xC0 0.--7. 1. "  PRI_192 ,Interrupt 192 Priority"
line.long 0xC4 "IPR49,Interrupt Priority Register"
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
hexmask.long.byte 0xC4 16.--23. 1. "  PRI_198 ,Interrupt 198 Priority"
hexmask.long.byte 0xC4 8.--15. 1. "  PRI_197 ,Interrupt 197 Priority"
hexmask.long.byte 0xC4 0.--7. 1. "  PRI_196 ,Interrupt 196 Priority"
line.long 0xC8 "IPR50,Interrupt Priority Register"
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
hexmask.long.byte 0xC8 16.--23. 1. "  PRI_202 ,Interrupt 202 Priority"
hexmask.long.byte 0xC8 8.--15. 1. "  PRI_201 ,Interrupt 201 Priority"
hexmask.long.byte 0xC8 0.--7. 1. "  PRI_200 ,Interrupt 200 Priority"
line.long 0xCC "IPR51,Interrupt Priority Register"
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
hexmask.long.byte 0xCC 16.--23. 1. "  PRI_206 ,Interrupt 206 Priority"
hexmask.long.byte 0xCC 8.--15. 1. "  PRI_205 ,Interrupt 205 Priority"
hexmask.long.byte 0xCC 0.--7. 1. "  PRI_204 ,Interrupt 204 Priority"
line.long 0xD0 "IPR52,Interrupt Priority Register"
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
hexmask.long.byte 0xD0 16.--23. 1. "  PRI_210 ,Interrupt 210 Priority"
hexmask.long.byte 0xD0 8.--15. 1. "  PRI_209 ,Interrupt 209 Priority"
hexmask.long.byte 0xD0 0.--7. 1. "  PRI_208 ,Interrupt 208 Priority"
line.long 0xD4 "IPR53,Interrupt Priority Register"
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
hexmask.long.byte 0xD4 16.--23. 1. "  PRI_214 ,Interrupt 214 Priority"
hexmask.long.byte 0xD4 8.--15. 1. "  PRI_213 ,Interrupt 213 Priority"
hexmask.long.byte 0xD4 0.--7. 1. "  PRI_212 ,Interrupt 212 Priority"
line.long 0xD8 "IPR54,Interrupt Priority Register"
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
hexmask.long.byte 0xD8 16.--23. 1. "  PRI_218 ,Interrupt 218 Priority"
hexmask.long.byte 0xD8 8.--15. 1. "  PRI_217 ,Interrupt 217 Priority"
hexmask.long.byte 0xD8 0.--7. 1. "  PRI_216 ,Interrupt 216 Priority"
line.long 0xDC "IPR55,Interrupt Priority Register"
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
hexmask.long.byte 0xDC 16.--23. 1. "  PRI_222 ,Interrupt 222 Priority"
hexmask.long.byte 0xDC 8.--15. 1. "  PRI_221 ,Interrupt 221 Priority"
hexmask.long.byte 0xDC 0.--7. 1. "  PRI_220 ,Interrupt 220 Priority"
line.long 0xE0 "IPR56,Interrupt Priority Register"
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
hexmask.long.byte 0xE0 16.--23. 1. "  PRI_226 ,Interrupt 226 Priority"
hexmask.long.byte 0xE0 8.--15. 1. "  PRI_225 ,Interrupt 225 Priority"
hexmask.long.byte 0xE0 0.--7. 1. "  PRI_224 ,Interrupt 224 Priority"
line.long 0xE4 "IPR57,Interrupt Priority Register"
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
hexmask.long.byte 0xE4 16.--23. 1. "  PRI_230 ,Interrupt 230 Priority"
hexmask.long.byte 0xE4 8.--15. 1. "  PRI_229 ,Interrupt 229 Priority"
hexmask.long.byte 0xE4 0.--7. 1. "  PRI_228 ,Interrupt 228 Priority"
line.long 0xE8 "IPR58,Interrupt Priority Register"
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
hexmask.long.byte 0xE8 16.--23. 1. "  PRI_234 ,Interrupt 234 Priority"
hexmask.long.byte 0xE8 8.--15. 1. "  PRI_233 ,Interrupt 233 Priority"
hexmask.long.byte 0xE8 0.--7. 1. "  PRI_232 ,Interrupt 232 Priority"
line.long 0xEC "IPR59,Interrupt Priority Register"
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
hexmask.long.byte 0xEC 16.--23. 1. "  PRI_238 ,Interrupt 238 Priority"
hexmask.long.byte 0xEC 8.--15. 1. "  PRI_237 ,Interrupt 237 Priority"
hexmask.long.byte 0xEC 0.--7. 1. "  PRI_236 ,Interrupt 236 Priority"
else
hgroup.long 0x400++0xEF
hide.long 0x0 "IPR0,Interrupt Priority Register"
hide.long 0x4 "IPR1,Interrupt Priority Register"
hide.long 0x8 "IPR2,Interrupt Priority Register"
hide.long 0xC "IPR3,Interrupt Priority Register"
hide.long 0x10 "IPR4,Interrupt Priority Register"
hide.long 0x14 "IPR5,Interrupt Priority Register"
hide.long 0x18 "IPR6,Interrupt Priority Register"
hide.long 0x1C "IPR7,Interrupt Priority Register"
hide.long 0x20 "IPR8,Interrupt Priority Register"
hide.long 0x24 "IPR9,Interrupt Priority Register"
hide.long 0x28 "IPR10,Interrupt Priority Register"
hide.long 0x2C "IPR11,Interrupt Priority Register"
hide.long 0x30 "IPR12,Interrupt Priority Register"
hide.long 0x34 "IPR13,Interrupt Priority Register"
hide.long 0x38 "IPR14,Interrupt Priority Register"
hide.long 0x3C "IPR15,Interrupt Priority Register"
hide.long 0x40 "IPR16,Interrupt Priority Register"
hide.long 0x44 "IPR17,Interrupt Priority Register"
hide.long 0x48 "IPR18,Interrupt Priority Register"
hide.long 0x4C "IPR19,Interrupt Priority Register"
hide.long 0x50 "IPR20,Interrupt Priority Register"
hide.long 0x54 "IPR21,Interrupt Priority Register"
hide.long 0x58 "IPR22,Interrupt Priority Register"
hide.long 0x5C "IPR23,Interrupt Priority Register"
hide.long 0x60 "IPR24,Interrupt Priority Register"
hide.long 0x64 "IPR25,Interrupt Priority Register"
hide.long 0x68 "IPR26,Interrupt Priority Register"
hide.long 0x6C "IPR27,Interrupt Priority Register"
hide.long 0x70 "IPR28,Interrupt Priority Register"
hide.long 0x74 "IPR29,Interrupt Priority Register"
hide.long 0x78 "IPR30,Interrupt Priority Register"
hide.long 0x7C "IPR31,Interrupt Priority Register"
hide.long 0x80 "IPR32,Interrupt Priority Register"
hide.long 0x84 "IPR33,Interrupt Priority Register"
hide.long 0x88 "IPR34,Interrupt Priority Register"
hide.long 0x8C "IPR35,Interrupt Priority Register"
hide.long 0x90 "IPR36,Interrupt Priority Register"
hide.long 0x94 "IPR37,Interrupt Priority Register"
hide.long 0x98 "IPR38,Interrupt Priority Register"
hide.long 0x9C "IPR39,Interrupt Priority Register"
hide.long 0xA0 "IPR40,Interrupt Priority Register"
hide.long 0xA4 "IPR41,Interrupt Priority Register"
hide.long 0xA8 "IPR42,Interrupt Priority Register"
hide.long 0xAC "IPR43,Interrupt Priority Register"
hide.long 0xB0 "IPR44,Interrupt Priority Register"
hide.long 0xB4 "IPR45,Interrupt Priority Register"
hide.long 0xB8 "IPR46,Interrupt Priority Register"
hide.long 0xBC "IPR47,Interrupt Priority Register"
hide.long 0xC0 "IPR48,Interrupt Priority Register"
hide.long 0xC4 "IPR49,Interrupt Priority Register"
hide.long 0xC8 "IPR50,Interrupt Priority Register"
hide.long 0xCC "IPR51,Interrupt Priority Register"
hide.long 0xD0 "IPR52,Interrupt Priority Register"
hide.long 0xD4 "IPR53,Interrupt Priority Register"
hide.long 0xD8 "IPR54,Interrupt Priority Register"
hide.long 0xDC "IPR55,Interrupt Priority Register"
hide.long 0xE0 "IPR56,Interrupt Priority Register"
hide.long 0xE4 "IPR57,Interrupt Priority Register"
hide.long 0xE8 "IPR58,Interrupt Priority Register"
hide.long 0xEC "IPR59,Interrupt Priority Register"
endif
tree.end
width 0x0b
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
sif CORENAME()=="CORTEXM4F"
tree "Floating-point Unit (FPU)"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 8.
group.long 0xF34++0x0B
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
bitfld.long 0x00 31. " ASPEN        ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
bitfld.long 0x00 30. "                      LSPEN    ,Enables lazy context save of FP state" "Disabled,Enabled"
bitfld.long 0x00 8. "       MONRDY  ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 6. " BFRDY        ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
bitfld.long 0x00 5. "                      MMRDY    ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
bitfld.long 0x00 4. "       HFRDY   ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
textline "                 "
bitfld.long 0x00 3. " THREAD       ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
bitfld.long 0x00 1. "                       USER     ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
bitfld.long 0x00 0. "   LSPACT  ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
hexmask.long 0x04 3.--31. 0x8 " ADDRESS      ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
bitfld.long 0x08 26. " AHP          ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
bitfld.long 0x08 25. "                 DN       ,Default value for FPSCR.DN" "NaN operands,Any operation"
bitfld.long 0x08 24. "  FZ      ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
textline "                 "
bitfld.long 0x08 22.--23. " RMODE        ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
rgroup.long 0xF40++0x07
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
bitfld.long 0x00 28.--31. " FPRNDMOD     ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
bitfld.long 0x00 24.--27. "                 SRTERR   ,Indicates the hardware support for FP short vectors" "Not supported,?..."
bitfld.long 0x00 20.--23. "  SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " DIV          ,Indicates the hardware support for FP divide operations" ",Supported,?..."
bitfld.long 0x00 12.--15. "                     FPEXTRP  ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
bitfld.long 0x00 8.--11. "  DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SNGLPREC     ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
bitfld.long 0x00 0.--3. "                     A_SIMD   ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
bitfld.long 0x04 24.--27. "                     FP_HPFP  ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
textline "                 "
bitfld.long 0x04 4.--7. " D_NAN        ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
bitfld.long 0x04 0.--3. "               FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
width 0xB
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
endif
tree "Debug"
tree "Core Debug"
sif COMPonent.AVAILABLE("COREDEBUG")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
width 7.
group.long 0xD30++0x03
line.long 0x00 "DFSR,Debug Fault Status Register"
eventfld.long 0x00 4. " EXTERNAL     ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
eventfld.long 0x00 3. "  VCATCH     ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
eventfld.long 0x00 2. "  DWTTRAP    ,Indicates a debug event generated by the DWT" "Not generated,Generated"
newline
eventfld.long 0x00 1. " BKPT         ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
eventfld.long 0x00 0. "  HALTED     ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
newline
hgroup.long 0xDF0++0x03
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
in
newline
wgroup.long 0xDF4++0x03
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
bitfld.long 0x00 16. " REGWNR       ,Register Read/Write" "Read,Write"
hexmask.long.byte 0x00 0.--6. 1. "          REGSEL     ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
group.long 0xDF8++0x03
line.long 0x00 "DCRDR,Debug Core Register Data Register"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
bitfld.long 0x00 18. "              MON_STEP   ,Setting this bit to 1 makes the step request pending" "No step,Step"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
else
group.long 0xDFC++0x03
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
bitfld.long 0x00 24. " TRCENA       ,Global enable for all DWT and ITM features" "Disabled,Enabled"
bitfld.long 0x00 19. "       MON_REQ    ,DebugMonitor semaphore bit" "0,1"
newline
bitfld.long 0x00 17. " MON_PEND     ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
bitfld.long 0x00 16. "    MON_EN     ,Enable the DebugMonitor exception" "Disabled,Enabled"
bitfld.long 0x00 10. "       VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 9. " VC_INTERR    ,Enable halting debug trap" "Disabled,Enabled"
bitfld.long 0x00 8. "       VC_BUSERR  ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
bitfld.long 0x00 7. "       VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
newline
bitfld.long 0x00 6. " VC_CHKERR    ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
bitfld.long 0x00 5. "       VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
bitfld.long 0x00 4. "       VC_MMERR   ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
newline
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
endif
width 0x0B
else
newline
textline "COREDEBUG component base address not specified"
newline
endif
tree.end
tree "Flash Patch and Breakpoint Unit (FPB)"
sif COMPonent.AVAILABLE("FPB")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
width 10.
group.long 0x00++0x07
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
bitfld.long 0x00 28.--31. " REV     ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
rbitfld.long 0x00 4.--7. 12.--14. "     NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
bitfld.long 0x00 1. "  KEY   ,Key Field" "Low,High"
bitfld.long 0x00 0. "      ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
textline ""
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
bitfld.long 0x04 29. " RMPSPT  ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
hexmask.long.tbyte 0x04 5.--28. 0x20 "               REMAP ,Remap Base Address Field"
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x8++0x03
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0xC++0x03
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x10++0x03
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x14++0x03
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x18++0x03
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x1C++0x03
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x20++0x03
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
hexmask.long 0x00 2.--28. 0x04 "  COMP  ,Comparison Address"
bitfld.long 0x00 0. "  ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
bitfld.long 0x00 0. " BE      ,Enable bit for Breakpoint" "Disabled,Enabled"
else
group.long 0x24++0x03
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
hexmask.long 0x00 1.--31. 0x02 " BPADDR  ,Breakpoint address"
bitfld.long 0x00 0. "                    BE    ,Enable bit for Breakpoint" "Disabled,Enabled"
endif
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0xB
else
newline
textline "FPB component base address not specified"
newline
endif
tree.end
tree "Data Watchpoint and Trace Unit (DWT)"
sif COMPonent.AVAILABLE("DWT")
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
width 15.
group.long 0x00++0x1B
line.long 0x00 "DWT_CTRL,Control Register"
rbitfld.long 0x00 28.--31. " NUMCOMP     ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rbitfld.long 0x00 27. "             NOTRCPKT   ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
rbitfld.long 0x00 26. "  NOEXTTRIG   ,Shows whether the implementation includes external match signals" "Supported,Not supported"
textline "                        "
rbitfld.long 0x00 25. " NOCYCCNT    ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
rbitfld.long 0x00 24. "  NOPRFCNT   ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
bitfld.long 0x00 22. "  CYCEVTENA   ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 21. " FOLDEVTENA  ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 20. "       LSUEVTENA  ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 19. "       SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 18. " EXCEVTENA   ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 17. "       CPIEVTENA  ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
bitfld.long 0x00 16. "       EXCTRCENA   ,Enables generation of exception trace" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
bitfld.long 0x00 10.--11. "       SYNCTAP    ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
bitfld.long 0x00 9. "     CYCTAP      ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
textline "                        "
bitfld.long 0x00 5.--8. " POSTINIT    ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 1.--4. "             POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0. "             CYCCNTENA   ,Enables CYCCNT" "Disabled,Enabled"
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
line.long 0x08 "DWT_CPICNT,CPI Count Register"
hexmask.long.byte 0x08 0.--7. 1. " CPICNT      ,The base CPI counter"
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT      ,The exception overhead counter"
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT    ,Sleep Counter"
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT      ,Load-store counter"
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT     ,Folded-instruction counter"
rgroup.long 0x1C++0x03
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
textline "                        "
group.long 0x20++0x07
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
else
group.long 0x28++0x03
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 7. " CYCMATCH    ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
bitfld.long 0x00 5. "    EMITRANGE  ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "       FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x30)++0x07
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x30+0x08)++0x03
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x40)++0x07
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x40+0x08)++0x03
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
group.long (0x50)++0x07
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
bitfld.long 0x04 0.--4. " MASK        ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
else
group.long (0x50+0x08)++0x03
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
bitfld.long 0x00 24. " MATCHED     ,Comparator match" "No matched,Matched"
bitfld.long 0x00 16.--19. "  DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12.--15. "             DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                        "
bitfld.long 0x00 10.--11. " DATAVSIZE   ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
bitfld.long 0x00 9. "    LNK1ENA    ,Supports use of a second linked comparator" "Not Supported,Supported"
bitfld.long 0x00 8. "  DATAVMATCH ,Data value compare" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " EMITRANGE   ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
bitfld.long 0x00 0.--3. "    FUNCTION   ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
endif
width 6.
tree "CoreSight Identification Registers"
rgroup.long 0xFE0++0x0F
line.long 0x00 "PID0,Peripheral ID0"
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
line.long 0x04 "PID1,Peripheral ID1"
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
hexmask.long.byte 0x04 0.--3. 1. "  Part_Num[11:8] ,Part Number bits[11:8]"
line.long 0x08 "PID2,Peripheral ID2"
hexmask.long.byte 0x08 4.--7. 1. " Revision      ,Revision"
bitfld.long 0x08 3. "  JEDEC          ,JEDEC assigned ID fields" "0,JEDEC"
hexmask.long.byte 0x08 0.--2. 1. "  JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
line.long 0x0c "PID3,Peripheral ID3"
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd        ,Minor revision field"
hexmask.long.byte 0x0C 0.--3. 1. "  CMB            ,Customer-modified block"
rgroup.long 0xFD0++0x03
line.long 0x00 "PID4,Peripheral Identification Register 4"
hexmask.long.byte 0x00 4.--7. 1. " Count         ,4KB count"
hexmask.long.byte 0x00 0.--3. 1. "  JEP106_CC      ,JEP106 continuation code"
rgroup.long 0xFF0++0x0F
line.long 0x00 "CID0,Component ID0 (Preamble)"
line.long 0x04 "CID1,Component ID1"
hexmask.long.byte 0x04 4.--7. 1. " CC            ,Component Class"
hexmask.long.byte 0x04 0.--3. 1. "  Preamble       ,Preamble"
line.long 0x08 "CID2,Component ID2"
line.long 0x0c "CID3,Component ID3"
tree.end
width 0x0B
else
newline
textline "DWT component base address not specified"
newline
endif
tree.end
tree.end
AUTOINDENT.POP
tree.end
elif (CORENAME()=="CORTEXR5F")
tree "Core Registers (Cortex-R5F)"
AUTOINDENT.PUSH
AUTOINDENT.OFF
width 0x8
; --------------------------------------------------------------------------------
;    Identification registers
; --------------------------------------------------------------------------------
tree "ID Registers"
rgroup.long c15:0x00++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL     ,Implementer code"
bitfld.long 0x0 20.--23.  "           VAR      ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19.  "           ARCH     ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7"
textline "                 "
hexmask.long.word 0x0 4.--15. 0x1 " PART     ,Primary Part Number"
bitfld.long 0x0 0.--3. "         REV      ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long c15:0x100++0x00
line.long 0x00 "CTR,Cache Type Register"
bitfld.long 0x00 24.--27. " CWG      ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline "                 "
bitfld.long 0x00 20.--23. " ERG      ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0 16.--19. "           DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
bitfld.long 0x0 14.--15. "  L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical"
textline "                 "
bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words"
rgroup.long c15:0x400--0x400
line.long 0x0 "MPUIR,MPU type register"
hexmask.long.byte 0x00 8.--15. 1. " REGNUM   ,Number of regions"
bitfld.long 0x00 0. "           TYPE     ,Type of MPU regions" "Unified,Seperated"
rgroup.long c15:0x500++0x00
line.long 0x0 "MPIDR,Multiprocessor Affinity Register"
bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system"
textline "                 "
hexmask.long.byte 0x00 16.--23. 1. " AFFL2    ,Affitnity Level 2"
hexmask.long.byte 0x00 8.--15. 1. "           AFFL1    ,Affitnity Level 1"
hexmask.long.byte 0x00 0.--7. 1. "           AFFL0    ,Affitnity Level 0"
textline "                 "
rgroup.long c15:0x0410++0x00
line.long 0x00 "MMFR0,Memory Model Feature Register 0"
bitfld.long 0x00 28.--31. " IT         ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      FCSE       ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " ACR        ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      TCM        ,TCM and Associated DMA Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SL         ,Number of Shareability levels implemented" "1,?..."
bitfld.long 0x00 8.--11. "              OS         ,Outermost Shareability domain support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " PMSA       ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  VMSA       ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0510++0x00
line.long 0x00 "MMFR1,Memory Model Feature Register 1"
bitfld.long 0x00 28.--31. " BTB        ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "   L1TCO      ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " L1UCMO     ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "  L1HCMO     ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " L1UCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "  L1HCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c15:0x0610++0x00
line.long 0x00 "MMFR2,Memory Model Feature Register 2"
bitfld.long 0x00 28.--31. " HAF        ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "  WFI        ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " MBF        ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      UTLBMO     ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " HTLBMO     ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      HL1CMRO    ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " HL1BPCRO   ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  HL1FPCRO   ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c15:0x0710++0x00
line.long 0x00 "MMFR3,Memory Model Feature Register 3"
bitfld.long 0x00 28.--31. " SS         ,Supersection support" "Supported,?..."
bitfld.long 0x00 20.--23. "      CW         ,Coherent walk" "Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " MB         ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " HCMOSW     ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      HCMOMVA    ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c15:0x020++0x00
line.long 0x00 "ISAR0,Instruction Set Attributes Register 0"
bitfld.long 0x00 24.--27. " DIVI       ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "  DEBI       ,Debug Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 16.--19. " CI         ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "  CBI        ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " BI         ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "      BCI        ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 0.--3. " SI         ,Swap Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x120++0x00
line.long 0x00 "ISAR1,Instruction Set Attributes Register 1"
bitfld.long 0x00 28.--31. " JI         ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      INTI       ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " IMMI       ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      ITEI       ,If Then Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " EXTI       ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      E2I        ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " E1I        ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      ENDI       ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x220++0x00
line.long 0x00 "ISAR2,Instruction Set Attributes Register 2"
bitfld.long 0x00 28.--31. " RI         ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      PSRI       ,PSR Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " UMI        ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      SMI        ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " MI         ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      II         ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " MHI        ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      LSI        ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x320++0x00
line.long 0x00 "ISAR3,Instruction Set Attributes Register 3"
bitfld.long 0x00 28.--31. " T2E        ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "      NOPI       ,True NOP Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " TCI        ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      TBI        ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SPI        ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      SVCI       ,SVC Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " SIMDI      ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      SI         ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c15:0x420++0x00
line.long 0x00 "ISAR4,Instruction Set Attributes Register 4"
bitfld.long 0x00 28.--31. " SWP_FRAC   ,SWAP_frac" "Supported,?..."
bitfld.long 0x00 24.--27. "      PSR_M_I    ,PSR_M Instructions Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 20.--23. " EI         ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "      BI         ,Barrier Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 12.--15. " SMII       ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "      WBI        ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 4.--7. " WSI        ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      UI         ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c15:0x0520++0x00
line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)"
rgroup.long c15:0x0620++0x00
line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)"
rgroup.long c15:0x0720++0x00
line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)"
rgroup.long c15:0x010++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "  STATE2 ,Java Extension Interface Support" "Not supported,?..."
bitfld.long 0x00 4.--7. "  STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
textline "                 "
bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c15:0x110++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM    ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. "  SE     ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "      PM     ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
textline "                 "
rgroup.long c15:0x210++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "  TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
bitfld.long 0x00 12.--15. "      TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
textline "                 "
bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "      SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "  CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c15:0x310++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c15:0x02f++0x00
line.long 0x00 "BO1R,Build Options 1 Register"
hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR    ,Default high address for the TCM"
bitfld.long 0x00 1. "                  FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented"
textline "                 "
bitfld.long 0x00 0. " PP_BUS_ECC          ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented"
group.long c15:0x12f++0x00
line.long 0x00 "BO2R,Build Options 2 Register"
bitfld.long 0x00 31. " NUM_CPU             ,Number of CPUs" "1,2"
bitfld.long 0x00 30. "                       LOCK_STEP       ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included"
textline "                 "
bitfld.long 0x00 29. " NO_ICACHE           ,Indicate whether the CPU contains instruction cache" "Yes,No"
bitfld.long 0x00 28. "                     NO_DCACHE       ,Indicate whether the CPU contains data cache" "Yes,No"
textline "                 "
bitfld.long 0x00 26.--27. " ATCM_ES             ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection"
bitfld.long 0x00 23.--25. "  BTCM_ES         ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..."
textline "                 "
bitfld.long 0x00 23. " NO_IE               ,Indicate whether the processor supports big-endian instructions" "Yes,No"
bitfld.long 0x00 22. "                     NO_FPU          ,Indicate whether the CPU contains a floating point unit" "Yes,No"
textline "                 "
bitfld.long 0x00 20.--21. " MPU_REGIONS         ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions"
bitfld.long 0x00 17.--19. "              BREAK_POINTS    ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
textline "                 "
bitfld.long 0x00 14.--16. " WATCH_POINTS        ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 13. "                       NO_A_TCM_INF    ,Indicate whether the CPUs contain ATCM ports" "Yes,No"
textline "                 "
bitfld.long 0x00 12. " NO_B0_TCM_INF       ,Indicate whether the CPUs contain B0TCM ports" "Yes,No"
bitfld.long 0x00 11. "                     NO_B1_TCM_INF   ,Indicate whether the CPUs contain B1TCM ports" "Yes,No"
textline "                 "
bitfld.long 0x00 10. " TCMBUSPARITY        ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes"
bitfld.long 0x00 9. "                     NO_SLAVE        ,Indicate whether the CPU contains an AXI slave port" "Yes,No"
textline "                 "
bitfld.long 0x00 7.--8. " ICACHE_ES           ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC"
bitfld.long 0x00 5.--6. "         DCACHE_ES       ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..."
textline "                 "
bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No"
bitfld.long 0x00 3. "                     AXI_BUS_ECC     ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes"
textline "                 "
bitfld.long 0x00 2. " SL                  ,Indicate whether the processor has been built with split/lock logic" "No,Yes"
bitfld.long 0x00 1. "                     AHB_PP          ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes"
textline "                 "
bitfld.long 0x00 0. " MICRO_SCU           ,Indicate whether the processor contain an ACP interface" "No,Yes"
group.long c15:0x72f++0x00
line.long 0x00 "POR,Pin Options Register"
bitfld.long 0x00 4. " DBGNOCLKSTOP        ,Value of the DBGNOCLKSTOP pin" "Low,High"
bitfld.long 0x00 3. "                    INTSYNCEN       ,Value of the INTSYNCEN pin" "Low,High"
textline "                 "
bitfld.long 0x00 2. " IRQADDRVSYNCEN      ,Value of the IRQADDRVSYNCEN pin" "Low,High"
bitfld.long 0x00 1. "                    SLBTCMSB        ,Value of the SLBTCMSBm pin" "Low,High"
textline "                 "
bitfld.long 0x00 0. " PARITYLEVEL         ,Value of the PARITYLEVEL pin" "Low,High"
tree.end
width 0x8
tree "System Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE  ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. "   TE  ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. "    AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. "  TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. "  NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 25. " EE  ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. "   VE  ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI  ,Fast Interrupts enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 19. " DZ  ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. "  BR  ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. "  RR  ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. "   V   ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline "                 "
bitfld.long 0x0 12. " I   ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. "  Z   ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. "  C   ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. "  A   ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. "  M   ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x101++0x00
line.long 0x0 "ACTLR,Auxiliary Control Register"
bitfld.long 0x00 31. " DICDI     ,Disable Case C dual issue control" "Enable,Disable"
bitfld.long 0x00 30. "    DIB2DI    ,Disable Case B2 dual issue control" "Enable,Disable"
bitfld.long 0x00 29. "    DIB1DI    ,Disable Case B1 dual issue control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 28. " DIADI     ,Disable Case A dual issue control" "Enable,Disable"
bitfld.long 0x00 27. "    B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 26. "    B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable"
textline "                 "
bitfld.long 0x00 25. " ATCMPCEN  ,B1TCM parity or ECC check enable" "Disable,Enable"
bitfld.long 0x00 24. "    AXISCEN   ,AXI slave cache access enable" "Disable,Enable"
bitfld.long 0x00 23. "    AXISCUEN  ,AXI slave cache User mode access enable" "Disable,Enable"
textline "                 "
bitfld.long 0x00 22. " DILSM     ,Disable LIL on load/store multiples" "Enable,Disable"
bitfld.long 0x00 21. "    DEOLP     ,Disable end of loop prediction" "Enable,Disable"
bitfld.long 0x00 20. "    DBHE      ,Disable BH extension" "Enable,Disable"
textline "                 "
bitfld.long 0x00 19. " FRCDIS    ,Fetch rate control disable" "Enable,Disable"
bitfld.long 0x00 17. "    RSDIS     ,Return stack disable" "Enable,Disable"
bitfld.long 0x00 15.--16. "    BP        ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..."
textline "                 "
bitfld.long 0x00 14. " DBWR      ,Disable write_burst on AXI master" "Enable,Disable"
bitfld.long 0x00 13. "    DLFO      ,Disable linefill optimization in the AXI master" "Enable,Disable"
bitfld.long 0x00 12. "    ERPEG     ,Enable random parity error generation" "Disable,Enable"
textline "                 "
bitfld.long 0x00 11. " DNCH      ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable"
bitfld.long 0x00 10. "    FORA      ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced"
bitfld.long 0x00 9. " FWT       ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced"
textline "                 "
bitfld.long 0x00 8. " FDSnS     ,Force D-side to not-shared when MPU is off" "Not forced,Forced"
bitfld.long 0x00 7. " SMOV      ,sMOV disabled" "Enabled,Disabled"
bitfld.long 0x0 6. "   DILS      ,Disable low interrupt latency on all load/store instructions" "Enable,Disable"
textline "                 "
bitfld.long 0x00 3.--5. " CEC       ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..."
textline "                 "
bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable"
bitfld.long 0x00 1. "    B0TCMECEN ,B0TCM external error enable" "Disable,Enable"
bitfld.long 0x00 0. "    ATCMECEN  ,ATCM external error enable" "Disable,Enable"
textline " "
group.long c15:0x0f++0x00
line.long 0x00 "SACTLR,Secondary Auxiliary Control Register"
bitfld.long 0x00 22. " DCHE      ,Disable hard-error support in the caches" "Enable,Disable"
bitfld.long 0x00 21. "    DR2B      ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable"
bitfld.long 0x00 20. "    DF6DI     ,F6 dual issue control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 19. " DF2DI     ,F2 dual issue control" "Enable,Disable"
bitfld.long 0x00 18. "    DDI       ,F1/F3/F4 dual issue control" "Enable,Disable"
bitfld.long 0x00 17. "    DOODPFP   ,Out-of-order Double Precision Floating-point control" "Enable,Disable"
textline "                 "
bitfld.long 0x00 16. " DOOFMACS  ,Out-of-order FMACS control" "Enable,Disable"
bitfld.long 0x00 13. "    IXC       ,Floating-point inexact exception output mask" "Mask,Propagate"
bitfld.long 0x00 12. "  OFC       ,Floating-point overflow exception output mask" "Mask,Propagate"
textline "                 "
bitfld.long 0x00 11. " UFC       ,Floating-point underflow exception output mask" "Mask,Propagate"
bitfld.long 0x00 10. "  IOC       ,Floating-point invalid operation exception output mask" "Mask,Propagate"
bitfld.long 0x00 9. "  DZC       ,Floating-point divide-by-zero exception output mask" "Mask,Propagate"
textline "                 "
bitfld.long 0x00 8. " IDC       ,Floating-point input denormal exception output mask" "Mask,Propagate"
bitfld.long 0x00 3. "  BTCMECC   ,Correction for internal ECC logic on BTCM ports" "Enable,Disable"
bitfld.long 0x00 2. "    ATCMECC   ,Correction for internal ECC logic on ATCM port" "Enable,Disable"
textline "                 "
bitfld.long 0x00 1. " BTCMRMW   ,Enable 64-bit stores on BTCMs" "Disable,Enable"
bitfld.long 0x00 0. "    ATCMRMW   ,Enable 64-bit stores on ATCM" "Disable,Enable"
textline " "
group.long c15:0x201++0x00
line.long 0x0 "CPACR,Coprocessor Access Control Register"
bitfld.long 0x0 31. " ASEDIS    ,Disable Advanced SIMD Extension functionality" "No,Yes"
bitfld.long 0x0 30. "        D32DIS    ,Disable use of D16-D31 of the VFP register file" "No,Yes"
textline "                 "
bitfld.long 0x0 26.--27. " CP13      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 24.--25. " CP12      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 22.--23. " CP11      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 20.--21. " CP10      ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 18.--19. " CP9       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 16.--17. " CP8       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 14.--15. " CP7       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 12.--13. " CP6       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 10.--11. " CP5       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 8.--9. " CP4       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 6.--7. " CP3       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 4.--5. " CP2       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                 "
bitfld.long 0x0 2.--3. " CP1       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
bitfld.long 0x0 0.--1. " CP0       ,Coprocesor access control" "Denied,Privileged,Reserved,Full"
textline "                      "
group.long c15:0x000b++0x00
line.long 0x00 "SPCR,Slave Port Control Register"
bitfld.long 0x00 1. " PRIV    ,Privilege access only" "User/Privilege,Privilege only"
bitfld.long 0x00 0. "  AXISLEN ,AXI slave port disable" "Enabled,Disabled"
tree.end
width 0x8
tree "MPU Control and Configuration"
group.long c15:0x01++0x00
line.long 0x00 "SCTLR,Control Register"
bitfld.long 0x0 31. " IE  ,Instruction endianness" "Little,Big"
bitfld.long 0x0 30. "   TE  ,Thumb exception enable" "ARM,Thumb"
bitfld.long 0x0 29. "    AFE ,Access Flag Enable" "Disable,Enable"
bitfld.long 0x0 28. "  TRE ,TEX remap enable" "Disable,Enable"
bitfld.long 0x0 27. "  NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 25. " EE  ,Exception endianess" "Little,Big"
bitfld.long 0x0 24. "   VE  ,Vector Enable" "Disable,Vectored"
bitfld.long 0x0 21. " FI  ,Fast Interrupts enable" "Disable,Enable"
textline "                 "
bitfld.long 0x0 19. " DZ  ,Divide by Zero exception bit" "Disable,Enable"
bitfld.long 0x0 17. "  BR  ,MPU Background region enable" "Disable,Enable"
bitfld.long 0x0 14. "  RR  ,Round-Robin bit" "Random,RRobin"
bitfld.long 0x0 13. "   V   ,Base Location of Exception Registers" "0x00000000,0xFFFF0000"
textline "                 "
bitfld.long 0x0 12. " I   ,Instruction Cache Enable" "Disable,Enable"
bitfld.long 0x0 11. "  Z   ,Branch Prediction Enable" "Disable,Enable"
bitfld.long 0x0 2. "  C   ,Enable data cache" "Disable,Enable"
bitfld.long 0x0 1. "  A   ,Strict Alignment" "Disable,Enable"
bitfld.long 0x0 0. "  M   ,MPU Enable" "Disable,Enable"
textline " "
group.long c15:0x05++0x00
line.long 0x00 "DFSR,Data Fault Status Register"
bitfld.long 0x00 12. " EXT      ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 11. "            RW       ,Access Caused an Abort Type" "Read,Write"
textline "                 "
bitfld.long 0x00 4.--7. " DOMAIN   ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15"
bitfld.long 0x00 0.--3. 10.  "               STATUS   ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x15++0x00
line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. "                SIDE     ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline "                 "
bitfld.long 0x00 21. " REC_ERR  ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. "   SIDE_EXT ,Source of the error" "Internal,External"
textline "                 "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,Index Value for The Access Giving the Error Register"
group.long c15:0x06++0x00
line.long 0x00 "DFAR,Data Fault Address Register"
textline " "
group.long c15:0x0105++0x00
line.long 0x00 "IFSR,Instruction Fault Status Register"
bitfld.long 0x00 12. " EXT      ,External Abort Qualifier" "DECERR,SLVERR"
bitfld.long 0x00 0.--3. 10. "            STATUS   ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..."
group.long c15:0x115++0x00
line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register"
bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 22.--23. 20. "                SIDE     ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved"
textline "                 "
bitfld.long 0x00 21. " REC_ERR  ,Error recoverability indication" "Not recoverable,Recoverable"
bitfld.long 0x00 20. "   SIDE_EXT ,Source of the error" "Internal,External"
textline "                 "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,Index Value for The Access Giving the Error Register"
group.long c15:0x206++0x00
line.long 0x00 "IFAR,Instruction Fault Address Register"
textline " "
group.long c15:0x0016++0x00
line.long 0x00 "RBAR,Region Base Address Register"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group.long c15:0x0216++0x00
line.long 0x00 "RSER,Region Size and Enable Register"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group.long c15:0x0416++0x00
line.long 0x00 "RACR,Region Access Control Register"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " TYPE  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
group.long c15:0x0026++0x00
line.long 0x00 "MRNR,Memory Region Number Register"
bitfld.long 0x00 0.--3. " REGION  ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
textline " "
group.long c15:0x010d++0x00
line.long 0x00 "CIDR,Context ID Register"
group.long c15:0x20d++0x00
line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register"
group.long c15:0x30d++0x00
line.long 0x00 "TIDRURO,User read only Thread and Process ID Register"
group.long c15:0x40d++0x00
line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register"
width 0x08
tree "MPU regions"
group c15:0x0016++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RBAR0,Region Base Address Register 0"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RSER0,Region Size and Enable Register 0"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x0
line.long 0x00 "RACR0,Region Access Control Register 0"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RBAR1,Region Base Address Register 1"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RSER1,Region Size and Enable Register 1"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x1
line.long 0x00 "RACR1,Region Access Control Register 1"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RBAR2,Region Base Address Register 2"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RSER2,Region Size and Enable Register 2"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x2
line.long 0x00 "RACR2,Region Access Control Register 2"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RBAR3,Region Base Address Register 3"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RSER3,Region Size and Enable Register 3"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x3
line.long 0x00 "RACR3,Region Access Control Register 3"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RBAR4,Region Base Address Register 4"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RSER4,Region Size and Enable Register 4"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x4
line.long 0x00 "RACR4,Region Access Control Register 4"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RBAR5,Region Base Address Register 5"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RSER5,Region Size and Enable Register 5"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x5
line.long 0x00 "RACR5,Region Access Control Register 5"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RBAR6,Region Base Address Register 6"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RSER6,Region Size and Enable Register 6"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x6
line.long 0x00 "RACR6,Region Access Control Register 6"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RBAR7,Region Base Address Register 7"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RSER7,Region Size and Enable Register 7"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x7
line.long 0x00 "RACR7,Region Access Control Register 7"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RBAR8,Region Base Address Register 8"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RSER8,Region Size and Enable Register 8"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x8
line.long 0x00 "RACR8,Region Access Control Register 8"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RBAR9,Region Base Address Register 9"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RSER9,Region Size and Enable Register 9"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0x9
line.long 0x00 "RACR9,Region Access Control Register 9"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RBAR10,Region Base Address Register 10"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RSER10,Region Size and Enable Register 10"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xA
line.long 0x00 "RACR10,Region Access Control Register 10"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RBAR11,Region Base Address Register 11"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RSER11,Region Size and Enable Register 11"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xB
line.long 0x00 "RACR11,Region Access Control Register 11"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RBAR12,Region Base Address Register 12"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RSER12,Region Size and Enable Register 12"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xC
line.long 0x00 "RACR12,Region Access Control Register 12"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RBAR13,Region Base Address Register 13"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RSER13,Region Size and Enable Register 13"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xD
line.long 0x00 "RACR13,Region Access Control Register 13"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RBAR14,Region Base Address Register 14"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RSER14,Region Size and Enable Register 14"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xE
line.long 0x00 "RACR14,Region Access Control Register 14"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
group c15:0x0016++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RBAR15,Region Base Address Register 15"
hexmask.long 0x00 5.--31. 0x20 " BA      ,Base address"
group c15:0x0216++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RSER15,Region Size and Enable Register 15"
bitfld.long 0x00 15. " SD      ,Subregion 7 disable" "-,D"
bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D"
bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D"
bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D"
bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D"
bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D"
bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D"
bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D"
bitfld.long 0x00 1.--5. "   RS      ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
bitfld.long 0x00 0. "   EN    ,Enable" "Disabled,Enabled"
group c15:0x0416++0x00
saveout c15:0x26 %l 0xF
line.long 0x00 "RACR15,Region Access Control Register 15"
bitfld.long 0x00 12. " XN      ,Execute never" "-,NoExec"
bitfld.long 0x00 2. "  S  ,Share" "No,Yes"
bitfld.long 0x00 8.--10. "    AP      ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved"
bitfld.long 0x00 0.--1. 3.--5. " type  ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate"
textline " "
tree.end
tree.end
width 0x9
tree "TCM Control and Configuration"
rgroup.long c15:0x200++0x00
line.long 0x00 "TCMTR,TCM Type Register"
bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "         ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7"
group.long c15:0x019++0x00
line.long 0x00 "BTCMRR,BTCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address (physical address)"
bitfld.long 0x00 2.--6. "  SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Enable instruction TCM" "Disabled,Enabled"
group.long c15:0x119++0x00
line.long 0x00 "ATCMRR,ATCM Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address (physical address)"
bitfld.long 0x00 2.--6. "  SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Enable instruction TCM" "Disabled,Enabled"
rgroup.long c15:0x29++0x00
line.long 0x00 "TCMSEL,TCM Selection Register"
textline " "
group.long c15:0x10f++0x00
line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x20f++0x00
line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
group.long c15:0x30f++0x00
line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register"
hexmask.long 0x00 12.--31. 0x1000 " BA   ,Base address of the interface"
bitfld.long 0x00 2.--6. "  SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..."
bitfld.long 0x00 0. "  EN ,Interface enable" "Disabled,Enabled"
tree.end
width 0xC
tree "Cache Control and Configuration"
rgroup.long c15:0x1100++0x00
line.long 0x00 "CLIDR,Cache Level ID Register"
bitfld.long 0x00 27.--29. " LOU      ,Level of Unification" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 24.--26. "  LOC       ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8"
textline "                     "
bitfld.long 0x00 21.--23. " CL8      ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 18.--20. "  CL7       ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 15.--17. " CL6      ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 12.--14. "  CL5       ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 9.--11. " CL4      ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--8. "  CL3       ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7"
textline "                     "
bitfld.long 0x00 3.--5. " CL2      ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--2. "  CL1       ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7"
rgroup.long c15:0x1700++0x00
line.long 0x00 "AIDR,Auxiliary ID Register"
rgroup.long c15:0x1000++0x00
line.long 0x00 "CCSIDR,Cache Size ID Register"
bitfld.long 0x00 31. " WT       ,Write-Through" "Not supported,Supported"
bitfld.long 0x00 30. "  WB     ,Write-Back" "Not supported,Supported"
textline "                     "
bitfld.long 0x00 29. " RA       ,Read-Allocate" "Not supported,Supported"
bitfld.long 0x00 28. "  WA     ,Write-Allocate" "Not supported,Supported"
textline "                     "
hexmask.long.word 0x00 13.--27. 1. " NUMSETS  ,Number of sets"
hexmask.long.word 0x00 3.--12. 1. "           ASSOCIATIVITY ,Associativity"
textline "                     "
bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7"
group.long c15:0x2000++0x00
line.long 0x0 "CSSELR,Cache Size Selection Register"
bitfld.long 0x00 1.--3. " LEVEL    ,Cache level to select" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0. "              IND    ,Instruction or data or unified cache to use" "Data/unified,Instruction"
group.long c15:0x03f++0x00
line.long 0x00 "CFLR,Correctable Fault Location Register"
bitfld.long 0x00 26.--29. " WAY      ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--25. "             SIDE   ,Source of the error" "0,1,2,3"
textline "                     "
hexmask.long.word 0x00 5.--13. 1. " INDEX    ,index of the location where the error occurred"
bitfld.long 0x00 0.--1. "           TYPE   ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP"
group.long c15:0x5f++0x00
line.long 0x00 "IADCR,Invalidate All Data Cache Register"
bitfld.long 0x00 30.--31. " WAY      ,Cache way to invalidate or clean" "0,1,2,3"
hexmask.long.byte 0x00 5.--10. 1. "              SET    ,Cache set to invalidate or clean"
group.long c15:0xef++0x00
line.long 0x00 "CSOR,Cache Size Override Register"
bitfld.long 0x00 4.--7. " Dcache   ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
bitfld.long 0x00 0.--3. "       Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB"
tree.end
width 12.
tree "System Performance Monitor"
group.long c15:0xc9++0x00
line.long 0x00 "PMCR,Performance Monitor Control Register"
hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code"
hexmask.long.byte 0x00 16.--23. 1. "           IDCODE ,Identification code"
bitfld.long 0x00 11.--15. "           N  ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 5. "           DP ,Disable PMCCNTR when prohibited" "No,Yes"
textline "                     "
bitfld.long 0x00 4. " X   ,Export enable" "Disabled,Enabled"
bitfld.long 0x00 3. "     D      ,Clock divider" "Every cycle,64th cycle"
bitfld.long 0x00 2. "  C  ,Clock counter reset" "No action,Reset"
bitfld.long 0x00 1. "    P  ,Event counter reset" "No action,Reset"
textline "                     "
bitfld.long 0x00 0. " E   ,Enable" "Disabled,Enabled"
group.long c15:0x1c9++0x00
line.long 0x00 "PMCNTENSET,Count Enable Set Register"
eventfld.long 0x00 31. " C   ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,PMN2 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,PMN1 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,PMN0 Enabled / Enable / Disable  counter" "Disabled,Enabled"
group.long c15:0x2c9++0x00
line.long 0x0 "PMCNTENCLR,Count Enable Clear Register"
eventfld.long 0x00 31. " C   ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,PMN2 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,PMN1 Enabled / Enable / Disable  counter" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,PMN0 Enabled / Enable / Disable  counter" "Disabled,Enabled"
group.long c15:0x3c9++0x00
line.long 0x0 "PMOVSR,Overflow Flag Status Register"
eventfld.long 0x00 31. " C   ,CCNT overflowed" "No overflow,Overflow"
eventfld.long 0x00  2. "  P2     ,PMN2 overflowed" "No overflow,Overflow"
eventfld.long 0x00  1. "  P1 ,PMN1 overflowed" "No overflow,Overflow"
eventfld.long 0x00  0. "  P0 ,PMN0 overflowed" "No overflow,Overflow"
group.long c15:0x4c9++0x00
line.long 0x0 "PMSWINC,Software Increment Register"
eventfld.long 0x00  2. " P2  ,Increment  PMN2" "No action,Increment"
eventfld.long 0x00  1. "    P1     ,Increment  PMN1" "No action,Increment"
eventfld.long 0x00  0. "    P0 ,Increment  PMN0" "No action,Increment"
group.long c15:0x01d9++0x00
line.long 0x00 "PMXEVTYPER,Event Type Selection Register"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected"
group.long c15:0x02d9++0x00
line.long 0x00 "PMXEVCNTR,Event Count Register"
group.long c15:0x5c9++0x00
line.long 0x00 "PMSELR,Performance Counter Selection Register"
bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..."
group.long c15:0xd9++0x00
line.long 0x00 "PMCCNTR,Cycle Count Register"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "ESR0,Event Selection Register 0"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x0
line.long 0x00 "PMCR0,Performance Monitor Count Register 0"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "ESR1,Event Selection Register 1"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x1
line.long 0x00 "PMCR1,Performance Monitor Count Register 1"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0x01d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "ESR2,Event Selection Register 2"
hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection"
group.long c15:0x02d9++0x00
saveout c15:0x5C9 %l 0x2
line.long 0x00 "PMCR2,Performance Monitor Count Register 2"
hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count"
group.long c15:0xe9++0x00
line.long 0x00 "PMUSERENR,User Enable Register"
bitfld.long 0x00  0. " EN  ,User mode access to performance monitor and validation registers" "Not allowed,Allowed"
group.long c15:0x1e9++0x00
line.long 0x00 "PMINTENSET,Interrupt Enable Set Register"
eventfld.long 0x00 31. " C   ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,Interrupt on PMN2 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
group.long c15:0x2e9++0x00
line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register"
eventfld.long 0x00 31. " C   ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled"
eventfld.long 0x00  2. "     P2     ,Interrupt on PMN2 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  1. "     P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
eventfld.long 0x00  0. "     P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable  Interrupt" "Disabled,Enabled"
tree "Validation Registers"
group.long c15:0x01f++0x00
line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x11f++0x00
line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x21f++0x00
line.long 0x00 "RESR,nVAL Reset Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow reset request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x31f++0x00
line.long 0x00 "RESR,VAL Debug Request Enable Set Register"
bitfld.long 0x00 31. " C  ,CCNT overflow debug request" "Not requested,Requested"
bitfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
bitfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
group.long c15:0x41f++0x00
line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested"
group.long c15:0x51f++0x00
line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested"
group.long c15:0x61f++0x00
line.long 0x00 "RECR,nVAL Reset Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow reset request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested"
group.long c15:0x71f++0x00
line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register"
eventfld.long 0x00 31. " C  ,CCNT overflow debug request" "Not requested,Requested"
eventfld.long 0x00 2. "  P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 1. "  P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested"
eventfld.long 0x00 0. "  P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested"
tree.end
tree.end
width 11.
width 18.
tree "Debug Registers"
tree "Processor Identifier Registers"
rgroup.long c14:832.++0x00
line.long 0x00 "MIDR,Main ID Register"
hexmask.long.byte 0x0 24.--31. 0x1 " IMPL       ,Implementer code"
hexmask.long.byte 0x0 20.--23. 0x1 "               SPECREV    ,Variant number"
textline "                           "
hexmask.long.byte 0x0 16.--19. 0x1 " ARCH       ,Architecture"
hexmask.long.word 0x0 4.--15. 0x1 "               PARTNUM    ,Part Number"
textline "                           "
hexmask.long.byte 0x0 0.--3. 0x1 " REV        ,Layout Revision"
rgroup.long c14:833.++0x00
line.long 0x00 "CACHETYPE,Cache Type Register"
bitfld.long 0x00 16.--19. " DMINLINE   ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
bitfld.long 0x00 14.--15. "  L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " IMINLINE   ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..."
rgroup.long c14:834.++0x00
line.long 0x00 "TCMTR,TCM Type Register"
group.long c14:835.++0x00
line.long 0x00 "AMIDR,Alias of MIDR"
rgroup.long c14:836.++0x00
line.long 0x00 "MPUTR,MPU Type Register"
rgroup.long c14:837.++0x00
line.long 0x00 "MPIDR,Multiprocessor Affinity Register"
group.long c14:838.++0x00
line.long 0x00 "AMIDR0,Alias of MIDR"
group.long c14:839.++0x00
line.long 0x00 "AMIDR1,Alias of MIDR"
rgroup.long c14:840.++0x00
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
bitfld.long 0x00 12.--15. " STATE3     ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        STATE2     ,Java Extension Interface Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " STATE1     ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        STATE0     ,ARM Instruction Set Support" "Reserved,Supported,?..."
rgroup.long c14:841.++0x00
line.long 0x00 "ID_PFR1,Processor Feature Register 1"
bitfld.long 0x00 8.--11. " MPM        ,Microcontroller Programmer's Model Support" "Supported,?..."
bitfld.long 0x00 4.--7. "        SE         ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " PM         ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..."
rgroup.long c14:842.++0x00
line.long 0x00 "ID_DFR0,Debug Feature Register 0"
bitfld.long 0x00 20.--23. " MDM_MM     ,Microcontroller Debug Model Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "    TDM_MM     ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " TDM_CB     ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    CDM_MM     ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " SDM_CB     ,Secure Debug Model (Coprocessor) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    CDM_CB     ,Coprocessor Debug Model Support" "Not supported,?..."
rgroup.long c14:843.++0x00
line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
rgroup.long c14:844.++0x00
line.long 0x00 "ID_MMFR0,Processor Feature Register 0"
bitfld.long 0x00 28.--31. " IT         ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        FCSE       ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " ACR        ,Auxiliary Control Register Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        TCM        ,TCM and Associated DMA Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " CC_PLEA    ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    CC_CPUA    ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " PMSA       ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    VMSA       ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..."
rgroup.long c14:845.++0x00
line.long 0x00 "ID_MMFR1,Processor Feature Register 1"
bitfld.long 0x00 28.--31. " BTB        ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..."
bitfld.long 0x00 24.--27. "     L1TCO      ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " L1UCMO     ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 16.--19. "    L1HCMO     ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " L1UCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 8.--11. "    L1HCLMOSW  ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..."
rgroup.long c14:846.++0x00
line.long 0x00 "ID_MMFR2,Processor Feature Register 2"
bitfld.long 0x00 28.--31. " HAF        ,Hardware Access Flag Support" "Not supported,?..."
bitfld.long 0x00 24.--27. "    WFI        ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " MBF        ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        UTLBMO     ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " HTLBMO     ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        HL1CMRO    ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " HL1BPCRO   ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
bitfld.long 0x00 0.--3. "    HL1FPCRO   ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..."
rgroup.long c14:847.++0x00
line.long 0x00 "ID_MMFR3,Processor Feature Register 3"
bitfld.long 0x00 4.--7. " HCMOSW     ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        HCMOMVA    ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..."
rgroup.long c14:848.++0x00
line.long 0x00 "ID_ISAR0,ISA Feature Register 0"
bitfld.long 0x00 24.--27. " DIVI       ,Divide Instructions Support" "Not supported,?..."
bitfld.long 0x00 20.--23. "    DEBI       ,Debug Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 16.--19. " CI         ,Coprocessor Instructions Support" "Not supported,?..."
bitfld.long 0x00 12.--15. "    CBI        ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 8.--11. " BI         ,Bitfield Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 4.--7. "        BCI        ,Bit Counting Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 0.--3. " AI         ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:849.++0x00
line.long 0x00 "ID_ISAR1,ISA Feature Register 1"
bitfld.long 0x00 28.--31. " JI         ,Jazelle Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        INTI       ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " IMMI       ,Immediate Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        ITEI       ,If Then Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " EXTI       ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        E2I        ,Exception 2 Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " E1I        ,Exception 1 Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        ENDI       ,Endianness Control Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:850.++0x00
line.long 0x00 "ID_ISAR2,ISA Feature Register 2"
bitfld.long 0x00 28.--31. " RI         ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        PSRI       ,PSR Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " UMI        ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        SMI        ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " MI         ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        II         ,Multi-Access Interruptible Instructions Support" "Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " MHI        ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        LSI        ,Load and Store Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:851.++0x00
line.long 0x00 "ID_ISAR3,ISA Feature Register 3"
bitfld.long 0x00 28.--31. " T2E        ,Thumb-2 Extensions Support" "Reserved,Supported,?..."
bitfld.long 0x00 24.--27. "        NOPI       ,True NOP Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 20.--23. " TCI        ,Thumb Copy Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        TBI        ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " SPI        ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        SWII       ,SWI Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " SIMDI      ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        SI         ,Saturate Instructions Support" "Reserved,Supported,?..."
rgroup.long c14:852.++0x00
line.long 0x00 "ID_ISAR4,ISA Feature Register 4"
bitfld.long 0x00 20.--23. " EI         ,Exclusive Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 16.--19. "        BI         ,Barrier Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 12.--15. " SMII       ,SMI Instructions Support" "Reserved,Supported,?..."
bitfld.long 0x00 8.--11. "        WBI        ,Write-Back Instructions Support" "Reserved,Supported,?..."
textline "                           "
bitfld.long 0x00 4.--7. " WSI        ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..."
bitfld.long 0x00 0.--3. "        UI         ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..."
rgroup.long c14:853.++0x00
line.long 0x00 "ID_ISAR5,ISA Feature Register 5"
tree.end
width 15.
tree "Coresight Management Registers"
group.long c14:960.++0x00
line.long 0x00 "DBGITCTRL,Integration Mode Control Register"
bitfld.long 0x00 0. " INTMODE      ,Processor integration mode" "Normal,Integration"
group.long c14:1000.++0x00
line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register"
hexmask.long.byte 0x00 0.--7. 1. " CTS          ,Claim tag set"
group.long c14:1001.++0x00
line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register"
hexmask.long.byte 0x00 0.--7. 1. " CTC          ,Claim tag clear"
wgroup.long c14:1004.++0x00
line.long 0x00 "DBGLAR,Lock Access Register"
rgroup.long c14:1005.++0x00
line.long 0x00 "DBGLSR,Lock Status Register"
bitfld.long 0x00 2. " 32BA         ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes"
textline "                        "
bitfld.long 0x00 1. " LB           ,Lock bit" "Not locked,Locked"
bitfld.long 0x00 0. "              LIB          ,Lock implemented bit" "Not locked,Locked"
rgroup.long c14:1006.++0x00
line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register"
bitfld.long 0x00 7. " SNDFI        ,Secure non-invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 6. "         SNDFE        ,Secure non-invasive debug features enable" "Disabled,Enabled"
textline "                        "
bitfld.long 0x00 5. " SIDFI        ,Secure invasive debug features implemented" "Not implemented,Implemented"
bitfld.long 0x00 4. "         SIDFE        ,Secure invasive debug features enabled" "Disabled,Enabled"
rgroup.long c14:1011.++0x00
line.long 0x00 "DBGDEVTYPE,Device Type Register"
hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE      ,Subtype"
hexmask.long.byte 0x00 0.--3. 1. "                      MAIN_CLASS   ,Main class"
tree.end
textline "                     "
width 12.
rgroup.long c14:0.++0x0
line.long 0x0 "DBGDIDR,Debug ID Register"
bitfld.long 0x0 28.--31. " WRP          ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
bitfld.long 0x0 24.--27. "                       BRP          ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..."
textline "                     "
bitfld.long 0x0 20.--23. " CTX_CMP      ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
hexmask.long.byte 0x0 16.--19. 1. "                      VERSION      ,Debug Architecture Version"
textline "                     "
bitfld.long 0x0 15. " DEVID        ,Debug Device ID" "Low,High"
bitfld.long 0x0 14. "                    NSUHD        ,Secure User halting debug-mode" "Low,High"
textline "                     "
bitfld.long 0x0 13. " PCSR         ,PC Sample register implemented" "Low,High"
bitfld.long 0x0 12. "                    SE           ,Security Extensions implemented" "Low,High"
textline "                     "
hexmask.long.byte 0x0 4.--7. 1. " VARIANT      ,Implementation-defined Variant Number"
hexmask.long.byte 0x0 0.--3. 1. "                      REVISION     ,Implementation-defined Revision Number"
group.long c14:34.++0x0
line.long 0x00 "DBGDSCREXT,Debug Status and Control Register"
bitfld.long 0x00 30. " RXFULL       ,DBGDTRRX Register full" "Empty,Full"
bitfld.long 0x00 29. "                   TXFULL       ,DBGDTRTX Register full" "Empty,Full"
textline "                     "
bitfld.long 0x00 25. " PIPEADV      ,PIPEADV Processor Idle flag" "Not idle,Idle"
bitfld.long 0x00 24. "                INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed"
textline "                     "
bitfld.long 0x00 20.--21. " EXTDCCMODE   ,External DCC access mode field" "Non-blocking,Stall,Fast,?..."
bitfld.long 0x00 19. "            ADADISCARD   ,Asynchronous Data Aborts Discarded bit" "Normal,Abort"
bitfld.long 0x00 18. "         NS      ,Non-secure status bit" "Secure,Non-secure"
textline "                     "
bitfld.long 0x00 17. " SPNIDDIS     ,Secure Privileged Non-Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 16. "                     SPIDDIS      ,Secure Privileged Invasive Debug Disable" "No,Yes"
bitfld.long 0x00 15. "            MDBGEN  ,Monitor debug-mode enable" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 14. " HDBGEN       ,Halting debug-mode" "Disabled,Enabled"
bitfld.long 0x00 13. "                ITREN        ,Execute ARM instruction enable" "Disabled,Enabled"
bitfld.long 0x00 12. "       UDCCDIS ,User mode access to Communications Channel disable" "No,Yes"
textline "                     "
bitfld.long 0x00 11. " INTDIS       ,Interrupt disable" "No,Yes"
bitfld.long 0x00 10. "                     DBGACK       ,Force debug acknowledge" "Normal,Forced"
textline "                     "
bitfld.long 0x00 8. " UND_L        ,Sticky undefined bit" "Not occurred,Occurred"
bitfld.long 0x00 7. "            ADABORT      ,Asynchronous data abort" "Not aborted,Aborted"
bitfld.long 0x00 6. "    SDABORT ,Synchronous data abort" "Not aborted,Aborted"
textline "                     "
bitfld.long 0x00 2.--5. " MOE          ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..."
bitfld.long 0x00 1. "  RESTARTED    ,Processor restarted" "Pending,Exited"
bitfld.long 0x00 0. "        HALTED  ,Processor halted" "Non-debug,Debug"
group.long c14:0x7++0x0
line.long 0x00 "DBGVCR,Debug Vector Catch register"
bitfld.long 0x00 7. " FIQVCE_S     ,FIQ vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 6. " IRQVCE_S     ,IRQ vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 4. "                DAVCE_S      ,Data Abort vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 3. " PAVCE_S      ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 2. "                SVCVCE_S     ,SVC vector catch in Secure state" "Disabled,Enabled"
textline "                     "
bitfld.long 0x00 1. " UIVCE_S      ,Undefined instruction vector catch in Secure state" "Disabled,Enabled"
bitfld.long 0x00 0. "                RVCE         ,Reset vector catch enable" "Disabled,Enabled"
hgroup.long c14:32.++0x0
hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register"
in
group.long c14:35.++0x00
line.long 0x0 "DTRTX,Host -> Target Data Transfer Register"
hexmask.long 0x00 0.--31. 1. " HTD          ,Host -> target data"
group.long c14:10.++0x0
line.long 0x00 "DBGDSCCR,Debug State Cache Control Register"
bitfld.long 0x00 2. " NWT          ,Write through disable" "No,Yes"
bitfld.long 0x00 1. "                     NIL          ,L1 instruction cache line-fills disable" "No,Yes"
textline "                     "
bitfld.long 0x00 0. " NDL          ,L1 data cache line-fills disable" "No,Yes"
wgroup.long c14:33.++0x0
line.long 0x00 "DBGITR,Instruction Transfer Register"
wgroup.long c14:36.++0x0
line.long 0x00 "DBGDRCR,Debug Run Control Register"
bitfld.long 0x00 4. " CMR          ,Cancel memory requests" "Not cancel,Cancel"
bitfld.long 0x00 3. "              CSPA         ,Clear Sticky Pipeline Advance bit" "No effect,Clear"
textline "                     "
bitfld.long 0x00 2. " CSE          ,Clear Sticky Exceptions bits" "No effect,Clear"
bitfld.long 0x00 1. "               RR           ,Restart request" "No effect,Restart"
textline "                     "
bitfld.long 0x00 0. " HR           ,Halt request" "No effect,Halt"
textline "                     "
rgroup.long c14:193.++0x0
line.long 0x00 "DBGOSLSR,Operating System Lock Status Register"
bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented"
group.long c14:196.++0x0
line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register"
bitfld.long 0x00 2. " HCWR         ,Hold core warm reset" "Not held,Held"
textline "                     "
bitfld.long 0x00 1. " CWRR         ,Reset reguest" "Not requested,Requested"
bitfld.long 0x00 0. "    CORENPDRQ ,Core no powerdown request" "Power-down,Emulate"
rgroup.long c14:197.++0x0
line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register"
bitfld.long 0x00 3. " SR           ,Sticky Reset Status" "Not reset,Reset"
bitfld.long 0x00 2. "        R         ,Reset Status" "No reset,Reset"
textline "                     "
bitfld.long 0x00 1. " SPD          ,Sticky Power-down Status" "Not reset,Reset"
bitfld.long 0x00 0. "        PU        ,Power-up Status" "Powered down,Powered up"
tree.end
width 7.
tree "Breakpoint Registers"
group.long c14:64.++0x0
line.long 0x00 "BVR0,Breakpoint Value 0 Register"
hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0"
group.long c14:80.++0x0
line.long 0x00 "BCR0,Breakpoint Control 0 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:65.++0x0
line.long 0x00 "BVR1,Breakpoint Value 1 Register"
hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1"
group.long c14:81.++0x0
line.long 0x00 "BCR1,Breakpoint Control 1 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:66.++0x0
line.long 0x00 "BVR2,Breakpoint Value 2 Register"
hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2"
group.long c14:82.++0x0
line.long 0x00 "BCR2,Breakpoint Control 2 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:67.++0x0
line.long 0x00 "BVR3,Breakpoint Value 3 Register"
hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3"
group.long c14:83.++0x0
line.long 0x00 "BCR3,Breakpoint Control 3 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:68.++0x0
line.long 0x00 "BVR4,Breakpoint Value 4 Register"
hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4"
group.long c14:84.++0x0
line.long 0x00 "BCR4,Breakpoint Control 4 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:69.++0x0
line.long 0x00 "BVR5,Breakpoint Value 5 Register"
hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5"
group.long c14:85.++0x0
line.long 0x00 "BCR5,Breakpoint Control 5 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:70.++0x0
line.long 0x00 "BVR6,Breakpoint Value 6 Register"
hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6"
group.long c14:86.++0x0
line.long 0x00 "BCR6,Breakpoint Control 6 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
group.long c14:71.++0x0
line.long 0x00 "BVR7,Breakpoint Value 7 Register"
hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7"
group.long c14:87.++0x0
line.long 0x00 "BCR7,Breakpoint Control 7 Register"
bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x00 20.--22. "  M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..."
bitfld.long 0x00 16.--19. "     LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x00 14.--15. "     SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..."
textline "                "
bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
bitfld.long 0x00 1.--2. "        S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any"
bitfld.long 0x00 0. "  B    ,Breakpoint Enable" "Disabled,Enabled"
tree.end
tree "Watchpoint Control Registers"
group.long c14:96.++0x0
line.long 0x00 "WVR0,Watchpoint Value 0 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:112.++0x0
line.long 0x00 "WCR0,Watchpoint Control 0 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:97.++0x0
line.long 0x00 "WVR1,Watchpoint Value 1 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:113.++0x0
line.long 0x00 "WCR1,Watchpoint Control 1 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:98.++0x0
line.long 0x00 "WVR2,Watchpoint Value 2 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:114.++0x0
line.long 0x00 "WCR2,Watchpoint Control 2 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:99.++0x0
line.long 0x00 "WVR3,Watchpoint Value 3 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:115.++0x0
line.long 0x00 "WCR3,Watchpoint Control 3 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:100.++0x0
line.long 0x00 "WVR4,Watchpoint Value 4 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:116.++0x0
line.long 0x00 "WCR4,Watchpoint Control 4 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:101.++0x0
line.long 0x00 "WVR5,Watchpoint Value 5 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:117.++0x0
line.long 0x00 "WCR5,Watchpoint Control 5 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:102.++0x0
line.long 0x00 "WVR6,Watchpoint Value 6 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:118.++0x0
line.long 0x00 "WCR6,Watchpoint Control 6 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:103.++0x0
line.long 0x00 "WVR7,Watchpoint Value 7 Register"
hexmask.long 0x00 2.--31. 0x04 " WA0   ,Watchpoint Address 0"
group.long c14:119.++0x0
line.long 0x00 "WCR7,Watchpoint Control 7 Register"
bitfld.long 0x0 24.--28. " WAM   ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF"
bitfld.long 0x0 20. "                  EL   ,Enable Linking" "Disabled,Enabled"
textline "                "
bitfld.long 0x0 16.--19. " LBN   ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15"
bitfld.long 0x0 14.--15. "                       SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..."
textline "                "
bitfld.long 0x0 12. " BAS   ,Byte 7 address select" "0,1"
bitfld.long 0x0 11. ",Byte 6 address select" "0,1"
bitfld.long 0x0 10. ",Byte 5 address select" "0,1"
bitfld.long 0x0 9. ",Byte 4 address select" "0,1"
bitfld.long 0x0 8. ",Byte 3 address select" "0,1"
bitfld.long 0x0 7. ",Byte 2 address select" "0,1"
bitfld.long 0x0 6. ",Byte 1 address select" "0,1"
bitfld.long 0x0 5. ",Byte 0 address select" "0,1"
textline "                "
bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any"
bitfld.long 0x0 1.--2. "                    PAC  ,Privileged access control" "Reserved,Privileged,USR,Any"
textline "                "
bitfld.long 0x0 0. " WE    ,Watchpoint enable" "Disabled,Enabled"
group.long c14:6.++0x0
line.long 0x00 "WFAR ,Watchpoint Fault Address Register"
hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction"
tree.end
width 11.
AUTOINDENT.POP
tree.end
else
AUTOINDENT.PUSH
AUTOINDENT.OFF
tree "Core Registers (c66x)"
config 16. 8.
width 0x0b
tree.open "Cache"
tree "L1P Cache"
base d:0x01840000
width 9.
group.long 0x20++0x7 "L1P Cache Control Registers"
line.long 0x00 "L1PCFG,L1P Configuration Register"
bitfld.long 0x00 0.--2. " L1PMODE ,Size of the L1P cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal"
line.long 0x04 "L1PCC,L1P Cache Control Register"
bitfld.long 0x04 16. " POPER   ,Holds the previous value of the OPER field" "0,1"
bitfld.long 0x04 0. "            OPER ,Controls the L1P freeze mode" "Disabled,Enabled"
wgroup.long 0x4020++0x3
line.long 0x00 "L1PIBAR,L1P Invalidate Base Address Register"
hexmask.long 0x00 0.--31. 1. " L1PIBAR ,32-bit base address for block invalidation"
group.long 0x4024++0x3
line.long 0x00 "L1PIWC,L1P Invalidate Word Count"
hexmask.long.word 0x00 0.--15. 1. " L1PIWC  ,Word count for block invalidation"
group.long 0x5028++0x3
line.long 0x00 "L1PINV,L1P Invalidate Register"
bitfld.long 0x00 0. " I       ,Controls the global invalidation of L1P cache" "Normal,Invalidate"
//width 13.
//wgroup.long 0xD00++0x13 "Memory Protection Lock Registers"
//    line.long 0x00 "L1PMPLK0,Memory Protection Lock Register 0"
//        hexmask.long 0x00 0.--31. 1. " LB   ,Lock Bits 31:0"
//    line.long 0x04 "L1PMPLK1,Memory Protection Lock Register 1"
//        hexmask.long 0x04 0.--31. 1. " LB   ,Lock Bits 63:32"
//    line.long 0x08 "L1PMPLK2,Memory Protection Lock Register 2"
//        hexmask.long 0x08 0.--31. 1. " LB   ,Lock Bits 95:64"
//    line.long 0x0c "L1PMPLK3,Memory Protection Lock Register 3"
//        hexmask.long 0x0c 0.--31. 1. " LB   ,Lock Bits 127:96"
//    line.long 0x10 "L1PMPLKCMD,Memory Protection Lock Command Register"
//        bitfld.long 0x10 2. " KEYR ,Reset status" "No effect,Reset"
//        bitfld.long 0x10 1. "   LOCK ,Interface to complete a lock sequence" "No effect,Locked"
//        bitfld.long 0x10 0. "  UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
//rgroup.long 0xD14++0x3
//    line.long 0x00 "L1PMPLKSTAT,Memory Protection Lock Status Register"
//        bitfld.long 0x00 0. " LK   ,Indicates the lock's current status" "Disengaged,Engaged"
base d:0x0184a000
width 12.
tree "Memory Page Protection Attribute Registers"
group.long 0x640++0x3f
line.long 0x0 "L1PMPPA16,Level 1 Memory Page Protection Attribute Register 16"
bitfld.long 0x0 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x0 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x0 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x0 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x0 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x0 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x0 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x0 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x0 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x0 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x0 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x0 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x0 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x0 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x4 "L1PMPPA17,Level 1 Memory Page Protection Attribute Register 17"
bitfld.long 0x4 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x4 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x4 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x4 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x4 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x4 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x4 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x4 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x4 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x4 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x4 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x4 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x4 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x4 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x8 "L1PMPPA18,Level 1 Memory Page Protection Attribute Register 18"
bitfld.long 0x8 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x8 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x8 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x8 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x8 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x8 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x8 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x8 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x8 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x8 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x8 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x8 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x8 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x8 0. "      UX     ,User execute access type" "Normal,User"
line.long 0xC "L1PMPPA19,Level 1 Memory Page Protection Attribute Register 19"
bitfld.long 0xC 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0xC 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0xC 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0xC 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0xC 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0xC 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0xC 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0xC 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0xC 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0xC 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0xC 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0xC 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0xC 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0xC 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x10 "L1PMPPA20,Level 1 Memory Page Protection Attribute Register 20"
bitfld.long 0x10 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x10 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x10 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x10 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x10 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x10 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x10 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x10 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x10 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x10 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x10 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x10 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x10 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x10 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x14 "L1PMPPA21,Level 1 Memory Page Protection Attribute Register 21"
bitfld.long 0x14 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x14 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x14 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x14 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x14 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x14 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x14 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x14 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x14 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x14 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x14 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x14 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x14 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x14 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x18 "L1PMPPA22,Level 1 Memory Page Protection Attribute Register 22"
bitfld.long 0x18 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x18 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x18 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x18 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x18 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x18 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x18 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x18 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x18 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x18 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x18 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x18 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x18 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x18 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x1C "L1PMPPA23,Level 1 Memory Page Protection Attribute Register 23"
bitfld.long 0x1C 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x1C 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x1C 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x1C 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x1C 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x1C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x1C 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x1C 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x1C 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x1C 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x1C 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x1C 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x1C 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x1C 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x20 "L1PMPPA24,Level 1 Memory Page Protection Attribute Register 24"
bitfld.long 0x20 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x20 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x20 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x20 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x20 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x20 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x20 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x20 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x20 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x20 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x20 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x20 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x20 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x20 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x24 "L1PMPPA25,Level 1 Memory Page Protection Attribute Register 25"
bitfld.long 0x24 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x24 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x24 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x24 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x24 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x24 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x24 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x24 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x24 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x24 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x24 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x24 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x24 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x24 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x28 "L1PMPPA26,Level 1 Memory Page Protection Attribute Register 26"
bitfld.long 0x28 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x28 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x28 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x28 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x28 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x28 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x28 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x28 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x28 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x28 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x28 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x28 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x28 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x28 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x2C "L1PMPPA27,Level 1 Memory Page Protection Attribute Register 27"
bitfld.long 0x2C 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x2C 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x2C 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x2C 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x2C 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x2C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x2C 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x2C 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x2C 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x2C 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x2C 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x2C 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x2C 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x2C 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x30 "L1PMPPA28,Level 1 Memory Page Protection Attribute Register 28"
bitfld.long 0x30 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x30 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x30 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x30 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x30 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x30 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x30 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x30 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x30 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x30 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x30 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x30 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x30 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x30 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x34 "L1PMPPA29,Level 1 Memory Page Protection Attribute Register 29"
bitfld.long 0x34 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x34 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x34 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x34 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x34 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x34 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x34 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x34 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x34 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x34 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x34 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x34 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x34 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x34 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x38 "L1PMPPA30,Level 1 Memory Page Protection Attribute Register 30"
bitfld.long 0x38 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x38 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x38 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x38 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x38 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x38 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x38 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x38 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x38 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x38 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x38 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x38 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x38 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x38 0. "      UX     ,User execute access type" "Normal,User"
line.long 0x3C "L1PMPPA31,Level 1 Memory Page Protection Attribute Register 31"
bitfld.long 0x3C 15. " AID5    ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x3C 14. "      AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x3C 13. "     AID3   ,Controls access from ID = 3" "Denied,Granted"
textline "                     "
bitfld.long 0x3C 12. " AID2    ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x3C 11. "      AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x3C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                     "
bitfld.long 0x3C 9. " AIDX    ,Controls access from ID>=6" "Denied,Granted"
bitfld.long 0x3C 8. "      LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                     "
bitfld.long 0x3C 5. " SR      ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x3C 4. "   SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x3C 3. "  SX     ,Supervisor execute access type" "Normal,Supervisor"
textline "                     "
bitfld.long 0x3C 2. " UR      ,User read access type" "Normal,User"
bitfld.long 0x3C 1. "       UW    ,User write access type" "Normal,User"
bitfld.long 0x3C 0. "      UX     ,User execute access type" "Normal,User"
tree.end
width 11.
rgroup.long 0x400++0x7 "Memory Protection Fault Registers"
line.long 0x00 "L1PMPFAR,L1P Memory Protection Fault Address"
hexmask.long 0x00 0.--31. 1. " FA     ,Fault Address"
line.long 0x04 "L1PMPFSR,L1P Memory Protection Fault Set Register"
hexmask.long.byte 0x04 9.--15. 1. " FID    ,Bit 6:0 of faulting requestor"
bitfld.long 0x04 8. "         LOCAL ,Local access" "Normal,Local"
bitfld.long 0x04 5. "  SR ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x04 4. "  SW ,Supervisor write access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x04 2. " UR     ,User read access type" "Normal,User"
bitfld.long 0x04 1. "     UW    ,User write access type" "Normal,User"
group.long 0x408++0x3
line.long 0x00 "L1PMPFCLR,L1P Memory Protection Fault Clear"
bitfld.long 0x00 0. " MPFCLR ,Command to clear the L1DMPFAR and L1DMPFCR" "No effect,Clear"
AUTOINDENT.ON right tree
rgroup.long 0x6404++0x3 "Error Detection Registers"
line.long 0x0 "L1PEDSTAT,L1P Error Detection Status Register"
bitfld.long 0x0  6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True"
bitfld.long 0x0  5. "PERR,Program fetch resulted in parity check error" "False,True"
bitfld.long 0x0  3. "SUSP,Error detection logic is suspended" "False,True"
bitfld.long 0x0  2. "DIS,Error detection logic is disabled" "False,True"
bitfld.long 0x0  0. "EN,Error detection logic is enabled" "False,True"
group.long 0x6408++0x3
line.long 0x0 "L1PEDCMD, L1P Error Detection Command Register"
bitfld.long 0x0  6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear"
bitfld.long 0x0  5. "PCLR,Clears the program fetch parity error status" "No effect,Clear"
bitfld.long 0x0  3. "SUSP,Suspends the error detection logic" "No effect,Suspend"
bitfld.long 0x0  2. "DIS,Disables the error detection logic" "No effect,Disable"
bitfld.long 0x0  0. "EN,Enables the error detection logic" "No effect,Enable"
rgroup.long 0x640C++0x3
line.long 0x0 "L1PEDADDR, L1P Error Detection Address Register"
hexmask.long.long 0x0   5.--31. 32. "ADDR,Contains the upper 27 bit of error location"
bitfld.long       0x0        0.     "RAM,Location where error was detected" "L1P cache,L1P RAM"
AUTOINDENT.OFF
width 0xb
tree.end
tree "L1D Cache"
base d:0x01840000
width 10.
group.long 0x40++0x7 "L1D Cache Control Registers"
line.long 0x00 "L1DCFG,L1D Cache Configuration"
bitfld.long 0x00 0.--2. " L1DMODE  ,Size of the L1D cache" "Disabled,4K,8K,16K,32K,Maximal,Maximal,Maximal"
line.long 0x04 "L1DCC,L1D Cache Control Register"
bitfld.long 0x04 16. " POPER    ,Holds the previous value of the OPER field" "0,1"
bitfld.long 0x04 0. "             OPER ,Controls the L1D freeze mode" "Disabled,Enabled"
wgroup.long 0x4030++0x3
line.long 0x00 "L1DWIBAR,L1D Writeback-Invalidated Base Address"
hexmask.long 0x00 0.--31. 1. " L1DWIBAR ,L1D Writeback-Invalidated Base Address"
group.long 0x4034++0x3
line.long 0x00 "L1DWIWC,L1D Writeback-Invalidated Word Count"
hexmask.long.word 0x00 0.--15. 1. " L1DWIWC  ,L1D Writeback-Invalidated Word Count"
wgroup.long 0x4040++0x3
line.long 0x00 "L1DWBAR,L1D Writeback Base Address"
hexmask.long 0x00 0.--31. 1. " L1DWBAR  ,L1D Writeback Base Address"
group.long 0x4044++0x3
line.long 0x00 "L1DWWC,L1D Writeback Word Count"
hexmask.long.word 0x00 0.--15. 1. " L1DWWC   ,L1D Writeback Word Count"
wgroup.long 0x4048++0x3
line.long 0x00 "L1DIBAR,L1D Invalidate Base Address"
hexmask.long 0x00 0.--31. 1. " L1DIBAR  ,L1D Invalidate Base Address"
group.long 0x404c++0x3
line.long 0x00 "L1DIWC,L1D Invalidate Word Count"
hexmask.long.word 0x00 0.--15. 1. " L1DIWC   ,L1D Invalidate Word Count"
group.long 0x5048++0x3
line.long 0x00 "L1DINV,L1D Invalidate Register"
bitfld.long 0x00 0. " I        ,Controls the global invalidation of L1D cache" "Normal,Invalidate"
group.long 0x5040++0x3
line.long 0x00 "L1DWB,L1P Writeback Register"
bitfld.long 0x00 0. " C        ,Controls the global writeback operation of L1D cache" "Normal,Write back"
group.long 0x5044++0x3
line.long 0x00 "L1DWBINV,L1D Writeback-Invalidate Register"
bitfld.long 0x00 0. " C        ,Controls the global writeback-invalidate operation of L1D cache" "Normal,Invalidate"
width 11.
base d:0x0184a000
tree "Memory Protection Attribute Registers"
group.long 0xe40++0x3f
line.long 0x0 "MPPA16,Memory Protection Attribute Register"
bitfld.long 0x0 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x0 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x0 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x0 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x0 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x0 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x0 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x0 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x0 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x0 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x0 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x0 1. "        UW    ,User write access type" "Normal,User"
line.long 0x4 "MPPA17,Memory Protection Attribute Register"
bitfld.long 0x4 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x4 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x4 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x4 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x4 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x4 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x4 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x4 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x4 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x4 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x4 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x4 1. "        UW    ,User write access type" "Normal,User"
line.long 0x8 "MPPA18,Memory Protection Attribute Register"
bitfld.long 0x8 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x8 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x8 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x8 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x8 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x8 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x8 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x8 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x8 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x8 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x8 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x8 1. "        UW    ,User write access type" "Normal,User"
line.long 0xC "MPPA19,Memory Protection Attribute Register"
bitfld.long 0xC 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0xC 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0xC 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0xC 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0xC 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0xC 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0xC 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0xC 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0xC 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0xC 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0xC 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0xC 1. "        UW    ,User write access type" "Normal,User"
line.long 0x10 "MPPA20,Memory Protection Attribute Register"
bitfld.long 0x10 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x10 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x10 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x10 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x10 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x10 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x10 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x10 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x10 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x10 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x10 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x10 1. "        UW    ,User write access type" "Normal,User"
line.long 0x14 "MPPA21,Memory Protection Attribute Register"
bitfld.long 0x14 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x14 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x14 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x14 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x14 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x14 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x14 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x14 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x14 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x14 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x14 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x14 1. "        UW    ,User write access type" "Normal,User"
line.long 0x18 "MPPA22,Memory Protection Attribute Register"
bitfld.long 0x18 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x18 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x18 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x18 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x18 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x18 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x18 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x18 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x18 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x18 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x18 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x18 1. "        UW    ,User write access type" "Normal,User"
line.long 0x1C "MPPA23,Memory Protection Attribute Register"
bitfld.long 0x1C 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x1C 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x1C 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x1C 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x1C 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x1C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x1C 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x1C 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x1C 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x1C 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x1C 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x1C 1. "        UW    ,User write access type" "Normal,User"
line.long 0x20 "MPPA24,Memory Protection Attribute Register"
bitfld.long 0x20 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x20 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x20 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x20 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x20 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x20 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x20 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x20 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x20 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x20 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x20 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x20 1. "        UW    ,User write access type" "Normal,User"
line.long 0x24 "MPPA25,Memory Protection Attribute Register"
bitfld.long 0x24 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x24 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x24 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x24 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x24 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x24 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x24 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x24 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x24 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x24 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x24 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x24 1. "        UW    ,User write access type" "Normal,User"
line.long 0x28 "MPPA26,Memory Protection Attribute Register"
bitfld.long 0x28 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x28 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x28 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x28 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x28 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x28 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x28 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x28 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x28 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x28 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x28 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x28 1. "        UW    ,User write access type" "Normal,User"
line.long 0x2C "MPPA27,Memory Protection Attribute Register"
bitfld.long 0x2C 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x2C 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x2C 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x2C 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x2C 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x2C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x2C 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x2C 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x2C 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x2C 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x2C 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x2C 1. "        UW    ,User write access type" "Normal,User"
line.long 0x30 "MPPA28,Memory Protection Attribute Register"
bitfld.long 0x30 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x30 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x30 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x30 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x30 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x30 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x30 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x30 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x30 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x30 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x30 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x30 1. "        UW    ,User write access type" "Normal,User"
line.long 0x34 "MPPA29,Memory Protection Attribute Register"
bitfld.long 0x34 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x34 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x34 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x34 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x34 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x34 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x34 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x34 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x34 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x34 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x34 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x34 1. "        UW    ,User write access type" "Normal,User"
line.long 0x38 "MPPA30,Memory Protection Attribute Register"
bitfld.long 0x38 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x38 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x38 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x38 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x38 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x38 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x38 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x38 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x38 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x38 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x38 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x38 1. "        UW    ,User write access type" "Normal,User"
line.long 0x3C "MPPA31,Memory Protection Attribute Register"
bitfld.long 0x3C 15. " AID5     ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x3C 14. "       AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x3C 13. "     AID3   ,Controls access from ID = 3 " "Denied,Granted"
textline "                    "
bitfld.long 0x3C 12. " AID2     ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x3C 11. "       AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x3C 10. "     AID0   ,Controls access from ID = 0" "Denied,Granted"
textline "                    "
bitfld.long 0x3C 9. " AIDX     ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x3C 8. "       LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                    "
bitfld.long 0x3C 4. " SW       ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x3C 5. "    SR    ,Supervisor read access type" "Normal,Supervisor"
textline "                    "
bitfld.long 0x3C 2. " UR       ,User read access type" "Normal,User"
bitfld.long 0x3C 1. "        UW    ,User write access type" "Normal,User"
tree.end
base d:0x0184a000
width 10.
rgroup.long 0xc00++0x7 "Memory Protection Fault Registers"
line.long 0x00 "L1DMPFAR,Memory Protection Fault Address Register"
hexmask.long 0x00 0.--31. 1. " FA     ,Fault Address"
line.long 0x04 "L1DMPFSR,Memory Protection Fault Set Register"
hexmask.long.byte 0x04 9.--15. 1. " FID    ,Bit 6:0 of ID of faulting requestor"
bitfld.long 0x04 8. "          LOCAL ,Local access" "Normal,Supervisor"
bitfld.long 0x04 5. "  SR ,Supervisor read access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x04 4. " SW     ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x04 2. "  UR    ,User read access type" "Normal,User"
bitfld.long 0x04 1. "      UW ,User write access type" "Normal,User"
group.long 0xc08++0x3
line.long 0x00 "L1DMPFCR,Memory Protection Fault Clear Register"
eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Cleared"
width 13.
wgroup.long 0xd00++0xf "Memory Protection Lock Registers"
line.long 0x00 "L1DMPLK0,Level 1 Data Memory Protection Lock Register 0"
hexmask.long 0x00 0.--31. 1. " LB   ,Lock Bits 31:0"
line.long 0x04 "L1DMPLK1,Level 1 Data Memory Protection Lock Register 1"
hexmask.long 0x04 0.--31. 1. " LB   ,Lock Bits 63:32"
line.long 0x08 "L1DMPLK2,Level 1 Data Memory Protection Lock Register 2"
line.long 0x0c "L1DMPLK3,Level 1 Data Memory Protection Lock Register 3"
wgroup.long 0xd10++0x3
line.long 0x00 "L1DMPLKCMD,Level 1 Data Memory Protection Lock Command Register"
bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset"
bitfld.long 0x00 1. "   LOCK ,Interface to complete a lock sequence" "No effect,Locked"
bitfld.long 0x00 0. "  UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
rgroup.long 0xd14++0x3
line.long 0x00 "L1DMPLKSTAT,Level 1 Data Memory Protection Lock Status Register"
bitfld.long 0x00 0. " LK   ,Indicates the lock's current status" "Disengaged,Engaged"
width 0xb
tree.end
tree "L2 Cache"
base d:0x01840000
width 9.
group.long 0x00++0x3 "L2 Cache Control Registers"
line.long 0x00 "L2CFG,L2 Configuration Register"
hexmask.long.byte 0x00 24.--27. 1. " NUM_MM  ,Number of megamodules minus one"
hexmask.long.byte 0x00 16.--19. 1. "           MMID  ,Contains the Megamodule ID number"
bitfld.long 0x00 9. "          IP     ,L1P global invalidate bit" "Normal,Invalidate"
textline "                  "
bitfld.long 0x00 8. " ID      ,L1D global invalidate bit" "Normal,Invalidate"
bitfld.long 0x00 3. "   L2CC  ,Freeze mode" "Normal,Frozen"
bitfld.long 0x00 0.--2. "      L2MODE ,Size of L2 cache" "Disabled,32K,64K,128K,256K,512K,1024K,Maximum"
wgroup.long 0x4000++0x3
line.long 0x00 "L2WBAR,L2 Writeback Base Address Register"
hexmask.long 0x00 0.--31. 1. " L2WBAR  ,L2 Writeback Base Address"
group.long 0x4004++0x3
line.long 0x00 "L2WWC,L2 Writeback Word Count Register"
hexmask.long.word 0x00 0.--15. 1. " L2WWC   ,L2 Writeback Word Count"
wgroup.long 0x4010++0x3
line.long 0x00 "L2WIBAR,L2 Writeback-Invalidate Base Address"
hexmask.long 0x00 0.--31. 1. " L2WIBAR ,L2 Writeback Invalidate Base Address"
group.long 0x4014++0x3
line.long 0x00 "L2WIWC,L2 Writeback Invalidate Word Count Register"
hexmask.long.word 0x00 0.--15. 1. " L2WIWC  ,L2 Writeback Invalidate Word Count"
wgroup.long 0x4018++0x3
line.long 0x00 "L2IBAR,L2 Invalidate Base Address Register"
hexmask.long 0x00 0.--31. 1. " L2IBAR  ,L2 Invalidate Base Address"
group.long 0x401c++0x3
line.long 0x00 "L2IWC,L2 Invalidate Word Count Register"
hexmask.long.word 0x00 0.--15. 1. " L2IWC   ,L2 Invalidate Word Count"
group.long 0x5000++0xb
line.long 0x00 "L2WB,L2 Writeback Register"
bitfld.long 0x00 0. " C       ,Controls the global writeback operation of L2 cache" "Normal,Writeback"
line.long 0x04 "L2WBINV,L2 Writeback-Invalidate Register"
bitfld.long 0x04 0. " C       ,Controls the global writeback-invalidate operation of L2 cache" "Normal,Writeback"
line.long 0x08 "L2INV,L2 Invalidate Register"
bitfld.long 0x08 0. " I       ,Controls the global invalidation of L2 cache" "Normal,Invalidate"
tree "Memory Attribute Registers"
width 8.
base d:0x01848000
rgroup.long 0x00++0x2f
line.long 0x0 "MAR0,Memory Attribute Register 0"
bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x4 "MAR1,Memory Attribute Register 1"
bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x8 "MAR2,Memory Attribute Register 2"
bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xC "MAR3,Memory Attribute Register 3"
bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x10 "MAR4,Memory Attribute Register 4"
bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x10 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x14 "MAR5,Memory Attribute Register 5"
bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x14 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x18 "MAR6,Memory Attribute Register 6"
bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x18 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1C "MAR7,Memory Attribute Register 7"
bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x20 "MAR8,Memory Attribute Register 8"
bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x20 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x24 "MAR9,Memory Attribute Register 9"
bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x24 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x28 "MAR10,Memory Attribute Register 10"
bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x28 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2C "MAR11,Memory Attribute Register 11"
bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
group.long 0x30++0x3cf
line.long 0x0 "MAR12,Memory Attribute Register 12"
bitfld.long 0x0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x4 "MAR13,Memory Attribute Register 13"
bitfld.long 0x4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x8 "MAR14,Memory Attribute Register 14"
bitfld.long 0x8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xC "MAR15,Memory Attribute Register 15"
bitfld.long 0xC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x10 "MAR16,Memory Attribute Register 16"
bitfld.long 0x10 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x10 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x14 "MAR17,Memory Attribute Register 17"
bitfld.long 0x14 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x14 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x18 "MAR18,Memory Attribute Register 18"
bitfld.long 0x18 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x18 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1C "MAR19,Memory Attribute Register 19"
bitfld.long 0x1C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x20 "MAR20,Memory Attribute Register 20"
bitfld.long 0x20 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x20 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x24 "MAR21,Memory Attribute Register 21"
bitfld.long 0x24 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x24 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x28 "MAR22,Memory Attribute Register 22"
bitfld.long 0x28 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x28 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2C "MAR23,Memory Attribute Register 23"
bitfld.long 0x2C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x30 "MAR24,Memory Attribute Register 24"
bitfld.long 0x30 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x30 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x34 "MAR25,Memory Attribute Register 25"
bitfld.long 0x34 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x34 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x38 "MAR26,Memory Attribute Register 26"
bitfld.long 0x38 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x38 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3C "MAR27,Memory Attribute Register 27"
bitfld.long 0x3C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x40 "MAR28,Memory Attribute Register 28"
bitfld.long 0x40 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x40 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x44 "MAR29,Memory Attribute Register 29"
bitfld.long 0x44 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x44 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x48 "MAR30,Memory Attribute Register 30"
bitfld.long 0x48 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x48 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x4C "MAR31,Memory Attribute Register 31"
bitfld.long 0x4C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x4C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x50 "MAR32,Memory Attribute Register 32"
bitfld.long 0x50 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x50 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x54 "MAR33,Memory Attribute Register 33"
bitfld.long 0x54 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x54 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x58 "MAR34,Memory Attribute Register 34"
bitfld.long 0x58 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x58 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x5C "MAR35,Memory Attribute Register 35"
bitfld.long 0x5C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x5C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x60 "MAR36,Memory Attribute Register 36"
bitfld.long 0x60 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x60 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x64 "MAR37,Memory Attribute Register 37"
bitfld.long 0x64 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x64 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x68 "MAR38,Memory Attribute Register 38"
bitfld.long 0x68 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x68 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x6C "MAR39,Memory Attribute Register 39"
bitfld.long 0x6C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x6C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x70 "MAR40,Memory Attribute Register 40"
bitfld.long 0x70 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x70 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x74 "MAR41,Memory Attribute Register 41"
bitfld.long 0x74 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x74 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x78 "MAR42,Memory Attribute Register 42"
bitfld.long 0x78 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x78 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x7C "MAR43,Memory Attribute Register 43"
bitfld.long 0x7C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x7C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x80 "MAR44,Memory Attribute Register 44"
bitfld.long 0x80 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x80 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x84 "MAR45,Memory Attribute Register 45"
bitfld.long 0x84 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x84 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x88 "MAR46,Memory Attribute Register 46"
bitfld.long 0x88 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x88 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x8C "MAR47,Memory Attribute Register 47"
bitfld.long 0x8C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x8C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x90 "MAR48,Memory Attribute Register 48"
bitfld.long 0x90 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x90 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x94 "MAR49,Memory Attribute Register 49"
bitfld.long 0x94 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x94 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x98 "MAR50,Memory Attribute Register 50"
bitfld.long 0x98 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x98 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x9C "MAR51,Memory Attribute Register 51"
bitfld.long 0x9C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x9C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xA0 "MAR52,Memory Attribute Register 52"
bitfld.long 0xA0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xA0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xA4 "MAR53,Memory Attribute Register 53"
bitfld.long 0xA4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xA4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xA8 "MAR54,Memory Attribute Register 54"
bitfld.long 0xA8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xA8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xAC "MAR55,Memory Attribute Register 55"
bitfld.long 0xAC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xAC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xB0 "MAR56,Memory Attribute Register 56"
bitfld.long 0xB0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xB0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xB4 "MAR57,Memory Attribute Register 57"
bitfld.long 0xB4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xB4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xB8 "MAR58,Memory Attribute Register 58"
bitfld.long 0xB8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xB8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xBC "MAR59,Memory Attribute Register 59"
bitfld.long 0xBC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xBC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xC0 "MAR60,Memory Attribute Register 60"
bitfld.long 0xC0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xC0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xC4 "MAR61,Memory Attribute Register 61"
bitfld.long 0xC4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xC4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xC8 "MAR62,Memory Attribute Register 62"
bitfld.long 0xC8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xC8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xCC "MAR63,Memory Attribute Register 63"
bitfld.long 0xCC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xCC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xD0 "MAR64,Memory Attribute Register 64"
bitfld.long 0xD0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xD0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xD4 "MAR65,Memory Attribute Register 65"
bitfld.long 0xD4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xD4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xD8 "MAR66,Memory Attribute Register 66"
bitfld.long 0xD8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xD8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xDC "MAR67,Memory Attribute Register 67"
bitfld.long 0xDC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xDC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xE0 "MAR68,Memory Attribute Register 68"
bitfld.long 0xE0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xE0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xE4 "MAR69,Memory Attribute Register 69"
bitfld.long 0xE4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xE4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xE8 "MAR70,Memory Attribute Register 70"
bitfld.long 0xE8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xE8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xEC "MAR71,Memory Attribute Register 71"
bitfld.long 0xEC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xEC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xF0 "MAR72,Memory Attribute Register 72"
bitfld.long 0xF0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xF0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xF4 "MAR73,Memory Attribute Register 73"
bitfld.long 0xF4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xF4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xF8 "MAR74,Memory Attribute Register 74"
bitfld.long 0xF8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xF8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0xFC "MAR75,Memory Attribute Register 75"
bitfld.long 0xFC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0xFC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x100 "MAR76,Memory Attribute Register 76"
bitfld.long 0x100 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x100 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x104 "MAR77,Memory Attribute Register 77"
bitfld.long 0x104 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x104 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x108 "MAR78,Memory Attribute Register 78"
bitfld.long 0x108 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x108 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x10C "MAR79,Memory Attribute Register 79"
bitfld.long 0x10C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x10C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x110 "MAR80,Memory Attribute Register 80"
bitfld.long 0x110 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x110 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x114 "MAR81,Memory Attribute Register 81"
bitfld.long 0x114 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x114 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x118 "MAR82,Memory Attribute Register 82"
bitfld.long 0x118 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x118 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x11C "MAR83,Memory Attribute Register 83"
bitfld.long 0x11C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x11C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x120 "MAR84,Memory Attribute Register 84"
bitfld.long 0x120 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x120 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x124 "MAR85,Memory Attribute Register 85"
bitfld.long 0x124 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x124 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x128 "MAR86,Memory Attribute Register 86"
bitfld.long 0x128 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x128 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x12C "MAR87,Memory Attribute Register 87"
bitfld.long 0x12C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x12C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x130 "MAR88,Memory Attribute Register 88"
bitfld.long 0x130 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x130 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x134 "MAR89,Memory Attribute Register 89"
bitfld.long 0x134 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x134 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x138 "MAR90,Memory Attribute Register 90"
bitfld.long 0x138 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x138 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x13C "MAR91,Memory Attribute Register 91"
bitfld.long 0x13C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x13C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x140 "MAR92,Memory Attribute Register 92"
bitfld.long 0x140 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x140 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x144 "MAR93,Memory Attribute Register 93"
bitfld.long 0x144 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x144 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x148 "MAR94,Memory Attribute Register 94"
bitfld.long 0x148 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x148 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x14C "MAR95,Memory Attribute Register 95"
bitfld.long 0x14C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x14C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x150 "MAR96,Memory Attribute Register 96"
bitfld.long 0x150 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x150 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x154 "MAR97,Memory Attribute Register 97"
bitfld.long 0x154 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x154 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x158 "MAR98,Memory Attribute Register 98"
bitfld.long 0x158 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x158 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x15C "MAR99,Memory Attribute Register 99"
bitfld.long 0x15C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x15C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x160 "MAR100,Memory Attribute Register 100"
bitfld.long 0x160 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x160 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x164 "MAR101,Memory Attribute Register 101"
bitfld.long 0x164 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x164 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x168 "MAR102,Memory Attribute Register 102"
bitfld.long 0x168 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x168 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x16C "MAR103,Memory Attribute Register 103"
bitfld.long 0x16C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x16C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x170 "MAR104,Memory Attribute Register 104"
bitfld.long 0x170 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x170 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x174 "MAR105,Memory Attribute Register 105"
bitfld.long 0x174 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x174 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x178 "MAR106,Memory Attribute Register 106"
bitfld.long 0x178 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x178 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x17C "MAR107,Memory Attribute Register 107"
bitfld.long 0x17C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x17C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x180 "MAR108,Memory Attribute Register 108"
bitfld.long 0x180 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x180 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x184 "MAR109,Memory Attribute Register 109"
bitfld.long 0x184 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x184 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x188 "MAR110,Memory Attribute Register 110"
bitfld.long 0x188 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x188 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x18C "MAR111,Memory Attribute Register 111"
bitfld.long 0x18C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x18C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x190 "MAR112,Memory Attribute Register 112"
bitfld.long 0x190 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x190 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x194 "MAR113,Memory Attribute Register 113"
bitfld.long 0x194 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x194 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x198 "MAR114,Memory Attribute Register 114"
bitfld.long 0x198 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x198 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x19C "MAR115,Memory Attribute Register 115"
bitfld.long 0x19C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x19C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1A0 "MAR116,Memory Attribute Register 116"
bitfld.long 0x1A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1A0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1A4 "MAR117,Memory Attribute Register 117"
bitfld.long 0x1A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1A4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1A8 "MAR118,Memory Attribute Register 118"
bitfld.long 0x1A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1A8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1AC "MAR119,Memory Attribute Register 119"
bitfld.long 0x1AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1AC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1B0 "MAR120,Memory Attribute Register 120"
bitfld.long 0x1B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1B0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1B4 "MAR121,Memory Attribute Register 121"
bitfld.long 0x1B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1B4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1B8 "MAR122,Memory Attribute Register 122"
bitfld.long 0x1B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1B8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1BC "MAR123,Memory Attribute Register 123"
bitfld.long 0x1BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1BC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1C0 "MAR124,Memory Attribute Register 124"
bitfld.long 0x1C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1C0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1C4 "MAR125,Memory Attribute Register 125"
bitfld.long 0x1C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1C4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1C8 "MAR126,Memory Attribute Register 126"
bitfld.long 0x1C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1C8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1CC "MAR127,Memory Attribute Register 127"
bitfld.long 0x1CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1CC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1D0 "MAR128,Memory Attribute Register 128"
bitfld.long 0x1D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1D0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1D4 "MAR129,Memory Attribute Register 129"
bitfld.long 0x1D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1D4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1D8 "MAR130,Memory Attribute Register 130"
bitfld.long 0x1D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1D8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1DC "MAR131,Memory Attribute Register 131"
bitfld.long 0x1DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1DC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1E0 "MAR132,Memory Attribute Register 132"
bitfld.long 0x1E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1E0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1E4 "MAR133,Memory Attribute Register 133"
bitfld.long 0x1E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1E4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1E8 "MAR134,Memory Attribute Register 134"
bitfld.long 0x1E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1E8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1EC "MAR135,Memory Attribute Register 135"
bitfld.long 0x1EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1EC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1F0 "MAR136,Memory Attribute Register 136"
bitfld.long 0x1F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1F0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1F4 "MAR137,Memory Attribute Register 137"
bitfld.long 0x1F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1F4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1F8 "MAR138,Memory Attribute Register 138"
bitfld.long 0x1F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1F8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x1FC "MAR139,Memory Attribute Register 139"
bitfld.long 0x1FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x1FC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x200 "MAR140,Memory Attribute Register 140"
bitfld.long 0x200 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x200 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x204 "MAR141,Memory Attribute Register 141"
bitfld.long 0x204 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x204 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x208 "MAR142,Memory Attribute Register 142"
bitfld.long 0x208 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x208 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x20C "MAR143,Memory Attribute Register 143"
bitfld.long 0x20C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x20C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x210 "MAR144,Memory Attribute Register 144"
bitfld.long 0x210 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x210 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x214 "MAR145,Memory Attribute Register 145"
bitfld.long 0x214 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x214 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x218 "MAR146,Memory Attribute Register 146"
bitfld.long 0x218 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x218 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x21C "MAR147,Memory Attribute Register 147"
bitfld.long 0x21C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x21C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x220 "MAR148,Memory Attribute Register 148"
bitfld.long 0x220 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x220 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x224 "MAR149,Memory Attribute Register 149"
bitfld.long 0x224 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x224 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x228 "MAR150,Memory Attribute Register 150"
bitfld.long 0x228 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x228 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x22C "MAR151,Memory Attribute Register 151"
bitfld.long 0x22C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x22C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x230 "MAR152,Memory Attribute Register 152"
bitfld.long 0x230 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x230 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x234 "MAR153,Memory Attribute Register 153"
bitfld.long 0x234 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x234 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x238 "MAR154,Memory Attribute Register 154"
bitfld.long 0x238 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x238 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x23C "MAR155,Memory Attribute Register 155"
bitfld.long 0x23C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x23C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x240 "MAR156,Memory Attribute Register 156"
bitfld.long 0x240 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x240 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x244 "MAR157,Memory Attribute Register 157"
bitfld.long 0x244 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x244 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x248 "MAR158,Memory Attribute Register 158"
bitfld.long 0x248 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x248 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x24C "MAR159,Memory Attribute Register 159"
bitfld.long 0x24C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x24C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x250 "MAR160,Memory Attribute Register 160"
bitfld.long 0x250 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x250 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x254 "MAR161,Memory Attribute Register 161"
bitfld.long 0x254 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x254 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x258 "MAR162,Memory Attribute Register 162"
bitfld.long 0x258 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x258 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x25C "MAR163,Memory Attribute Register 163"
bitfld.long 0x25C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x25C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x260 "MAR164,Memory Attribute Register 164"
bitfld.long 0x260 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x260 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x264 "MAR165,Memory Attribute Register 165"
bitfld.long 0x264 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x264 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x268 "MAR166,Memory Attribute Register 166"
bitfld.long 0x268 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x268 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x26C "MAR167,Memory Attribute Register 167"
bitfld.long 0x26C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x26C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x270 "MAR168,Memory Attribute Register 168"
bitfld.long 0x270 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x270 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x274 "MAR169,Memory Attribute Register 169"
bitfld.long 0x274 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x274 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x278 "MAR170,Memory Attribute Register 170"
bitfld.long 0x278 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x278 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x27C "MAR171,Memory Attribute Register 171"
bitfld.long 0x27C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x27C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x280 "MAR172,Memory Attribute Register 172"
bitfld.long 0x280 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x280 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x284 "MAR173,Memory Attribute Register 173"
bitfld.long 0x284 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x284 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x288 "MAR174,Memory Attribute Register 174"
bitfld.long 0x288 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x288 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x28C "MAR175,Memory Attribute Register 175"
bitfld.long 0x28C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x28C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x290 "MAR176,Memory Attribute Register 176"
bitfld.long 0x290 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x290 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x294 "MAR177,Memory Attribute Register 177"
bitfld.long 0x294 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x294 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x298 "MAR178,Memory Attribute Register 178"
bitfld.long 0x298 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x298 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x29C "MAR179,Memory Attribute Register 179"
bitfld.long 0x29C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x29C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2A0 "MAR180,Memory Attribute Register 180"
bitfld.long 0x2A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2A0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2A4 "MAR181,Memory Attribute Register 181"
bitfld.long 0x2A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2A4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2A8 "MAR182,Memory Attribute Register 182"
bitfld.long 0x2A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2A8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2AC "MAR183,Memory Attribute Register 183"
bitfld.long 0x2AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2AC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2B0 "MAR184,Memory Attribute Register 184"
bitfld.long 0x2B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2B0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2B4 "MAR185,Memory Attribute Register 185"
bitfld.long 0x2B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2B4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2B8 "MAR186,Memory Attribute Register 186"
bitfld.long 0x2B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2B8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2BC "MAR187,Memory Attribute Register 187"
bitfld.long 0x2BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2BC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2C0 "MAR188,Memory Attribute Register 188"
bitfld.long 0x2C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2C0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2C4 "MAR189,Memory Attribute Register 189"
bitfld.long 0x2C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2C4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2C8 "MAR190,Memory Attribute Register 190"
bitfld.long 0x2C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2C8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2CC "MAR191,Memory Attribute Register 191"
bitfld.long 0x2CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2CC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2D0 "MAR192,Memory Attribute Register 192"
bitfld.long 0x2D0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2D0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2D4 "MAR193,Memory Attribute Register 193"
bitfld.long 0x2D4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2D4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2D8 "MAR194,Memory Attribute Register 194"
bitfld.long 0x2D8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2D8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2DC "MAR195,Memory Attribute Register 195"
bitfld.long 0x2DC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2DC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2E0 "MAR196,Memory Attribute Register 196"
bitfld.long 0x2E0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2E0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2E4 "MAR197,Memory Attribute Register 197"
bitfld.long 0x2E4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2E4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2E8 "MAR198,Memory Attribute Register 198"
bitfld.long 0x2E8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2E8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2EC "MAR199,Memory Attribute Register 199"
bitfld.long 0x2EC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2EC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2F0 "MAR200,Memory Attribute Register 200"
bitfld.long 0x2F0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2F0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2F4 "MAR201,Memory Attribute Register 201"
bitfld.long 0x2F4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2F4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2F8 "MAR202,Memory Attribute Register 202"
bitfld.long 0x2F8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2F8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x2FC "MAR203,Memory Attribute Register 203"
bitfld.long 0x2FC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x2FC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x300 "MAR204,Memory Attribute Register 204"
bitfld.long 0x300 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x300 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x304 "MAR205,Memory Attribute Register 205"
bitfld.long 0x304 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x304 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x308 "MAR206,Memory Attribute Register 206"
bitfld.long 0x308 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x308 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x30C "MAR207,Memory Attribute Register 207"
bitfld.long 0x30C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x30C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x310 "MAR208,Memory Attribute Register 208"
bitfld.long 0x310 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x310 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x314 "MAR209,Memory Attribute Register 209"
bitfld.long 0x314 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x314 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x318 "MAR210,Memory Attribute Register 210"
bitfld.long 0x318 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x318 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x31C "MAR211,Memory Attribute Register 211"
bitfld.long 0x31C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x31C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x320 "MAR212,Memory Attribute Register 212"
bitfld.long 0x320 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x320 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x324 "MAR213,Memory Attribute Register 213"
bitfld.long 0x324 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x324 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x328 "MAR214,Memory Attribute Register 214"
bitfld.long 0x328 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x328 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x32C "MAR215,Memory Attribute Register 215"
bitfld.long 0x32C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x32C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x330 "MAR216,Memory Attribute Register 216"
bitfld.long 0x330 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x330 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x334 "MAR217,Memory Attribute Register 217"
bitfld.long 0x334 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x334 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x338 "MAR218,Memory Attribute Register 218"
bitfld.long 0x338 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x338 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x33C "MAR219,Memory Attribute Register 219"
bitfld.long 0x33C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x33C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x340 "MAR220,Memory Attribute Register 220"
bitfld.long 0x340 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x340 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x344 "MAR221,Memory Attribute Register 221"
bitfld.long 0x344 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x344 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x348 "MAR222,Memory Attribute Register 222"
bitfld.long 0x348 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x348 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x34C "MAR223,Memory Attribute Register 223"
bitfld.long 0x34C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x34C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x350 "MAR224,Memory Attribute Register 224"
bitfld.long 0x350 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x350 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x354 "MAR225,Memory Attribute Register 225"
bitfld.long 0x354 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x354 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x358 "MAR226,Memory Attribute Register 226"
bitfld.long 0x358 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x358 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x35C "MAR227,Memory Attribute Register 227"
bitfld.long 0x35C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x35C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x360 "MAR228,Memory Attribute Register 228"
bitfld.long 0x360 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x360 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x364 "MAR229,Memory Attribute Register 229"
bitfld.long 0x364 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x364 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x368 "MAR230,Memory Attribute Register 230"
bitfld.long 0x368 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x368 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x36C "MAR231,Memory Attribute Register 231"
bitfld.long 0x36C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x36C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x370 "MAR232,Memory Attribute Register 232"
bitfld.long 0x370 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x370 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x374 "MAR233,Memory Attribute Register 233"
bitfld.long 0x374 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x374 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x378 "MAR234,Memory Attribute Register 234"
bitfld.long 0x378 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x378 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x37C "MAR235,Memory Attribute Register 235"
bitfld.long 0x37C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x37C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x380 "MAR236,Memory Attribute Register 236"
bitfld.long 0x380 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x380 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x384 "MAR237,Memory Attribute Register 237"
bitfld.long 0x384 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x384 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x388 "MAR238,Memory Attribute Register 238"
bitfld.long 0x388 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x388 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x38C "MAR239,Memory Attribute Register 239"
bitfld.long 0x38C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x38C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x390 "MAR240,Memory Attribute Register 240"
bitfld.long 0x390 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x390 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x394 "MAR241,Memory Attribute Register 241"
bitfld.long 0x394 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x394 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x398 "MAR242,Memory Attribute Register 242"
bitfld.long 0x398 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x398 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x39C "MAR243,Memory Attribute Register 243"
bitfld.long 0x39C 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x39C 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3A0 "MAR244,Memory Attribute Register 244"
bitfld.long 0x3A0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3A0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3A4 "MAR245,Memory Attribute Register 245"
bitfld.long 0x3A4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3A4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3A8 "MAR246,Memory Attribute Register 246"
bitfld.long 0x3A8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3A8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3AC "MAR247,Memory Attribute Register 247"
bitfld.long 0x3AC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3AC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3B0 "MAR248,Memory Attribute Register 248"
bitfld.long 0x3B0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3B0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3B4 "MAR249,Memory Attribute Register 249"
bitfld.long 0x3B4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3B4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3B8 "MAR250,Memory Attribute Register 250"
bitfld.long 0x3B8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3B8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3BC "MAR251,Memory Attribute Register 251"
bitfld.long 0x3BC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3BC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3C0 "MAR252,Memory Attribute Register 252"
bitfld.long 0x3C0 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3C0 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3C4 "MAR253,Memory Attribute Register 253"
bitfld.long 0x3C4 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3C4 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3C8 "MAR254,Memory Attribute Register 254"
bitfld.long 0x3C8 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3C8 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
line.long 0x3CC "MAR255,Memory Attribute Register 255"
bitfld.long 0x3CC 3. " PFS ,Enables/disables the prefetchability of the affected address range" "Not prefetchable,Prefetchable"
bitfld.long 0x3CC 0. "   PC ,Permit Copies field enables/disables the cacheability of the affected address range" "Not cacheable,Cacheable"
tree.end
width 10.
base d:0x0184a000
tree "Memory Protection Page Attribute Registers"
group.long 0x200++0x7f
line.long 0x0 "L2MPPA0,Level 2 Memory Protection Page Attribute Register 0"
bitfld.long 0x0 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x0 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x0 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x0 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x0 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x0 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x0 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x0 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x0 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x0 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x0 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x0 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x0 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x0 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x4 "L2MPPA1,Level 2 Memory Protection Page Attribute Register 1"
bitfld.long 0x4 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x4 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x4 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x4 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x4 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x4 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x4 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x4 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x4 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x4 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x4 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x4 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x4 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x4 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x8 "L2MPPA2,Level 2 Memory Protection Page Attribute Register 2"
bitfld.long 0x8 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x8 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x8 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x8 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x8 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x8 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x8 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x8 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x8 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x8 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x8 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x8 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x8 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x8 0. "     UX   ,User execute access type" "Normal,User"
line.long 0xC "L2MPPA3,Level 2 Memory Protection Page Attribute Register 3"
bitfld.long 0xC 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0xC 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0xC 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0xC 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0xC 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0xC 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0xC 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0xC 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0xC 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0xC 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0xC 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0xC 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0xC 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0xC 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x10 "L2MPPA4,Level 2 Memory Protection Page Attribute Register 4"
bitfld.long 0x10 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x10 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x10 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x10 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x10 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x10 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x10 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x10 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x10 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x10 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x10 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x10 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x10 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x10 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x14 "L2MPPA5,Level 2 Memory Protection Page Attribute Register 5"
bitfld.long 0x14 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x14 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x14 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x14 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x14 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x14 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x14 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x14 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x14 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x14 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x14 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x14 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x14 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x14 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x18 "L2MPPA6,Level 2 Memory Protection Page Attribute Register 6"
bitfld.long 0x18 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x18 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x18 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x18 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x18 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x18 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x18 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x18 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x18 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x18 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x18 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x18 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x18 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x18 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x1C "L2MPPA7,Level 2 Memory Protection Page Attribute Register 7"
bitfld.long 0x1C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x1C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x1C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x1C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x1C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x1C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x1C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x1C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x1C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x1C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x1C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x1C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x1C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x1C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x20 "L2MPPA8,Level 2 Memory Protection Page Attribute Register 8"
bitfld.long 0x20 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x20 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x20 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x20 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x20 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x20 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x20 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x20 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x20 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x20 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x20 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x20 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x20 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x20 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x24 "L2MPPA9,Level 2 Memory Protection Page Attribute Register 9"
bitfld.long 0x24 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x24 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x24 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x24 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x24 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x24 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x24 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x24 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x24 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x24 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x24 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x24 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x24 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x24 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x28 "L2MPPA10,Level 2 Memory Protection Page Attribute Register 10"
bitfld.long 0x28 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x28 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x28 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x28 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x28 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x28 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x28 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x28 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x28 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x28 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x28 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x28 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x28 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x28 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x2C "L2MPPA11,Level 2 Memory Protection Page Attribute Register 11"
bitfld.long 0x2C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x2C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x2C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x2C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x2C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x2C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x2C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x2C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x2C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x2C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x2C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x2C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x2C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x2C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x30 "L2MPPA12,Level 2 Memory Protection Page Attribute Register 12"
bitfld.long 0x30 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x30 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x30 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x30 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x30 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x30 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x30 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x30 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x30 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x30 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x30 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x30 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x30 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x30 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x34 "L2MPPA13,Level 2 Memory Protection Page Attribute Register 13"
bitfld.long 0x34 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x34 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x34 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x34 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x34 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x34 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x34 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x34 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x34 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x34 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x34 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x34 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x34 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x34 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x38 "L2MPPA14,Level 2 Memory Protection Page Attribute Register 14"
bitfld.long 0x38 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x38 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x38 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x38 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x38 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x38 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x38 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x38 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x38 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x38 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x38 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x38 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x38 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x38 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x3C "L2MPPA15,Level 2 Memory Protection Page Attribute Register 15"
bitfld.long 0x3C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x3C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x3C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x3C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x3C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x3C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x3C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x3C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x3C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x3C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x3C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x3C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x3C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x3C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x40 "L2MPPA16,Level 2 Memory Protection Page Attribute Register 16"
bitfld.long 0x40 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x40 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x40 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x40 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x40 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x40 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x40 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x40 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x40 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x40 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x40 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x40 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x40 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x40 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x44 "L2MPPA17,Level 2 Memory Protection Page Attribute Register 17"
bitfld.long 0x44 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x44 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x44 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x44 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x44 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x44 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x44 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x44 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x44 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x44 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x44 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x44 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x44 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x44 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x48 "L2MPPA18,Level 2 Memory Protection Page Attribute Register 18"
bitfld.long 0x48 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x48 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x48 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x48 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x48 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x48 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x48 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x48 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x48 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x48 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x48 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x48 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x48 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x48 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x4C "L2MPPA19,Level 2 Memory Protection Page Attribute Register 19"
bitfld.long 0x4C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x4C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x4C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x4C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x4C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x4C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x4C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x4C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x4C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x4C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x4C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x4C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x4C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x4C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x50 "L2MPPA20,Level 2 Memory Protection Page Attribute Register 20"
bitfld.long 0x50 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x50 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x50 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x50 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x50 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x50 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x50 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x50 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x50 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x50 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x50 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x50 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x50 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x50 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x54 "L2MPPA21,Level 2 Memory Protection Page Attribute Register 21"
bitfld.long 0x54 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x54 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x54 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x54 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x54 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x54 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x54 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x54 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x54 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x54 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x54 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x54 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x54 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x54 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x58 "L2MPPA22,Level 2 Memory Protection Page Attribute Register 22"
bitfld.long 0x58 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x58 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x58 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x58 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x58 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x58 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x58 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x58 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x58 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x58 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x58 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x58 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x58 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x58 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x5C "L2MPPA23,Level 2 Memory Protection Page Attribute Register 23"
bitfld.long 0x5C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x5C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x5C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x5C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x5C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x5C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x5C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x5C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x5C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x5C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x5C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x5C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x5C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x5C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x60 "L2MPPA24,Level 2 Memory Protection Page Attribute Register 24"
bitfld.long 0x60 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x60 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x60 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x60 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x60 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x60 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x60 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x60 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x60 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x60 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x60 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x60 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x60 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x60 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x64 "L2MPPA25,Level 2 Memory Protection Page Attribute Register 25"
bitfld.long 0x64 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x64 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x64 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x64 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x64 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x64 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x64 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x64 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x64 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x64 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x64 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x64 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x64 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x64 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x68 "L2MPPA26,Level 2 Memory Protection Page Attribute Register 26"
bitfld.long 0x68 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x68 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x68 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x68 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x68 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x68 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x68 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x68 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x68 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x68 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x68 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x68 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x68 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x68 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x6C "L2MPPA27,Level 2 Memory Protection Page Attribute Register 27"
bitfld.long 0x6C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x6C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x6C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x6C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x6C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x6C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x6C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x6C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x6C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x6C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x6C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x6C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x6C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x6C 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x70 "L2MPPA28,Level 2 Memory Protection Page Attribute Register 28"
bitfld.long 0x70 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x70 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x70 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x70 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x70 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x70 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x70 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x70 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x70 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x70 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x70 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x70 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x70 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x70 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x74 "L2MPPA29,Level 2 Memory Protection Page Attribute Register 29"
bitfld.long 0x74 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x74 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x74 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x74 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x74 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x74 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x74 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x74 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x74 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x74 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x74 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x74 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x74 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x74 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x78 "L2MPPA30,Level 2 Memory Protection Page Attribute Register 30"
bitfld.long 0x78 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x78 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x78 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x78 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x78 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x78 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x78 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x78 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x78 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x78 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x78 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x78 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x78 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x78 0. "     UX   ,User execute access type" "Normal,User"
line.long 0x7C "L2MPPA31,Level 2 Memory Protection Page Attribute Register 31"
bitfld.long 0x7C 15. " AID5 ,Controls access from ID = 5" "Denied,Granted"
bitfld.long 0x7C 14. "     AID4  ,Controls access from ID = 4" "Denied,Granted"
bitfld.long 0x7C 13. "    AID3 ,Controls access from ID = 3 " "Denied,Granted"
textline "                   "
bitfld.long 0x7C 12. " AID2 ,Controls access from ID = 2" "Denied,Granted"
bitfld.long 0x7C 11. "     AID1  ,Controls access from ID = 1" "Denied,Granted"
bitfld.long 0x7C 10. "    AID0 ,Controls access from ID = 0" "Denied,Granted"
textline "                   "
bitfld.long 0x7C 9. " AIDX ,Controls ID >=6" "Denied,Granted"
bitfld.long 0x7C 8. "     LOCAL ,Controls access from CPU to local memories" "Denied,Granted"
textline "                   "
bitfld.long 0x7C 5. " SR   ,Supervisor read access type" "Normal,Supervisor"
bitfld.long 0x7C 4. "  SW    ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x7C 3. " SX   ,Supervisor execute access type" "Normal,Supervisor"
textline "                   "
bitfld.long 0x7C 2. " UR   ,User read access type" "Normal,User"
bitfld.long 0x7C 1. "      UW    ,User write access type" "Normal,User"
bitfld.long 0x7C 0. "     UX   ,User execute access type" "Normal,User"
tree.end
width 9.
rgroup.long 0x000++0x7 "Memory Protection Fault Registers"
line.long 0x00 "L2MPFAR,Level 2 Memory Protection Fault Address Register"
hexmask.long 0x00 0.--31. 1. " FA     ,Fault Address"
line.long 0x04 "L2MPFSR,Level 2 Memory Protection Fault Set Register"
hexmask.long.byte 0x04 9.--15. 1. " FID    ,Bit 6:0 of ID of faulting requestor"
bitfld.long 0x04 8. "          LOCAL ,Local access" "Normal,Supervisor"
bitfld.long 0x04 5. "  SR ,Supervisor read access type" "Normal,Supervisor"
textline "                  "
bitfld.long 0x04 4. " SW     ,Supervisor write access type" "Normal,Supervisor"
bitfld.long 0x04 2. "  UR    ,User read access type" "Normal,User"
bitfld.long 0x04 1. "      UW ,User write access type" "Normal,User"
group.long 0x008++0x3
line.long 0x00 "L2MPFCR,Level 2 Memory Protection Fault Clear Register"
eventfld.long 0x00 0. " MPFCLR ,Clear L1DMPFAR and L1DMPFCR" "No effect,Clear"
width 12.
wgroup.long 0x100++0xf "Memory Protection Lock Registers"
line.long 0x00 "L2MPLK0,Level 2 Memory Protection Lock 0"
hexmask.long 0x00 0.--31. 1. " LB   ,Lock Bits 31:0"
line.long 0x04 "L2MPLK1,Level 2 Memory Protection Lock 1"
hexmask.long 0x04 0.--31. 1. " LB   ,Lock Bits 63:32"
line.long 0x08 "L2MPLK2,Level 2 Memory Protection Lock 2"
hexmask.long 0x08 0.--31. 1. " LB   ,Lock Bits 95:64"
line.long 0x0c "L2MPLK3,Level 2 Memory Protection Lock 3"
hexmask.long 0x0c 0.--31. 1. " LB   ,Lock Bits 127:96"
wgroup.long 0x110++0x3
line.long 0x00 "L2MPLKCMD,Level 2 Memory Protection Lock Command Register"
bitfld.long 0x00 2. " KEYR ,Reset status" "No effect,Reset"
bitfld.long 0x00 1. "   LOCK ,Interface to complete a lock sequence" "No effect,Locked"
bitfld.long 0x00 0. "  UNLOCK ,Interface to complete an unlock sequence" "No effect,Unlocked"
rgroup.long 0x114++0x3
line.long 0x00 "L2MPLKSTAT,Level 2 Memory Protection Lock Status Register"
bitfld.long 0x00 0. " LK   ,Indicates the lock's current status" "Disengaged,Engaged"
AUTOINDENT.ON right tree
base d:0x01846000
rgroup.long 0x4++0x3 "Error Detection Registers"
line.long 0x0 "L2EDSTAT,L2 Error Detection Status Register"
decmask.long.byte 0x0  16.--23. "BITPOS,Single Bit error position"
bitfld.long       0x0    8.--9. "NERR" "Single Bit error,Double Bit error,,Error in parity value"
newline
bitfld.long       0x0        7. "VERR,Error occurred on L2 victims" "False,True"
bitfld.long       0x0        6. "DMAERR,DMA/IDMA access to L1P memory resulted in parity check error" "False,True"
bitfld.long       0x0        5. "PERR,Program fetch resulted in parity check error" "False,True"
newline
bitfld.long       0x0        3. "SUSP,Error detection logic is suspended" "False,True"
bitfld.long       0x0        2. "DIS,Error detection logic is disabled" "False,True"
bitfld.long       0x0        0. "EN,Error detection logic is enabled" "False,True"
group.long 0x8++0x3
line.long 0x0 "L2EDCMD, L2 Error Detection Command Register"
bitfld.long 0x0  7. "VCLR,Clears the victim parity error status" "No effect,Clear"
bitfld.long 0x0  6. "DMACLR,Clears the DMA/IDMA read parity error status" "No effect,Clear"
bitfld.long 0x0  5. "PCLR,Clears the program fetch parity error status" "No effect,Clear"
bitfld.long 0x0  4. "DCLR,Clears the data fetch parity error status" "No effect,Clear"
newline
bitfld.long 0x0  3. "SUSP,Suspends the error detection logic" "No effect,Suspend"
bitfld.long 0x0  2. "DIS,Disables the error detection logic" "No effect,Disable"
bitfld.long 0x0  0. "EN,Enables the error detection logic" "No effect,Enable"
rgroup.long 0xC++0x3
line.long 0x0 "L2EDADDR,L2 Error Detection Address Register"
hexmask.long.long 0x0   5.--31. 32. "ADDR,Address of parity error (5 LSBs assumed to be 00000b)"
bitfld.long       0x0    8.--9.     "L2WAY,Error detected in Way" "Way 0,Way 1,Way 2,Way 3"
bitfld.long       0x0        0.     "RAM,Location where error was detected" "L2,RAM"
rgroup.long 0x18++0x3
line.long 0x0 "L2EDCPEC,L2 Error Detection Correctable Parity Error Counter Register"
hexmask.long.byte 0x0    0.--7.     "CNT,Counter value"
rgroup.long 0x1C++0x3
line.long 0x0 "L2EDNPEC,L2 Error Detection Non-correctable Parity Error Counter Register"
hexmask.long.byte 0x0    0.--7.     "CNT,Counter value"
group.long 0x30++0x3
line.long 0x0 "L2EDCEN,L2 Error Detection and Correction Enable Register"
bitfld.long       0x0        0. "SDMAEN,EDC on SDMA read from L2 RAM" "Disabled,Enabled"
bitfld.long       0x0        0. "PL2SEN,EDC on L1P memory controller read from L2 RAM" "Disabled,Enabled"
bitfld.long       0x0        0. "DL2SEN,EDC on L1D memory controller read from L2 RAM" "Disabled,Enabled"
bitfld.long       0x0        0. "PL2CEN,EDC on L1P memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled"
bitfld.long       0x0        0. "DL2CEN,EDC on L1D memory controller reads from an external address (Hits L2 cache)" "Disabled,Enabled"
AUTOINDENT.OFF
width 0xb
tree.end
tree.end
tree "IDMA (Internal Direct Memory Access Controller)"
width 14.
base d:0x01820000
rgroup.long 0x00++0x3 "Channel 0"
line.long 0x00 "IDMA0_STAT,IDMA Channel 0 Status Register"
bitfld.long 0x00 1. " PEND       ,Pending transfer" "Not pending,Pending"
bitfld.long 0x00 0. "  ACTV  ,Active transfer" "Not active,Active"
group.long 0x04++0xf
line.long 0x00 "IDMA0_MASK,IDMA Channel 0 Mask Register"
bitfld.long 0x00 31. " M31        ,Mask bit 31" "Not masked,Masked"
bitfld.long 0x00 30. "   M30   ,Mask bit 30" "Not masked,Masked"
bitfld.long 0x00 29. "  M29  ,Mask bit 29" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 28. " M28        ,Mask bit 28" "Not masked,Masked"
bitfld.long 0x00 27. "   M27   ,Mask bit 27" "Not masked,Masked"
bitfld.long 0x00 26. "  M26  ,Mask bit 26" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 25. " M25        ,Mask bit 25" "Not masked,Masked"
bitfld.long 0x00 24. "   M24   ,Mask bit 24" "Not masked,Masked"
bitfld.long 0x00 23. "  M23  ,Mask bit 23" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 22. " M22        ,Mask bit 22" "Not masked,Masked"
bitfld.long 0x00 21. "   M21   ,Mask bit 21" "Not masked,Masked"
bitfld.long 0x00 20. "  M20  ,Mask bit 20" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 19. " M19        ,Mask bit 19" "Not masked,Masked"
bitfld.long 0x00 18. "   M18   ,Mask bit 18" "Not masked,Masked"
bitfld.long 0x00 17. "  M17  ,Mask bit 17" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 16. " M16        ,Mask bit 16" "Not masked,Masked"
bitfld.long 0x00 15. "   M15   ,Mask bit 15" "Not masked,Masked"
bitfld.long 0x00 14. "  M14  ,Mask bit 14" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 13. " M13        ,Mask bit 13" "Not masked,Masked"
bitfld.long 0x00 12. "   M12   ,Mask bit 12" "Not masked,Masked"
bitfld.long 0x00 11. "  M11  ,Mask bit 11" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 10. " M10        ,Mask bit 10" "Not masked,Masked"
bitfld.long 0x00 9. "   M9    ,Mask bit 9" "Not masked,Masked"
bitfld.long 0x00 8. "  M8   ,Mask bit 8" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 7. " M7         ,Mask bit 7" "Not masked,Masked"
bitfld.long 0x00 6. "   M6    ,Mask bit 6" "Not masked,Masked"
bitfld.long 0x00 5. "  M5   ,Mask bit 5" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 4. " M4         ,Mask bit 4" "Not masked,Masked"
bitfld.long 0x00 3. "   M3    ,Mask bit 3" "Not masked,Masked"
bitfld.long 0x00 2. "  M2   ,Mask bit 2" "Not masked,Masked"
textline "                       "
bitfld.long 0x00 1. " M1         ,Mask bit 1" "Not masked,Masked"
bitfld.long 0x00 0. "   M0    ,Mask bit 0" "Not masked,Masked"
line.long 0x04 "IDMA0_SOURCE,IDMA Channel 0 Source Address Register"
hexmask.long 0x04 5.--31. 0x20 " SOURCEADDR ,Source address"
line.long 0x08 "IDMA0_DEST,IDMA Channel 0 Destination Address Register"
hexmask.long 0x08 5.--31. 0x20 " DESTADDR   ,Destination address"
line.long 0x0c "IDMA0_COUNT,IDMA Channel 0 Count Register"
bitfld.long 0x0c 28. " INT        ,CPU interrupt enable" "Disabled,Enabled"
bitfld.long 0x0c 0.--3. "     COUNT ,4-bit block count" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
rgroup.long 0x100++0x3 "Channel 1"
line.long 0x00 "IDMA1_STAT,IDMA Channel 1 Status Register"
bitfld.long 0x00 1. " PEND       ,Pending transfer" "Not pending,Pending"
bitfld.long 0x00 0. "  ACTV  ,Active transfer" "Not active,Active"
group.long 0x108++0xb
line.long 0x00 "IDMA1_SOURCE,IDMA Channel 1 Source Address Register"
hexmask.long 0x00 0.--31. 1. " SOURCEADDR ,Source address"
line.long 0x04 "IDMA1_DEST,IDMA Channel 1 Destination Address Register"
hexmask.long 0x04 2.--31. 0x4 " DESTADDR   ,Destination address"
line.long 0x08 "IDMA1_COUNT,IDMA Channel 1 Count Register"
bitfld.long 0x08 29.--31. " PRI        ,Transfer priority" "Highest,1,2,3,4,5,6,Lowest"
bitfld.long 0x08 28. "      INT   ,CPU interrupt enable" "Disabled,Enabled"
bitfld.long 0x08 16. "    FILL ,Block fill" "0,1"
textline "                       "
hexmask.long.word 0x08 0.--15. 1. " COUNT      ,Byte count"
width 0xb
tree.end
tree "XMC (Extended Memory Controller)"
width 14.
AUTOINDENT.ON right tree
base d:0x08000000
group.long 0x00++0x7F "XMC MPAX Segment Registers"
line.long 0x0 "XMPAXL0,MPAX segment 0 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x0       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x0       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x0       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x0       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x0       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x0       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x0+0x4 "XMPAXH0,MPAX segment 0 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x0    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x8 "XMPAXL1,MPAX segment 1 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x8       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x8       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x8       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x8       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x8       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x8       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x8+0x4 "XMPAXH1,MPAX segment 1 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x8    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x10 "XMPAXL2,MPAX segment 2 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x10       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x10       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x10       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x10       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x10       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x10       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x10+0x4 "XMPAXH2,MPAX segment 2 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x10    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x18 "XMPAXL3,MPAX segment 3 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x18       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x18       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x18       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x18       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x18       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x18       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x18+0x4 "XMPAXH3,MPAX segment 3 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x18    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x20 "XMPAXL4,MPAX segment 4 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x20       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x20       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x20       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x20       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x20       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x20       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x20+0x4 "XMPAXH4,MPAX segment 4 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x20    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x28 "XMPAXL5,MPAX segment 5 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x28       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x28       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x28       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x28       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x28       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x28       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x28+0x4 "XMPAXH5,MPAX segment 5 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x28    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x30 "XMPAXL6,MPAX segment 6 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x30       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x30       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x30       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x30       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x30       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x30       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x30+0x4 "XMPAXH6,MPAX segment 6 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x30    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x38 "XMPAXL7,MPAX segment 7 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x38       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x38       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x38       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x38       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x38       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x38       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x38+0x4 "XMPAXH7,MPAX segment 7 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x38    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x40 "XMPAXL8,MPAX segment 8 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x40       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x40       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x40       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x40       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x40       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x40       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x40+0x4 "XMPAXH8,MPAX segment 8 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x40    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x48 "XMPAXL9,MPAX segment 9 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x48       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x48       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x48       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x48       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x48       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x48       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x48+0x4 "XMPAXH9,MPAX segment 9 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x48    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x50 "XMPAXL10,MPAX segment 10 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x50       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x50       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x50       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x50       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x50       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x50       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x50+0x4 "XMPAXH10,MPAX segment 10 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x50    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x58 "XMPAXL11,MPAX segment 11 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x58       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x58       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x58       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x58       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x58       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x58       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x58+0x4 "XMPAXH11,MPAX segment 11 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x58    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x60 "XMPAXL12,MPAX segment 12 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x60       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x60       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x60       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x60       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x60       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x60       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x60+0x4 "XMPAXH12,MPAX segment 12 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x60    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x68 "XMPAXL13,MPAX segment 13 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x68       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x68       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x68       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x68       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x68       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x68       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x68+0x4 "XMPAXH13,MPAX segment 13 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x68    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x70 "XMPAXL14,MPAX segment 14 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x70       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x70       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x70       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x70       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x70       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x70       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x70+0x4 "XMPAXH14,MPAX segment 14 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x70    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
line.long 0x78 "XMPAXL15,MPAX segment 15 low register"
hexmask.long 0x0 8.--31.    "RADDR,Bits that replace and extend the upper address bits matched by BADDR"
bitfld.long  0x78       5.    "SR,Supervisor mode may read from segment" "False,True"
bitfld.long  0x78       4.    "SW,Supervisor mode may write to segment" "False,True"
bitfld.long  0x78       3.    "SX,Supervisor mode may execute from segment" "False,True"
bitfld.long  0x78       2.    "UR,User mode may read from segment" "False,True"
bitfld.long  0x78       1.    "UW,User mode may write to segment" "False,True"
bitfld.long  0x78       0.    "UX,User mode may execute from segment" "False,True"
line.long 0x78+0x4 "XMPAXH15,MPAX segment 15 high register"
hexmask.long 0x0  12.--31.    "BADDR,Base Address"
bitfld.long   0x78    0.--4.    "SEGSZ,Segment size" "Disabled,,,,,,,,,,,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB"
textline ""
rgroup.long 0x200++0x3 "Memory Protection Fault Reporting Registers"
line.long 0. "XMPFAR,Memory Protection Fault Address Register"
hexmask.long 0x0   0.--31.    "Fault Address,Fault Address"
rgroup.long 0x204++0x3
line.long 0. "XMPFSR,Memory Protection Fault Status Register"
bitfld.long  0.         8.    "LOCAL,Access was a LOCAL access" "False,True"
bitfld.long  0.         5.    "SR,When set, indicates a supervisor read request" "False,True"
bitfld.long  0.         4.    "SW,When set, indicates a supervisor write request" "False,True"
bitfld.long  0.         3.    "SX,When set, indicates a supervisor program fetch request" "False,True"
bitfld.long  0.         2.    "UR,When set, indicates a user read request" "False,True"
bitfld.long  0.         1.    "UW,When set, indicates a user write request" "False,True"
bitfld.long  0.         0.    "UX,When set, indicates a user program fetch request" "False,True"
group.long 0x208++0x3
line.long 0. "XMPFCR,Memory Protection Fault Clear Register"
bitfld.long  0.         0.    "MPFCLR,Clear fault" "No effect,Clear"
group.long 0x280++0x3 "Prefetch Priority Register"
line.long 0. "MDMAARBX,MDMA Arbitration Priority Register"
bitfld.long  0.  16.--18.    "PRI,Priority" "0 (highest),1,2,3,4,5,6,7 (lowest)"
rgroup.long 0x300++0x3 "Prefetch Buffer Registers"
line.long 0. "XPFCMD,Prefetch Command Register"
bitfld.long        0.      4.    "ACRST,Analysis Counter Reset" "No effect,Reset"
hexmask.long.byte  0.  2.--3.    "ACEN,Analysis Counter Enable"
bitfld.long        0.      1.    "ACENL,Analysis Counter ENable (ACEN) Load" "False,True"
bitfld.long        0.      0.    "INV,Invalidate prefetch buffer contents" "No effect,Invalidate"
rgroup.long 0x304++0x3 "Prefetch Buffer Performance Analysis Registers"
line.long 0. "XPFACS,Prefetch Analysis Counter Status"
rgroup.long 0x310++0xF
line.long 0x0 "XPFAC0,Prefetch Analysis Counter 0"
line.long 0x4 "XPFAC1,Prefetch Analysis Counter 1"
line.long 0x8 "XPFAC2,Prefetch Analysis Counter 2"
line.long 0xC "XPFAC3,Prefetch Analysis Counter 3"
rgroup.long 0x400++0x1F
line.long 0x0 "XPFADDR0,Prefetch Address for Slot 0"
line.long 0x4 "XPFADDR1,Prefetch Address for Slot 1"
line.long 0x8 "XPFADDR2,Prefetch Address for Slot 2"
line.long 0xC "XPFADDR3,Prefetch Address for Slot 3"
line.long 0x10 "XPFADDR4,Prefetch Address for Slot 4"
line.long 0x14 "XPFADDR5,Prefetch Address for Slot 5"
line.long 0x18 "XPFADDR6,Prefetch Address for Slot 6"
line.long 0x1C "XPFADDR7,Prefetch Address for Slot 7"
AUTOINDENT.OFF
width 0xb
tree.end
tree "Bandwith Management"
width 13.
base d:0x01841000
group.long 0x40++0xf "L1D"
line.long 0x00 "CPUARBD,L1D CPU Arbitration Control Register"
bitfld.long 0x00 16.--18. " PRI     ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
bitfld.long 0x00 0.--5. "  MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x04 "IDMAARBD,L1D IDMA Arbitration Control Register"
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x08 "SDMAARBD,L1D Slave DMA Arbitration Control Register"
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x0c "UCARBD,L1D User Coherence Arbitration Control Register"
bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
width 13.
group.long 0x00++0xf "L2"
line.long 0x00 "CPUARBU,L2D CPU Arbitration Control Register"
bitfld.long 0x00 16.--18. " PRI     ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
bitfld.long 0x00 0.--5. "  MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x04 "IDMAARBU,L1D IDMA Arbitration Control Register"
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x08 "SDMAARBU,L1D Slave DMA Arbitration Control Register"
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x0c "UCARBU,L1D User Coherence Arbitration Control Register"
bitfld.long 0x0c 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
width 13.
base d:0x01820000
group.long 0x200++0xf "EMC"
line.long 0x00 "CPUARBE,EMC CPU Arbitration Control Register"
bitfld.long 0x00 16.--18. " PRI     ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
bitfld.long 0x00 0.--5. "  MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x04 "IDMAARBE,EMC IDMA Arbitration Control Register"
bitfld.long 0x04 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x08 "SDMAARBE,EMC Slave DMA Arbitration Control Register"
bitfld.long 0x08 0.--5. " MAXWAIT ,Maximum wait time in EMC cycles" "Highest,1 cycle,2 cycles,,4 cycles,,,,8 cycles,,,,,,,,16 cycles,,,,,,,,,,,,,,,,32 cycles,..."
line.long 0x0c "MDMAARBE,EMC Master DMA Arbitration Control Register"
bitfld.long 0x0c 16.--18. " PRI     ,Priority field" "Highest,Priority 1,Priority 2,Priority 3,Priority 4,Priority 5,Priority 6,Lowest"
width 0xb
tree.end
tree "Interrupt Controller"
width 11.
base d:0x01800000
group.long 0x00++0xf
line.long 0x00 "EVTFLAG0,Event Flag Register 0"
setclrfld.long 0x00 14. 0x20 14. 0x40 14. " EF14_set/clr  ,State of event EVT14" "Not occurred,Occurred"
setclrfld.long 0x00 13. 0x20 13. 0x40 13. "  EF13_set/clr  ,State of event EVT13" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 12. 0x20 12. 0x40 12. " EF12_set/clr  ,State of event EVT12" "Not occurred,Occurred"
setclrfld.long 0x00 11. 0x20 11. 0x40 11. "  EF11_set/clr  ,State of event EVT11" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 9. 0x20 9. 0x40 9. " EF9_set/clr   ,State of event EVT9" "Not occurred,Occurred"
setclrfld.long 0x00 8. 0x20 8. 0x40 8. "  EF8_set/clr   ,State of event EVT8" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 7. 0x20 7. 0x40 7. " EF7_set/clr   ,State of event EVT7" "Not occurred,Occurred"
setclrfld.long 0x00 6. 0x20 6. 0x40 6. "  EF6_set/clr   ,State of event EVT6" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 5. 0x20 5. 0x40 5. " EF5_set/clr   ,State of event EVT5" "Not occurred,Occurred"
setclrfld.long 0x00 4. 0x20 4. 0x40 4. "  EF4_set/clr   ,State of event EVT4" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 3. 0x20 3. 0x40 3. " EF3_set/clr   ,State of event EVT3" "Not occurred,Occurred"
setclrfld.long 0x00 2. 0x20 2. 0x40 2. "  EF2_set/clr   ,State of event EVT2" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x00 1. 0x20 1. 0x40 1. " EF1_set/clr   ,State of event EVT1" "Not occurred,Occurred"
setclrfld.long 0x00 0. 0x20 0. 0x40 0. "  EF0_set/clr   ,State of event EVT0" "Not occurred,Occurred"
line.long 0x04 "EVTFLAG1,Event Flag Register 1"
setclrfld.long 0x04 28. 0x24 28. 0x44 28. " EF60_set/clr  ,State of event EVT60" "Not occurred,Occurred"
setclrfld.long 0x04 27. 0x24 27. 0x44 27. "  EF59_set/clr  ,State of event EVT59" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 24. 0x24 24. 0x44 24. " EF56_set/clr  ,State of event EVT56" "Not occurred,Occurred"
setclrfld.long 0x04 23. 0x24 23. 0x44 23. "  EF55_set/clr  ,State of event EVT55" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 22. 0x24 22. 0x44 22. " EF54_set/clr  ,State of event EVT54" "Not occurred,Occurred"
setclrfld.long 0x04 21. 0x24 21. 0x44 21. "  EF53_set/clr  ,State of event EVT53" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 19. 0x24 19. 0x44 19. " EF51_set/clr  ,State of event EVT51" "Not occurred,Occurred"
setclrfld.long 0x04 18. 0x24 18. 0x44 18. "  EF50_set/clr  ,State of event EVT50" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 17. 0x24 17. 0x44 17. " EF49_set/clr  ,State of event EVT49" "Not occurred,Occurred"
setclrfld.long 0x04 16. 0x24 16. 0x44 16. "  EF48_set/clr  ,State of event EVT48" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 15. 0x24 15. 0x44 15. " EF47_set/clr  ,State of event EVT47" "Not occurred,Occurred"
setclrfld.long 0x04 11. 0x24 11. 0x44 11. "  EF43_set/clr  ,State of event EVT43" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 9. 0x24 9. 0x44 9. " EF41_set/clr  ,State of event EVT41" "Not occurred,Occurred"
setclrfld.long 0x04 8. 0x24 8. 0x44 8. "  EF40_set/clr  ,State of event EVT40" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 7. 0x24 7. 0x44 7. " EF39_set/clr  ,State of event EVT39" "Not occurred,Occurred"
setclrfld.long 0x04 6. 0x24 6. 0x44 6. "  EF38_set/clr  ,State of event EVT38" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 5. 0x24 5. 0x44 5. " EF37_set/clr  ,State of event EVT37" "Not occurred,Occurred"
setclrfld.long 0x04 4. 0x24 4. 0x44 4. "  EF36_set/clr  ,State of event EVT36" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x04 3. 0x24 3. 0x44 3. " EF35_set/clr  ,State of event EVT35" "Not occurred,Occurred"
setclrfld.long 0x04 2. 0x24 2. 0x44 2. "  EF34_set/clr  ,State of event EVT34" "Not occurred,Occurred"
line.long 0x08 "EVTFLAG2,Event Flag Register 2"
setclrfld.long 0x08 21. 0x28 21. 0x48 21. " EF85_set/clr  ,State of event EVT85" "Not occurred,Occurred"
setclrfld.long 0x08 20. 0x28 20. 0x48 20. "  EF84_set/clr  ,State of event EVT84" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 19. 0x28 19. 0x48 19. " EF83_set/clr  ,State of event EVT83" "Not occurred,Occurred"
setclrfld.long 0x08 18. 0x28 18. 0x48 18. "  EF82_set/clr  ,State of event EVT82" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 17. 0x28 17. 0x48 17. " EF81_set/clr  ,State of event EVT81" "Not occurred,Occurred"
setclrfld.long 0x08 16. 0x28 16. 0x48 16. "  EF80_set/clr  ,State of event EVT80" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 14. 0x28 14. 0x48 14. " EF78_set/clr  ,State of event EVT78" "Not occurred,Occurred"
setclrfld.long 0x08 13. 0x28 13. 0x48 13. "  EF77_set/clr  ,State of event EVT77" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 12. 0x28 12. 0x48 12. " EF76_set/clr  ,State of event EVT76" "Not occurred,Occurred"
setclrfld.long 0x08 11. 0x28 11. 0x48 11. "  EF75_set/clr  ,State of event EVT75" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 10. 0x28 10. 0x48 10. " EF74_set/clr  ,State of event EVT74" "Not occurred,Occurred"
setclrfld.long 0x08 9. 0x28 9. 0x48 9. "  EF73_set/clr  ,State of event EVT73" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 8. 0x28 8. 0x48 8. " EF72_set/clr  ,State of event EVT72" "Not occurred,Occurred"
setclrfld.long 0x08 7. 0x28 7. 0x48 7. "  EF71_set/clr  ,State of event EVT71" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 6. 0x28 6. 0x48 6. " EF70_set/clr  ,State of event EVT70" "Not occurred,Occurred"
setclrfld.long 0x08 5. 0x28 5. 0x48 5. "  EF69_set/clr  ,State of event EVT69" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 4. 0x28 4. 0x48 4. " EF68_set/clr  ,State of event EVT68" "Not occurred,Occurred"
setclrfld.long 0x08 3. 0x28 3. 0x48 3. "  EF67_set/clr  ,State of event EVT67" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 2. 0x28 2. 0x48 2. " EF66_set/clr  ,State of event EVT66" "Not occurred,Occurred"
setclrfld.long 0x08 1. 0x28 1. 0x48 1. "  EF65_set/clr  ,State of event EVT65" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x08 0. 0x28 0. 0x48 0. " EF64_set/clr  ,State of event EVT64" "Not occurred,Occurred"
line.long 0x0c "EVTFLAG3,Event Flag Register 3"
setclrfld.long 0x0c 31. 0x2c 31. 0x4c 31. " EF127_set/clr ,State of event EVT127" "Not occurred,Occurred"
setclrfld.long 0x0c 30. 0x2c 30. 0x4c 30. "  EF126_set/clr ,State of event EVT126" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 29. 0x2c 29. 0x4c 29. " EF125_set/clr ,State of event EVT125" "Not occurred,Occurred"
setclrfld.long 0x0c 28. 0x2c 28. 0x4c 28. "  EF124_set/clr ,State of event EVT124" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 27. 0x2c 27. 0x4c 27. " EF123_set/clr ,State of event EVT123" "Not occurred,Occurred"
setclrfld.long 0x0c 26. 0x2c 26. 0x4c 26. "  EF122_set/clr ,State of event EVT122" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 25. 0x2c 25. 0x4c 25. " EF121_set/clr ,State of event EVT121" "Not occurred,Occurred"
setclrfld.long 0x0c 24. 0x2c 24. 0x4c 24. "  EF120_set/clr ,State of event EVT120" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 23. 0x2c 23. 0x4c 23. " EF119_set/clr ,State of event EVT119" "Not occurred,Occurred"
setclrfld.long 0x0c 22. 0x2c 22. 0x4c 22. "  EF118_set/clr ,State of event EVT118" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 21. 0x2c 21. 0x4c 21. " EF117_set/clr ,State of event EVT117" "Not occurred,Occurred"
setclrfld.long 0x0c 20. 0x2c 20. 0x4c 20. "  EF116_set/clr ,State of event EVT116" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 17. 0x2c 17. 0x4c 17. " EF113_set/clr ,State of event EVT113" "Not occurred,Occurred"
setclrfld.long 0x0c 1. 0x2c 1. 0x4c 1. "  EF97_set/clr  ,State of event EVT97" "Not occurred,Occurred"
textline "                    "
setclrfld.long 0x0c 0. 0x2c 0. 0x4c 0. " EF96_set/clr  ,State of event EVT96" "Not occurred,Occurred"
width 11.
group.long 0x80++0xf
line.long 0x00 "EVTMASK0,Event Mask Register 0"
bitfld.long 0x00 14. " EM14  ,Disables event EVT14 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 13. "  EM13  ,Disables event EVT13 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 12. "  EM12  ,Disables event EVT12 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 11. " EM11  ,Disables event EVT11 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 9. "  EM9   ,Disables event EVT9 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 8. "  EM8   ,Disables event EVT8 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 7. " EM7   ,Disables event EVT7 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 6. "  EM6   ,Disables event EVT6 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 5. "  EM5   ,Disables event EVT5 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 4. " EM4   ,Disables event EVT4 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 3. "  EM3   ,Disables event EVT3 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 2. "  EM2   ,Disables event EVT2 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 1. " EM1   ,Disables event EVT1 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x00 0. "  EM0   ,Disables event EVT0 from being used as input to the event combiner" "Combined,Disabled"
line.long 0x04 "EVTMASK1,Event Mask Register 1"
bitfld.long 0x04 28. " EM60  ,Disables event EVT60 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 27. "  EM59  ,Disables event EVT59 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 24. "  EM56  ,Disables event EVT56 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 23. " EM55  ,Disables event EVT55 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 22. "  EM54  ,Disables event EVT54 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 21. "  EM53  ,Disables event EVT53 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 19. " EM51  ,Disables event EVT51 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 18. "  EM50  ,Disables event EVT50 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 17. "  EM49  ,Disables event EVT49 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 16. " EM48  ,Disables event EVT48 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 15. "  EM47  ,Disables event EVT47 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 11. "  EM43  ,Disables event EVT43 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 9. " EM41  ,Disables event EVT41 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 8. "  EM40  ,Disables event EVT40 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 7. "  EM39  ,Disables event EVT39 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 6. " EM38  ,Disables event EVT38 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 5. "  EM37  ,Disables event EVT37 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 4. "  EM36  ,Disables event EVT36 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 3. " EM35  ,Disables event EVT35 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x04 2. "  EM34  ,Disables event EVT34 from being used as input to the event combiner" "Combined,Disabled"
line.long 0x08 "EVTMASK2,Event Mask Register 2"
bitfld.long 0x08 21. " EM85  ,Disables event EVT85 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 20. "  EM84  ,Disables event EVT84 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 19. "  EM83  ,Disables event EVT83 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 18. " EM82  ,Disables event EVT82 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 17. "  EM81  ,Disables event EVT81 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 16. "  EM80  ,Disables event EVT80 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 14. " EM78  ,Disables event EVT78 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 13. "  EM77  ,Disables event EVT77 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 12. "  EM76  ,Disables event EVT76 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 11. " EM75  ,Disables event EVT75 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 10. "  EM74  ,Disables event EVT74 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 9. "  EM73  ,Disables event EVT73 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 8. " EM72  ,Disables event EVT72 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 7. "  EM71  ,Disables event EVT71 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 6. "  EM70  ,Disables event EVT70 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 5. " EM69  ,Disables event EVT69 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 4. "  EM68  ,Disables event EVT68 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 3. "  EM67  ,Disables event EVT67 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 2. " EM66  ,Disables event EVT66 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 1. "  EM65  ,Disables event EVT65 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x08 0. "  EM64  ,Disables event EVT64 from being used as input to the event combiner" "Combined,Disabled"
line.long 0x0c "EVTMASK3,Event Mask Register 3"
bitfld.long 0x0c 31. " EM127 ,Disables event EVT127 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 30. "  EM126 ,Disables event EVT126 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 29. "  EM125 ,Disables event EVT125 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 28. " EM124 ,Disables event EVT124 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 27. "  EM123 ,Disables event EVT123 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 26. "  EM122 ,Disables event EVT122 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 25. " EM121 ,Disables event EVT121 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 24. "  EM120 ,Disables event EVT120 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 23. "  EM119 ,Disables event EVT119 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 22. " EM118 ,Disables event EVT118 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 21. "  EM117 ,Disables event EVT117 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 20. "  EM116 ,Disables event EVT116 from being used as input to the event combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 17. " EM113 ,Disables event EVT113 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 1. "  EM97  ,Disables event EVT97 from being used as input to the event combiner" "Combined,Disabled"
bitfld.long 0x0c 0. "  EM96  ,Disables event EVT96 from being used as input to the event combiner" "Combined,Disabled"
group.long 0xc0++0xf
line.long 0x00 "EXPMASK0,Exception Mask Register 0"
bitfld.long 0x00 14. " XM14  ,Event EVT14 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 13. "  XM13  ,Event EVT13 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 12. "  XM12  ,Event EVT12 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 11. " XM11  ,Event EVT11 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 9. "  XM9   ,Event EVT9 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 8. "  XM8   ,Event EVT8 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 7. " XM7   ,Event EVT7 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 6. "  XM6   ,Event EVT6 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 5. "  XM5   ,Event EVT5 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 4. " XM4   ,Event EVT4 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 3. "  XM3   ,Event EVT3 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 2. "  XM2   ,Event EVT2 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x00 1. " XM1   ,Event EVT1 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x00 0. "  XM0   ,Event EVT0 disabled from being used in the exception combiner" "Combined,Disabled"
line.long 0x04 "EXPMASK1,Exception Mask Register 1"
bitfld.long 0x04 28. " XM60  ,Event EVT60 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 27. "  XM59  ,Event EVT59 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 24. "  XM56  ,Event EVT56 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 23. " XM55  ,Event EVT55 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 22. "  XM54  ,Event EVT54 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 21. "  XM53  ,Event EVT53 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 19. " XM51  ,Event EVT51 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 18. "  XM50  ,Event EVT50 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 17. "  XM49  ,Event EVT49 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 16. " XM48  ,Event EVT48 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 15. "  XM47  ,Event EVT47 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 11. "  XM43  ,Event EVT43 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 9. " XM41  ,Event EVT41 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 8. "  XM40  ,Event EVT40 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 7. "  XM39  ,Event EVT39 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 6. " XM38  ,Event EVT38 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 5. "  XM37  ,Event EVT37 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 4. "  XM36  ,Event EVT36 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x04 3. " XM35  ,Event EVT35 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x04 2. "  XM34  ,Event EVT34 disabled from being used in the exception combiner" "Combined,Disabled"
line.long 0x08 "EXPMASK2,Exception Mask Register 2"
bitfld.long 0x08 21. " XM85  ,Event EVT85 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 20. "  XM84  ,Event EVT84 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 19. "  XM83  ,Event EVT83 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 18. " XM82  ,Event EVT82 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 17. "  XM81  ,Event EVT81 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 16. "  XM80  ,Event EVT80 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 14. " XM78  ,Event EVT78 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 13. "  XM77  ,Event EVT77 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 12. "  XM76  ,Event EVT76 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 11. " XM75  ,Event EVT75 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 10. "  XM74  ,Event EVT74 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 9. "  XM73  ,Event EVT73 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 8. " XM72  ,Event EVT72 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 7. "  XM71  ,Event EVT71 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 6. "  XM70  ,Event EVT70 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 5. " XM69  ,Event EVT69 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 4. "  XM68  ,Event EVT68 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 3. "  XM67  ,Event EVT67 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x08 2. " XM66  ,Event EVT66 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 1. "  XM65  ,Event EVT65 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x08 0. "  XM64  ,Event EVT64 disabled from being used in the exception combiner" "Combined,Disabled"
line.long 0x0c "EXPMASK3,Exception Mask Register 3"
bitfld.long 0x0c 31. " XM127 ,Event EVT127 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 30. "  XM126 ,Event EVT126 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 29. "  XM125 ,Event EVT125 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 28. " XM124 ,Event EVT124 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 27. "  XM123 ,Event EVT123 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 26. "  XM122 ,Event EVT122 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 25. " XM121 ,Event EVT121 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 24. "  XM120 ,Event EVT120 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 23. "  XM119 ,Event EVT119 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 22. " XM118 ,Event EVT118 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 21. "  XM117 ,Event EVT117 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 20. "  XM116 ,Event EVT116 disabled from being used in the exception combiner" "Combined,Disabled"
textline "                    "
bitfld.long 0x0c 17. " XM113 ,Event EVT113 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 1. "  XM97  ,Event EVT97 disabled from being used in the exception combiner" "Combined,Disabled"
bitfld.long 0x0c 0. "  XM96  ,Event EVT96 disabled from being used in the exception combiner" "Combined,Disabled"
width 11.
rgroup.long 0xa0++0xf
line.long 0x00 "MEVTFLAG0,Masked Event Flag Register 0"
hexmask.long 0x00 0.--31. 1. " MEF[31:0]   ,Displays content of EF when EM=0"
line.long 0x04 "MEVTFLAG1,Masked Event Flag Register 1"
hexmask.long 0x04 0.--31. 1. " MEF[63:32]  ,Displays content of EF when EM=0"
line.long 0x08 "MEVTFLAG2,Masked Event Flag Register 2"
hexmask.long 0x08 0.--31. 1. " MEF[95:64]  ,Displays content of EF when EM=0"
line.long 0x0c "MEVTFLAG3,Masked Event Flag Register 3"
hexmask.long 0x0c 0.--31. 1. " MEF[127:96] ,Displays content of EF when EM=0"
rgroup.long 0xe0++0xf
line.long 0x00 "MEXPFLAG0,Masked Exception Flag Register 0"
line.long 0x04 "MEXPFLAG1,Masked ExceptionFlag Register 1"
line.long 0x08 "MEXPFLAG2,Masked Exception Flag Register 2"
line.long 0x0c "MEXPFLAG3,Masked Exception Flag Register 3"
width 11.
group.long 0x104++0xb
line.long 0x00 "INTMUX1,Interrupt Mux Register 1"
hexmask.long.byte 0x00 24.--30. 1. " INTSEL7  ,Number of the event that maps to CPUINT7"
hexmask.long.byte 0x00 16.--22. 1. "  INTSEL6  ,Number of the event that maps to CPUINT6"
hexmask.long.byte 0x00 8.--14. 1. "  INTSEL5  ,Number of the event that maps to CPUINT5"
hexmask.long.byte 0x00 0.--6. 1. "  INTSEL4  ,Number of the event that maps to CPUINT4"
line.long 0x04 "INTMUX2,Interrupt Mux Register 2"
hexmask.long.byte 0x04 24.--30. 1. " INTSEL11 ,Number of the event that maps to CPUINT11"
hexmask.long.byte 0x04 16.--22. 1. "  INTSEL10 ,Number of the event that maps to CPUINT10"
hexmask.long.byte 0x04 8.--14. 1. "  INTSEL9  ,Number of the event that maps to CPUINT9"
hexmask.long.byte 0x04 0.--6. 1. "  INTSEL8  ,Number of the event that maps to CPUINT8"
line.long 0x08 "INTMUX3,Interrupt Mux Register 3"
hexmask.long.byte 0x08 24.--30. 1. " INTSEL15 ,Number of the event that maps to CPUINT15"
hexmask.long.byte 0x08 16.--22. 1. "  INTSEL14 ,Number of the event that maps to CPUINT14"
hexmask.long.byte 0x08 8.--14. 1. "  INTSEL13 ,Number of the event that maps to CPUINT13"
hexmask.long.byte 0x08 0.--6. 1. "  INTSEL12 ,Number of the event that maps to CPUINT12"
rgroup.long 0x180++0x3
line.long 0x00 "INTXSTAT,Interrupt Exception Status Register"
hexmask.long.byte 0x00 24.--31. 1. " SYSINT   ,System Event number"
hexmask.long.byte 0x00 16.--23. 1. "  CPUINT   ,CPU interrupt number"
bitfld.long 0x00 0. "  DROP     ,Dropped event flag" "No event dropped,Event dropped"
width 11.
wgroup.long 0x184++0x3
line.long 0x00 "INTXCLR,Interrupt Exception Clear Register"
bitfld.long 0x00 0. " CLEAR ,Clears the interrupt exception status" "No effect,Cleared"
rgroup.long 0x188++0x3
line.long 0x00 "INTDMASK,Dropped Interrupt Mask Register"
bitfld.long 0x00 15. " IDM15 ,Disables CPUINT15 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 14. "  IDM14 ,Disables CPUINT14 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 13. "  IDM13 ,Disables CPUINT13 from being detected by the drop detection hardware" "No effect,Ignored"
textline "                    "
bitfld.long 0x00 12. " IDM12 ,Disables CPUINT12 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 11. "  IDM11 ,Disables CPUINT11 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 10. "  IDM10 ,Disables CPUINT10 from being detected by the drop detection hardware" "No effect,Ignored"
textline "                    "
bitfld.long 0x00 9. " IDM9  ,Disables CPUINT9 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 8. "  IDM8  ,Disables CPUINT8 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 7. "  IDM7  ,Disables CPUINT7 from being detected by the drop detection hardware" "No effect,Ignored"
textline "                    "
bitfld.long 0x00 6. " IDM6  ,Disables CPUINT6 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 5. "  IDM5  ,Disables CPUINT5 from being detected by the drop detection hardware" "No effect,Ignored"
bitfld.long 0x00 4. "  IDM4  ,Disables CPUINT4 from being detected by the drop detection hardware" "No effect,Ignored"
width 11.
group.long 0x140++0x07
line.long 0x00 "AEGMUX0,Advanced Event Generator Mux Registers"
hexmask.long.byte 0x00 24.--31. 1. " AEGSEL3 ,Advanced Event Generator Select"
hexmask.long.byte 0x00 16.--23. 1. "  AEGSEL2 ,Advanced Event Generator Select"
hexmask.long.byte 0x00 8.--15. 1. "  AEGSEL1 ,Advanced Event Generator Select"
hexmask.long.byte 0x00 0.--7. 1. "  AEGSEL0 ,Advanced Event Generator Select"
line.long 0x04 "AEGMUX1,Advanced Event Generator Mux Registers"
hexmask.long.byte 0x04 24.--31. 1. " AEGSEL7 ,Advanced Event Generator Select"
hexmask.long.byte 0x04 16.--23. 1. "  AEGSEL6 ,Advanced Event Generator Select"
hexmask.long.byte 0x04 8.--15. 1. "  AEGSEL5 ,Advanced Event Generator Select"
hexmask.long.byte 0x04 0.--7. 1. "  AEGSEL4 ,Advanced Event Generator Select"
width 0xb
tree.end
tree "Power-Down Controller"
width 8.
base d:0x01810000
group.long 0x00++0x3
line.long 0x00 "PDCCMD,Power-Down Controller Command Register"
bitfld.long 0x00 16. " MEGPD ,Power-down during IDLE" "Normal,Sleep mode"
width 0xb
tree.end
tree.end
AUTOINDENT.POP
endif
AUTOINDENT.ON center tree
sif (cpuis("AM2732-HSM"))
tree "CM4_ICFG (CM4 ICFG Module Registers)"
base ad:0xE0000000
group.long 0xE00++0x03
line.long 0x00 "CMX_ITM_TER,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xE40++0x03
line.long 0x00 "CMX_ITM_TPR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xE80++0x03
line.long 0x00 "CMX_ITM_TCR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xEF8++0x0B
line.long 0x00 "CMX_ITM_IWR,ITM Integration Write Register (privileged access only)"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
bitfld.long 0x00 0. "ATVALIDM,Write Only" "0,1"
line.long 0x04 "CMX_ITM_IRR,ITM Integration Read Register (privileged access only)"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
bitfld.long 0x04 0. "ATREADYM,Only use with integration test (on-chip connectivity test)" "0,1"
line.long 0x08 "CMX_ITM_IMCR,ITM Integration Mode Control Register (privileged access only)"
hexmask.long 0x08 1.--31. 1. "Reserved,Reserved"
bitfld.long 0x08 0. "INTEGRATION,Only use with integration test (on-chip connectivity test)" "0,1"
group.long 0xFB0++0x07
line.long 0x00 "CMX_LAR,https://static.docs.arm.com/ihi0029/e/coresight_v3_0_architecture_specification_IHI0029E.pdf?_ga=2.243641541.19024475.1571741864-233759942.1562499274"
line.long 0x04 "CMX_LSR,https://static.docs.arm.com/ihi0029/e/coresight_v3_0_architecture_specification_IHI0029E.pdf?_ga=2.243641541.19024475.1571741864-233759942.1562499274"
hexmask.long 0x04 3.--31. 1. "Reserved,Reserved"
bitfld.long 0x04 2. "nTT,This bit is always zero which indicates that the component implements a 32-bit LAR" "0,1"
bitfld.long 0x04 1. "SLK,This field is used to return the current software lock status" "0,1"
bitfld.long 0x04 0. "SLI,This field indicates whether a Software lock mechanism is implemented" "0,1"
rgroup.long 0xFD0++0x03
line.long 0x00 "CMX_ITM_PID4,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0xFE4++0x07
line.long 0x00 "CMX_ITM_PID1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_ITM_PID2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0xFF0++0x3B
line.long 0x00 "CMX_ITM_CID0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_ITM_CID1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_ITM_CID2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x0C "CMX_ITM_CID3,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x10 "CMX_DWT_CTRL,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x14 "CMX_DWT_CYCCNT,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x18 "CMX_DWT_CPICNT,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x1C "CMX_DWT_EXCCNT,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x20 "CMX_DWT_SLEEPCNT,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x24 "CMX_DWT_LSUCNT,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x28 "CMX_DWT_FOLDCNT,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x2C "CMX_DWT_PCSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x30 "CMX_DWT_COMP0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x34 "CMX_DWT_MASK0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x38 "CMX_DWT_FUNCTION0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0x1030++0x0B
line.long 0x00 "CMX_DWT_COMP1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_DWT_MASK1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_DWT_FUNCTION1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0x1040++0x0B
line.long 0x00 "CMX_DWT_COMP2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_DWT_MASK2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_DWT_FUNCTION2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0x1050++0x0B
line.long 0x00 "CMX_DWT_COMP3,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_DWT_MASK3,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_DWT_FUNCTION3,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x1FD0++0x03
line.long 0x00 "CMX_DWT_PID4,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x1FE4++0x07
line.long 0x00 "CMX_DWT_PID1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_DWT_PID2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x1FF0++0x1B
line.long 0x00 "CMX_DWT_CID0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_DWT_CID1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_DWT_CID2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x0C "CMX_DWT_CID3,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x10 "CMX_FP_CTRL,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x14 "CMX_FP_REMAP,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x18 "CMX_FP_COMP0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x2FD0++0x03
line.long 0x00 "CMX_FP_PID4,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x2FE4++0x07
line.long 0x00 "CMX_FP_PID1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_FP_PID2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x2FF0++0x0F
line.long 0x00 "CMX_FP_CID0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_FP_CID1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_FP_CID2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x0C "CMX_FP_CID3,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xE008++0x03
line.long 0x00 "CMX_ACTLR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xE010++0x0F
line.long 0x00 "CMX_STCSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_STRVR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_STCVR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x0C "CMX_STCR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0xED00++0x17
line.long 0x00 "CMX_CPUID,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_ICSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_VTOR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x0C "CMX_AIRCR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x10 "CMX_SCR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x14 "CMX_CCR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xED24++0x2F
line.long 0x00 "CMX_SHCSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_CFSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_HFSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x0C "CMX_DFSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x10 "CMX_MMFAR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x14 "CMX_BFAR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x18 "CMX_AFSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x1C "CMX_ID_PFR0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x20 "CMX_ID_PFR1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x24 "CMX_ID_DFR0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x28 "CMX_ID_AFR0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x2C "CMX_ID_MMFR0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0xED60++0x13
line.long 0x00 "CMX_ID_ISAR0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_ID_ISAR1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_ID_ISAR2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x0C "CMX_ID_ISAR3,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x10 "CMX_ID_ISAR4,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xED88++0x03
line.long 0x00 "CMX_CPACR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xEDF0++0x0F
line.long 0x00 "CMX_DHCSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_DCRSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_DCRDR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x0C "CMX_DEMCR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xEF00++0x03
line.long 0x00 "CMX_STIR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x40000++0x07
line.long 0x00 "CMX_TPIU_SSPSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_TPIU_CSPSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0x40010++0x03
line.long 0x00 "CMX_TPIU_ACPR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0x400F0++0x03
line.long 0x00 "CMX_TPIU_SPPR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x40300++0x0B
line.long 0x00 "CMX_TPIU_FFSR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_TPIU_FFCR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_TPIU_FSCR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x40EE8++0x0B
line.long 0x00 "CMX_TPIU_TRIGGER,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_TPIU_FIFO_DATA0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_TPIU_ITATBCTR2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x40EF8++0x0B
line.long 0x00 "CMX_TPIU_ITATBCTR0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_TPIU_FIFO_DATA1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_TPIU_ITCTRL,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0x40FA0++0x07
line.long 0x00 "CMX_TPIU_CLAIMSET,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_TPIU_CLAIMCLR,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x40FC8++0x03
line.long 0x00 "CMX_TPIU_DEVID,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x40FD0++0x03
line.long 0x00 "CMX_TPIU_PID4,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x40FE0++0x0B
line.long 0x00 "CMX_TPIU_PID0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_TPIU_PID1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_TPIU_PID2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x40FF0++0x03
line.long 0x00 "CMX_TPIU_CID0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0x40FFC++0x03
line.long 0x00 "CMX_TPIU_CID3,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xFF000++0x1B
line.long 0x00 "CMX_SCS,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_DWT,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_FPB,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x0C "CMX_ITM,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x10 "CMX_TPIU,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x14 "CMX_ETM,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x18 "CMX_ENDMARKER,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
group.long 0xFFFCC++0x07
line.long 0x00 "CMX_SYSACCESS,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_PeripheralID4,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
rgroup.long 0xFFFE0++0x1F
line.long 0x00 "CMX_PeripheralID0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x04 "CMX_PeripheralID1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x08 "CMX_PeripheralID2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x0C "CMX_PeripheralID3,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x10 "CMX_ComponentID0,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x14 "CMX_ComponentID1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x18 "CMX_ComponentID2,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
line.long 0x1C "CMX_ComponentID3,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
rgroup.long ($2+0x40FF4)++0x03
line.long 0x00 "CMX_TPIU_CID$1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
repeat.end
repeat 4. (list 5. 6. 7. 3. )(list 0x00 0x04 0x08 0x18 )
rgroup.long ($2+0x40FD4)++0x03
line.long 0x00 "CMX_TPIU_PID$1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
repeat.end
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
rgroup.long ($2+0xED54)++0x03
line.long 0x00 "CMX_ID_MMFR$1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
repeat.end
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
group.long ($2+0xED18)++0x03
line.long 0x00 "CMX_SHPR$1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
repeat.end
repeat 5. (list 5. 6. 7. 0. 3. )(list 0x00 0x04 0x08 0x0C 0x18 )
rgroup.long ($2+0x2FD4)++0x03
line.long 0x00 "CMX_FP_PID$1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
repeat.end
repeat 7. (list 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 )
group.long ($2+0x200C)++0x03
line.long 0x00 "CMX_FP_COMP$1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
repeat.end
repeat 5. (list 5. 6. 7. 0. 3. )(list 0x00 0x04 0x08 0x0C 0x18 )
rgroup.long ($2+0x1FD4)++0x03
line.long 0x00 "CMX_DWT_PID$1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
repeat.end
repeat 5. (list 5. 6. 7. 0. 3. )(list 0x00 0x04 0x08 0x0C 0x18 )
rgroup.long ($2+0xFD4)++0x03
line.long 0x00 "CMX_ITM_PID$1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
repeat.end
repeat 2. (list 0. 31. )(list 0x00 0x7C )
group.long ($2+0x00)++0x03
line.long 0x00 "CMX_ITM_STIM$1,http://infocenter.arm.com/help/topic/com.arm.doc.ddi0439b/DDI0439B_cortex_m4_r0p0_trm.pdf"
repeat.end
width 0x0B
tree.end
tree "DSS_CBUFF (DSS CBUFF Module Registers)"
base ad:0x56040000
group.long 0x00++0x1B
line.long 0x00 "CONFIG_REG_0,Basic Config register"
bitfld.long 0x00 28.--31. "dbussel,TI Internal feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 27. "cswcrst,CBUFF controller SW Reset" "RELEASE RESET for CBUFF Controller,RESET the CBUFF Controller"
newline
bitfld.long 0x00 26. "cswlrst,TI Internal Feature" "RELEASE RESET,RESET the FSM"
newline
bitfld.long 0x00 25. "CFG_FRAME_START_TRIG,SW Trigger generation : Write 1 to this bit to generate a Frame Start SW Trigger" "0,1"
newline
bitfld.long 0x00 24. "CFG_CHIRP_AVAIL_TRIG,SW Trigger generation : Write 1 to this bit to generate a Chirp Available SW Trigger" "0,1"
newline
bitfld.long 0x00 20.--23. "CFG_VBUSP_BURST_EN,TI Internal Feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "dbusen,TC2 Mode selection" "Normal,When in TC2 mode.."
newline
bitfld.long 0x00 18. "ccfwpen,TI Internal Feature" "Use the fifo_free_words directly from CSI2 by..,Process the fifo_free_words and use it by.."
newline
bitfld.long 0x00 16.--17. "cvc3en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 3 is..,A VSYNC End packet on Virtual Channel 3 is..,A VSYNC Start packet on Virtual Channel 3 is.."
newline
bitfld.long 0x00 14.--15. "cvc2en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 2 is..,A VSYNC End packet on Virtual Channel 2 is..,A VSYNC Start packet on Virtual Channel 2 is.."
newline
bitfld.long 0x00 12.--13. "cvc1en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 1 is..,A VSYNC End packet on Virtual Channel 1 is..,A VSYNC Start packet on Virtual Channel 1 is.."
newline
bitfld.long 0x00 10.--11. "cvc0en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 0 is..,A VSYNC End packet on Virtual Channel 0 is..,A VSYNC Start packet on Virtual Channel 0 is.."
newline
bitfld.long 0x00 9. "crdthsel,TI Internal Feature" "The read threshold is selected based on the..,The read threshold is selected based on the Read.."
newline
bitfld.long 0x00 8. "ccfwlen,TI Internal Feature" "0,1"
newline
rbitfld.long 0x00 4.--7. "NU1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "CFG_SW_TRIG_EN,Select Chirp Available Trigger Source" "Chirp Available trigger will be generated by HW,Chirp Available trigger will be generated by SW"
newline
bitfld.long 0x00 2. "cftrigen,Select Frame Start Trigger Source" "Frame trigger will be generated by HW,Frame trigger will be generated by SW"
newline
bitfld.long 0x00 1. "CFG_ECC_EN," "0,1"
newline
bitfld.long 0x00 0. "CFG_1LVDS_0CSI," "0,1"
line.long 0x04 "CFG_SPHDR_ADDRESS,Short Packet Header Address"
line.long 0x08 "CFG_CMD_HSVAL,HSYNC Value"
line.long 0x0C "CFG_CMD_HEVAL,HEND Value"
line.long 0x10 "CFG_CMD_VSVAL,VSYNC Value"
line.long 0x14 "CFG_CMD_VEVAL,VEND Value"
line.long 0x18 "CFG_LPHDR_ADDRESS,Long Packet Address"
group.long 0x20++0x1D3
line.long 0x00 "CFG_CHIRPS_PER_FRAME,Number of Chirps per Frame"
line.long 0x04 "CFG_FIFO_FREE_THRESHOLD,CSI2 FIFO threshold for transferring data from CBUFF to CSI2"
hexmask.long.byte 0x04 24.--31. 1. "CFG_FIFO_FREE_THRESHOLD3,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO3 in the CSI Protocol engine"
newline
hexmask.long.byte 0x04 16.--23. 1. "CFG_FIFO_FREE_THRESHOLD2,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO2 in the CSI Protocol engine"
newline
hexmask.long.byte 0x04 8.--15. 1. "CFG_FIFO_FREE_THRESHOLD1,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO1 in the CSI Protocol engine"
newline
hexmask.long.byte 0x04 0.--7. 1. "CFG_FIFO_FREE_THRESHOLD0,CSI2 only Programming : Configure the threshold used to fill the FIFO0 in the CSI Protocol engine"
line.long 0x08 "CFG_LPPYLD_ADDRESS,Long payload Address"
line.long 0x0C "CFG_DELAY_CONFIG,Delay Config Registers"
hexmask.long.byte 0x0C 24.--31. 1. "NU,"
newline
hexmask.long.byte 0x0C 16.--23. 1. "CFG_DATA_WR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Long packet Payload"
newline
hexmask.long.byte 0x0C 8.--15. 1. "CFG_LPHDR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Long packet Header"
newline
hexmask.long.byte 0x0C 0.--7. 1. "CFG_SPHDR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Short packet"
line.long 0x10 "CFG_DATA_LL0,Payload Description : Linked list entry 0"
bitfld.long 0x10 31. "LL0_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10 30. "LL0_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10 29. "LL0_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10 28. "LL0_CRC_EN," "0,1"
newline
bitfld.long 0x10 27. "LL0_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x10 26. "LL0_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x10 23.--25. "LL0_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 9.--22. 1. "LL0_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x10 8. "LL0_FMT_IN," "0,1"
newline
bitfld.long 0x10 7. "LL0_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x10 5.--6. "LL0_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x10 3.--4. "LL0_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x10 2. "LL0_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x10 1. "LL0_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x10 0. "LL0_VALID," "0,1"
line.long 0x14 "CFG_DATA_LL0_LPHDR_VAL,Payload Description : Linked list entry 0"
line.long 0x18 "CFG_DATA_LL0_THRESHOLD,"
hexmask.long.word 0x18 19.--31. 1. "NU3,"
newline
bitfld.long 0x18 16.--18. "ll0dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x18 15. "NU2," "0,1"
newline
hexmask.long.byte 0x18 8.--14. 1. "LL0_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x18 7. "NU1," "0,1"
newline
hexmask.long.byte 0x18 0.--6. 1. "LL0_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x1C "CFG_DATA_LL1,"
bitfld.long 0x1C 31. "LL1_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x1C 30. "LL1_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x1C 29. "LL1_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x1C 28. "LL1_CRC_EN," "0,1"
newline
bitfld.long 0x1C 27. "LL1_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x1C 26. "LL1_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x1C 23.--25. "LL1_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 9.--22. 1. "LL1_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x1C 8. "LL1_FMT_IN," "0,1"
newline
bitfld.long 0x1C 7. "LL1_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x1C 5.--6. "LL1_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x1C 3.--4. "LL1_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x1C 2. "LL1_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x1C 1. "LL1_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x1C 0. "LL1_VALID," "0,1"
line.long 0x20 "CFG_DATA_LL1_LPHDR_VAL,"
line.long 0x24 "CFG_DATA_LL1_THRESHOLD,"
hexmask.long.word 0x24 19.--31. 1. "NU3,"
newline
bitfld.long 0x24 16.--18. "ll1dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x24 15. "NU2," "0,1"
newline
hexmask.long.byte 0x24 8.--14. 1. "LL1_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x24 7. "NU1," "0,1"
newline
hexmask.long.byte 0x24 0.--6. 1. "LL1_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x28 "CFG_DATA_LL2,"
bitfld.long 0x28 31. "LL2_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x28 30. "LL2_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x28 29. "LL2_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x28 28. "LL2_CRC_EN," "0,1"
newline
bitfld.long 0x28 27. "LL2_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x28 26. "LL2_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x28 23.--25. "LL2_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 9.--22. 1. "LL2_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x28 8. "LL2_FMT_IN," "0,1"
newline
bitfld.long 0x28 7. "LL2_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x28 5.--6. "LL2_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x28 3.--4. "LL2_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x28 2. "LL2_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x28 1. "LL2_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x28 0. "LL2_VALID," "0,1"
line.long 0x2C "CFG_DATA_LL2_LPHDR_VAL,"
line.long 0x30 "CFG_DATA_LL2_THRESHOLD,"
hexmask.long.word 0x30 19.--31. 1. "NU3,"
newline
bitfld.long 0x30 16.--18. "ll2dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x30 15. "NU2," "0,1"
newline
hexmask.long.byte 0x30 8.--14. 1. "LL2_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x30 7. "NU1," "0,1"
newline
hexmask.long.byte 0x30 0.--6. 1. "LL2_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x34 "CFG_DATA_LL3,"
bitfld.long 0x34 31. "LL3_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x34 30. "LL3_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x34 29. "LL3_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x34 28. "LL3_CRC_EN," "0,1"
newline
bitfld.long 0x34 27. "LL3_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x34 26. "LL3_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x34 23.--25. "LL3_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 9.--22. 1. "LL3_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x34 8. "LL3_FMT_IN," "0,1"
newline
bitfld.long 0x34 7. "LL3_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x34 5.--6. "LL3_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x34 3.--4. "LL3_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x34 2. "LL3_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x34 1. "LL3_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x34 0. "LL3_VALID," "0,1"
line.long 0x38 "CFG_DATA_LL3_LPHDR_VAL,"
line.long 0x3C "CFG_DATA_LL3_THRESHOLD,"
hexmask.long.word 0x3C 19.--31. 1. "NU3,"
newline
bitfld.long 0x3C 16.--18. "ll3dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x3C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x3C 8.--14. 1. "LL3_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x3C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x3C 0.--6. 1. "LL3_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x40 "CFG_DATA_LL4,"
bitfld.long 0x40 31. "LL4_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x40 30. "LL4_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x40 29. "LL4_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x40 28. "LL4_CRC_EN," "0,1"
newline
bitfld.long 0x40 27. "LL4_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x40 26. "LL4_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x40 23.--25. "LL4_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x40 9.--22. 1. "LL4_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x40 8. "LL4_FMT_IN," "0,1"
newline
bitfld.long 0x40 7. "LL4_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x40 5.--6. "LL4_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x40 3.--4. "LL4_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x40 2. "LL4_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x40 1. "LL4_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x40 0. "LL4_VALID," "0,1"
line.long 0x44 "CFG_DATA_LL4_LPHDR_VAL,"
line.long 0x48 "CFG_DATA_LL4_THRESHOLD,"
hexmask.long.word 0x48 19.--31. 1. "NU3,"
newline
bitfld.long 0x48 16.--18. "ll4dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x48 15. "NU2," "0,1"
newline
hexmask.long.byte 0x48 8.--14. 1. "LL4_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x48 7. "NU1," "0,1"
newline
hexmask.long.byte 0x48 0.--6. 1. "LL4_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x4C "CFG_DATA_LL5,"
bitfld.long 0x4C 31. "LL5_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x4C 30. "LL5_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x4C 29. "LL5_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x4C 28. "LL5_CRC_EN," "0,1"
newline
bitfld.long 0x4C 27. "LL5_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x4C 26. "LL5_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x4C 23.--25. "LL5_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x4C 9.--22. 1. "LL5_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x4C 8. "LL5_FMT_IN," "0,1"
newline
bitfld.long 0x4C 7. "LL5_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x4C 5.--6. "LL5_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x4C 3.--4. "LL5_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x4C 2. "LL5_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x4C 1. "LL5_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x4C 0. "LL5_VALID," "0,1"
line.long 0x50 "CFG_DATA_LL5_LPHDR_VAL,"
line.long 0x54 "CFG_DATA_LL5_THRESHOLD,"
hexmask.long.word 0x54 19.--31. 1. "NU3,"
newline
bitfld.long 0x54 16.--18. "ll5dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x54 15. "NU2," "0,1"
newline
hexmask.long.byte 0x54 8.--14. 1. "LL5_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x54 7. "NU1," "0,1"
newline
hexmask.long.byte 0x54 0.--6. 1. "LL5_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x58 "CFG_DATA_LL6,"
bitfld.long 0x58 31. "LL6_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x58 30. "LL6_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x58 29. "LL6_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x58 28. "LL6_CRC_EN," "0,1"
newline
bitfld.long 0x58 27. "LL6_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x58 26. "LL6_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x58 23.--25. "LL6_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x58 9.--22. 1. "LL6_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x58 8. "LL6_FMT_IN," "0,1"
newline
bitfld.long 0x58 7. "LL6_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x58 5.--6. "LL6_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x58 3.--4. "LL6_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x58 2. "LL6_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x58 1. "LL6_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x58 0. "LL6_VALID," "0,1"
line.long 0x5C "CFG_DATA_LL6_LPHDR_VAL,"
line.long 0x60 "CFG_DATA_LL6_THRESHOLD,"
hexmask.long.word 0x60 19.--31. 1. "NU3,"
newline
bitfld.long 0x60 16.--18. "ll6dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x60 15. "NU2," "0,1"
newline
hexmask.long.byte 0x60 8.--14. 1. "LL6_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x60 7. "NU1," "0,1"
newline
hexmask.long.byte 0x60 0.--6. 1. "LL6_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x64 "CFG_DATA_LL7,"
bitfld.long 0x64 31. "LL7_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x64 30. "LL7_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x64 29. "LL7_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x64 28. "LL7_CRC_EN," "0,1"
newline
bitfld.long 0x64 27. "LL7_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x64 26. "LL7_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x64 23.--25. "LL7_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x64 9.--22. 1. "LL7_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x64 8. "LL7_FMT_IN," "0,1"
newline
bitfld.long 0x64 7. "LL7_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x64 5.--6. "LL7_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x64 3.--4. "LL7_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x64 2. "LL7_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x64 1. "LL7_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x64 0. "LL7_VALID," "0,1"
line.long 0x68 "CFG_DATA_LL7_LPHDR_VAL,"
line.long 0x6C "CFG_DATA_LL7_THRESHOLD,"
hexmask.long.word 0x6C 19.--31. 1. "NU3,"
newline
bitfld.long 0x6C 16.--18. "ll7dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x6C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x6C 8.--14. 1. "LL7_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x6C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x6C 0.--6. 1. "LL7_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x70 "CFG_DATA_LL8,"
bitfld.long 0x70 31. "LL8_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x70 30. "LL8_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x70 29. "LL8_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x70 28. "LL8_CRC_EN," "0,1"
newline
bitfld.long 0x70 27. "LL8_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x70 26. "LL8_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x70 23.--25. "LL8_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x70 9.--22. 1. "LL8_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x70 8. "LL8_FMT_IN," "0,1"
newline
bitfld.long 0x70 7. "LL8_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x70 5.--6. "LL8_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x70 3.--4. "LL8_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x70 2. "LL8_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x70 1. "LL8_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x70 0. "LL8_VALID," "0,1"
line.long 0x74 "CFG_DATA_LL8_LPHDR_VAL,"
line.long 0x78 "CFG_DATA_LL8_THRESHOLD,"
hexmask.long.word 0x78 19.--31. 1. "NU3,"
newline
bitfld.long 0x78 16.--18. "ll8dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x78 15. "NU2," "0,1"
newline
hexmask.long.byte 0x78 8.--14. 1. "LL8_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x78 7. "NU1," "0,1"
newline
hexmask.long.byte 0x78 0.--6. 1. "LL8_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x7C "CFG_DATA_LL9,"
bitfld.long 0x7C 31. "LL9_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x7C 30. "LL9_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x7C 29. "LL9_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x7C 28. "LL9_CRC_EN," "0,1"
newline
bitfld.long 0x7C 27. "LL9_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x7C 26. "LL9_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x7C 23.--25. "LL9_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x7C 9.--22. 1. "LL9_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x7C 8. "LL9_FMT_IN," "0,1"
newline
bitfld.long 0x7C 7. "LL9_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x7C 5.--6. "LL9_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x7C 3.--4. "LL9_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x7C 2. "LL9_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x7C 1. "LL9_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x7C 0. "LL9_VALID," "0,1"
line.long 0x80 "CFG_DATA_LL9_LPHDR_VAL,"
line.long 0x84 "CFG_DATA_LL9_THRESHOLD,"
hexmask.long.word 0x84 19.--31. 1. "NU3,"
newline
bitfld.long 0x84 16.--18. "ll9dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x84 15. "NU2," "0,1"
newline
hexmask.long.byte 0x84 8.--14. 1. "LL9_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x84 7. "NU1," "0,1"
newline
hexmask.long.byte 0x84 0.--6. 1. "LL9_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x88 "CFG_DATA_LL10,"
bitfld.long 0x88 31. "LL10_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x88 30. "LL10_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x88 29. "LL10_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x88 28. "LL10_CRC_EN," "0,1"
newline
bitfld.long 0x88 27. "LL10_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x88 26. "LL10_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x88 23.--25. "LL10_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x88 9.--22. 1. "LL10_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x88 8. "LL10_FMT_IN," "0,1"
newline
bitfld.long 0x88 7. "LL10_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x88 5.--6. "LL10_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x88 3.--4. "LL10_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x88 2. "LL10_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x88 1. "LL10_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x88 0. "LL10_VALID," "0,1"
line.long 0x8C "CFG_DATA_LL10_LPHDR_VAL,"
line.long 0x90 "CFG_DATA_LL10_THRESHOLD,"
hexmask.long.word 0x90 19.--31. 1. "NU3,"
newline
bitfld.long 0x90 16.--18. "ll10dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x90 15. "NU2," "0,1"
newline
hexmask.long.byte 0x90 8.--14. 1. "LL10_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x90 7. "NU1," "0,1"
newline
hexmask.long.byte 0x90 0.--6. 1. "LL10_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x94 "CFG_DATA_LL11,"
bitfld.long 0x94 31. "LL11_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x94 30. "LL11_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x94 29. "LL11_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x94 28. "LL11_CRC_EN," "0,1"
newline
bitfld.long 0x94 27. "LL11_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x94 26. "LL11_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x94 23.--25. "LL11_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x94 9.--22. 1. "LL11_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x94 8. "LL11_FMT_IN," "0,1"
newline
bitfld.long 0x94 7. "LL11_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x94 5.--6. "LL11_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x94 3.--4. "LL11_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x94 2. "LL11_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x94 1. "LL11_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x94 0. "LL11_VALID," "0,1"
line.long 0x98 "CFG_DATA_LL11_LPHDR_VAL,"
line.long 0x9C "CFG_DATA_LL11_THRESHOLD,"
hexmask.long.word 0x9C 19.--31. 1. "NU3,"
newline
bitfld.long 0x9C 16.--18. "ll11dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x9C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x9C 8.--14. 1. "LL11_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x9C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x9C 0.--6. 1. "LL11_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xA0 "CFG_DATA_LL12,"
bitfld.long 0xA0 31. "LL12_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xA0 30. "LL12_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xA0 29. "LL12_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xA0 28. "LL12_CRC_EN," "0,1"
newline
bitfld.long 0xA0 27. "LL12_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xA0 26. "LL12_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xA0 23.--25. "LL12_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xA0 9.--22. 1. "LL12_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xA0 8. "LL12_FMT_IN," "0,1"
newline
bitfld.long 0xA0 7. "LL12_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xA0 5.--6. "LL12_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xA0 3.--4. "LL12_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xA0 2. "LL12_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xA0 1. "LL12_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xA0 0. "LL12_VALID," "0,1"
line.long 0xA4 "CFG_DATA_LL12_LPHDR_VAL,"
line.long 0xA8 "CFG_DATA_LL12_THRESHOLD,"
hexmask.long.word 0xA8 19.--31. 1. "NU3,"
newline
bitfld.long 0xA8 16.--18. "ll12dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xA8 15. "NU2," "0,1"
newline
hexmask.long.byte 0xA8 8.--14. 1. "LL12_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xA8 7. "NU1," "0,1"
newline
hexmask.long.byte 0xA8 0.--6. 1. "LL12_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xAC "CFG_DATA_LL13,"
bitfld.long 0xAC 31. "LL13_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xAC 30. "LL13_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xAC 29. "LL13_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xAC 28. "LL13_CRC_EN," "0,1"
newline
bitfld.long 0xAC 27. "LL13_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xAC 26. "LL13_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xAC 23.--25. "LL13_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xAC 9.--22. 1. "LL13_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xAC 8. "LL13_FMT_IN," "0,1"
newline
bitfld.long 0xAC 7. "LL13_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xAC 5.--6. "LL13_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xAC 3.--4. "LL13_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xAC 2. "LL13_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xAC 1. "LL13_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xAC 0. "LL13_VALID," "0,1"
line.long 0xB0 "CFG_DATA_LL13_LPHDR_VAL,"
line.long 0xB4 "CFG_DATA_LL13_THRESHOLD,"
hexmask.long.word 0xB4 19.--31. 1. "NU3,"
newline
bitfld.long 0xB4 16.--18. "ll13dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xB4 15. "NU2," "0,1"
newline
hexmask.long.byte 0xB4 8.--14. 1. "LL13_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xB4 7. "NU1," "0,1"
newline
hexmask.long.byte 0xB4 0.--6. 1. "LL13_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xB8 "CFG_DATA_LL14,"
bitfld.long 0xB8 31. "LL14_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xB8 30. "LL14_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xB8 29. "LL14_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xB8 28. "LL14_CRC_EN," "0,1"
newline
bitfld.long 0xB8 27. "LL14_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xB8 26. "LL14_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xB8 23.--25. "LL14_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xB8 9.--22. 1. "LL14_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xB8 8. "LL14_FMT_IN," "0,1"
newline
bitfld.long 0xB8 7. "LL14_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xB8 5.--6. "LL14_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xB8 3.--4. "LL14_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xB8 2. "LL14_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xB8 1. "LL14_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xB8 0. "LL14_VALID," "0,1"
line.long 0xBC "CFG_DATA_LL14_LPHDR_VAL,"
line.long 0xC0 "CFG_DATA_LL14_THRESHOLD,"
hexmask.long.word 0xC0 19.--31. 1. "NU3,"
newline
bitfld.long 0xC0 16.--18. "ll14dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xC0 15. "NU2," "0,1"
newline
hexmask.long.byte 0xC0 8.--14. 1. "LL14_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xC0 7. "NU1," "0,1"
newline
hexmask.long.byte 0xC0 0.--6. 1. "LL14_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xC4 "CFG_DATA_LL15,"
bitfld.long 0xC4 31. "LL15_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xC4 30. "LL15_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xC4 29. "LL15_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xC4 28. "LL15_CRC_EN," "0,1"
newline
bitfld.long 0xC4 27. "LL15_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xC4 26. "LL15_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xC4 23.--25. "LL15_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xC4 9.--22. 1. "LL15_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xC4 8. "LL15_FMT_IN," "0,1"
newline
bitfld.long 0xC4 7. "LL15_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xC4 5.--6. "LL15_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xC4 3.--4. "LL15_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xC4 2. "LL15_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xC4 1. "LL15_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xC4 0. "LL15_VALID," "0,1"
line.long 0xC8 "CFG_DATA_LL15_LPHDR_VAL,"
line.long 0xCC "CFG_DATA_LL15_THRESHOLD,"
hexmask.long.word 0xCC 19.--31. 1. "NU3,"
newline
bitfld.long 0xCC 16.--18. "ll15dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xCC 15. "NU2," "0,1"
newline
hexmask.long.byte 0xCC 8.--14. 1. "LL15_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xCC 7. "NU1," "0,1"
newline
hexmask.long.byte 0xCC 0.--6. 1. "LL15_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xD0 "CFG_DATA_LL16,"
bitfld.long 0xD0 31. "LL16_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xD0 30. "LL16_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xD0 29. "LL16_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xD0 28. "LL16_CRC_EN," "0,1"
newline
bitfld.long 0xD0 27. "LL16_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xD0 26. "LL16_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xD0 23.--25. "LL16_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xD0 9.--22. 1. "LL16_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xD0 8. "LL16_FMT_IN," "0,1"
newline
bitfld.long 0xD0 7. "LL16_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xD0 5.--6. "LL16_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xD0 3.--4. "LL16_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xD0 2. "LL16_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xD0 1. "LL16_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xD0 0. "LL16_VALID," "0,1"
line.long 0xD4 "CFG_DATA_LL16_LPHDR_VAL,"
line.long 0xD8 "CFG_DATA_LL16_THRESHOLD,"
hexmask.long.word 0xD8 19.--31. 1. "NU3,"
newline
bitfld.long 0xD8 16.--18. "ll16dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xD8 15. "NU2," "0,1"
newline
hexmask.long.byte 0xD8 8.--14. 1. "LL16_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xD8 7. "NU1," "0,1"
newline
hexmask.long.byte 0xD8 0.--6. 1. "LL16_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xDC "CFG_DATA_LL17,"
bitfld.long 0xDC 31. "LL17_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xDC 30. "LL17_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xDC 29. "LL17_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xDC 28. "LL17_CRC_EN," "0,1"
newline
bitfld.long 0xDC 27. "LL17_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xDC 26. "LL17_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xDC 23.--25. "LL17_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xDC 9.--22. 1. "LL17_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xDC 8. "LL17_FMT_IN," "0,1"
newline
bitfld.long 0xDC 7. "LL17_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xDC 5.--6. "LL17_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xDC 3.--4. "LL17_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xDC 2. "LL17_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xDC 1. "LL17_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xDC 0. "LL17_VALID," "0,1"
line.long 0xE0 "CFG_DATA_LL17_LPHDR_VAL,"
line.long 0xE4 "CFG_DATA_LL17_THRESHOLD,"
hexmask.long.word 0xE4 19.--31. 1. "NU3,"
newline
bitfld.long 0xE4 16.--18. "ll17dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xE4 15. "NU2," "0,1"
newline
hexmask.long.byte 0xE4 8.--14. 1. "LL17_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xE4 7. "NU1," "0,1"
newline
hexmask.long.byte 0xE4 0.--6. 1. "LL17_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xE8 "CFG_DATA_LL18,"
bitfld.long 0xE8 31. "LL18_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xE8 30. "LL18_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xE8 29. "LL18_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xE8 28. "LL18_CRC_EN," "0,1"
newline
bitfld.long 0xE8 27. "LL18_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xE8 26. "LL18_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xE8 23.--25. "LL18_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xE8 9.--22. 1. "LL18_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xE8 8. "LL18_FMT_IN," "0,1"
newline
bitfld.long 0xE8 7. "LL18_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xE8 5.--6. "LL18_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xE8 3.--4. "LL18_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xE8 2. "LL18_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xE8 1. "LL18_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xE8 0. "LL18_VALID," "0,1"
line.long 0xEC "CFG_DATA_LL18_LPHDR_VAL,"
line.long 0xF0 "CFG_DATA_LL18_THRESHOLD,"
hexmask.long.word 0xF0 19.--31. 1. "NU3,"
newline
bitfld.long 0xF0 16.--18. "ll18dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xF0 15. "NU2," "0,1"
newline
hexmask.long.byte 0xF0 8.--14. 1. "LL18_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xF0 7. "NU1," "0,1"
newline
hexmask.long.byte 0xF0 0.--6. 1. "LL18_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xF4 "CFG_DATA_LL19,"
bitfld.long 0xF4 31. "LL19_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xF4 30. "LL19_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xF4 29. "LL19_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xF4 28. "LL19_CRC_EN," "0,1"
newline
bitfld.long 0xF4 27. "LL19_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xF4 26. "LL19_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xF4 23.--25. "LL19_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xF4 9.--22. 1. "LL19_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xF4 8. "LL19_FMT_IN," "0,1"
newline
bitfld.long 0xF4 7. "LL19_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xF4 5.--6. "LL19_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xF4 3.--4. "LL19_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xF4 2. "LL19_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xF4 1. "LL19_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xF4 0. "LL19_VALID," "0,1"
line.long 0xF8 "CFG_DATA_LL19_LPHDR_VAL,"
line.long 0xFC "CFG_DATA_LL19_THRESHOLD,"
hexmask.long.word 0xFC 19.--31. 1. "NU3,"
newline
bitfld.long 0xFC 16.--18. "ll19dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xFC 15. "NU2," "0,1"
newline
hexmask.long.byte 0xFC 8.--14. 1. "LL19_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xFC 7. "NU1," "0,1"
newline
hexmask.long.byte 0xFC 0.--6. 1. "LL19_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x100 "CFG_DATA_LL20,"
bitfld.long 0x100 31. "LL20_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x100 30. "LL20_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x100 29. "LL20_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x100 28. "LL20_CRC_EN," "0,1"
newline
bitfld.long 0x100 27. "LL20_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x100 26. "LL20_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x100 23.--25. "LL20_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x100 9.--22. 1. "LL20_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x100 8. "LL20_FMT_IN," "0,1"
newline
bitfld.long 0x100 7. "LL20_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x100 5.--6. "LL20_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x100 3.--4. "LL20_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x100 2. "LL20_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x100 1. "LL20_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x100 0. "LL20_VALID," "0,1"
line.long 0x104 "CFG_DATA_LL20_LPHDR_VAL,"
line.long 0x108 "CFG_DATA_LL20_THRESHOLD,"
hexmask.long.word 0x108 19.--31. 1. "NU3,"
newline
bitfld.long 0x108 16.--18. "ll20dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x108 15. "NU2," "0,1"
newline
hexmask.long.byte 0x108 8.--14. 1. "LL20_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x108 7. "NU1," "0,1"
newline
hexmask.long.byte 0x108 0.--6. 1. "LL20_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x10C "CFG_DATA_LL21,"
bitfld.long 0x10C 31. "LL21_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10C 30. "LL21_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10C 29. "LL21_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10C 28. "LL21_CRC_EN," "0,1"
newline
bitfld.long 0x10C 27. "LL21_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x10C 26. "LL21_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x10C 23.--25. "LL21_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10C 9.--22. 1. "LL21_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x10C 8. "LL21_FMT_IN," "0,1"
newline
bitfld.long 0x10C 7. "LL21_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x10C 5.--6. "LL21_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x10C 3.--4. "LL21_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x10C 2. "LL21_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x10C 1. "LL21_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x10C 0. "LL21_VALID," "0,1"
line.long 0x110 "CFG_DATA_LL21_LPHDR_VAL,"
line.long 0x114 "CFG_DATA_LL21_THRESHOLD,"
hexmask.long.word 0x114 19.--31. 1. "NU3,"
newline
bitfld.long 0x114 16.--18. "ll21dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x114 15. "NU2," "0,1"
newline
hexmask.long.byte 0x114 8.--14. 1. "LL21_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x114 7. "NU1," "0,1"
newline
hexmask.long.byte 0x114 0.--6. 1. "LL21_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x118 "CFG_DATA_LL22,"
bitfld.long 0x118 31. "LL22_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x118 30. "LL22_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x118 29. "LL22_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x118 28. "LL22_CRC_EN," "0,1"
newline
bitfld.long 0x118 27. "LL22_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x118 26. "LL22_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x118 23.--25. "LL22_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x118 9.--22. 1. "LL22_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x118 8. "LL22_FMT_IN," "0,1"
newline
bitfld.long 0x118 7. "LL22_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x118 5.--6. "LL22_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x118 3.--4. "LL22_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x118 2. "LL22_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x118 1. "LL22_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x118 0. "LL22_VALID," "0,1"
line.long 0x11C "CFG_DATA_LL22_LPHDR_VAL,"
line.long 0x120 "CFG_DATA_LL22_THRESHOLD,"
hexmask.long.word 0x120 19.--31. 1. "NU3,"
newline
bitfld.long 0x120 16.--18. "ll22dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x120 15. "NU2," "0,1"
newline
hexmask.long.byte 0x120 8.--14. 1. "LL22_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x120 7. "NU1," "0,1"
newline
hexmask.long.byte 0x120 0.--6. 1. "LL22_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x124 "CFG_DATA_LL23,"
bitfld.long 0x124 31. "LL23_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x124 30. "LL23_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x124 29. "LL23_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x124 28. "LL23_CRC_EN," "0,1"
newline
bitfld.long 0x124 27. "LL23_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x124 26. "LL23_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x124 23.--25. "LL23_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x124 9.--22. 1. "LL23_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x124 8. "LL23_FMT_IN," "0,1"
newline
bitfld.long 0x124 7. "LL23_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x124 5.--6. "LL23_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x124 3.--4. "LL23_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x124 2. "LL23_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x124 1. "LL23_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x124 0. "LL23_VALID," "0,1"
line.long 0x128 "CFG_DATA_LL23_LPHDR_VAL,"
line.long 0x12C "CFG_DATA_LL23_THRESHOLD,"
hexmask.long.word 0x12C 19.--31. 1. "NU3,"
newline
bitfld.long 0x12C 16.--18. "ll23dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x12C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x12C 8.--14. 1. "LL23_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x12C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x12C 0.--6. 1. "LL23_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x130 "CFG_DATA_LL24,"
bitfld.long 0x130 31. "LL24_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x130 30. "LL24_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x130 29. "LL24_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x130 28. "LL24_CRC_EN," "0,1"
newline
bitfld.long 0x130 27. "LL24_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x130 26. "LL24_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x130 23.--25. "LL24_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x130 9.--22. 1. "LL24_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x130 8. "LL24_FMT_IN," "0,1"
newline
bitfld.long 0x130 7. "LL24_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x130 5.--6. "LL24_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x130 3.--4. "LL24_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x130 2. "LL24_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x130 1. "LL24_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x130 0. "LL24_VALID," "0,1"
line.long 0x134 "CFG_DATA_LL24_LPHDR_VAL,"
line.long 0x138 "CFG_DATA_LL24_THRESHOLD,"
hexmask.long.word 0x138 19.--31. 1. "NU3,"
newline
bitfld.long 0x138 16.--18. "ll24dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x138 15. "NU2," "0,1"
newline
hexmask.long.byte 0x138 8.--14. 1. "LL24_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x138 7. "NU1," "0,1"
newline
hexmask.long.byte 0x138 0.--6. 1. "LL24_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x13C "CFG_DATA_LL25,"
bitfld.long 0x13C 31. "LL25_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x13C 30. "LL25_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x13C 29. "LL25_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x13C 28. "LL25_CRC_EN," "0,1"
newline
bitfld.long 0x13C 27. "LL25_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x13C 26. "LL25_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x13C 23.--25. "LL25_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x13C 9.--22. 1. "LL25_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x13C 8. "LL25_FMT_IN," "0,1"
newline
bitfld.long 0x13C 7. "LL25_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x13C 5.--6. "LL25_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x13C 3.--4. "LL25_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x13C 2. "LL25_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x13C 1. "LL25_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x13C 0. "LL25_VALID," "0,1"
line.long 0x140 "CFG_DATA_LL25_LPHDR_VAL,"
line.long 0x144 "CFG_DATA_LL25_THRESHOLD,"
hexmask.long.word 0x144 19.--31. 1. "NU3,"
newline
bitfld.long 0x144 16.--18. "ll25dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x144 15. "NU2," "0,1"
newline
hexmask.long.byte 0x144 8.--14. 1. "LL25_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x144 7. "NU1," "0,1"
newline
hexmask.long.byte 0x144 0.--6. 1. "LL25_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x148 "CFG_DATA_LL26,"
bitfld.long 0x148 31. "LL26_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x148 30. "LL26_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x148 29. "LL26_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x148 28. "LL26_CRC_EN," "0,1"
newline
bitfld.long 0x148 27. "LL26_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x148 26. "LL26_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x148 23.--25. "LL26_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x148 9.--22. 1. "LL26_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x148 8. "LL26_FMT_IN," "0,1"
newline
bitfld.long 0x148 7. "LL26_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x148 5.--6. "LL26_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x148 3.--4. "LL26_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x148 2. "LL26_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x148 1. "LL26_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x148 0. "LL26_VALID," "0,1"
line.long 0x14C "CFG_DATA_LL26_LPHDR_VAL,"
line.long 0x150 "CFG_DATA_LL26_THRESHOLD,"
hexmask.long.word 0x150 19.--31. 1. "NU3,"
newline
bitfld.long 0x150 16.--18. "ll26dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x150 15. "NU2," "0,1"
newline
hexmask.long.byte 0x150 8.--14. 1. "LL26_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x150 7. "NU1," "0,1"
newline
hexmask.long.byte 0x150 0.--6. 1. "LL26_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x154 "CFG_DATA_LL27,"
bitfld.long 0x154 31. "LL27_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x154 30. "LL27_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x154 29. "LL27_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x154 28. "LL27_CRC_EN," "0,1"
newline
bitfld.long 0x154 27. "LL27_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x154 26. "LL27_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x154 23.--25. "LL27_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x154 9.--22. 1. "LL27_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x154 8. "LL27_FMT_IN," "0,1"
newline
bitfld.long 0x154 7. "LL27_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x154 5.--6. "LL27_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x154 3.--4. "LL27_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x154 2. "LL27_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x154 1. "LL27_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x154 0. "LL27_VALID," "0,1"
line.long 0x158 "CFG_DATA_LL27_LPHDR_VAL,"
line.long 0x15C "CFG_DATA_LL27_THRESHOLD,"
hexmask.long.word 0x15C 19.--31. 1. "NU3,"
newline
bitfld.long 0x15C 16.--18. "ll27dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x15C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x15C 8.--14. 1. "LL27_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x15C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x15C 0.--6. 1. "LL27_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x160 "CFG_DATA_LL28,"
bitfld.long 0x160 31. "LL28_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x160 30. "LL28_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x160 29. "LL28_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x160 28. "LL28_CRC_EN," "0,1"
newline
bitfld.long 0x160 27. "LL28_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x160 26. "LL28_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x160 23.--25. "LL28_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x160 9.--22. 1. "LL28_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x160 8. "LL28_FMT_IN," "0,1"
newline
bitfld.long 0x160 7. "LL28_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x160 5.--6. "LL28_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x160 3.--4. "LL28_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x160 2. "LL28_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x160 1. "LL28_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x160 0. "LL28_VALID," "0,1"
line.long 0x164 "CFG_DATA_LL28_LPHDR_VAL,"
line.long 0x168 "CFG_DATA_LL28_THRESHOLD,"
hexmask.long.word 0x168 19.--31. 1. "NU3,"
newline
bitfld.long 0x168 16.--18. "ll28dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x168 15. "NU2," "0,1"
newline
hexmask.long.byte 0x168 8.--14. 1. "LL28_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x168 7. "NU1," "0,1"
newline
hexmask.long.byte 0x168 0.--6. 1. "LL28_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x16C "CFG_DATA_LL29,"
bitfld.long 0x16C 31. "LL29_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x16C 30. "LL29_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x16C 29. "LL29_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x16C 28. "LL29_CRC_EN," "0,1"
newline
bitfld.long 0x16C 27. "LL29_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x16C 26. "LL29_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x16C 23.--25. "LL29_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x16C 9.--22. 1. "LL29_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x16C 8. "LL29_FMT_IN," "0,1"
newline
bitfld.long 0x16C 7. "LL29_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x16C 5.--6. "LL29_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x16C 3.--4. "LL29_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x16C 2. "LL29_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x16C 1. "LL29_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x16C 0. "LL29_VALID," "0,1"
line.long 0x170 "CFG_DATA_LL29_LPHDR_VAL,"
line.long 0x174 "CFG_DATA_LL29_THRESHOLD,"
hexmask.long.word 0x174 19.--31. 1. "NU3,"
newline
bitfld.long 0x174 16.--18. "ll29dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x174 15. "NU2," "0,1"
newline
hexmask.long.byte 0x174 8.--14. 1. "LL29_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x174 7. "NU1," "0,1"
newline
hexmask.long.byte 0x174 0.--6. 1. "LL29_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x178 "CFG_DATA_LL30,"
bitfld.long 0x178 31. "LL30_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x178 30. "LL30_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x178 29. "LL30_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x178 28. "LL30_CRC_EN," "0,1"
newline
bitfld.long 0x178 27. "LL30_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x178 26. "LL30_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x178 23.--25. "LL30_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x178 9.--22. 1. "LL30_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x178 8. "LL30_FMT_IN," "0,1"
newline
bitfld.long 0x178 7. "LL30_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x178 5.--6. "LL30_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x178 3.--4. "LL30_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x178 2. "LL30_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x178 1. "LL30_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x178 0. "LL30_VALID," "0,1"
line.long 0x17C "CFG_DATA_LL30_LPHDR_VAL,"
line.long 0x180 "CFG_DATA_LL30_THRESHOLD,"
hexmask.long.word 0x180 19.--31. 1. "NU3,"
newline
bitfld.long 0x180 16.--18. "ll30dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x180 15. "NU2," "0,1"
newline
hexmask.long.byte 0x180 8.--14. 1. "LL30_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x180 7. "NU1," "0,1"
newline
hexmask.long.byte 0x180 0.--6. 1. "LL30_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x184 "CFG_DATA_LL31,"
bitfld.long 0x184 31. "LL31_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x184 30. "LL31_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x184 29. "LL31_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x184 28. "LL31_CRC_EN," "0,1"
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bitfld.long 0x184 27. "LL31_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
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bitfld.long 0x184 26. "LL31_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
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bitfld.long 0x184 23.--25. "LL31_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x184 9.--22. 1. "LL31_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
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bitfld.long 0x184 8. "LL31_FMT_IN," "0,1"
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bitfld.long 0x184 7. "LL31_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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bitfld.long 0x184 5.--6. "LL31_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
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bitfld.long 0x184 3.--4. "LL31_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
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bitfld.long 0x184 2. "LL31_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
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bitfld.long 0x184 1. "LL31_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
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bitfld.long 0x184 0. "LL31_VALID," "0,1"
line.long 0x188 "CFG_DATA_LL31_LPHDR_VAL,"
line.long 0x18C "CFG_DATA_LL31_THRESHOLD,"
hexmask.long.word 0x18C 19.--31. 1. "NU3,"
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bitfld.long 0x18C 16.--18. "ll31dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
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rbitfld.long 0x18C 15. "NU2," "0,1"
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hexmask.long.byte 0x18C 8.--14. 1. "LL31_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
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rbitfld.long 0x18C 7. "NU1," "0,1"
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hexmask.long.byte 0x18C 0.--6. 1. "LL31_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x190 "CFG_LVDS_MAPPING_LANE0_FMT_0,"
bitfld.long 0x190 28.--31. "CFG_LVDS_MAPPING_LANE0_FMT_0_H,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 24.--27. "CFG_LVDS_MAPPING_LANE0_FMT_0_G,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 20.--23. "CFG_LVDS_MAPPING_LANE0_FMT_0_F,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 16.--19. "CFG_LVDS_MAPPING_LANE0_FMT_0_E,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 12.--15. "CFG_LVDS_MAPPING_LANE0_FMT_0_D,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 8.--11. "CFG_LVDS_MAPPING_LANE0_FMT_0_C,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 4.--7. "CFG_LVDS_MAPPING_LANE0_FMT_0_B,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 0.--3. "CFG_LVDS_MAPPING_LANE0_FMT_0_A,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
line.long 0x194 "CFG_LVDS_MAPPING_LANE1_FMT_0,"
bitfld.long 0x194 28.--31. "CFG_LVDS_MAPPING_LANE1_FMT_0_H,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 24.--27. "CFG_LVDS_MAPPING_LANE1_FMT_0_G,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 20.--23. "CFG_LVDS_MAPPING_LANE1_FMT_0_F,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 16.--19. "CFG_LVDS_MAPPING_LANE1_FMT_0_E,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 12.--15. "CFG_LVDS_MAPPING_LANE1_FMT_0_D,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 8.--11. "CFG_LVDS_MAPPING_LANE1_FMT_0_C,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 4.--7. "CFG_LVDS_MAPPING_LANE1_FMT_0_B,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 0.--3. "CFG_LVDS_MAPPING_LANE1_FMT_0_A,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
line.long 0x198 "CFG_LVDS_MAPPING_LANE2_FMT_0,"
bitfld.long 0x198 28.--31. "CFG_LVDS_MAPPING_LANE2_FMT_0_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 24.--27. "CFG_LVDS_MAPPING_LANE2_FMT_0_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 20.--23. "CFG_LVDS_MAPPING_LANE2_FMT_0_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 16.--19. "CFG_LVDS_MAPPING_LANE2_FMT_0_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 12.--15. "CFG_LVDS_MAPPING_LANE2_FMT_0_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 8.--11. "CFG_LVDS_MAPPING_LANE2_FMT_0_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 4.--7. "CFG_LVDS_MAPPING_LANE2_FMT_0_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 0.--3. "CFG_LVDS_MAPPING_LANE2_FMT_0_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "CFG_LVDS_MAPPING_LANE3_FMT_0,"
bitfld.long 0x19C 28.--31. "CFG_LVDS_MAPPING_LANE3_FMT_0_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 24.--27. "CFG_LVDS_MAPPING_LANE3_FMT_0_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 20.--23. "CFG_LVDS_MAPPING_LANE3_FMT_0_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 16.--19. "CFG_LVDS_MAPPING_LANE3_FMT_0_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 12.--15. "CFG_LVDS_MAPPING_LANE3_FMT_0_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 8.--11. "CFG_LVDS_MAPPING_LANE3_FMT_0_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 4.--7. "CFG_LVDS_MAPPING_LANE3_FMT_0_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 0.--3. "CFG_LVDS_MAPPING_LANE3_FMT_0_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "CFG_LVDS_MAPPING_LANE0_FMT_1,"
bitfld.long 0x1A0 28.--31. "CFG_LVDS_MAPPING_LANE0_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 24.--27. "CFG_LVDS_MAPPING_LANE0_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 20.--23. "CFG_LVDS_MAPPING_LANE0_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 16.--19. "CFG_LVDS_MAPPING_LANE0_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 12.--15. "CFG_LVDS_MAPPING_LANE0_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 8.--11. "CFG_LVDS_MAPPING_LANE0_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 4.--7. "CFG_LVDS_MAPPING_LANE0_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 0.--3. "CFG_LVDS_MAPPING_LANE0_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "CFG_LVDS_MAPPING_LANE1_FMT_1,"
bitfld.long 0x1A4 28.--31. "CFG_LVDS_MAPPING_LANE1_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 24.--27. "CFG_LVDS_MAPPING_LANE1_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 20.--23. "CFG_LVDS_MAPPING_LANE1_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 16.--19. "CFG_LVDS_MAPPING_LANE1_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 12.--15. "CFG_LVDS_MAPPING_LANE1_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 8.--11. "CFG_LVDS_MAPPING_LANE1_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 4.--7. "CFG_LVDS_MAPPING_LANE1_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 0.--3. "CFG_LVDS_MAPPING_LANE1_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "CFG_LVDS_MAPPING_LANE2_FMT_1,"
bitfld.long 0x1A8 28.--31. "CFG_LVDS_MAPPING_LANE2_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 24.--27. "CFG_LVDS_MAPPING_LANE2_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 20.--23. "CFG_LVDS_MAPPING_LANE2_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 16.--19. "CFG_LVDS_MAPPING_LANE2_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 12.--15. "CFG_LVDS_MAPPING_LANE2_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 8.--11. "CFG_LVDS_MAPPING_LANE2_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 4.--7. "CFG_LVDS_MAPPING_LANE2_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 0.--3. "CFG_LVDS_MAPPING_LANE2_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "CFG_LVDS_MAPPING_LANE3_FMT_1,"
bitfld.long 0x1AC 28.--31. "CFG_LVDS_MAPPING_LANE3_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 24.--27. "CFG_LVDS_MAPPING_LANE3_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 20.--23. "CFG_LVDS_MAPPING_LANE3_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 16.--19. "CFG_LVDS_MAPPING_LANE3_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 12.--15. "CFG_LVDS_MAPPING_LANE3_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 8.--11. "CFG_LVDS_MAPPING_LANE3_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 4.--7. "CFG_LVDS_MAPPING_LANE3_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 0.--3. "CFG_LVDS_MAPPING_LANE3_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "CFG_LVDS_GEN_0,"
bitfld.long 0x1B0 30.--31. "cpz,LVDS Clock config" "0,1,2,3"
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bitfld.long 0x1B0 29. "cblpen,TI Internal CFG_LASTPULSE_EN" "0,1"
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bitfld.long 0x1B0 28. "cbcrcen,LVDS Frame CRC" "CRC is not sent at the end of LVDS Frame,CRC is sent at the end of the LVDS Frame"
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bitfld.long 0x1B0 24.--27. "cfdly,LVDS FIFO Initial Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1B0 23. "cmsbf," "0,1"
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bitfld.long 0x1B0 22. "cpossel," "0,1"
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bitfld.long 0x1B0 16.--21. "cckdiv,TI Internal feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x1B0 15. "cclksel1,TRM Description" "DDR mode clock mux,SDR mode clock mux TI Restricted Description"
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bitfld.long 0x1B0 14. "cclksel,TI Internal feature" "0,1"
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bitfld.long 0x1B0 12.--13. "ckchar,TI Internal feature" "0,1,2,3"
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bitfld.long 0x1B0 11. "ccsmen,TRM Description : As per alignment TI Restricted Description" "Regular operation,Continuous Streaming Mode Enabled (Not supported.."
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bitfld.long 0x1B0 10. "CFG_BIT_CLK_MODE,Bit Clock Mode" "SDR clocking mode,DDR clocking mode"
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bitfld.long 0x1B0 8.--9. "CFG_LINE_MODE,TI Internal feature" "0,1,2,3"
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bitfld.long 0x1B0 7. "cpkfmt,TI Internal feature" "0,1"
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bitfld.long 0x1B0 6. "cacdsel,TI Internal feature" "If the LVDS clock frequency (SDR) is >= 200MHz,If the LVDS clock frequency (SDR) is < 200MHz"
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bitfld.long 0x1B0 5. "ctc2en,TI Internal feature" "Regular operation,TC2MODE Enable (Not supported internally also in.."
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bitfld.long 0x1B0 4. "CFG_8B10B_EN,TI Internal Feature" "No encoding,8B10B encoding"
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bitfld.long 0x1B0 3. "CFG_LVDS_LANE3_EN,LVDS only programming" "LVDS Lane 3 is disbaled,LVDS Lane 3 is enabled"
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bitfld.long 0x1B0 2. "CFG_LVDS_LANE2_EN,LVDS only programming" "LVDS Lane 2 is disbaled,LVDS Lane 2 is enabled"
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bitfld.long 0x1B0 1. "CFG_LVDS_LANE1_EN,LVDS only programming" "LVDS Lane 1 is disbaled,LVDS Lane 1 is enabled"
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bitfld.long 0x1B0 0. "CFG_LVDS_LANE0_EN,LVDS only programming" "LVDS Lane 0 is disbaled,LVDS Lane 0 is enabled"
line.long 0x1B4 "CFG_LVDS_GEN_1,"
hexmask.long.word 0x1B4 19.--31. 1. "NU2,RESERVED"
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bitfld.long 0x1B4 18. "cgbcen,TI Internal Feature" "Bit clk is free running,Bit clk is valid only during the valid frame"
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bitfld.long 0x1B4 17. "cfcpol,TI Internal Feature" "During IDLE Frame clock will be 0,During IDLE"
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bitfld.long 0x1B4 16. "clfven,TI Internal feature" "Regular Operation,The frame_valid would start early by about 10.."
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bitfld.long 0x1B4 14.--15. "ctpsel3,TI Internal feature" "0,1,2,3"
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bitfld.long 0x1B4 12.--13. "ctpsel2,TI Internal feature" "0,1,2,3"
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bitfld.long 0x1B4 10.--11. "ctpsel1,TI Internal feature" "0,1,2,3"
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bitfld.long 0x1B4 8.--9. "ctpsel0,TI Internal feature" "0,1,2,3"
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rbitfld.long 0x1B4 7. "NU1,RESERVED" "0,1"
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bitfld.long 0x1B4 4.--6. "ctiddly,TI Internal feature" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x1B4 3. "NU3," "0,1"
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bitfld.long 0x1B4 2. "c3c3l,LVDS Only Programming" "Regular Operation,Enable 3Ch-3Lane mode in LVDS"
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bitfld.long 0x1B4 1. "csdrinv,TI Internal feature" "No inversion,Inversion"
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bitfld.long 0x1B4 0. "ctpen,TI Internal feature" "Regular Operation,LVDS Testpattern Enable"
line.long 0x1B8 "CFG_LVDS_GEN_2,"
line.long 0x1BC "CFG_MASK_REG0,"
line.long 0x1C0 "CFG_MASK_REG1,"
line.long 0x1C4 "CFG_MASK_REG2,"
line.long 0x1C8 "CFG_MASK_REG3,"
line.long 0x1CC "STAT_CBUFF_REG0,"
hexmask.long.tbyte 0x1CC 13.--31. 1. "STAT_CBUFF_REG0_OTHERS,Reseved for future enhancement"
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bitfld.long 0x1CC 12. "S_FRAME_DONE,Indicates that CBUFF has completed sending out data for the current Frame" "0,1"
newline
bitfld.long 0x1CC 11. "S_CHIRP_DONE,Indicates that CBUFF has completed sending out data for the current Chirp" "0,1"
newline
bitfld.long 0x1CC 6.--10. "S_LL_INDEX,TI Internal Feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1CC 5. "S_CSI_PKT_LP_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Long Data Packet" "0,1"
newline
bitfld.long 0x1CC 4. "S_CSI_PKT_HE_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Hsync End Packet" "0,1"
newline
bitfld.long 0x1CC 3. "S_CSI_PKT_HS_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Hsync Start Packet" "0,1"
newline
bitfld.long 0x1CC 2. "S_CSI_PKT_VE_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Vsync End Packet" "0,1"
newline
bitfld.long 0x1CC 1. "S_CSI_PKT_VS_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Vsync Start Packet" "0,1"
newline
bitfld.long 0x1CC 0. "S_CSI_PKT_RCVD,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine" "0,1"
line.long 0x1D0 "STAT_CBUFF_REG1,"
hexmask.long.word 0x1D0 21.--31. 1. "S1_UNUSED3,"
newline
bitfld.long 0x1D0 20. "S_CBFIFO_READY_IN_FSM,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 19. "S_CBFIFO_EMPTY_IN_FSM,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 18. "S_PKTRCV_ERR,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 17. "S_FRAME_ERR,Indicates the FrameStart arrived before CBUFF has completed sending out data for all the Chirps programmed" "0,1"
newline
bitfld.long 0x1D0 16. "S_CHIRP_ERR,Indicates tha the chirpAvailable from ADCBuffer arrived before CBUFF has completed sending out the previous Chirp data" "0,1"
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bitfld.long 0x1D0 12.--15. "S1_UNUSED2,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1D0 11. "S_CBFIFO_EMPTY,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 10. "S_CBFIFO_FULL,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 9. "S_CBPUSH_ERR,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 8. "S_CBPOP_ERR,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 3.--7. "S1_UNUSED1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1D0 2. "S_LCLPUSH_ERR,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 1. "S_LCLPOP_ERR,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 0. "S_LCLFSM_ERR,TI Internal Feature" "0,1"
rgroup.long 0x1FC++0x03
line.long 0x00 "STAT_LVDS_REG0,"
group.long 0x20C++0x27
line.long 0x00 "CLR_CBUFF_REG0,"
hexmask.long.tbyte 0x00 13.--31. 1. "CLR_CBUFF_REG0_OTHERS,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0"
newline
bitfld.long 0x00 12. "C_FRAME_DONE,Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
newline
bitfld.long 0x00 11. "C_CHIRP_DONE,Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
newline
bitfld.long 0x00 6.--10. "C_LL_INDEX,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 5. "C_CSI_PKT_LP_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 4. "C_CSI_PKT_HE_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
newline
bitfld.long 0x00 3. "C_CSI_PKT_HS_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
newline
bitfld.long 0x00 2. "C_CSI_PKT_VE_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 1. "C_CSI_PKT_VS_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 0. "C_CSI_PKT_RCVD,TI Internal Feature" "0,1"
line.long 0x04 "CLR_CBUFF_REG1,"
line.long 0x08 "CLR_LVDS_REG0,"
line.long 0x0C "CLR_LVDS_REG1,"
line.long 0x10 "STAT_CBUFF_ECC_REG,"
hexmask.long.tbyte 0x10 10.--31. 1. "NU2,"
newline
bitfld.long 0x10 9. "seccdbe," "0,1"
newline
bitfld.long 0x10 8. "seccsbe," "0,1"
newline
bitfld.long 0x10 6.--7. "NU1," "0,1,2,3"
newline
bitfld.long 0x10 0.--5. "seccadd,6-bit address where the ECC error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "MASK_CBUFF_ECC_REG,"
hexmask.long.tbyte 0x14 10.--31. 1. "NU2,"
newline
bitfld.long 0x14 9. "meccdbe," "0,1"
newline
bitfld.long 0x14 8. "meccsbe," "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "NU1,"
line.long 0x18 "CLR_CBUFF_ECC_REG,"
hexmask.long.tbyte 0x18 10.--31. 1. "NU2,"
newline
bitfld.long 0x18 9. "ceccdbe,Clear Register field corresponding to STAT_CBUFF_ECC" "0,1"
newline
bitfld.long 0x18 8. "ceccsbe,Clear Register field corresponding to STAT_CBUFF_ECC" "0,1"
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hexmask.long.byte 0x18 1.--7. 1. "NU1,"
newline
bitfld.long 0x18 0. "ceccadd,Clear Register field corresponding to STAT_CBUFF_ECC" "0,1"
line.long 0x1C "STAT_SAFETY,"
hexmask.long.tbyte 0x1C 9.--31. 1. "SAF_UNUSED1,RESERVED"
newline
bitfld.long 0x1C 8. "SAF_CHIRP_ERR,Safety Error" "0,1"
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abitfld.long 0x1C 0.--7. "SAF_CRC,TRM Desccription : Indicates a CRC error between ADCBuffer and CBUFF" "0x00=CRC for col-0 - [15:0],0x01=CRC for col-1 [31:16],0x02=CRC for col-2 [47:32],0x03=CRC for col-3 [63:48],0x04=CRC for col-4 - [79:64],0x05=CRC for col-5 [95:80],0x06=CRC for col-6 [111 :96,0x07=for col-7 [127:112]"
line.long 0x20 "MASK_SAFETY,"
line.long 0x24 "CLR_SAFETY,"
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x200)++0x03
line.long 0x00 "STAT_LVDS_REG$1,"
repeat.end
repeat 2. (list 2. 3. )(list 0x00 0x04 )
rgroup.long ($2+0x1F4)++0x03
line.long 0x00 "STAT_CBUFF_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_CM4_CTRL (DSS CM4 Control Module Registers)"
base ad:0x48020000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 11.--15. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "UNDEFINED_NAME," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x7F
line.long 0x00 "HWA_CM4_B0_MEMINIT_START,"
bitfld.long 0x00 0. "hwa_cm4_b0_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x04 "HWA_CM4_B0_MEMINIT_STATUS,"
bitfld.long 0x04 0. "hwa_cm4_b0_meminit_status,Status field" "0,1"
line.long 0x08 "HWA_CM4_B0_MEMINIT_DONE,"
bitfld.long 0x08 0. "hwa_cm4_b0_meminit_done,Status field" "0,1"
line.long 0x0C "HWA_CM4_B1_MEMINIT_START,"
bitfld.long 0x0C 0. "hwa_cm4_b1_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x10 "HWA_CM4_B1_MEMINIT_STATUS,"
bitfld.long 0x10 0. "hwa_cm4_b1_meminit_status,Status field" "0,1"
line.long 0x14 "HWA_CM4_B1_MEMINIT_DONE,"
bitfld.long 0x14 0. "hwa_cm4_b1_meminit_done,Status field" "0,1"
line.long 0x18 "HWA_CM4_B2_MEMINIT_START,"
bitfld.long 0x18 0. "hwa_cm4_b2_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x1C "HWA_CM4_B2_MEMINIT_STATUS,"
bitfld.long 0x1C 0. "hwa_cm4_b2_meminit_status,Status field" "0,1"
line.long 0x20 "HWA_CM4_B2_MEMINIT_DONE,"
bitfld.long 0x20 0. "hwa_cm4_b2_meminit_done,Status field" "0,1"
line.long 0x24 "HWA_CM4_MBOX_MEMINIT_START,"
bitfld.long 0x24 0. "hwa_cm4_mbox_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x28 "HWA_CM4_MBOX_MEMINIT_STATUS,"
bitfld.long 0x28 0. "hwa_cm4_mbox_meminit_status,Status field" "0,1"
line.long 0x2C "HWA_CM4_MBOX_MEMINIT_DONE,"
bitfld.long 0x2C 0. "hwa_cm4_mbox_meminit_done,Status field" "0,1"
line.long 0x30 "HWA_CM4_MBOX_WRITE_DONE,"
bitfld.long 0x30 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
bitfld.long 0x30 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
newline
bitfld.long 0x30 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
bitfld.long 0x30 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
newline
bitfld.long 0x30 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
bitfld.long 0x30 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
newline
bitfld.long 0x30 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
bitfld.long 0x30 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0x34 "HWA_CM4_MBOX_READ_REQ,"
bitfld.long 0x34 28. "proc_7,This is request from processor 7 to HSM" "0,1"
bitfld.long 0x34 24. "proc_6,This is request from processor 6 to HSM" "0,1"
newline
bitfld.long 0x34 20. "proc_5,This is request from processor 5 to HSM" "0,1"
bitfld.long 0x34 16. "proc_4,This is request from processor 4 to HSM" "0,1"
newline
bitfld.long 0x34 12. "proc_3,This is request from processor 3 to HSM" "0,1"
bitfld.long 0x34 8. "proc_2,This is request from processor 2 to HSM" "0,1"
newline
bitfld.long 0x34 4. "proc_1,This is request from processor 1 to HSM" "0,1"
bitfld.long 0x34 0. "proc_0,This is request from processor 0 to HSM" "0,1"
line.long 0x38 "HWA_CM4_MBOX_READ_DONE,"
bitfld.long 0x38 28. "proc_7,This register should be written once finishing reading from hsm's mailbox written by proc 7" "0,1"
bitfld.long 0x38 24. "proc_6,This register should be written once finishing reading from hsm's mailbox written by proc 6" "0,1"
newline
bitfld.long 0x38 20. "proc_5,This register should be written once finishing reading from hsm's mailbox written by proc 5" "0,1"
bitfld.long 0x38 16. "proc_4,This register should be written once finishing reading from hsm's mailbox written by proc 4" "0,1"
newline
bitfld.long 0x38 12. "proc_3,This register should be written once finishing reading from hsm's mailbox written by proc 3" "0,1"
bitfld.long 0x38 8. "proc_2,This register should be written once finishing reading from hsm's mailbox written by proc 2" "0,1"
newline
bitfld.long 0x38 4. "proc_1,This register should be written once finishing reading from hsm's mailbox written by proc 1" "0,1"
bitfld.long 0x38 0. "proc_0,This register should be written once finishing reading from hsm's mailbox written by proc 0" "0,1"
line.long 0x3C "HWA_CM4_IRQ_REQ,"
bitfld.long 0x3C 0.--1. "select,Software configration for INT Request" "0,1,2,3"
line.long 0x40 "HWA_CM4_POR_RST_CTRL,"
bitfld.long 0x40 0.--2. "assert,Por reset control for CM4" "0,1,2,3,4,5,6,7"
line.long 0x44 "HWA_CM4_SYS_RST_CTRL,"
bitfld.long 0x44 0.--2. "assert,Reset control for CM4" "0,1,2,3,4,5,6,7"
line.long 0x48 "HWA_CM4_CFG,"
bitfld.long 0x48 12.--14. "cm4_sys_reset_hold,In development mode by default cm4 will be held in reset" "0,1,2,3,4,5,6,7"
bitfld.long 0x48 8. "cm4_clk_gate,CM4 Clock Gate" "Un-gate the clock,Clock gated"
newline
bitfld.long 0x48 2. "wicenreq,WIC mode Request from PMU" "0,1"
bitfld.long 0x48 1. "sleep_hold_reqn,Hold core in sleep mode" "0,1"
newline
bitfld.long 0x48 0. "force_hclk_active,Force HCLK to run overrides GATEHCLK" "0,1"
line.long 0x4C "HWA_CM4_RST_CAUSE_CLR,"
bitfld.long 0x4C 0.--2. "clear,Writing '111' will clear the HWA_CM4_RST_STATUS_REG" "0,1,2,3,4,5,6,7"
line.long 0x50 "HWA_CM4_RST_CAUSE,"
hexmask.long.byte 0x50 0.--7. 1. "status,Reset Cause Register"
line.long 0x54 "HWA_CM4_FSM_RST_CTRL,"
bitfld.long 0x54 28.--30. "rst_fsm_trig,writing '111' will triggger the reset fsm for CM4" "0,1,2,3,4,5,6,7"
bitfld.long 0x54 24.--26. "rst_wficheck,writing '111' will check for WFI before asserting reset to CM4" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x54 16.--23. 1. "rst_assertdly_common,This field the decides number of cycles reset to CM4 should be asserted"
hexmask.long.byte 0x54 8.--15. 1. "rst2assertdly,This field the decides number cycles for which the reset should be held before asserting reset for CM4"
line.long 0x58 "HWA_CM4_WFI_OVERRIDE,"
bitfld.long 0x58 0.--2. "wfi_override,writing '111' will override the wfi signal from CM4" "0,1,2,3,4,5,6,7"
line.long 0x5C "HWA_CM4_PERIPH_ERRAGG_MASK,"
bitfld.long 0x5C 11. "rcss_ctrl_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 10. "rcss_ctrl_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 9. "rcss_rcm_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 8. "rcss_rcm_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 7. "dss_hwa_cfg_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 6. "dss_hwa_cfg_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 5. "dss_cm4_ctrl_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 4. "dss_cm4_ctrl_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 3. "dss_ctrl_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 2. "dss_ctrl_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 1. "dss_rcm_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 0. "dss_rcm_rd,Writing '1' will mask the respective peripheral error line" "0,1"
line.long 0x60 "HWA_CM4_PERIPH_ERRAGG_STATUS,"
bitfld.long 0x60 11. "rcss_ctrl_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 10. "rcss_ctrl_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 9. "rcss_rcm_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 8. "rcss_rcm_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 7. "dss_hwa_cfg_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 6. "dss_hwa_cfg_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 5. "dss_cm4_ctrl_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 4. "dss_cm4_ctrl_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 3. "dss_ctrl_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 2. "dss_ctrl_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 1. "dss_rcm_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 0. "dss_rcm_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
line.long 0x64 "HWA_CM4_PERIPH_ERRAGG_STATUS_RAW,"
bitfld.long 0x64 11. "rcss_ctrl_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 10. "rcss_ctrl_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 9. "rcss_rcm_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 8. "rcss_rcm_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 7. "dss_hwa_cfg_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 6. "dss_hwa_cfg_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 5. "dss_cm4_ctrl_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 4. "dss_cm4_ctrl_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 3. "dss_ctrl_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 2. "dss_ctrl_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 1. "dss_rcm_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 0. "dss_rcm_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
line.long 0x68 "HWA_CM4_AHB_ERRAGG_MASK,"
bitfld.long 0x68 2. "sbus_write,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x68 1. "dbus_write,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x68 0. "ibus_write,Writing '1' will mask the respective peripheral error line" "0,1"
line.long 0x6C "HWA_CM4_AHB_ERRAGG_STATUS,"
bitfld.long 0x6C 2. "sbus_write,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x6C 1. "dbus_write,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x6C 0. "ibus_write,Indicates the post mask status of the respective peripheral error line" "0,1"
line.long 0x70 "HWA_CM4_AHB_ERRAGG_STATUS_RAW,"
bitfld.long 0x70 2. "sbus_write,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x70 1. "dbus_write,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x70 0. "ibus_write,Indicates the pre mask status of the respective peripheral error line" "0,1"
line.long 0x74 "HWA_CM4_ECC_ERRAGG_MASK,"
bitfld.long 0x74 3. "mbox_ded,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x74 2. "bank2_ded,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x74 1. "bank1_ded,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x74 0. "bank0_ded,Writing '1' will mask the respective peripheral error line" "0,1"
line.long 0x78 "HWA_CM4_ECC_ERRAGG_STATUS,"
bitfld.long 0x78 3. "mbox_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x78 2. "bank2_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
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bitfld.long 0x78 1. "bank1_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x78 0. "bank0_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
line.long 0x7C "HWA_CM4_ECC_ERRAGG_STATUS_RAW,"
bitfld.long 0x7C 3. "mbox_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x7C 2. "bank2_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
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bitfld.long 0x7C 1. "bank1_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x7C 0. "bank0_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "UNDEFINED_NAME,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "UNDEFINED_NAME,Kick access violation error" "0,1"
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bitfld.long 0x08 1. "UNDEFINED_NAME,Addressing violation error" "0,1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "UNDEFINED_NAME,Kick access violation error" "0,1"
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bitfld.long 0x0C 1. "UNDEFINED_NAME,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "UNDEFINED_NAME,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "UNDEFINED_NAME,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "UNDEFINED_NAME,Kick access violation error enable" "0,1"
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bitfld.long 0x10 1. "UNDEFINED_NAME,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "UNDEFINED_NAME,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "UNDEFINED_NAME,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "UNDEFINED_NAME,Kick access violation error enable clear" "0,1"
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bitfld.long 0x14 1. "UNDEFINED_NAME,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "UNDEFINED_NAME,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "UNDEFINED_NAME,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "UNDEFINED_NAME,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "UNDEFINED_NAME,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "UNDEFINED_NAME,XID"
hexmask.long.word 0x24 8.--19. 1. "UNDEFINED_NAME,Route ID"
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hexmask.long.byte 0x24 0.--7. 1. "UNDEFINED_NAME,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "UNDEFINED_NAME,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_CM4_STC (DSS DSP STC Module Registers)"
base ad:0x56F79200
group.long 0x00++0x11B
line.long 0x00 "STCGCR0,Self test Global control Reg0"
hexmask.long.word 0x00 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run"
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rbitfld.long 0x00 11.--15. "NU0,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval" "Continue NSTC run from previous interval,Restart NSTC run from ROM address 0 1X = Start..,?..."
line.long 0x04 "STCGCR1,Self test Global control Reg1"
hexmask.long.tbyte 0x04 12.--31. 1. "NU2,Reserved bits"
newline
bitfld.long 0x04 8.--11. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x04 7. "NU3,Reserved bits" "0,1"
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bitfld.long 0x04 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode" "XOR mode,Spread mode"
newline
bitfld.long 0x04 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration" "Operates in Normal Scan Mode,Operates in Low Power Scan Mode"
newline
bitfld.long 0x04 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
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bitfld.long 0x04 0.--3. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "STCTPR,Time out counter preload register"
line.long 0x0C "STC_CADDR,Current Address register for CORE1"
line.long 0x10 "STCCICR,Current Interval count register"
hexmask.long.word 0x10 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well"
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hexmask.long.word 0x10 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run"
line.long 0x14 "STCGSTAT,Global Status Register"
hexmask.long.tbyte 0x14 12.--31. 1. "NU4,Reserved bits"
newline
bitfld.long 0x14 8.--11. "ST_ACTIVE,Tells whether self test is currently active or not" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 2.--7. "NU5,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)" "Self test run has not failed,SelfTest run has failed"
newline
bitfld.long 0x14 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)" "Not completed,SelfTest run Completed"
line.long 0x18 "STCFSTAT,Fail Status Register"
hexmask.long 0x18 5.--31. 1. "NU6,Reserved bits"
newline
bitfld.long 0x18 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur" "Failure on Segment 0,Failure on Segment 1,Failure on Segment 2,Failure on Segment 3"
newline
bitfld.long 0x18 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)" "No time out error occurred,SelfTest run failed due to a timeout error"
newline
bitfld.long 0x18 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)" "No MISR mismatch for CORE2,Self test run failed due to MISR mismatch for.."
newline
bitfld.long 0x18 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments" "No MISR mismatch for CORE1,Self test run failed due to MISR mismatch for.."
line.long 0x1C "STCSCSCR,Signature compare Self Check Register"
hexmask.long 0x1C 5.--31. 1. "NU7,Reserved bits"
newline
bitfld.long 0x1C 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)" "No fault insertion,Inserts fault in the logic unedr test which will.."
newline
bitfld.long 0x1C 0.--3. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "STC_CADDR2,Current Address register for CORE2"
line.long 0x24 "STC_CLKDIV,Clock Divider Register"
rbitfld.long 0x24 27.--31. "NU8,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 19.--23. "NU9,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 11.--15. "NU10,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 3.--7. "NU11,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
line.long 0x28 "STC_SEGPLR,Segment 1st interval Preload Register"
hexmask.long 0x28 2.--31. 1. "NU12,Reserved bits"
newline
bitfld.long 0x28 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter" "Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of.."
line.long 0x2C "SEG0_START_ADDR,ROM Start address for Segment0"
hexmask.long.word 0x2C 20.--31. 1. "NU13,Reserved bits"
newline
hexmask.long.tbyte 0x2C 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x30 "SEG1_START_ADDR,ROM Start address for Segment1"
hexmask.long.word 0x30 20.--31. 1. "NU14,Reserved bits"
newline
hexmask.long.tbyte 0x30 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x34 "SEG2_START_ADDR,ROM Start address for Segment2"
hexmask.long.word 0x34 20.--31. 1. "NU15,Reserved bits"
newline
hexmask.long.tbyte 0x34 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x38 "SEG3_START_ADDR,ROM Start address for Segment3"
hexmask.long.word 0x38 20.--31. 1. "NU16,Reserved bits"
newline
hexmask.long.tbyte 0x38 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x3C "CORE1_CURMISR_0,Holds the MISR signature for CORE1"
line.long 0x40 "CORE1_CURMISR_1,Holds the MISR signature for CORE1"
line.long 0x44 "CORE1_CURMISR_2,Holds the MISR signature for CORE1"
line.long 0x48 "CORE1_CURMISR_3,Holds the MISR signature for CORE1"
line.long 0x4C "CORE1_CURMISR_4,Holds the MISR signature for CORE1"
line.long 0x50 "CORE1_CURMISR_5,Holds the MISR signature for CORE1"
line.long 0x54 "CORE1_CURMISR_6,Holds the MISR signature for CORE1"
line.long 0x58 "CORE1_CURMISR_7,Holds the MISR signature for CORE1"
line.long 0x5C "CORE1_CURMISR_8,Holds the MISR signature for CORE1"
line.long 0x60 "CORE1_CURMISR_9,Holds the MISR signature for CORE1"
line.long 0x64 "CORE1_CURMISR_10,Holds the MISR signature for CORE1"
line.long 0x68 "CORE1_CURMISR_11,Holds the MISR signature for CORE1"
line.long 0x6C "CORE1_CURMISR_12,Holds the MISR signature for CORE1"
line.long 0x70 "CORE1_CURMISR_13,Holds the MISR signature for CORE1"
line.long 0x74 "CORE1_CURMISR_14,Holds the MISR signature for CORE1"
line.long 0x78 "CORE1_CURMISR_15,Holds the MISR signature for CORE1"
line.long 0x7C "CORE1_CURMISR_16,Holds the MISR signature for CORE1"
line.long 0x80 "CORE1_CURMISR_17,Holds the MISR signature for CORE1"
line.long 0x84 "CORE1_CURMISR_18,Holds the MISR signature for CORE1"
line.long 0x88 "CORE1_CURMISR_19,Holds the MISR signature for CORE1"
line.long 0x8C "CORE1_CURMISR_20,Holds the MISR signature for CORE1"
line.long 0x90 "CORE1_CURMISR_21,Holds the MISR signature for CORE1"
line.long 0x94 "CORE1_CURMISR_22,Holds the MISR signature for CORE1"
line.long 0x98 "CORE1_CURMISR_23,Holds the MISR signature for CORE1"
line.long 0x9C "CORE1_CURMISR_24,Holds the MISR signature for CORE1"
line.long 0xA0 "CORE1_CURMISR_25,Holds the MISR signature for CORE1"
line.long 0xA4 "CORE1_CURMISR_26,Holds the MISR signature for CORE1"
line.long 0xA8 "CORE1_CURMISR_27,Holds the MISR signature for CORE1"
line.long 0xAC "CORE2_CURMISR_0,Holds the MISR signature for CORE2"
line.long 0xB0 "CORE2_CURMISR_1,Holds the MISR signature for CORE2"
line.long 0xB4 "CORE2_CURMISR_2,Holds the MISR signature for CORE2"
line.long 0xB8 "CORE2_CURMISR_3,Holds the MISR signature for CORE2"
line.long 0xBC "CORE2_CURMISR_4,Holds the MISR signature for CORE2"
line.long 0xC0 "CORE2_CURMISR_5,Holds the MISR signature for CORE2"
line.long 0xC4 "CORE2_CURMISR_6,Holds the MISR signature for CORE2"
line.long 0xC8 "CORE2_CURMISR_7,Holds the MISR signature for CORE2"
line.long 0xCC "CORE2_CURMISR_8,Holds the MISR signature for CORE2"
line.long 0xD0 "CORE2_CURMISR_9,Holds the MISR signature for CORE2"
line.long 0xD4 "CORE2_CURMISR_10,Holds the MISR signature for CORE2"
line.long 0xD8 "CORE2_CURMISR_11,Holds the MISR signature for CORE2"
line.long 0xDC "CORE2_CURMISR_12,Holds the MISR signature for CORE2"
line.long 0xE0 "CORE2_CURMISR_13,Holds the MISR signature for CORE2"
line.long 0xE4 "CORE2_CURMISR_14,Holds the MISR signature for CORE2"
line.long 0xE8 "CORE2_CURMISR_15,Holds the MISR signature for CORE2"
line.long 0xEC "CORE2_CURMISR_16,Holds the MISR signature for CORE2"
line.long 0xF0 "CORE2_CURMISR_17,Holds the MISR signature for CORE2"
line.long 0xF4 "CORE2_CURMISR_18,Holds the MISR signature for CORE2"
line.long 0xF8 "CORE2_CURMISR_19,Holds the MISR signature for CORE2"
line.long 0xFC "CORE2_CURMISR_20,Holds the MISR signature for CORE2"
line.long 0x100 "CORE2_CURMISR_21,Holds the MISR signature for CORE2"
line.long 0x104 "CORE2_CURMISR_22,Holds the MISR signature for CORE2"
line.long 0x108 "CORE2_CURMISR_23,Holds the MISR signature for CORE2"
line.long 0x10C "CORE2_CURMISR_24,Holds the MISR signature for CORE2"
line.long 0x110 "CORE2_CURMISR_25,Holds the MISR signature for CORE2"
line.long 0x114 "CORE2_CURMISR_26,Holds the MISR signature for CORE2"
line.long 0x118 "CORE2_CURMISR_27,Holds the MISR signature for CORE2"
width 0x0B
tree.end
tree "DSS_CTRL (DSS CTRL Module Registers)"
base ad:0x56020000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x5B
line.long 0x00 "DSS_SW_INT,"
bitfld.long 0x00 0.--3. "dss_swint,DSS SW Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DSS_TPCC_A_ERRAGG_MASK,"
bitfld.long 0x04 26. "tptc_a1_read_access_error,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 25. "tptc_a0_read_access_error,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 24. "tpcc_a_read_access_error,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 18. "tptc_a1_write_access_error,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPTC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 17. "tptc_a0_write_access_error,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPTC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 16. "tpcc_a_write_access_error,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 8. "tpcc_a_parity_err,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 3. "tptc_a1_err,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 2. "tptc_a0_err,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 1. "tpcc_a_mpint,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 0. "tpcc_a_errint,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x08 "DSS_TPCC_A_ERRAGG_STATUS,"
bitfld.long 0x08 26. "tptc_a1_read_access_error,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 25. "tptc_a0_read_access_error,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 24. "tpcc_a_read_access_error,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 18. "tptc_a1_write_access_error,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 17. "tptc_a0_write_access_error,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 16. "tpcc_a_write_access_error,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 8. "tpcc_a_parity_err,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 3. "tptc_a1_err,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 2. "tptc_a0_err,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 1. "tpcc_a_mpint,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 0. "tpcc_a_errint,Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x0C "DSS_TPCC_A_ERRAGG_STATUS_RAW,"
bitfld.long 0x0C 26. "tptc_a1_read_access_error,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x0C 25. "tptc_a0_read_access_error,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x0C 24. "tpcc_a_read_access_error,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 18. "tptc_a1_write_access_error,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x0C 17. "tptc_a0_write_access_error,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x0C 16. "tpcc_a_write_access_error,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 8. "tpcc_a_parity_err,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 3. "tptc_a1_err,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x0C 2. "tptc_a0_err,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x0C 1. "tpcc_a_mpint,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 0. "tpcc_a_errint,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x10 "DSS_TPCC_A_INTAGG_MASK,"
bitfld.long 0x10 17. "tptc_a1,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 16. "tptc_a0,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 8. "tpcc_a_int7,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 7. "tpcc_a_int6,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 6. "tpcc_a_int5,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 5. "tpcc_a_int4,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 4. "tpcc_a_int3,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 3. "tpcc_a_int2,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 2. "tpcc_a_int1,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 1. "tpcc_a_int0,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 0. "tpcc_a_intg,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x14 "DSS_TPCC_A_INTAGG_STATUS,"
bitfld.long 0x14 17. "tptc_a1,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x14 16. "tptc_a0,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x14 8. "tpcc_a_int7,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 7. "tpcc_a_int6,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 6. "tpcc_a_int5,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 5. "tpcc_a_int4,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 4. "tpcc_a_int3,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 3. "tpcc_a_int2,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 2. "tpcc_a_int1,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 1. "tpcc_a_int0,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 0. "tpcc_a_intg,Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x18 "DSS_TPCC_A_INTAGG_STATUS_RAW,"
bitfld.long 0x18 17. "tptc_a1,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x18 16. "tptc_a0,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x18 8. "tpcc_a_int7,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 7. "tpcc_a_int6,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 6. "tpcc_a_int5,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 5. "tpcc_a_int4,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 4. "tpcc_a_int3,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 3. "tpcc_a_int2,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 2. "tpcc_a_int1,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 1. "tpcc_a_int0,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 0. "tpcc_a_intg,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x1C "DSS_TPCC_B_ERRAGG_MASK,"
bitfld.long 0x1C 26. "tptc_b1_read_access_error,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 25. "tptc_b0_read_access_error,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 24. "tpcc_b_read_access_error,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 18. "tptc_b1_write_access_error,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 17. "tptc_b0_write_access_error,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 16. "tpcc_b_write_access_error,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 8. "tpcc_b_parity_err,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 3. "tptc_b1_err,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 2. "tptc_b0_err,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 1. "tpcc_b_mpint,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 0. "tpcc_b_errint,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x20 "DSS_TPCC_B_ERRAGG_STATUS,"
bitfld.long 0x20 26. "tptc_b1_read_access_error,Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x20 25. "tptc_b0_read_access_error,Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x20 24. "tpcc_b_read_access_error,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 18. "tptc_b1_write_access_error,Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x20 17. "tptc_b0_write_access_error,Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x20 16. "tpcc_b_write_access_error,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 8. "tpcc_b_parity_err,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 3. "tptc_b1_err,Status of Error from DSS_TPCC_B1" "0,1"
newline
bitfld.long 0x20 2. "tptc_b0_err,Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x20 1. "tpcc_b_mpint,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 0. "tpcc_b_errint,Status of Error from DSS_TPCC_B" "0,1"
line.long 0x24 "DSS_TPCC_B_ERRAGG_STATUS_RAW,"
bitfld.long 0x24 26. "tptc_b1_read_access_error,Raw Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x24 25. "tptc_b0_read_access_error,Raw Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x24 24. "tpcc_b_read_access_error,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 18. "tptc_b1_write_access_error,Raw Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x24 17. "tptc_b0_write_access_error,Raw Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x24 16. "tpcc_b_write_access_error,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 8. "tpcc_b_parity_err,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 3. "tptc_b1_err,Raw Status of Error from DSS_TPCC_B1" "0,1"
newline
bitfld.long 0x24 2. "tptc_b0_err,Raw Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x24 1. "tpcc_b_mpint,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 0. "tpcc_b_errint,Raw Status of Error from DSS_TPCC_B" "0,1"
line.long 0x28 "DSS_TPCC_B_INTAGG_MASK,"
bitfld.long 0x28 17. "tptc_b1,Mask Interrupt from DSS_TPTC_B1 to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 16. "tptc_b0,Mask Interrupt from DSS_TPTC_B0 to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 8. "tpcc_b_int7,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 7. "tpcc_b_int6,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 6. "tpcc_b_int5,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 5. "tpcc_b_int4,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 4. "tpcc_b_int3,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 3. "tpcc_b_int2,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 2. "tpcc_b_int1,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 1. "tpcc_b_int0,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 0. "tpcc_b_intg,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x2C "DSS_TPCC_B_INTAGG_STATUS,"
bitfld.long 0x2C 17. "tptc_b1,Status of Interrupt from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x2C 16. "tptc_b0,Status of Interrupt from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x2C 8. "tpcc_b_int7,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 7. "tpcc_b_int6,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 6. "tpcc_b_int5,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 5. "tpcc_b_int4,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 4. "tpcc_b_int3,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 3. "tpcc_b_int2,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 2. "tpcc_b_int1,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 1. "tpcc_b_int0,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 0. "tpcc_b_intg,Status of Interrupt from DSS_TPCC_B" "0,1"
line.long 0x30 "DSS_TPCC_B_INTAGG_STATUS_RAW,"
bitfld.long 0x30 17. "tptc_b1,Raw Status of Interrupt from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x30 16. "tptc_b0,Raw Status of Interrupt from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x30 8. "tpcc_b_int7,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 7. "tpcc_b_int6,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 6. "tpcc_b_int5,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 5. "tpcc_b_int4,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 4. "tpcc_b_int3,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 3. "tpcc_b_int2,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 2. "tpcc_b_int1,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 1. "tpcc_b_int0,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 0. "tpcc_b_intg,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
line.long 0x34 "DSS_TPCC_C_ERRAGG_MASK,"
bitfld.long 0x34 30. "tptc_c5_read_access_error,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 29. "tptc_c4_read_access_error,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 28. "tptc_c3_read_access_error,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 27. "tptc_c2_read_access_error,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 26. "tptc_c1_read_access_error,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 25. "tptc_c0_read_access_error,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 24. "tpcc_c_read_access_error,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 22. "tptc_c5_write_access_error,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 21. "tptc_c4_write_access_error,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 20. "tptc_c3_write_access_error,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 19. "tptc_c2_write_access_error,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 18. "tptc_c1_write_access_error,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 17. "tptc_c0_write_access_error,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 16. "tpcc_c_write_access_error,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 8. "tpcc_c_parity_err,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 7. "tptc_c5_err,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 6. "tptc_c4_err,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 5. "tptc_c3_err,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 4. "tptc_c2_err,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 3. "tptc_c1_err,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 2. "tptc_c0_err,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 1. "tpcc_c_mpint,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 0. "tpcc_c_errint,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x38 "DSS_TPCC_C_ERRAGG_STATUS,"
bitfld.long 0x38 30. "tptc_c5_read_access_error,Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x38 29. "tptc_c4_read_access_error,Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x38 28. "tptc_c3_read_access_error,Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x38 27. "tptc_c2_read_access_error,Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x38 26. "tptc_c1_read_access_error,Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x38 25. "tptc_c0_read_access_error,Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x38 24. "tpcc_c_read_access_error,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 22. "tptc_c5_write_access_error,Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x38 21. "tptc_c4_write_access_error,Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x38 20. "tptc_c3_write_access_error,Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x38 19. "tptc_c2_write_access_error,Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x38 18. "tptc_c1_write_access_error,Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x38 17. "tptc_c0_write_access_error,Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x38 16. "tpcc_c_write_access_error,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 8. "tpcc_c_parity_err,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 7. "tptc_c5_err,Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x38 6. "tptc_c4_err,Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x38 5. "tptc_c3_err,Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x38 4. "tptc_c2_err,Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x38 3. "tptc_c1_err,Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x38 2. "tptc_c0_err,Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x38 1. "tpcc_c_mpint,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 0. "tpcc_c_errint,Status of Error from DSS_TPCC_C" "0,1"
line.long 0x3C "DSS_TPCC_C_ERRAGG_STATUS_RAW,"
bitfld.long 0x3C 30. "tptc_c5_read_access_error,Raw Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x3C 29. "tptc_c4_read_access_error,Raw Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x3C 28. "tptc_c3_read_access_error,Raw Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x3C 27. "tptc_c2_read_access_error,Raw Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x3C 26. "tptc_c1_read_access_error,Raw Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x3C 25. "tptc_c0_read_access_error,Raw Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x3C 24. "tpcc_c_read_access_error,Raw Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x3C 22. "tptc_c5_write_access_error,Raw Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x3C 21. "tptc_c4_write_access_error,Raw Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x3C 20. "tptc_c3_write_access_error,Raw Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x3C 19. "tptc_c2_write_access_error,Raw Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x3C 18. "tptc_c1_write_access_error,Raw Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x3C 17. "tptc_c0_write_access_error,Raw Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x3C 16. "tpcc_c_write_access_error,Raw Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x3C 8. "tpcc_c_parity_err,Raw Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x3C 7. "tptc_c5_err,Raw Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x3C 6. "tptc_c4_err,Raw Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x3C 5. "tptc_c3_err,Raw Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x3C 4. "tptc_c2_err,Raw Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x3C 3. "tptc_c1_err,Raw Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x3C 2. "tptc_c0_err,Raw Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x3C 1. "tpcc_c_mpint,Raw Status of Error from DSS_TPCC_C0" "0,1"
newline
bitfld.long 0x3C 0. "tpcc_c_errint,Raw Status of Error from DSS_TPCC_C" "0,1"
line.long 0x40 "DSS_TPCC_C_INTAGG_MASK,"
bitfld.long 0x40 21. "tptc_c5,Mask Interrupt from DSS_TPTC_C5 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 20. "tptc_c4,Mask Interrupt from DSS_TPTC_C4 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 19. "tptc_c3,Mask Interrupt from DSS_TPTC_C3 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 18. "tptc_c2,Mask Interrupt from DSS_TPTC_C2 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 17. "tptc_c1,Mask Interrupt from DSS_TPTC_C1 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 16. "tptc_c0,Mask Interrupt from DSS_TPTC_C0 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 8. "tpcc_c_int7,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 7. "tpcc_c_int6,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 6. "tpcc_c_int5,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 5. "tpcc_c_int4,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 4. "tpcc_c_int3,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 3. "tpcc_c_int2,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 2. "tpcc_c_int1,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 1. "tpcc_c_int0,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 0. "tpcc_c_intg,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x44 "DSS_TPCC_C_INTAGG_STATUS,"
bitfld.long 0x44 21. "tptc_c5,Status of Interrupt from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x44 20. "tptc_c4,Status of Interrupt from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x44 19. "tptc_c3,Status of Interrupt from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x44 18. "tptc_c2,Status of Interrupt from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x44 17. "tptc_c1,Status of Interrupt from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x44 16. "tptc_c0,Status of Interrupt from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x44 8. "tpcc_c_int7,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 7. "tpcc_c_int6,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 6. "tpcc_c_int5,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 5. "tpcc_c_int4,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 4. "tpcc_c_int3,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 3. "tpcc_c_int2,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 2. "tpcc_c_int1,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 1. "tpcc_c_int0,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 0. "tpcc_c_intg,Status of Interrupt from DSS_TPCC_C" "0,1"
line.long 0x48 "DSS_TPCC_C_INTAGG_STATUS_RAW,"
bitfld.long 0x48 21. "tptc_c5,Raw Status of Interrupt from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x48 20. "tptc_c4,Raw Status of Interrupt from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x48 19. "tptc_c3,Raw Status of Interrupt from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x48 18. "tptc_c2,Raw Status of Interrupt from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x48 17. "tptc_c1,Raw Status of Interrupt from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x48 16. "tptc_c0,Raw Status of Interrupt from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x48 8. "tpcc_c_int7,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 7. "tpcc_c_int6,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 6. "tpcc_c_int5,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 5. "tpcc_c_int4,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 4. "tpcc_c_int3,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 3. "tpcc_c_int2,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 2. "tpcc_c_int1,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 1. "tpcc_c_int0,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 0. "tpcc_c_intg,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
line.long 0x4C "DSS_TPCC_MEMINIT_START,"
bitfld.long 0x4C 2. "tpcc_c_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x4C 1. "tpcc_b_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x4C 0. "tpcc_a_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
line.long 0x50 "DSS_TPCC_MEMINIT_STATUS,"
bitfld.long 0x50 2. "tpcc_c_meminit_status,Status field" "0,1"
newline
bitfld.long 0x50 1. "tpcc_b_meminit_status,Status field" "0,1"
newline
bitfld.long 0x50 0. "tpcc_a_meminit_status,Status field" "0,1"
line.long 0x54 "DSS_TPCC_MEMINIT_DONE,"
bitfld.long 0x54 2. "tpcc_c_meminit_done,Status field" "0,1"
newline
bitfld.long 0x54 1. "tpcc_b_meminit_done,Status field" "0,1"
newline
bitfld.long 0x54 0. "tpcc_a_meminit_done,Status field" "0,1"
line.long 0x58 "DSS_DSP_L2RAM_PARITY_CTRL,"
hexmask.long.byte 0x58 8.--15. 1. "err_clear,Write to bit N to clear L2 Parity Error line N"
newline
hexmask.long.byte 0x58 0.--7. 1. "enable,Write to bit N to enable L2 Parity N"
group.long 0x80++0x23
line.long 0x00 "DSS_DSP_L2RAM_MEMINIT_START,"
bitfld.long 0x00 7. "vb31,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 6. "vb30,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 5. "vb21,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 4. "vb20,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 3. "vb11,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 2. "vb10,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 1. "vb01,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 0. "vb00,Start Memory intialization of DSP L2 memory" "0,1"
line.long 0x04 "DSS_DSP_L2RAM_MEMINIT_STATUS,"
bitfld.long 0x04 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x04 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x04 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x04 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x04 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x04 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x04 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x04 0. "vb00,Status field" "0,1"
line.long 0x08 "DSS_DSP_L2RAM_MEMINIT_DONE,"
bitfld.long 0x08 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x08 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x08 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x08 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x08 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x08 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x08 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x08 0. "vb00,Status field" "0,1"
line.long 0x0C "DSS_DSP_L2RAM_PARITY_MEMINIT_START,"
bitfld.long 0x0C 7. "vb31,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 6. "vb30,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 5. "vb21,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 4. "vb20,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 3. "vb11,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 2. "vb10,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 1. "vb01,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 0. "vb00,Start Memory intialization of DSP L2 Parity memory" "0,1"
line.long 0x10 "DSS_DSP_L2RAM_PARITY_MEMINIT_STATUS,"
bitfld.long 0x10 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x10 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x10 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x10 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x10 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x10 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x10 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x10 0. "vb00,Status field" "0,1"
line.long 0x14 "DSS_DSP_L2RAM_PARITY_MEMINIT_DONE,"
bitfld.long 0x14 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x14 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x14 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x14 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x14 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x14 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x14 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x14 0. "vb00,Status field" "0,1"
line.long 0x18 "DSS_L3RAM_MEMINIT_START,"
bitfld.long 0x18 3. "l3ram3_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x18 2. "l3ram2_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x18 1. "l3ram1_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x18 0. "l3ram0_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
line.long 0x1C "DSS_L3RAM_MEMINIT_STATUS,"
bitfld.long 0x1C 3. "l3ram3_meminit_status,Status field" "0,1"
newline
bitfld.long 0x1C 2. "l3ram2_meminit_status,Status field" "0,1"
newline
bitfld.long 0x1C 1. "l3ram1_meminit_status,Status field" "0,1"
newline
bitfld.long 0x1C 0. "l3ram0_meminit_status,Status field" "0,1"
line.long 0x20 "DSS_L3RAM_MEMINIT_DONE,"
bitfld.long 0x20 3. "l3ram3_meminit_done,Status field" "0,1"
newline
bitfld.long 0x20 2. "l3ram2_meminit_done,Status field" "0,1"
newline
bitfld.long 0x20 1. "l3ram1_meminit_done,Status field" "0,1"
newline
bitfld.long 0x20 0. "l3ram0_meminit_done,Status field" "0,1"
group.long 0xB0++0x33
line.long 0x00 "DSS_MAILBOX_MEMINIT_START,"
bitfld.long 0x00 0. "meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
line.long 0x04 "DSS_MAILBOX_MEMINIT_STATUS,"
bitfld.long 0x04 0. "meminit_status,Status field" "0,1"
line.long 0x08 "DSS_MAILBOX_MEMINIT_DONE,"
bitfld.long 0x08 0. "meminit_done,Status field" "0,1"
line.long 0x0C "DSS_TPCC_A_PARITY_CTRL,"
bitfld.long 0x0C 2. "parity_err_clr,Write 0x1 to clear the Parit Error status for TPCC" "0,1"
newline
bitfld.long 0x0C 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
newline
bitfld.long 0x0C 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x10 "DSS_TPCC_B_PARITY_CTRL,"
bitfld.long 0x10 2. "parity_err_clr,Write 0x1 to clear the Parit Error status for TPCC" "0,1"
newline
bitfld.long 0x10 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
newline
bitfld.long 0x10 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x14 "DSS_TPCC_C_PARITY_CTRL,"
bitfld.long 0x14 2. "parity_err_clr,Write 0x1 to clear the Parit Error status for TPCC" "0,1"
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bitfld.long 0x14 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
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bitfld.long 0x14 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x18 "DSS_TPCC_A_PARITY_STATUS,"
hexmask.long.byte 0x18 0.--7. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x1C "DSS_TPCC_B_PARITY_STATUS,"
hexmask.long.byte 0x1C 0.--7. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x20 "DSS_TPCC_C_PARITY_STATUS,"
hexmask.long.word 0x20 0.--8. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x24 "TPTC_DBS_CONFIG,"
bitfld.long 0x24 18.--19. "tptc_c5,Max Burst size tieoff value for TPTC C5" "0,1,2,3"
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bitfld.long 0x24 16.--17. "tptc_c4,Max Burst size tieoff value for TPTC C4" "0,1,2,3"
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bitfld.long 0x24 14.--15. "tptc_c3,Max Burst size tieoff value for TPTC C3" "0,1,2,3"
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bitfld.long 0x24 12.--13. "tptc_c2,Max Burst size tieoff value for TPTC C2" "0,1,2,3"
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bitfld.long 0x24 10.--11. "tptc_c1,Max Burst size tieoff value for TPTC C1" "0,1,2,3"
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bitfld.long 0x24 8.--9. "tptc_c0,Max Burst size tieoff value for TPTC C0" "0,1,2,3"
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bitfld.long 0x24 6.--7. "tptc_b1,Max Burst size tieoff value for TPTC B0" "0,1,2,3"
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bitfld.long 0x24 4.--5. "tptc_b0,Max Burst size tieoff value for TPTC B0" "0,1,2,3"
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bitfld.long 0x24 2.--3. "tptc_a1,Max Burst size tieoff value for TPTC A1" "0,1,2,3"
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bitfld.long 0x24 0.--1. "tptc_a0,Max Burst size tieoff value for TPTC A0" "0,1,2,3"
line.long 0x28 "DSS_DSP_BOOTCFG,"
bitfld.long 0x28 25. "L1P_CACHE_MODE,DSP Boot Configuration : L1P Cache Mode" "0,1"
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bitfld.long 0x28 24. "L1D_CACHE_MODE,DSP Boot Configuration : L1D Cache Mode" "0,1"
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hexmask.long.tbyte 0x28 0.--21. 1. "ISTP_RST_VAL,DSP Boot Configuration : Reset Vector"
line.long 0x2C "DSS_DSP_NMI_GATE,"
bitfld.long 0x2C 0.--2. "gate,Write 3'b111 to gate the Non Maskable Interrupt to the DSP" "0,1,2,3,4,5,6,7"
line.long 0x30 "DSS_PBIST_KEY_RESET,"
bitfld.long 0x30 4.--7. "dss_pbist_st_reset,DSS PBIST controller will be brought out of reset when value is 0xA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "dss_pbist_st_key,DSS PBIST Selftest Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xEC++0x17
line.long 0x00 "DSS_TPTC_BOUNDARY_CFG0,"
bitfld.long 0x00 24.--29. "tptc_b1_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--21. "tptc_b0_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "tptc_a1_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "tptc_a0_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DSS_TPTC_BOUNDARY_CFG1,"
bitfld.long 0x04 24.--29. "tptc_c3_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 16.--21. "tptc_c2_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 8.--13. "tptc_c1_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 0.--5. "tptc_c0_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DSS_TPTC_BOUNDARY_CFG2,"
bitfld.long 0x08 8.--13. "tptc_c5_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 0.--5. "tptc_c4_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DSS_TPTC_XID_REORDER_CFG0,"
bitfld.long 0x0C 24. "tptc_b1_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x0C 16. "tptc_b0_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x0C 8. "tptc_a1_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x0C 0. "tptc_a0_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
line.long 0x10 "DSS_TPTC_XID_REORDER_CFG1,"
bitfld.long 0x10 24. "tptc_c3_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x10 16. "tptc_c2_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x10 8. "tptc_c1_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x10 0. "tptc_c0_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
line.long 0x14 "DSS_TPTC_XID_REORDER_CFG2,"
bitfld.long 0x14 8. "tptc_c5_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x14 0. "tptc_c4_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
group.long 0x108++0x0F
line.long 0x00 "ESM_GATING0,"
line.long 0x04 "ESM_GATING1,"
line.long 0x08 "ESM_GATING2,"
line.long 0x0C "ESM_GATING3,"
group.long 0x560++0x37
line.long 0x00 "DSS_PERIPH_ERRAGG_MASK0,"
bitfld.long 0x00 11. "rcss_ctrl_wr,Mask the Write error from RCSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 10. "rcss_ctrl_rd,Mask the Read error from RCSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 9. "rcss_rcm_wr,Mask the Write error from RCSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 8. "rcss_rcm_rd,Mask the Read error from RCSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 7. "dss_hwa_cfg_wr,Mask the Write error from DSS_HWA_CFG space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 6. "dss_hwa_cfg_rd,Mask the Read error from DSS_HWA_CFG space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 5. "dss_cm4_ctrl_wr,Mask the Write error from DSS_CM4_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 4. "dss_cm4_ctrl_rd,Mask the Read error from DSS_CM4_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 3. "dss_ctrl_wr,Mask the Write error from DSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 2. "dss_ctrl_rd,Mask the Read error from DSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 1. "dss_rcm_wr,Mask the Write error from DSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 0. "dss_rcm_rd,Mask the Read error from DSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
line.long 0x04 "DSS_PERIPH_ERRAGG_STATUS0,"
bitfld.long 0x04 11. "rcss_ctrl_wr,Status of the Write error from RCSS_CTRL space" "0,1"
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bitfld.long 0x04 10. "rcss_ctrl_rd,Status of the Read error from RCSS_CTRL space" "0,1"
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bitfld.long 0x04 9. "rcss_rcm_wr,Status of the Write error from RCSS_RCM space" "0,1"
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bitfld.long 0x04 8. "rcss_rcm_rd,Status of the Read error from RCSS_RCM space" "0,1"
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bitfld.long 0x04 7. "dss_hwa_cfg_wr,Status of the Write error from DSS_HWA_CFG space" "0,1"
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bitfld.long 0x04 6. "dss_hwa_cfg_rd,Status of the Read error from DSS_HWA_CFG space" "0,1"
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bitfld.long 0x04 5. "dss_cm4_ctrl_wr,Status of the Write error from DSS_CM4_CTRL space" "0,1"
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bitfld.long 0x04 4. "dss_cm4_ctrl_rd,Status of the Read error from DSS_CM4_CTRL space" "0,1"
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bitfld.long 0x04 3. "dss_ctrl_wr,Status of the Write error from DSS_CTRL space" "0,1"
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bitfld.long 0x04 2. "dss_ctrl_rd,Status of the Read error from DSS_CTRL space" "0,1"
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bitfld.long 0x04 1. "dss_rcm_wr,Status of the Write error from DSS_RCM space" "0,1"
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bitfld.long 0x04 0. "dss_rcm_rd,Status of the Read error from DSS_RCM space" "0,1"
line.long 0x08 "DSS_PERIPH_ERRAGG_STATUS_RAW0,"
bitfld.long 0x08 11. "rcss_ctrl_wr,Raw Status of the Write error from RCSS_CTRL space irrespective of it being masked" "0,1"
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bitfld.long 0x08 10. "rcss_ctrl_rd,Raw Status of the Read error from RCSS_CTRL space irrespective of it being masked" "0,1"
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bitfld.long 0x08 9. "rcss_rcm_wr,Raw Status of the Write error from RCSS_RCM space irrespective of it being masked" "0,1"
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bitfld.long 0x08 8. "rcss_rcm_rd,Raw Status of the Read error from RCSS_RCM space irrespective of it being masked" "0,1"
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bitfld.long 0x08 7. "dss_hwa_cfg_wr,Raw Status of the Write error from DSS_HWA_CFG space irrespective of it being masked" "0,1"
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bitfld.long 0x08 6. "dss_hwa_cfg_rd,Raw Status of the Read error from DSS_HWA_CFG space irrespective of it being masked" "0,1"
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bitfld.long 0x08 5. "dss_cm4_ctrl_wr,Raw Status of the Write error from DSS_CM4_CTRL space irrespective of it being masked" "0,1"
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bitfld.long 0x08 4. "dss_cm4_ctrl_rd,Raw Status of the Read error from DSS_CM4_CTRL space irrespective of it being masked" "0,1"
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bitfld.long 0x08 3. "dss_ctrl_wr,Raw Status of the Write error from DSS_CTRL space irrespective of it being masked" "0,1"
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bitfld.long 0x08 2. "dss_ctrl_rd,Raw Status of the Read error from DSS_CTRL space irrespective of it being masked" "0,1"
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bitfld.long 0x08 1. "dss_rcm_wr,Raw Status of the Write error from DSS_RCM space irrespective of it being masked" "0,1"
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bitfld.long 0x08 0. "dss_rcm_rd,Raw Status of the Read error from DSS_RCM space irrespective of it being masked" "0,1"
line.long 0x0C "DSS_DSP_MBOX_WRITE_DONE,"
bitfld.long 0x0C 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
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bitfld.long 0x0C 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
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bitfld.long 0x0C 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
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bitfld.long 0x0C 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
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bitfld.long 0x0C 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
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bitfld.long 0x0C 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
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bitfld.long 0x0C 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
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bitfld.long 0x0C 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0x10 "DSS_DSP_MBOX_READ_REQ,"
bitfld.long 0x10 28. "proc_7,This is request from processor 7 to DSS_DSP" "0,1"
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bitfld.long 0x10 24. "proc_6,This is request from processor 6 to DSS_DSP" "0,1"
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bitfld.long 0x10 20. "proc_5,This is request from processor 5 to DSS_DSP" "0,1"
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bitfld.long 0x10 16. "proc_4,This is request from processor 4 to DSS_DSP" "0,1"
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bitfld.long 0x10 12. "proc_3,This is request from processor 3 to DSS_DSP" "0,1"
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bitfld.long 0x10 8. "proc_2,This is request from processor 2 to DSS_DSP" "0,1"
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bitfld.long 0x10 4. "proc_1,This is request from processor 1 to DSS_DSP" "0,1"
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bitfld.long 0x10 0. "proc_0,This is request from processor 0 to DSS_DSP" "0,1"
line.long 0x14 "DSS_DSP_MBOX_READ_DONE,"
bitfld.long 0x14 28. "proc_7,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 7" "0,1"
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bitfld.long 0x14 24. "proc_6,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 6" "0,1"
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bitfld.long 0x14 20. "proc_5,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 5" "0,1"
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bitfld.long 0x14 16. "proc_4,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 4" "0,1"
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bitfld.long 0x14 12. "proc_3,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 3" "0,1"
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bitfld.long 0x14 8. "proc_2,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 2" "0,1"
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bitfld.long 0x14 4. "proc_1,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 1" "0,1"
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bitfld.long 0x14 0. "proc_0,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 0" "0,1"
line.long 0x18 "DSS_WDT_EVENT_CAPTURE_SEL,"
hexmask.long.byte 0x18 8.--14. 1. "cap1,Select the DSS_WDT Capture Event 1 from the DSS DSP Interrupt Map"
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hexmask.long.byte 0x18 0.--6. 1. "cap0,Select the DSS_WDT Capture Event 0 from the DSS DSP Interrupt Map"
line.long 0x1C "DSS_RTIA_EVENT_CAPTURE_SEL,"
hexmask.long.byte 0x1C 8.--14. 1. "cap1,Select the DSS_RTIA Capture Event 1 from the DSS DSP Interrupt Map"
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hexmask.long.byte 0x1C 0.--6. 1. "cap0,Select the DSS_RTIA Capture Event 0 from the DSS DSP Interrupt Map"
line.long 0x20 "DSS_RTIB_EVENT_CAPTURE_SEL,"
hexmask.long.byte 0x20 8.--14. 1. "cap1,Select the DSS_RTIB Capture Event 1 from the DSS DSP Interrupt Map"
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hexmask.long.byte 0x20 0.--6. 1. "cap0,Select the DSS_RTIB Capture Event 0 from the DSS DSP Interrupt Map"
line.long 0x24 "DBG_ACK_CPU_CTRL,"
bitfld.long 0x24 0. "sel,Select the Processor Suspend that is used to Suspend the DSS Peripehrals" "DSP,MSS CR5"
line.long 0x28 "DBG_ACK_CTL0,"
bitfld.long 0x28 20.--22. "DSS_WDT,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 16.--18. "DSS_SCIA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 12.--14. "DSS_RTIB,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 8.--10. "DSS_RTIA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 4.--6. "DSS_DCCB,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 0.--2. "DSS_DCCA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x2C "DBG_ACK_CTL1,"
bitfld.long 0x2C 28.--30. "DSS_HWA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x2C 24.--26. "DSS_MCRC,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x30 "DSS_DSP_INT_SEL,"
bitfld.long 0x30 0.--2. "RCSS_CSI2_ICSSM,DSS DSP Interrupt selcet" "CSI2 Interrupts are propagated to DSP,?,?,?,?,?,?,ICSSM Interrupts are propagted to DSP"
line.long 0x34 "DSS_CBUFF_TRIGGER_SEL,"
hexmask.long.byte 0x34 0.--6. 1. "sel,DSS CBUFF HW Trigger select from DSS DSP Interrupt Map"
group.long 0x800++0x17
line.long 0x00 "DSS_BUS_SAFETY_CTRL,"
bitfld.long 0x00 4.--6. "clk_disable,Option to clock gate the safety infrastructure is Safety is disabled" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x04 "DSS_BUS_SAFETY_SEC_ERR_STAT0,"
bitfld.long 0x04 28. "DSS_MDO_FIFO,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 27. "DSS_CBUFF_FIFO,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 26. "DSS_PCR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 25. "DSS_TPTC_C5_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 24. "DSS_TPTC_C4_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 23. "DSS_TPTC_C3_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 22. "DSS_TPTC_C2_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 21. "DSS_TPTC_C1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 20. "DSS_TPTC_C0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 19. "DSS_TPTC_B1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 18. "DSS_TPTC_B0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 17. "DSS_TPTC_A1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 16. "DSS_TPTC_A0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 15. "DSS_TPTC_C5_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 14. "DSS_TPTC_C4_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 13. "DSS_TPTC_C3_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 12. "DSS_TPTC_C2_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 11. "DSS_TPTC_C1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 10. "DSS_TPTC_C0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 9. "DSS_TPTC_B1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 8. "DSS_TPTC_B0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 7. "DSS_TPTC_A1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 6. "DSS_TPTC_A0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 5. "DSS_DSP_SDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 4. "DSS_L3_BANKD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 3. "DSS_L3_BANKC,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 2. "DSS_L3_BANKB,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 1. "DSS_L3_BANKA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0. "DSS_DSP_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x08 "DSS_BUS_SAFETY_SEC_ERR_STAT1,"
bitfld.long 0x08 5. "DSS_MBOX,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 4. "DSS_CM4_S,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 3. "DSS_CM4_M,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 2. "DSS_HWA_DMA1,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 1. "DSS_HWA_DMA0,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 0. "DSS_MCRC,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x0C "DSS_DSP_MDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x0C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x0C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x0C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x10 "DSS_DSP_MDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x10 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x14 "DSS_DSP_MDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x14 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x820++0x1B
line.long 0x00 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKA_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x844++0x1B
line.long 0x00 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKB_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKB_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x868++0x1B
line.long 0x00 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKC_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x88C++0x1B
line.long 0x00 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKD_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x8B0++0x277
line.long 0x00 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_DSP_SDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_DSP_SDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_DSP_SDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1C "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x20 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x24 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x28 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x2C "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x30 "DSS_TPTC_A0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x30 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x30 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x30 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x34 "DSS_TPTC_A0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x34 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x34 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x34 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x34 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x38 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x38 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x38 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x38 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x38 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3C "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x40 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x44 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x48 "DSS_TPTC_A1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x48 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x48 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x48 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4C "DSS_TPTC_A1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x4C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x50 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x50 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x50 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x50 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x50 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x54 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x54 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x54 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x54 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x54 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x58 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x5C "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x60 "DSS_TPTC_B0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x60 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x60 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x60 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x64 "DSS_TPTC_B0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x64 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x64 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x68 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x68 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x6C "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x6C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x70 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x74 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x78 "DSS_TPTC_B1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x78 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x78 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x78 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x7C "DSS_TPTC_B1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x7C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x7C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x7C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x7C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x80 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x80 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x80 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x80 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x80 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x84 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x84 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x88 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x8C "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x90 "DSS_TPTC_C0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x90 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x90 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x90 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x94 "DSS_TPTC_C0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x94 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x94 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x94 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x94 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x98 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x98 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x98 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x98 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x98 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x9C "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x9C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x9C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x9C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x9C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xA0 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xA4 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xA8 "DSS_TPTC_C1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xA8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xAC "DSS_TPTC_C1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xAC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xAC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xB0 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xB0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB4 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xB4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB8 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xBC "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xC0 "DSS_TPTC_C2_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xC0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xC4 "DSS_TPTC_C2_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xC4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xC8 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xC8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xCC "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xCC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xD0 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xD4 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xD8 "DSS_TPTC_C3_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xD8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xD8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xD8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xDC "DSS_TPTC_C3_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xDC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xDC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xDC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xDC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xE0 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xE0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xE4 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xE4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xE8 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xEC "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xF0 "DSS_TPTC_C4_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xF0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xF0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xF4 "DSS_TPTC_C4_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xF4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xF4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xF8 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xF8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xFC "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xFC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xFC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xFC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xFC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x100 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x104 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x108 "DSS_TPTC_C5_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x108 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x108 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x108 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x10C "DSS_TPTC_C5_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x10C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x110 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x110 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x110 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x110 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x110 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x114 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x114 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x114 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x114 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x114 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x118 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x11C "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x120 "DSS_TPTC_A0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x120 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x120 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x120 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x124 "DSS_TPTC_A0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x124 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x124 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x124 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x124 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x128 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x128 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x128 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x128 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x128 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x12C "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x12C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x12C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x12C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x12C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x130 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x134 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x138 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x13C "DSS_TPTC_A1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x13C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x13C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x13C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x140 "DSS_TPTC_A1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x140 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x140 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x140 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x140 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x144 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x144 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x144 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x144 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x144 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x148 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x148 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x148 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x148 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x148 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x14C "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x150 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x154 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x158 "DSS_TPTC_B0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x158 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x158 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x158 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x15C "DSS_TPTC_B0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x15C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x15C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x15C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x15C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x160 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x160 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x160 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x160 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x160 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x164 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x164 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x164 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x164 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x164 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x168 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x16C "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x170 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x174 "DSS_TPTC_B1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x174 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x174 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x174 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x178 "DSS_TPTC_B1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x178 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x178 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x178 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x178 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x17C "DSS_TPTC_B1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x17C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x17C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x17C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x17C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x180 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x180 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x180 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x180 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x180 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x184 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x188 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x18C "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x190 "DSS_TPTC_C0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x190 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x190 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x190 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x194 "DSS_TPTC_C0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x194 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x194 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x194 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x194 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x198 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x198 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x198 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x198 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x198 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x19C "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x19C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x19C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x19C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x19C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1A0 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1A4 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1A8 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1AC "DSS_TPTC_C1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1AC 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1AC 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1AC 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "DSS_TPTC_C1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1B0 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B0 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B0 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1B0 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1B4 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1B4 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B8 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1B8 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1BC "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1C0 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1C4 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1C8 "DSS_TPTC_C2_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1C8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1CC "DSS_TPTC_C2_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1CC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1CC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1CC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1CC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1D0 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1D0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1D4 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1D4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1D8 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1DC "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1E0 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1E4 "DSS_TPTC_C3_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1E4 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E4 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1E8 "DSS_TPTC_C3_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1E8 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E8 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1EC "DSS_TPTC_C3_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1EC 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1F0 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1F0 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F0 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1F4 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1F8 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1FC "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x200 "DSS_TPTC_C4_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x200 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x200 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x200 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x204 "DSS_TPTC_C4_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x204 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x204 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x208 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x208 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x20C "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x20C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x210 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x214 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x218 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x21C "DSS_TPTC_C5_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x21C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x21C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x21C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x220 "DSS_TPTC_C5_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x220 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x220 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x220 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x220 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x224 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x224 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x228 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x228 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x22C "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x230 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x234 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x238 "DSS_MDO_FIFO_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x238 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x238 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x238 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x23C "DSS_MDO_FIFO_BUS_SAFETY_FI,"
hexmask.long.byte 0x23C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x23C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x23C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x23C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x240 "DSS_MDO_FIFO_BUS_SAFETY_ERR,"
hexmask.long.byte 0x240 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x240 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x240 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x240 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x244 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x244 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x244 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x244 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x244 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x248 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x24C "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x250 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x254 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x258 "DSS_CBUFF_FIFO_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x258 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x258 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x258 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x25C "DSS_CBUFF_FIFO_BUS_SAFETY_FI,"
hexmask.long.byte 0x25C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x25C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x25C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x25C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x260 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR,"
hexmask.long.byte 0x260 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x260 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x260 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x260 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x264 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x264 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x264 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x264 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x264 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x268 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x26C "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x270 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x274 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_WRITERESP,"
group.long 0xBC8++0xDF
line.long 0x00 "DSS_MCRC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x00 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x00 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x00 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x04 "DSS_MCRC_BUS_SAFETY_FI,"
hexmask.long.byte 0x04 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x04 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x08 "DSS_MCRC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x08 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x0C "DSS_MCRC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x0C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x10 "DSS_MCRC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x14 "DSS_MCRC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x18 "DSS_MCRC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1C "DSS_MCRC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x20 "DSS_PCR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x20 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x20 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x20 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x24 "DSS_PCR_BUS_SAFETY_FI,"
hexmask.long.byte 0x24 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x24 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x28 "DSS_PCR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x28 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2C "DSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x30 "DSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x34 "DSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x38 "DSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3C "DSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x40 "DSS_HWA_DMA0_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x40 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x40 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x40 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x44 "DSS_HWA_DMA0_BUS_SAFETY_FI,"
hexmask.long.byte 0x44 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x44 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x48 "DSS_HWA_DMA0_BUS_SAFETY_ERR,"
hexmask.long.byte 0x48 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4C "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x50 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x54 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x58 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x5C "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x60 "DSS_HWA_DMA1_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x60 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x60 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x60 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x64 "DSS_HWA_DMA1_BUS_SAFETY_FI,"
hexmask.long.byte 0x64 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x64 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x68 "DSS_HWA_DMA1_BUS_SAFETY_ERR,"
hexmask.long.byte 0x68 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x6C "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x6C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x70 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x74 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x78 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x7C "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x80 "DSS_CM4_M_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x80 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x80 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x80 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x84 "DSS_CM4_M_BUS_SAFETY_FI,"
hexmask.long.byte 0x84 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x84 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x88 "DSS_CM4_M_BUS_SAFETY_ERR,"
hexmask.long.byte 0x88 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x8C "DSS_CM4_M_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x8C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x90 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x94 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x98 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x9C "DSS_CM4_M_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xA0 "DSS_CM4_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xA0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xA4 "DSS_CM4_S_BUS_SAFETY_FI,"
hexmask.long.byte 0xA4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xA8 "DSS_CM4_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0xA8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xAC "DSS_CM4_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xAC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB0 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xB4 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0xB8 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xBC "DSS_CM4_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xC0 "DSS_MBOX_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xC0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xC4 "DSS_MBOX_BUS_SAFETY_FI,"
hexmask.long.byte 0xC4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xC8 "DSS_MBOX_BUS_SAFETY_ERR,"
hexmask.long.byte 0xC8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xCC "DSS_MBOX_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xCC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xD0 "DSS_MBOX_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xD4 "DSS_MBOX_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0xD8 "DSS_MBOX_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xDC "DSS_MBOX_BUS_SAFETY_ERR_STAT_WRITERESP,"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x8A8)++0x03
line.long 0x00 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x884)++0x03
line.long 0x00 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x860)++0x03
line.long 0x00 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x83C)++0x03
line.long 0x00 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x818)++0x03
line.long 0x00 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xE4)++0x03
line.long 0x00 "DSS_PBIST_REG$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x70)++0x03
line.long 0x00 "DSS_DSP_L2RAM_PARITY_ERR_STATUS_VB$1,"
hexmask.long.word 0x00 16.--27. 1. "addr1,Error address 1 for Virtual Bank 0"
hexmask.long.word 0x00 0.--11. 1. "addr0,Error address 0 for Virtual Bank 0"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_DCCA (DSS DCCA Module Registers)"
base ad:0x56F79C00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "DSS_DCCB (DSS DCCB Module Registers)"
base ad:0x56F79D00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "DSS_DSP_PBIST (DSS DSP PBIST Module Registers)"
base ad:0x56F79000
hgroup.long 0x120++0x07
hide.long 0x00 "PBIST_DD10,DD0 Data Register 16 (D0)"
hide.long 0x04 "PBIST_DE10,DE0 Data Register 16 (D0)"
group.long 0x160++0x03
line.long 0x00 "PBIST_RAMT,RAM Configuration (RAMT -RAM)"
hexmask.long.byte 0x00 24.--31. 1. "RGS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 16.--23. 1. "RDS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 8.--15. 1. "DWR,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 0.--7. 1. "RAM,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
group.word 0x164++0x01
line.word 0x00 "PBIST_DLR,Datalogger 0"
hexmask.word.byte 0x00 8.--15. 1. "DLR1,Datalogger Register [8] : Reserevd [9] : Default Testing Mode"
hexmask.word.byte 0x00 0.--7. 1. "DLR0,Datalogger Register [1:0] : Reserved [2] : ROM-based testing mode"
group.byte 0x168++0x00
line.byte 0x00 "PBIST_CMS,Clock mux select"
bitfld.byte 0x00 0.--3. "PBIST_CMS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x16C++0x00
line.byte 0x00 "PBIST_PC,Program Control"
bitfld.byte 0x00 0.--4. "PBIST_PC,TI Internal Register.Reserved for HW RnD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x178++0x03
line.long 0x00 "PBIST_CS,Chip Select 0"
hexmask.long.byte 0x00 24.--31. 1. "CS3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "CS2,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 8.--15. 1. "CS1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "CS0,TI Internal Register.Reserved for HW RnD"
group.byte 0x17C++0x00
line.byte 0x00 "PBIST_FDLY,Fail Delay"
group.byte 0x180++0x00
line.byte 0x00 "PBIST_PACT,Pbist Active"
bitfld.byte 0x00 0. "PBIST_PACT,Pbist Active/ROM Clock Enable Register [0]: This bit must be set to turn on internal PBIST clocks" "Disable internal PBIST clocks Value,Enable internal PBIST clocks"
group.byte 0x184++0x00
line.byte 0x00 "PBIST_ID,PBIST ID"
bitfld.byte 0x00 0.--4. "PBIST_ID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hgroup.long 0x188++0x03
hide.long 0x00 "PBIST_OVR,PBIST Overrides"
rgroup.byte 0x190++0x00
line.byte 0x00 "PBIST_FSFR0,Fail status fail - port 0"
bitfld.byte 0x00 0. "PBIST_FSFR0,Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x194++0x00
line.byte 0x00 "PBIST_FSFR1,Fail status fail - port 1"
bitfld.byte 0x00 0. "PBIST_FSFR1,Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x198++0x00
line.byte 0x00 "PBIST_FSRCR0,Fail Count fail - port 0"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR0,Fail Status Count - Port 0 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x19C++0x00
line.byte 0x00 "PBIST_FSRCR1,Fail Count fail - port 1"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR1,Fail Status Count - Port 1 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1A0++0x03
hide.long 0x00 "PBIST_FSRA0,Fail status address - port 0"
rgroup.word 0x1A4++0x01
line.word 0x00 "PBIST_FSRA1,Fail status address - port 1"
hgroup.long 0x1B4++0x0B
hide.long 0x00 "PBIST_MARGIN,Margin Mode"
hide.long 0x04 "PBIST_WRENZ,WRENZ"
hide.long 0x08 "PBIST_PGS,PAGE/PGS"
group.byte 0x1C0++0x00
line.byte 0x00 "PBIST_ROM,Rom Mask"
bitfld.byte 0x00 0.--1. "PBIST_ROM,Rom Mask" "No information is used from ROM Value,Only RAM Group information from ROM Vaule,Only Algorithm information from ROM Value,Both Algorithm and RAM information from ROM"
group.long 0x1C4++0x0B
line.long 0x00 "PBIST_ALGO,ROM Algorithm Mask 0"
hexmask.long.byte 0x00 24.--31. 1. "ALGO3,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 16.--23. 1. "ALGO2,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 8.--15. 1. "ALGO1,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 0.--7. 1. "ALGO0,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
line.long 0x04 "PBIST_RINFOL,RAM Info Mask Lower 0"
hexmask.long.byte 0x04 24.--31. 1. "RINFOL3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 16.--23. 1. "RINFOL2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 8.--15. 1. "RINFOL1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 0.--7. 1. "RINFOL0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
line.long 0x08 "PBIST_RINFOU,RAM Info Mask Upper 0"
hexmask.long.byte 0x08 24.--31. 1. "RINFOU3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 16.--23. 1. "RINFOU2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 8.--15. 1. "RINFOU1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 0.--7. 1. "RINFOU0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
repeat 2. (list 0. 1. )(list 0x00 0x08 )
rgroup.long ($2+0x1A8)++0x03
line.long 0x00 "PBIST_FSRDL$1,Fail status Data - port 0"
repeat.end
repeat 2. (list 1. 4. )(list 0x00 0x04 )
group.long ($2+0x170)++0x03
line.long 0x00 "PBIST_SCR$1,Address Scramble 0 -3"
hexmask.long.byte 0x00 24.--31. 1. "SCR3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "SCR2,TI Internal Register.Reserved for HW RnD"
newline
hexmask.long.byte 0x00 8.--15. 1. "SCR1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "SCR0,TI Internal Register.Reserved for HW RnD"
repeat.end
repeat 2. (list 2. 3. )(list 0x00 0x04 )
group.word ($2+0x158)++0x01
line.word 0x00 "PBIST_CI$1,Constant Increment Register2"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
hgroup.long ($2+0x150)++0x03
hide.long 0x00 "PBIST_CI$1,Constant Increment Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x140)++0x03
hide.long 0x00 "PBIST_CL$1,Constant Loop Count Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x130)++0x03
hide.long 0x00 "PBIST_CA$1,Constant Address Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x110)++0x03
hide.long 0x00 "PBIST_L$1,Variable Loop Count Register L0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x100)++0x03
hide.long 0x00 "PBIST_A$1,Variable Address Register0"
repeat.end
width 0x0B
tree.end
tree "DSS_DSP_STC (DSS DSP STC Module Registers)"
base ad:0x56F79200
group.long 0x00++0x11B
line.long 0x00 "STCGCR0,Self test Global control Reg0"
hexmask.long.word 0x00 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run"
newline
rbitfld.long 0x00 11.--15. "NU0,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval" "Continue NSTC run from previous interval,Restart NSTC run from ROM address 0 1X = Start..,?..."
line.long 0x04 "STCGCR1,Self test Global control Reg1"
hexmask.long.tbyte 0x04 12.--31. 1. "NU2,Reserved bits"
newline
bitfld.long 0x04 8.--11. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x04 7. "NU3,Reserved bits" "0,1"
newline
bitfld.long 0x04 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode" "XOR mode,Spread mode"
newline
bitfld.long 0x04 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration" "Operates in Normal Scan Mode,Operates in Low Power Scan Mode"
newline
bitfld.long 0x04 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
newline
bitfld.long 0x04 0.--3. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "STCTPR,Time out counter preload register"
line.long 0x0C "STC_CADDR,Current Address register for CORE1"
line.long 0x10 "STCCICR,Current Interval count register"
hexmask.long.word 0x10 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well"
newline
hexmask.long.word 0x10 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run"
line.long 0x14 "STCGSTAT,Global Status Register"
hexmask.long.tbyte 0x14 12.--31. 1. "NU4,Reserved bits"
newline
bitfld.long 0x14 8.--11. "ST_ACTIVE,Tells whether self test is currently active or not" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 2.--7. "NU5,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)" "Self test run has not failed,SelfTest run has failed"
newline
bitfld.long 0x14 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)" "Not completed,SelfTest run Completed"
line.long 0x18 "STCFSTAT,Fail Status Register"
hexmask.long 0x18 5.--31. 1. "NU6,Reserved bits"
newline
bitfld.long 0x18 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur" "Failure on Segment 0,Failure on Segment 1,Failure on Segment 2,Failure on Segment 3"
newline
bitfld.long 0x18 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)" "No time out error occurred,SelfTest run failed due to a timeout error"
newline
bitfld.long 0x18 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)" "No MISR mismatch for CORE2,Self test run failed due to MISR mismatch for.."
newline
bitfld.long 0x18 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments" "No MISR mismatch for CORE1,Self test run failed due to MISR mismatch for.."
line.long 0x1C "STCSCSCR,Signature compare Self Check Register"
hexmask.long 0x1C 5.--31. 1. "NU7,Reserved bits"
newline
bitfld.long 0x1C 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)" "No fault insertion,Inserts fault in the logic unedr test which will.."
newline
bitfld.long 0x1C 0.--3. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "STC_CADDR2,Current Address register for CORE2"
line.long 0x24 "STC_CLKDIV,Clock Divider Register"
rbitfld.long 0x24 27.--31. "NU8,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 19.--23. "NU9,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 11.--15. "NU10,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 3.--7. "NU11,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
line.long 0x28 "STC_SEGPLR,Segment 1st interval Preload Register"
hexmask.long 0x28 2.--31. 1. "NU12,Reserved bits"
newline
bitfld.long 0x28 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter" "Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of.."
line.long 0x2C "SEG0_START_ADDR,ROM Start address for Segment0"
hexmask.long.word 0x2C 20.--31. 1. "NU13,Reserved bits"
newline
hexmask.long.tbyte 0x2C 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x30 "SEG1_START_ADDR,ROM Start address for Segment1"
hexmask.long.word 0x30 20.--31. 1. "NU14,Reserved bits"
newline
hexmask.long.tbyte 0x30 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x34 "SEG2_START_ADDR,ROM Start address for Segment2"
hexmask.long.word 0x34 20.--31. 1. "NU15,Reserved bits"
newline
hexmask.long.tbyte 0x34 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x38 "SEG3_START_ADDR,ROM Start address for Segment3"
hexmask.long.word 0x38 20.--31. 1. "NU16,Reserved bits"
newline
hexmask.long.tbyte 0x38 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x3C "CORE1_CURMISR_0,Holds the MISR signature for CORE1"
line.long 0x40 "CORE1_CURMISR_1,Holds the MISR signature for CORE1"
line.long 0x44 "CORE1_CURMISR_2,Holds the MISR signature for CORE1"
line.long 0x48 "CORE1_CURMISR_3,Holds the MISR signature for CORE1"
line.long 0x4C "CORE1_CURMISR_4,Holds the MISR signature for CORE1"
line.long 0x50 "CORE1_CURMISR_5,Holds the MISR signature for CORE1"
line.long 0x54 "CORE1_CURMISR_6,Holds the MISR signature for CORE1"
line.long 0x58 "CORE1_CURMISR_7,Holds the MISR signature for CORE1"
line.long 0x5C "CORE1_CURMISR_8,Holds the MISR signature for CORE1"
line.long 0x60 "CORE1_CURMISR_9,Holds the MISR signature for CORE1"
line.long 0x64 "CORE1_CURMISR_10,Holds the MISR signature for CORE1"
line.long 0x68 "CORE1_CURMISR_11,Holds the MISR signature for CORE1"
line.long 0x6C "CORE1_CURMISR_12,Holds the MISR signature for CORE1"
line.long 0x70 "CORE1_CURMISR_13,Holds the MISR signature for CORE1"
line.long 0x74 "CORE1_CURMISR_14,Holds the MISR signature for CORE1"
line.long 0x78 "CORE1_CURMISR_15,Holds the MISR signature for CORE1"
line.long 0x7C "CORE1_CURMISR_16,Holds the MISR signature for CORE1"
line.long 0x80 "CORE1_CURMISR_17,Holds the MISR signature for CORE1"
line.long 0x84 "CORE1_CURMISR_18,Holds the MISR signature for CORE1"
line.long 0x88 "CORE1_CURMISR_19,Holds the MISR signature for CORE1"
line.long 0x8C "CORE1_CURMISR_20,Holds the MISR signature for CORE1"
line.long 0x90 "CORE1_CURMISR_21,Holds the MISR signature for CORE1"
line.long 0x94 "CORE1_CURMISR_22,Holds the MISR signature for CORE1"
line.long 0x98 "CORE1_CURMISR_23,Holds the MISR signature for CORE1"
line.long 0x9C "CORE1_CURMISR_24,Holds the MISR signature for CORE1"
line.long 0xA0 "CORE1_CURMISR_25,Holds the MISR signature for CORE1"
line.long 0xA4 "CORE1_CURMISR_26,Holds the MISR signature for CORE1"
line.long 0xA8 "CORE1_CURMISR_27,Holds the MISR signature for CORE1"
line.long 0xAC "CORE2_CURMISR_0,Holds the MISR signature for CORE2"
line.long 0xB0 "CORE2_CURMISR_1,Holds the MISR signature for CORE2"
line.long 0xB4 "CORE2_CURMISR_2,Holds the MISR signature for CORE2"
line.long 0xB8 "CORE2_CURMISR_3,Holds the MISR signature for CORE2"
line.long 0xBC "CORE2_CURMISR_4,Holds the MISR signature for CORE2"
line.long 0xC0 "CORE2_CURMISR_5,Holds the MISR signature for CORE2"
line.long 0xC4 "CORE2_CURMISR_6,Holds the MISR signature for CORE2"
line.long 0xC8 "CORE2_CURMISR_7,Holds the MISR signature for CORE2"
line.long 0xCC "CORE2_CURMISR_8,Holds the MISR signature for CORE2"
line.long 0xD0 "CORE2_CURMISR_9,Holds the MISR signature for CORE2"
line.long 0xD4 "CORE2_CURMISR_10,Holds the MISR signature for CORE2"
line.long 0xD8 "CORE2_CURMISR_11,Holds the MISR signature for CORE2"
line.long 0xDC "CORE2_CURMISR_12,Holds the MISR signature for CORE2"
line.long 0xE0 "CORE2_CURMISR_13,Holds the MISR signature for CORE2"
line.long 0xE4 "CORE2_CURMISR_14,Holds the MISR signature for CORE2"
line.long 0xE8 "CORE2_CURMISR_15,Holds the MISR signature for CORE2"
line.long 0xEC "CORE2_CURMISR_16,Holds the MISR signature for CORE2"
line.long 0xF0 "CORE2_CURMISR_17,Holds the MISR signature for CORE2"
line.long 0xF4 "CORE2_CURMISR_18,Holds the MISR signature for CORE2"
line.long 0xF8 "CORE2_CURMISR_19,Holds the MISR signature for CORE2"
line.long 0xFC "CORE2_CURMISR_20,Holds the MISR signature for CORE2"
line.long 0x100 "CORE2_CURMISR_21,Holds the MISR signature for CORE2"
line.long 0x104 "CORE2_CURMISR_22,Holds the MISR signature for CORE2"
line.long 0x108 "CORE2_CURMISR_23,Holds the MISR signature for CORE2"
line.long 0x10C "CORE2_CURMISR_24,Holds the MISR signature for CORE2"
line.long 0x110 "CORE2_CURMISR_25,Holds the MISR signature for CORE2"
line.long 0x114 "CORE2_CURMISR_26,Holds the MISR signature for CORE2"
line.long 0x118 "CORE2_CURMISR_27,Holds the MISR signature for CORE2"
width 0x0B
tree.end
tree "DSS_ECC_AGG (DSS ECC AGG Module Registers)"
base ad:0x560A0000
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 22. "RCSS_TPTC_B1_PEND,Interrupt Pending Status for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x04 21. "RCSS_TPTC_B0_PEND,Interrupt Pending Status for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x04 20. "RCSS_TPTC_A1_PEND,Interrupt Pending Status for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x04 19. "RCSS_TPTC_A0_PEND,Interrupt Pending Status for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x04 18. "DSS_TPTC_C5_PEND,Interrupt Pending Status for dss_tptc_c5_pend" "0,1"
bitfld.long 0x04 17. "DSS_TPTC_C4_PEND,Interrupt Pending Status for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x04 16. "DSS_TPTC_C3_PEND,Interrupt Pending Status for dss_tptc_c3_pend" "0,1"
bitfld.long 0x04 15. "DSS_TPTC_C2_PEND,Interrupt Pending Status for dss_tptc_c2_pend" "0,1"
bitfld.long 0x04 14. "DSS_TPTC_C1_PEND,Interrupt Pending Status for dss_tptc_c1_pend" "0,1"
bitfld.long 0x04 13. "DSS_TPTC_C0_PEND,Interrupt Pending Status for dss_tptc_c0_pend" "0,1"
bitfld.long 0x04 12. "DSS_TPTC_B1_PEND,Interrupt Pending Status for dss_tptc_b1_pend" "0,1"
bitfld.long 0x04 11. "DSS_TPTC_B0_PEND,Interrupt Pending Status for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x04 10. "DSS_TPTC_A1_PEND,Interrupt Pending Status for dss_tptc_a1_pend" "0,1"
bitfld.long 0x04 9. "DSS_TPTC_A0_PEND,Interrupt Pending Status for dss_tptc_a0_pend" "0,1"
bitfld.long 0x04 8. "HWACM4_MAILBOX_PEND,Interrupt Pending Status for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x04 7. "HWACM4_RAM_B2_PEND,Interrupt Pending Status for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x04 6. "HWACM4_RAM_B1_PEND,Interrupt Pending Status for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x04 5. "HWACM4_RAM_B0_PEND,Interrupt Pending Status for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x04 4. "DSS_MAILBOX_PEND,Interrupt Pending Status for dss_mailbox_pend" "0,1"
bitfld.long 0x04 3. "DSS_L3RAM3_PEND,Interrupt Pending Status for dss_l3ram3_pend" "0,1"
bitfld.long 0x04 2. "DSS_L3RAM2_PEND,Interrupt Pending Status for dss_l3ram2_pend" "0,1"
bitfld.long 0x04 1. "DSS_L3RAM1_PEND,Interrupt Pending Status for dss_l3ram1_pend" "0,1"
bitfld.long 0x04 0. "DSS_L3RAM0_PEND,Interrupt Pending Status for dss_l3ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 22. "RCSS_TPTC_B1_PEND,Interrupt Pending Status for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x04 21. "RCSS_TPTC_B0_PEND,Interrupt Pending Status for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x04 20. "RCSS_TPTC_A1_PEND,Interrupt Pending Status for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x04 19. "RCSS_TPTC_A0_PEND,Interrupt Pending Status for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x04 18. "DSS_TPTC_C5_PEND,Interrupt Pending Status for dss_tptc_c5_pend" "0,1"
bitfld.long 0x04 17. "DSS_TPTC_C4_PEND,Interrupt Pending Status for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x04 16. "DSS_TPTC_C3_PEND,Interrupt Pending Status for dss_tptc_c3_pend" "0,1"
bitfld.long 0x04 15. "DSS_TPTC_C2_PEND,Interrupt Pending Status for dss_tptc_c2_pend" "0,1"
bitfld.long 0x04 14. "DSS_TPTC_C1_PEND,Interrupt Pending Status for dss_tptc_c1_pend" "0,1"
bitfld.long 0x04 13. "DSS_TPTC_C0_PEND,Interrupt Pending Status for dss_tptc_c0_pend" "0,1"
bitfld.long 0x04 12. "DSS_TPTC_B1_PEND,Interrupt Pending Status for dss_tptc_b1_pend" "0,1"
bitfld.long 0x04 11. "DSS_TPTC_B0_PEND,Interrupt Pending Status for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x04 10. "DSS_TPTC_A1_PEND,Interrupt Pending Status for dss_tptc_a1_pend" "0,1"
bitfld.long 0x04 9. "DSS_TPTC_A0_PEND,Interrupt Pending Status for dss_tptc_a0_pend" "0,1"
bitfld.long 0x04 8. "HWACM4_MAILBOX_PEND,Interrupt Pending Status for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x04 7. "HWACM4_RAM_B2_PEND,Interrupt Pending Status for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x04 6. "HWACM4_RAM_B1_PEND,Interrupt Pending Status for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x04 5. "HWACM4_RAM_B0_PEND,Interrupt Pending Status for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x04 4. "DSS_MAILBOX_PEND,Interrupt Pending Status for dss_mailbox_pend" "0,1"
bitfld.long 0x04 3. "DSS_L3RAM3_PEND,Interrupt Pending Status for dss_l3ram3_pend" "0,1"
bitfld.long 0x04 2. "DSS_L3RAM2_PEND,Interrupt Pending Status for dss_l3ram2_pend" "0,1"
bitfld.long 0x04 1. "DSS_L3RAM1_PEND,Interrupt Pending Status for dss_l3ram1_pend" "0,1"
bitfld.long 0x04 0. "DSS_L3RAM0_PEND,Interrupt Pending Status for dss_l3ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "DSS_ESM (DSS ESM Module Registers)"
base ad:0x56F7D000
group.long 0x00++0x5B
line.long 0x00 "ESMIEPSR1,ESM Enable ERROR Pin Action/Response Register 1"
line.long 0x04 "ESMIEPCR1,ESM Disable ERROR Pin Action/Response Register 1"
line.long 0x08 "ESMIESR1,ESM Interrupt Enable Set/Status Register 1"
line.long 0x0C "ESMIECR1,ESM Interrupt Enable Clear/Status Register 1"
line.long 0x10 "ESMILSR1,Interrupt Level Set/Status Register 1"
line.long 0x14 "ESMILCR1,Interrupt Level Clear/Status Register 1"
line.long 0x18 "ESMSR1,ESM Status Register 1"
line.long 0x1C "ESMSR2,ESM Status Register 2"
line.long 0x20 "ESMSR3,ESM Status Register 3"
line.long 0x24 "ESMEPSR,ESM ERROR Pin Status Register"
hexmask.long 0x24 1.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EPSF,ERROR Pin Status Flag" "0,1"
line.long 0x28 "ESMIOFFHR,ESM Interrupt Offset High Register"
hexmask.long.tbyte 0x28 9.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x28 0.--8. 1. "INTOFFH,Offset High Level Interrupt"
line.long 0x2C "ESMIOFFLR,ESM Interrupt Offset Low Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x2C 0.--7. 1. "INTOFFL,Offset Low Level Interrupt"
line.long 0x30 "ESMLTCR,ESM Low-Time Counter Register"
hexmask.long.word 0x30 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x30 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin"
line.long 0x34 "ESMLTCPR,ESM Low-Time Counter Preload Register"
hexmask.long.word 0x34 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x34 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter"
line.long 0x38 "ESMEKR,ESM Error Key Register"
hexmask.long 0x38 4.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0.--3. "EKEY,Error Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "ESMSSR2,ESM Status Shadow Register 2"
line.long 0x40 "ESMIEPSR4,ESM Enable ERROR Pin Action/Response Register 4"
line.long 0x44 "ESMIEPCR4,ESM Disable ERROR Pin Action/Response Register 4"
line.long 0x48 "ESMIESR4,ESM Interrupt Enable Set/Status Register 4"
line.long 0x4C "ESMIECR4,ESM Interrupt Enable Clear/Status Register 4"
line.long 0x50 "ESMILSR4,Interrupt Level Set/Status Register 4"
line.long 0x54 "ESMILCR4,Interrupt Level Clear/Status Register 4"
line.long 0x58 "ESMSR4,ESM Status Register 4"
group.long 0x80++0x1B
line.long 0x00 "ESMIEPSR7,ESM Enable ERROR Pin Action/Response Register 7"
line.long 0x04 "ESMIEPCR7,ESM Disable ERROR Pin Action/Response Register 7"
line.long 0x08 "ESMIESR7,ESM Interrupt Enable Set/Status Register 7"
line.long 0x0C "ESMIECR7,ESM Interrupt Enable Clear/Status Register 7"
line.long 0x10 "ESMILSR7,Interrupt Level Set/Status Register 7"
line.long 0x14 "ESMILCR7,Interrupt Level Clear/Status Register 7"
line.long 0x18 "ESMSR7,ESM Status Register 7"
group.long 0xC0++0x1B
line.long 0x00 "ESMIEPSR10,ESM Enable ERROR Pin Action/Response Register 10"
line.long 0x04 "ESMIEPCR10,ESM Disable ERROR Pin Action/Response Register 10"
line.long 0x08 "ESMIESR10,ESM Interrupt Enable Set/Status Register 10"
line.long 0x0C "ESMIECR10,ESM Interrupt Enable Clear/Status Register 10"
line.long 0x10 "ESMILSR10,Interrupt Level Set/Status Register 10"
line.long 0x14 "ESMILCR10,Interrupt Level Clear/Status Register 10"
line.long 0x18 "ESMSR10,ESM Status Register 10"
width 0x0B
tree.end
tree "DSS_HWA_CFG (DSS HWA CFG Module Registers)"
base ad:0x56062000
rgroup.long 0x00++0x457
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
newline
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PARAM_RAM_IDX,"
hexmask.long.word 0x04 16.--25. 1. "param_end_idx,The state machine starts at the parameter-set specified by PARAM_START_IDX and loads each parameter-set one after another and runs the accelerator as per that configuration"
newline
hexmask.long.word 0x04 0.--9. 1. "param_start_idx,The state machine starts at the parameter-set specified by PARAM_START_IDX and loads each parameter-set one after another and runs the accelerator as per that configuration"
line.long 0x08 "PARAM_RAM_LOOP,"
hexmask.long.word 0x08 0.--11. 1. "numloops,Number of loops: This register controls the number of times the State Machine will loop through the parameter-sets (from a programmed start index till a programmed end index) and run them"
line.long 0x0C "PARAM_RAM_IDX_ALT,"
hexmask.long.word 0x0C 16.--25. 1. "param_end_idx,PARAM_END_IDX for alternate thread"
newline
hexmask.long.word 0x0C 0.--9. 1. "param_start_idx,PARAM_START_IDX for alternate thread"
line.long 0x10 "PARAM_RAM_LOOP_ALT,"
hexmask.long.word 0x10 0.--11. 1. "numloops,NUMLOOPS for alternate thread"
line.long 0x14 "PREVIOUS_NAME,"
bitfld.long 0x14 24. "hwa_dyn_clk_en,Dynamic Clock-gating Control: Setting this register bit to '1' enables the capability to clock gate the 4 Radar Accelerator core IPs (FFT datapath CFAR Memory compression Local Maxima) based on the ParamSet being executed" "0,1"
newline
bitfld.long 0x14 16.--18. "hwa_reset,Software Reset Control: This register provides software reset control for the Radar Hardware Accelerator" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 8.--10. "hwa_clk_en,Clock-gating Control: This register controls the enable/disable for the clock of the Radar Accelerator" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0.--2. "hwa_en,Enable/Disable Control: A value of ACC_ENABLE = 111b enables the Radar Hardware Accelerator and any other value of the register keeps the Accelerator Engine in disabled state" "0,1,2,3,4,5,6,7"
line.long 0x18 "CS_CONFIG,"
bitfld.long 0x18 16.--20. "cs_trgsrc,In case of DMA trigger this specifies which DMA channel (which bit in DMA2HWA_TRIG register) to wait for In case of HW-based trigger this specifies which CSI2 trigger signal (out of the 20 possible trigger signals) to wait for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--11. "cs_trigmode,Trigger mode for context switching" "?,?,?,DMA-based trigger (used in conjunction with..,Hardware based trigger (used in conjunction with..,Software trigger (used in conjunction with..,?..."
newline
bitfld.long 0x18 0. "cs_enable,Master enable for the Conxtext switching feature.Setting this bit will allow context switching to ALT thread if it is enabled in the Param set" "0,1"
line.long 0x1C "FW2DMA_TRIG,"
line.long 0x20 "DMA2HWA_TRIG,"
line.long 0x24 "SIGDMACH0DONE,"
line.long 0x28 "SIGDMACH1DONE,"
line.long 0x2C "SIGDMACH2DONE,"
line.long 0x30 "SIGDMACH3DONE,"
line.long 0x34 "SIGDMACH4DONE,"
line.long 0x38 "SIGDMACH5DONE,"
line.long 0x3C "SIGDMACH6DONE,"
line.long 0x40 "SIGDMACH7DONE,"
line.long 0x44 "SIGDMACH8DONE,"
line.long 0x48 "SIGDMACH9DONE,"
line.long 0x4C "SIGDMACH10DONE,"
line.long 0x50 "SIGDMACH11DONE,"
line.long 0x54 "SIGDMACH12DONE,"
line.long 0x58 "SIGDMACH13DONE,"
line.long 0x5C "SIGDMACH14DONE,"
line.long 0x60 "SIGDMACH15DONE,"
line.long 0x64 "SIGDMACH16DONE,"
line.long 0x68 "SIGDMACH17DONE,"
line.long 0x6C "SIGDMACH18DONE,"
line.long 0x70 "SIGDMACH19DONE,"
line.long 0x74 "SIGDMACH20DONE,"
line.long 0x78 "SIGDMACH21DONE,"
line.long 0x7C "SIGDMACH22DONE,"
line.long 0x80 "SIGDMACH23DONE,"
line.long 0x84 "SIGDMACH24DONE,"
line.long 0x88 "SIGDMACH25DONE,"
line.long 0x8C "SIGDMACH26DONE,"
line.long 0x90 "SIGDMACH27DONE,"
line.long 0x94 "SIGDMACH28DONE,"
line.long 0x98 "SIGDMACH29DONE,"
line.long 0x9C "SIGDMACH30DONE,"
line.long 0xA0 "SIGDMACH31DONE,"
line.long 0xA4 "FW2HWA_TRIG_0,"
bitfld.long 0xA4 0. "fw2hwa_trigger_0,Software trigger bit" "0,1"
line.long 0xA8 "FW2HWA_TRIG_1,"
bitfld.long 0xA8 0. "fw2hwa_trigger_1,Software trigger bit" "0,1"
line.long 0xAC "CS_FW2ACC_TRIG,"
bitfld.long 0xAC 0. "fw2hwa_trigger_cs,CPU can set this register bit to trigger a context switch when CS_TRIGMODE = 101b It s a Self clearing bit" "0,1"
line.long 0xB0 "BPM_PATTERN_0,"
line.long 0xB4 "BPM_PATTERN_1,"
line.long 0xB8 "BPM_PATTERN_2,"
line.long 0xBC "BPM_PATTERN_3,"
line.long 0xC0 "BPM_PATTERN_4,"
line.long 0xC4 "BPM_PATTERN_5,"
line.long 0xC8 "BPM_PATTERN_6,"
line.long 0xCC "BPM_PATTERN_7,"
line.long 0xD0 "BPM_RATE,"
hexmask.long.word 0xD0 0.--9. 1. "bpm_rate,BPM rate: Specifies the number of input samples corresponding to each BPM bit"
line.long 0xD4 "PARAM_DONE_SET_STATUS_0,"
line.long 0xD8 "PARAM_DONE_SET_STATUS_1,"
line.long 0xDC "PARAM_DONE_CLR_0,"
line.long 0xE0 "PARAM_DONE_CLR_1,"
line.long 0xE4 "TRIGGER_SET_STATUS_0,"
line.long 0xE8 "TRIGGER_SET_STATUS_1,"
line.long 0xEC "TRIGGER_SET_IN_CLR_0,"
bitfld.long 0xEC 0. "trigger_set_in_clr_0,Clear trigger_set_status : This register-bit when set clears the trigger status register TRIGGER_SET_STATUS_0 described above It s a Self clearing bit" "0,1"
line.long 0xF0 "TRIGGER_SET_IN_CLR_1,"
bitfld.long 0xF0 0. "trigger_set_in_clr_1,Clear trigger_set_status : This register-bit when set clears the trigger status register TRIGGER_SET_STATUS_1 described above It s a Self clearing bit" "0,1"
line.long 0xF4 "DC_EST_RESET_SW,"
bitfld.long 0xF4 0. "dc_est_reset_sw,Reset for all 12 DC estimation accumulators It s a Self clearing bit" "0,1"
line.long 0xF8 "DC_EST_CTRL,"
bitfld.long 0xF8 16.--19. "dc_est_shift,Programmable shift applied to all 12 accumulator outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0xF8 0.--8. 1. "dc_est_scale,9-bit scale applied to all 12 accumulators"
line.long 0xFC "DC_EST_I_0_VAL,"
hexmask.long.tbyte 0xFC 0.--23. 1. "dc_est_i_0_val,This read only register provide the DC estimates I for bcnt= 0"
line.long 0x100 "DC_EST_I_1_VAL,"
hexmask.long.tbyte 0x100 0.--23. 1. "dc_est_i_1_val,This read only register provide the DC estimates I for bcnt= 1"
line.long 0x104 "DC_EST_I_2_VAL,"
hexmask.long.tbyte 0x104 0.--23. 1. "dc_est_i_2_val,This read only register provide the DC estimates I for bcnt= 2"
line.long 0x108 "DC_EST_I_3_VAL,"
hexmask.long.tbyte 0x108 0.--23. 1. "dc_est_i_3_val,This read only register provide the DC estimates I for bcnt= 3"
line.long 0x10C "DC_EST_I_4_VAL,"
hexmask.long.tbyte 0x10C 0.--23. 1. "dc_est_i_4_val,This read only register provide the DC estimates I for bcnt= 4"
line.long 0x110 "DC_EST_I_5_VAL,"
hexmask.long.tbyte 0x110 0.--23. 1. "dc_est_i_5_val,This read only register provide the DC estimates I for bcnt= 5"
line.long 0x114 "DC_EST_I_6_VAL,"
hexmask.long.tbyte 0x114 0.--23. 1. "dc_est_i_6_val,This read only register provide the DC estimates I for bcnt= 6"
line.long 0x118 "DC_EST_I_7_VAL,"
hexmask.long.tbyte 0x118 0.--23. 1. "dc_est_i_7_val,This read only register provide the DC estimates I for bcnt= 7"
line.long 0x11C "DC_EST_I_8_VAL,"
hexmask.long.tbyte 0x11C 0.--23. 1. "dc_est_i_8_val,This read only register provide the DC estimates I for bcnt= 8"
line.long 0x120 "DC_EST_I_9_VAL,"
hexmask.long.tbyte 0x120 0.--23. 1. "dc_est_i_9_val,This read only register provide the DC estimates I for bcnt= 9"
line.long 0x124 "DC_EST_I_10_VAL,"
hexmask.long.tbyte 0x124 0.--23. 1. "dc_est_i_10_val,This read only register provide the DC estimates I for bcnt= 10"
line.long 0x128 "DC_EST_I_11_VAL,"
hexmask.long.tbyte 0x128 0.--23. 1. "dc_est_i_11_val,This read only register provide the DC estimates I for bcnt= 11"
line.long 0x12C "DC_EST_Q_0_VAL,"
hexmask.long.tbyte 0x12C 0.--23. 1. "dc_est_q_0_val,This read only register provide the DC estimates Q for bcnt= 0"
line.long 0x130 "DC_EST_Q_1_VAL,"
hexmask.long.tbyte 0x130 0.--23. 1. "dc_est_q_1_val,This read only register provide the DC estimates Q for bcnt= 1"
line.long 0x134 "DC_EST_Q_2_VAL,"
hexmask.long.tbyte 0x134 0.--23. 1. "dc_est_q_2_val,This read only register provide the DC estimates Q for bcnt= 2"
line.long 0x138 "DC_EST_Q_3_VAL,"
hexmask.long.tbyte 0x138 0.--23. 1. "dc_est_q_3_val,This read only register provide the DC estimates Q for bcnt= 3"
line.long 0x13C "DC_EST_Q_4_VAL,"
hexmask.long.tbyte 0x13C 0.--23. 1. "dc_est_q_4_val,This read only register provide the DC estimates Q for bcnt= 4"
line.long 0x140 "DC_EST_Q_5_VAL,"
hexmask.long.tbyte 0x140 0.--23. 1. "dc_est_q_5_val,This read only register provide the DC estimates Q for bcnt= 5"
line.long 0x144 "DC_EST_Q_6_VAL,"
hexmask.long.tbyte 0x144 0.--23. 1. "dc_est_q_6_val,This read only register provide the DC estimates Q for bcnt= 6"
line.long 0x148 "DC_EST_Q_7_VAL,"
hexmask.long.tbyte 0x148 0.--23. 1. "dc_est_q_7_val,This read only register provide the DC estimates Q for bcnt= 7"
line.long 0x14C "DC_EST_Q_8_VAL,"
hexmask.long.tbyte 0x14C 0.--23. 1. "dc_est_q_8_val,This read only register provide the DC estimates Q for bcnt= 8"
line.long 0x150 "DC_EST_Q_9_VAL,"
hexmask.long.tbyte 0x150 0.--23. 1. "dc_est_q_9_val,This read only register provide the DC estimates Q for bcnt= 9"
line.long 0x154 "DC_EST_Q_10_VAL,"
hexmask.long.tbyte 0x154 0.--23. 1. "dc_est_q_10_val,This read only register provide the DC estimates Q for bcnt= 10"
line.long 0x158 "DC_EST_Q_11_VAL,"
hexmask.long.tbyte 0x158 0.--23. 1. "dc_est_q_11_val,This read only register provide the DC estimates Q for bcnt= 11"
line.long 0x15C "DC_ACC_I_0_VAL_LSB,"
line.long 0x160 "DC_ACC_I_0_VAL_MSB,"
bitfld.long 0x160 0.--3. "dc_acc_i_0_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "DC_ACC_I_1_VAL_LSB,"
line.long 0x168 "DC_ACC_I_1_VAL_MSB,"
bitfld.long 0x168 0.--3. "dc_acc_i_1_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "DC_ACC_I_2_VAL_LSB,"
line.long 0x170 "DC_ACC_I_2_VAL_MSB,"
bitfld.long 0x170 0.--3. "dc_acc_i_2_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "DC_ACC_I_3_VAL_LSB,"
line.long 0x178 "DC_ACC_I_3_VAL_MSB,"
bitfld.long 0x178 0.--3. "dc_acc_i_3_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "DC_ACC_I_4_VAL_LSB,"
line.long 0x180 "DC_ACC_I_4_VAL_MSB,"
bitfld.long 0x180 0.--3. "dc_acc_i_4_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "DC_ACC_I_5_VAL_LSB,"
line.long 0x188 "DC_ACC_I_5_VAL_MSB,"
bitfld.long 0x188 0.--3. "dc_acc_i_5_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "DC_ACC_I_6_VAL_LSB,"
line.long 0x190 "DC_ACC_I_6_VAL_MSB,"
bitfld.long 0x190 0.--3. "dc_acc_i_6_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "DC_ACC_I_7_VAL_LSB,"
line.long 0x198 "DC_ACC_I_7_VAL_MSB,"
bitfld.long 0x198 0.--3. "dc_acc_i_7_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "DC_ACC_I_8_VAL_LSB,"
line.long 0x1A0 "DC_ACC_I_8_VAL_MSB,"
bitfld.long 0x1A0 0.--3. "dc_acc_i_8_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "DC_ACC_I_9_VAL_LSB,"
line.long 0x1A8 "DC_ACC_I_9_VAL_MSB,"
bitfld.long 0x1A8 0.--3. "dc_acc_i_9_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "DC_ACC_I_10_VAL_LSB,"
line.long 0x1B0 "DC_ACC_I_10_VAL_MSB,"
bitfld.long 0x1B0 0.--3. "dc_acc_i_10_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "DC_ACC_I_11_VAL_LSB,"
line.long 0x1B8 "DC_ACC_I_11_VAL_MSB,"
bitfld.long 0x1B8 0.--3. "dc_acc_i_11_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "DC_ACC_Q_0_VAL_LSB,"
line.long 0x1C0 "DC_ACC_Q_0_VAL_MSB,"
bitfld.long 0x1C0 0.--3. "dc_acc_q_0_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "DC_ACC_Q_1_VAL_LSB,"
line.long 0x1C8 "DC_ACC_Q_1_VAL_MSB,"
bitfld.long 0x1C8 0.--3. "dc_acc_q_1_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "DC_ACC_Q_2_VAL_LSB,"
line.long 0x1D0 "DC_ACC_Q_2_VAL_MSB,"
bitfld.long 0x1D0 0.--3. "dc_acc_q_2_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "DC_ACC_Q_3_VAL_LSB,"
line.long 0x1D8 "DC_ACC_Q_3_VAL_MSB,"
bitfld.long 0x1D8 0.--3. "dc_acc_q_3_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "DC_ACC_Q_4_VAL_LSB,"
line.long 0x1E0 "DC_ACC_Q_4_VAL_MSB,"
bitfld.long 0x1E0 0.--3. "dc_acc_q_4_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "DC_ACC_Q_5_VAL_LSB,"
line.long 0x1E8 "DC_ACC_Q_5_VAL_MSB,"
bitfld.long 0x1E8 0.--3. "dc_acc_q_5_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1EC "DC_ACC_Q_6_VAL_LSB,"
line.long 0x1F0 "DC_ACC_Q_6_VAL_MSB,"
bitfld.long 0x1F0 0.--3. "dc_acc_q_6_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F4 "DC_ACC_Q_7_VAL_LSB,"
line.long 0x1F8 "DC_ACC_Q_7_VAL_MSB,"
bitfld.long 0x1F8 0.--3. "dc_acc_q_7_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1FC "DC_ACC_Q_8_VAL_LSB,"
line.long 0x200 "DC_ACC_Q_8_VAL_MSB,"
bitfld.long 0x200 0.--3. "dc_acc_q_8_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x204 "DC_ACC_Q_9_VAL_LSB,"
line.long 0x208 "DC_ACC_Q_9_VAL_MSB,"
bitfld.long 0x208 0.--3. "dc_acc_q_9_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20C "DC_ACC_Q_10_VAL_LSB,"
line.long 0x210 "DC_ACC_Q_10_VAL_MSB,"
bitfld.long 0x210 0.--3. "dc_acc_q_10_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x214 "DC_ACC_Q_11_VAL_LSB,"
line.long 0x218 "DC_ACC_Q_11_VAL_MSB,"
bitfld.long 0x218 0.--3. "dc_acc_q_11_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x21C "DC_ACC_CLIP_STATUS,"
hexmask.long.word 0x21C 0.--11. 1. "dc_acc_clip_status,This register contains the clip status of both I/Q of DC accumulators 0 to 11"
line.long 0x220 "DC_EST_CLIP_STATUS,"
hexmask.long.word 0x220 0.--11. 1. "dc_est_clip_status,This register contains the clip status of DC estimates (both I & Q combined)"
line.long 0x224 "DC_I0_SW,"
hexmask.long.tbyte 0x224 0.--23. 1. "dc_i0_sw,SW programmed DC I value(for bcnt =0 ) used in DC subtraction"
line.long 0x228 "DC_I1_SW,"
hexmask.long.tbyte 0x228 0.--23. 1. "dc_i1_sw,SW programmed DC I value(for bcnt =1) used in DC subtraction"
line.long 0x22C "DC_I2_SW,"
hexmask.long.tbyte 0x22C 0.--23. 1. "dc_i2_sw,SW programmed DC I value(for bcnt =2 ) used in DC subtraction"
line.long 0x230 "DC_I3_SW,"
hexmask.long.tbyte 0x230 0.--23. 1. "dc_i3_sw,SW programmed DC I value(for bcnt =3) used in DC subtraction"
line.long 0x234 "DC_I4_SW,"
hexmask.long.tbyte 0x234 0.--23. 1. "dc_i4_sw,SW programmed DC I value(for bcnt =4 ) used in DC subtraction"
line.long 0x238 "DC_I5_SW,"
hexmask.long.tbyte 0x238 0.--23. 1. "dc_i5_sw,SW programmed DC I value(for bcnt =5 ) used in DC subtraction"
line.long 0x23C "DC_I6_SW,"
hexmask.long.tbyte 0x23C 0.--23. 1. "dc_i6_sw,SW programmed DC I value(for bcnt =6 ) used in DC subtraction"
line.long 0x240 "DC_I7_SW,"
hexmask.long.tbyte 0x240 0.--23. 1. "dc_i7_sw,SW programmed DC I value(for bcnt =7 ) used in DC subtraction"
line.long 0x244 "DC_I8_SW,"
hexmask.long.tbyte 0x244 0.--23. 1. "dc_i8_sw,SW programmed DC I value(for bcnt =8) used in DC subtraction"
line.long 0x248 "DC_I9_SW,"
hexmask.long.tbyte 0x248 0.--23. 1. "dc_i9_sw,SW programmed DC I value(for bcnt =9 ) used in DC subtraction"
line.long 0x24C "DC_I10_SW,"
hexmask.long.tbyte 0x24C 0.--23. 1. "dc_i10_sw,SW programmed DC I value(for bcnt =10 ) used in DC subtraction"
line.long 0x250 "DC_I11_SW,"
hexmask.long.tbyte 0x250 0.--23. 1. "dc_i11_sw,SW programmed DC I value(for bcnt =11) used in DC subtraction"
line.long 0x254 "DC_Q0_SW,"
hexmask.long.tbyte 0x254 0.--23. 1. "dc_q0_sw,SW programmed DC Q value(for bcnt =0 ) used in DC subtraction"
line.long 0x258 "DC_Q1_SW,"
hexmask.long.tbyte 0x258 0.--23. 1. "dc_q1_sw,SW programmed DC Q value(for bcnt =1) used in DC subtraction"
line.long 0x25C "DC_Q2_SW,"
hexmask.long.tbyte 0x25C 0.--23. 1. "dc_q2_sw,SW programmed DC Q value(for bcnt =2 ) used in DC subtraction"
line.long 0x260 "DC_Q3_SW,"
hexmask.long.tbyte 0x260 0.--23. 1. "dc_q3_sw,SW programmed DC Q value(for bcnt =3) used in DC subtraction"
line.long 0x264 "DC_Q4_SW,"
hexmask.long.tbyte 0x264 0.--23. 1. "dc_q4_sw,SW programmed DC Q value(for bcnt =4 ) used in DC subtraction"
line.long 0x268 "DC_Q5_SW,"
hexmask.long.tbyte 0x268 0.--23. 1. "dc_q5_sw,SW programmed DC Q value(for bcnt =5 ) used in DC subtraction"
line.long 0x26C "DC_Q6_SW,"
hexmask.long.tbyte 0x26C 0.--23. 1. "dc_q6_sw,SW programmed DC Q value(for bcnt =6 ) used in DC subtraction"
line.long 0x270 "DC_Q7_SW,"
hexmask.long.tbyte 0x270 0.--23. 1. "dc_q7_sw,SW programmed DC Q value(for bcnt =7 ) used in DC subtraction"
line.long 0x274 "DC_Q8_SW,"
hexmask.long.tbyte 0x274 0.--23. 1. "dc_q8_sw,SW programmed DC Q value(for bcnt =8) used in DC subtraction"
line.long 0x278 "DC_Q9_SW,"
hexmask.long.tbyte 0x278 0.--23. 1. "dc_q9_sw,SW programmed DC Q value(for bcnt =9 ) used in DC subtraction"
line.long 0x27C "DC_Q10_SW,"
hexmask.long.tbyte 0x27C 0.--23. 1. "dc_q10_sw,SW programmed DC Q value(for bcnt =10 ) used in DC subtraction"
line.long 0x280 "DC_Q11_SW,"
hexmask.long.tbyte 0x280 0.--23. 1. "dc_q11_sw,SW programmed DC Q value(for bcnt =11) used in DC subtraction"
line.long 0x284 "DC_SUB_CLIP,"
bitfld.long 0x284 0. "DC_SUB_CLIP,Indicates the DC subtraction clip status" "0,1"
line.long 0x288 "DC_RESERVED_2,"
line.long 0x28C "DC_RESERVED_3,"
line.long 0x290 "DC_RESERVED_4,"
line.long 0x294 "DC_RESERVED_5,"
line.long 0x298 "INTF_STATS_RESET_SW,"
bitfld.long 0x298 0. "intf_stats_reset_sw,SW reset for Interference stats module" "0,1"
line.long 0x29C "INTF_STATS_CTRL,"
hexmask.long.byte 0x29C 24.--31. 1. "intf_stats_magdiff_scale,Unsigned scaler (5.3) applied to INTERFSUM_MAGDIFFn from interference statistics block"
newline
hexmask.long.byte 0x29C 16.--23. 1. "intf_stats_mag_scale,Unsigned scaler (5.3) applied to INTERFSUM_MAGn from interference statistics block"
newline
bitfld.long 0x29C 4.--6. "intf_stats_magdiff_shift,Right shift applied after scaling - 2^(6+INTERFSUM_MAGDIFF_SHIFT)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x29C 0.--2. "intf_stats_mag_shift,Right shift applied after scaling - 2^(6+INTERSUM_MAGS_SHIFT)" "0,1,2,3,4,5,6,7"
line.long 0x2A0 "INTF_LOC_THRESH_MAG0_VAL,"
hexmask.long.tbyte 0x2A0 0.--23. 1. "intf_loc_thresh_mag0_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =0"
line.long 0x2A4 "INTF_LOC_THRESH_MAG1_VAL,"
hexmask.long.tbyte 0x2A4 0.--23. 1. "intf_loc_thresh_mag1_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =1"
line.long 0x2A8 "INTF_LOC_THRESH_MAG2_VAL,"
hexmask.long.tbyte 0x2A8 0.--23. 1. "intf_loc_thresh_mag2_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =2"
line.long 0x2AC "INTF_LOC_THRESH_MAG3_VAL,"
hexmask.long.tbyte 0x2AC 0.--23. 1. "intf_loc_thresh_mag3_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =3"
line.long 0x2B0 "INTF_LOC_THRESH_MAG4_VAL,"
hexmask.long.tbyte 0x2B0 0.--23. 1. "intf_loc_thresh_mag4_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =4"
line.long 0x2B4 "INTF_LOC_THRESH_MAG5_VAL,"
hexmask.long.tbyte 0x2B4 0.--23. 1. "intf_loc_thresh_mag5_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =5"
line.long 0x2B8 "INTF_LOC_THRESH_MAG6_VAL,"
hexmask.long.tbyte 0x2B8 0.--23. 1. "intf_loc_thresh_mag6_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =6"
line.long 0x2BC "INTF_LOC_THRESH_MAG7_VAL,"
hexmask.long.tbyte 0x2BC 0.--23. 1. "intf_loc_thresh_mag7_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =7"
line.long 0x2C0 "INTF_LOC_THRESH_MAG8_VAL,"
hexmask.long.tbyte 0x2C0 0.--23. 1. "intf_loc_thresh_mag8_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =8"
line.long 0x2C4 "INTF_LOC_THRESH_MAG9_VAL,"
hexmask.long.tbyte 0x2C4 0.--23. 1. "intf_loc_thresh_mag9_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =9"
line.long 0x2C8 "INTF_LOC_THRESH_MAG10_VAL,"
hexmask.long.tbyte 0x2C8 0.--23. 1. "intf_loc_thresh_mag10_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =10"
line.long 0x2CC "INTF_LOC_THRESH_MAG11_VAL,"
hexmask.long.tbyte 0x2CC 0.--23. 1. "intf_loc_thresh_mag11_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =11"
line.long 0x2D0 "INTF_LOC_THRESH_MAGDIFF0_VAL,"
hexmask.long.tbyte 0x2D0 0.--23. 1. "intf_loc_thresh_magdiff0_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =0"
line.long 0x2D4 "INTF_LOC_THRESH_MAGDIFF1_VAL,"
hexmask.long.tbyte 0x2D4 0.--23. 1. "intf_loc_thresh_magdiff1_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =1"
line.long 0x2D8 "INTF_LOC_THRESH_MAGDIFF2_VAL,"
hexmask.long.tbyte 0x2D8 0.--23. 1. "intf_loc_thresh_magdiff2_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =2"
line.long 0x2DC "INTF_LOC_THRESH_MAGDIFF3_VAL,"
hexmask.long.tbyte 0x2DC 0.--23. 1. "intf_loc_thresh_magdiff3_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =3"
line.long 0x2E0 "INTF_LOC_THRESH_MAGDIFF4_VAL,"
hexmask.long.tbyte 0x2E0 0.--23. 1. "intf_loc_thresh_magdiff4_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =4"
line.long 0x2E4 "INTF_LOC_THRESH_MAGDIFF5_VAL,"
hexmask.long.tbyte 0x2E4 0.--23. 1. "intf_loc_thresh_magdiff5_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =5"
line.long 0x2E8 "INTF_LOC_THRESH_MAGDIFF6_VAL,"
hexmask.long.tbyte 0x2E8 0.--23. 1. "intf_loc_thresh_magdiff6_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =6"
line.long 0x2EC "INTF_LOC_THRESH_MAGDIFF7_VAL,"
hexmask.long.tbyte 0x2EC 0.--23. 1. "intf_loc_thresh_magdiff7_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =7"
line.long 0x2F0 "INTF_LOC_THRESH_MAGDIFF8_VAL,"
hexmask.long.tbyte 0x2F0 0.--23. 1. "intf_loc_thresh_magdiff8_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =8"
line.long 0x2F4 "INTF_LOC_THRESH_MAGDIFF9_VAL,"
hexmask.long.tbyte 0x2F4 0.--23. 1. "intf_loc_thresh_magdiff9_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =9"
line.long 0x2F8 "INTF_LOC_THRESH_MAGDIFF10_VAL,"
hexmask.long.tbyte 0x2F8 0.--23. 1. "intf_loc_thresh_magdiff10_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =10"
line.long 0x2FC "INTF_LOC_THRESH_MAGDIFF11_VAL,"
hexmask.long.tbyte 0x2FC 0.--23. 1. "intf_loc_thresh_magdiff11_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =11"
line.long 0x300 "INTF_LOC_COUNT_ALL_CHIRP,"
hexmask.long.word 0x300 0.--11. 1. "intf_loc_count_all_chirp,Number of samples that exceeded the threshold in a chirp"
line.long 0x304 "INTF_LOC_COUNT_ALL_FRAME,"
hexmask.long.tbyte 0x304 0.--19. 1. "intf_loc_count_all_frame,Number of samples that exceeded the threshold in a frame"
line.long 0x308 "INTF_STATS_MAG_ACC_0_LSB,"
line.long 0x30C "INTF_STATS_MAG_ACC_0_MSB,"
bitfld.long 0x30C 0.--3. "intf_stats_mag_acc_0_msb,This read only register contains the accumulator value of interference magnitude(MSB 4 bits) for bcnt = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x310 "INTF_STATS_MAG_ACC_1_LSB,"
line.long 0x314 "INTF_STATS_MAG_ACC_1_MSB,"
bitfld.long 0x314 0.--3. "intf_stats_mag_acc_1_msb,This read only contains the accumulator value of interference magnitude (MSB 4 bits) for bcnt = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x318 "INTF_STATS_MAG_ACC_2_LSB,"
line.long 0x31C "INTF_STATS_MAG_ACC_2_MSB,"
bitfld.long 0x31C 0.--3. "intf_stats_mag_acc_2_msb,This read only register contains the accumulator value of interference magnitude (MSB 4 bits) for bcnt = 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x320 "INTF_STATS_MAG_ACC_3_LSB,"
line.long 0x324 "INTF_STATS_MAG_ACC_3_MSB,"
bitfld.long 0x324 0.--3. "intf_stats_mag_acc_3_msb,This read only register contains the accumulator value of the interference magnitude(for MSB 4 bits) for bcnt = 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x328 "INTF_STATS_MAG_ACC_4_LSB,"
line.long 0x32C "INTF_STATS_MAG_ACC_4_MSB,"
bitfld.long 0x32C 0.--3. "intf_stats_mag_acc_4_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x330 "INTF_STATS_MAG_ACC_5_LSB,"
line.long 0x334 "INTF_STATS_MAG_ACC_5_MSB,"
bitfld.long 0x334 0.--3. "intf_stats_mag_acc_5_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x338 "INTF_STATS_MAG_ACC_6_LSB,"
line.long 0x33C "INTF_STATS_MAG_ACC_6_MSB,"
bitfld.long 0x33C 0.--3. "intf_stats_mag_acc_6_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x340 "INTF_STATS_MAG_ACC_7_LSB,"
line.long 0x344 "INTF_STATS_MAG_ACC_7_MSB,"
bitfld.long 0x344 0.--3. "intf_stats_mag_acc_7_msb,This read only register contains the accumulator value of the interference magnitude (MSB4 bits)for bcnt = 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x348 "INTF_STATS_MAG_ACC_8_LSB,"
line.long 0x34C "INTF_STATS_MAG_ACC_8_MSB,"
bitfld.long 0x34C 0.--3. "intf_stats_mag_acc_8_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x350 "INTF_STATS_MAG_ACC_9_LSB,"
line.long 0x354 "INTF_STATS_MAG_ACC_9_MSB,"
bitfld.long 0x354 0.--3. "intf_stats_mag_acc_9_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x358 "INTF_STATS_MAG_ACC_10_LSB,"
line.long 0x35C "INTF_STATS_MAG_ACC_10_MSB,"
bitfld.long 0x35C 0.--3. "intf_stats_mag_acc_10_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x360 "INTF_STATS_MAG_ACC_11_LSB,"
line.long 0x364 "INTF_STATS_MAG_ACC_11_MSB,"
bitfld.long 0x364 0.--3. "intf_stats_mag_acc_11_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x368 "INTF_STATS_MAGDIFF_ACC_0_LSB,"
line.long 0x36C "INTF_STATS_MAGDIFF_ACC_0_MSB,"
bitfld.long 0x36C 0.--3. "intf_stats_magdiff_acc_0_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x370 "INTF_STATS_MAGDIFF_ACC_1_LSB,"
line.long 0x374 "INTF_STATS_MAGDIFF_ACC_1_MSB,"
bitfld.long 0x374 0.--3. "intf_stats_magdiff_acc_1_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x378 "INTF_STATS_MAGDIFF_ACC_2_LSB,"
line.long 0x37C "INTF_STATS_MAGDIFF_ACC_2_MSB,"
bitfld.long 0x37C 0.--3. "intf_stats_magdiff_acc_2_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x380 "INTF_STATS_MAGDIFF_ACC_3_LSB,"
line.long 0x384 "INTF_STATS_MAGDIFF_ACC_3_MSB,"
bitfld.long 0x384 0.--3. "intf_stats_magdiff_acc_3_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x388 "INTF_STATS_MAGDIFF_ACC_4_LSB,"
line.long 0x38C "INTF_STATS_MAGDIFF_ACC_4_MSB,"
bitfld.long 0x38C 0.--3. "intf_stats_magdiff_acc_4_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x390 "INTF_STATS_MAGDIFF_ACC_5_LSB,"
line.long 0x394 "INTF_STATS_MAGDIFF_ACC_5_MSB,"
bitfld.long 0x394 0.--3. "intf_stats_magdiff_acc_5_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x398 "INTF_STATS_MAGDIFF_ACC_6_LSB,"
line.long 0x39C "INTF_STATS_MAGDIFF_ACC_6_MSB,"
bitfld.long 0x39C 0.--3. "intf_stats_magdiff_acc_6_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A0 "INTF_STATS_MAGDIFF_ACC_7_LSB,"
line.long 0x3A4 "INTF_STATS_MAGDIFF_ACC_7_MSB,"
bitfld.long 0x3A4 0.--3. "intf_stats_magdiff_acc_7_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A8 "INTF_STATS_MAGDIFF_ACC_8_LSB,"
line.long 0x3AC "INTF_STATS_MAGDIFF_ACC_8_MSB,"
bitfld.long 0x3AC 0.--3. "intf_stats_magdiff_acc_8_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B0 "INTF_STATS_MAGDIFF_ACC_9_LSB,"
line.long 0x3B4 "INTF_STATS_MAGDIFF_ACC_9_MSB,"
bitfld.long 0x3B4 0.--3. "intf_stats_magdiff_acc_9_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B8 "INTF_STATS_MAGDIFF_ACC_10_LSB,"
line.long 0x3BC "INTF_STATS_MAGDIFF_ACC_10_MSB,"
bitfld.long 0x3BC 0.--3. "intf_stats_magdiff_acc_10_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C0 "INTF_STATS_MAGDIFF_ACC_11_LSB,"
line.long 0x3C4 "INTF_STATS_MAGDIFF_ACC_11_MSB,"
bitfld.long 0x3C4 0.--3. "intf_stats_magdiff_acc_11_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C8 "INTF_LOC_THRESH_MAG0_SW,"
hexmask.long.tbyte 0x3C8 0.--23. 1. "intf_loc_thresh_mag0_sw,SW programmed interface threshold magnitude for bcnt=0"
line.long 0x3CC "INTF_LOC_THRESH_MAG1_SW,"
hexmask.long.tbyte 0x3CC 0.--23. 1. "intf_loc_thresh_mag1_sw,SW programmed interface threshold magnitude for bcnt=1"
line.long 0x3D0 "INTF_LOC_THRESH_MAG2_SW,"
hexmask.long.tbyte 0x3D0 0.--23. 1. "intf_loc_thresh_mag2_sw,SW programmed interface threshold magnitude for bcnt=2"
line.long 0x3D4 "INTF_LOC_THRESH_MAG3_SW,"
hexmask.long.tbyte 0x3D4 0.--23. 1. "intf_loc_thresh_mag3_sw,SW programmed interface threshold magnitude for bcnt=3"
line.long 0x3D8 "INTF_LOC_THRESH_MAG4_SW,"
hexmask.long.tbyte 0x3D8 0.--23. 1. "intf_loc_thresh_mag4_sw,SW programmed interface threshold magnitude for bcnt=4"
line.long 0x3DC "INTF_LOC_THRESH_MAG5_SW,"
hexmask.long.tbyte 0x3DC 0.--23. 1. "intf_loc_thresh_mag5_sw,SW programmed interface threshold magnitude for bcnt=5"
line.long 0x3E0 "INTF_LOC_THRESH_MAG6_SW,"
hexmask.long.tbyte 0x3E0 0.--23. 1. "intf_loc_thresh_mag6_sw,SW programmed interface threshold magnitude for bcnt=6"
line.long 0x3E4 "INTF_LOC_THRESH_MAG7_SW,"
hexmask.long.tbyte 0x3E4 0.--23. 1. "intf_loc_thresh_mag7_sw,SW programmed interface threshold magnitude for bcnt=7"
line.long 0x3E8 "INTF_LOC_THRESH_MAG8_SW,"
hexmask.long.tbyte 0x3E8 0.--23. 1. "intf_loc_thresh_mag8_sw,SW programmed interface threshold magnitude for bcnt=8"
line.long 0x3EC "INTF_LOC_THRESH_MAG9_SW,"
hexmask.long.tbyte 0x3EC 0.--23. 1. "intf_loc_thresh_mag9_sw,SW programmed interface threshold magnitude for bcnt=9"
line.long 0x3F0 "INTF_LOC_THRESH_MAG10_SW,"
hexmask.long.tbyte 0x3F0 0.--23. 1. "intf_loc_thresh_mag10_sw,SW programmed interface threshold magnitude for bcnt=10"
line.long 0x3F4 "INTF_LOC_THRESH_MAG11_SW,"
hexmask.long.tbyte 0x3F4 0.--23. 1. "intf_loc_thresh_mag11_sw,SW programmed interface threshold magnitude for bcnt=11"
line.long 0x3F8 "INTF_LOC_THRESH_MAGDIFF0_SW,"
hexmask.long.tbyte 0x3F8 0.--23. 1. "intf_loc_thresh_magdiff0_sw,SW programmed interface threshold magnitude difference for bcnt=0"
line.long 0x3FC "INTF_LOC_THRESH_MAGDIFF1_SW,"
hexmask.long.tbyte 0x3FC 0.--23. 1. "intf_loc_thresh_magdiff1_sw,SW programmed interface threshold magnitude difference for bcnt=1"
line.long 0x400 "INTF_LOC_THRESH_MAGDIFF2_SW,"
hexmask.long.tbyte 0x400 0.--23. 1. "intf_loc_thresh_magdiff2_sw,SW programmed interface threshold magnitude difference for bcnt=2"
line.long 0x404 "INTF_LOC_THRESH_MAGDIFF3_SW,"
hexmask.long.tbyte 0x404 0.--23. 1. "intf_loc_thresh_magdiff3_sw,SW programmed interface threshold magnitude difference for bcnt=3"
line.long 0x408 "INTF_LOC_THRESH_MAGDIFF4_SW,"
hexmask.long.tbyte 0x408 0.--23. 1. "intf_loc_thresh_magdiff4_sw,SW programmed interface threshold magnitude difference for bcnt=4"
line.long 0x40C "INTF_LOC_THRESH_MAGDIFF5_SW,"
hexmask.long.tbyte 0x40C 0.--23. 1. "intf_loc_thresh_magdiff5_sw,SW programmed interface threshold magnitude difference for bcnt=5"
line.long 0x410 "INTF_LOC_THRESH_MAGDIFF6_SW,"
hexmask.long.tbyte 0x410 0.--23. 1. "intf_loc_thresh_magdiff6_sw,SW programmed interface threshold magnitude difference for bcnt=6"
line.long 0x414 "INTF_LOC_THRESH_MAGDIFF7_SW,"
hexmask.long.tbyte 0x414 0.--23. 1. "intf_loc_thresh_magdiff7_sw,SW programmed interface threshold magnitude difference for bcnt=7"
line.long 0x418 "INTF_LOC_THRESH_MAGDIFF8_SW,"
hexmask.long.tbyte 0x418 0.--23. 1. "intf_loc_thresh_magdiff8_sw,SW programmed interface threshold magnitude difference for bcnt=8"
line.long 0x41C "INTF_LOC_THRESH_MAGDIFF9_SW,"
hexmask.long.tbyte 0x41C 0.--23. 1. "intf_loc_thresh_magdiff9_sw,SW programmed interface threshold magnitude difference for bcnt=9"
line.long 0x420 "INTF_LOC_THRESH_MAGDIFF10_SW,"
hexmask.long.tbyte 0x420 0.--23. 1. "intf_loc_thresh_magdiff10_sw,SW programmed interface threshold magnitude difference for bcnt=10"
line.long 0x424 "INTF_LOC_THRESH_MAGDIFF11_SW,"
hexmask.long.tbyte 0x424 0.--23. 1. "intf_loc_thresh_magdiff11_sw,SW programmed interface threshold magnitude difference for bcnt=11"
line.long 0x428 "INTF_STATS_ACC_CLIP_STATUS,"
hexmask.long.word 0x428 16.--27. 1. "intf_stats_magdiff_accumulator_clip_status,Interference magnitue difference accumulator Clip status"
newline
hexmask.long.word 0x428 0.--11. 1. "intf_stats_mag_accumulator_clip_status,Interference magnitue accumulator Clip status"
line.long 0x42C "INTF_STATS_THRESH_CLIP_STATUS,"
hexmask.long.word 0x42C 16.--27. 1. "intf_stats_thresh_magdiff_clip_status,Interference magnitude difference threshold Clip status"
newline
hexmask.long.word 0x42C 0.--11. 1. "intf_stats_thresh_mag_clip_status,Interference magnitude threshold Clip status"
line.long 0x430 "INTF_MITG_WINDOW_PARAM_0,"
bitfld.long 0x430 0.--4. "intf_mitg_window_param_0,This is a programmable array of window parameters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x434 "INTF_MITG_WINDOW_PARAM_1,"
bitfld.long 0x434 0.--4. "intf_mitg_window_param_1,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x438 "INTF_MITG_WINDOW_PARAM_2,"
bitfld.long 0x438 0.--4. "intf_mitg_window_param_2,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x43C "INTF_MITG_WINDOW_PARAM_3,"
bitfld.long 0x43C 0.--4. "intf_mitg_window_param_3,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x440 "INTF_MITG_WINDOW_PARAM_4,"
bitfld.long 0x440 0.--4. "intf_mitg_window_param_4,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x444 "INTF_STATS_SUM_MAG_VAL,"
hexmask.long.tbyte 0x444 0.--23. 1. "intf_stats_sum_mag_val,Indicates the sum of mag values ; Only Configured BCNT mag values are added"
line.long 0x448 "INTF_STATS_SUM_MAG_VAL_CLIP_STATUS,"
bitfld.long 0x448 0. "intf_stats_sum_mag_val_clip_status,Indicates the clip status of sum of mag values" "0,1"
line.long 0x44C "INTF_STATS_SUM_MAGDIFF_VAL,"
hexmask.long.tbyte 0x44C 0.--23. 1. "intf_stats_sum_magdiff_val,Indicates the sum of magdiff values ; Only Configured BCNT magdiff values are added"
line.long 0x450 "INTF_STATS_SUM_MAGDIFF_VAL_CLIP_STATUS,"
bitfld.long 0x450 0. "intf_stats_sum_magdiff_val_clip_status,indicates the clip status of sum of magdiff values" "0,1"
line.long 0x454 "INTERF_RESERVED_5,"
group.long 0x4B8++0x1BB
line.long 0x00 "TWID_INCR_DELTA_FRAC,"
hexmask.long.word 0x00 0.--9. 1. "twid_incr_delta_frac,Used in complex multiplier mode 10 Delta Fractional frequency increment per param-set looping Instantaneous frequency is (TWIDINCR << 10) +TWID_INCR_DELTA_ FRAC*c c is current execution count of the parameter set"
line.long 0x04 "RECWIN_RESET_SW,"
bitfld.long 0x04 0. "recwin_reset_sw,This resets the param set counter / execution counter used in Complex multiplier mode 8" "0,1"
line.long 0x08 "TWID_INCR_DELTA_FRAC_RESET_SW,"
bitfld.long 0x08 0. "twid_incr_delta_frac_reset_sw,This resets the param set counter used in Complex multiplier mode 10" "0,1"
line.long 0x0C "TWID_INCR_DELTA_FRAC_CLIP_STATUS,"
bitfld.long 0x0C 0. "twid_incr_delta_frac_clip_status,Indicates the clip status for TWID_INCR_DELTA_FRAC accumulator" "0,1"
line.long 0x10 "RECWIN_INIT_KVAL,"
hexmask.long.word 0x10 0.--11. 1. "recwin_init_kval,Indicates the initialization value of execution counter in recursive window mode"
line.long 0x14 "CMULT_RESERVED_2,"
line.long 0x18 "CHAN_COMB_SIZE,"
hexmask.long.byte 0x18 0.--7. 1. "chan_comb_size,Number of samples after combination"
line.long 0x1C "CHAN_COMB_VEC_0,"
line.long 0x20 "CHAN_COMB_VEC_1,"
line.long 0x24 "CHAN_COMB_VEC_2,"
line.long 0x28 "CHAN_COMB_VEC_3,"
line.long 0x2C "CHAN_COMB_VEC_4,"
line.long 0x30 "CHAN_COMB_VEC_5,"
line.long 0x34 "CHAN_COMB_VEC_6,"
line.long 0x38 "CHAN_COMB_VEC_7,"
line.long 0x3C "CHANNEL_COMB_CLIP_STATUS,"
bitfld.long 0x3C 0. "channel_comb_clip_status,Indicates the clip status of the channel combination" "0,1"
line.long 0x40 "ZERO_INSERT_NUM,"
hexmask.long.byte 0x40 0.--7. 1. "zero_insert_num,Number of zeros to be inserted in an iteration"
line.long 0x44 "ZERO_INSERT_MASK_0,"
line.long 0x48 "ZERO_INSERT_MASK_1,"
line.long 0x4C "ZERO_INSERT_MASK_2,"
line.long 0x50 "ZERO_INSERT_MASK_3,"
line.long 0x54 "ZERO_INSERT_MASK_4,"
line.long 0x58 "ZERO_INSERT_MASK_5,"
line.long 0x5C "ZERO_INSERT_MASK_6,"
line.long 0x60 "ZERO_INSERT_MASK_7,"
line.long 0x64 "ZERO_INSERT_RESERVED_1,"
line.long 0x68 "ZERO_INSERT_RESERVED_2,"
line.long 0x6C "ZERO_INSERT_RESERVED_3,"
line.long 0x70 "ZERO_INSERT_RESERVED_4,"
line.long 0x74 "LFSR_SEED,"
hexmask.long 0x74 0.--28. 1. "lfsr_seed,Seed for LFSR (random pattern): For twiddle factor dithering there is an LFSR that is used whose seed value is loaded by writing to this 29-bit LFSRSEED register"
line.long 0x78 "LFSR_LOAD,"
bitfld.long 0x78 0. "lfsr_load,Its self clearing bit" "0,1"
line.long 0x7C "DITHER_TWID_EN,"
bitfld.long 0x7C 0. "dither_twid_en,Twiddle factor dithering enable: This register-bit is used to enable and disable dithering of twiddle factors in the FFT" "0,1"
line.long 0x80 "FFT_CLIP,"
hexmask.long.word 0x80 0.--12. 1. "fft_clip,FFT Clip Status (read-only): This is a read-only status register which indicates any saturation/clipping events that have happened in the FFT butterfly stages"
line.long 0x84 "CLR_FFTCLIP,"
bitfld.long 0x84 0. "clr_fftclip,Clear FFT Clip Status register: This register bit when set clears the FFTCLIP register" "0,1"
line.long 0x88 "CLR_CLIP_MISC,"
bitfld.long 0x88 0. "clr_clip_status,This clears the following clip register channel_comb_clip_status dc_acc_clip_status dc_est_clip_status intf_stats_mag_accumulator_clip_status intf_stats_magdiff_accumulator_clip_status intf_stats_thresh_mag_clip_status.." "0,1"
line.long 0x8C "IP_OP_FORMATTER_CLIP_STATUS,"
bitfld.long 0x8C 16. "op_formatter_clip_status,Indicates the output formatter clip status" "0,1"
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bitfld.long 0x8C 0. "ip_formatter_clip_status,Indicates the input formatter clip status" "0,1"
line.long 0x90 "FFT_RESERVED_1,"
line.long 0x94 "FFT_RESERVED_2,"
line.long 0x98 "FFT_RESERVED_3,"
line.long 0x9C "MAX1_VALUE,"
hexmask.long.tbyte 0x9C 0.--23. 1. "max1_value,These registers contain the max value on a per-iteration basis"
line.long 0xA0 "MAX2_VALUE,"
hexmask.long.tbyte 0xA0 0.--23. 1. "max2_value,These registers contain the max value on a per-iteration basis"
line.long 0xA4 "MAX3_VALUE,"
hexmask.long.tbyte 0xA4 0.--23. 1. "max3_value,These registers contain the max value on a per-iteration basis"
line.long 0xA8 "MAX4_VALUE,"
hexmask.long.tbyte 0xA8 0.--23. 1. "max4_value,These registers contain the max value on a per-iteration basis"
line.long 0xAC "MAX1_INDEX,"
hexmask.long.word 0xAC 0.--11. 1. "max1_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xB0 "MAX2_INDEX,"
hexmask.long.word 0xB0 0.--11. 1. "max2_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xB4 "MAX3_INDEX,"
hexmask.long.word 0xB4 0.--11. 1. "max3_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xB8 "MAX4_INDEX,"
hexmask.long.word 0xB8 0.--11. 1. "max4_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xBC "I_SUM1_LSB,"
line.long 0xC0 "I_SUM1_MSB,"
bitfld.long 0xC0 0.--3. "i_sum1_msb,I Sum value 1 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "I_SUM2_LSB,"
line.long 0xC8 "I_SUM2_MSB,"
bitfld.long 0xC8 0.--3. "i_sum2_msb,I Sum value 2 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "I_SUM3_LSB,"
line.long 0xD0 "I_SUM3_MSB,"
bitfld.long 0xD0 0.--3. "i_sum3_msb,I Sum value 3 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "I_SUM4_LSB,"
line.long 0xD8 "I_SUM4_MSB,"
bitfld.long 0xD8 0.--3. "i_sum4_msb,I Sum value 4 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "Q_SUM1_LSB,"
line.long 0xE0 "Q_SUM1_MSB,"
bitfld.long 0xE0 0.--3. "q_sum1_msb,Q Sum value 1 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "Q_SUM2_LSB,"
line.long 0xE8 "Q_SUM2_MSB,"
bitfld.long 0xE8 0.--3. "q_sum2_msb,Q Sum value 2 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "Q_SUM3_LSB,"
line.long 0xF0 "Q_SUM3_MSB,"
bitfld.long 0xF0 0.--3. "q_sum3_msb,Q Sum value 3 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "Q_SUM4_LSB,"
line.long 0xF8 "Q_SUM4_MSB,"
bitfld.long 0xF8 0.--3. "q_sum4_msb,Q Sum value 4 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "FFTSUMDIV,"
bitfld.long 0xFC 0.--4. "fftsumdiv,Right-shifting for Sum statistic: This register specifies the number of bits to right-shift the sum statistic before it is written to destination memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x100 "MAX2D_OFFSET_DIM1,"
hexmask.long.tbyte 0x100 0.--23. 1. "max2d_offset_dim1,Offset to be added to dimension 1 Maxima results"
line.long 0x104 "MAX2D_OFFSET_DIM2,"
hexmask.long.tbyte 0x104 0.--23. 1. "max2d_offset_dim2,Offset to be added to dimension 2 Maxima results"
line.long 0x108 "CDF_CNT_THRESH,"
hexmask.long.word 0x108 0.--11. 1. "cdf_cnt_thresh,This register is applicable in CDF_CNT_THRESH mode of operation"
line.long 0x10C "STATS_RESERVED_1,"
line.long 0x110 "STATS_RESERVED_2,"
line.long 0x114 "STATS_RESERVED_3,"
line.long 0x118 "STATS_RESERVED_4,"
line.long 0x11C "STATS_RESERVED_5,"
line.long 0x120 "CFAR_PEAKCNT,"
hexmask.long.word 0x120 0.--11. 1. "cfar_peakcnt,CFAR detected peak count: This is a read-only register that contains the number of detected peaks that are logged in the destination memory when CFAR Engine is configured in Detected Peaks List mode"
line.long 0x124 "CFAR_DET_THR,"
hexmask.long.tbyte 0x124 0.--23. 1. "cfar_det_thr,To be added"
line.long 0x128 "CFAR_TEST_REG,"
hexmask.long.tbyte 0x128 0.--23. 1. "cfar_test_reg,To be added"
line.long 0x12C "CFAR_THRESH,"
hexmask.long.tbyte 0x12C 0.--17. 1. "cfar_thresh,Threshold scale factor: This register is used to specify the threshold scale factor"
line.long 0x130 "CFAR_RESERVED_1,"
line.long 0x134 "CFAR_RESERVED_2,"
line.long 0x138 "CFAR_RESERVED_3,"
line.long 0x13C "CFAR_RESERVED_4,"
line.long 0x140 "CMP_EGE_K0123,"
bitfld.long 0x140 24.--28. "cmp_ege_k3,3th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 16.--20. "cmp_ege_k2,2th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 8.--12. "cmp_ege_k1,1th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 0.--4. "cmp_ege_k0,0th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x144 "CMP_EGE_K4567,"
bitfld.long 0x144 24.--28. "cmp_ege_k7,7th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x144 16.--20. "cmp_ege_k6,6th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x144 8.--12. "cmp_ege_k5,5th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x144 0.--4. "cmp_ege_k4,4th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x148 "MEM_INIT_START,"
bitfld.long 0x148 14. "hist_odd_ram,writing 1'b1 would start the memory initialization for the Histogram memory 2 It s a self clearing bit" "0,1"
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bitfld.long 0x148 13. "hist_even_ram,writing 1'b1 would start the memory initialization for the Histogram memory 1 It s a self clearing bit" "0,1"
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bitfld.long 0x148 12. "per_iter_max_val_ram,writing 1'b1 would start the memory initialization for the 2D MAX per iteration RAM It s a self clearing bit" "0,1"
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bitfld.long 0x148 11. "per_sample_max_val_odd_ram,writing 1'b1 would start the memory initialization for the 2D MAX per sample RAM 2 It s a self clearing bit" "0,1"
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bitfld.long 0x148 10. "per_sample_max_val_even_ram,writing 1'b1 would start the memory initialization for the 2D MAX per sample RAM 1 It s a self clearing bit" "0,1"
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bitfld.long 0x148 9. "window_ram,writing 1'b1 would start the memory initialization for the window memory It s a self clearing bit" "0,1"
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bitfld.long 0x148 8. "param_ram,writing 1'b1 would start the memory initialization for the Param memory It s a self clearing bit" "0,1"
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bitfld.long 0x148 7. "dmem7,writing 1'b1 would start the memory initialization for the DMEM7 It s a self clearing bit" "0,1"
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bitfld.long 0x148 6. "dmem6,writing 1'b1 would start the memory initialization for the DMEM6 It s a self clearing bit" "0,1"
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bitfld.long 0x148 5. "dmem5,writing 1'b1 would start the memory initialization for the DMEM5 It s a self clearing bit" "0,1"
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bitfld.long 0x148 4. "dmem4,writing 1'b1 would start the memory initialization for the DMEM4 It s a self clearing bit" "0,1"
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bitfld.long 0x148 3. "dmem3,writing 1'b1 would start the memory initialization for the DMEM3 It s a self clearing bit" "0,1"
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bitfld.long 0x148 2. "dmem2,writing 1'b1 would start the memory initialization for the DMEM2 It s a self clearing bit" "0,1"
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bitfld.long 0x148 1. "dmem1,writing 1'b1 would start the memory initialization for the DMEM1" "0,1"
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bitfld.long 0x148 0. "dmem0,writing 1'b1 would start the memory initialization for the DMEM0 It s a self clearing bit" "0,1"
line.long 0x14C "MEM_INIT_DONE,"
bitfld.long 0x14C 14. "hist_odd_ram,Will be 1'b1 after cmpletion of memory initialization for hist_odd_ram" "0,1"
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bitfld.long 0x14C 13. "hist_even_ram,Will be 1'b1 after cmpletion of memory initialization for hist_even_ram" "0,1"
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bitfld.long 0x14C 12. "per_iteration_max_val_ram,Will be 1'b1 after cmpletion of memory initialization for per_iteration_max_val_ram" "0,1"
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bitfld.long 0x14C 11. "per_sample_max_val_odd_ram,Will be 1'b1 after cmpletion of memory initialization for per_sample_max_val_odd_ram" "0,1"
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bitfld.long 0x14C 10. "per_sample_max_val_even_ram,Will be 1'b1 after cmpletion of memory initialization for per_sample_max_val_even_ram" "0,1"
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bitfld.long 0x14C 9. "window_ram,Will be 1'b1 after cmpletion of memory initialization for window_ram" "0,1"
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bitfld.long 0x14C 8. "param_ram,Will be 1'b1 after cmpletion of memory initialization for param_ram" "0,1"
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bitfld.long 0x14C 7. "dmem7,Will be 1'b1 after cmpletion of memory initialization for dmem7" "0,1"
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bitfld.long 0x14C 6. "dmem6,Will be 1'b1 after cmpletion of memory initialization for dmem6" "0,1"
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bitfld.long 0x14C 5. "dmem5,Will be 1'b1 after cmpletion of memory initialization for dmem5" "0,1"
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bitfld.long 0x14C 4. "dmem4,Will be 1'b1 after cmpletion of memory initialization for dmem4" "0,1"
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bitfld.long 0x14C 3. "dmem3,Will be 1'b1 after cmpletion of memory initialization for dmem3" "0,1"
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bitfld.long 0x14C 2. "dmem2,Will be 1'b1 after cmpletion of memory initialization for dmem2" "0,1"
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bitfld.long 0x14C 1. "dmem1,Will be 1'b1 after cmpletion of memory initialization for dmem1" "0,1"
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bitfld.long 0x14C 0. "dmem0,Will be 1'b1 after cmpletion of memory initialization for dmem0" "0,1"
line.long 0x150 "MEM_INIT_STATUS,"
bitfld.long 0x150 14. "hist_odd_ram,Will be 1'b1 during memory initialization for hist_odd_ram" "0,1"
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bitfld.long 0x150 13. "hist_even_ram,Will be 1'b1 during memory initialization for hist_even_ram" "0,1"
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bitfld.long 0x150 12. "per_iteration_max_val_ram,Will be 1'b1 during memory initialization for per_iteration_max_val_ram" "0,1"
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bitfld.long 0x150 11. "per_sample_max_val_odd_ram,Will be 1'b1 during memory initialization for per_sample_max_val_odd_ram" "0,1"
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bitfld.long 0x150 10. "per_sample_max_val_even_ram,Will be 1'b1 during memory initialization for per_sample_max_val_even_ram" "0,1"
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bitfld.long 0x150 9. "window_ram,Will be 1'b1 during memory initialization for window_ram" "0,1"
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bitfld.long 0x150 8. "param_ram,Will be 1'b1 during memory initialization for param_ram" "0,1"
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bitfld.long 0x150 7. "dmem7,Will be 1'b1 during memory initialization for dmem7" "0,1"
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bitfld.long 0x150 6. "dmem6,Will be 1'b1 during memory initialization for dmem6" "0,1"
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bitfld.long 0x150 5. "dmem5,Will be 1'b1 during memory initialization for dmem5" "0,1"
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bitfld.long 0x150 4. "dmem4,Will be 1'b1 during memory initialization for dmem4" "0,1"
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bitfld.long 0x150 3. "dmem3,Will be 1'b1 during memory initialization for dmem3" "0,1"
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bitfld.long 0x150 2. "dmem2,Will be 1'b1 during memory initialization for dmem2" "0,1"
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bitfld.long 0x150 1. "dmem1,Will be 1'b1 during memory initialization for dmem1" "0,1"
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bitfld.long 0x150 0. "dmem0,Will be 1'b1 during memory initialization for dmem0" "0,1"
line.long 0x154 "LM_THRESH_VAL,"
hexmask.long.word 0x154 16.--31. 1. "dimc_thresh_val,Threshold value configured for Dimension C"
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hexmask.long.word 0x154 0.--15. 1. "dimb_thresh_val,Threshold value configured for Dimension B"
line.long 0x158 "LM_2DSTATS_BASE_ADDR,"
hexmask.long.word 0x158 16.--27. 1. "base_addr_dimc,Base Address in Stats RAM for the Threshold values corresponding to dimension C"
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hexmask.long.word 0x158 0.--11. 1. "base_addr_dimb,Base Address in Stats RAM for the Threshold values corresponding to dimension B"
line.long 0x15C "HWA_SAFETY_EN,"
bitfld.long 0x15C 3. "cfg_dmem_parity_en,Writing 1'b1 would enable the parity chekcer for the 8 DMEM memories" "0,1"
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bitfld.long 0x15C 2. "cfg_window_ram_parity_en,Writing 1'b1 enables parity for windowing RAM" "0,1"
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bitfld.long 0x15C 1. "cfg_fsm_lockstep_inv_en,Writing 1'b1 will invert the redundant FSM outputs" "0,1"
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bitfld.long 0x15C 0. "cfg_fsm_lockstep_en,Writing 1'b1 would enable the lockstep logic for FSM" "0,1"
line.long 0x160 "HWA_SAFETY_ERR_MASK,"
bitfld.long 0x160 9. "fsm_lockstep," "FSM lockstep error is not masked,FSM lockstep error is masked"
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bitfld.long 0x160 8. "window_ram," "window RAM parity error is not masked,window RAM parity error is masked"
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bitfld.long 0x160 7. "dmem7," "DMEM7 parity error is not masked,DMEM7 parity error is masked"
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bitfld.long 0x160 6. "dmem6," "DMEM6 parity error is not masked,DMEM6 parity error is masked"
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bitfld.long 0x160 5. "dmem5," "DMEM5 parity error is not masked,DMEM5 parity error is masked"
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bitfld.long 0x160 4. "dmem4," "DMEM4 parity error is not masked,DMEM4 parity error is masked"
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bitfld.long 0x160 3. "dmem3," "DMEM3 parity error is not masked,DMEM3 parity error is masked"
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bitfld.long 0x160 2. "dmem2," "DMEM2 parity error is not masked,DMEM2 parity error is masked"
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bitfld.long 0x160 1. "dmem1," "DMEM1 parity error is not masked,DMEM1 parity error is masked"
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bitfld.long 0x160 0. "dmem0," "DMEM0 parity error is not masked,DMEM0 parity error is masked"
line.long 0x164 "HWA_SAFETY_ERR_STATUS,"
bitfld.long 0x164 9. "fsm_lockstep,Indicates the FSM lockstep error (Masked status)" "0,1"
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bitfld.long 0x164 8. "window_ram,Indicates the parity error in window RAM (Masked status)" "0,1"
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bitfld.long 0x164 7. "dmem7,Indicates the parity error in dmem7 (Masked status)" "0,1"
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bitfld.long 0x164 6. "dmem6,Indicates the parity error in dmem6 (Masked status)" "0,1"
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bitfld.long 0x164 5. "dmem5,Indicates the parity error in dmem5 (Masked status)" "0,1"
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bitfld.long 0x164 4. "dmem4,Indicates the parity error in dmem4 (Masked status)" "0,1"
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bitfld.long 0x164 3. "dmem3,Indicates the parity error in dmem3 (Masked status)" "0,1"
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bitfld.long 0x164 2. "dmem2,Indicates the parity error in dmem2 (Masked status)" "0,1"
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bitfld.long 0x164 1. "dmem1,Indicates the parity error in dmem1 (Masked status)" "0,1"
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bitfld.long 0x164 0. "dmem0,Indicates the parity error in dmem0 (Masked status)" "0,1"
line.long 0x168 "HWA_SAFETY_ERR_STATUS_RAW,"
bitfld.long 0x168 9. "fsm_lockstep,Indicates the FSM lockstep error (raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 9" "0,1"
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bitfld.long 0x168 8. "window_ram,Indicates the parity error in window RAM(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 8" "0,1"
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bitfld.long 0x168 7. "dmem7,Indicates the parity error in dmem7(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 7" "0,1"
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bitfld.long 0x168 6. "dmem6,Indicates the parity error in dmem6(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 6" "0,1"
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bitfld.long 0x168 5. "dmem5,Indicates the parity error in dmem5(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 5" "0,1"
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bitfld.long 0x168 4. "dmem4,Indicates the parity error in dmem4(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 4" "0,1"
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bitfld.long 0x168 3. "dmem3,Indicates the parity error in dmem3(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 3" "0,1"
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bitfld.long 0x168 2. "dmem2,Indicates the parity error in dmem2(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 2" "0,1"
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bitfld.long 0x168 1. "dmem1,Indicates the parity error in dmem1(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 1" "0,1"
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bitfld.long 0x168 0. "dmem0,Indicates the parity error in dmem0(raw status)" "0,1"
line.long 0x16C "HWA_SAFETY_DMEM0_ERR_ADDR,"
hexmask.long.word 0x16C 0.--9. 1. "dmem0_err_addr,Captures the address where parity error occured for dmem0"
line.long 0x170 "HWA_SAFETY_DMEM1_ERR_ADDR,"
hexmask.long.word 0x170 0.--9. 1. "dmem1_err_addr,Captures the address where parity error occured for dmem1"
line.long 0x174 "HWA_SAFETY_DMEM2_ERR_ADDR,"
hexmask.long.word 0x174 0.--9. 1. "dmem2_err_addr,Captures the address where parity error occured for dmem2"
line.long 0x178 "HWA_SAFETY_DMEM3_ERR_ADDR,"
hexmask.long.word 0x178 0.--9. 1. "dmem3_err_addr,Captures the address where parity error occured for dmem3"
line.long 0x17C "HWA_SAFETY_DMEM4_ERR_ADDR,"
hexmask.long.word 0x17C 0.--9. 1. "dmem4_err_addr,Captures the address where parity error occured for dmem4"
line.long 0x180 "HWA_SAFETY_DMEM5_ERR_ADDR,"
hexmask.long.word 0x180 0.--9. 1. "dmem5_err_addr,Captures the address where parity error occured for dmem5"
line.long 0x184 "HWA_SAFETY_DMEM6_ERR_ADDR,"
hexmask.long.word 0x184 0.--9. 1. "dmem6_err_addr,Captures the address where parity error occured for dmem6"
line.long 0x188 "HWA_SAFETY_DMEM7_ERR_ADDR,"
hexmask.long.word 0x188 0.--9. 1. "dmem7_err_addr,Captures the address where parity error occured for dmem7"
line.long 0x18C "HWA_SAFETY_WINDOW_RAM_ERR_ADDR,"
hexmask.long.word 0x18C 0.--10. 1. "window_ram_err_addr,Captures the address where parity error occured for window RAM"
line.long 0x190 "MEM_ACCESS_ERR_STATUS,"
bitfld.long 0x190 7. "dmem7,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem7 at the same time" "0,1"
newline
bitfld.long 0x190 6. "dmem6,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem6 at the same time" "0,1"
newline
bitfld.long 0x190 5. "dmem5,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem5 at the same time" "0,1"
newline
bitfld.long 0x190 4. "dmem4,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem4 at the same time" "0,1"
newline
bitfld.long 0x190 3. "dmem3,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem3 at the same time" "0,1"
newline
bitfld.long 0x190 2. "dmem2,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem2 at the same time" "0,1"
newline
bitfld.long 0x190 1. "dmem1,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem1 at the same time" "0,1"
newline
bitfld.long 0x190 0. "dmem0,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem0 at the same time" "0,1"
line.long 0x194 "LOOP_CNT,"
hexmask.long.word 0x194 16.--27. 1. "loop_cnt_alt,Loop count for alternate thread"
newline
hexmask.long.word 0x194 0.--11. 1. "loop_cnt,Loop count"
line.long 0x198 "PARAMADDR,"
bitfld.long 0x198 0.--5. "paramaddr,Index of the current parameter set being executed from PARAM RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x19C "PARAMADDR_CPUINTR0,"
bitfld.long 0x19C 0.--5. "paramaddr,Index of the parameter set when PARAM_DONE_INTR0 is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1A0 "PARAMADDR_CPUINTR1,"
bitfld.long 0x1A0 0.--5. "paramaddr,Index of the parameter set when PARAM_DONE_INTR1 is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1A4 "FSM_STATE,"
bitfld.long 0x1A4 0.--2. "fsm_state,Current state of the state machine" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "SINGLE_STEP_EN,"
bitfld.long 0x1A8 0. "single_step_en,Single step enable" "0,1"
line.long 0x1AC "SINGLE_STEP_TRIG,"
bitfld.long 0x1AC 0. "single_step_trig,This is a self clearing sofware trigger bit" "0,1"
line.long 0x1B0 "HWA_DMEM_A_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "HWA_DMEM_A_BUS_SAFETY_FI,"
hexmask.long.byte 0x1B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1B8 "HWA_DMEM_A_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x678++0x0F
line.long 0x00 "HWA_DMEM_A_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x04 "HWA_DMEM_B_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x04 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x04 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x08 "HWA_DMEM_B_BUS_SAFETY_FI,"
hexmask.long.byte 0x08 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x08 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x0C "HWA_DMEM_B_BUS_SAFETY_ERR,"
hexmask.long.byte 0x0C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x68C++0x03
line.long 0x00 "HWA_DMEM_B_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "proxy_err,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "prot_err,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "enabled_proxy_err,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "enabled_kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "fault_ns,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "fault_type,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "fault_xid,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "fault_routeid,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "fault_privid,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "fault_clr,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x488)++0x03
line.long 0x00 "QCMULT_SCALE$1,"
hexmask.long.tbyte 0x00 0.--20. 1. "qcmult_scale0,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11 per-iteration based.."
repeat.end
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x458)++0x03
line.long 0x00 "ICMULT_SCALE$1,"
hexmask.long.tbyte 0x00 0.--20. 1. "icmult_scale0,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11 per-iteration based.."
repeat.end
width 0x0B
tree.end
tree "DSS_MCRC (DSS MCRC Module Registers)"
base ad:0x83300000
group.long 0x00++0x03
line.long 0x00 "CRC_CTRL0,Contains sw reset control bit to reset PSA"
rbitfld.long 0x00 31. "NU12,Reserved" "0,1"
rbitfld.long 0x00 30. "NU11,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "NU10,Reserved" "0,1"
rbitfld.long 0x00 27.--28. "NU9,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 25.--26. "NU8,Reserved" "0,1,2,3"
rbitfld.long 0x00 24. "NU7,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "NU6,Reserved" "0,1"
rbitfld.long 0x00 22. "NU5,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "NU4,Reserved" "0,1"
rbitfld.long 0x00 19.--20. "NU3,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 17.--18. "NU2,Reserved" "0,1,2,3"
rbitfld.long 0x00 16. "NU1,Reserved" "0,1"
newline
bitfld.long 0x00 15. "CH2_CRC_SEL2,Refer 'CH2_DW_SEL' field description" "0,1"
bitfld.long 0x00 14. "CH2_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 13. "CH2_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 11.--12. "CH2_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 9.--10. "CH2_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 8. "CH2_PSA_SWREST,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 7. "CH1_CRC_SEL2,Refer 'CH1_DW_SEL' field description" "0,1"
bitfld.long 0x00 6. "CH1_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 5. "CH1_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 3.--4. "CH1_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 1.--2. "CH1_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 0. "CH1_PSA_SWREST,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
group.long 0x08++0x03
line.long 0x00 "CRC_CTRL1,Contains power down control bit"
hexmask.long 0x00 1.--31. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode"
group.long 0x10++0x03
line.long 0x00 "CRC_CTRL2,Contains channel mode. data trace enable control bits"
rbitfld.long 0x00 26.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "NU14,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 18.--23. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 16.--17. "NU13,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 10.--15. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode: 0" "reserved 1,Full-CPU mode,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved2,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable" "Data Trace disable,Data Trace enable"
newline
rbitfld.long 0x00 2.--3. "Reserved1,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode: 0" "reserved 1,Full-CPU mode,?..."
group.long 0x18++0x03
line.long 0x00 "CRC_INTS,Write one to a bit to enable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU22,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU21,Reserved" "0,1"
rbitfld.long 0x00 26. "NU20,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU19,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU18,Reserved" "0,1"
rbitfld.long 0x00 19. "NU17,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU16,Reserved" "0,1"
rbitfld.long 0x00 17. "NU15,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENS,Channel 2 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENS,Channel 1 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
bitfld.long 0x00 1. "CH1_CRCFAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x20++0x03
line.long 0x00 "CRC_INTR,Write one to a bit to disable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU30,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU29,Reserved" "0,1"
rbitfld.long 0x00 26. "NU28,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU27,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU26,Reserved" "0,1"
rbitfld.long 0x00 19. "NU25,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU24,Reserved" "0,1"
rbitfld.long 0x00 17. "NU23,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENR,Channel 2 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
newline
bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENR,Channel 1 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
newline
bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
bitfld.long 0x00 1. "CH1_CRCFAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x28++0x03
line.long 0x00 "CRC_STATUS_REG,Contains interrupt flags for different types of interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU38,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU37,Reserved" "0,1"
rbitfld.long 0x00 26. "NU36,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU35,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU34,Reserved" "0,1"
rbitfld.long 0x00 19. "NU33,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU32,Reserved" "0,1"
rbitfld.long 0x00 17. "NU31,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUT,Channel 2 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 9. "CH2_CRCFAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUT,Channel 1 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
bitfld.long 0x00 1. "CH1_CRCFAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x30++0x03
line.long 0x00 "CRC_INT_OFFSET_REG,Contains the interrupt offset vector address"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "OFSTREG,CRC Interrupt Offset"
rgroup.long 0x38++0x03
line.long 0x00 "CRC_BUSY,Contains the busy flag for each channel"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "NU40,Reserved" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved3,Reserved"
bitfld.long 0x00 16. "NU39,Reserved" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved2,Reserved"
bitfld.long 0x00 8. "Ch2_BUSY,Ch2_BUSY" "0,1"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "CH1_BUSY,CH1_BUSY" "0,1"
group.long 0x40++0x13
line.long 0x00 "CRC_PCOUNT_REG1,Channel 1 preload register for the pattern count"
hexmask.long.word 0x00 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register"
line.long 0x04 "CRC_SCOUNT_REG1,Channel 1 preload register for the sector count"
hexmask.long.word 0x04 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register"
line.long 0x08 "CRC_CURSEC_REG1,Channel 1 current sector register contains the sector number which causes CRC failure"
hexmask.long.word 0x08 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register"
line.long 0x0C "CRC_WDTOPLD1,Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register"
line.long 0x10 "CRC_BCTOPLD1,Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x10 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Regis- ter"
group.long 0x60++0x33
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA signature low register"
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA signature high register"
line.long 0x08 "CRC_REGL1,Channel 1 CRC value low register"
line.long 0x0C "CRC_REGH1,Channel 1 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL1,Channel 1 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH1,Channel 1 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL1,Channel 1 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH1,Channel 1 un-compressed raw data high register"
line.long 0x20 "CRC_PCOUNT_REG2,Channel 2 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,Channel 2 Pattern Counter Preload Register"
line.long 0x24 "CRC_SCOUNT_REG2,Channel 2 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register"
line.long 0x28 "CRC_CURSEC_REG2,Channel 2 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register"
line.long 0x2C "CRC_WDTOPLD2,Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register"
line.long 0x30 "CRC_BCTOPLD2,Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Regis- ter"
group.long 0xA0++0x33
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA signature low register"
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA signature high register"
line.long 0x08 "CRC_REGL2,Channel 2 CRC value low register"
line.long 0x0C "CRC_REGH2,Channel 2 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL2,Channel 2 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH2,Channel 2 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL2,Channel 2 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH2,Channel 2 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG3,Channel 3 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU41,Reserved"
line.long 0x24 "CRC_SCOUNT_REG3,Channel 3 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU42,Reserved"
line.long 0x28 "CRC_CURSEC_REG3,Channel 3 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU43,Reserved"
line.long 0x2C "CRC_WDTOPLD3,Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU44,Reserved"
line.long 0x30 "CRC_BCTOPLD3,Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU45,Reserved"
rgroup.long 0xE0++0x33
line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA signature low register"
line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA signature high register"
line.long 0x08 "CRC_REGL3,Channel 3 CRC value low register"
line.long 0x0C "CRC_REGH3,Channel 3 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL3,Channel 3 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH3,Channel 3 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL3,Channel 3 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH3,Channel 3 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG4,Channel 4 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU54,Reserved"
line.long 0x24 "CRC_SCOUNT_REG4,Channel 4 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU55,Reserved"
line.long 0x28 "CRC_CURSEC_REG4,Channel 4 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU56,Reserved"
line.long 0x2C "CRC_WDTOPLD4,Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU57,Reserved"
line.long 0x30 "CRC_BCTOPLD4,Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU58,Reserved"
rgroup.long 0x120++0x27
line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA signature low register"
line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA signature high register"
line.long 0x08 "CRC_REGL4,Channel 4 CRC value low register"
line.long 0x0C "CRC_REGH4,Channel 4 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL4,Channel 4 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH4,Channel 4 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL4,Channel 4 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH4,Channel 4 un-compressed raw data high Register"
line.long 0x20 "MCRC_BUS_SEL,Disables either or all tracing of data buses"
hexmask.long 0x20 3.--31. 1. "NU67,Reserved"
bitfld.long 0x20 2. "MEn,MEn" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled"
newline
bitfld.long 0x20 1. "DTCMEn,DTCMEn" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.."
bitfld.long 0x20 0. "ITCMEn,ITCMEn" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled"
line.long 0x24 "MCRC_RESERVED,0x144 to 0x1FF is reserved area"
width 0x0B
tree.end
tree "DSS_PCR (DSS PCR Module Registers)"
base ad:0x56F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "DSS_RCM (DSS RCM Module Registers)"
base ad:0x56000000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x27
line.long 0x00 "DSP_PD_CTRL,"
bitfld.long 0x00 4. "proc_halt,Controls the unhalting on the processor during the power-up sequence" "The processor is unhalted at the end of the..,The DSP is kept in halt state at the end of the.."
newline
bitfld.long 0x00 0. "interrupt_mask,Masks interrupts to the DSP" "Send the interrupts to the DSP after power on,Mask interrupts to the DSP before powering off.."
line.long 0x04 "DSP_PD_TRIGGER_WAKUP,"
bitfld.long 0x04 0. "wakeup_trigger,Write pulse bit field: Trigger Power Up of the DSP" "0,1"
line.long 0x08 "DSP_PD_TRIGGER_SLEEP,"
bitfld.long 0x08 0. "sleep_trigger,Write pulse bit field: Trigger Power Down of the DSP" "0,1"
line.long 0x0C "DSP_PD_STATUS,"
bitfld.long 0x0C 8. "pwrsm_dbg_ovrd,Status bit indicating if there is an override for the DSP from Debug SubSystem" "No override from DebugSS,Override from DebugSS"
newline
bitfld.long 0x0C 4.--5. "pd_status,Power Mode status of DSP" "Powered OFF,Transitioning from OFF to ON..,Transitioning from ON to OFF..,Powered ON"
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bitfld.long 0x0C 0. "proc_halted,Processor is halted" "0,1"
line.long 0x10 "DSP_PD_CTRL_MISC0,"
bitfld.long 0x10 24.--29. "pwrsm_grst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of GRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 18.--23. "pwrsm_porrst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of POR during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 12.--17. "pwrsm_lrst_assertcnt,TI Internal Feature No of cycles to wait after assertion of LRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 6.--11. "pwrsm_grst_assertcnt,TI Internal Feature No of cycles to wait after assertion of GRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 0.--5. "pwrsm_porrst_assertcnt,TI Internal Feature No of cycles to wait after assertion of POR during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DSP_PD_CTRL_MISC1,"
bitfld.long 0x14 24.--26. "iso_sync_bypass,HW RnD reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20.--22. "rst_sync_bypass,HW RnD reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 18. "pwrsm_lresetout_mask,TI Internal Feature" "0,1"
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bitfld.long 0x14 12.--17. "pwrsm_isoen_assertcnt,TI Internal Feature No of cycles to wait after assertion of ISO_ENABLE during GEM power-down sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 6.--11. "pwrsm_clkstop_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of GEM_CLK_STOP_REQ during GEM Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 0.--5. "pwrsm_lrst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of LRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DSP_PD_STATUS_MISC0,"
bitfld.long 0x18 17. "pwrsm_lrstout,TI Internal Feature Lreset output indication from GEM" "0,1"
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bitfld.long 0x18 16. "pwrsm_c66_clkstop_ack,TI Internal Feature Clock stop request ack from GEM" "0,1"
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bitfld.long 0x18 15. "pwrsm_sdma_async2scr_clkstop_ack,TI Internal Feature SDMA slave disable Done from clock stop ack from the master port of the async bridge present in the SDMA port" "0,1"
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bitfld.long 0x18 14. "pwrsm_sdma_async2rcm_clkstop_req,TI Internal Feature SDMA Slave disable Ack from Interconnect" "0,1"
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bitfld.long 0x18 13. "pwrsm_sdma_scr2async_clkstop_req,TI Internal Feature Clock Stop request from SCR to SDMA Async Bridge" "0,1"
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bitfld.long 0x18 12. "pwrsm_mem_agoodout,TI Internal Feature Memory AGOOD Output from GEM (synchronized to Bus clock)" "0,1"
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bitfld.long 0x18 11. "pwrsm_mem_aonout,TI Internal Feature Memory AON Output from GEM (synchronized to Bus clock)" "0,1"
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bitfld.long 0x18 10. "pwrsm_mem_pgoodout,TI Internal Feature Memory PGOOD Output from DSP (synchronized to Bus clock)" "0,1"
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bitfld.long 0x18 9. "pwrsm_mem_ponout,TI Internal Feature Memory PON Output from DSP (synchronized to Bus clock)" "0,1"
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bitfld.long 0x18 8. "pwrsm_pgoodout,TI Internal Feature Logic PGOOD Output from DSP (synchronized to Bus clock)" "0,1"
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bitfld.long 0x18 7. "pwrsm_ponout,TI Internal Feature Logic PON Output from DSP (synchronized to Bus clock)" "0,1"
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bitfld.long 0x18 0.--5. "state,This is the internal state of the DSP power State machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DSP_PD_WAKEUP_MASK0,"
line.long 0x20 "DSP_PD_WAKEUP_MASK1,"
line.long 0x24 "DSP_PD_WAKEUP_MASK2,"
group.long 0x48++0x10B
line.long 0x00 "DSP_PD_WAKEUP_STATUS0_CLR,"
line.long 0x04 "DSP_PD_WAKEUP_STATUS1_CLR,"
line.long 0x08 "DSP_PD_WAKEUP_STATUS2_CLR,"
line.long 0x0C "DSP_PD_MISSED_EVENT_MASK0,"
line.long 0x10 "DSP_PD_MISSED_EVENT_MASK1,"
line.long 0x14 "DSP_PD_MISSED_EVENT_MASK2,"
line.long 0x18 "DSP_PD_MISSED_EVENT_STATUS0,"
line.long 0x1C "DSP_PD_MISSED_EVENT_STATUS1,"
line.long 0x20 "DSP_PD_MISSED_EVENT_STATUS2,"
line.long 0x24 "DSP_RST_CAUSE,"
abitfld.long 0x24 16.--23. "por_cause,DSP POR reset Bitwise Indication : Bit" "0x00=Por Reset Bit,0x01=Sub system Reset from TOPRCM Bit,0x02=Reset from DSS_RCM,0x03=Reset from Power FSM Bit,0x04=Reset from STC FSM"
newline
abitfld.long 0x24 8.--15. "grst_cause,DSP Greset Bitwise Indication : Bit" "0x00=Por Reset Bit,0x01=Sub system Reset from TOPRCM Bit,0x02=Reset from DSS_RCM,0x03=Reset from Power FSM Bit,0x04=Reset from STC FSM"
newline
abitfld.long 0x24 0.--7. "lrst_cause,DSP Lreset Bitwise Indication : Bit" "0x00=Por Reset Bit,0x01=Sub system Reset from TOPRCM Bit,0x02=Reset from DSS_RCM,0x03=Reset from Debugss Bit,0x04=Reset from Power FSM Bit,0x05=Reset from STC FSM"
line.long 0x28 "DSP_RST_CAUSE_CLR,"
bitfld.long 0x28 0. "clear,Write pulse bit field: Write 0x1 to clear the reset cause register for any previous resets : Its a wspecial access type write to this field will generate a pulse" "0,1"
line.long 0x2C "DSP_STC_PBIST_CTRL,"
bitfld.long 0x2C 16.--21. "pbist_tmode_vlct_assertcnt,No of clocks (in terms of 200 MHz DSPSS Bus clock) after asserting GEM TMODE VLCT signal before proceeding to the next state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x2C 10.--15. "pbist_tmode_vlct_deassertcnt,No of clocks (in terms of 200 MHz DSPSS Bus clock) after De-asserting GEM TMODE VLCT signal before proceeding to the next state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x2C 6.--9. "pbist_selftest_key,[4:1] DSP PBIST SELFTEST KEY = 4'b1010" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x2C 5. "stc_b2b_en,Enables back to Back STC.Needs to be set to 1 for self test" "0,1"
newline
bitfld.long 0x2C 4. "stc_clk_stp_ack_mask,Mask bit for ignoring the clock stop ack from GEM" "0,1"
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bitfld.long 0x2C 3. "proc_halt,Configuration to halt the state machine before the final de-assertion of LRST to enable program download" "0,1"
newline
bitfld.long 0x2C 2. "stc_boot_en,Enable GEM STC during GEM power UP" "0,1"
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bitfld.long 0x2C 0.--1. "mode_enable,Enable for PBIST and STC" "0,1,2,3"
line.long 0x30 "DSP_STC_PBIST_STATUS,"
bitfld.long 0x30 2.--7. "stc_pbist_sm_status,PBIST status from GEM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 0.--1. "pbist_status,Current state of STC PBIST state machine" "0,1,2,3"
line.long 0x34 "DSP_STC_PBIST_CTRL_MISC0,"
hexmask.long.word 0x34 16.--31. 1. "byp_value,DSP PBIST STC misc Control"
newline
hexmask.long.word 0x34 0.--15. 1. "byp_en,DSP PBIST STC misc Control"
line.long 0x38 "DSP_STC_PBIST_CTRL_MISC1,"
bitfld.long 0x38 4.--9. "sm_ovr_val,TI Internal Register.Reserved for HW RnD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x38 3. "sm_ovr_en,TI Internal Register.Reserved for HW RnD" "0,1"
line.long 0x3C "DSP_STC_PBIST_START,"
bitfld.long 0x3C 0. "sm_trig,Write pulse bit field: Trigger pulse for the STC PBIST state machine" "0,1"
line.long 0x40 "DSP_STC_PBIST_STATUS_CLR,"
bitfld.long 0x40 0. "clear,Write pulse bit field: Clear bit for PBIST Status : Its a wspecial access type write to this field will generate a pulse" "0,1"
line.long 0x44 "DSS_DSP_CLK_SRC_SEL,"
hexmask.long.word 0x44 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS DSP"
line.long 0x48 "DSS_HWA_CLK_SRC_SEL,"
bitfld.long 0x48 0.--2. "clksrcsel,Select line for selecting source clock for DSS HWA" "TOPRCM_CR5_CLK,?,?,?,?,?,?,TOPRCM_SYS_CLK"
line.long 0x4C "DSS_RTIA_CLK_SRC_SEL,"
hexmask.long.word 0x4C 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS_RTIA"
line.long 0x50 "DSS_RTIB_CLK_SRC_SEL,"
hexmask.long.word 0x50 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS RTIB"
line.long 0x54 "DSS_WDT_CLK_SRC_SEL,"
hexmask.long.word 0x54 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS Watchdog"
line.long 0x58 "DSS_SCIA_CLK_SRC_SEL,"
hexmask.long.word 0x58 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS SCIA"
line.long 0x5C "DSS_DSP_CLK_DIV_VAL,"
hexmask.long.word 0x5C 0.--11. 1. "clkdiv,Divider value for DSS DSP selected clock"
line.long 0x60 "DSS_RTIA_CLK_DIV_VAL,"
hexmask.long.word 0x60 0.--11. 1. "clkdiv,Divider value for DSS RTIA selected clock"
line.long 0x64 "DSS_RTIB_CLK_DIV_VAL,"
hexmask.long.word 0x64 0.--11. 1. "clkdiv,Divider value for DSS RTIB selected clock"
line.long 0x68 "DSS_WDT_CLK_DIV_VAL,"
hexmask.long.word 0x68 0.--11. 1. "clkdiv,Divider value for DSS Watchdog selected clock"
line.long 0x6C "DSS_SCIA_CLK_DIV_VAL,"
hexmask.long.word 0x6C 0.--11. 1. "clkdiv,Divider value for DSS SCIA selected clock"
line.long 0x70 "DSS_DSP_CLK_GATE,"
bitfld.long 0x70 0.--2. "gated,Clock gatring config for DSS DSP" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x74 "DSS_HWA_CLK_GATE,"
bitfld.long 0x74 0.--2. "gated,Clock gatring config for DSS HWA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x78 "DSS_RTIA_CLK_GATE,"
bitfld.long 0x78 0.--2. "gated,Clock gatring config for DSS RTA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x7C "DSS_RTIB_CLK_GATE,"
bitfld.long 0x7C 0.--2. "gated,Clock gatring config for DSS RTIB Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x80 "DSS_WDT_CLK_GATE,"
bitfld.long 0x80 0.--2. "gated,Clock gatring config for DSS Watchdog Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x84 "DSS_SCIA_CLK_GATE,"
bitfld.long 0x84 0.--2. "gated,Clock gatring config for DSS SCIA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x88 "DSS_CBUFF_CLK_GATE,"
bitfld.long 0x88 0.--2. "gated,Not Supported" "0,1,2,3,4,5,6,7"
line.long 0x8C "DSS_DSP_CLK_STATUS,"
hexmask.long.byte 0x8C 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS DSP Clock"
newline
hexmask.long.byte 0x8C 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS DSP Clock"
line.long 0x90 "DSS_HWA_CLK_STATUS,"
bitfld.long 0x90 0.--1. "clkinuse,Status shows the source clock slected for DSS HWA Clock" "0,1,2,3"
line.long 0x94 "DSS_RTIA_CLK_STATUS,"
hexmask.long.byte 0x94 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS RTIA Clock"
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hexmask.long.byte 0x94 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS RTIA Clock"
line.long 0x98 "DSS_RTIB_CLK_STATUS,"
hexmask.long.byte 0x98 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS RTIB Clock"
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hexmask.long.byte 0x98 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS RTIB Clock"
line.long 0x9C "DSS_WDT_CLK_STATUS,"
hexmask.long.byte 0x9C 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS Watchdog Clock"
newline
hexmask.long.byte 0x9C 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS Watchdog Clock"
line.long 0xA0 "DSS_SCIA_CLK_STATUS,"
hexmask.long.byte 0xA0 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS SCIA Clock"
newline
hexmask.long.byte 0xA0 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS SCIA Clock"
line.long 0xA4 "DSS_DSP_RST_CTRL,"
bitfld.long 0xA4 8.--10. "assert_local,Local Reset control for DSS DSP Data should be loaded as multibit" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0xA4 4.--6. "assert_global,Global Reset control forDSS DSP Data should be loaded as multibit" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0xA4 0.--2. "assert_por,Power on Reset control for DSS DSP Data should be loaded as multibit" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0xA8 "DSS_ESM_RST_CTRL,"
bitfld.long 0xA8 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xAC "DSS_SCIA_RST_CTRL,"
bitfld.long 0xAC 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xB0 "DSS_RTIA_RST_CTRL,"
bitfld.long 0xB0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xB4 "DSS_RTIB_RST_CTRL,"
bitfld.long 0xB4 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xB8 "DSS_WDT_RST_CTRL,"
bitfld.long 0xB8 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xBC "DSS_DCCA_RST_CTRL,"
bitfld.long 0xBC 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xC0 "DSS_DCCB_RST_CTRL,"
bitfld.long 0xC0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xC4 "DSS_MCRC_RST_CTRL,"
bitfld.long 0xC4 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xC8 "DSP_DFT_DIV_CTRL,"
bitfld.long 0xC8 4.--6. "clk_disable,DSP DFT Control for clock_disable" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC8 0.--3. "div_factor,DSP DFT Control for div factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "DSS_DSP_L2_PD_CTRL,"
bitfld.long 0xCC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xCC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xCC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xD0 "DSS_L3_BANKA0_PD_CTRL,"
bitfld.long 0xD0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xD4 "DSS_L3_BANKA1_PD_CTRL,"
bitfld.long 0xD4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xD8 "DSS_L3_BANKA2_PD_CTRL,"
bitfld.long 0xD8 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD8 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD8 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xDC "DSS_L3_BANKA3_PD_CTRL,"
bitfld.long 0xDC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xDC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xDC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xE0 "DSS_L3_BANKB0_PD_CTRL,"
bitfld.long 0xE0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xE4 "DSS_L3_BANKB1_PD_CTRL,"
bitfld.long 0xE4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xE8 "DSS_L3_BANKB2_PD_CTRL,"
bitfld.long 0xE8 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE8 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE8 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xEC "DSS_L3_BANKB3_PD_CTRL,"
bitfld.long 0xEC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xEC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xEC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xF0 "DSS_L3_BANKC0_PD_CTRL,"
bitfld.long 0xF0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xF4 "DSS_L3_BANKC1_PD_CTRL,"
bitfld.long 0xF4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xF8 "DSS_L3_BANKC2_PD_CTRL,"
bitfld.long 0xF8 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xFC "DSS_L3_BANKC3_PD_CTRL,"
bitfld.long 0xFC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xFC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xFC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x100 "DSS_L3_BANKD0_PD_CTRL,"
bitfld.long 0x100 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x104 "DSS_L3_BANKD1_PD_CTRL,"
bitfld.long 0x104 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x108 "DSS_L3_BANKD2_PD_CTRL,"
bitfld.long 0x108 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x108 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x108 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
group.long 0x158++0x43
line.long 0x00 "DSS_HWA_PD_CTRL,"
bitfld.long 0x00 16.--18. "pgoodin,SW Control for <IP>_PD_CTRL Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "ponin,SW Control for <IP>_PD_CTRL Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x04 "DSS_DSP_L2_PD_STATUS,"
bitfld.long 0x04 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x04 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x08 "DSS_L3_BANKA0_PD_STATUS,"
bitfld.long 0x08 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x08 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x08 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x08 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x0C "DSS_L3_BANKA1_PD_STATUS,"
bitfld.long 0x0C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x0C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x0C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x0C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x10 "DSS_L3_BANKA2_PD_STATUS,"
bitfld.long 0x10 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x10 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x10 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x10 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x14 "DSS_L3_BANKA3_PD_STATUS,"
bitfld.long 0x14 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x14 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x14 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x14 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x18 "DSS_L3_BANKB0_PD_STATUS,"
bitfld.long 0x18 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x18 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x18 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x18 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x1C "DSS_L3_BANKB1_PD_STATUS,"
bitfld.long 0x1C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x1C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x1C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x1C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x20 "DSS_L3_BANKB2_PD_STATUS,"
bitfld.long 0x20 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x20 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x20 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x20 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x24 "DSS_L3_BANKB3_PD_STATUS,"
bitfld.long 0x24 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x24 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x24 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x24 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x28 "DSS_L3_BANKC0_PD_STATUS,"
bitfld.long 0x28 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x28 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x28 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x28 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x2C "DSS_L3_BANKC1_PD_STATUS,"
bitfld.long 0x2C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x2C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x2C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x2C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x30 "DSS_L3_BANKC2_PD_STATUS,"
bitfld.long 0x30 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x30 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x30 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x30 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x34 "DSS_L3_BANKC3_PD_STATUS,"
bitfld.long 0x34 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x34 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x34 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x34 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x38 "DSS_L3_BANKD0_PD_STATUS,"
bitfld.long 0x38 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x38 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x38 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x38 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x3C "DSS_L3_BANKD1_PD_STATUS,"
bitfld.long 0x3C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x3C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x3C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x3C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x40 "DSS_L3_BANKD2_PD_STATUS,"
bitfld.long 0x40 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x40 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x40 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x40 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
rgroup.long 0x1A0++0x43
line.long 0x00 "DSS_HWA_PD_STATUS,"
bitfld.long 0x00 3. "pgoodout,Status for <IP>_PD_CTRL Power up CRTL1" "0,1"
newline
bitfld.long 0x00 2. "ponout,Status for <IP>_PD_CTRL Power up CRTL0" "0,1"
newline
bitfld.long 0x00 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x00 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x04 "DSS_DSP_TRCCLK_DIVRATIO,"
bitfld.long 0x04 0.--3. "divratio,DSP Trace Clock Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DSS_DSP_TCLK_DIVRATIO,"
bitfld.long 0x08 0.--3. "divratio,DSP TCLK Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DSS_DSP_DITHERED_CLK_CTRL,"
bitfld.long 0x0C 31. "load,Write pulse bit field: DSP Dithered Clock LFSR Load" "0,1"
newline
bitfld.long 0x0C 28.--30. "enable,DSP Dithered Clock Enable" "Disabled,?,?,?,?,?,?,Enabled"
newline
hexmask.long 0x0C 0.--27. 1. "seed,DSP Dithered Clock LFSR Seed"
line.long 0x10 "DSS_L3_PD_CTRL_STICKYBIT,"
bitfld.long 0x10 0.--2. "set,Sticky bit for DSS L3 PD CTRL" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSP_PD_CTRL_MISC2,"
hexmask.long.word 0x14 16.--31. 1. "pwrsm_agood_assertcnt,Value of agood asertion delay"
newline
hexmask.long.word 0x14 0.--15. 1. "pwrsm_pgood_assertcnt,Value of pgood asertion delay"
line.long 0x18 "DSP_PD_CTRL_MISC3,"
bitfld.long 0x18 16. "lreset_req_gate,Gate the lreset request from GEM" "0,1"
newline
hexmask.long.word 0x18 0.--15. 1. "pwrs_pd_waitcnt,Value of power down wait delay"
line.long 0x1C "DSP_PD_CTRL_OVERRIDE0,"
bitfld.long 0x1C 24.--29. "state_bypass_val,DSS DSP power FSM state bypass control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.tbyte 0x1C 0.--23. 1. "bypass_val,DSS DSP power FSM bypass control"
line.long 0x20 "DSP_PD_CTRL_OVERRIDE1,"
bitfld.long 0x20 24. "state_bypass_en,DSS DSP power FSM state bypass control enable.For debug pupose" "0,1"
newline
hexmask.long.tbyte 0x20 0.--23. 1. "bypass_en,DSS DSP power FSM bypass control enable.For debug pupose"
line.long 0x24 "DSP_PD_CTRL_OVERRIDE2,"
bitfld.long 0x24 0.--2. "override_enable,DSS DSP power FSM override enable .For debug pupose" "0,1,2,3,4,5,6,7"
line.long 0x28 "DSS_HWA_RST_CTRL,"
bitfld.long 0x28 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x2C "DSS_HWA_RST_CTRL,"
bitfld.long 0x2C 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x30 "DSS_EDMA_RST_CTRL,"
bitfld.long 0x30 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x34 "DSS_EDMA_RST_CTRL,"
bitfld.long 0x34 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x38 "DSS_EDMA_RST_CTRL,"
bitfld.long 0x38 4.--6. "assert_tc1,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x38 0.--2. "assert_tc0,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x3C "DSS_EDMA_RST_CTRL,"
bitfld.long 0x3C 4.--6. "assert_tc1,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x3C 0.--2. "assert_tc0,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x40 "DSS_TPTCC_RST_CTRL,"
bitfld.long 0x40 20.--22. "assert_tc5,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 16.--18. "assert_tc4,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 12.--14. "assert_tc3,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 8.--10. "assert_tc2,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 4.--6. "assert_tc1,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 0.--2. "assert_tc0,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x3C)++0x03
line.long 0x00 "DSP_PD_WAKEUP_STATUS$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_RTIA (DSS RTIA Module Registers)"
base ad:0x56F7A000
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "DSS_RTIB (DSS RTIB Module Registers)"
base ad:0x56F7A100
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "DSS_SCIA (DSS SCIA Module Registers)"
base ad:0x56F7B000
group.long 0x00++0x5F
line.long 0x00 "SCIGCR0,The SCIGCR0 register defines the module reset"
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
newline
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
line.long 0x04 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
rbitfld.long 0x04 26.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
newline
bitfld.long 0x04 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
newline
rbitfld.long 0x04 18.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
newline
bitfld.long 0x04 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
newline
rbitfld.long 0x04 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
newline
bitfld.long 0x04 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function" "0,1"
newline
bitfld.long 0x04 7. "SW_nRESET,Software reset (active low)" "0,1"
newline
rbitfld.long 0x04 6. "RESERVED1,Reserved" "0,1"
newline
bitfld.long 0x04 5. "CLOCK,SCI internal clock enable" "0,1"
newline
bitfld.long 0x04 4. "STOP,SCI number of stop bits" "0,1"
newline
bitfld.long 0x04 3. "PARITY,SCI parity odd/even selection" "0,1"
newline
bitfld.long 0x04 2. "PARITY_ENA,SCI parity enable" "0,1"
newline
bitfld.long 0x04 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0,1"
newline
bitfld.long 0x04 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0,1"
line.long 0x08 "RESERVED1,Reserved"
line.long 0x0C "SCISETINT,SCI Set Interrupt Register"
rbitfld.long 0x0C 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x0C 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request for address and data frames"
newline
bitfld.long 0x0C 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x0C 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x0C 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 8. "SET_TX_INT,Set Transmitter interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x0C 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 0. "SET_BRKDT_INT,Set Break-detect interrupt" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x10 "SCICLEARINT,SCI Clear Interrupt Register"
rbitfld.long 0x10 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 25. "CLR_OE_INT,Clear Overrun-Error Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 24. "CLR_PE_INT,Clear Parity Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x10 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 18. "CLR_RX_DMA_ALL,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request for address frames"
newline
bitfld.long 0x10 17. "CLR_RX_DMA,Clear RX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x10 16. "CLR_TX_DMA,Clear TX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
newline
rbitfld.long 0x10 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 9. "CLR_RX_INT,Clear Receiver interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 8. "CLR_TX_INT,Clear Transmitter interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
rbitfld.long 0x10 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 0. "CLR_BRKDT_INT,Clear Break-detect interrupt" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x14 "SCISETINTLVL,SCI Set Interrupt Level Register"
rbitfld.long 0x14 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
bitfld.long 0x14 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
bitfld.long 0x14 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
rbitfld.long 0x14 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read)" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
rbitfld.long 0x14 16.--17. "RESERVED3,Reserved" "0,1,2,3"
newline
bitfld.long 0x14 15. "SET_INC_BR_INT_LVL," "0,1"
newline
rbitfld.long 0x14 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
bitfld.long 0x14 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
rbitfld.long 0x14 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
line.long 0x18 "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
rbitfld.long 0x18 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x18 15. "CLR_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x18 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x18 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
line.long 0x1C "SCIFLR,SCI Flags Register"
rbitfld.long 0x1C 27.--31. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 26. "FE,SCI framing error flag Read" "No effect,Clears this bit to 0"
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rbitfld.long 0x1C 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
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rbitfld.long 0x1C 24. "PE,SCI parity error flag" "0,1"
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hexmask.long.word 0x1C 13.--23. 1. "RESERVED2,Reserved"
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rbitfld.long 0x1C 12. "RXWAKE,Receiver wake-up detect flag" "0,1"
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rbitfld.long 0x1C 11. "TX_EMPTY,Transmitter empty flag" "0,1"
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bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wake-up method select" "0,1"
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rbitfld.long 0x1C 9. "RXRDY,SCI receiver ready flag" "0,1"
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rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag" "0,1"
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rbitfld.long 0x1C 4.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame" "0,1"
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rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state" "0,1"
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rbitfld.long 0x1C 1. "WAKEUP,Wake-up flag" "0,1"
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rbitfld.long 0x1C 0. "BRKDT,SCI break-detect flag" "0,1"
line.long 0x20 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x20 0.--3. "INTVECT0,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x24 0.--3. "INTVECT1,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "SCICHAR,SCI Character Control Register"
hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x28 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
line.long 0x2C "SCIBAUD,SCI Baud Rate Selection Register"
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED,Reserved"
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hexmask.long.tbyte 0x2C 0.--23. 1. "BAUD,SCI 24-bit baud selection"
line.long 0x30 "SCIED,Receiver Emulation Data Buffer"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x30 0.--7. 1. "ED,Receiver Emulation Data Buffer"
line.long 0x34 "SCIRD,Receiver Data Buffer"
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x34 0.--7. 1. "RD,Contains received data"
line.long 0x38 "SCITD,Transmit Data Buffer Register"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x38 0.--7. 1. "TD,Contains Data to be transmitted"
line.long 0x3C "SCIPIO0,SCI Pin I/O Control Register 0"
hexmask.long 0x3C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x3C 2. "TX_FUNC,Defines the function of pin SCITX" "SCIRX is a general-purpose digital I/O pin,SCIRX is the SCI receive pin"
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bitfld.long 0x3C 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x3C 0. "CLK_FUNC,Clock function" "SCICLK is a general-purpose digital I/O pin,SCICLK is the SCI serial clock pin"
line.long 0x40 "SCIPIO1,SCI Pin I/O Control Register 1"
hexmask.long 0x40 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x40 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0)" "SCITX is a general-purpose input pin,SCITX is a general-purpose output pin"
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bitfld.long 0x40 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x40 0. "CLK_DIR,Clock data direction" "0,1"
line.long 0x44 "SCIPIO2,SCI Pin I/O Control Register 2"
hexmask.long 0x44 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x44 2. "TX_DATA_IN,Contains current value on the SCITX pin" "SCITX value is logic low,SCITX value is logic high"
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bitfld.long 0x44 1. "RX_DATA_IN,Contains current value on the SCIRX pin" "SCIRX value is logic low,SCIRX value is logic high"
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bitfld.long 0x44 0. "CLK_DATA_IN,Contains the current value on pin SCICLK" "Pin SCICLK value is logic low,Pin SCICLK value is logic high"
line.long 0x48 "SCIPIO3,SCI Pin I/O Control Register 3"
hexmask.long 0x48 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x48 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "Output value on SCITX is a 0 (logic low),Output value on SCITX is a 1 (logic high)"
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bitfld.long 0x48 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "Output value on SCIRX is 0 (logic low),Output value on SCIRX is 1 (logic high)"
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bitfld.long 0x48 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "Output value on SCICLK is a 0 (logic low),Output value on SCICLK is a 1 (logic high)"
line.long 0x4C "SCIPIO4,SCI Pin I/O Control Register 4"
hexmask.long 0x4C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4C 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
line.long 0x50 "SCIPIO5,SCI Pin I/O Control Register 5"
hexmask.long 0x50 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x50 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
line.long 0x54 "SCIPIO6,SCI Pin I/O Control Register 6"
hexmask.long 0x54 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x54 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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bitfld.long 0x54 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x54 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
line.long 0x58 "SCIPIO7,SCI Pin I/O Control Register 7"
hexmask.long 0x58 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x58 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX" "Pull Control on SCITX pin is enabled,Pull Control on SCITX pin is disabled"
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bitfld.long 0x58 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX" "Pull Control on SCIRX pin is enabled,Pull Control on SCIRX pin is disabled"
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bitfld.long 0x58 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK" "Pull Control on SCICLK pin is enabled,Pull Control on SCICLK pin is disabled"
line.long 0x5C "SCIPIO8,SCI Pin I/O Control Register 8"
hexmask.long 0x5C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x5C 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX" "Pull-Down is on SCITX pin,Pull-Up is on SCITX pin"
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bitfld.long 0x5C 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX" "Pull-Down is on SCIRX pin,Pull-Up is on SCIRX pin"
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bitfld.long 0x5C 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK" "Pull-Down is on SCICLK pin,Pull-Up is on SCICLK pin"
group.long 0x80++0x03
line.long 0x00 "SCIPIO9,SCI Pin I/O Control Register 9"
hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 2. "TX_SL,This bit controls the slew rate for the SCITX pin" "The normal output buffer is used for SCITX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 1. "RX_SL,This bit controls the slew rate for the SCIRX pin" "The normal output buffer is used for SCIRX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin" "The normal output buffer is used for SCICLK pin,The output buffer with slew control is used for.."
group.long 0x90++0x03
line.long 0x00 "SCIIODCTRL,SCI IO DFT Control"
rbitfld.long 0x00 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 26. "FEN,Frame Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 25. "PEN,Parity Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 24. "BRKDT_ENA,Break Detect Error Enable" "No effect,This bit is used to.."
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rbitfld.long 0x00 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry" "0,1,2,3"
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bitfld.long 0x00 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 12.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "LBP_ENA,Module loopback enable" "Digital loopback is enabled,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x00 0. "RXP_ENA,Module Analog loopback through receive pin enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
repeat 8. (list 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "DSS_TPCC_A (DSS TPCCA Module Registers)"
base ad:0x56100000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
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bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
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bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
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bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
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bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
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bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
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bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
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bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
newline
hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
newline
hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
newline
bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
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bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
newline
bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
newline
bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
newline
bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
newline
bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
newline
bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
newline
bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
newline
bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
newline
bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
newline
bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
newline
bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
newline
bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
newline
bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
newline
bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
newline
bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
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bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
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bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
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bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
tree "DSS_TPCC_B (DSS TPCCB Module Registers)"
base ad:0x56120000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
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bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
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bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
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bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
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bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
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bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
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bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
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bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
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bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
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bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
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bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
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bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
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bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
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bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
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bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
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bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
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bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
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bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
newline
hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
newline
hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
newline
bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
newline
bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
newline
bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
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bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
newline
bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
newline
bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
newline
bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
newline
bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
newline
bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
newline
bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
newline
bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
newline
bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
newline
bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
newline
bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
newline
bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
newline
bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
newline
bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
newline
bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
newline
bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
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bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
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bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
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bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
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bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
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bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
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bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
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bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
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bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
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bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
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bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
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bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
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bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
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bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
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bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
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bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
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bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
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bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
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bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
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bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
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bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
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bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
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bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
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bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
tree "DSS_TPCC_C (DSS TPCCC Module Registers)"
base ad:0x56140000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
newline
hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
newline
hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
newline
bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
newline
bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
newline
bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
newline
bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
newline
bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
newline
bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
newline
bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
newline
bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
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bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
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bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
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bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
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bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
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bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
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bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
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bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
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bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
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bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
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bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
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bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
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bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
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bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
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bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
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bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
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bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
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bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
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bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
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bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
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bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
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bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
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bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
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bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
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bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
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bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
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bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
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bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
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bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
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bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
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bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
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bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
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bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
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bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
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bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
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bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
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bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
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bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
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bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
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bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
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bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
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bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
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bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
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bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
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bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
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bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
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bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
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bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
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bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
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bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
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bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
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bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
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bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
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bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
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bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
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bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
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bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
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bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
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bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
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bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
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bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
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bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
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bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
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bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
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bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
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bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
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bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
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bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
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bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
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bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
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bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
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bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
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bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
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bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
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bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
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bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
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bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
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bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
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bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
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bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
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bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
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bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
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bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
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bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
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bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
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bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
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bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x56160000 ad:0x56180000 )
tree "DSS_TPTC_A$1 (DSS TPTC A$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
repeat 2. (list 0. 1. )(list ad:0x561A0000 ad:0x561C0000 )
tree "DSS_TPTC_B$1 (DSS TPTC B$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list ad:0x561E0000 ad:0x56200000 ad:0x56220000 ad:0x56240000 ad:0x56260000 ad:0x56280000 )
tree "DSS_TPTC_C$1 (DSS TPTC C$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
tree "DSS_WDT (DSS WDT Module Registers)"
base ad:0x56F7A200
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x401A0000 ad:0x401C0000 )
tree "MPU_DSS_HWA_DMA$1 (DSS HWA DMA$1 MPU Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
repeat.end
tree "MPU_DSS_HWA_PROC (DSS HWA PROC MPU Module Registers)"
base ad:0x401E0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKA (DSS L3 BANKA MPU Module Registers)"
base ad:0x40120000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKB (DSS L3 BANKB MPU Module Registers)"
base ad:0x40140000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKC (DSS L3 BANKC MPU Module Registers)"
base ad:0x40160000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKD (MSS L3 BANKD MPU Module Registers)"
base ad:0x40180000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_MBOX (DSS MBOX MPU Module Registers)"
base ad:0x40200000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_CR5A_AXIS (MSS CR5A AXIS MPU Module Registers)"
base ad:0x400E0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_CR5B_AXIS (MSS CR5B AXIS MPU Module Registers)"
base ad:0x40100000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_L2_BANKA (MSS L2 BANKA MPU Module Registers)"
base ad:0x40020000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_L2_BANKB (MSS L2 BANKB MPU Module Registers)"
base ad:0x40040000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_MBOX (MPU MSS MBOX Module Registers)"
base ad:0x40080000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_PCRA (MSS PCRA MPU Module Registers)"
base ad:0x400A0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_QSPI (MSS QSPI MPU Module Registers)"
base ad:0x400C0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MSS_CCMR (MSS CCMR Module Registers)"
base ad:0x52F7AC00
group.long 0x00++0x1B
line.long 0x00 "CCMSR1,CPU Compare Status Register"
hexmask.long.word 0x00 17.--31. 1. "NU2,Reserved"
bitfld.long 0x00 16. "CMPE1,Compare Error" "CPU signals are identical,CPU signal compare mismatch Writes '1' to clear.."
newline
hexmask.long.byte 0x00 9.--15. 1. "NU1,Reserved"
bitfld.long 0x00 8. "STC1,Self Test Complete" "self test on-going if self test mode asserted,self test is complete Writes have no effect"
newline
bitfld.long 0x00 2.--7. "NU0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "STET1,Self Test Error Type" "self test failed during Compare Match test,self test failed during Compare mismatch test.."
newline
bitfld.long 0x00 0. "STE1,Self Test Error" "self test passed,self test failed Writes have no effect"
line.long 0x04 "CCMKEYR1,CPU Compare Key Register"
hexmask.long 0x04 4.--31. 1. "NU3,Reserved"
bitfld.long 0x04 0.--3. "MKEY1,Mode Key" "lock step mode,?,?,?,?,?,self test mode,?,?,error forcing mode,?,?,?,?,?,self test error forcing mode"
line.long 0x08 "CCMSR2,VIM Compare Status Register"
hexmask.long.word 0x08 17.--31. 1. "NU6,Reserved"
bitfld.long 0x08 16. "CMPE2,Compare Error" "VIM signals are identical,VIM signal compare mismatch Writes '1' to clear.."
newline
hexmask.long.byte 0x08 9.--15. 1. "NU5,Reserved"
bitfld.long 0x08 8. "STC2,Self Test Complete" "self test on-going if self test mode asserted,self test is complete Writes have no effect"
newline
bitfld.long 0x08 2.--7. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 1. "STET2,Self Test Error Type" "self test failed during Compare Match test,self test failed during Compare mismatch test.."
newline
bitfld.long 0x08 0. "STE2,Self Test Error" "self test passed,self test failed Writes have no effect"
line.long 0x0C "CCMKEYR2,VIM Compare Key Register"
hexmask.long 0x0C 4.--31. 1. "NU7,Reserved"
bitfld.long 0x0C 0.--3. "MKEY2,Mode Key" "lock step mode,?,?,?,?,?,self test mode,?,?,error forcing mode,?,?,?,?,?,self test error forcing mode"
line.long 0x10 "CCMSR3,Inactivity Monitor Status Register"
hexmask.long.word 0x10 17.--31. 1. "NU10,Reserved"
bitfld.long 0x10 16. "CMPE3,Compare Error" "Inactivity monitor signals are identical,Inactivity monitor signal compare mismatch.."
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hexmask.long.byte 0x10 9.--15. 1. "NU9,Reserved"
bitfld.long 0x10 8. "STC3,Self Test Complete" "self test on-going if self test mode asserted,self test is complete Writes have no effect"
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bitfld.long 0x10 2.--7. "NU8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 1. "STET3,Self Test Error Type" "self test failed during Compare Match test,self test failed during Compare mismatch test.."
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bitfld.long 0x10 0. "STE3,Self Test Error" "self test passed,self test failed Writes have no effect"
line.long 0x14 "CCMKEYR3,Inactivity Monitor Key Register"
hexmask.long 0x14 4.--31. 1. "NU11,Reserved"
bitfld.long 0x14 0.--3. "MKEY3,Mode Key" "lock step mode,?,?,?,?,?,self test mode,?,?,error forcing mode,?,?,?,?,?,self test error forcing mode"
line.long 0x18 "CCMPOLCNTRL,CPU Compare Polarity Control Register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU12,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "POL_INV,This value is used to invert the 8 XOR of the CPU1 to create compare fail in functional active compare mode"
width 0x0B
tree.end
tree "MSS_CPSW (MSS CPSW Module Registers)"
base ad:0x57000000
rgroup.long 0x00++0x0F
line.long 0x00 "SS_IDVER_REG,SS ID Version Register"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification value"
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bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "SS_SYNCE_COUNT_REG,SS SYNCE Count Register"
line.long 0x08 "SS_SYNCE_MUX_REG,SS Synce Mux Register"
bitfld.long 0x08 0.--5. "SYNCE_SEL,Sync E Select Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "SS_CONTROL_REG,SS Control Register"
bitfld.long 0x0C 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode" "The low power indicate state includes gating off..,The low power indicate state does not gate the.."
newline
bitfld.long 0x0C 0. "EEE_EN,Energy Efficient Ethernet Enable" "EEE is disabled,EEE is enabled"
group.long 0x18++0x07
line.long 0x00 "SS_INT_CONTROL_REG,SS Interrupt Control Register"
bitfld.long 0x00 31. "INT_TEST,Interrupt Test" "0,1"
newline
bitfld.long 0x00 16.--21. "INT_BYPASS,Interrupt Bypass Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--11. 1. "INT_PRESCALE,Interrupt Prescale Value"
line.long 0x04 "SS_STATUS_REG,SS Status Register"
bitfld.long 0x04 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1"
rgroup.long 0x30++0x03
line.long 0x00 "SS_RGMII1_STATUS_REG,RGMII1 Status Register"
bitfld.long 0x00 3. "FULLDUPLEX,Rgmii full dulex" "Half-duplex,Full-duplex"
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bitfld.long 0x00 1.--2. "SPEED,Rgmii1 speed" "0,1,2,3"
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bitfld.long 0x00 0. "LINK,Rgmii1 link indicator" "Link is down,Link is up"
group.long 0x80++0x0F
line.long 0x00 "SS_TH_THRESH_PULSE_EN_REG,THost Threshold Pulse Interrupt Enable Register"
hexmask.long.byte 0x00 0.--7. 1. "TH_THRESH_PULSE_EN,THost Threshold Pulse Interrupt Enable Register"
line.long 0x04 "SS_TH_PULSE_EN_REG,THost Pulse Interrupt Enable Register"
hexmask.long.byte 0x04 0.--7. 1. "TH_PULSE_EN,THost Pulse Interrupt Enable Register"
line.long 0x08 "SS_FH_PULSE_EN_REG,FHost Pulse Interrupt Enable Register"
hexmask.long.byte 0x08 0.--7. 1. "FH_PULSE_EN,FHost Pulse Interrupt Enable Register"
line.long 0x0C "SS_MISC_EN_REG,Misc Interrupt Enable Register"
bitfld.long 0x0C 6. "DED_PEND_EN,MISC DED Memory Protect Error Interrupt Enable" "0,1"
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bitfld.long 0x0C 5. "SEC_PEND_EN,MISC SEC Memory Protect Error Interrupt Enable" "0,1"
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bitfld.long 0x0C 4. "EVNT_PEND_EN,MISC CPTS Event Interrupt Enable" "0,1"
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bitfld.long 0x0C 3. "STAT_PEND_EN,MISC Statistics Interrupt Enable - OR of bits n downto 0" "0,1"
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bitfld.long 0x0C 2. "HOST_PEND_EN,MISC Host Interrupt Enable" "0,1"
newline
bitfld.long 0x0C 1. "MDIO_LINKINT_EN,MISC MDIO linkint - OR of bits 1 and 0" "0,1"
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bitfld.long 0x0C 0. "MDIO_USERINT_EN,MISC_MDIO userint interrupt enable - OR of bits 1 and 0" "0,1"
rgroup.long 0xB0++0x0F
line.long 0x00 "SS_TH_THRESH_PULSE_STATUS_REG,THost Threshold Pulse Interrupt Status Register"
hexmask.long.byte 0x00 0.--7. 1. "TH_THRESH_PULSE_ST,THost Threshold Pulse Interrupt Status Register"
line.long 0x04 "SS_TH_PULSE_STATUS_REG,THost Pulse Interrupt Status Register"
hexmask.long.byte 0x04 0.--7. 1. "TH_PULSE_STATUS,THost Pulse Interrupt Status Register"
line.long 0x08 "SS_FH_PULSE_STATUS_REG,FHost Pulse Interrupt Status Register"
hexmask.long.byte 0x08 0.--7. 1. "FH_PULSE_STATUS,FHost Pulse Interrupt Status Register"
line.long 0x0C "SS_MISC_STATUS_REG,Misc Interrupt Status Register - Set bits in this register indicate that an enabled interrupt is asserted"
bitfld.long 0x0C 6. "DED_PEND,MISC DED Memory Protect Error Interrupt" "0,1"
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bitfld.long 0x0C 5. "SEC_PEND,MISC SEC Memory Protect Error Interrupt" "0,1"
newline
bitfld.long 0x0C 4. "EVNT_PEND,MISC CPTS Event Interrupt" "0,1"
newline
bitfld.long 0x0C 3. "STAT_PEND,MISC Statistics Interrupt - OR of bits n downto 0" "0,1"
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bitfld.long 0x0C 2. "HOST_PEND,MISC Host Interrupt Enable" "0,1"
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bitfld.long 0x0C 1. "MDIO_LINKINT,MISC MDIO linkint - OR of bits 1 and 0" "0,1"
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bitfld.long 0x0C 0. "MDIO_USERINT,MISC_MDIO userint interrupt - OR of bits 1 and 0" "0,1"
group.long 0xE0++0x07
line.long 0x00 "SS_TH_IMAX_REG,THost Interrupt Max Register Register"
bitfld.long 0x00 0.--5. "TH_IMAX,THost Interrupt Max Register Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SS_FH_IMAX_REG,FHost Interrupt Max Register Register"
bitfld.long 0x04 0.--5. "FH_IMAX,FHost Interrupt Max Register Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0xF00++0x47
line.long 0x00 "MDIO_VERSION_REG,MDIO Version Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CONTROL_REG,MDIO Control Register"
rbitfld.long 0x04 31. "IDLE,MDIO state machine idle" "0,1"
newline
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
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rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
newline
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
newline
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
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bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
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hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider"
line.long 0x08 "ALIVE_REG,MDIO Alive Register"
line.long 0x0C "LINK_REG,MDIO Link Register"
line.long 0x10 "LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x14 "LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x18 "LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x18 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0x1C "LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
bitfld.long 0x1C 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x20 "USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
bitfld.long 0x20 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
line.long 0x24 "USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
bitfld.long 0x24 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
line.long 0x28 "USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x28 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
line.long 0x2C "USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
bitfld.long 0x2C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
line.long 0x30 "MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x30 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
newline
bitfld.long 0x30 1. "MDIO_OE,MDIO Output Enable" "0,1"
newline
bitfld.long 0x30 0. "MDIO_PIN,MDIO Pin" "0,1"
line.long 0x34 "POLL_REG,MDIO Poll Register"
bitfld.long 0x34 31. "MANUALMODE,MDIO Manual Mode" "0,1"
newline
bitfld.long 0x34 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
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hexmask.long.byte 0x34 0.--7. 1. "IPG,MDIO IPG"
line.long 0x38 "POLL_EN_REG,MDIO Poll Enable Register"
line.long 0x3C "CLAUS45_REG,MDIO Clause45 Register"
line.long 0x40 "USER_ADDR0_REG,MDIO Address 0 Register"
hexmask.long.word 0x40 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
line.long 0x44 "USER_ADDR1_REG,MDIO Address 1 Register"
hexmask.long.word 0x44 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
group.long 0xF80++0x07
line.long 0x00 "USER_ACCESS_REG,MDIO User Access Register"
bitfld.long 0x00 31. "GO,Go" "0,1"
newline
bitfld.long 0x00 30. "WRITE," "0,1"
newline
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
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bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
line.long 0x04 "USER_PHY_SEL_REG,MDIO User PHY Select Register"
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
newline
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
newline
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x20000++0x07
line.long 0x00 "CPSW_ID_VER_REG,CPSW ID Version"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification Value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM_VER,Custom Version Value" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR_VER,Minor Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CONTROL_REG,CPSW Switch Control"
bitfld.long 0x04 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1"
newline
bitfld.long 0x04 18. "EST_ENABLE,Intersperced Express Traffic enable" "0,1"
newline
bitfld.long 0x04 17. "UNUSED,Unused" "0,1"
newline
bitfld.long 0x04 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1"
newline
bitfld.long 0x04 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1"
newline
bitfld.long 0x04 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1"
newline
bitfld.long 0x04 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1"
newline
bitfld.long 0x04 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1"
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bitfld.long 0x04 2. "P0_ENABLE,Port 0 Enable" "0,1"
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bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "0,1"
newline
bitfld.long 0x04 0. "S_CN_SWITCH,VLAN Aware Mode" "0,1"
group.long 0x20010++0x37
line.long 0x00 "EM_CONTROL_REG,CPSW Emulation Control"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
newline
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "STAT_PORT_EN_REG,CPSW Statistics Port Enable"
bitfld.long 0x04 8. "P8_STAT_EN,Port 8 Statistics Enable" "0,1"
newline
bitfld.long 0x04 7. "P7_STAT_EN,Port 7 Statistics Enable" "0,1"
newline
bitfld.long 0x04 6. "P6_STAT_EN,Port 6 Statistics Enable" "0,1"
newline
bitfld.long 0x04 5. "P5_STAT_EN,Port 5 Statistics Enable" "0,1"
newline
bitfld.long 0x04 4. "P4_STAT_EN,Port 4 Statistics Enable" "0,1"
newline
bitfld.long 0x04 3. "P3_STAT_EN,Port 3 Statistics Enable" "0,1"
newline
bitfld.long 0x04 2. "P2_STAT_EN,Port 2 Statistics Enable" "0,1"
newline
bitfld.long 0x04 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1"
newline
bitfld.long 0x04 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1"
line.long 0x08 "PTYPE_REG,CPSW Transmit Priority Type"
bitfld.long 0x08 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 0.--4. "ESC_PRI_LD_VAL,Escalate Priority Load Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "SOFT_IDLE_REG,CPSW Software Idle"
bitfld.long 0x0C 0. "SOFT_IDLE,Software Idle" "0,1"
line.long 0x10 "THRU_RATE_REG,CPSW Thru Rate"
bitfld.long 0x10 12.--15. "SL_RX_THRU_RATE,Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 0.--3. "P0_RX_THRU_RATE,CPPI FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold"
bitfld.long 0x14 0.--4. "GAP_THRESH,Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "TX_START_WDS_REG,CPSW Transmit FIFO Start Words"
hexmask.long.word 0x18 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit Start Words"
line.long 0x1C "EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value"
hexmask.long.word 0x1C 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value"
line.long 0x20 "TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set"
bitfld.long 0x20 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear"
bitfld.long 0x24 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low"
hexmask.long.byte 0x28 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
newline
hexmask.long.byte 0x28 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
newline
hexmask.long.byte 0x28 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
newline
hexmask.long.byte 0x28 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x2C "TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High"
hexmask.long.byte 0x2C 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
newline
hexmask.long.byte 0x2C 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
newline
hexmask.long.byte 0x2C 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
newline
hexmask.long.byte 0x2C 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
line.long 0x30 "TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low"
hexmask.long.byte 0x30 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
newline
hexmask.long.byte 0x30 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
newline
hexmask.long.byte 0x30 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
newline
hexmask.long.byte 0x30 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x34 "TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High"
hexmask.long.byte 0x34 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
newline
hexmask.long.byte 0x34 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
newline
hexmask.long.byte 0x34 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
newline
hexmask.long.byte 0x34 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
group.long 0x20050++0x07
line.long 0x00 "VLAN_LTYPE_REG,VLAN Length/type"
hexmask.long.word 0x00 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType"
newline
hexmask.long.word 0x00 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType"
line.long 0x04 "EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain"
hexmask.long.byte 0x04 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain"
group.long 0x20100++0x1F
line.long 0x00 "TX_PRI0_MAXLEN_REG,Transmit Priority 0 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Length"
line.long 0x04 "TX_PRI1_MAXLEN_REG,Transmit Priority 1 Maximum Length"
hexmask.long.word 0x04 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Length"
line.long 0x08 "TX_PRI2_MAXLEN_REG,Transmit Priority 2 Maximum Length"
hexmask.long.word 0x08 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Length"
line.long 0x0C "TX_PRI3_MAXLEN_REG,Transmit Priority 3 Maximum Length"
hexmask.long.word 0x0C 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Length"
line.long 0x10 "TX_PRI4_MAXLEN_REG,Transmit Priority 4 Maximum Length"
hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Length"
line.long 0x14 "TX_PRI5_MAXLEN_REG,Transmit Priority 5 Maximum Length"
hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Length"
line.long 0x18 "TX_PRI6_MAXLEN_REG,Transmit Priority 6 Maximum Length"
hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Length"
line.long 0x1C "TX_PRI7_MAXLEN_REG,Transmit Priority 7 Maximum Length"
hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Length"
group.long 0x21004++0x07
line.long 0x00 "P0_CONTROL_REG,CPPI Port 0 Control"
bitfld.long 0x00 18. "RX_REMAP_DSCP_V6,Port 0 Remap DSCP_V6 Enable" "0,1"
newline
bitfld.long 0x00 17. "RX_REMAP_DSCP_V4,Port 0 Remap DSCP_V4 Enable" "0,1"
newline
bitfld.long 0x00 16. "RX_REMAP_VLAN,Port 0 Remap VLAN Enable" "0,1"
newline
bitfld.long 0x00 15. "RX_ECC_ERR_EN,Port 0 Receive ECC Error Enable" "0,1"
newline
bitfld.long 0x00 14. "TX_ECC_ERR_EN,Port 0 Transmit ECC Error Enable" "0,1"
newline
bitfld.long 0x00 2. "DSCP_IPV6_EN,Port 0 IPv6 DSCP enable" "0,1"
newline
bitfld.long 0x00 1. "DSCP_IPV4_EN,Port 0 IPv4 DSCP enable" "0,1"
newline
bitfld.long 0x00 0. "RX_CHECKSUM_EN,Port 0 Receive Checksum Enable" "0,1"
line.long 0x04 "P0_FLOW_ID_OFFSET_REG,CPPI Port 0 Flow ID Offset"
hexmask.long.word 0x04 0.--13. 1. "VALUE,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0"
rgroup.long 0x21010++0x1B
line.long 0x00 "P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count"
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Port 0 Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--5. "RX_BLK_CNT,Port 0 Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "P0_PORT_VLAN_REG,CPPI Port 0 VLAN"
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
newline
hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
line.long 0x08 "P0_TX_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x08 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x0C "P0_PRI_CTL_REG,CPPI Port 0 Priority Control"
hexmask.long.byte 0x0C 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
newline
bitfld.long 0x0C 8. "RX_PTYPE,Receive Priority Type" "0,1"
line.long 0x10 "P0_RX_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map"
bitfld.long 0x10 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "P0_RX_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length"
hexmask.long.word 0x14 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length"
line.long 0x18 "P0_TX_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority"
bitfld.long 0x18 28.--31. "PRI7,Priority 7 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 24.--27. "PRI6,Priority 6 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 20.--23. "PRI5,Priority 5 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 16.--19. "PRI4,Priority 4 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 12.--15. "PRI3,Priority 3 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 8.--11. "PRI2,Priority 2 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 4.--7. "PRI1,Priority 1 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "PRI0,Priority 0 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x21030++0x0F
line.long 0x00 "P0_IDLE2LPI_REG,Port 0 EEE Idle to LPI counter"
hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Port 0 EEE Idle to LPI counter load value"
line.long 0x04 "P0_LPI2WAKE_REG,Port 0 EEE LPI to wake counter"
hexmask.long.tbyte 0x04 0.--23. 1. "COUNT,Port 0 EEE LPI to wake counter load value"
line.long 0x08 "P0_EEE_STATUS_REG,Port 0 EEE status"
bitfld.long 0x08 6. "TX_FIFO_EMPTY,CPPI port 0 transmit FIFO (switch egress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x08 5. "RX_FIFO_EMPTY,CPPI port 0 receive FIFO (switch ingress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x08 4. "TX_FIFO_HOLD,CPPI port 0 transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
newline
bitfld.long 0x08 3. "TX_WAKE,CPPI port 0 transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
newline
bitfld.long 0x08 2. "TX_LPI,CPPI port 0 transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
newline
bitfld.long 0x08 1. "RX_LPI,CPPI port 0 receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
newline
bitfld.long 0x08 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
line.long 0x0C "P0_RX_PKTS_PRI_REG,CPPI Port Receive Packets per priority"
bitfld.long 0x0C 28.--31. "PRI7,Priority 7 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 24.--27. "PRI6,Priority 6 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 20.--23. "PRI5,Priority 5 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 16.--19. "PRI4,Priority 4 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 12.--15. "PRI3,Priority 3 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 8.--11. "PRI2,Priority 2 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 4.--7. "PRI1,Priority 1 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0.--3. "PRI0,Priority 0 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2104C++0x07
line.long 0x00 "P0_RX_GAP_REG,Port 0 Receive Gap Register"
hexmask.long.word 0x00 16.--25. 1. "RX_GAP_CNT,Port 0 Receive Gap Count"
newline
hexmask.long.byte 0x00 0.--7. 1. "RX_GAP_EN,Port 0 Receive Gap Enable"
line.long 0x04 "P0_FIFO_STATUS_REG,Port 0 FIFO Status"
hexmask.long.byte 0x04 0.--7. 1. "TX_PRI_ACTIVE,Port 0 FIFO Status"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x21120)++0x03
line.long 0x00 "P0_RX_DSCP_MAP_REG_$1,CPPI Port 0 Receive IPV4/IPV6 DSCP Map N"
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x21140)++0x03
line.long 0x00 "P0_PRI_CIR_REG_$1,CPPI Port 0 Rx Priority P Committed Information Rate"
hexmask.long 0x00 0.--27. 1. "PRI_CIR,Priority N CIR"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x21160)++0x03
line.long 0x00 "P0_PRI_EIR_REG_$1,CPPI Port 0 Rx Priority P Excess Information Rate"
hexmask.long 0x00 0.--27. 1. "PRI_EIR,Priority N EIR"
repeat.end
group.long 0x21180++0x1F
line.long 0x00 "P0_TX_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "P0_TX_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High"
bitfld.long 0x04 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "P0_TX_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low"
bitfld.long 0x08 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "P0_TX_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High"
bitfld.long 0x0C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "P0_TX_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x10 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "P0_TX_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x14 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "P0_TX_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x18 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "P0_TX_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x1C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21300++0x07
line.long 0x00 "P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A"
hexmask.long.byte 0x00 24.--31. 1. "PORT4,Port 4 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x00 16.--23. 1. "PORT3,Port 3 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x00 8.--15. 1. "PORT2,Port 2 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x00 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value"
line.long 0x04 "P0_SRC_ID_B_REG,CPPI Port 0 CPPI Source ID B"
hexmask.long.byte 0x04 24.--31. 1. "PORT8,Port 8 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x04 16.--23. 1. "PORT7,Port 7 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x04 8.--15. 1. "PORT6,Port 6 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x04 0.--7. 1. "PORT5,Port 5 CPPI Info Word0 Source ID Value"
group.long 0x21320++0x03
line.long 0x00 "P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority"
bitfld.long 0x00 28.--31. "PRI7,Priority 7 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "PRI6,Priority 6 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 20.--23. "PRI5,Priority 5 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "PRI4,Priority 4 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 12.--15. "PRI3,Priority 3 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "PRI2,Priority 2 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "PRI1,Priority 1 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PRI0,Priority 0 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x22000++0x0B
line.long 0x00 "PN_RESERVED_REG,Reserved"
line.long 0x04 "PN_CONTROL_REG,Enet Port N Control"
bitfld.long 0x04 17. "EST_PORT_EN,EST Port Enable" "0,1"
newline
bitfld.long 0x04 15. "RX_ECC_ERR_EN,Port 0 Receive ECC Error Enable" "0,1"
newline
bitfld.long 0x04 14. "TX_ECC_ERR_EN,Port 0 Transmit ECC Error Enable" "0,1"
newline
bitfld.long 0x04 12. "TX_LPI_CLKSTOP_EN,Transmit LPI clockstop enable" "0,1"
newline
bitfld.long 0x04 2. "DSCP_IPV6_EN,IPv6 DSCP enable" "0,1"
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bitfld.long 0x04 1. "DSCP_IPV4_EN,IPv4 DSCP enable" "0,1"
line.long 0x08 "PN_MAX_BLKS_REG,Enet Port N FIFO Max Blocks"
hexmask.long.byte 0x08 8.--15. 1. "TX_MAX_BLKS,Transmit FIFO maximum blocks"
newline
hexmask.long.byte 0x08 0.--7. 1. "RX_MAX_BLKS,Receive FIFO maximum blocks"
rgroup.long 0x22010++0x2B
line.long 0x00 "PN_BLK_CNT_REG,Enet Port N FIFO Block Usage Count"
bitfld.long 0x00 16.--21. "RX_BLK_CNT_P,Receive Prempt Queue Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--5. "RX_BLK_CNT_E,Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PN_PORT_VLAN_REG,Enet Port N VLAN"
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
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hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
line.long 0x08 "PN_TX_PRI_MAP_REG,Enet Port N Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x08 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x0C "PN_PRI_CTL_REG,Enet Port N Priority Control"
hexmask.long.byte 0x0C 24.--31. 1. "TX_FLOW_PRI,Transmit Priority Based Flow Control Enable (per priority)"
newline
hexmask.long.byte 0x0C 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
newline
bitfld.long 0x0C 12.--15. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "PN_RX_PRI_MAP_REG,Enet Port N RX Pkt Pri to Header Pri Map"
bitfld.long 0x10 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "PN_RX_MAXLEN_REG,Enet Port N Receive Frame Max Length"
hexmask.long.word 0x14 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length"
line.long 0x18 "PN_TX_BLKS_PRI_REG,Enet Port N Transmit Block Sub Per Priority"
bitfld.long 0x18 28.--31. "PRI7,Priority 7 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 24.--27. "PRI6,Priority 6 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 20.--23. "PRI5,Priority 5 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "PRI4,Priority 4 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 12.--15. "PRI3,Priority 3 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 8.--11. "PRI2,Priority 2 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 4.--7. "PRI1,Priority 1 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "PRI0,Priority 0 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "PN_RX_FLOW_THRESH_REG,Enet MAC Receive Flow Threshold in Receive Buffer Words"
hexmask.long.word 0x1C 0.--8. 1. "COUNT,Receive Flow Threshold in Words"
line.long 0x20 "PN_IDLE2LPI_REG,Enet Port N EEE Idle to LPI counter"
hexmask.long.tbyte 0x20 0.--23. 1. "COUNT,EEE Idle to LPI counter load value"
line.long 0x24 "PN_LPI2WAKE_REG,Enet Port N EEE LPI to wake counter"
hexmask.long.tbyte 0x24 0.--23. 1. "COUNT,EEE LPI to wake counter load value"
line.long 0x28 "PN_EEE_STATUS_REG,Enet Port N EEE status"
bitfld.long 0x28 6. "TX_FIFO_EMPTY,Transmit FIFO (switch egress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x28 5. "RX_FIFO_EMPTY,Receive FIFO (switch ingress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x28 4. "TX_FIFO_HOLD,Transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
newline
bitfld.long 0x28 3. "TX_WAKE,Transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
newline
bitfld.long 0x28 2. "TX_LPI,Transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
newline
bitfld.long 0x28 1. "RX_LPI,Receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
newline
bitfld.long 0x28 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
rgroup.long 0x22050++0x03
line.long 0x00 "PN_FIFO_STATUS_REG,Enet Port N FIFO STATUS"
bitfld.long 0x00 18. "EST_BUFACT,Transmit FIFO EST Buffer Active" "0,1"
newline
bitfld.long 0x00 17. "EST_ADD_ERR,Transmit FIFO EST Address Error" "0,1"
newline
bitfld.long 0x00 16. "EST_CNT_ERR,Transmit FIFO EST Count Error" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "TX_E_MAC_ALLOW,Transmit FIFO Express Queue Priority Allow"
newline
hexmask.long.byte 0x00 0.--7. 1. "TX_PRI_ACTIVE,Transmit FIFO Priority Active"
group.long 0x22060++0x03
line.long 0x00 "PN_EST_CONTROL_REG,Enet Port N EST CONTROL"
hexmask.long.word 0x00 16.--25. 1. "EST_FILL_MARGIN,Transmit FIFO EST Fill Margin"
newline
hexmask.long.byte 0x00 9.--15. 1. "EST_PREMPT_COMP,Transmit FIFO EST Prempt Comparision Value"
newline
bitfld.long 0x00 8. "EST_FILL_EN,Transmit FIFO EST Fill Enable" "0,1"
newline
bitfld.long 0x00 5.--7. "EST_TS_PRI,Transmit FIFO EST TimeStamp Priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "EST_TS_ONEPRI,Transmit FIFO EST TimeStamp One Priority" "0,1"
newline
bitfld.long 0x00 3. "EST_TS_FIRST,Transmit FIFO EST TimeStamp First Express Packet" "0,1"
newline
bitfld.long 0x00 2. "EST_TS_EN,Transmit FIFO EST TimeStamp Enable" "0,1"
newline
bitfld.long 0x00 1. "EST_BUFSEL,Transmit FIFO EST Buffer Select" "0,1"
newline
bitfld.long 0x00 0. "EST_ONEBUF,Transmit FIFO EST One Buffer" "0,1"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22120)++0x03
line.long 0x00 "PN_RX_DSCP_MAP_REG_$1,Enet Port N Receive IPV4/IPV6 DSCP Map M"
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22140)++0x03
line.long 0x00 "PN_PRI_CIR_REG_$1,Enet Port N Rx Priority P Committed Information Rate Value"
hexmask.long 0x00 0.--27. 1. "PRI_CIR,Priority N committed information rate"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22160)++0x03
line.long 0x00 "PN_PRI_EIR_REG_$1,Enet Port N Rx Priority P Excess Informatoin Rate Value"
hexmask.long 0x00 0.--27. 1. "PRI_EIR,Priority N Excess Information Rate count"
repeat.end
group.long 0x22180++0x1F
line.long 0x00 "PN_TX_D_THRESH_SET_L_REG,Enet Port N Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "PN_TX_D_THRESH_SET_H_REG,Enet Port N Tx PFC Destination Threshold Set High"
bitfld.long 0x04 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "PN_TX_D_THRESH_CLR_L_REG,Enet Port N Tx PFC Destination Threshold Clr Low"
bitfld.long 0x08 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "PN_TX_D_THRESH_CLR_H_REG,Enet Port N Tx PFC Destination Threshold Clr High"
bitfld.long 0x0C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "PN_TX_G_BUF_THRESH_SET_L_REG,Enet Port N Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x10 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "PN_TX_G_BUF_THRESH_SET_H_REG,Enet Port N Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x14 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "PN_TX_G_BUF_THRESH_CLR_L_REG,Enet Port N Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x18 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "PN_TX_G_BUF_THRESH_CLR_H_REG,Enet Port N Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x1C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22300++0x23
line.long 0x00 "PN_TX_D_OFLOW_ADDVAL_L_REG,Enet Port N Tx Destination Out Flow Add Values Low"
bitfld.long 0x00 24.--28. "PRI3,Port PFC Destination Based Out Flow Add Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 16.--20. "PRI2,Port PFC Destination Based Out Flow Add Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--12. "PRI1,Port PFC Destination Based Out Flow Add Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--4. "PRI0,Port PFC Destination Based Out Flow Add Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "PN_TX_D_OFLOW_ADDVAL_H_REG,Enet Port N Tx Destination Out Flow Add Values High"
bitfld.long 0x04 24.--28. "PRI7,Port PFC Destination Based Out Flow Add Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 16.--20. "PRI6,Port PFC Destination Based Out Flow Add Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 8.--12. "PRI5,Port PFC Destination Based Out Flow Add Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0.--4. "PRI4,Port PFC Destination Based Out Flow Add Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "PN_SA_L_REG,Enet Port N Tx Pause Frame Source Address Low"
hexmask.long.byte 0x08 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits"
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hexmask.long.byte 0x08 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8"
line.long 0x0C "PN_SA_H_REG,Enet Port N Tx Pause Frame Source Address High"
hexmask.long.byte 0x0C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16"
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hexmask.long.byte 0x0C 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24"
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hexmask.long.byte 0x0C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32"
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hexmask.long.byte 0x0C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40"
line.long 0x10 "PN_TS_CTL_REG,Enet Port N Time Sync Control"
hexmask.long.word 0x10 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable"
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bitfld.long 0x10 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable" "0,1"
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bitfld.long 0x10 10. "TS_TX_ANNEX_E_EN,Time Synce Transmit Annex E Enable" "0,1"
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bitfld.long 0x10 9. "TS_RX_ANNEX_E_EN,Time Synce Receive Annex E Enable" "0,1"
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bitfld.long 0x10 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 enable transmit and receive" "0,1"
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bitfld.long 0x10 7. "TS_TX_ANNEX_D_EN,Time Synce Transmit Annex D Enable" "0,1"
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bitfld.long 0x10 6. "TS_TX_VLAN_LTYPE2_E,Time Sync Transmit VLAN LTYPE 2 enable" "0,1"
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bitfld.long 0x10 5. "TS_TX_VLAN_LTYPE1_E,Time Sync Transmit VLAN LTYPE 1 enable" "0,1"
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bitfld.long 0x10 4. "TS_TX_ANNEX_F_EN,Time Synce Transmit Annex F Enable" "0,1"
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bitfld.long 0x10 3. "TS_RX_ANNEX_D_EN,Time Synce Receive Annex D Enable" "0,1"
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bitfld.long 0x10 2. "TS_RX_VLAN_LTYPE2_E,Time Sync Receive VLAN LTYPE 2 enable" "0,1"
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bitfld.long 0x10 1. "TS_RX_VLAN_LTYPE1_E,Time Sync Receive VLAN LTYPE 1 enable" "0,1"
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bitfld.long 0x10 0. "TS_RX_ANNEX_F_EN,Time Synce Receive Annex F Enable" "0,1"
line.long 0x14 "PN_TS_SEQ_LTYPE_REG,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)"
bitfld.long 0x14 16.--21. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1"
line.long 0x18 "PN_TS_VLAN_LTYPE_REG,Enet Port N Time Sync VLAN2 and VLAN2"
hexmask.long.word 0x18 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2"
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hexmask.long.word 0x18 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1"
line.long 0x1C "PN_TS_CTL_LTYPE2_REG,Enet Port N Time Sync Control and LTYPE 2"
bitfld.long 0x1C 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1"
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bitfld.long 0x1C 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1"
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bitfld.long 0x1C 22. "TS_320,Time Sync Destination IP Address 320 Enable" "0,1"
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bitfld.long 0x1C 21. "TS_319,Time Sync Destination IP Address 319 Enable" "0,1"
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bitfld.long 0x1C 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1"
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bitfld.long 0x1C 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1"
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bitfld.long 0x1C 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1"
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bitfld.long 0x1C 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1"
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bitfld.long 0x1C 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1"
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hexmask.long.word 0x1C 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2"
line.long 0x20 "PN_TS_CTL2_REG,Enet Port N Time Sync Control 2"
bitfld.long 0x20 16.--21. "TS_DOMAIN_OFFSET,Time Sync Domain Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x20 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable"
group.long 0x22330++0x13
line.long 0x00 "PN_MAC_CONTROL_REG,Enet Port N Mac Control"
bitfld.long 0x00 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable" "0,1"
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bitfld.long 0x00 23. "RX_CSF_EN,RX Copy Short Frames Enable" "0,1"
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bitfld.long 0x00 22. "RX_CEF_EN,RX Copy Error Frames Enable" "0,1"
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bitfld.long 0x00 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable" "0,1"
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bitfld.long 0x00 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
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bitfld.long 0x00 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable" "0,1"
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bitfld.long 0x00 18. "EXT_EN,External Enable" "0,1"
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bitfld.long 0x00 17. "GIG_FORCE,Gigabit Mode Force" "0,1"
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bitfld.long 0x00 16. "IFCTL_B,Interface Control B" "0,1"
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bitfld.long 0x00 15. "IFCTL_A,Interface Control A" "0,1"
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bitfld.long 0x00 12. "CRC_TYPE,Port CRC Type" "0,1"
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bitfld.long 0x00 11. "CMD_IDLE,Command Idle" "0,1"
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bitfld.long 0x00 10. "TX_SHORT_GAP_ENABLE,Transmit Short Gap Enable" "0,1"
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bitfld.long 0x00 7. "GIG,Gigabit Mode" "0,1"
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bitfld.long 0x00 6. "TX_PACE,Transmit Pacing Enable" "0,1"
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bitfld.long 0x00 5. "GMII_EN,GMII Enable" "0,1"
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bitfld.long 0x00 4. "TX_FLOW_EN,Transmit Flow Control Enable" "0,1"
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bitfld.long 0x00 3. "RX_FLOW_EN,Receive Flow Control Enable" "0,1"
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bitfld.long 0x00 2. "MTEST,Manufacturing Test Mode" "0,1"
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bitfld.long 0x00 1. "LOOPBACK,Loop Back Mode" "0,1"
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bitfld.long 0x00 0. "FULLDUPLEX,Full Duplex mode" "0,1"
line.long 0x04 "PN_MAC_STATUS_REG,Enet Port N Mac Status"
bitfld.long 0x04 31. "IDLE,cpxmac_sl IDLE" "0,1"
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bitfld.long 0x04 30. "E_IDLE,Express cpxmac_sl IDLE" "0,1"
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bitfld.long 0x04 28. "MAC_TX_IDLE,Prempt and Express cpxmac_sl Transmit IDLE" "0,1"
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bitfld.long 0x04 27. "TORF,Top of receive FIFO flow control trigger occurred" "0,1"
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bitfld.long 0x04 24.--26. "TORF_PRI,The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x04 16.--23. 1. "TX_PFC_FLOW_ACT,Transmit Priority Based Flow Control Active (priority 7 down to 0)"
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hexmask.long.byte 0x04 8.--15. 1. "RX_PFC_FLOW_ACT,Receive Priority Based Flow Control Active (priority 7 down to 0)"
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bitfld.long 0x04 6. "EXT_RX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
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bitfld.long 0x04 5. "EXT_TX_FLOW_EN,External Receive Flow Control Enable" "0,1"
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bitfld.long 0x04 4. "EXT_GIG,External GIG mode" "0,1"
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bitfld.long 0x04 3. "EXT_FULLDUPLEX,External Fullduplex" "0,1"
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bitfld.long 0x04 1. "RX_FLOW_ACT,Receive Flow Control Active" "0,1"
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bitfld.long 0x04 0. "TX_FLOW_ACT,Transmit Flow Control Active" "0,1"
line.long 0x08 "PN_MAC_SOFT_RESET_REG,Enet Port N Mac Soft Reset"
bitfld.long 0x08 0. "SOFT_RESET,Software reset" "0,1"
line.long 0x0C "PN_MAC_BOFFTEST_REG,Enet Port N Mac Backoff Test"
bitfld.long 0x0C 26.--30. "PACEVAL,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x0C 16.--25. 1. "RNDNUM,Backoff Random Number Generator"
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rbitfld.long 0x0C 12.--15. "COLL_COUNT,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x0C 0.--9. 1. "TX_BACKOFF,Backoff Count"
line.long 0x10 "PN_MAC_RX_PAUSETIMER_REG,Enet Port N 802.3 Receive Pause Timer"
hexmask.long.word 0x10 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22350)++0x03
line.long 0x00 "PN_MAC_RXN_PAUSETIMER_REG_$1,Enet Port N PFC Priority P Rx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value"
repeat.end
group.long 0x22370++0x03
line.long 0x00 "PN_MAC_TX_PAUSETIMER_REG,Enet Port N 802.3 Tx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22380)++0x03
line.long 0x00 "PN_MAC_TXN_PAUSETIMER_REG_$1,Enet Port N PFC Priority P Tx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value"
repeat.end
group.long 0x223A0++0x07
line.long 0x00 "PN_MAC_EMCONTROL_REG,Enet Port N Emulation Control"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
newline
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "PN_MAC_TX_GAP_REG,Enet Port N Tx Inter Packet Gap"
hexmask.long.word 0x04 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap"
group.long 0x223AC++0x13
line.long 0x00 "PN_INTERVLAN_OPX_POINTER_REG,Enet Port N Tx Egress InterVLAN Operation Pointer"
bitfld.long 0x00 0.--2. "PN_INTERVLAN_OPX_POINTER_REG,Egress InterVLAN Operation Pointer" "0,1,2,3,4,5,6,7"
line.long 0x04 "PN_INTERVLAN_OPX_A_REG,Enet Port N Tx Egress InterVLAN A"
line.long 0x08 "PN_INTERVLAN_OPX_B_REG,Enet Port N Tx Egress InterVLAN B"
line.long 0x0C "PN_INTERVLAN_OPX_C_REG,Enet Port N Tx Egress InterVLAN C"
line.long 0x10 "PN_INTERVLAN_OPX_D_REG,Enet Port N Tx Egress InterVLAN D"
hexmask.long.word 0x10 0.--15. 1. "INTERVLAN_OPX_D,Egress InterVLAN D"
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
rgroup.long 0x34000++0x0B
line.long 0x00 "CPDMA_FH_IDVER_REG,CPDMA Transmit IDVER"
line.long 0x04 "CPDMA_FH_CONTROL_REG,CPDMA Transmit Control Register"
bitfld.long 0x04 0. "FH_EN,CPDMA Transmit DMA Enable" "0,1"
line.long 0x08 "CPDMA_FH_TEARDOWN_REG,CPDMA Transmit Teardown Register"
bitfld.long 0x08 31. "FH_TDN_RDY,CPDMA Transmit Teardown Ready" "0,1"
newline
bitfld.long 0x08 0.--2. "FH_TDN_CH,CPDMA Transmit Teardown Channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x34010++0x1F
line.long 0x00 "CPDMA_TH_IDVER_REG,CPDMA Receive IDVER"
line.long 0x04 "CPDMA_TH_CONTROL_REG,CPDMA Receive Control Register"
bitfld.long 0x04 0. "TH_EN,CPDMA Receive DMA Enable" "0,1"
line.long 0x08 "CPDMA_TH_TEARDOWN_REG,CPDMA Receive Teardown Register"
bitfld.long 0x08 31. "TH_TDN_RDY,CPDMA Receive Teardown Ready" "0,1"
newline
bitfld.long 0x08 0.--2. "TH_TDN_CH,CPDMA Receive Teardown Channel" "0,1,2,3,4,5,6,7"
line.long 0x0C "CPDMA_SOFT_RESET_REG,CPDMA Soft Reset Register"
bitfld.long 0x0C 0. "SOFT_RESET,CPDMA and CPSW Soft Reset Enable" "0,1"
line.long 0x10 "CPDMA_CONTROL_REG,CPDMA Control Register"
bitfld.long 0x10 6. "TH_TS_ENCAP,CPDMA Receive TimeStamp Encapsulated" "0,1"
newline
bitfld.long 0x10 5. "TH_VLAN_ENCAP,CPDMA Receive VLAN Encapsulated" "0,1"
newline
bitfld.long 0x10 4. "TH_CEF,CPDMA Receive Copy Error Frames" "0,1"
newline
bitfld.long 0x10 3. "CMD_IDLE,CPDMA Command Idle" "0,1"
newline
bitfld.long 0x10 2. "TH_OFFLEN_BLOCK,CPDMA Receive Offset/Length Word Write Block" "0,1"
newline
bitfld.long 0x10 1. "TH_OWNERSHIP,CPDMA Receive Ownership Write Bit Value" "0,1"
newline
bitfld.long 0x10 0. "FH_PTYPE,CPDMA Transmit Queue Priority Type" "0,1"
line.long 0x14 "CPDMA_STATUS_REG,CPDMA Status Register"
bitfld.long 0x14 31. "IDLE,CPDMA Transmit Host Error Code" "0,1"
newline
bitfld.long 0x14 20.--23. "FH_HOST_ERROR_CODE,CPDMA Transmit Host Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 16.--18. "FH_ERR_CH,CPDMA Transmit Error Channel Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 12.--15. "TH_HOST_ERROR_CODE,CPDMA Receive Host Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 8.--10. "TH_ERR_CH,CPDMA Receive Error Channel Number" "0,1,2,3,4,5,6,7"
line.long 0x18 "CPDMA_TH_BUFFER_OFFSET_REG,CPDMA Receive Buffer Offset Register"
hexmask.long.word 0x18 0.--10. 1. "TH_BUFFER_OFFSET,CPDMA Receive Buffer Offset Register"
line.long 0x1C "CPDMA_EMULATION_CONTROL_REG,CPDMA Receive Buffer Offset Register"
bitfld.long 0x1C 1. "FREE,CPDMA Receive Buffer Offset Register" "0,1"
newline
bitfld.long 0x1C 0. "SOFT,CPDMA Receive Buffer Offset Register" "0,1"
rgroup.long 0x34080++0x17
line.long 0x00 "CPDMA_FH_INTSTAT_RAW_REG,CPDMA FHost Interrupt Status RAW"
bitfld.long 0x00 7. "FH7_PEND_RAW,CPDMA FHost Channel 7 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 6. "FH6_PEND_RAW,CPDMA FHost Channel 6 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 5. "FH5_PEND_RAW,CPDMA FHost Channel 5 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 4. "FH4_PEND_RAW,CPDMA FHost Channel 4 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 3. "FH3_PEND_RAW,CPDMA FHost Channel 3 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 2. "FH2_PEND_RAW,CPDMA FHost Channel 2 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 1. "FH1_PEND_RAW,CPDMA FHost Channel 1 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 0. "FH0_PEND_RAW,CPDMA FHost Channel 0 Interrupt Pending RAW" "0,1"
line.long 0x04 "CPDMA_FH_INTSTAT_MASKED_REG,CPDMA FHost Interrupt Status MASKED"
bitfld.long 0x04 7. "FH7_PEND_MASKED,CPDMA FHost Channel 7 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 6. "FH6_PEND_MASKED,CPDMA FHost Channel 6 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 5. "FH5_PEND_MASKED,CPDMA FHost Channel 5 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 4. "FH4_PEND_MASKED,CPDMA FHost Channel 4 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 3. "FH3_PEND_MASKED,CPDMA FHost Channel 3 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 2. "FH2_PEND_MASKED,CPDMA FHost Channel 2 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 1. "FH1_PEND_MASKED,CPDMA FHost Channel 1 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 0. "FH0_PEND_MASKED,CPDMA FHost Channel 0 Interrupt Pending MASKED" "0,1"
line.long 0x08 "CPDMA_FH_INTSTAT_MASKED_SET_REG,CPDMA FHost Interrupt Masked SET"
bitfld.long 0x08 7. "FH7_PEND_MASKED_SET,CPDMA FHost Channel 7 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 6. "FH6_PEND_MASKED_SET,CPDMA FHost Channel 6 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 5. "FH5_PEND_MASKED_SET,CPDMA FHost Channel 5 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 4. "FH4_PEND_MASKED_SET,CPDMA FHost Channel 4 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 3. "FH3_PEND_MASKED_SET,CPDMA FHost Channel 3 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 2. "FH2_PEND_MASKED_SET,CPDMA FHost Channel 2 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 1. "FH1_PEND_MASKED_SET,CPDMA FHost Channel 1 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 0. "FH0_PEND_MASKED_SET,CPDMA FHost Channel 0 Interrupt Pending MASKED Set" "0,1"
line.long 0x0C "CPDMA_FH_INTSTAT_MASKED_CLR_REG,CPDMA FHost Interrupt Masked CLR"
bitfld.long 0x0C 7. "FH7_PEND_MASKED_CLR,CPDMA FHost Channel 7 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 6. "FH6_PEND_MASKED_CLR,CPDMA FHost Channel 6 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 5. "FH5_PEND_MASKED_CLR,CPDMA FHost Channel 5 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 4. "FH4_PEND_MASKED_CLR,CPDMA FHost Channel 4 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 3. "FH3_PEND_MASKED_CLR,CPDMA FHost Channel 3 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 2. "FH2_PEND_MASKED_CLR,CPDMA FHost Channel 2 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 1. "FH1_PEND_MASKED_CLR,CPDMA FHost Channel 1 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 0. "FH0_PEND_MASKED_CLR,CPDMA FHost Channel 0 Interrupt Pending MASKED Clr" "0,1"
line.long 0x10 "CPDMA_IN_VECTOR_REG,CPDMA DMA IN Vector"
line.long 0x14 "CPDMA_EOI_VECTOR_REG,CPDMA DMA EOI Vector"
bitfld.long 0x14 0.--4. "DMA_EOI_VECTOR,CPDMA DMA EOI Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x340A0++0x5F
line.long 0x00 "CPDMA_TH_INTSTAT_RAW_REG,CPDMA Receive Interrupt Status RAW"
bitfld.long 0x00 15. "TH7_THRESH_PEND_RAW,CPDMA Receive Channel 7 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 14. "TH6_THRESH_PEND_RAW,CPDMA Receive Channel 6 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 13. "TH5_THRESH_PEND_RAW,CPDMA Receive Channel 5 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 12. "TH4_THRESH_PEND_RAW,CPDMA Receive Channel 4 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 11. "TH3_THRESH_PEND_RAW,CPDMA Receive Channel 3 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 10. "TH2_THRESH_PEND_RAW,CPDMA Receive Channel 2 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 9. "TH1_THRESH_PEND_RAW,CPDMA Receive Channel 1 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 8. "TH0_THRESH_PEND_RAW,CPDMA Receive Channel 0 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 7. "TH7_PEND_RAW,CPDMA Receive Channel 7 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 6. "TH6_PEND_RAW,CPDMA Receive Channel 6 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 5. "TH5_PEND_RAW,CPDMA Receive Channel 5 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 4. "TH4_PEND_RAW,CPDMA Receive Channel 4 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 3. "TH3_PEND_RAW,CPDMA Receive Channel 3 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 2. "TH2_PEND_RAW,CPDMA Receive Channel 2 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 1. "TH1_PEND_RAW,CPDMA Receive Channel 1 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 0. "TH0_PEND_RAW,CPDMA Receive Channel 0 Interrupt Pending RAW" "0,1"
line.long 0x04 "CPDMA_TH_INTSTAT_MASKED_REG,CPDMA Receive Interrupt Status MASKED"
bitfld.long 0x04 15. "TH7_THRESH_PEND_MASKED,CPDMA Receive Channel 7 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 14. "TH6_THRESH_PEND_MASKED,CPDMA Receive Channel 6 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 13. "TH5_THRESH_PEND_MASKED,CPDMA Receive Channel 5 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 12. "TH4_THRESH_PEND_MASKED,CPDMA Receive Channel 4 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 11. "TH3_THRESH_PEND_MASKED,CPDMA Receive Channel 3 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 10. "TH2_THRESH_PEND_MASKED,CPDMA Receive Channel 2 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 9. "TH1_THRESH_PEND_MASKED,CPDMA Receive Channel 1 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 8. "TH0_THRESH_PEND_MASKED,CPDMA Receive Channel 0 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 7. "TH7_PEND_MASKED,CPDMA Receive Channel 7 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 6. "TH6_PEND_MASKED,CPDMA Receive Channel 6 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 5. "TH5_PEND_MASKED,CPDMA Receive Channel 5 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 4. "TH4_PEND_MASKED,CPDMA Receive Channel 4 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 3. "TH3_PEND_MASKED,CPDMA Receive Channel 3 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 2. "TH2_PEND_MASKED,CPDMA Receive Channel 2 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 1. "TH1_PEND_MASKED,CPDMA Receive Channel 1 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 0. "TH0_PEND_MASKED,CPDMA Receive Channel 0 Interrupt Pending MASKED" "0,1"
line.long 0x08 "CPDMA_TH_INTSTAT_SET_REG,CPDMA THost Interrupt Masked SET"
bitfld.long 0x08 15. "TH7_THRESH_PEND_MASKED_SET,CPDMA THost Channel 7 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 14. "TH6_THRESH_PEND_MASKED_SET,CPDMA THost Channel 6 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 13. "TH5_THRESH_PEND_MASKED_SET,CPDMA THost Channel 5 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 12. "TH4_THRESH_PEND_MASKED_SET,CPDMA THost Channel 4 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 11. "TH3_THRESH_PEND_MASKED_SET,CPDMA THost Channel 3 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 10. "TH2_THRESH_PEND_MASKED_SET,CPDMA THost Channel 2 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 9. "TH1_THRESH_PEND_MASKED_SET,CPDMA THost Channel 1 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 8. "TH0_THRESH_PEND_MASKED_SET,CPDMA THost Channel 0 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 7. "TH7_PEND_MASKED_SET,CPDMA THost Channel 7 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 6. "TH6_PEND_MASKED_SET,CPDMA THost Channel 6 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 5. "TH5_PEND_MASKED_SET,CPDMA THost Channel 5 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 4. "TH4_PEND_MASKED_SET,CPDMA THost Channel 4 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 3. "TH3_PEND_MASKED_SET,CPDMA THost Channel 3 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 2. "TH2_PEND_MASKED_SET,CPDMA THost Channel 2 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 1. "TH1_PEND_MASKED_SET,CPDMA THost Channel 1 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 0. "TH0_PEND_MASKED_SET,CPDMA THost Channel 0 Interrupt Pending SET" "0,1"
line.long 0x0C "CPDMA_TH_INTSTAT_CLR_REG,CPDMA THost Interrupt Masked CLR"
bitfld.long 0x0C 15. "TH7_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 7 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 14. "TH6_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 6 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 13. "TH5_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 5 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 12. "TH4_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 4 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 11. "TH3_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 3 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 10. "TH2_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 2 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 9. "TH1_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 1 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 8. "TH0_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 0 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 7. "TH7_PEND_MASKED_CLR,CPDMA THost Channel 7 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 6. "TH6_PEND_MASKED_CLR,CPDMA THost Channel 6 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 5. "TH5_PEND_MASKED_CLR,CPDMA THost Channel 5 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 4. "TH4_PEND_MASKED_CLR,CPDMA THost Channel 4 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 3. "TH3_PEND_MASKED_CLR,CPDMA THost Channel 3 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 2. "TH2_PEND_MASKED_CLR,CPDMA THost Channel 2 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 1. "TH1_PEND_MASKED_CLR,CPDMA THost Channel 1 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 0. "TH0_PEND_MASKED_CLR,CPDMA THost Channel 0 Interrupt Pending CLR" "0,1"
line.long 0x10 "CPDMA_INTSTAT_RAW_REG,CPDMA DMA Interrupt Status RAW"
bitfld.long 0x10 1. "HOST_PEND_RAW,CPDMA HOST Interrupt Pending RAW" "0,1"
line.long 0x14 "CPDMA_INTSTAT_MASKED_REG,CPDMA DMA Interrupt Status MASKED"
bitfld.long 0x14 1. "HOST_PEND,CPDMA HOST Interrupt Pending MASKED" "0,1"
line.long 0x18 "CPDMA_INTSTAT_SET_REG,CPDMA DMA Interrupt Status SET"
bitfld.long 0x18 1. "HOST_PEND_MASKED_SET,CPDMA HOST Interrupt Masked SET" "0,1"
line.long 0x1C "CPDMA_INTSTAT_CLR_REG,CPDMA DMA Interrupt Status CLR"
bitfld.long 0x1C 1. "HOST_PEND_MASKED_CLR,CPDMA HOST Interrupt Masked CLR" "0,1"
line.long 0x20 "CPDMA_TH0_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x20 0.--7. 1. "TH0_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x24 "CPDMA_TH1_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x24 0.--7. 1. "TH1_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x28 "CPDMA_TH2_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x28 0.--7. 1. "TH2_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x2C "CPDMA_TH3_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x2C 0.--7. 1. "TH3_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x30 "CPDMA_TH4_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x30 0.--7. 1. "TH4_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x34 "CPDMA_TH5_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x34 0.--7. 1. "TH5_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x38 "CPDMA_TH6_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x38 0.--7. 1. "TH6_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x3C "CPDMA_TH7_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x3C 0.--7. 1. "TH7_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x40 "CPDMA_TH0_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x40 0.--14. 1. "TH0_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x44 "CPDMA_TH1_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x44 0.--14. 1. "TH1_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x48 "CPDMA_TH2_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x48 0.--14. 1. "TH2_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x4C "CPDMA_TH3_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x4C 0.--14. 1. "TH3_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x50 "CPDMA_TH4_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x50 0.--14. 1. "TH4_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x54 "CPDMA_TH5_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x54 0.--14. 1. "TH5_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x58 "CPDMA_TH6_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x58 0.--14. 1. "TH6_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x5C "CPDMA_TH7_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x5C 0.--14. 1. "TH7_FREEBUFFER,CPDMA THost Free Buffer Count Register"
group.long 0x34200++0x7F
line.long 0x00 "CPDMA_FH0_HDP_REG,CPDMA FHost Channel 0 Head Descriptor Pointer"
line.long 0x04 "CPDMA_FH1_HDP_REG,CPDMA FHost Channel 1 Head Descriptor Pointer"
line.long 0x08 "CPDMA_FH2_HDP_REG,CPDMA FHost Channel 2 Head Descriptor Pointer"
line.long 0x0C "CPDMA_FH3_HDP_REG,CPDMA FHost Channel 3 Head Descriptor Pointer"
line.long 0x10 "CPDMA_FH4_HDP_REG,CPDMA FHost Channel 4 Head Descriptor Pointer"
line.long 0x14 "CPDMA_FH5_HDP_REG,CPDMA FHost Channel 5 Head Descriptor Pointer"
line.long 0x18 "CPDMA_FH6_HDP_REG,CPDMA FHost Channel 6 Head Descriptor Pointer"
line.long 0x1C "CPDMA_FH7_HDP_REG,CPDMA FHost Channel 7 Head Descriptor Pointer"
line.long 0x20 "CPDMA_TH0_HDP_REG,CPDMA THost Channel 0 Head Descriptor Pointer"
line.long 0x24 "CPDMA_TH1_HDP_REG,CPDMA THost Channel 1 Head Descriptor Pointer"
line.long 0x28 "CPDMA_TH2_HDP_REG,CPDMA THost Channel 2 Head Descriptor Pointer"
line.long 0x2C "CPDMA_TH3_HDP_REG,CPDMA THost Channel 3 Head Descriptor Pointer"
line.long 0x30 "CPDMA_TH4_HDP_REG,CPDMA THost Channel 4 Head Descriptor Pointer"
line.long 0x34 "CPDMA_TH5_HDP_REG,CPDMA THost Channel 5 Head Descriptor Pointer"
line.long 0x38 "CPDMA_TH6_HDP_REG,CPDMA THost Channel 6 Head Descriptor Pointer"
line.long 0x3C "CPDMA_TH7_HDP_REG,CPDMA THost Channel 7 Head Descriptor Pointer"
line.long 0x40 "CPDMA_FH0_CP_REG,CPDMA FHost Channel 0 Completion Pointer"
line.long 0x44 "CPDMA_FH1_CP_REG,CPDMA FHost Channel 1 Completion Pointer"
line.long 0x48 "CPDMA_FH2_CP_REG,CPDMA FHost Channel 2 Completion Pointer"
line.long 0x4C "CPDMA_FH3_CP_REG,CPDMA FHost Channel 3 Completion Pointer"
line.long 0x50 "CPDMA_FH4_CP_REG,CPDMA FHost Channel 4 Completion Pointer"
line.long 0x54 "CPDMA_FH5_CP_REG,CPDMA FHost Channel 5 Completion Pointer"
line.long 0x58 "CPDMA_FH6_CP_REG,CPDMA FHost Channel 6 Completion Pointer"
line.long 0x5C "CPDMA_FH7_CP_REG,CPDMA FHost Channel 7 Completion Pointer"
line.long 0x60 "CPDMA_TH0_CP_REG,CPDMA THost Channel 0 Completion Pointer"
line.long 0x64 "CPDMA_TH1_CP_REG,CPDMA THost Channel 1 Completion Pointer"
line.long 0x68 "CPDMA_TH2_CP_REG,CPDMA THost Channel 2 Completion Pointer"
line.long 0x6C "CPDMA_TH3_CP_REG,CPDMA THost Channel 3 Completion Pointer"
line.long 0x70 "CPDMA_TH4_CP_REG,CPDMA THost Channel 4 Completion Pointer"
line.long 0x74 "CPDMA_TH5_CP_REG,CPDMA THost Channel 5 Completion Pointer"
line.long 0x78 "CPDMA_TH6_CP_REG,CPDMA THost Channel 6 Completion Pointer"
line.long 0x7C "CPDMA_TH7_CP_REG,CPDMA THost Channel 7 Completion Pointer"
group.long 0x34300++0x7F
line.long 0x00 "TEST_CPDMA_FH0_HDP_REG,Test CPDMA FHost Channel 0 Head Descriptor Pointer"
line.long 0x04 "TEST_CPDMA_FH1_HDP_REG,Test CPDMA FHost Channel 1 Head Descriptor Pointer"
line.long 0x08 "TEST_CPDMA_FH2_HDP_REG,Test CPDMA FHost Channel 2 Head Descriptor Pointer"
line.long 0x0C "TEST_CPDMA_FH3_HDP_REG,Test CPDMA FHost Channel 3 Head Descriptor Pointer"
line.long 0x10 "TEST_CPDMA_FH4_HDP_REG,Test CPDMA FHost Channel 4 Head Descriptor Pointer"
line.long 0x14 "TEST_CPDMA_FH5_HDP_REG,Test CPDMA FHost Channel 5 Head Descriptor Pointer"
line.long 0x18 "TEST_CPDMA_FH6_HDP_REG,Test CPDMA FHost Channel 6 Head Descriptor Pointer"
line.long 0x1C "TEST_CPDMA_FH7_HDP_REG,Test CPDMA FHost Channel 7 Head Descriptor Pointer"
line.long 0x20 "TEST_CPDMA_TH0_HDP_REG,Test CPDMA THost Channel 0 Head Descriptor Pointer"
line.long 0x24 "TEST_CPDMA_TH1_HDP_REG,Test CPDMA THost Channel 1 Head Descriptor Pointer"
line.long 0x28 "TEST_CPDMA_TH2_HDP_REG,Test CPDMA THost Channel 2 Head Descriptor Pointer"
line.long 0x2C "TEST_CPDMA_TH3_HDP_REG,Test CPDMA THost Channel 3 Head Descriptor Pointer"
line.long 0x30 "TEST_CPDMA_TH4_HDP_REG,Test CPDMA THost Channel 4 Head Descriptor Pointer"
line.long 0x34 "TEST_CPDMA_TH5_HDP_REG,Test CPDMA THost Channel 5 Head Descriptor Pointer"
line.long 0x38 "TEST_CPDMA_TH6_HDP_REG,Test CPDMA THost Channel 6 Head Descriptor Pointer"
line.long 0x3C "TEST_CPDMA_TH7_HDP_REG,Test CPDMA THost Channel 7 Head Descriptor Pointer"
line.long 0x40 "TEST_CPDMA_FH0_CP_REG,Test CPDMA FHost Channel 0 Completion Pointer"
line.long 0x44 "TEST_CPDMA_FH1_CP_REG,Test CPDMA FHost Channel 1 Completion Pointer"
line.long 0x48 "TEST_CPDMA_FH2_CP_REG,Test CPDMA FHost Channel 2 Completion Pointer"
line.long 0x4C "TEST_CPDMA_FH3_CP_REG,Test CPDMA FHost Channel 3 Completion Pointer"
line.long 0x50 "TEST_CPDMA_FH4_CP_REG,Test CPDMA FHost Channel 4 Completion Pointer"
line.long 0x54 "TEST_CPDMA_FH5_CP_REG,Test CPDMA FHost Channel 5 Completion Pointer"
line.long 0x58 "TEST_CPDMA_FH6_CP_REG,Test CPDMA FHost Channel 6 Completion Pointer"
line.long 0x5C "TEST_CPDMA_FH7_CP_REG,Test CPDMA FHost Channel 7 Completion Pointer"
line.long 0x60 "TEST_CPDMA_TH0_CP_REG,Test CPDMA THost Channel 0 Completion Pointer"
line.long 0x64 "TEST_CPDMA_TH1_CP_REG,Test CPDMA THost Channel 1 Completion Pointer"
line.long 0x68 "TEST_CPDMA_TH2_CP_REG,Test CPDMA THost Channel 2 Completion Pointer"
line.long 0x6C "TEST_CPDMA_TH3_CP_REG,Test CPDMA THost Channel 3 Completion Pointer"
line.long 0x70 "TEST_CPDMA_TH4_CP_REG,Test CPDMA THost Channel 4 Completion Pointer"
line.long 0x74 "TEST_CPDMA_TH5_CP_REG,Test CPDMA THost Channel 5 Completion Pointer"
line.long 0x78 "TEST_CPDMA_TH6_CP_REG,Test CPDMA THost Channel 6 Completion Pointer"
line.long 0x7C "TEST_CPDMA_TH7_CP_REG,Test CPDMA THost Channel 7 Completion Pointer"
group.long 0x3A000++0x0B
line.long 0x00 "RXGOODFRAMES,Total number of good frames received"
line.long 0x04 "RXBROADCASTFRAMES,Total number of good broadcast frames received"
line.long 0x08 "RXMULTICASTFRAMES,Total number of good multicast frames received"
group.long 0x3A010++0x03
line.long 0x00 "RXCRCERRORS,Total number of CRC errors frames received"
group.long 0x3A018++0x03
line.long 0x00 "RXOVERSIZEDFRAMES,Total number of oversized frames received"
group.long 0x3A020++0x1F
line.long 0x00 "RXUNDERSIZEDFRAMES,Total number of undersized frames received"
line.long 0x04 "RXFRAGMENTS,Total number of fragmented frames received"
line.long 0x08 "ALE_DROP,Total number of frames dropped by the ALE"
line.long 0x0C "ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
line.long 0x10 "RXOCTETS,Total number of received bytes in good frames"
line.long 0x14 "TXGOODFRAMES,Total number of good frames transmitted"
line.long 0x18 "TXBROADCASTFRAMES,Total number of good broadcast frames transmitted"
line.long 0x1C "TXMULTICASTFRAMES,Total number of good multicast frames transmitted"
group.long 0x3A04C++0x07
line.long 0x00 "TXSINGLECOLLFRAMES,Total number of transmitted frames experiencing a single collision"
line.long 0x04 "TXMULTCOLLFRAMES,Total number of transmitted frames experiencing multiple collisions"
group.long 0x3A064++0x7B
line.long 0x00 "TXOCTETS,Total number of bytes in all good frames transmitted"
line.long 0x04 "OCTETFRAMES64,Total number of 64-byte frames received and transmitted"
line.long 0x08 "OCTETFRAMES65T127,Total number of frames of size 65 to 127 bytes received and transmitted"
line.long 0x0C "OCTETFRAMES128T255,Total number of frames of size 128 to 255 bytes received and transmitted"
line.long 0x10 "OCTETFRAMES256T511,Total number of frames of size 256 to 511 bytes received and transmitted"
line.long 0x14 "OCTETFRAMES512T1023,Total number of frames of size 512 to 1023 bytes received and transmitted"
line.long 0x18 "OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
line.long 0x1C "NETOCTETS,Total number of bytes received and transmitted"
line.long 0x20 "RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop"
line.long 0x24 "PORTMASK_DROP,Total number of dropped frames received due to portmask"
line.long 0x28 "RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop"
line.long 0x2C "ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting"
line.long 0x30 "ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress"
line.long 0x34 "ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA"
line.long 0x38 "ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode"
line.long 0x3C "ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode"
line.long 0x40 "ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication"
line.long 0x44 "ALE_UNKN_UNI,ALE Receive Unknown Unicast"
line.long 0x48 "ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount"
line.long 0x4C "ALE_UNKN_MLT,ALE Receive Unknown Multicast"
line.long 0x50 "ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount"
line.long 0x54 "ALE_UNKN_BRD,ALE Receive Unknown Broadcast"
line.long 0x58 "ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount"
line.long 0x5C "ALE_POL_MATCH,ALE Policer Matched"
line.long 0x60 "ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red"
line.long 0x64 "ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow"
line.long 0x68 "ALE_MULT_SA_DROP,ALE Multicast Source Address Drop"
line.long 0x6C "ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop"
line.long 0x70 "ALE_LEN_ERROR_DROP,ALE Length Error Drop"
line.long 0x74 "ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop"
line.long 0x78 "ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop"
group.long 0x3A17C++0x03
line.long 0x00 "TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error"
group.long 0x3A200++0xDF
line.long 0x00 "RXGOODFRAMES,Total number of good frames received"
line.long 0x04 "RXBROADCASTFRAMES,Total number of good broadcast frames received"
line.long 0x08 "RXMULTICASTFRAMES,Total number of good multicast frames received"
line.long 0x0C "RXPAUSEFRAMES,Total number of pause frames received"
line.long 0x10 "RXCRCERRORS,Total number of CRC errors frames received"
line.long 0x14 "RXALIGNCODEERRORS,Total number of alignment/code errors received"
line.long 0x18 "RXOVERSIZEDFRAMES,Total number of oversized frames received"
line.long 0x1C "RXJABBERFRAMES,Total number of jabber frames received"
line.long 0x20 "RXUNDERSIZEDFRAMES,Total number of undersized frames received"
line.long 0x24 "RXFRAGMENTS,Total number of fragmented frames received"
line.long 0x28 "ALE_DROP,Total number of frames dropped by the ALE"
line.long 0x2C "ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
line.long 0x30 "RXOCTETS,Total number of received bytes in good frames"
line.long 0x34 "TXGOODFRAMES,Total number of good frames transmitted"
line.long 0x38 "TXBROADCASTFRAMES,Total number of good broadcast frames transmitted"
line.long 0x3C "TXMULTICASTFRAMES,Total number of good multicast frames transmitted"
line.long 0x40 "TXPAUSEFRAMES,Total number of pause frames transmitted"
line.long 0x44 "TXDEFERREDFRAMES,Total number of deferred frames transmitted"
line.long 0x48 "TXCOLLISIONFRAMES,Total number of transmitted frames experiencing a collision"
line.long 0x4C "TXSINGLECOLLFRAMES,Total number of transmitted frames experiencing a single collision"
line.long 0x50 "TXMULTCOLLFRAMES,Total number of transmitted frames experiencing multiple collisions"
line.long 0x54 "TXEXCESSIVECOLLISIONS,Total number of transmitted frames abandoned due to excessive collisions"
line.long 0x58 "TXLATECOLLISIONS,Total number of transmitted frames abandoned due to a late collision"
line.long 0x5C "RXIPGERROR,Total number of receive inter-packet gap errors (10G only)"
line.long 0x60 "TXCARRIERSENSEERRORS,Total number of transmitted frames that experienced a carrier loss"
line.long 0x64 "TXOCTETS,Total number of bytes in all good frames transmitted"
line.long 0x68 "OCTETFRAMES64,Total number of 64-byte frames received and transmitted"
line.long 0x6C "OCTETFRAMES65T127,Total number of frames of size 65 to 127 bytes received and transmitted"
line.long 0x70 "OCTETFRAMES128T255,Total number of frames of size 128 to 255 bytes received and transmitted"
line.long 0x74 "OCTETFRAMES256T511,Total number of frames of size 256 to 511 bytes received and transmitted"
line.long 0x78 "OCTETFRAMES512T1023,Total number of frames of size 512 to 1023 bytes received and transmitted"
line.long 0x7C "OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
line.long 0x80 "NETOCTETS,Total number of bytes received and transmitted"
line.long 0x84 "RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop"
line.long 0x88 "PORTMASK_DROP,Total number of dropped frames received due to portmask"
line.long 0x8C "RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop"
line.long 0x90 "ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting"
line.long 0x94 "ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress"
line.long 0x98 "ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA"
line.long 0x9C "ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode"
line.long 0xA0 "ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode"
line.long 0xA4 "ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication"
line.long 0xA8 "ALE_UNKN_UNI,ALE Receive Unknown Unicast"
line.long 0xAC "ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount"
line.long 0xB0 "ALE_UNKN_MLT,ALE Receive Unknown Multicast"
line.long 0xB4 "ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount"
line.long 0xB8 "ALE_UNKN_BRD,ALE Receive Unknown Broadcast"
line.long 0xBC "ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount"
line.long 0xC0 "ALE_POL_MATCH,ALE Policer Matched"
line.long 0xC4 "ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red"
line.long 0xC8 "ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow"
line.long 0xCC "ALE_MULT_SA_DROP,ALE Multicast Source Address Drop"
line.long 0xD0 "ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop"
line.long 0xD4 "ALE_LEN_ERROR_DROP,ALE Length Error Drop"
line.long 0xD8 "ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop"
line.long 0xDC "ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop"
group.long 0x3A37C++0x83
line.long 0x00 "TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error"
line.long 0x04 "ENET_PN_TX_PRI_REG_0,ENET Port n PRIORITY N Packet Count"
line.long 0x08 "ENET_PN_TX_PRI_REG_1,ENET Port n PRIORITY N Packet Count"
line.long 0x0C "ENET_PN_TX_PRI_REG_2,ENET Port n PRIORITY N Packet Count"
line.long 0x10 "ENET_PN_TX_PRI_REG_3,ENET Port n PRIORITY N Packet Count"
line.long 0x14 "ENET_PN_TX_PRI_REG_4,ENET Port n PRIORITY N Packet Count"
line.long 0x18 "ENET_PN_TX_PRI_REG_5,ENET Port n PRIORITY N Packet Count"
line.long 0x1C "ENET_PN_TX_PRI_REG_6,ENET Port n PRIORITY N Packet Count"
line.long 0x20 "ENET_PN_TX_PRI_REG_7,ENET Port n PRIORITY N Packet Count"
line.long 0x24 "ENET_PN_TX_PRI_BCNT_REG_0,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x28 "ENET_PN_TX_PRI_BCNT_REG_1,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x2C "ENET_PN_TX_PRI_BCNT_REG_2,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x30 "ENET_PN_TX_PRI_BCNT_REG_3,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x34 "ENET_PN_TX_PRI_BCNT_REG_4,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x38 "ENET_PN_TX_PRI_BCNT_REG_5,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x3C "ENET_PN_TX_PRI_BCNT_REG_6,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x40 "ENET_PN_TX_PRI_BCNT_REG_7,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x44 "ENET_PN_TX_PRI_DROP_REG_0,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x48 "ENET_PN_TX_PRI_DROP_REG_1,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x4C "ENET_PN_TX_PRI_DROP_REG_2,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x50 "ENET_PN_TX_PRI_DROP_REG_3,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x54 "ENET_PN_TX_PRI_DROP_REG_4,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x58 "ENET_PN_TX_PRI_DROP_REG_5,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x5C "ENET_PN_TX_PRI_DROP_REG_6,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x60 "ENET_PN_TX_PRI_DROP_REG_7,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x64 "ENET_PN_TX_PRI_DROP_BCNT_REG_0,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x68 "ENET_PN_TX_PRI_DROP_BCNT_REG_1,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x6C "ENET_PN_TX_PRI_DROP_BCNT_REG_2,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x70 "ENET_PN_TX_PRI_DROP_BCNT_REG_3,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x74 "ENET_PN_TX_PRI_DROP_BCNT_REG_4,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x78 "ENET_PN_TX_PRI_DROP_BCNT_REG_5,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x7C "ENET_PN_TX_PRI_DROP_BCNT_REG_6,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x80 "ENET_PN_TX_PRI_DROP_BCNT_REG_7,ENET Port n PRIORITY N Packet Drop Byte Count"
rgroup.long 0x3D000++0x5B
line.long 0x00 "IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,Identification value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CONTROL_REG,Time Sync Control Register"
bitfld.long 0x04 28.--31. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1"
newline
bitfld.long 0x04 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1"
newline
bitfld.long 0x04 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
newline
bitfld.long 0x04 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
newline
bitfld.long 0x04 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
newline
bitfld.long 0x04 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
newline
bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
newline
bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
newline
bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
newline
bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
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bitfld.long 0x04 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1"
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bitfld.long 0x04 6. "TS_COMP_TOG,Timestamp Compare Toggle mode" "TS_COMP is in non-toggle mode,TS_COMP is in toggle mode"
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bitfld.long 0x04 5. "MODE,Timestamp mode" "0,1"
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bitfld.long 0x04 4. "SEQUENCE_EN,Sequence Enable" "0,1"
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bitfld.long 0x04 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1"
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bitfld.long 0x04 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1"
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bitfld.long 0x04 1. "INT_TEST,Interrupt test" "0,1"
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bitfld.long 0x04 0. "CPTS_EN,Time sync enable" "0,1"
line.long 0x08 "RFTCLK_SEL_REG,RFTCLK Select Register"
bitfld.long 0x08 0.--4. "RFTCLK_SEL,Reference clock select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x0C 0. "TS_PUSH,Time stamp event push" "0,1"
line.long 0x10 "TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
line.long 0x14 "TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x14 0. "TS_LOAD_EN,Time stamp load enable" "0,1"
line.long 0x18 "TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
line.long 0x1C "TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
line.long 0x20 "INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x20 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
line.long 0x24 "INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x24 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
line.long 0x28 "INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x28 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x2C "TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x2C 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
line.long 0x30 "EVENT_POP_REG,Event Pop Register"
bitfld.long 0x30 0. "EVENT_POP,Event pop" "0,1"
line.long 0x34 "EVENT_0_REG,Event 0 Register"
line.long 0x38 "EVENT_1_REG,Event 1 Register"
bitfld.long 0x38 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
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bitfld.long 0x38 24.--28. "PORT_NUMBER,Port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 20.--23. "EVENT_TYPE,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 16.--19. "MESSAGE_TYPE,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x38 0.--15. 1. "SEQUENCE_ID,Sequence ID"
line.long 0x3C "EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x3C 0.--7. 1. "DOMAIN,Domain"
line.long 0x40 "EVENT_3_REG,Event 3 Register"
line.long 0x44 "TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
line.long 0x48 "TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
line.long 0x4C "TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x4C 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7"
line.long 0x50 "TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
line.long 0x54 "TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x54 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value"
line.long 0x58 "TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x58 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value"
group.long 0x3D0E0++0x1B
line.long 0x00 "COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
line.long 0x04 "COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
line.long 0x08 "CONTROL_REG,Time Stamp Generate Function Control"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1"
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bitfld.long 0x08 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1"
line.long 0x0C "LENGTH_REG,Time Stamp Generate Function Length Value"
line.long 0x10 "PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
line.long 0x14 "PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
line.long 0x18 "NUDGE_REG,Time Stamp Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
group.long 0x3D200++0x1B
line.long 0x00 "COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value"
line.long 0x04 "COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value"
line.long 0x08 "CONTROL_REG,Time Stamp ESTF Generate Function Control"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1"
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bitfld.long 0x08 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1"
line.long 0x0C "LENGTH_REG,Time Stamp ESTF Generate Function Length Value"
line.long 0x10 "PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value"
line.long 0x14 "PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value"
line.long 0x18 "NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value"
rgroup.long 0x3E000++0x17
line.long 0x00 "MOD_VER,The Module and Version Register identifies the module identifier and revision of the ALE_2g32 module"
hexmask.long.word 0x00 16.--31. 1. "MODULE_ID,ALE_2g32 module ID"
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bitfld.long 0x00 11.--15. "RTL_VERSION,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR_REVISION,Major Revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM_REVISION,Custom Revision" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR_REVISION,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ALE_STATUS,The ALE status provides information on the ALE configuration and state"
bitfld.long 0x04 31. "UREGANDREGMSK12,When set the unregistered multicast field is a mask versus an index on 12 bit boundary in the ALE table" "0,1"
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bitfld.long 0x04 30. "UREGANDREGMSK08,When set the unregistered multicast field is a mask versus an index on 8 bit boundary in the ALE table" "0,1"
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hexmask.long.byte 0x04 8.--15. 1. "POLCNTDIV8,This is the number of policer engines the ALE implements divided by 8"
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bitfld.long 0x04 7. "RAMDEPTH128,The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both ramdepth128 and ramdepth32 are zero the depth is 64" "0,1"
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bitfld.long 0x04 6. "RAMDEPTH32,The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both ramdepth128 and ramdepth32 are zero the depth is 64" "0,1"
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bitfld.long 0x04 0.--4. "KLUENTRIES,This is the number of table entries total divided by 1024" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "ALE_CONTROL,The ALE Control Register is used to set the ALE modes used for all ports"
bitfld.long 0x08 31. "ENABLE_ALE,Enable ALE " "Drop all packets,Enable ALE packet processing"
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bitfld.long 0x08 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero" "0,1"
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bitfld.long 0x08 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit" "0,1"
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bitfld.long 0x08 24. "MIRROR_DP,Mirror Destination Port - This field defines the port to which destination traffic destined will be duplicated" "0,1"
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bitfld.long 0x08 21.--23. "UPD_BW_CTRL,The ~iupd_bw_ctrl field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16. "MIRROR_TOP,Mirror To Port - This field defines the destination port for the mirror traffic" "0,1"
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bitfld.long 0x08 15. "UPD_STATIC,Update Static Entries - A static Entry is an entry that is not agable" "0,1"
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bitfld.long 0x08 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn - This field when set will prevent source addresses of unknown VLAN IDs from being automatically added into the look up table if learning is enabled" "0,1"
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bitfld.long 0x08 12. "MIRROR_MEN,Mirror Match Entry Enable - This field enables the match mirror option" "0,1"
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bitfld.long 0x08 11. "MIRROR_DEN,Mirror Destination Port Enable - This field enables the destination port mirror option" "0,1"
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bitfld.long 0x08 10. "MIRROR_SEN,Mirror Source Port Enable - This field enables the source port mirror option" "0,1"
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bitfld.long 0x08 8. "EN_HOST_UNI_FLOOD,Unknown unicast packets flood to host " "unknown unicast packets are not sent to the host,unknown unicast packets flood to host port as.."
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bitfld.long 0x08 7. "LEARN_NO_VLANID,Learn No VID - " "VID is learned with the source address,VID is not learned with the source address.."
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bitfld.long 0x08 6. "ENABLE_VID0_MODE,Enable VLAN ID = 0 Mode " "Process the priority tagged packet with VID =..,Process the priority tagged packet with VID = 0"
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bitfld.long 0x08 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode - When set any packet with a non-matching OUI source address will be dropped to the host unless the packet destination address matches a supervisory destination address table entry" "0,1"
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bitfld.long 0x08 4. "ENABLE_BYPASS,ALE Bypass - When set packets received on non-host ports are sent to the host" "no bypass,bypass the ALE"
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bitfld.long 0x08 3. "BCAST_MCAST_CTL,Rate Limit Transmit mode " "Broadcast and multicast rate limit counters are..,Broadcast and multicast rate limit counters are.."
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bitfld.long 0x08 2. "ALE_VLAN_AWARE,ALE VLAN Aware - Determines how traffic is forwarded using VLAN rules. " "Simple switch rules packets forwarded to all..,VLAN Aware rules packets forwarded based on VLAN.."
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bitfld.long 0x08 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software" "The ALE is not in MAC authorization mode,The ALE is in MAC authorization mode"
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bitfld.long 0x08 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit " "Broadcast/Multicast rates not limited,Broadcast/Multicast packet reception limited to.."
line.long 0x0C "ALE_CTRL2,The ALE Control 2 Register is used to set the extended features used for all ports"
bitfld.long 0x0C 31. "TRK_EN_DST,Trunk Enable Destination Address - This field enables the destination MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 30. "TRK_EN_SRC,Trunk Enable Source Address - This field enables the source MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 29. "TRK_EN_PRI,Trunk Enable Priority - This field enables the VLAN Priority bits to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 27. "TRK_EN_IVLAN,Trunk Enable Inner VLAN - This field enables the inner VLAN ID value (C-VLANID) to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 25. "TRK_EN_SIP,Trunk Enable Source IP Address - This field enables the source IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged VLAN tagged.." "0,1"
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bitfld.long 0x0C 24. "TRK_EN_DIP,Trunk Enable Destination IP Address - This field enables the destination IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged.." "0,1"
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bitfld.long 0x0C 23. "DROP_BADLEN,Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet" "0,1"
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bitfld.long 0x0C 22. "NODROP_SRCMCST,No Drop Source Multicast will disable the dropping of any source address with the multicast bit set" "0,1"
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bitfld.long 0x0C 21. "DEFNOFRAG,Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found" "0,1"
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bitfld.long 0x0C 20. "DEFLMTNXTHDR,Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match the ~iALE_NXT_HDR register values" "0,1"
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bitfld.long 0x0C 16.--18. "TRK_BASE,Trunk Base - This field is the hash formula starting value" "?,~i00000000,~i01010101,~i02102102,~i03210321,?..."
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bitfld.long 0x0C 0.--4. "MIRROR_MIDX,Mirror Index - This field is the ALE lookup table entry index that when a match occurs will cause this traffic to be mirrored to the ~imirror_top port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "ALE_PRESCALE,The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value"
hexmask.long.tbyte 0x10 0.--19. 1. "ALE_PRESCALE,ALE Prescale - The input clock is divided by this value for use in the multicast/broadcast rate limiters"
line.long 0x14 "ALE_AGING_CTRL,The ALE Aging Control sets the aging interval which will cause periodic aging to occur"
bitfld.long 0x14 31. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable - When set will divide the aging interval by 1000" "0,1"
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bitfld.long 0x14 30. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable - When set will divide the aging interval by 1000" "0,1"
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hexmask.long.tbyte 0x14 0.--23. 1. "ALE_AGING_TIMER,ALE Aging Timer - This field specifies the number of clock cycles times 1 000 000 between aging operations"
group.long 0x3E01C++0x07
line.long 0x00 "ALE_NXT_HDR,The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header"
hexmask.long.byte 0x00 24.--31. 1. "IP_NXT_HDR3,The ~iip_nxt_hdr3 is the forth protocol or next header compared when enabled"
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hexmask.long.byte 0x00 16.--23. 1. "IP_NXT_HDR2,The ~iip_nxt_hdr2 is the third protocol or next header compared when enabled"
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hexmask.long.byte 0x00 8.--15. 1. "IP_NXT_HDR1,The ~iip_nxt_hdr1 is the second protocol or next header compared when enabled"
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hexmask.long.byte 0x00 0.--7. 1. "IP_NXT_HDR0,The ~iip_nxt_hdr0 is the first protocol or next header compared when enabled"
line.long 0x04 "ALE_TBLCTL,The ALE table control register is used to read or write that ALE table entries"
bitfld.long 0x04 31. "TABLEWR,Table Write - This bit is used to write the table words to the lookup table. " "Table Read Operation is performed,Table write operation is performed"
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bitfld.long 0x04 0.--4. "TABLEIDX,The table index is used to determine which lookup table entry is read or written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3E034++0x0B
line.long 0x00 "ALE_TBLW2,The ALE Table Word 2 is the most significant word of an ALE table entry"
hexmask.long.byte 0x00 0.--6. 1. "TABLEWRD2,Table Entry bits [71:64]"
line.long 0x04 "ALE_TBLW1,The ALE Table Word 1 is the middle word of an ALE table entry"
line.long 0x08 "ALE_TBLW0,The ALE Table Word 0 is the least significant word of an ALE table entry"
repeat 2. (list 0x0 0x1 )(list 0x0 0x4 )
group.long ($2+0x3E040)++0x03
line.long 0x00 "I0_ALE_PORTCTL0_$1,The ALE Port Control Register sets the port specific modes of operation"
hexmask.long.byte 0x00 24.--31. 1. "I0_REG_P0_BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter"
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hexmask.long.byte 0x00 16.--23. 1. "I0_REG_P0_MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter"
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bitfld.long 0x00 15. "I0_REG_P0_DROP_DOUBLE_VLAN,Drop Double VLAN - When set cause any received packet with double VLANs to be dropped" "0,1"
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bitfld.long 0x00 14. "I0_REG_P0_DROP_DUAL_VLAN,Drop Dual VLAN - When set will cause any received packet with dual VLAN stag followed by ctag to be dropped" "0,1"
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bitfld.long 0x00 13. "I0_REG_P0_MACONLY_CAF,Mac Only Copy All Frames - When set a Mac Only port will transfer all received good frames to the host" "0,1"
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bitfld.long 0x00 12. "I0_REG_P0_DIS_PAUTHMOD,Disable Port" "0,1"
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bitfld.long 0x00 11. "I0_REG_P0_MACONLY,MAC Only - When set enables this port be treated like a MAC port for the host" "0,1"
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bitfld.long 0x00 10. "I0_REG_P0_TRUNKEN,Trunk Enable - This field is used to enable a port into a trunk" "0,1"
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bitfld.long 0x00 8.--9. "I0_REG_P0_TRUNKNUM,Trunk Number - This field is used as the trunk number when the ~ip0_trunken is also set" "0,1,2,3"
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bitfld.long 0x00 7. "I0_REG_P0_MIRROR_SP,Mirror Source Port - This field enables the source port mirror option" "0,1"
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bitfld.long 0x00 5. "I0_REG_P0_NO_SA_UPDATE,No Source Address Update - When set will not update the source addresses for this port" "0,1"
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bitfld.long 0x00 4. "I0_REG_P0_NO_LEARN,No Learn - When set will not learn the source addresses for this port" "0,1"
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bitfld.long 0x00 3. "I0_REG_P0_VID_INGRESS_CHECK,VLAN Ingress" "0,1"
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bitfld.long 0x00 2. "I0_REG_P0_DROP_UN_TAGGED,If Drop Untagged - When set will drop packets without a VLAN tag" "0,1"
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bitfld.long 0x00 0.--1. "I0_REG_P0_PORTSTATE,Port State - Defins the current port state used for lookup operations. " "Disabled,Blocked,Learning,Forwarding"
repeat.end
group.long 0x3E090++0x0F
line.long 0x00 "ALE_UVLAN_MEMBER,The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID"
bitfld.long 0x00 0.--1. "UVLAN_MEMBER_LIST,Unknown VLAN Member List - Each bit represents the port member status for unknown VLANs" "0,1,2,3"
line.long 0x04 "ALE_UVLAN_URCAST,The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID"
bitfld.long 0x04 0.--1. "UVLAN_UNREG_MCAST,Unknown VLAN Unregister Multicast Flood Mask - Each bit represents the port to which unregistered multicast are sent for unregistered VLANs" "0,1,2,3"
line.long 0x08 "ALE_UVLAN_RMCAST,The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID"
bitfld.long 0x08 0.--1. "UVLAN_REG_MCAST_FLOOD_MASK,Unknown VLAN Register Multicast Flood Mask - Each bit represents the port to which registered multicast are sent for unregistered VLANs" "0,1,2,3"
line.long 0x0C "ALE_UVLAN_UNTAG,The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed"
bitfld.long 0x0C 0.--1. "UVLAN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress Mask - Each bit represents the port where the VLAN will be removed for unregistered VLANs" "0,1,2,3"
group.long 0x3E0B8++0x0B
line.long 0x00 "ALE_STAT_DIAG,The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters"
bitfld.long 0x00 15. "PBCAST_DIAG,When set and the ~iport_diag is set to zero will allow all ports to see the same stat diagnostic increment" "0,1"
newline
bitfld.long 0x00 8. "PORT_DIAG,The port selected that a received packet will cause the selected error to increment" "0,1"
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bitfld.long 0x00 0.--3. "STAT_DIAG,When non-zero will cause the selected statistic to increment on the next frame received" "Disabled,Destination Equal Source Drop Stat will count,VLAN Ingress Check Drop Stat will count,Source Multicast Drop Stat will count,Dual VLAN Drop Stat will count,Ether Type length error Drop Stat will count,Next Hop Limit Drop Stat will count,IPv4 Fragment Drop Stat will count,Classifier Hit Stat will count,Classifier Red Drop Stat will count,Classifier Yellow Drop Stat will count,ALE Overflow Drop Stat will count,Rate Limit Drop Stat will count,Blocked Address Drop Stat will count,Secure Address Drop Stat will count,Authorization Drop Stat will count"
line.long 0x04 "ALE_OAM_LB_CTRL,The ALE OAM Control allows ports to be put into OAM Loopback. only non-supervisor packet are looped back to the source port"
bitfld.long 0x04 0.--1. "OAM_LB_CTRL,The ~ioam_lb_ctrl allows any port to be put into OAM loopback that is any packet received will be returned to the same port with an egressop of 0xFF which swaps the source and destination address" "0,1,2,3"
line.long 0x08 "ALE_MSK_MUX0,VLAN Mask Mux x - The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for vlan registered and unregister mask respectively"
bitfld.long 0x08 0.--1. "VLAN_MASK_MUX_0,VLAN Mask Mux x - When selected by the VLAN lookup table entry FwdUnRegIdx or FwdAllRegIdx is used as the FwdUnRegMask or FwdUnRegMask values anded with the member list to determine the forwarding of packets" "0,1,2,3"
repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x4 0x8 )
group.long ($2+0x3E0C4)++0x03
line.long 0x00 "I1_ALE_MSK_MUX1_$1,VLAN Mask Mux x - The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for vlan registered and unregister mask respectively"
bitfld.long 0x00 0.--1. "I1_REG_VLAN_MASK_MUX_1,VLAN Mask Mux x - When selected by the VLAN lookup table entry FwdUnRegIdx or FwdAllRegIdx is used as the FwdUnRegMask or FwdUnRegMask values anded with the member list to determine the forwarding of packets" "0,1,2,3"
repeat.end
group.long 0x3E0FC++0x17
line.long 0x00 "EGRESSOP,The Egress Operation register allows enabled classifiers with IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions"
abitfld.long 0x00 24.--31. "EGRESS_OP,The Egress Operation defines the operation performed by the CPSW Egress Packet Operations " "0x00=NOP,0xFF=Swap SA and DA of packet this is intended.."
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bitfld.long 0x00 21.--23. "EGRESS_TRK,The Egress Trunk Index is the calculated trunk index from the SA DA or VLAN if modified to that InterVLAN routing will work on trunks as well" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "TTL_CHECK,The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions" "0,1"
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bitfld.long 0x00 0.--1. "DEST_PORTS,The Destination Ports is a list of the ports the classified packet will be set to" "0,1,2,3"
line.long 0x04 "POLICECFG0,The Policing Config 0 holds the port. frame priority and ONU address index as well as match enables for port. frame priority and ONU address matching"
bitfld.long 0x04 31. "PORT_MEN,Port Match Enable - Enabled port match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 30. "TRUNKID,Trunk ID - When set indicates the port number is a trunk group" "0,1"
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bitfld.long 0x04 25. "PORT_NUM,Port Number - Specifies the port address to match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 19. "PRI_MEN,Priority Match Enable - Enables frame priority match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 16.--18. "PRI_VAL,Priority Value - Specifies the frame priority to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 15. "ONU_MEN,OUI Match Enable - Enables frame ONU address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 0.--4. "ONU_INDEX,OUI Table Entry Index - Specifies the ALE ONU address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "POLICECFG1,The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses"
bitfld.long 0x08 31. "DST_MEN,Destination Address Match Enable - Enables frame L2 destination address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x08 16.--20. "DST_INDEX,Destination Address Table Entry Index - Specifies the ALE L2 destination address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 15. "SRC_MEN,Source Address Match Enable - Enables frame L2 source address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x08 0.--4. "SRC_INDEX,Source Address Table Entry Index - Specifies the ALE L2 source address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "POLICECFG2,The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses"
bitfld.long 0x0C 31. "OVLAN_MEN,Outer VLAN Match Enable - Enables frame Outer VLAN address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x0C 16.--20. "OVLAN_INDEX,Outer VLAN Table Entry Index - Specifies the ALE Outer VLAN address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 15. "IVLAN_MEN,Inner VLAN Match Enable - Enables frame Inner VLAN address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x0C 0.--4. "IVLAN_INDEX,Inner VLAN Table Entry Index - Specifies the ALE Inner VLAN address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "POLICECFG3,The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address"
bitfld.long 0x10 31. "ETHERTYPE_MEN,EtherType Match Enable - Enables frame Ether Type match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x10 16.--20. "ETHERTYPE_INDEX,EtherType Table Entry Index - Specifies the ALE Ether Type lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 15. "IPSRC_MEN,IP Source Address Match Enable - Enables frame IP Source address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x10 0.--4. "IPSRC_INDEX,IP Source Address Table Entry Index - Specifies the ALE IP Source address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "POLICECFG4,The Policing Config 4 holds the match enable/match index for the IP Destination address"
bitfld.long 0x14 31. "IPDST_MEN,IP Destination Address Match Enable - Enables frame IP Destination address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x14 16.--20. "IPDST_INDEX,IP Destination Address Table Entry Index - Specifies the ALE IP Destination address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3E118++0x17
line.long 0x00 "POLICECFG6,The PIR counter is a 37 bit internal counter where ~ipir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time"
line.long 0x04 "POLICECFG7,The CIR counter is a 37 bit internal counter where ~icir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time"
line.long 0x08 "POLICETBLCTL,The Policing Table Control is used to read or write the selected policing/classifier entry"
bitfld.long 0x08 31. "WRITE_ENABLE,Write Enable - Setting this bit will write the POLICECFG0-7 to the ~ipol_tbl_idx selected policing/classifier entry" "0,1"
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bitfld.long 0x08 0.--1. "POL_TBL_IDX,Policer Entry Index - This field specifies the policing/classifier entry to be read or written" "0,1,2,3"
line.long 0x0C "POLICECONTROL,The Control Enables color marking as well as internal ALE packet dropping rules"
bitfld.long 0x0C 31. "POLICING_EN,Policing Enable - Enables the policing to color the packets this also enables red or yellow drop capabilities" "0,1"
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bitfld.long 0x0C 29. "RED_DROP_EN,RED Drop Enable - Enables the ALE to drop the red colored packets" "0,1"
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bitfld.long 0x0C 28. "YELLOW_DROP_EN,WELLOW Drop Enable - Enables the ALE to drop yellow packets based on the ~iyellowthresh value" "0,1"
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bitfld.long 0x0C 24.--26. "YELLOWTHRESH,Yellow Threshold - When set enables a portion of the yellow packets to be dropped based on the ~iyellow_drop_en enable. 0-100% " "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 22.--23. "POLMCHMODE,Policing Match Mode - This field determines what happens to packets that fail to hit any policing/classifier entry. " "No Hit packets are marked GREEN,No Hit packets are marked YELLOW,No Hit packets are marked RED,No Hit packets are marked based on.."
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bitfld.long 0x0C 21. "PRIORITY_THREAD_EN,Priority Thread Enable - This field determines if priority is OR'd to the default thread when no classifiers hit and the default thread is enabled" "0,1"
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bitfld.long 0x0C 20. "MAC_ONLY_DEF_DIS,MAC Only Default Disable - This field when set disables the default thread on MAC Only Ports" "0,1"
line.long 0x10 "POLICETESTCTL,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition"
bitfld.long 0x10 31. "POL_CLRALL_HIT,Policer Clear - This bit clears all the policing/classifier hit bits" "0,1"
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bitfld.long 0x10 30. "POL_CLRALL_REDHIT,Policer Clear RED - This bit clears all the policing/classifier RED hit bits" "0,1"
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bitfld.long 0x10 29. "POL_CLRALL_YELLOWHIT,Policer Clear YELLOW - This bit clears all the policing/classifier YELLOW hit bits" "0,1"
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bitfld.long 0x10 28. "POL_CLRSEL_ALL,Police Clear Selected - This bit clears the selected policing/classifier hit redhit and yellowhit bits" "0,1"
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bitfld.long 0x10 0.--1. "POL_TEST_IDX,Policer Test Index - This field selects which policing/classifier hit bits will be read or written" "0,1,2,3"
line.long 0x14 "POLICEHSTAT,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier"
bitfld.long 0x14 31. "POL_HIT,Policer Hit - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit by a packet seen on any port that matches the policing/classifier entry match" "0,1"
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bitfld.long 0x14 30. "POL_REDHIT,Policer Hit RED - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit during a RED condition by a packet seen on any port that matches the policing/classifier entry match" "0,1"
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bitfld.long 0x14 29. "POL_YELLOWHIT,Policer Hit YELLOW - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit during a YELLOW condition by a packet seen on any port that matches the policing/classifier entry match" "0,1"
group.long 0x3E134++0x0B
line.long 0x00 "THREADMAPDEF,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched."
bitfld.long 0x00 15. "DEFTHREAD_EN,Default Tread Enable - When set the switch will use the ~idefthreadval for the host interface thread ID if no classifier is matched" "0,1"
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bitfld.long 0x00 0.--5. "DEFTHREADVAL,Default Thread Value - This field specifies the default thread ID value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "THREADMAPCTL,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host"
bitfld.long 0x04 0.--1. "CLASSINDEX,Classifier Index - This is the classifier index entry that the thread enable and thread value will be read or written by the ~bTHREADMAPVAL register" "0,1,2,3"
line.long 0x08 "THREADMAPVAL,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry"
bitfld.long 0x08 15. "THREAD_EN,Thread Enable - When set the switch will use the ~ithreadval for the selected classifier match" "0,1"
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bitfld.long 0x08 0.--5. "THREADVAL,Thread Value - This field is the thread ID value that is used to map a classifier hit to thread ID for host traffic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x3F000++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3F008++0x27
line.long 0x00 "vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
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bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "reserved_svbus_0,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x0C "reserved_svbus_1,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x10 "reserved_svbus_2,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x14 "reserved_svbus_3,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x18 "reserved_svbus_4,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x1C "reserved_svbus_5,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x20 "reserved_svbus_6,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x24 "reserved_svbus_7,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3F03C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
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bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
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bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
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bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
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bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
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bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
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bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
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bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
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bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
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bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
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bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
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bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
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bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
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bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
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bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
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bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
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bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
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bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
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bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
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bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x3F080++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
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bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
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bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
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bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
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bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
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bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
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bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
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bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
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bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
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bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
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bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
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bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
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bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
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bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
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bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
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bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
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bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
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bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
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bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
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bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x3F0C0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
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bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
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bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
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bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
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bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
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bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
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bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
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bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
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bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
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bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
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bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
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bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
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bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
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bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
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bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
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bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
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bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
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bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
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bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
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bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x3F13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
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bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
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bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
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bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
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bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
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bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
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bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
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bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
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bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
newline
bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
newline
bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
newline
bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
newline
bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
newline
bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
newline
bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
newline
bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
newline
bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
newline
bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
newline
bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
newline
bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x3F180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
newline
bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
newline
bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
newline
bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
newline
bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
newline
bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
newline
bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
newline
bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
newline
bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
newline
bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
newline
bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
newline
bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
newline
bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
newline
bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
newline
bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x3F1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
newline
bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
newline
bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
newline
bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
newline
bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
newline
bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
newline
bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
newline
bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
newline
bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
newline
bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
newline
bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
newline
bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
newline
bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
newline
bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
newline
bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x3F200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_CTRL (MSS CTRL Module Registers)"
base ad:0x52120000
rgroup.long 0x00++0x517
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MSS_SW_INT,"
bitfld.long 0x04 0.--4. "pulse,Write_pulse bit field: writing 1'b1 to each bit will trigger MSS_SW_INT<0-4> respectively to CR5A/B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "MSS_CAPEVNT_SEL,"
hexmask.long.byte 0x08 8.--15. 1. "src1,Writing a value 'N' will select Nth interrupt from CR5A/B interrupt mapping to trigger CAP-EVENT1 to all MSS_RTIs"
newline
hexmask.long.byte 0x08 0.--7. 1. "src0,Writing a value 'N' will select Nth interrupt from CR5A/B interrupt mapping to trigger CAP-EVENT0 to all MSS_RTIs"
line.long 0x0C "MSS_DMA_REQ_SEL,"
line.long 0x10 "MSS_DMA1_REQ_SEL,"
line.long 0x14 "MSS_IRQ_REQ_SEL,"
line.long 0x18 "MSS_SPI_TRIG_SRC,"
hexmask.long.word 0x18 16.--26. 1. "trig_spib,Writing 1'b1 to each bit will trigger MSS_SPIB Trigger<0-10> respectively"
newline
bitfld.long 0x18 0.--1. "trig_spia,Writing 1'b1 to each bit will trigger MSS_SPIA Trigger<0-1> respectively" "0,1,2,3"
line.long 0x1C "MSS_ATCM_MEM_INIT,"
bitfld.long 0x1C 0. "mem_init,Write_pulse bit field: Writing 1'b1 will start initializing the ATCM banks of CR5A/B" "0,1"
line.long 0x20 "MSS_ATCM_MEM_INIT_DONE,"
bitfld.long 0x20 0. "mem_init_done,This field will be high once initialization of ATCM banks is finished" "0,1"
line.long 0x24 "MSS_ATCM_MEM_INIT_STATUS,"
bitfld.long 0x24 0. "mem_status," "0,1"
line.long 0x28 "MSS_BTCM_MEM_INIT,"
bitfld.long 0x28 0. "mem_init,Write_pulse bit field: Writing 1'b1 will start initializing the B0/1TCM banks of CR5A/B" "0,1"
line.long 0x2C "MSS_BTCM_MEM_INIT_DONE,"
bitfld.long 0x2C 0. "mem_init_done,This field will be high once initialization of B0/1TCM banks is finished" "0,1"
line.long 0x30 "MSS_BTCM_MEM_INIT_STATUS,"
bitfld.long 0x30 0. "mem_status," "0,1"
line.long 0x34 "MSS_L2_MEM_INIT,"
bitfld.long 0x34 1. "partition1,Write_pulse bit field: Writing 1'b1 will start initializing the L2 Bank1" "0,1"
newline
bitfld.long 0x34 0. "partition0,Write_pulse bit field: Writing 1'b1 will start initializing the L2 Bank0" "0,1"
line.long 0x38 "MSS_L2_MEM_INIT_DONE,"
bitfld.long 0x38 1. "partition1,This field will be high once intialization of L2 bank1 is finished" "0,1"
newline
bitfld.long 0x38 0. "partition0,This field will be high once intialization of L2 bank0 is finished" "0,1"
line.long 0x3C "MSS_L2_MEM_INIT_STATUS,"
bitfld.long 0x3C 1. "partition1," "0,1"
newline
bitfld.long 0x3C 0. "partition0," "0,1"
line.long 0x40 "MSS_MAILBOX_MEM_INIT,"
bitfld.long 0x40 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_MBOX" "0,1"
line.long 0x44 "MSS_MAIlBOX_MEM_INIT_DONE,"
bitfld.long 0x44 0. "mem0_done,This field will be high once intialization of MSS_MBOX is finished" "0,1"
line.long 0x48 "MSS_MAILBOX_MEM_INIT_STATUS,"
bitfld.long 0x48 0. "mem0_status," "0,1"
line.long 0x4C "MSS_RETRAM_MEM_INIT,"
bitfld.long 0x4C 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_RETRAM" "0,1"
line.long 0x50 "MSS_RETRAM_MEM_INIT_DONE,"
bitfld.long 0x50 0. "mem0_done,This field will be high once intialization of MSS_RETRAM is finished" "0,1"
line.long 0x54 "MSS_RETRAM_MEM_INIT_STATUS,"
bitfld.long 0x54 0. "mem0_status," "0,1"
line.long 0x58 "MSS_SPIA_MEM_INIT,"
bitfld.long 0x58 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_SPIA" "0,1"
line.long 0x5C "MSS_SPIA_MEM_INIT_DONE,"
bitfld.long 0x5C 0. "mem0_done,This field will be high once intialization of MSS_SPIA is finished" "0,1"
line.long 0x60 "MSS_SPIA_MEM_INIT_STATUS,"
bitfld.long 0x60 0. "mem0_status," "0,1"
line.long 0x64 "MSS_SPIB_MEM_INIT,"
bitfld.long 0x64 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_SPIB" "0,1"
line.long 0x68 "MSS_SPIB_MEM_INIT_DONE,"
bitfld.long 0x68 0. "mem0_done,This field will be high once intialization of MSS_SPIB is finished" "0,1"
line.long 0x6C "MSS_SPIB_MEM_INIT_STATUS,"
bitfld.long 0x6C 0. "mem0_status," "0,1"
line.long 0x70 "MSS_TPCC_MEMINIT_START,"
bitfld.long 0x70 16. "tpcc_b_meminit_start,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_TPCCB" "0,1"
newline
bitfld.long 0x70 0. "tpcc_a_meminit_start,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_TPCCA" "0,1"
line.long 0x74 "MSS_TPCC_MEMINIT_DONE,"
bitfld.long 0x74 16. "tpcc_b_meminit_done,This field will be high once intialization of MSS_TPCCB is finished" "0,1"
newline
bitfld.long 0x74 0. "tpcc_a_meminit_done,This field will be high once intialization of MSS_TPCCA is finished" "0,1"
line.long 0x78 "MSS_TPCC_MEMINIT_STATUS,"
bitfld.long 0x78 16. "tpcc_b_meminit_status," "0,1"
newline
bitfld.long 0x78 0. "tpcc_a_meminit_status," "0,1"
line.long 0x7C "MSS_GPADC_MEM_INIT,"
bitfld.long 0x7C 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_GPADC_DATA_MEM" "0,1"
line.long 0x80 "MSS_GPADC_MEM_INIT_DONE,"
bitfld.long 0x80 0. "mem0_done,This field will be high once intialization of MSS_GPADC_DATA_MEM is finished" "0,1"
line.long 0x84 "MSS_GPADC_MEM_INIT_STATUS,"
bitfld.long 0x84 0. "mem0_status," "0,1"
line.long 0x88 "MSS_SPIA_CFG,"
bitfld.long 0x88 24. "spia_int_trig_polarity,SPIA trigger source polarity select" "0,1"
newline
bitfld.long 0x88 16. "spia_trig_gate_en,When set the TRIGGER s are un-gated only when chip-select is active" "0,1"
newline
bitfld.long 0x88 8. "spia_cs_trigsrc_en,MIBSPIB CS Trigger SRC enable" "0,1"
newline
bitfld.long 0x88 0.--2. "spiasync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x8C "MSS_SPIB_CFG,"
bitfld.long 0x8C 24. "spib_int_trig_polarity,SPIB trigger source polarity select" "0,1"
newline
bitfld.long 0x8C 16. "spib_trig_gate_en,When set the TRIGGER s are un-gated only when chip-select is active" "0,1"
newline
bitfld.long 0x8C 8. "spib_cs_trigsrc_en,MIBSPIB CS Trigger SRC enable" "0,1"
newline
bitfld.long 0x8C 0.--2. "spibsync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x90 "MSS_EPWM_CFG,"
line.long 0x94 "MSS_GIO_CFG,"
line.long 0x98 "MSS_MCAN_FE_SELECT,"
bitfld.long 0x98 16.--18. "mcanb_fe_select,writing a value'N' would select Nth filter interrupt combination for hwa_cm4 interrupt and also HW_SYNC_IN Example: writing 3'd<1-7> selects MSS_MCANB_FE_INT<1-7> respectively" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x98 0.--2. "mcana_fe_select,writing a value'N' would select Nth filter interrupt combination for hwa_cm4 interrupt and also HW_SYNC_IN Example: writing 3'd<1-7> would select MSS_MCANA_FE_INT<1-7> respectively" "0,1,2,3,4,5,6,7"
line.long 0x9C "HW_SPARE_REG1,"
line.long 0xA0 "MSS_MCANA_INT_CLR,"
line.long 0xA4 "MSS_MCANA_INT_MASK,"
line.long 0xA8 "MSS_MCANA_INT_STAT,"
line.long 0xAC "HW_SPARE_REG2,"
line.long 0xB0 "CCC_ERR_STATUS,"
hexmask.long.byte 0xB0 16.--23. 1. "cccb_errot_status,CCCB Error Status (for Debug) {3'd0 counter_error counter_done timeout_error counter_error counter_done}"
newline
hexmask.long.byte 0xB0 0.--7. 1. "ccca_errot_status,CCCA Error Status (for Debug) {3'd0 counter_error counter_done timeout_error counter_error counter_done}"
line.long 0xB4 "CCCA_CFG0,"
hexmask.long.word 0xB4 16.--31. 1. "ccca_margin_count,Margin value for clock comparison in terms of counter1 clock.CCC error will not be generated if counter1 counter value is within count1_expected_val +/- MARGIN_COUNT"
newline
hexmask.long.byte 0xB4 9.--15. 1. "Reserved,Not used"
newline
bitfld.long 0xB4 8. "ccca_single_shot_mode," "0,1"
newline
bitfld.long 0xB4 7. "ccca_enable_module," "0,1"
newline
bitfld.long 0xB4 6. "ccca_disable_clocks," "0,1"
newline
bitfld.long 0xB4 3.--5. "ccca_clk1_sel,Selection for Clock 1" "Select clock0_src0 as source for counter1,Select clock0_src1 as source for counter1,Select clock0_src2 as source for counter1,?,?,?,?,Select clock0_src7 as source for counter1"
newline
bitfld.long 0xB4 0.--2. "ccca_clk0_sel,Selection for Clock 0" "Select clock0_src0 as source for counter0,Select clock0_src1 as source for counter0,Select clock0_src2 as source for counter0,?,?,?,?,Select clock0_src7 as source for counter0"
line.long 0xB8 "CCCA_CFG1,"
line.long 0xBC "CCCA_CFG2,"
line.long 0xC0 "CCCA_CFG3,"
line.long 0xC4 "CCCA_CNTVAL,"
line.long 0xC8 "CCCB_CFG0,"
hexmask.long.word 0xC8 16.--31. 1. "cccb_margin_count,Margin value for clock comparison in terms of counter1 clock.CCC error will not be generated if counter1 counter value is within count1_expected_val +/- MARGIN_COUNT"
newline
hexmask.long.byte 0xC8 9.--15. 1. "Reserved,Not used"
newline
bitfld.long 0xC8 8. "cccb_single_shot_mode," "0,1"
newline
bitfld.long 0xC8 7. "cccb_enable_module," "0,1"
newline
bitfld.long 0xC8 6. "cccb_disable_clocks," "0,1"
newline
bitfld.long 0xC8 3.--5. "CCCB_clk1_sel,Selection for Clock 1" "Select clock0_src0 as source for counter1,Select clock0_src1 as source for counter1,Select clock0_src2 as source for counter1,?,?,?,?,Select clock0_src7 as source for counter1"
newline
bitfld.long 0xC8 0.--2. "CCCB_clk0_sel,Selection for Clock 0" "Select clock0_src0 as source for counter0,Select clock0_src1 as source for counter0,Select clock0_src2 as source for counter0,?,?,?,?,Select clock0_src7 as source for counter0"
line.long 0xCC "CCCB_CFG1,"
line.long 0xD0 "CCCB_CFG2,"
line.long 0xD4 "CCCB_CFG3,"
line.long 0xD8 "CCCB_CNTVAL,"
line.long 0xDC "CCC_DCC_COMMON,"
bitfld.long 0xDC 12. "enable_cccb_err_nmi," "0,1"
newline
bitfld.long 0xDC 8. "enable_cccb_err_rstn," "0,1"
line.long 0xE0 "R5_GLOBAL_CONFIG,"
bitfld.long 0xE0 0. "teinit,Exception handling state at reset" "0,1"
line.long 0xE4 "R5_AHB_EN,"
bitfld.long 0xE4 16.--18. "cpu1_ahb_init,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE4 0.--2. "cpu0_ahb_init,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0xE8 "R5A_AHB_BASE,"
hexmask.long.tbyte 0xE8 0.--19. 1. "ahb_base,Ti internal Register"
line.long 0xEC "R5A_AHB_SIZE,"
bitfld.long 0xEC 0.--4. "ahb_size,Ti internal Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xF0 "R5B_AHB_BASE,"
hexmask.long.tbyte 0xF0 0.--19. 1. "ahb_base,Ti internal Register"
line.long 0xF4 "R5B_AHB_SIZE,"
bitfld.long 0xF4 0.--4. "ahb_size,Ti internal Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xF8 "R5_TCM_EXT_ERR_EN,"
bitfld.long 0xF8 16.--18. "cpu1_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 0.--2. "cpu0_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0xFC "R5_TCM_ERR_EN,"
bitfld.long 0xFC 16.--18. "cpu1_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xFC 0.--2. "cpu0_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0x100 "R5_INIT_TCM,"
bitfld.long 0x100 20.--22. "lockzram_cpu1,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 16.--18. "tcmb_cpu1,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 12.--14. "tcma_cpu1,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 8.--10. "lockzram_cpu0,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 4.--6. "tcmb_cpu0,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 0.--2. "tcma_cpu0,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0x104 "R5_TCM_ECC_WRENZ_EN,"
bitfld.long 0x104 20.--22. "cpu1_tcmb1_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x104 16.--18. "cpu1_tcmb0_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x104 12.--14. "cpu1_tcma_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x104 8.--10. "cpu0_tcmb1_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A" "0,1,2,3,4,5,6,7"
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bitfld.long 0x104 4.--6. "cpu0_tcmb0_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A" "0,1,2,3,4,5,6,7"
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bitfld.long 0x104 0.--2. "cpu0_tcma_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x108 "ESM_GATING0,"
line.long 0x10C "ESM_GATING1,"
line.long 0x110 "ESM_GATING2,"
line.long 0x114 "ESM_GATING3,"
line.long 0x118 "ESM_GATING4,"
line.long 0x11C "ESM_GATING5,"
line.long 0x120 "ESM_GATING6,"
line.long 0x124 "ESM_GATING7,"
line.long 0x128 "ERR_PARITY_ATCM0,"
hexmask.long.tbyte 0x128 0.--19. 1. "addr,Address lathched when parity error is occurred for ATCM of CR5A"
line.long 0x12C "ERR_PARITY_ATCM1,"
hexmask.long.tbyte 0x12C 0.--19. 1. "addr,Address lathched when parity error is occurred for ATCM of CR5B"
line.long 0x130 "ERR_PARITY_B0TCM0,"
hexmask.long.tbyte 0x130 0.--19. 1. "addr,Address lathched when parity error is occurred for B0TCM of CR5A"
line.long 0x134 "ERR_PARITY_B0TCM1,"
hexmask.long.tbyte 0x134 0.--19. 1. "addr,Address lathched when parity error is occurred for B0TCM of CR5B"
line.long 0x138 "ERR_PARITY_B1TCM0,"
hexmask.long.tbyte 0x138 0.--19. 1. "addr,Address lathched when parity error is occurred for B1TCM of CR5A"
line.long 0x13C "ERR_PARITY_B1TCM1,"
hexmask.long.tbyte 0x13C 0.--19. 1. "addr,Address lathched when parity error is occurred for B1TCM of CR5B"
line.long 0x140 "TCM_PARITY_CTRL,"
bitfld.long 0x140 20.--22. "b1tcm1_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 16.--18. "b1tcm0_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 12.--14. "b0cm1_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 8.--10. "b0tcm0_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 4.--6. "atcm1_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 0.--2. "atcm0_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x144 "TCM_PARITY_ERRFRC,"
bitfld.long 0x144 20.--22. "b1tcm1,Pulse bit-field writing 3'b111 forces a parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 16.--18. "b1tcm0,Pulse bit-field writing 3'b111 forces a parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 12.--14. "b0tcm1,Pulse bit-field writing 3'b111 forces a parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x144 8.--10. "b0tcm0,Pulse bit-field writing 3'b111 forces a parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7"
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bitfld.long 0x144 4.--6. "atcm1,Pulse bit-field writing 3'b111 forces a parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7"
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bitfld.long 0x144 0.--2. "atcm0,Pulse bit-field writing 3'b111 forces a parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x148 "HW_SPARE_REG3,"
line.long 0x14C "SPIA_IO_CFG,"
bitfld.long 0x14C 16.--18. "miso_oen_by_cs,MIBSPIA MISO OE_N Control based on Chip selectCS-applicable in slave mode" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
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bitfld.long 0x14C 8.--10. "cs_pol,MIBSPIA CS polarity-slave mode" "Active low,Active high,?..."
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bitfld.long 0x14C 0.--2. "cs_deact," "0,1,2,3,4,5,6,7"
line.long 0x150 "SPIB_IO_CFG,"
bitfld.long 0x150 16.--18. "miso_oen_by_cs,MIBSPIB MISO OE_N Control based on Chip selectCS-applicable in slave mode" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
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bitfld.long 0x150 8.--10. "cs_pol,MIBSPIB CS polarity-slave mode" "Active low,Active high,?..."
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bitfld.long 0x150 0.--2. "cs_deact," "0,1,2,3,4,5,6,7"
line.long 0x154 "SPI_HOST_IRQ,"
bitfld.long 0x154 0.--2. "host_irq,HOST IRQ" "0,1,2,3,4,5,6,7"
line.long 0x158 "TPTC_DBS_CONFIG,"
bitfld.long 0x158 8.--9. "tptc_b0,Default burst size tieoff value for TPTC_B0" "0,1,2,3"
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bitfld.long 0x158 4.--5. "tptc_a1,Default burst size tieoff value for TPTC_A1" "0,1,2,3"
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bitfld.long 0x158 0.--1. "tptc_a0,Default burst size tieoff value for TPTC_A0" "0,1,2,3"
line.long 0x15C "TPCC_PARITY_CTRL,"
bitfld.long 0x15C 20. "tpcc_b_parity_err_clr,parity clear bit" "0,1"
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bitfld.long 0x15C 16. "tpcc_a_parity_err_clr,parity clear bit" "0,1"
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bitfld.long 0x15C 12. "tpcc_b_parity_testen,parity test enable for tpcc b" "0,1"
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bitfld.long 0x15C 8. "tpcc_b_parity_en,parity en for tpcc b" "0,1"
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bitfld.long 0x15C 4. "tpcc_a_parity_testen,parity test enable for tpcc a" "0,1"
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bitfld.long 0x15C 0. "tpcc_a_parity_en,writing 1'b1 enables parity for TPCC_A" "0,1"
line.long 0x160 "TPCC_PARITY_STATUS,"
hexmask.long.byte 0x160 16.--23. 1. "tpcc_b_parity_addr,address where parity error happened for tpccb"
newline
hexmask.long.byte 0x160 0.--7. 1. "tpcc_a_parity_addr,address where parity error happened for tpcca"
line.long 0x164 "MSS_DBG_ACK_CTL0,"
bitfld.long 0x164 24.--26. "cpsw,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x164 20.--22. "dccd,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x164 16.--18. "dccc,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x164 12.--14. "dccb,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 8.--10. "dcca,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 4.--6. "cccb,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 0.--2. "ccca,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x168 "MSS_DBG_ACK_CTL1,"
bitfld.long 0x168 24.--26. "scib,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 20.--22. "scia,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x168 16.--18. "i2c,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 12.--14. "mcrc,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 8.--10. "wdt,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x168 4.--6. "rti,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 0.--2. "dcan,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x16C "CPSW_CONTROL,"
bitfld.long 0x16C 16. "rgmii1_id_mode,writing 1'b1 would disable the internal clock delays" "0,1"
newline
bitfld.long 0x16C 8. "rmii_ref_clk_oe_n,To select the rmii_ref_clk from PAD or from MSS_RCM" "clock will be from mss_rcm through..,will be from"
newline
bitfld.long 0x16C 0.--2. "port1_mode_sel,Port 1 Interface" "GMII/MII,RMII,RGMII,Not Supported,?..."
line.long 0x170 "MSS_TPCC_A_ERRAGG_MASK,"
bitfld.long 0x170 26. "tptc_a1_read_access_error,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
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bitfld.long 0x170 25. "tptc_a0_read_access_error,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
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bitfld.long 0x170 24. "tpcc_a_read_access_error,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
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bitfld.long 0x170 18. "tptc_a1_write_access_error,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 17. "tptc_a0_write_access_error,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 16. "tpcc_a_write_access_error,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 4. "tpcc_a_par_err,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
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bitfld.long 0x170 3. "tptc_a1_err,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 2. "tptc_a0_err,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 1. "tpcc_a_mpint,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
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bitfld.long 0x170 0. "tpcc_a_errint,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x174 "MSS_TPCC_A_ERRAGG_STATUS,"
bitfld.long 0x174 26. "tptc_a1_read_access_error,Status of Error from MSS_TPTC_A1" "0,1"
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bitfld.long 0x174 25. "tptc_a0_read_access_error,Status of Error from MSS_TPTC_A0" "0,1"
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bitfld.long 0x174 24. "tpcc_a_read_access_error,Status of Error from MSS_TPCC_A" "0,1"
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bitfld.long 0x174 18. "tptc_a1_write_access_error,Status of Error from MSS_TPTC_A1" "0,1"
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bitfld.long 0x174 17. "tptc_a0_write_access_error,Status of Error from MSS_TPTC_A0" "0,1"
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bitfld.long 0x174 16. "tpcc_a_write_access_error,Status of Error from MSS_TPCC_A" "0,1"
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bitfld.long 0x174 4. "tpcc_a_par_err,Status of Error from MSS_TPCC_A" "0,1"
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bitfld.long 0x174 3. "tptc_a1_err,Status of Error from MSS_TPTC_A1" "0,1"
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bitfld.long 0x174 2. "tptc_a0_err,Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x174 1. "tpcc_a_mpint,Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x174 0. "tpcc_a_errint,Status of Error from MSS_TPCC_A" "0,1"
line.long 0x178 "MSS_TPCC_A_ERRAGG_STATUS_RAW,"
bitfld.long 0x178 26. "tptc_a1_read_access_error,Raw Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x178 25. "tptc_a0_read_access_error,Raw Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x178 24. "tpcc_a_read_access_error,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 18. "tptc_a1_write_access_error,Raw Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x178 17. "tptc_a0_write_access_error,Raw Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x178 16. "tpcc_a_write_access_error,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 4. "tpcc_a_par_err,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 3. "tptc_a1_err,Raw Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x178 2. "tptc_a0_err,Raw Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x178 1. "tpcc_a_mpint,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 0. "tpcc_a_errint,Raw Status of Error from MSS_TPCC_A" "0,1"
line.long 0x17C "MSS_TPCC_A_INTAGG_MASK,"
bitfld.long 0x17C 17. "tptc_a1,Mask Interrupt from TPTC A1 to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 16. "tptc_a0,Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 8. "tpcc_a_int7,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 7. "tpcc_a_int6,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 6. "tpcc_a_int5,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 5. "tpcc_a_int4,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 4. "tpcc_a_int3,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 3. "tpcc_a_int2,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 2. "tpcc_a_int1,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 1. "tpcc_a_int0,Mask Interrupt from TPCC A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 0. "tpcc_a_intg,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x180 "MSS_TPCC_A_INTAGG_STATUS,"
bitfld.long 0x180 17. "tptc_a1,Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x180 16. "tptc_a0,Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x180 8. "tpcc_a_int7,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 7. "tpcc_a_int6,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 6. "tpcc_a_int5,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 5. "tpcc_a_int4,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 4. "tpcc_a_int3,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 3. "tpcc_a_int2,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 2. "tpcc_a_int1,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 1. "tpcc_a_int0,Status of Interrupt from TPCC A Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x180 0. "tpcc_a_intg,Status of Interrupt from MSS_TPCC_A" "0,1"
line.long 0x184 "MSS_TPCC_A_INTAGG_STATUS_RAW,"
bitfld.long 0x184 17. "tptc_a1,Raw Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x184 16. "tptc_a0,Raw Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x184 8. "tpcc_a_int7,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 7. "tpcc_a_int6,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 6. "tpcc_a_int5,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 5. "tpcc_a_int4,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 4. "tpcc_a_int3,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 3. "tpcc_a_int2,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 2. "tpcc_a_int1,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 1. "tpcc_a_int0,Raw Status of Interrupt from TPCC A" "0,1"
newline
bitfld.long 0x184 0. "tpcc_a_intg,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
line.long 0x188 "MSS_TPCC_B_ERRAGG_MASK,"
bitfld.long 0x188 25. "tptc_b0_read_access_error,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 24. "tpcc_b_read_access_error,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 17. "tptc_b0_write_access_error,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 16. "tpcc_b_write_access_error,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 4. "tpcc_b_par_err,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 2. "tptc_b0_err,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 1. "tpcc_b_mpint,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 0. "tpcc_b_errint,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x18C "MSS_TPCC_B_ERRAGG_STATUS,"
bitfld.long 0x18C 25. "tptc_b0_read_access_error,Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x18C 24. "tpcc_b_read_access_error,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 17. "tptc_b0_write_access_error,Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x18C 16. "tpcc_b_write_access_error,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 4. "tpcc_b_par_err,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 2. "tptc_b0_err,Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x18C 1. "tpcc_b_mpint,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 0. "tpcc_b_errint,Status of Error from MSS_TPCC_B" "0,1"
line.long 0x190 "MSS_TPCC_B_ERRAGG_STATUS_RAW,"
bitfld.long 0x190 25. "tptc_b0_read_access_error,Raw Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x190 24. "tpcc_b_read_access_error,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 17. "tptc_b0_write_access_error,Raw Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x190 16. "tpcc_b_write_access_error,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 4. "tpcc_b_par_err,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 2. "tptc_b0_err,Raw Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x190 1. "tpcc_b_mpint,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 0. "tpcc_b_errint,Raw Status of Error from MSS_TPCC_B" "0,1"
line.long 0x194 "MSS_TPCC_B_INTAGG_MASK,"
bitfld.long 0x194 16. "tptc_b0,Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 8. "tpcc_b_int7,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 7. "tpcc_b_int6,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 6. "tpcc_b_int5,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 5. "tpcc_b_int4,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 4. "tpcc_b_int3,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 3. "tpcc_b_int2,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 2. "tpcc_b_int1,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 1. "tpcc_b_int0,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 0. "tpcc_b_intg,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x198 "MSS_TPCC_B_INTAGG_STATUS,"
bitfld.long 0x198 16. "tptc_b0,Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x198 8. "tpcc_b_int7,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 7. "tpcc_b_int6,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 6. "tpcc_b_int5,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 5. "tpcc_b_int4,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 4. "tpcc_b_int3,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 3. "tpcc_b_int2,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 2. "tpcc_b_int1,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 1. "tpcc_b_int0,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 0. "tpcc_b_intg,Status of Interrupt from MSS_TPCC_B" "0,1"
line.long 0x19C "MSS_TPCC_B_INTAGG_STATUS_RAW,"
bitfld.long 0x19C 16. "tptc_b0,Raw Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x19C 8. "tpcc_b_int7,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 7. "tpcc_b_int6,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 6. "tpcc_b_int5,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 5. "tpcc_b_int4,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 4. "tpcc_b_int3,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 3. "tpcc_b_int2,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 2. "tpcc_b_int1,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 1. "tpcc_b_int0,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 0. "tpcc_b_intg,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
line.long 0x1A0 "MSS_BUS_SAFETY_CTRL,"
bitfld.long 0x1A0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1A4 "MSS_CR5A_AXI_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1A4 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A4 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "MSS_CR5A_AXI_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x1A8 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A8 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1AC "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1AC 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B0 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1B0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B4 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1B8 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1BC "MSS_CR5B_AXI_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1BC 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1BC 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1BC 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "MSS_CR5B_AXI_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x1C0 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C0 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C0 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C0 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1C4 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1C4 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1C8 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1C8 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1CC "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1D0 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1D4 "MSS_CR5A_AXI_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1D4 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1D4 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D4 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1D8 "MSS_CR5A_AXI_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1D8 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D8 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D8 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1D8 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1DC "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1DC 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1DC 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1DC 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1DC 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1E0 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1E0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1E4 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1E8 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1EC "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1F0 "MSS_CR5B_AXI_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1F0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1F0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1F4 "MSS_CR5B_AXI_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1F4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1F4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1F8 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1F8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1FC "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1FC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1FC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x200 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x204 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x208 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x20C "MSS_CR5A_AXI_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x20C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x20C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x20C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x210 "MSS_CR5A_AXI_S_BUS_SAFETY_FI,"
hexmask.long.byte 0x210 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x210 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x210 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x210 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x214 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0x214 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x214 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x214 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x214 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x218 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x218 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x218 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x21C "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x220 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x224 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x228 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x22C "MSS_CR5B_AXI_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x22C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x22C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x22C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x230 "MSS_CR5B_AXI_S_BUS_SAFETY_FI,"
hexmask.long.byte 0x230 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x230 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x230 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x230 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x234 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0x234 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x234 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x234 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x234 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x238 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x238 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x238 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x23C "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x240 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x244 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x248 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x24C "MSS_TPTC_A0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x24C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x24C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x250 "MSS_TPTC_A0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x250 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x250 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x250 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x250 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x254 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x254 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x254 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x254 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x254 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x258 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x258 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x258 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x25C "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x260 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x264 "MSS_TPTC_A1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x264 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x264 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x264 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x268 "MSS_TPTC_A1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x268 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x268 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x268 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x268 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x26C "MSS_TPTC_A1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x26C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x26C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x26C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x26C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x270 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x270 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x270 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x274 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x278 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x27C "MSS_TPTC_B0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x27C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x27C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x27C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x280 "MSS_TPTC_B0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x280 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x280 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x280 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x280 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x284 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x284 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x284 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x284 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x284 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x288 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x288 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x288 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x28C "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x290 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x294 "MSS_TPTC_A0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x294 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x294 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x294 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x298 "MSS_TPTC_A0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x298 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x298 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x298 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x298 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x29C "MSS_TPTC_A0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x29C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x29C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x29C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x29C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2A0 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2A0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2A0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2A4 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2A8 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x2AC "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x2B0 "MSS_TPTC_A1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x2B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x2B4 "MSS_TPTC_A1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x2B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x2B8 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x2B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2BC "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2BC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2BC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2C0 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2C4 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x2C8 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x2CC "MSS_TPTC_B0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x2CC 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2CC 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2CC 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x2D0 "MSS_TPTC_B0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x2D0 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D0 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D0 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2D0 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x2D4 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x2D4 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D4 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D4 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D4 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2D8 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2D8 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D8 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2DC "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2E0 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x2E4 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x2E8 "HSM_TPTC_A0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x2E8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2E8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2E8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x2EC "HSM_TPTC_A0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x2EC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2EC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2EC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2EC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x2F0 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x2F0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2F4 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2F4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2F8 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2FC "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x300 "HSM_TPTC_A1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x300 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x300 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x300 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x304 "HSM_TPTC_A1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x304 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x304 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x304 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x304 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x308 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x308 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x308 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x308 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x308 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x30C "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x30C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x30C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x310 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x314 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x318 "HSM_TPTC_A0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x318 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x318 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x318 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x31C "HSM_TPTC_A0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x31C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x31C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x31C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x31C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x320 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x320 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x320 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x320 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x320 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x324 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x324 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x324 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x328 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x32C "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x330 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x334 "HSM_TPTC_A1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x334 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x334 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x334 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x338 "HSM_TPTC_A1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x338 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x338 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x338 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x338 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x33C "HSM_TPTC_A1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x33C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x33C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x33C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x33C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x340 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x340 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x340 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x344 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x348 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x34C "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x350 "MSS_QSPI_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x350 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x350 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x350 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x354 "MSS_QSPI_BUS_SAFETY_FI,"
hexmask.long.byte 0x354 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x354 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x354 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x354 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x358 "MSS_QSPI_BUS_SAFETY_ERR,"
hexmask.long.byte 0x358 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x358 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x358 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x358 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x35C "MSS_QSPI_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x35C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x35C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x360 "MSS_QSPI_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x364 "MSS_QSPI_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x368 "MSS_QSPI_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x36C "MSS_QSPI_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x370 "HSM_DTHE_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x370 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x370 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x370 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x374 "HSM_DTHE_BUS_SAFETY_FI,"
hexmask.long.byte 0x374 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x374 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x374 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x374 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x378 "HSM_DTHE_BUS_SAFETY_ERR,"
hexmask.long.byte 0x378 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x378 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x378 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x378 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x37C "HSM_DTHE_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x37C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x37C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x380 "HSM_DTHE_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x384 "HSM_DTHE_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x388 "HSM_DTHE_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x38C "HSM_DTHE_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x390 "MSS_CPSW_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x390 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x390 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x390 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x394 "MSS_CPSW_BUS_SAFETY_FI,"
hexmask.long.byte 0x394 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x394 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x394 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x394 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x398 "MSS_CPSW_BUS_SAFETY_ERR,"
hexmask.long.byte 0x398 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x398 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x398 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x398 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x39C "MSS_CPSW_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x39C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x39C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3A0 "MSS_CPSW_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x3A4 "MSS_CPSW_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x3A8 "MSS_CPSW_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3AC "MSS_CPSW_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x3B0 "MSS_MCRC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x3B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x3B4 "MSS_MCRC_BUS_SAFETY_FI,"
hexmask.long.byte 0x3B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x3B8 "MSS_MCRC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x3B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3BC "MSS_MCRC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3BC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3BC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3C0 "MSS_MCRC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x3C4 "MSS_MCRC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x3C8 "MSS_MCRC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3CC "MSS_MCRC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x3D0 "MSS_PCR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x3D0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3D0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x3D4 "MSS_PCR_BUS_SAFETY_FI,"
hexmask.long.byte 0x3D4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3D4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x3D8 "MSS_PCR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x3D8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3DC "MSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3DC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3DC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3E0 "MSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x3E4 "MSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x3E8 "MSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3EC "MSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x3F0 "MSS_PCR2_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x3F0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3F0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x3F4 "MSS_PCR2_BUS_SAFETY_FI,"
hexmask.long.byte 0x3F4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3F4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x3F8 "MSS_PCR2_BUS_SAFETY_ERR,"
hexmask.long.byte 0x3F8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3FC "MSS_PCR2_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3FC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3FC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x400 "MSS_PCR2_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x404 "MSS_PCR2_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x408 "MSS_PCR2_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x40C "MSS_PCR2_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x410 "HSM_M_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x410 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x410 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x410 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x414 "HSM_M_BUS_SAFETY_FI,"
hexmask.long.byte 0x414 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x414 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x414 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x414 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x418 "HSM_M_BUS_SAFETY_ERR,"
hexmask.long.byte 0x418 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x418 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x418 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x418 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x41C "HSM_M_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x41C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x41C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x420 "HSM_M_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x424 "HSM_M_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x428 "HSM_M_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x42C "HSM_M_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x430 "HSM_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x430 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x430 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x430 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x434 "HSM_S_BUS_SAFETY_FI,"
hexmask.long.byte 0x434 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x434 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x434 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x434 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x438 "HSM_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0x438 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x438 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x438 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x438 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x43C "HSM_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x43C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x43C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x440 "HSM_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x444 "HSM_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x448 "HSM_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x44C "HSM_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x450 "DAP_R232_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x450 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x450 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x450 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x454 "DAP_R232_BUS_SAFETY_FI,"
hexmask.long.byte 0x454 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x454 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x454 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x454 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x458 "DAP_R232_BUS_SAFETY_ERR,"
hexmask.long.byte 0x458 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x458 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x458 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x458 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x45C "DAP_R232_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x45C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x45C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x460 "DAP_R232_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x464 "DAP_R232_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x468 "DAP_R232_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x46C "DAP_R232_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x470 "MSS_L2_A_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x470 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x470 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x470 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x474 "MSS_L2_A_BUS_SAFETY_FI,"
hexmask.long.byte 0x474 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x474 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x474 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x474 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x478 "MSS_L2_A_BUS_SAFETY_ERR,"
hexmask.long.byte 0x478 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x478 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x478 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x478 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x47C "MSS_L2_A_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x47C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x47C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x480 "MSS_L2_A_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x484 "MSS_L2_A_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x488 "MSS_L2_A_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x48C "MSS_L2_A_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x490 "MSS_L2_B_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x490 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x490 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x490 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x494 "MSS_L2_B_BUS_SAFETY_FI,"
hexmask.long.byte 0x494 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x494 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x494 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x494 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x498 "MSS_L2_B_BUS_SAFETY_ERR,"
hexmask.long.byte 0x498 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x498 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x498 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x498 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x49C "MSS_L2_B_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x49C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x49C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4A0 "MSS_L2_B_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x4A4 "MSS_L2_B_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x4A8 "MSS_L2_B_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x4AC "MSS_L2_B_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x4B0 "MSS_MBOX_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x4B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4B4 "MSS_MBOX_BUS_SAFETY_FI,"
hexmask.long.byte 0x4B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x4B8 "MSS_MBOX_BUS_SAFETY_ERR,"
hexmask.long.byte 0x4B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4BC "MSS_MBOX_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4BC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4BC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4C0 "MSS_MBOX_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x4C4 "MSS_MBOX_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x4C8 "MSS_MBOX_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x4CC "MSS_MBOX_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x4D0 "MSS_SWBUF_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x4D0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4D0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4D4 "MSS_SWBUF_BUS_SAFETY_FI,"
hexmask.long.byte 0x4D4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4D4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x4D8 "MSS_SWBUF_BUS_SAFETY_ERR,"
hexmask.long.byte 0x4D8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4DC "MSS_SWBUF_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4DC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4DC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4E0 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x4E4 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x4E8 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x4EC "MSS_SWBUF_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x4F0 "MSS_GPADC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x4F0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4F0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4F4 "MSS_GPADC_BUS_SAFETY_FI,"
hexmask.long.byte 0x4F4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4F4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x4F8 "MSS_GPADC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x4F8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4FC "MSS_GPADC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4FC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4FC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x500 "MSS_GPADC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x504 "MSS_GPADC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x508 "MSS_GPADC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x50C "MSS_GPADC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x510 "MSS_BUS_SAFETY_SEC_ERR_STAT0,"
bitfld.long 0x510 31. "mss_dmmslv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 30. "mss_dmm,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 29. "gpadc,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 28. "mss_swbuf,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 27. "mss_mbox,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 26. "l2ram1,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 25. "l2ram0,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 24. "dthe,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 23. "hsm_s,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 22. "per_pcr2,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 21. "per_pcr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 20. "mcrc,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 19. "qspi,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 18. "hsm_tptc_A1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 17. "hsm_tptc_A1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 16. "hsm_tptc_A0_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 15. "hsm_tptc_A0_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 14. "mss_tptc_B1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 13. "mss_tptc_A1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 12. "mss_tptc_A0_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 11. "mss_tptc_B1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 10. "mss_tptc_A1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 9. "mss_tptc_A0_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 8. "cpsw,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 7. "hsm,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 6. "dap_rs232,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 5. "cr5b_slv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 4. "cr5a_slv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 3. "cr5b_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 2. "cr5a_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 1. "cr5b_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 0. "cr5a_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
line.long 0x514 "MSS_BUS_SAFETY_SEC_ERR_STAT1,"
bitfld.long 0x514 24. "mss_to_mdo,Bus safety single-bit-error of Node mentioned in the field" "0,1"
group.long 0x520++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x538++0xDF
line.long 0x00 "MSS_DMM_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x00 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x00 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x00 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x04 "MSS_DMM_BUS_SAFETY_FI,"
hexmask.long.byte 0x04 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x04 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x08 "MSS_DMM_BUS_SAFETY_ERR,"
hexmask.long.byte 0x08 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x0C "MSS_DMM_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x0C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x10 "MSS_DMM_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x14 "MSS_DMM_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x18 "MSS_DMM_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1C "MSS_DMM_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x20 "MSS_DMM_SLV_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x20 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x20 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x20 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x24 "MSS_DMM_SLV_BUS_SAFETY_FI,"
hexmask.long.byte 0x24 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x24 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x28 "MSS_DMM_SLV_BUS_SAFETY_ERR,"
hexmask.long.byte 0x28 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2C "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x30 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x34 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x38 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3C "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x40 "MSS_TO_MDO_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x40 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x40 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x40 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x44 "MSS_TO_MDO_BUS_SAFETY_FI,"
hexmask.long.byte 0x44 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x44 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x48 "MSS_TO_MDO_BUS_SAFETY_ERR,"
hexmask.long.byte 0x48 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4C "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x50 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x54 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x58 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x5C "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x60 "MSS_SCRP_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x60 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x60 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x60 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x64 "MSS_SCRP_BUS_SAFETY_FI,"
hexmask.long.byte 0x64 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x64 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x68 "MSS_SCRP_BUS_SAFETY_ERR,"
hexmask.long.byte 0x68 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x6C "MSS_SCRP_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x6C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x70 "MSS_SCRP_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x74 "MSS_SCRP_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x78 "MSS_SCRP_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x7C "MSS_SCRP_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x80 "MSS_CR5A_AHB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x80 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x80 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x80 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x84 "MSS_CR5A_AHB_BUS_SAFETY_FI,"
hexmask.long.byte 0x84 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x84 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x88 "MSS_CR5A_AHB_BUS_SAFETY_ERR,"
hexmask.long.byte 0x88 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x8C "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x8C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x90 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x94 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x98 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x9C "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xA0 "MSS_CR5B_AHB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xA0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xA4 "MSS_CR5B_AHB_BUS_SAFETY_FI,"
hexmask.long.byte 0xA4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xA8 "MSS_CR5B_AHB_BUS_SAFETY_ERR,"
hexmask.long.byte 0xA8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xAC "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xAC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB0 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xB4 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0xB8 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xBC "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xC0 "DMM_CTRL_REG,"
bitfld.long 0xC0 0. "dmm_pad_select," "0,1"
line.long 0xC4 "MSS_CR5A_MBOX_WRITE_DONE,"
bitfld.long 0xC4 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
newline
bitfld.long 0xC4 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
newline
bitfld.long 0xC4 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
newline
bitfld.long 0xC4 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
newline
bitfld.long 0xC4 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
newline
bitfld.long 0xC4 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
newline
bitfld.long 0xC4 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
newline
bitfld.long 0xC4 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0xC8 "MSS_CR5A_MBOX_READ_REQ,"
bitfld.long 0xC8 28. "proc_7,This is request from processor 7 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 24. "proc_6,This is request from processor 6 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 20. "proc_5,This is request from processor 5 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 16. "proc_4,This is request from processor 4 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 12. "proc_3,This is request from processor 3 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 8. "proc_2,This is request from processor 2 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 4. "proc_1,This is request from processor 1 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 0. "proc_0,This is request from processor 0 to mss_cr5a" "0,1"
line.long 0xCC "MSS_CR5A_MBOX_READ_DONE,"
bitfld.long 0xCC 28. "proc_7,This register should be written once finishing reading from CR5A's mailbox written by proc 7" "0,1"
newline
bitfld.long 0xCC 24. "proc_6,This register should be written once finishing reading from CR5A's mailbox written by proc 6" "0,1"
newline
bitfld.long 0xCC 20. "proc_5,This register should be written once finishing reading from CR5A's mailbox written by proc 5" "0,1"
newline
bitfld.long 0xCC 16. "proc_4,This register should be written once finishing reading from CR5A's mailbox written by proc 4" "0,1"
newline
bitfld.long 0xCC 12. "proc_3,This register should be written once finishing reading from CR5A's mailbox written by proc 3" "0,1"
newline
bitfld.long 0xCC 8. "proc_2,This register should be written once finishing reading from CR5A's mailbox written by proc 2" "0,1"
newline
bitfld.long 0xCC 4. "proc_1,This register should be written once finishing reading from CR5A's mailbox written by proc 1" "0,1"
newline
bitfld.long 0xCC 0. "proc_0,This register should be written once finishing reading from CR5A's mailbox written by proc 0" "0,1"
line.long 0xD0 "MSS_CR5B_MBOX_WRITE_DONE,"
bitfld.long 0xD0 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
newline
bitfld.long 0xD0 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
newline
bitfld.long 0xD0 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
newline
bitfld.long 0xD0 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
newline
bitfld.long 0xD0 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
newline
bitfld.long 0xD0 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
newline
bitfld.long 0xD0 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
newline
bitfld.long 0xD0 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0xD4 "MSS_CR5B_MBOX_READ_REQ,"
bitfld.long 0xD4 28. "proc_7,This is request from processor 7 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 24. "proc_6,This is request from processor 6 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 20. "proc_5,This is request from processor 5 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 16. "proc_4,This is request from processor 4 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 12. "proc_3,This is request from processor 3 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 8. "proc_2,This is request from processor 2 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 4. "proc_1,This is request from processor 1 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 0. "proc_0,This is request from processor 0 to mss_CR5B" "0,1"
line.long 0xD8 "MSS_CR5B_MBOX_READ_DONE,"
bitfld.long 0xD8 28. "proc_7,This register should be written once finishing reading from CR5B's mailbox written by proc 7" "0,1"
newline
bitfld.long 0xD8 24. "proc_6,This register should be written once finishing reading from CR5B's mailbox written by proc 6" "0,1"
newline
bitfld.long 0xD8 20. "proc_5,This register should be written once finishing reading from CR5B's mailbox written by proc 5" "0,1"
newline
bitfld.long 0xD8 16. "proc_4,This register should be written once finishing reading from CR5B's mailbox written by proc 4" "0,1"
newline
bitfld.long 0xD8 12. "proc_3,This register should be written once finishing reading from CR5B's mailbox written by proc 3" "0,1"
newline
bitfld.long 0xD8 8. "proc_2,This register should be written once finishing reading from CR5B's mailbox written by proc 2" "0,1"
newline
bitfld.long 0xD8 4. "proc_1,This register should be written once finishing reading from CR5B's mailbox written by proc 1" "0,1"
newline
bitfld.long 0xD8 0. "proc_0,This register should be written once finishing reading from CR5B's mailbox written by proc 0" "0,1"
line.long 0xDC "MSS_PBIST_KEY_RST,"
bitfld.long 0xDC 4.--7. "pbist_st_rst,MSS PBIST controller will be brought out of reset when value is 0xA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0xDC 0.--3. "pbist_st_key,Top PBIST Selftest Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x624++0x0F
line.long 0x00 "MSS_QSPI_CONFIG,"
bitfld.long 0x00 8.--10. "clk_loopback,Write 3'b111 to take board level loop back clock for QSPI" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "ext_clk,Write 3'b111 to external clock as QSPI baud clock source needed for DFT IO char" "0,1,2,3,4,5,6,7"
line.long 0x04 "MSS_STC_CONTROL,"
bitfld.long 0x04 0.--2. "cr5_wfi_overide,writing 3'b111 will bypass the wfi signals from R5SS" "0,1,2,3,4,5,6,7"
line.long 0x08 "MSS_CTI_TRIG_SEL,"
hexmask.long.byte 0x08 0.--7. 1. "trig8_sel,Used for selecting the trigger source for 8th trigger of MSS_CTI"
line.long 0x0C "MSS_DBGSS_CTI_TRIG_SEL,"
hexmask.long.byte 0x0C 16.--23. 1. "trig3,Used for selecting the trigger source for 3rd trigger of ONE_MCU_CTI"
newline
hexmask.long.byte 0x0C 8.--15. 1. "trig2,Used for selecting the trigger source for 2nd trigger of ONE_MCU_CTI"
newline
hexmask.long.byte 0x0C 0.--7. 1. "trig1,Used for selecting the trigger source for 1st trigger of ONE_MCU_CTI"
group.long 0x654++0x8B
line.long 0x00 "MSS_TPTC_ECCAGGR_CLK_CNTRL,"
bitfld.long 0x00 2. "tptc_B0,Writing '0' will gate the clock to TPTC_B0-FIFO during ECC-AGGR interaction(fault injection)" "0,1"
newline
bitfld.long 0x00 1. "tptc_A1,Writing '0' will gate the clock to TPTC_A1-FIFO during ECC-AGGR interaction(fault injection)" "0,1"
newline
bitfld.long 0x00 0. "tptc_A0,Writing '0' will gate the clock to TPTC_A0-FIFO during ECC-AGGR interaction(fault injection)" "0,1"
line.long 0x04 "MSS_PERIPH_ERRAGG_MASK0,"
bitfld.long 0x04 27. "top_mdo_wr,Mask Interrupt from TOP_MDO to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 26. "top_mdo_rd,Mask Interrupt from TOP_MDO to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 25. "rcss_rcm_wr,Mask Interrupt from RCSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 24. "rcss_rcm_rd,Mask Interrupt from RCSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 23. "rcss_ctrl_wr,Mask Interrupt from RCSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 22. "rcss_ctrl_rd,Mask Interrupt from RCSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 21. "hwa_cfg_wr,Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 20. "hwa_cfg_rd,Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 19. "dss_cm4_ctrl_wr,Mask Interrupt from DSS_CM4_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 18. "dss_cm4_ctrl_rd,Mask Interrupt from DSS_CM4_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 17. "dss_rcm_wr,Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 16. "dss_rcm_rd,Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 15. "dss_ctrl_wr,Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 14. "dss_ctrl_rd,Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 13. "hsm_ctrl_wr,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 12. "hsm_ctrl_rd,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 11. "hsm_soc_ctrl_wr,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 10. "hsm_soc_ctrl_rd,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 9. "top_aurora_wr,Mask Interrupt from TOP_AURORA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 8. "top_aurora_rd,Mask Interrupt from TOP_AURORA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 7. "top_rcm_wr,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 6. "top_rcm_rd,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 5. "top_ctrl_wr,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 4. "top_ctrl_rd,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 3. "mss_rcm_wr,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 2. "mss_rcm_rd,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 1. "mss_ctrl_wr,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 0. "mss_ctrl_rd,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x08 "MSS_PERIPH_ERRAGG_STATUS0,"
bitfld.long 0x08 27. "top_mdo_wr,Status of Interrupt from TOP_MDO Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 26. "top_mdo_rd,Status of Interrupt from TOP_MDO Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 25. "rcss_rcm_wr,Status of Interrupt from RCSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 24. "rcss_rcm_rd,Status of Interrupt from RCSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 23. "rcss_ctrl_wr,Status of Interrupt from RCSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 22. "rcss_ctrl_rd,Status of Interrupt from RCSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 21. "hwa_cfg_wr,Status of Interrupt from HWA_CFG Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 20. "hwa_cfg_rd,Status of Interrupt from HWA_CFG Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 19. "dss_cm4_ctrl_wr,Status of Interrupt from DSS_CM4_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 18. "dss_cm4_ctrl_rd,Status of Interrupt from DSS_CM4_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 17. "dss_rcm_wr,Status of Interrupt from DSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 16. "dss_rcm_rd,Status of Interrupt from DSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 15. "dss_ctrl_wr,Status of Interrupt from DSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 14. "dss_ctrl_rd,Status of Interrupt from DSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 13. "hsm_ctrl_wr,Status of Interrupt from HSM_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 12. "hsm_ctrl_rd,Status of Interrupt from HSM_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 11. "hsm_soc_ctrl_wr,Status of Interrupt from HSM_SOC_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 10. "hsm_soc_ctrl_rd,Status of Interrupt from HSM_SOC_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 9. "top_aurora_wr,Status of Interrupt from TOP_AURORA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 8. "top_aurora_rd,Status of Interrupt from TOP_AURORA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 7. "top_rcm_wr,Status of Interrupt from TOP_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 6. "top_rcm_rd,Status of Interrupt from TOP_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 5. "top_ctrl_wr,Status of Interrupt from TOP_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 4. "top_ctrl_rd,Status of Interrupt from TOP_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 3. "mss_rcm_wr,Status of Interrupt from MSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 2. "mss_rcm_rd,Status of Interrupt from MSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 1. "mss_ctrl_wr,Status of Interrupt from MSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x08 0. "mss_ctrl_rd,Status of Interrupt from MSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
line.long 0x0C "MSS_PERIPH_ERRAGG_STATUS_RAW0,"
bitfld.long 0x0C 27. "top_mdo_wr,Raw Status of Interrupt from TOP_MDO" "0,1"
newline
bitfld.long 0x0C 26. "top_mdo_rd,Raw Status of Interrupt from TOP_MDO" "0,1"
newline
bitfld.long 0x0C 25. "rcss_rcm_wr,Raw Status of Interrupt from RCSS_RCM" "0,1"
newline
bitfld.long 0x0C 24. "rcss_rcm_rd,Raw Status of Interrupt from RCSS_RCM" "0,1"
newline
bitfld.long 0x0C 23. "rcss_ctrl_wr,Raw Status of Interrupt from RCSS_CTRL" "0,1"
newline
bitfld.long 0x0C 22. "rcss_ctrl_rd,Raw Status of Interrupt from RCSS_CTRL" "0,1"
newline
bitfld.long 0x0C 21. "hwa_cfg_wr,Raw Status of Interrupt from HWA_CFG" "0,1"
newline
bitfld.long 0x0C 20. "hwa_cfg_rd,Raw Status of Interrupt from HWA_CFG" "0,1"
newline
bitfld.long 0x0C 19. "dss_cm4_ctrl_wr,Raw Status of Interrupt from DSS_CM4_CTRL" "0,1"
newline
bitfld.long 0x0C 18. "dss_cm4_ctrl_rd,Raw Status of Interrupt from DSS_CM4_CTRL" "0,1"
newline
bitfld.long 0x0C 17. "dss_rcm_wr,Raw Status of Interrupt from DSS_RCM" "0,1"
newline
bitfld.long 0x0C 16. "dss_rcm_rd,Raw Status of Interrupt from DSS_RCM" "0,1"
newline
bitfld.long 0x0C 15. "dss_ctrl_wr,Raw Status of Interrupt from DSS_CTRL" "0,1"
newline
bitfld.long 0x0C 14. "dss_ctrl_rd,Raw Status of Interrupt from DSS_CTRL" "0,1"
newline
bitfld.long 0x0C 13. "hsm_ctrl_wr,Raw Status of Interrupt from HSM_CTRL" "0,1"
newline
bitfld.long 0x0C 12. "hsm_ctrl_rd,Raw Status of Interrupt from HSM_CTRL" "0,1"
newline
bitfld.long 0x0C 11. "hsm_soc_ctrl_wr,Raw Status of Interrupt from HSM_SOC_CTRL" "0,1"
newline
bitfld.long 0x0C 10. "hsm_soc_ctrl_rd,Raw Status of Interrupt from HSM_SOC_CTRL" "0,1"
newline
bitfld.long 0x0C 9. "top_aurora_wr,Raw Status of Interrupt from TOP_AURORA" "0,1"
newline
bitfld.long 0x0C 8. "top_aurora_rd,Raw Status of Interrupt from TOP_AURORA" "0,1"
newline
bitfld.long 0x0C 7. "top_rcm_wr,Raw Status of Interrupt from TOP_RCM" "0,1"
newline
bitfld.long 0x0C 6. "top_rcm_rd,Raw Status of Interrupt from TOP_RCM" "0,1"
newline
bitfld.long 0x0C 5. "top_ctrl_wr,Raw Status of Interrupt from TOP_CTRL" "0,1"
newline
bitfld.long 0x0C 4. "top_ctrl_rd,Raw Status of Interrupt from TOP_CTRL" "0,1"
newline
bitfld.long 0x0C 3. "mss_rcm_wr,Raw Status of Interrupt from MSS_RCM" "0,1"
newline
bitfld.long 0x0C 2. "mss_rcm_rd,Raw Status of Interrupt from MSS_RCM" "0,1"
newline
bitfld.long 0x0C 1. "mss_ctrl_wr,Raw Status of Interrupt from MSS_CTRL" "0,1"
newline
bitfld.long 0x0C 0. "mss_ctrl_rd,Raw Status of Interrupt from MSS_CTRL" "0,1"
line.long 0x10 "MSS_PERIPH_ERRAGG_MASK1,"
bitfld.long 0x10 16. "mpu_rd_hsm,Mask Interrupt from MPU_DSS_HSM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 15. "mpu_rd_dss_mbox,Mask Interrupt from MPU_DSS_MBOX to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 14. "mpu_rd_dss_hwa_proc,Mask Interrupt from MPU_DSS_HWA_PROC to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 13. "mpu_rd_dss_hwa_dma1,Mask Interrupt from MPU_DSS_HWA_DMA1 to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 12. "mpu_rd_dss_hwa_dma0,Mask Interrupt from MPU_DSS_HWA_DMA0 to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 11. "mpu_rd_dss_l3_bankd,Mask Interrupt from MPU_DSS_L3_BANKD to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 10. "mpu_rd_dss_l3_bankc,Mask Interrupt from MPU_DSS_L3_BANKC to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 9. "mpu_rd_dss_l3_bankb,Mask Interrupt from MPU_DSS_L3_BANKB to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 8. "mpu_rd_dss_l3_banka,Mask Interrupt from MPU_DSS_L3_BANKA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 7. "mpu_rd_mss_cr5b_axis,Mask Interrupt from MPU_MSS_CR5B_AXIS to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 6. "mpu_rd_mss_cr5a_axis,Mask Interrupt from MPU_MSS_CR5A_AXIS to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 5. "mpu_rd_mss_qspi,Mask Interrupt from MPU_MSS_QSPI to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 4. "mpu_rd_mss_pcra,Mask Interrupt from MPU_MSS_PCRA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 3. "mpu_rd_mss_mbox,Mask Interrupt from MPU_MSS_MBOX to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 2. "mpu_rd_hsm_dthe,Mask Interrupt from MPU_HSM_DTHE to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 1. "mpu_rd_mss_l2_bankb,Mask Interrupt from MPU_MSS_L2_BANKB to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 0. "mpu_rd_mss_l2_banka,Mask Interrupt from MPU_MSS_L2_BANKA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x14 "MSS_PERIPH_ERRAGG_STATUS1,"
bitfld.long 0x14 16. "mpu_rd_hsm,Status of Interrupt from MPU_HSM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 15. "mpu_rd_dss_mbox,Status of Interrupt from MPU_DSS_MBOX Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 14. "mpu_rd_dss_hwa_proc,Status of Interrupt from MPU_DSS_HWA_PROC Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 13. "mpu_rd_dss_hwa_dma1,Status of Interrupt from MPU_DSS_HWA_DMA1 Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 12. "mpu_rd_dss_hwa_dma0,Status of Interrupt from MPU_DSS_HWA_DMA0 Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 11. "mpu_rd_dss_l3_bankd,Status of Interrupt from MPU_DSS_L3_BANKD Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 10. "mpu_rd_dss_l3_bankc,Status of Interrupt from MPU_DSS_L3_BANKC Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 9. "mpu_rd_dss_l3_bankb,Status of Interrupt from MPU_DSS_L3_BANKB Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 8. "mpu_rd_dss_l3_banka,Status of Interrupt from MPU_DSS_L3_BANKA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 7. "mpu_rd_mss_cr5b_axis,Status of Interrupt from MPU_MSS_CR5B_AXIS Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 6. "mpu_rd_mss_cr5a_axis,Status of Interrupt from MPU_MSS_CR5A_AXIS Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 5. "mpu_rd_mss_qspi,Status of Interrupt from MPU_MSS_QSPI Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 4. "mpu_rd_mss_pcra,Status of Interrupt from MPU_MSS_PCRA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 3. "mpu_rd_mss_mbox,Status of Interrupt from MPU_MSS_MBOX Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 2. "mpu_rd_hsm_dthe,Status of Interrupt from MPU_HSM_DTHE Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 1. "mpu_rd_mss_l2_bankb,Status of Interrupt from MPU_MSS_L2_BANKB Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 0. "mpu_rd_mss_l2_banka,Status of Interrupt from MPU_MSS_L2_BANKA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
line.long 0x18 "MSS_PERIPH_ERRAGG_STATUS_RAW1,"
bitfld.long 0x18 16. "mpu_rd_hsm,Raw Status of Interrupt from MPU_HSM" "0,1"
newline
bitfld.long 0x18 15. "mpu_rd_dss_mbox,Raw Status of Interrupt from MPU_DSS_MBOX" "0,1"
newline
bitfld.long 0x18 14. "mpu_rd_dss_hwa_proc,Raw Status of Interrupt from MPU_DSS_HWA_PROC" "0,1"
newline
bitfld.long 0x18 13. "mpu_rd_dss_hwa_dma1,Raw Status of Interrupt from MPU_DSS_HWA_DMA1" "0,1"
newline
bitfld.long 0x18 12. "mpu_rd_dss_hwa_dma0,Raw Status of Interrupt from MPU_DSS_HWA_DMA0" "0,1"
newline
bitfld.long 0x18 11. "mpu_rd_dss_l3_bankd,Raw Status of Interrupt from MPU_DSS_L3_BANKD" "0,1"
newline
bitfld.long 0x18 10. "mpu_rd_dss_l3_bankc,Raw Status of Interrupt from MPU_DSS_L3_BANKC" "0,1"
newline
bitfld.long 0x18 9. "mpu_rd_dss_l3_bankb,Raw Status of Interrupt from MPU_DSS_L3_BANKB" "0,1"
newline
bitfld.long 0x18 8. "mpu_rd_dss_l3_banka,Raw Status of Interrupt from MPU_DSS_L3_BANKA" "0,1"
newline
bitfld.long 0x18 7. "mpu_rd_mss_cr5b_axis,Raw Status of Interrupt from MPU_MSS_CR5B_AXIS" "0,1"
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bitfld.long 0x18 6. "mpu_rd_mss_cr5a_axis,Raw Status of Interrupt from MPU_MSS_CR5A_AXIS" "0,1"
newline
bitfld.long 0x18 5. "mpu_rd_mss_qspi,Raw Status of Interrupt from MPU_MSS_QSPI" "0,1"
newline
bitfld.long 0x18 4. "mpu_rd_mss_pcra,Raw Status of Interrupt from MPU_MSS_PCRA" "0,1"
newline
bitfld.long 0x18 3. "mpu_rd_mss_mbox,Raw Status of Interrupt from MPU_MSS_MBOX" "0,1"
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bitfld.long 0x18 2. "mpu_rd_hsm_dthe,Raw Status of Interrupt from MPU_HSM_D" "0,1"
newline
bitfld.long 0x18 1. "mpu_rd_mss_l2_bankb,Raw Status of Interrupt from MPU_MSS_L2_BANKB" "0,1"
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bitfld.long 0x18 0. "mpu_rd_mss_l2_banka,Raw Status of Interrupt from MPU_MSS_L2_BANKA" "0,1"
line.long 0x1C "MSS_DMM_EVENT0_REG,"
bitfld.long 0x1C 28. "event_sel3,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x1C 24. "event_trig3,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
newline
bitfld.long 0x1C 20. "event_sel2,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x1C 16. "event_trig2,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
newline
bitfld.long 0x1C 12. "event_sel1,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x1C 8. "event_trig1,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
newline
bitfld.long 0x1C 4. "event_sel0,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
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bitfld.long 0x1C 0. "event_trig0,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
line.long 0x20 "MSS_DMM_EVENT1_REG,"
bitfld.long 0x20 28. "event_sel7,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x20 24. "event_trig7,DMM trigger for RCSS_CSI2A_SOF_INT1" "0,1"
newline
bitfld.long 0x20 20. "event_sel6,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x20 16. "event_trig6,DMM trigger for RCSS_CSI2A_SOF_INT1" "0,1"
newline
bitfld.long 0x20 12. "event_sel5,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x20 8. "event_trig5,DMM trigger for RCSS_CSI2A_SOF_INT1" "0,1"
newline
bitfld.long 0x20 4. "event_sel4,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
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bitfld.long 0x20 0. "event_trig4,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
line.long 0x24 "MSS_DMM_EVENT2_REG,"
bitfld.long 0x24 28. "event_sel11,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 24. "event_trig11,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x24 20. "event_sel10,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 16. "event_trig10,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x24 12. "event_sel9,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 8. "event_trig9,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x24 4. "event_sel8,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
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bitfld.long 0x24 0. "event_trig8,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
line.long 0x28 "MSS_DMM_EVENT3_REG,"
bitfld.long 0x28 28. "event_sel15,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 24. "event_trig15,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x28 20. "event_sel14,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 16. "event_trig14,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x28 12. "event_sel13,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 8. "event_trig13,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x28 4. "event_sel12,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
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bitfld.long 0x28 0. "event_trig12,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
line.long 0x2C "MSS_DMM_EVENT4_REG,"
bitfld.long 0x2C 28. "event_sel19,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 24. "event_trig19,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x2C 20. "event_sel18,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 16. "event_trig18,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x2C 12. "event_sel17,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 8. "event_trig17,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x2C 4. "event_sel16,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
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bitfld.long 0x2C 0. "event_trig16,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
line.long 0x30 "MSS_DMM_EVENT5_REG,"
bitfld.long 0x30 28. "event_sel23,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 24. "event_trig23,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x30 20. "event_sel22,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 16. "event_trig22,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x30 12. "event_sel21,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 8. "event_trig21,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
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bitfld.long 0x30 4. "event_sel20,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
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bitfld.long 0x30 0. "event_trig20,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
line.long 0x34 "MSS_DMM_EVENT6_REG,"
bitfld.long 0x34 28. "event_sel27,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 24. "event_trig27,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
newline
bitfld.long 0x34 20. "event_sel26,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 16. "event_trig26,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
newline
bitfld.long 0x34 12. "event_sel25,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 8. "event_trig25,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
newline
bitfld.long 0x34 4. "event_sel24,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 0. "event_trig24,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
line.long 0x38 "MSS_DMM_EVENT7_REG,"
bitfld.long 0x38 28. "event_sel31,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 24. "event_trig31,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
newline
bitfld.long 0x38 20. "event_sel30,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 16. "event_trig30,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
newline
bitfld.long 0x38 12. "event_sel29,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 8. "event_trig29,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
newline
bitfld.long 0x38 4. "event_sel28,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 0. "event_trig28,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
line.long 0x3C "MSS_DMM_EVENT8_REG,"
bitfld.long 0x3C 28. "event_sel35,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 24. "event_trig35,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
newline
bitfld.long 0x3C 20. "event_sel34,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 16. "event_trig34,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
newline
bitfld.long 0x3C 12. "event_sel33,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 8. "event_trig33,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
newline
bitfld.long 0x3C 4. "event_sel32,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 0. "event_trig32,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
line.long 0x40 "MSS_DMM_EVENT9_REG,"
bitfld.long 0x40 28. "event_sel39,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 24. "event_trig39,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
newline
bitfld.long 0x40 20. "event_sel38,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 16. "event_trig38,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
newline
bitfld.long 0x40 12. "event_sel37,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 8. "event_trig37,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
newline
bitfld.long 0x40 4. "event_sel36,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 0. "event_trig36,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
line.long 0x44 "MSS_DMM_EVENT10_REG,"
bitfld.long 0x44 28. "event_sel43,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 24. "event_trig43,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
newline
bitfld.long 0x44 20. "event_sel42,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 16. "event_trig42,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
newline
bitfld.long 0x44 12. "event_sel41,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 8. "event_trig41,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
newline
bitfld.long 0x44 4. "event_sel40,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 0. "event_trig40,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
line.long 0x48 "MSS_DMM_EVENT11_REG,"
bitfld.long 0x48 28. "event_sel47,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 24. "event_trig47,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
newline
bitfld.long 0x48 20. "event_sel46,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 16. "event_trig46,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
newline
bitfld.long 0x48 12. "event_sel45,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 8. "event_trig45,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
newline
bitfld.long 0x48 4. "event_sel44,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 0. "event_trig44,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
line.long 0x4C "MSS_DMM_EVENT12_REG,"
bitfld.long 0x4C 28. "event_sel51,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 24. "event_trig51,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x4C 20. "event_sel50,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 16. "event_trig50,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x4C 12. "event_sel49,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 8. "event_trig49,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x4C 4. "event_sel48,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 0. "event_trig48,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
line.long 0x50 "MSS_DMM_EVENT13_REG,"
bitfld.long 0x50 28. "event_sel55,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 24. "event_trig55,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x50 20. "event_sel54,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 16. "event_trig54,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x50 12. "event_sel53,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 8. "event_trig53,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x50 4. "event_sel52,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 0. "event_trig52,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
line.long 0x54 "MSS_DMM_EVENT14_REG,"
bitfld.long 0x54 28. "event_sel59,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 24. "event_trig59,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x54 20. "event_sel58,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 16. "event_trig58,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x54 12. "event_sel57,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 8. "event_trig57,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x54 4. "event_sel56,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 0. "event_trig56,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
line.long 0x58 "MSS_DMM_EVENT15_REG,"
bitfld.long 0x58 28. "event_sel63,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 24. "event_trig63,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x58 20. "event_sel62,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 16. "event_trig62,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x58 12. "event_sel61,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 8. "event_trig61,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x58 4. "event_sel60,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 0. "event_trig60,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
line.long 0x5C "MSS_TPTC_BOUNDARY_CFG,"
bitfld.long 0x5C 16.--21. "tptc_b0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_B0 Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x5C 8.--13. "tptc_a1_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A1 Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x5C 0.--5. "tptc_a0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A0 Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x60 "MSS_TPTC_XID_REORDER_CFG,"
bitfld.long 0x60 16. "tptc_b0_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x60 8. "tptc_a1_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x60 0. "tptc_a0_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A0" "0,1"
line.long 0x64 "GPADC_CTRL,"
bitfld.long 0x64 8.--12. "gpadc_trigin_sel,Writing below decimal values to this regiter will select corresponding interrupt as GPADC trigger source" "GPIO_0,GPIO_1,GPIO_2,GPIO_3,RSS_CSI2A_EOL_INT,RSS_CSI2A_SOF_INT0,RSS_CSI2A_SOF_INT1,RSS_CSI2A_SOF_INT,RSS_CSI2B_SOF_INT,HW_Sync_FE1,HW_Sync_FE2,DSS_RTIA_1,DSS_RTIB_1,MSS_RTIA_INT1,MSS_RTIB_INT1,MMR based SW trigger,?..."
newline
bitfld.long 0x64 0. "gpadc_sw_trig,Writing 1'b1 will give MMR based SW trigger to GPADC" "0,1"
line.long 0x68 "HW_Sync_FE_CTRL,"
bitfld.long 0x68 8. "fe2_sel,Writing" "Selects MCANA filter event as HW_Sync_FE2,Selects MCANB filter event as HW_Sync_FE2"
newline
bitfld.long 0x68 0. "fe1_sel,Writing" "Selects MCANA filter event as HW_Sync_FE1,Selects MCANB filter event as HW_Sync_FE1"
line.long 0x6C "DEBUGSS_CSETB_FLUSH,"
rbitfld.long 0x6C 10. "CSETB_FULL,When HIGH indicates that the ETB RAM has overflowed or wrapped around to address zero" "0,1"
newline
rbitfld.long 0x6C 9. "CSETB_ACQ_COMPLETE,When HIGH indicates that trace acquisition is complete by ETB that is the trigger counter is at zero" "0,1"
newline
rbitfld.long 0x6C 8. "CSETB_FLUSHINACK,Return acknowledgement to CSETBFLUSHIN" "0,1"
newline
bitfld.long 0x6C 0. "CSETB_FLUSHIN,External control used to assert the ATB signal AFVALIDS and drain any historical FIFO information on the bus" "0,1"
line.long 0x70 "ANALOG_WU_STATUS_REG_POLARITY_INV,"
line.long 0x74 "ANALOG_CLK_STATUS_REG_POLARITY_INV,"
line.long 0x78 "ANALOG_WU_STATUS_REG_GRP1_MASK,"
line.long 0x7C "ANALOG_CLK_STATUS_REG_GRP1_MASK,"
line.long 0x80 "ANALOG_WU_STATUS_REG_GRP2_MASK,"
line.long 0x84 "ANALOG_CLK_STATUS_REG_GRP2_MASK,"
line.long 0x88 "NERROR_MASK,"
bitfld.long 0x88 0.--2. "mask,writing 3'b111 will mask the Nerror propagation to pad Writing 3'b000 will unmask the Nerror propagation to pad" "0,1,2,3,4,5,6,7"
group.long 0x800++0x13
line.long 0x00 "R5_CONTROL,"
bitfld.long 0x00 24.--26. "rom_wait_state,writing '111' enables a single cycle wait state with respect to CR5A_clk for rom access" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "reset_fsm_trigger,writing 3'b111 will trigger the reset FSM" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "lock_step_switch_wait,writing 3'b111 ensures switch happens only after R5SS reset" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "lock_step,writing 3'b000 ensures R5 to be in Dual-Core mode" "0,1,2,3,4,5,6,7"
line.long 0x04 "R5_ROM_ECLIPSE,"
bitfld.long 0x04 8.--10. "memswap_wait,writing 3'b111 ensures ROM-Eclipsing happens only after R5SS reset" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--2. "memswap,writing '111' ensures eclipsing of CR5A_ROM immediately if memswap_wait is not set" "0,1,2,3,4,5,6,7"
line.long 0x08 "R5_COREA_HALT,"
bitfld.long 0x08 0.--2. "halt,writing '000' will unhalt CR5A" "0,1,2,3,4,5,6,7"
line.long 0x0C "R5_COREB_HALT,"
bitfld.long 0x0C 0.--2. "halt,writing '000' will unhalt for CR5B" "0,1,2,3,4,5,6,7"
line.long 0x10 "R5_STATUS_REG,"
bitfld.long 0x10 8. "lock_step,Reading" "confirms R5SS is in Dual-core mode,confirms R5SS is in lockstep mode"
newline
bitfld.long 0x10 0. "memswap,reading" "0,1"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x634)++0x03
line.long 0x00 "MSS_BOOT_INFO_REG$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x618)++0x03
line.long 0x00 "MSS_PBIST_REG$1,"
repeat.end
repeat 7. (list 0. 1. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x518)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_DCCA (MSS DCCA Module Registers)"
base ad:0x52F79C00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DCCB (MSS DCCB Module Registers)"
base ad:0x52F79D00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DCCC (MSS DCCC Module Registers)"
base ad:0x52F79E00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DCCD (MSS DCCD Module Registers)"
base ad:0x52F79F00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DMM_A (MSS DMMA Module Registers)"
base ad:0x53F79C00
group.long 0x00++0x8F
line.long 0x00 "GLBCTRL,Sets the global configuration of the module"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "BUSY,BUSY User and privilege mode (read)" "the DMM does not currently receive data and has..,the module is currently receiving data or has.."
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rbitfld.long 0x00 19.--23. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18. "CONTCLK,CONTCLK" "suspend RTPCLK between packets,enable free running clock between packets"
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bitfld.long 0x00 17. "COS,COS" "disable data reception while in suspend mode,enable data reception while in suspend mode"
bitfld.long 0x00 16. "RESET,RESET This bit resets the statemachine and the registers to its reset value except the RESET bit itself" "no reset of DMM module,reset DMM module to its reset state"
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rbitfld.long 0x00 11.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9.--10. "DDM_WIDTH,DDM_WIDTH: Packet Width in Direct Data Mode User and privilege mode read and write operation: Bit Encoding Transfer Size 00 8 bit 01 16 bit 10 32 bit 11 Reserved" "0,1,2,3"
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bitfld.long 0x00 8. "TM_DMM,TM_DMM: Packet Format If this bit is set the DMM module assumes to receive packets by the Direct Data Mode" "enable Trace Mode,enable Direct Data Mode"
rbitfld.long 0x00 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "ONOFF,ON/OFF User and privilege mode (read)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTSET       ,Enables interrupts"
hexmask.long.word 0x04 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x04 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Set This enables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Set This enables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,enable interrupt when BMM HRESP = Error"
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bitfld.long 0x04 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Set This enables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Set This enables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,enable interrupt"
bitfld.long 0x04 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Set This enables the interrupt generation in case of an error condition" "no influence on bit,enable interrupt (sets corresponding bit in.."
line.long 0x08 "INTCLR,Disables interrupts"
hexmask.long.word 0x08 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x08 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Clear This disables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Clear This disables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,disable interrupt on BMM HRESP = Error"
newline
bitfld.long 0x08 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Clear This disables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Clear This disables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Clear This disables the interrupt generation in case of an error condition" "no influence on bit,disable interrupt (clears corresponding bit in.."
line.long 0x0C "INTLVL,Selects high or low priority interrupt level"
hexmask.long.word 0x0C 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x0C 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
line.long 0x10 "INTFLAG,Interrupt Flags"
hexmask.long.word 0x10 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x10 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 7. "BUSERROR,BUSERROR: BMM Bus Error Response This bit is set when the BMM HRESP = Error" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
line.long 0x14 "OFF1,Interrupt offset for high priority level"
hexmask.long 0x14 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x14 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "OFF2,Interrupt offset for low priority level"
hexmask.long 0x18 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x18 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "DDMDEST,Configuration of Buffer for Direct Data Mode"
line.long 0x20 "DDMBL,Defines the blocksize for the buffer in Direct Data Mode"
hexmask.long 0x20 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x20 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DDMPT,Pointer to the last written entry in the buffer"
hexmask.long.tbyte 0x24 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x24 0.--14. 1. "POINTER,POINTER These bits hold the pointer to the next entry to be written in the buffer"
line.long 0x28 "INTPT,Programmable Interrupt Pointer"
hexmask.long.tbyte 0x28 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x28 0.--14. 1. "INTPT,INTPT: Interrupt Pointer When the buffer pointer (DMMDDMPT) matches the programmed value in DMMINTPT and the PROG_BUF interrupt is set a interrupt is generated"
line.long 0x2C "DEST0REG1,Defines Region 1 for Destination 0"
hexmask.long.word 0x2C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x2C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x30 "DEST0BL1,Defines the blocksize for the buffer for Destination 0 Region 1"
hexmask.long 0x30 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x30 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DEST0REG2,Defines Region 2 for Destination 0"
hexmask.long.word 0x34 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x34 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x38 "DEST0BL2,Defines the blocksize for the buffer for Destination 0 Region 2"
hexmask.long 0x38 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x38 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "DEST1REG1,Defines Region 1 for Destination1"
hexmask.long.word 0x3C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x3C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x40 "DEST1BL1,Defines the blocksize for the buffer for Destination 1 Region 1"
hexmask.long 0x40 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x40 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "DEST1REG2,Defines Region 2 for Destination 1"
hexmask.long.word 0x44 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x44 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x48 "DEST1BL2,Defines the blocksize for the buffer for Destination 1 Region 2"
hexmask.long 0x48 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x48 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "DEST2REG1,Defines Region 1 for Destination 2"
hexmask.long.word 0x4C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x4C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x50 "DEST2BL1,Defines the blocksize for the buffer for Destination 2 Region 1"
hexmask.long 0x50 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x50 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "DEST2REG2,Defines Region 2 for Destination 2"
hexmask.long.word 0x54 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x54 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x58 "DEST2BL2,Defines the blocksize for the buffer for Destination 2 Region 2"
hexmask.long 0x58 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x58 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "DEST3REG1,Defines Region 1 for Destination 3"
hexmask.long.word 0x5C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x5C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x60 "DEST3BL1,Defines the blocksize for the buffer for Destination 3 Region 1"
hexmask.long 0x60 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x60 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "DEST3REG2,Defines Region 2 for Destination 3"
hexmask.long.word 0x64 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x64 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x68 "DEST3BL2,Defines the blocksize for the buffer for Destination 3 Region 2"
hexmask.long 0x68 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x68 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "DMMPC0,Defines functional or GIO mode of pins"
hexmask.long.word 0x6C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x6C 18. "ENAFUNC,ENAFUNC: Functional mode of DMMENA pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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abitfld.long 0x6C 2.--17. "DATAxFUNC,DATAxFUNC: Functional mode of DMMDATA[x] pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "0x0000=Pin is used in GIO mode,0x0001=Pin is used in Functional model mode"
bitfld.long 0x6C 1. "CLKFUNC,CLKFUNC: Functional mode of DMMCLK pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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bitfld.long 0x6C 0. "SYNCFUNC,SYNCFUNC: Functional mode of DMMSYNC pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
line.long 0x70 "DMMPC1,Defines direction of pins"
hexmask.long.word 0x70 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x70 18. "ENADIR,ENADIR: Direction of DMMENA pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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abitfld.long 0x70 2.--17. "DATAxDIR,DATAxDIR: Direction of DMMDATA[x] pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "0x0000=Pin is set to input,0x0001=Pin is set to output"
bitfld.long 0x70 1. "CLKDIR,CLKDIR: Direction of DMMCLK pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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bitfld.long 0x70 0. "SYNCDIR,SYNCDIR: Direction of DMMSYNC pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
line.long 0x74 "DMMPC2,Input level of pins"
hexmask.long.word 0x74 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x74 18. "ENAIN,ENAIN: DMMENA input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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abitfld.long 0x74 2.--17. "DATAxIN,DATAxIN: DMMDATA[x] input This bit reflects the state of the pin in all modes User and privilege mode (read)" "0x0000=Logic low (input voltage is VIL or lower),0x0001=Logic high (input voltage is VIH or.."
bitfld.long 0x74 1. "CLKIN,CLKIN: DMMCLK input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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bitfld.long 0x74 0. "SYNCIN,SYNCIN: DMMSYNC input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
line.long 0x78 "DMMPC3,Sets pins to high or low"
hexmask.long.word 0x78 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x78 18. "ENAOUT,ENAOUT: Output state of DMMENA pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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abitfld.long 0x78 2.--17. "DATAxOUT,DATAxOUT: Output state of DMMDATA[x] pin This bit sets the pin to logic low or high level User and privilege mode (read)" "0x0000=Logic low (output voltage is set to VOL..,0x0001=Logic high (output voltage is set to VOH.."
bitfld.long 0x78 1. "CLKOUT,CLKOUT: Output state of DMMCLK pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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bitfld.long 0x78 0. "SYNCOUT,SYNCOUT: Output state of DMMSYNC pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
line.long 0x7C "DMMPC4,Sets pins to high"
hexmask.long.word 0x7C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x7C 18. "ENASET,ENASET: Sets output state of DMMENA pin to logic high Value in the ENASET bit sets the data output control register bit to 1 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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abitfld.long 0x7C 2.--17. "DATAxSET,DATAxSET: Sets output state of DMMDATA[x] pin to logic high Value in the DATAxSET bit sets the data output control register bit to 1 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=Sets the pin to Logic high (output.."
bitfld.long 0x7C 1. "CLKSET,CLKSET: Sets output state of DMMCLK pin to logic high Value in the CLKSET bit sets the data output control register bit to 1 regardless of the current value in the CLKOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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bitfld.long 0x7C 0. "SYNCSET,SYNCSET: Sets output state of DMMSYNC pin logic high Value in the SYNCSET bit sets the data output control register bit to 1 regardless of the current value in the SYNCOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
line.long 0x80 "DMMPC5,Sets pins to low"
hexmask.long.word 0x80 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x80 18. "ENACLR,ENACLR: Sets output state of DMMENA pin to logic low Value in the ENACLR bit clears the data output control register bit to 0 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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abitfld.long 0x80 2.--17. "DATAxCLR,DATAxCLR: Sets output state of DMMDATA[x] pin to logic low Value in the DATAxCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=clears the pin to logic low (output.."
bitfld.long 0x80 1. "CLKCLR,CLKCLR: Sets output state of DMMCLK pin to logic low Value in the CLKCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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bitfld.long 0x80 0. "SYNCCLR,SYNCCLR: Sets output state of DMMSYNC pin to logic low Value in the SYNCCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
line.long 0x84 "DMMPC6,Configures open drain functionality of pin"
hexmask.long.word 0x84 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x84 18. "ENAPDR,ENAPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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abitfld.long 0x84 2.--17. "DATAxPDR,DATAxPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "0x0000=configures pin as push/pull,0x0001=configures pin as open drain"
bitfld.long 0x84 1. "CLKPDR,CLKPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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bitfld.long 0x84 0. "SYNCPDR,SYNCPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
line.long 0x88 "DMMPC7,Enables/Disables pullup/pulldown structure of pin"
hexmask.long.word 0x88 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x88 18. "ENAPDIS,ENAPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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abitfld.long 0x88 2.--17. "DATAxPDIS,DATAxPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "0x0000=enables pullup/pulldown functionality,0x0001=disables pullup/pulldown functionality"
bitfld.long 0x88 1. "CLKPDIS,CLKPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
newline
bitfld.long 0x88 0. "SYNCPDIS,SYNCPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
line.long 0x8C "DMMPC8,Enables pullup or pulldown structure of pin"
hexmask.long.word 0x8C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x8C 18. "ENAPSEL,ENAPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
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abitfld.long 0x8C 2.--17. "DATAxPSEL,DATAxPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "0x0000=enables pulldown functionality,0x0001=enables pullup functionality"
bitfld.long 0x8C 1. "CLKPDSEL,CLKPDSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
newline
bitfld.long 0x8C 0. "SYNCPSEL,SYNCPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
width 0x0B
tree.end
tree "MSS_DMM_B (MSS DMMB Module Registers)"
base ad:0x53F79E00
group.long 0x00++0x8F
line.long 0x00 "GLBCTRL,Sets the global configuration of the module"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "BUSY,BUSY User and privilege mode (read)" "the DMM does not currently receive data and has..,the module is currently receiving data or has.."
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rbitfld.long 0x00 19.--23. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18. "CONTCLK,CONTCLK" "suspend RTPCLK between packets,enable free running clock between packets"
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bitfld.long 0x00 17. "COS,COS" "disable data reception while in suspend mode,enable data reception while in suspend mode"
bitfld.long 0x00 16. "RESET,RESET This bit resets the statemachine and the registers to its reset value except the RESET bit itself" "no reset of DMM module,reset DMM module to its reset state"
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rbitfld.long 0x00 11.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9.--10. "DDM_WIDTH,DDM_WIDTH: Packet Width in Direct Data Mode User and privilege mode read and write operation: Bit Encoding Transfer Size 00 8 bit 01 16 bit 10 32 bit 11 Reserved" "0,1,2,3"
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bitfld.long 0x00 8. "TM_DMM,TM_DMM: Packet Format If this bit is set the DMM module assumes to receive packets by the Direct Data Mode" "enable Trace Mode,enable Direct Data Mode"
rbitfld.long 0x00 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 0.--3. "ONOFF,ON/OFF User and privilege mode (read)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTSET       ,Enables interrupts"
hexmask.long.word 0x04 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x04 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Set This enables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Set This enables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,enable interrupt when BMM HRESP = Error"
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bitfld.long 0x04 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Set This enables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Set This enables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,enable interrupt"
bitfld.long 0x04 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Set This enables the interrupt generation in case of an error condition" "no influence on bit,enable interrupt (sets corresponding bit in.."
line.long 0x08 "INTCLR,Disables interrupts"
hexmask.long.word 0x08 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x08 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Clear This disables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Clear This disables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,disable interrupt on BMM HRESP = Error"
newline
bitfld.long 0x08 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Clear This disables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Clear This disables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Clear This disables the interrupt generation in case of an error condition" "no influence on bit,disable interrupt (clears corresponding bit in.."
line.long 0x0C "INTLVL,Selects high or low priority interrupt level"
hexmask.long.word 0x0C 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x0C 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
line.long 0x10 "INTFLAG,Interrupt Flags"
hexmask.long.word 0x10 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x10 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 7. "BUSERROR,BUSERROR: BMM Bus Error Response This bit is set when the BMM HRESP = Error" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
line.long 0x14 "OFF1,Interrupt offset for high priority level"
hexmask.long 0x14 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x14 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "OFF2,Interrupt offset for low priority level"
hexmask.long 0x18 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x18 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "DDMDEST,Configuration of Buffer for Direct Data Mode"
line.long 0x20 "DDMBL,Defines the blocksize for the buffer in Direct Data Mode"
hexmask.long 0x20 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x20 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DDMPT,Pointer to the last written entry in the buffer"
hexmask.long.tbyte 0x24 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x24 0.--14. 1. "POINTER,POINTER These bits hold the pointer to the next entry to be written in the buffer"
line.long 0x28 "INTPT,Programmable Interrupt Pointer"
hexmask.long.tbyte 0x28 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x28 0.--14. 1. "INTPT,INTPT: Interrupt Pointer When the buffer pointer (DMMDDMPT) matches the programmed value in DMMINTPT and the PROG_BUF interrupt is set a interrupt is generated"
line.long 0x2C "DEST0REG1,Defines Region 1 for Destination 0"
hexmask.long.word 0x2C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x2C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x30 "DEST0BL1,Defines the blocksize for the buffer for Destination 0 Region 1"
hexmask.long 0x30 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x30 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DEST0REG2,Defines Region 2 for Destination 0"
hexmask.long.word 0x34 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x34 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x38 "DEST0BL2,Defines the blocksize for the buffer for Destination 0 Region 2"
hexmask.long 0x38 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x38 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "DEST1REG1,Defines Region 1 for Destination1"
hexmask.long.word 0x3C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x3C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x40 "DEST1BL1,Defines the blocksize for the buffer for Destination 1 Region 1"
hexmask.long 0x40 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x40 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "DEST1REG2,Defines Region 2 for Destination 1"
hexmask.long.word 0x44 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x44 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x48 "DEST1BL2,Defines the blocksize for the buffer for Destination 1 Region 2"
hexmask.long 0x48 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x48 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "DEST2REG1,Defines Region 1 for Destination 2"
hexmask.long.word 0x4C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x4C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x50 "DEST2BL1,Defines the blocksize for the buffer for Destination 2 Region 1"
hexmask.long 0x50 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x50 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "DEST2REG2,Defines Region 2 for Destination 2"
hexmask.long.word 0x54 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x54 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x58 "DEST2BL2,Defines the blocksize for the buffer for Destination 2 Region 2"
hexmask.long 0x58 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x58 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "DEST3REG1,Defines Region 1 for Destination 3"
hexmask.long.word 0x5C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x5C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x60 "DEST3BL1,Defines the blocksize for the buffer for Destination 3 Region 1"
hexmask.long 0x60 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x60 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "DEST3REG2,Defines Region 2 for Destination 3"
hexmask.long.word 0x64 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x64 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x68 "DEST3BL2,Defines the blocksize for the buffer for Destination 3 Region 2"
hexmask.long 0x68 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x68 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "DMMPC0,Defines functional or GIO mode of pins"
hexmask.long.word 0x6C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x6C 18. "ENAFUNC,ENAFUNC: Functional mode of DMMENA pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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abitfld.long 0x6C 2.--17. "DATAxFUNC,DATAxFUNC: Functional mode of DMMDATA[x] pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "0x0000=Pin is used in GIO mode,0x0001=Pin is used in Functional model mode"
bitfld.long 0x6C 1. "CLKFUNC,CLKFUNC: Functional mode of DMMCLK pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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bitfld.long 0x6C 0. "SYNCFUNC,SYNCFUNC: Functional mode of DMMSYNC pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
line.long 0x70 "DMMPC1,Defines direction of pins"
hexmask.long.word 0x70 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x70 18. "ENADIR,ENADIR: Direction of DMMENA pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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abitfld.long 0x70 2.--17. "DATAxDIR,DATAxDIR: Direction of DMMDATA[x] pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "0x0000=Pin is set to input,0x0001=Pin is set to output"
bitfld.long 0x70 1. "CLKDIR,CLKDIR: Direction of DMMCLK pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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bitfld.long 0x70 0. "SYNCDIR,SYNCDIR: Direction of DMMSYNC pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
line.long 0x74 "DMMPC2,Input level of pins"
hexmask.long.word 0x74 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x74 18. "ENAIN,ENAIN: DMMENA input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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abitfld.long 0x74 2.--17. "DATAxIN,DATAxIN: DMMDATA[x] input This bit reflects the state of the pin in all modes User and privilege mode (read)" "0x0000=Logic low (input voltage is VIL or lower),0x0001=Logic high (input voltage is VIH or.."
bitfld.long 0x74 1. "CLKIN,CLKIN: DMMCLK input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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bitfld.long 0x74 0. "SYNCIN,SYNCIN: DMMSYNC input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
line.long 0x78 "DMMPC3,Sets pins to high or low"
hexmask.long.word 0x78 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x78 18. "ENAOUT,ENAOUT: Output state of DMMENA pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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abitfld.long 0x78 2.--17. "DATAxOUT,DATAxOUT: Output state of DMMDATA[x] pin This bit sets the pin to logic low or high level User and privilege mode (read)" "0x0000=Logic low (output voltage is set to VOL..,0x0001=Logic high (output voltage is set to VOH.."
bitfld.long 0x78 1. "CLKOUT,CLKOUT: Output state of DMMCLK pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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bitfld.long 0x78 0. "SYNCOUT,SYNCOUT: Output state of DMMSYNC pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
line.long 0x7C "DMMPC4,Sets pins to high"
hexmask.long.word 0x7C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x7C 18. "ENASET,ENASET: Sets output state of DMMENA pin to logic high Value in the ENASET bit sets the data output control register bit to 1 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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abitfld.long 0x7C 2.--17. "DATAxSET,DATAxSET: Sets output state of DMMDATA[x] pin to logic high Value in the DATAxSET bit sets the data output control register bit to 1 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=Sets the pin to Logic high (output.."
bitfld.long 0x7C 1. "CLKSET,CLKSET: Sets output state of DMMCLK pin to logic high Value in the CLKSET bit sets the data output control register bit to 1 regardless of the current value in the CLKOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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bitfld.long 0x7C 0. "SYNCSET,SYNCSET: Sets output state of DMMSYNC pin logic high Value in the SYNCSET bit sets the data output control register bit to 1 regardless of the current value in the SYNCOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
line.long 0x80 "DMMPC5,Sets pins to low"
hexmask.long.word 0x80 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x80 18. "ENACLR,ENACLR: Sets output state of DMMENA pin to logic low Value in the ENACLR bit clears the data output control register bit to 0 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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abitfld.long 0x80 2.--17. "DATAxCLR,DATAxCLR: Sets output state of DMMDATA[x] pin to logic low Value in the DATAxCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=clears the pin to logic low (output.."
bitfld.long 0x80 1. "CLKCLR,CLKCLR: Sets output state of DMMCLK pin to logic low Value in the CLKCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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bitfld.long 0x80 0. "SYNCCLR,SYNCCLR: Sets output state of DMMSYNC pin to logic low Value in the SYNCCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
line.long 0x84 "DMMPC6,Configures open drain functionality of pin"
hexmask.long.word 0x84 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x84 18. "ENAPDR,ENAPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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abitfld.long 0x84 2.--17. "DATAxPDR,DATAxPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "0x0000=configures pin as push/pull,0x0001=configures pin as open drain"
bitfld.long 0x84 1. "CLKPDR,CLKPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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bitfld.long 0x84 0. "SYNCPDR,SYNCPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
line.long 0x88 "DMMPC7,Enables/Disables pullup/pulldown structure of pin"
hexmask.long.word 0x88 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x88 18. "ENAPDIS,ENAPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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abitfld.long 0x88 2.--17. "DATAxPDIS,DATAxPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "0x0000=enables pullup/pulldown functionality,0x0001=disables pullup/pulldown functionality"
bitfld.long 0x88 1. "CLKPDIS,CLKPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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bitfld.long 0x88 0. "SYNCPDIS,SYNCPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
line.long 0x8C "DMMPC8,Enables pullup or pulldown structure of pin"
hexmask.long.word 0x8C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x8C 18. "ENAPSEL,ENAPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
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abitfld.long 0x8C 2.--17. "DATAxPSEL,DATAxPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "0x0000=enables pulldown functionality,0x0001=enables pullup functionality"
bitfld.long 0x8C 1. "CLKPDSEL,CLKPDSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
newline
bitfld.long 0x8C 0. "SYNCPSEL,SYNCPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
width 0x0B
tree.end
tree "MSS_ECC_AGG_MSS (MSS ECC Aggregator MSS Module Registers)"
base ad:0x52F7C000
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 7. "TPTC_B0_PEND,Interrupt Pending Status for tptc_b0_pend" "0,1"
bitfld.long 0x04 6. "TPTC_A1_PEND,Interrupt Pending Status for tptc_a1_pend" "0,1"
bitfld.long 0x04 5. "TPTC_A0_PEND,Interrupt Pending Status for tptc_a0_pend" "0,1"
bitfld.long 0x04 4. "GPADC_PEND,Interrupt Pending Status for gpadc_pend" "0,1"
bitfld.long 0x04 3. "MSS_RETRAM_PEND,Interrupt Pending Status for mss_retram_pend" "0,1"
bitfld.long 0x04 2. "MSS_MBOX_PEND,Interrupt Pending Status for mss_mbox_pend" "0,1"
newline
bitfld.long 0x04 1. "MSS_L2SLV1_PEND,Interrupt Pending Status for mss_l2slv1_pend" "0,1"
bitfld.long 0x04 0. "MSS_L2SLV0_PEND,Interrupt Pending Status for mss_l2slv0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_SET,Interrupt Enable Set Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_SET,Interrupt Enable Set Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_SET,Interrupt Enable Set Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_CLR,Interrupt Enable Clear Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_CLR,Interrupt Enable Clear Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_CLR,Interrupt Enable Clear Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 7. "TPTC_B0_PEND,Interrupt Pending Status for tptc_b0_pend" "0,1"
bitfld.long 0x04 6. "TPTC_A1_PEND,Interrupt Pending Status for tptc_a1_pend" "0,1"
bitfld.long 0x04 5. "TPTC_A0_PEND,Interrupt Pending Status for tptc_a0_pend" "0,1"
bitfld.long 0x04 4. "GPADC_PEND,Interrupt Pending Status for gpadc_pend" "0,1"
bitfld.long 0x04 3. "MSS_RETRAM_PEND,Interrupt Pending Status for mss_retram_pend" "0,1"
bitfld.long 0x04 2. "MSS_MBOX_PEND,Interrupt Pending Status for mss_mbox_pend" "0,1"
newline
bitfld.long 0x04 1. "MSS_L2SLV1_PEND,Interrupt Pending Status for mss_l2slv1_pend" "0,1"
bitfld.long 0x04 0. "MSS_L2SLV0_PEND,Interrupt Pending Status for mss_l2slv0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_SET,Interrupt Enable Set Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_SET,Interrupt Enable Set Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_SET,Interrupt Enable Set Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_CLR,Interrupt Enable Clear Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_CLR,Interrupt Enable Clear Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_CLR,Interrupt Enable Clear Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_ECC_AGG_R5A (MSS ECC Aggregator R5A Module Registers)"
base ad:0x52F7B800
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_ECC_AGG_R5B (MSS ECC Aggregator R5B Module Registers)"
base ad:0x52F7BC00
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_ESM (MSS ESM Module Registers)"
base ad:0x52F7A400
group.long 0x00++0x5B
line.long 0x00 "ESMIEPSR1,ESM Enable ERROR Pin Action/Response Register 1"
line.long 0x04 "ESMIEPCR1,ESM Disable ERROR Pin Action/Response Register 1"
line.long 0x08 "ESMIESR1,ESM Interrupt Enable Set/Status Register 1"
line.long 0x0C "ESMIECR1,ESM Interrupt Enable Clear/Status Register 1"
line.long 0x10 "ESMILSR1,Interrupt Level Set/Status Register 1"
line.long 0x14 "ESMILCR1,Interrupt Level Clear/Status Register 1"
line.long 0x18 "ESMSR1,ESM Status Register 1"
line.long 0x1C "ESMSR2,ESM Status Register 2"
line.long 0x20 "ESMSR3,ESM Status Register 3"
line.long 0x24 "ESMEPSR,ESM ERROR Pin Status Register"
hexmask.long 0x24 1.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EPSF,ERROR Pin Status Flag" "0,1"
line.long 0x28 "ESMIOFFHR,ESM Interrupt Offset High Register"
hexmask.long.tbyte 0x28 9.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x28 0.--8. 1. "INTOFFH,Offset High Level Interrupt"
line.long 0x2C "ESMIOFFLR,ESM Interrupt Offset Low Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x2C 0.--7. 1. "INTOFFL,Offset Low Level Interrupt"
line.long 0x30 "ESMLTCR,ESM Low-Time Counter Register"
hexmask.long.word 0x30 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x30 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin"
line.long 0x34 "ESMLTCPR,ESM Low-Time Counter Preload Register"
hexmask.long.word 0x34 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x34 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter"
line.long 0x38 "ESMEKR,ESM Error Key Register"
hexmask.long 0x38 4.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0.--3. "EKEY,Error Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "ESMSSR2,ESM Status Shadow Register 2"
line.long 0x40 "ESMIEPSR4,ESM Enable ERROR Pin Action/Response Register 4"
line.long 0x44 "ESMIEPCR4,ESM Disable ERROR Pin Action/Response Register 4"
line.long 0x48 "ESMIESR4,ESM Interrupt Enable Set/Status Register 4"
line.long 0x4C "ESMIECR4,ESM Interrupt Enable Clear/Status Register 4"
line.long 0x50 "ESMILSR4,Interrupt Level Set/Status Register 4"
line.long 0x54 "ESMILCR4,Interrupt Level Clear/Status Register 4"
line.long 0x58 "ESMSR4,ESM Status Register 4"
group.long 0x80++0x1B
line.long 0x00 "ESMIEPSR7,ESM Enable ERROR Pin Action/Response Register 7"
line.long 0x04 "ESMIEPCR7,ESM Disable ERROR Pin Action/Response Register 7"
line.long 0x08 "ESMIESR7,ESM Interrupt Enable Set/Status Register 7"
line.long 0x0C "ESMIECR7,ESM Interrupt Enable Clear/Status Register 7"
line.long 0x10 "ESMILSR7,Interrupt Level Set/Status Register 7"
line.long 0x14 "ESMILCR7,Interrupt Level Clear/Status Register 7"
line.long 0x18 "ESMSR7,ESM Status Register 7"
group.long 0xC0++0x1B
line.long 0x00 "ESMIEPSR10,ESM Enable ERROR Pin Action/Response Register 10"
line.long 0x04 "ESMIEPCR10,ESM Disable ERROR Pin Action/Response Register 10"
line.long 0x08 "ESMIESR10,ESM Interrupt Enable Set/Status Register 10"
line.long 0x0C "ESMIECR10,ESM Interrupt Enable Clear/Status Register 10"
line.long 0x10 "ESMILSR10,Interrupt Level Set/Status Register 10"
line.long 0x14 "ESMILCR10,Interrupt Level Clear/Status Register 10"
line.long 0x18 "ESMSR10,ESM Status Register 10"
width 0x0B
tree.end
tree "MSS_ETPWMA (MSS ETPWMA Module Registers)"
base ad:0x53F78C00
group.long 0x00++0x3F
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
hexmask.long.word 0x00 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x00 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value" "0,1"
bitfld.long 0x00 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred" "0,1"
bitfld.long 0x00 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit" "0,1"
newline
bitfld.long 0x00 14.--15. "TBCTL_FREE,_SOFT,Emulation Mode Bits" "0,1,2,3"
bitfld.long 0x00 13. "TBCTL_PHSDIR,Phase Direction Bit" "0,1"
bitfld.long 0x00 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0" "0,1"
bitfld.long 0x00 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select" "0,1,2,3"
bitfld.long 0x00 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero" "0,1"
bitfld.long 0x00 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
newline
bitfld.long 0x00 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation" "0,1,2,3"
line.long 0x04 "TBPHS,Time-Base Phase Register"
hexmask.long.word 0x04 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal"
hexmask.long.word 0x04 0.--15. 1. "Reserved,Reserved"
line.long 0x08 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
hexmask.long.word 0x08 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter"
hexmask.long.word 0x08 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value"
line.long 0x0C "CMPCTL,Counter-Compare Control Register"
rbitfld.long 0x0C 26.--31. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
bitfld.long 0x0C 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made" "0,1"
rbitfld.long 0x0C 23. "Reserved3,Reserved" "0,1"
newline
bitfld.long 0x0C 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode" "0,1"
rbitfld.long 0x0C 21. "Reserved2,Reserved" "0,1"
bitfld.long 0x0C 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode" "0,1"
bitfld.long 0x0C 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1)" "0,1,2,3"
newline
bitfld.long 0x0C 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "0,1,2,3"
hexmask.long.word 0x0C 0.--15. 1. "Reserved1,Reserved"
line.long 0x10 "CMPA,Counter-Compare A Register"
hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR)"
hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
rbitfld.long 0x14 28.--31. "Reserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
newline
bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period" "0,1,2,3"
bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero" "0,1,2,3"
hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR)"
line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is.." "0,1,2,3"
bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
newline
bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low High High Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
rbitfld.long 0x18 12.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period" "0,1,2,3"
newline
bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero" "0,1,2,3"
line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled" "0,1"
hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28" "0,1,2,3"
bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28" "0,1,2,3"
newline
bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28" "0,1,2,3"
hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
rbitfld.long 0x20 26.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count"
rbitfld.long 0x20 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count"
line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
rbitfld.long 0x24 28.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation" "0,1"
rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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rbitfld.long 0x28 12.--15. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3"
bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3"
line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect" "0,1"
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hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred" "0,1"
bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred" "0,1"
bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated" "0,1"
line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB" "0,1"
bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated" "0,1,2,3,4,5,6,7"
bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA" "0,1"
bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x30 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored" "0,1"
bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored" "0,1"
rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB" "0,1"
bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set" "0,1"
rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated" "0,1"
bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred" "0,1,2,3"
bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated" "0,1,2,3"
bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred" "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated" "0,1,2,3"
rbitfld.long 0x34 4.--7. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred" "0,1,2,3"
bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated" "0,1,2,3"
line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit" "0,1"
bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit" "0,1"
rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit" "0,1"
hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
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rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
line.long 0x3C "PCCTL,PWM-Chopper Control Register"
hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 1.--4. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
group.long 0x60++0x13
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
rbitfld.long 0x00 26.--31. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
rbitfld.long 0x00 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x00 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x00 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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bitfld.long 0x00 12.--15. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
hexmask.long.word 0x04 22.--31. 1. "Reserved3,Reserved"
bitfld.long 0x04 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
bitfld.long 0x04 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
bitfld.long 0x04 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
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bitfld.long 0x04 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
rbitfld.long 0x04 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x04 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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rbitfld.long 0x04 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x04 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x04 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x04 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
hexmask.long.word 0x08 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied"
hexmask.long.word 0x08 2.--15. 1. "Reserved,Reserved"
bitfld.long 0x08 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode" "0,1"
bitfld.long 0x08 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture" "0,1"
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated"
hexmask.long.word 0x0C 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter"
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1"
hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_ETPWMB (MSS ETPWMB Module Registers)"
base ad:0x53F78D00
group.long 0x00++0x3F
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
hexmask.long.word 0x00 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x00 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value" "0,1"
bitfld.long 0x00 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred" "0,1"
bitfld.long 0x00 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit" "0,1"
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bitfld.long 0x00 14.--15. "TBCTL_FREE,_SOFT,Emulation Mode Bits" "0,1,2,3"
bitfld.long 0x00 13. "TBCTL_PHSDIR,Phase Direction Bit" "0,1"
bitfld.long 0x00 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0" "0,1"
bitfld.long 0x00 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select" "0,1,2,3"
bitfld.long 0x00 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero" "0,1"
bitfld.long 0x00 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
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bitfld.long 0x00 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation" "0,1,2,3"
line.long 0x04 "TBPHS,Time-Base Phase Register"
hexmask.long.word 0x04 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal"
hexmask.long.word 0x04 0.--15. 1. "Reserved,Reserved"
line.long 0x08 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
hexmask.long.word 0x08 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter"
hexmask.long.word 0x08 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value"
line.long 0x0C "CMPCTL,Counter-Compare Control Register"
rbitfld.long 0x0C 26.--31. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
bitfld.long 0x0C 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made" "0,1"
rbitfld.long 0x0C 23. "Reserved3,Reserved" "0,1"
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bitfld.long 0x0C 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode" "0,1"
rbitfld.long 0x0C 21. "Reserved2,Reserved" "0,1"
bitfld.long 0x0C 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode" "0,1"
bitfld.long 0x0C 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1)" "0,1,2,3"
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bitfld.long 0x0C 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "0,1,2,3"
hexmask.long.word 0x0C 0.--15. 1. "Reserved1,Reserved"
line.long 0x10 "CMPA,Counter-Compare A Register"
hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR)"
hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
rbitfld.long 0x14 28.--31. "Reserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period" "0,1,2,3"
bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero" "0,1,2,3"
hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR)"
line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is.." "0,1,2,3"
bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low High High Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
rbitfld.long 0x18 12.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period" "0,1,2,3"
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bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero" "0,1,2,3"
line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled" "0,1"
hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28" "0,1,2,3"
bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28" "0,1,2,3"
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bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28" "0,1,2,3"
hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
rbitfld.long 0x20 26.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count"
rbitfld.long 0x20 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count"
line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
rbitfld.long 0x24 28.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation" "0,1"
rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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rbitfld.long 0x28 12.--15. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3"
bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3"
line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect" "0,1"
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hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred" "0,1"
bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred" "0,1"
bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated" "0,1"
line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB" "0,1"
bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated" "0,1,2,3,4,5,6,7"
bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA" "0,1"
bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x30 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored" "0,1"
bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored" "0,1"
rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB" "0,1"
bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set" "0,1"
rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated" "0,1"
bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred" "0,1,2,3"
bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated" "0,1,2,3"
bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred" "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated" "0,1,2,3"
rbitfld.long 0x34 4.--7. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred" "0,1,2,3"
bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated" "0,1,2,3"
line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit" "0,1"
bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit" "0,1"
rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit" "0,1"
hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
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rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
line.long 0x3C "PCCTL,PWM-Chopper Control Register"
hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 1.--4. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
group.long 0x60++0x13
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
rbitfld.long 0x00 26.--31. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
rbitfld.long 0x00 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x00 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x00 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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bitfld.long 0x00 12.--15. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
hexmask.long.word 0x04 22.--31. 1. "Reserved3,Reserved"
bitfld.long 0x04 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
bitfld.long 0x04 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
bitfld.long 0x04 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
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bitfld.long 0x04 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
rbitfld.long 0x04 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x04 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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rbitfld.long 0x04 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x04 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x04 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x04 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
hexmask.long.word 0x08 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied"
hexmask.long.word 0x08 2.--15. 1. "Reserved,Reserved"
bitfld.long 0x08 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode" "0,1"
bitfld.long 0x08 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture" "0,1"
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated"
hexmask.long.word 0x0C 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter"
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1"
hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_ETPWMC (MSS ETPWMC Module Registers)"
base ad:0x53F78E00
group.long 0x00++0x3F
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
hexmask.long.word 0x00 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x00 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value" "0,1"
bitfld.long 0x00 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred" "0,1"
bitfld.long 0x00 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit" "0,1"
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bitfld.long 0x00 14.--15. "TBCTL_FREE,_SOFT,Emulation Mode Bits" "0,1,2,3"
bitfld.long 0x00 13. "TBCTL_PHSDIR,Phase Direction Bit" "0,1"
bitfld.long 0x00 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0" "0,1"
bitfld.long 0x00 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select" "0,1,2,3"
bitfld.long 0x00 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero" "0,1"
bitfld.long 0x00 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
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bitfld.long 0x00 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation" "0,1,2,3"
line.long 0x04 "TBPHS,Time-Base Phase Register"
hexmask.long.word 0x04 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal"
hexmask.long.word 0x04 0.--15. 1. "Reserved,Reserved"
line.long 0x08 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
hexmask.long.word 0x08 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter"
hexmask.long.word 0x08 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value"
line.long 0x0C "CMPCTL,Counter-Compare Control Register"
rbitfld.long 0x0C 26.--31. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
bitfld.long 0x0C 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made" "0,1"
rbitfld.long 0x0C 23. "Reserved3,Reserved" "0,1"
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bitfld.long 0x0C 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode" "0,1"
rbitfld.long 0x0C 21. "Reserved2,Reserved" "0,1"
bitfld.long 0x0C 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode" "0,1"
bitfld.long 0x0C 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1)" "0,1,2,3"
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bitfld.long 0x0C 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "0,1,2,3"
hexmask.long.word 0x0C 0.--15. 1. "Reserved1,Reserved"
line.long 0x10 "CMPA,Counter-Compare A Register"
hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR)"
hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
rbitfld.long 0x14 28.--31. "Reserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period" "0,1,2,3"
bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero" "0,1,2,3"
hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR)"
line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is.." "0,1,2,3"
bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low High High Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
rbitfld.long 0x18 12.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period" "0,1,2,3"
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bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero" "0,1,2,3"
line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled" "0,1"
hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28" "0,1,2,3"
bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28" "0,1,2,3"
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bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28" "0,1,2,3"
hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
rbitfld.long 0x20 26.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count"
rbitfld.long 0x20 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count"
line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
rbitfld.long 0x24 28.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation" "0,1"
rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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rbitfld.long 0x28 12.--15. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3"
bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3"
line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect" "0,1"
newline
hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred" "0,1"
bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred" "0,1"
bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated" "0,1"
line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB" "0,1"
bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated" "0,1,2,3,4,5,6,7"
bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA" "0,1"
bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x30 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored" "0,1"
bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored" "0,1"
rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB" "0,1"
bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set" "0,1"
rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated" "0,1"
bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred" "0,1,2,3"
bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated" "0,1,2,3"
bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred" "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated" "0,1,2,3"
rbitfld.long 0x34 4.--7. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred" "0,1,2,3"
bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated" "0,1,2,3"
line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit" "0,1"
bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit" "0,1"
rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit" "0,1"
hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
newline
rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
line.long 0x3C "PCCTL,PWM-Chopper Control Register"
hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 1.--4. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
group.long 0x60++0x13
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
rbitfld.long 0x00 26.--31. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
rbitfld.long 0x00 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x00 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x00 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
newline
bitfld.long 0x00 12.--15. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
hexmask.long.word 0x04 22.--31. 1. "Reserved3,Reserved"
bitfld.long 0x04 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
bitfld.long 0x04 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
bitfld.long 0x04 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
newline
bitfld.long 0x04 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
rbitfld.long 0x04 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x04 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
newline
rbitfld.long 0x04 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x04 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x04 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
newline
bitfld.long 0x04 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
hexmask.long.word 0x08 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied"
hexmask.long.word 0x08 2.--15. 1. "Reserved,Reserved"
bitfld.long 0x08 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode" "0,1"
bitfld.long 0x08 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture" "0,1"
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated"
hexmask.long.word 0x0C 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter"
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1"
hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_GIO (MSS GIO Module Registers)"
base ad:0x52F7B400
group.long 0x00++0x03
line.long 0x00 "GIOGCR,GIO reset"
hexmask.long 0x00 1.--31. 1. "NU0,Reserved"
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "GIOPWDN,GIO power down mode register"
bitfld.long 0x00 0. "GIOPWDN,Writing to the GIOPWDN bit is only allowed in privilege mode" "Normal operation; clocks enabled to GIO..,Power-down mode"
group.long 0x08++0x14B
line.long 0x00 "GIOINTDET,Interrupt detection select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x00 24.--31. 1. "GIOINTDET_3,Interrupt detection select for pins GIOD[7:0]"
hexmask.long.byte 0x00 16.--23. 1. "GIOINTDET_2,Interrupt detection select for pins GIOC[7:0]"
hexmask.long.byte 0x00 8.--15. 1. "GIOINTDET_1,Interrupt detection select for pins GIOB[7:0]"
hexmask.long.byte 0x00 0.--7. 1. "GIOINTDET_0,Interrupt detection select for pins GIOA[7:0]"
line.long 0x04 "GIOPOL,Interrupt polarity select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x04 24.--31. 1. "GIOPOL_3,Interrupt polarity select for pins GIOD[7:0]"
hexmask.long.byte 0x04 16.--23. 1. "GIOPOL_2,Interrupt polarity select for pins GIOC[7:0]"
hexmask.long.byte 0x04 8.--15. 1. "GIOPOL_1,Interrupt polarity select for pins GIOB[7:0]"
hexmask.long.byte 0x04 0.--7. 1. "GIOPOL_0,Interrupt polarity select for pins GIOA[7:0]"
line.long 0x08 "GIOENASET,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x08 24.--31. 1. "GIOENASET_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x08 16.--23. 1. "GIOENASET_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x08 8.--15. 1. "GIOENASET_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x08 0.--7. 1. "GIOENASET_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x0C "GIOENACLR,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x0C 24.--31. 1. "GIOENACLR_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x0C 16.--23. 1. "GIOENACLR_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x0C 8.--15. 1. "GIOENACLR_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x0C 0.--7. 1. "GIOENACLR_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x10 "GIOLVLSET,GIO high priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x10 24.--31. 1. "GIOLVLSET_3,GIO high priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x10 16.--23. 1. "GIOLVLSET_2,GIO high priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x10 8.--15. 1. "GIOLVLSET_1,GIO high priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x10 0.--7. 1. "GIOLVLSET_0,GIO high priority interrupt for pins GIOA[7:0]"
line.long 0x14 "GIOLVLCLR,GIO low priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x14 24.--31. 1. "GIOLVLCLR_3,GIO low priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x14 16.--23. 1. "GIOLVLCLR_2,GIO low priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x14 8.--15. 1. "GIOLVLCLR_1,GIO low priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x14 0.--7. 1. "GIOLVLCLR_0,GIO low priority interrupt for pins GIOA[7:0]"
line.long 0x18 "GIOFLG,GIO flag for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x18 24.--31. 1. "GIOFLG_3,GIO flag for pins GIOD[7:0]"
hexmask.long.byte 0x18 16.--23. 1. "GIOFLG_2,GIO flag for pins GIOC[7:0]"
hexmask.long.byte 0x18 8.--15. 1. "GIOFLG_1,GIO flag for pins GIOB[7:0]"
hexmask.long.byte 0x18 0.--7. 1. "GIOFLG_0,GIO flag for pins GIOA[7:0]"
line.long 0x1C "GIOOFFA,Index bits for currently pending high-priority interrupt Register A"
hexmask.long 0x1C 6.--31. 1. "NU1,Reserved"
bitfld.long 0x1C 0.--5. "GIOOFFA,Index bits for currently pending high-priority interrupt Register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "GIOOFFB,Index bits for currently pending high-priority interrupt Register B"
hexmask.long 0x20 6.--31. 1. "NU2,Reserved"
bitfld.long 0x20 0.--5. "GIOOFFB,Index bits for currently pending high-priority interrupt Register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "GIOEMUA,GIO emulation register A"
hexmask.long 0x24 6.--31. 1. "NU3,Reserved"
bitfld.long 0x24 0.--5. "GIOEMUA,GIO emulation register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "GIOEMUB,GIO emulation register B"
hexmask.long 0x28 6.--31. 1. "NU4,Reserved"
bitfld.long 0x28 0.--5. "GIOEMUB,GIO emulation register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "GIODIRA,GIO data direction of pins in Port A"
hexmask.long.tbyte 0x2C 8.--31. 1. "NU5,Reserved"
hexmask.long.byte 0x2C 0.--7. 1. "GIODIRA,GIO data direction of pins in Port A"
line.long 0x30 "GIODINA,GIO data input for pins in port A"
hexmask.long.tbyte 0x30 8.--31. 1. "NU11,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "GIODINA,GIO data input for pins in port A"
line.long 0x34 "GIODOUTA,GIO data output for pins in port A"
hexmask.long.tbyte 0x34 8.--31. 1. "NU17,Reserved"
hexmask.long.byte 0x34 0.--7. 1. "GIODOUTA,GIO data output for pins in port A"
line.long 0x38 "GIOSETA,GIO data set for port A"
hexmask.long.tbyte 0x38 8.--31. 1. "NU23,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "GIODSETA,GIO data set for port A"
line.long 0x3C "GIOCLRA,GIO data clear for port A"
hexmask.long.tbyte 0x3C 8.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x3C 0.--7. 1. "GIODCLRA,GIO data clear for port A"
line.long 0x40 "GIOPDRA,GIO open drain for port A"
hexmask.long.tbyte 0x40 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x40 0.--7. 1. "GIOPDRA,GIO open drain for port A"
line.long 0x44 "GIOPULDISA,GIO pul disable for port A"
hexmask.long.tbyte 0x44 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x44 0.--7. 1. "GIOPULDISA,GIO pull disable for port A"
line.long 0x48 "GIOPSLA,GIO pul select for port A"
hexmask.long.tbyte 0x48 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x48 0.--7. 1. "GIOPSLA,GIO pull select for port A"
line.long 0x4C "GIODIRB,GIO data direction of pins in Port B"
hexmask.long.tbyte 0x4C 8.--31. 1. "NU6,Reserved"
hexmask.long.byte 0x4C 0.--7. 1. "GIODIRB,GIO data direction of pins in Port B"
line.long 0x50 "GIODINB,GIO data input for pins in port B"
hexmask.long.tbyte 0x50 8.--31. 1. "NU12,Reserved"
hexmask.long.byte 0x50 0.--7. 1. "GIODINB,GIO data input for pins in port B"
line.long 0x54 "GIODOUTB,GIO data output for pins in port B"
hexmask.long.tbyte 0x54 8.--31. 1. "NU18,Reserved"
hexmask.long.byte 0x54 0.--7. 1. "GIODOUTB,GIO data output for pins in port B"
line.long 0x58 "GIOSETB,GIO data set for port B"
hexmask.long.tbyte 0x58 8.--31. 1. "NU24,Reserved"
hexmask.long.byte 0x58 0.--7. 1. "GIODSETB,GIO data set for port B"
line.long 0x5C "GIOCLRB,GIO data clear for port B"
hexmask.long.tbyte 0x5C 8.--31. 1. "NU30,Reserved"
hexmask.long.byte 0x5C 0.--7. 1. "GIODCLRB,GIO data clear for port B"
line.long 0x60 "GIOPDRB,GIO open drain for port B"
hexmask.long.tbyte 0x60 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x60 0.--7. 1. "GIOPDRB,GIO open drain for port B"
line.long 0x64 "GIOPULDISB,GIO pul disable for port B"
hexmask.long.tbyte 0x64 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x64 0.--7. 1. "GIOPULDISB,GIO pull disable for port B"
line.long 0x68 "GIOPSLB,GIO pul select for port B"
hexmask.long.tbyte 0x68 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x68 0.--7. 1. "GIOPSLB,GIO pull select for port B"
line.long 0x6C "GIODIRC,GIO data direction of pins in Port C"
hexmask.long.tbyte 0x6C 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x6C 0.--7. 1. "GIODIRC,GIO data direction of pins in Port C"
line.long 0x70 "GIODINC,GIO data input for pins in port C"
hexmask.long.tbyte 0x70 8.--31. 1. "NU13,Reserved"
hexmask.long.byte 0x70 0.--7. 1. "GIODINC,GIO data input for pins in port C"
line.long 0x74 "GIODOUTC,GIO data output for pins in port C"
hexmask.long.tbyte 0x74 8.--31. 1. "NU19,Reserved"
hexmask.long.byte 0x74 0.--7. 1. "GIODOUTC,GIO data output for pins in port C"
line.long 0x78 "GIOSETC,GIO data set for port C"
hexmask.long.tbyte 0x78 8.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x78 0.--7. 1. "GIODSETC,GIO data set for port C"
line.long 0x7C "GIOCLRC,GIO data clear for port C"
hexmask.long.tbyte 0x7C 8.--31. 1. "NU31,Reserved"
hexmask.long.byte 0x7C 0.--7. 1. "GIODCLRC,GIO data clear for port C"
line.long 0x80 "GIOPDRC,GIO open drain for port C"
hexmask.long.tbyte 0x80 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x80 0.--7. 1. "GIOPDRC,GIO open drain for port C"
line.long 0x84 "GIOPULDISC,GIO pul disable for port C"
hexmask.long.tbyte 0x84 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x84 0.--7. 1. "GIOPULDISC,GIO pull disable for port C"
line.long 0x88 "GIOPSLC,GIO pul select for port C"
hexmask.long.tbyte 0x88 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x88 0.--7. 1. "GIOPSLC,GIO pull select for port C"
line.long 0x8C "GIODIRD,GIO data direction of pins in Port D"
hexmask.long.tbyte 0x8C 8.--31. 1. "NU8,Reserved"
hexmask.long.byte 0x8C 0.--7. 1. "GIODIRD,GIO data direction of pins in Port D"
line.long 0x90 "GIODIND,GIO data input for pins in port D"
hexmask.long.tbyte 0x90 8.--31. 1. "NU14,Reserved"
hexmask.long.byte 0x90 0.--7. 1. "GIODIND,GIO data input for pins in port D"
line.long 0x94 "GIODOUTD,GIO data output for pins in port D"
hexmask.long.tbyte 0x94 8.--31. 1. "NU20,Reserved"
hexmask.long.byte 0x94 0.--7. 1. "GIODOUTD,GIO data output for pins in port D"
line.long 0x98 "GIOSETD,GIO data set for port D"
hexmask.long.tbyte 0x98 8.--31. 1. "NU26,Reserved"
hexmask.long.byte 0x98 0.--7. 1. "GIODSETD,GIO data set for port D"
line.long 0x9C "GIOCLRD,GIO data clear for port D"
hexmask.long.tbyte 0x9C 8.--31. 1. "NU32,Reserved"
hexmask.long.byte 0x9C 0.--7. 1. "GIODCLRD,GIO data clear for port D"
line.long 0xA0 "GIOPDRD,GIO open drain for port D"
hexmask.long.tbyte 0xA0 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA0 0.--7. 1. "GIOPDRD,GIO open drain for port D"
line.long 0xA4 "GIOPULDISD,GIO pul disable for port D"
hexmask.long.tbyte 0xA4 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA4 0.--7. 1. "GIOPULDISD,GIO pull disable for port D"
line.long 0xA8 "GIOPSLD,GIO pul select for port D"
hexmask.long.tbyte 0xA8 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA8 0.--7. 1. "GIOPSLD,GIO pull select for port D"
line.long 0xAC "GIODIRE,GIO data direction of pins in Port E"
hexmask.long.tbyte 0xAC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xAC 0.--7. 1. "GIODIRE,GIO data direction of pins in Port E"
line.long 0xB0 "GIODINE,GIO data input for pins in port E"
hexmask.long.tbyte 0xB0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xB0 0.--7. 1. "GIODINE,GIO data input for pins in port E"
line.long 0xB4 "GIODOUTE,GIO data output for pins in port E"
hexmask.long.tbyte 0xB4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xB4 0.--7. 1. "GIODOUTE,GIO data output for pins in port E"
line.long 0xB8 "GIOSETE,GIO data set for port E"
hexmask.long.tbyte 0xB8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xB8 0.--7. 1. "GIODSETE,GIO data set for port E"
line.long 0xBC "GIOCLRE,GIO data clear for port E"
hexmask.long.tbyte 0xBC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xBC 0.--7. 1. "GIODCLRE,GIO data clear for port E"
line.long 0xC0 "GIOPDRE,GIO open drain for port E"
hexmask.long.tbyte 0xC0 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC0 0.--7. 1. "GIOPDRE,GIO open drain for port E"
line.long 0xC4 "GIOPULDISE,GIO pul disable for port E"
hexmask.long.tbyte 0xC4 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC4 0.--7. 1. "GIOPULDISE,GIO pull disable for port E"
line.long 0xC8 "GIOPSLE,GIO pul select for port E"
hexmask.long.tbyte 0xC8 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC8 0.--7. 1. "GIOPSLE,GIO pull select for port E"
line.long 0xCC "GIODIRF,GIO data direction of pins in Port F"
hexmask.long.tbyte 0xCC 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0xCC 0.--7. 1. "GIODIRF,GIO data direction of pins in Port F"
line.long 0xD0 "GIODINF,GIO data input for pins in Port F"
hexmask.long.tbyte 0xD0 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0xD0 0.--7. 1. "GIODINF,GIO data input for pins in port F"
line.long 0xD4 "GIODOUTF,GIO data output for pins in Port F"
hexmask.long.tbyte 0xD4 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0xD4 0.--7. 1. "GIODOUTF,GIO data output for pins in port F"
line.long 0xD8 "GIOSETF,GIO data set for Port F"
hexmask.long.tbyte 0xD8 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0xD8 0.--7. 1. "GIODSETF,GIO data set for port F"
line.long 0xDC "GIOCLRF,GIO data clear for Port F"
hexmask.long.tbyte 0xDC 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0xDC 0.--7. 1. "GIODCLRF,GIO data clear for port F"
line.long 0xE0 "GIOPDRF,GIO open drain for Port F"
hexmask.long.tbyte 0xE0 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE0 0.--7. 1. "GIOPDRF,GIO open drain for port F"
line.long 0xE4 "GIOPULDISF,GIO pul disable for port F"
hexmask.long.tbyte 0xE4 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE4 0.--7. 1. "GIOPULDISF,GIO pull disable for port F"
line.long 0xE8 "GIOPSLF,GIO pul select for port F"
hexmask.long.tbyte 0xE8 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE8 0.--7. 1. "GIOPSLF,GIO pull select for port F"
line.long 0xEC "GIODIRG,GIO data direction of pins in Port G"
hexmask.long.tbyte 0xEC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xEC 0.--7. 1. "GIODIRG,GIO data direction of pins in Port G"
line.long 0xF0 "GIODING,GIO data input for pins in port G"
hexmask.long.tbyte 0xF0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xF0 0.--7. 1. "GIODING,GIO data input for pins in port G"
line.long 0xF4 "GIODOUTG,GIO data output for pins in port G"
hexmask.long.tbyte 0xF4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xF4 0.--7. 1. "GIODOUTG,GIO data output for pins in port G"
line.long 0xF8 "GIOSETG,GIO data set for port G"
hexmask.long.tbyte 0xF8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xF8 0.--7. 1. "GIODSETG,GIO data set for port G"
line.long 0xFC "GIOCLRG,GIO data clear for port G"
hexmask.long.tbyte 0xFC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xFC 0.--7. 1. "GIODCLRG,GIO data clear for port G"
line.long 0x100 "GIOPDRG,GIO open drain for port G"
hexmask.long.tbyte 0x100 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x100 0.--7. 1. "GIOPDRG,GIO open drain for port G"
line.long 0x104 "GIOPULDISG,GIO pul disable for port G"
hexmask.long.tbyte 0x104 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x104 0.--7. 1. "GIOPULDISG,GIO pull disable for port G"
line.long 0x108 "GIOPSLG,GIO pul select for port G"
hexmask.long.tbyte 0x108 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x108 0.--7. 1. "GIOPSLG,GIO pull select for port G"
line.long 0x10C "GIODIRH,GIO data direction of pins in Port H"
hexmask.long.tbyte 0x10C 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0x10C 0.--7. 1. "GIODIRH,GIO data direction of pins in Port H"
line.long 0x110 "GIODINH,GIO data input for pins in Port H"
hexmask.long.tbyte 0x110 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x110 0.--7. 1. "GIODINH,GIO data input for pins in port H"
line.long 0x114 "GIODOUTH,GIO data output for pins in Port H"
hexmask.long.tbyte 0x114 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0x114 0.--7. 1. "GIODOUTH,GIO data output for pins in port H"
line.long 0x118 "GIOSETH,GIO data set for Port H"
hexmask.long.tbyte 0x118 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0x118 0.--7. 1. "GIODSETH,GIO data set for port H"
line.long 0x11C "GIOCLRH,GIO data clear for Port H"
hexmask.long.tbyte 0x11C 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0x11C 0.--7. 1. "GIODCLRH,GIO data clear for port H"
line.long 0x120 "GIOPDRH,GIO open drain for Port H"
hexmask.long.tbyte 0x120 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x120 0.--7. 1. "GIOPDRH,GIO open drain for port H"
line.long 0x124 "GIOPULDISH,GIO pul disable for port H"
hexmask.long.tbyte 0x124 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x124 0.--7. 1. "GIOPULDISH,GIO pull disable for port H"
line.long 0x128 "GIOPSLH,GIO pul select for port H"
hexmask.long.tbyte 0x128 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x128 0.--7. 1. "GIOPSLH,GIO pull select for port H"
line.long 0x12C "GIOSRCA,GIO slew rate select for port A"
hexmask.long.tbyte 0x12C 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x12C 0.--7. 1. "GIOSRCA,GIO slew rate control for port A"
line.long 0x130 "GIOSRCB,GIO slew rate select for port B"
hexmask.long.tbyte 0x130 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x130 0.--7. 1. "GIOSRCB,GIO slew rate control for port B"
line.long 0x134 "GIOSRCC,GIO slew rate select for port C"
hexmask.long.tbyte 0x134 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x134 0.--7. 1. "GIOSRCC,GIO slew rate control for port C"
line.long 0x138 "GIOSRCD,GIO slew rate select for port D"
hexmask.long.tbyte 0x138 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x138 0.--7. 1. "GIOSRCD,GIO slew rate control for port D"
line.long 0x13C "GIOSRCE,GIO slew rate select for port E"
hexmask.long.tbyte 0x13C 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x13C 0.--7. 1. "GIOSRCE,GIO slew rate control for port E"
line.long 0x140 "GIOSRCF,GIO slew rate select for port F"
hexmask.long.tbyte 0x140 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x140 0.--7. 1. "GIOSRCF,GIO slew rate control for port F"
line.long 0x144 "GIOSRCG,GIO slew rate select for port G"
hexmask.long.tbyte 0x144 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x144 0.--7. 1. "GIOSRCG,GIO slew rate control for port G"
line.long 0x148 "GIOSRCH,GIO slew rate select for port H"
hexmask.long.tbyte 0x148 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x148 0.--7. 1. "GIOSRCH,GIO slew rate control for port H"
width 0x0B
tree.end
tree "MSS_GPADC_DATA_RAM (MSS GPADC DATA RAM Module Registers)"
base ad:0xC5030000
group.long 0x00++0x03
line.long 0x00 "START,"
group.long 0x7FC++0x03
line.long 0x00 "END,"
width 0x0B
tree.end
tree "MSS_GPADC_PKT_RAM (MSS GPADC PKT RAM Module Registers)"
base ad:0x530C0000
group.long 0x00++0x7FF
line.long 0x00 "INST0_0,"
line.long 0x04 "INST0_1,"
hexmask.long.byte 0x04 25.--31. 1. "NU2,"
rbitfld.long 0x04 24. "NU1," "0,1"
bitfld.long 0x04 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x04 16.--22. 1. "SKIP_SAMPLES,Number of GPADC clock cycles to skip before collecting valid samples"
hexmask.long.byte 0x04 8.--15. 1. "COLLECT_SAMPLES,Number of GPADC samples to collect"
hexmask.long.byte 0x04 0.--7. 1. "PARAM,Parameter(input to one hot encoding) to be passed to analog"
line.long 0x08 "INST1_0,"
line.long 0x0C "INST1_1,"
hexmask.long.byte 0x0C 25.--31. 1. "NU2,"
rbitfld.long 0x0C 24. "NU1," "0,1"
bitfld.long 0x0C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x0C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x0C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x0C 0.--7. 1. "PARAM,"
line.long 0x10 "INST2_0,"
line.long 0x14 "INST2_1,"
hexmask.long.byte 0x14 25.--31. 1. "NU2,"
rbitfld.long 0x14 24. "NU1," "0,1"
bitfld.long 0x14 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x14 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x14 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x14 0.--7. 1. "PARAM,"
line.long 0x18 "INST3_0,"
line.long 0x1C "INST3_1,"
hexmask.long.byte 0x1C 25.--31. 1. "NU2,"
rbitfld.long 0x1C 24. "NU1," "0,1"
bitfld.long 0x1C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1C 0.--7. 1. "PARAM,"
line.long 0x20 "INST4_0,"
line.long 0x24 "INST4_1,"
hexmask.long.byte 0x24 25.--31. 1. "NU2,"
rbitfld.long 0x24 24. "NU1," "0,1"
bitfld.long 0x24 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x24 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x24 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x24 0.--7. 1. "PARAM,"
line.long 0x28 "INST5_0,"
line.long 0x2C "INST5_1,"
hexmask.long.byte 0x2C 25.--31. 1. "NU2,"
rbitfld.long 0x2C 24. "NU1," "0,1"
bitfld.long 0x2C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2C 0.--7. 1. "PARAM,"
line.long 0x30 "INST6_0,"
line.long 0x34 "INST6_1,"
hexmask.long.byte 0x34 25.--31. 1. "NU2,"
rbitfld.long 0x34 24. "NU1," "0,1"
bitfld.long 0x34 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x34 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x34 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x34 0.--7. 1. "PARAM,"
line.long 0x38 "INST7_0,"
line.long 0x3C "INST7_1,"
hexmask.long.byte 0x3C 25.--31. 1. "NU2,"
rbitfld.long 0x3C 24. "NU1," "0,1"
bitfld.long 0x3C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3C 0.--7. 1. "PARAM,"
line.long 0x40 "INST8_0,"
line.long 0x44 "INST8_1,"
hexmask.long.byte 0x44 25.--31. 1. "NU2,"
rbitfld.long 0x44 24. "NU1," "0,1"
bitfld.long 0x44 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x44 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x44 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x44 0.--7. 1. "PARAM,"
line.long 0x48 "INST9_0,"
line.long 0x4C "INST9_1,"
hexmask.long.byte 0x4C 25.--31. 1. "NU2,"
rbitfld.long 0x4C 24. "NU1," "0,1"
bitfld.long 0x4C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4C 0.--7. 1. "PARAM,"
line.long 0x50 "INST10_0,"
line.long 0x54 "INST10_1,"
hexmask.long.byte 0x54 25.--31. 1. "NU2,"
rbitfld.long 0x54 24. "NU1," "0,1"
bitfld.long 0x54 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x54 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x54 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x54 0.--7. 1. "PARAM,"
line.long 0x58 "INST11_0,"
line.long 0x5C "INST11_1,"
hexmask.long.byte 0x5C 25.--31. 1. "NU2,"
rbitfld.long 0x5C 24. "NU1," "0,1"
bitfld.long 0x5C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5C 0.--7. 1. "PARAM,"
line.long 0x60 "INST12_0,"
line.long 0x64 "INST12_1,"
hexmask.long.byte 0x64 25.--31. 1. "NU2,"
rbitfld.long 0x64 24. "NU1," "0,1"
bitfld.long 0x64 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x64 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x64 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x64 0.--7. 1. "PARAM,"
line.long 0x68 "INST13_0,"
line.long 0x6C "INST13_1,"
hexmask.long.byte 0x6C 25.--31. 1. "NU2,"
rbitfld.long 0x6C 24. "NU1," "0,1"
bitfld.long 0x6C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6C 0.--7. 1. "PARAM,"
line.long 0x70 "INST14_0,"
line.long 0x74 "INST14_1,"
hexmask.long.byte 0x74 25.--31. 1. "NU2,"
rbitfld.long 0x74 24. "NU1," "0,1"
bitfld.long 0x74 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x74 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x74 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x74 0.--7. 1. "PARAM,"
line.long 0x78 "INST15_0,"
line.long 0x7C "INST15_1,"
hexmask.long.byte 0x7C 25.--31. 1. "NU2,"
rbitfld.long 0x7C 24. "NU1," "0,1"
bitfld.long 0x7C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7C 0.--7. 1. "PARAM,"
line.long 0x80 "INST16_0,"
line.long 0x84 "INST16_1,"
hexmask.long.byte 0x84 25.--31. 1. "NU2,"
rbitfld.long 0x84 24. "NU1," "0,1"
bitfld.long 0x84 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x84 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x84 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x84 0.--7. 1. "PARAM,"
line.long 0x88 "INST17_0,"
line.long 0x8C "INST17_1,"
hexmask.long.byte 0x8C 25.--31. 1. "NU2,"
rbitfld.long 0x8C 24. "NU1," "0,1"
bitfld.long 0x8C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x8C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x8C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x8C 0.--7. 1. "PARAM,"
line.long 0x90 "INST18_0,"
line.long 0x94 "INST18_1,"
hexmask.long.byte 0x94 25.--31. 1. "NU2,"
rbitfld.long 0x94 24. "NU1," "0,1"
bitfld.long 0x94 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x94 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x94 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x94 0.--7. 1. "PARAM,"
line.long 0x98 "INST19_0,"
line.long 0x9C "INST19_1,"
hexmask.long.byte 0x9C 25.--31. 1. "NU2,"
rbitfld.long 0x9C 24. "NU1," "0,1"
bitfld.long 0x9C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x9C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x9C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x9C 0.--7. 1. "PARAM,"
line.long 0xA0 "INST20_0,"
line.long 0xA4 "INST20_1,"
hexmask.long.byte 0xA4 25.--31. 1. "NU2,"
rbitfld.long 0xA4 24. "NU1," "0,1"
bitfld.long 0xA4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xA4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xA4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xA4 0.--7. 1. "PARAM,"
line.long 0xA8 "INST21_0,"
line.long 0xAC "INST21_1,"
hexmask.long.byte 0xAC 25.--31. 1. "NU2,"
rbitfld.long 0xAC 24. "NU1," "0,1"
bitfld.long 0xAC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xAC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xAC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xAC 0.--7. 1. "PARAM,"
line.long 0xB0 "INST22_0,"
line.long 0xB4 "INST22_1,"
hexmask.long.byte 0xB4 25.--31. 1. "NU2,"
rbitfld.long 0xB4 24. "NU1," "0,1"
bitfld.long 0xB4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xB4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xB4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xB4 0.--7. 1. "PARAM,"
line.long 0xB8 "INST23_0,"
line.long 0xBC "INST23_1,"
hexmask.long.byte 0xBC 25.--31. 1. "NU2,"
rbitfld.long 0xBC 24. "NU1," "0,1"
bitfld.long 0xBC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xBC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xBC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xBC 0.--7. 1. "PARAM,"
line.long 0xC0 "INST24_0,"
line.long 0xC4 "INST24_1,"
hexmask.long.byte 0xC4 25.--31. 1. "NU2,"
rbitfld.long 0xC4 24. "NU1," "0,1"
bitfld.long 0xC4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xC4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xC4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xC4 0.--7. 1. "PARAM,"
line.long 0xC8 "INST25_0,"
line.long 0xCC "INST25_1,"
hexmask.long.byte 0xCC 25.--31. 1. "NU2,"
rbitfld.long 0xCC 24. "NU1," "0,1"
bitfld.long 0xCC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xCC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xCC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xCC 0.--7. 1. "PARAM,"
line.long 0xD0 "INST26_0,"
line.long 0xD4 "INST26_1,"
hexmask.long.byte 0xD4 25.--31. 1. "NU2,"
rbitfld.long 0xD4 24. "NU1," "0,1"
bitfld.long 0xD4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xD4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xD4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xD4 0.--7. 1. "PARAM,"
line.long 0xD8 "INST27_0,"
line.long 0xDC "INST27_1,"
hexmask.long.byte 0xDC 25.--31. 1. "NU2,"
rbitfld.long 0xDC 24. "NU1," "0,1"
bitfld.long 0xDC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xDC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xDC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xDC 0.--7. 1. "PARAM,"
line.long 0xE0 "INST28_0,"
line.long 0xE4 "INST28_1,"
hexmask.long.byte 0xE4 25.--31. 1. "NU2,"
rbitfld.long 0xE4 24. "NU1," "0,1"
bitfld.long 0xE4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xE4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xE4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xE4 0.--7. 1. "PARAM,"
line.long 0xE8 "INST29_0,"
line.long 0xEC "INST29_1,"
hexmask.long.byte 0xEC 25.--31. 1. "NU2,"
rbitfld.long 0xEC 24. "NU1," "0,1"
bitfld.long 0xEC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xEC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xEC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xEC 0.--7. 1. "PARAM,"
line.long 0xF0 "INST30_0,"
line.long 0xF4 "INST30_1,"
hexmask.long.byte 0xF4 25.--31. 1. "NU2,"
rbitfld.long 0xF4 24. "NU1," "0,1"
bitfld.long 0xF4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xF4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xF4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xF4 0.--7. 1. "PARAM,"
line.long 0xF8 "INST31_0,"
line.long 0xFC "INST31_1,"
hexmask.long.byte 0xFC 25.--31. 1. "NU2,"
rbitfld.long 0xFC 24. "NU1," "0,1"
bitfld.long 0xFC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xFC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xFC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xFC 0.--7. 1. "PARAM,"
line.long 0x100 "INST32_0,"
line.long 0x104 "INST32_1,"
hexmask.long.byte 0x104 25.--31. 1. "NU2,"
rbitfld.long 0x104 24. "NU1," "0,1"
bitfld.long 0x104 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x104 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x104 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x104 0.--7. 1. "PARAM,"
line.long 0x108 "INST33_0,"
line.long 0x10C "INST33_1,"
hexmask.long.byte 0x10C 25.--31. 1. "NU2,"
rbitfld.long 0x10C 24. "NU1," "0,1"
bitfld.long 0x10C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x10C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x10C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x10C 0.--7. 1. "PARAM,"
line.long 0x110 "INST34_0,"
line.long 0x114 "INST34_1,"
hexmask.long.byte 0x114 25.--31. 1. "NU2,"
rbitfld.long 0x114 24. "NU1," "0,1"
bitfld.long 0x114 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x114 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x114 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x114 0.--7. 1. "PARAM,"
line.long 0x118 "INST35_0,"
line.long 0x11C "INST35_1,"
hexmask.long.byte 0x11C 25.--31. 1. "NU2,"
rbitfld.long 0x11C 24. "NU1," "0,1"
bitfld.long 0x11C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x11C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x11C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x11C 0.--7. 1. "PARAM,"
line.long 0x120 "INST36_0,"
line.long 0x124 "INST36_1,"
hexmask.long.byte 0x124 25.--31. 1. "NU2,"
rbitfld.long 0x124 24. "NU1," "0,1"
bitfld.long 0x124 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x124 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x124 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x124 0.--7. 1. "PARAM,"
line.long 0x128 "INST37_0,"
line.long 0x12C "INST37_1,"
hexmask.long.byte 0x12C 25.--31. 1. "NU2,"
rbitfld.long 0x12C 24. "NU1," "0,1"
bitfld.long 0x12C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x12C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x12C 0.--7. 1. "PARAM,"
line.long 0x130 "INST38_0,"
line.long 0x134 "INST38_1,"
hexmask.long.byte 0x134 25.--31. 1. "NU2,"
rbitfld.long 0x134 24. "NU1," "0,1"
bitfld.long 0x134 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x134 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x134 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x134 0.--7. 1. "PARAM,"
line.long 0x138 "INST39_0,"
line.long 0x13C "INST39_1,"
hexmask.long.byte 0x13C 25.--31. 1. "NU2,"
rbitfld.long 0x13C 24. "NU1," "0,1"
bitfld.long 0x13C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x13C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x13C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x13C 0.--7. 1. "PARAM,"
line.long 0x140 "INST40_0,"
line.long 0x144 "INST40_1,"
hexmask.long.byte 0x144 25.--31. 1. "NU2,"
rbitfld.long 0x144 24. "NU1," "0,1"
bitfld.long 0x144 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x144 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x144 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x144 0.--7. 1. "PARAM,"
line.long 0x148 "INST41_0,"
line.long 0x14C "INST41_1,"
hexmask.long.byte 0x14C 25.--31. 1. "NU2,"
rbitfld.long 0x14C 24. "NU1," "0,1"
bitfld.long 0x14C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x14C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x14C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x14C 0.--7. 1. "PARAM,"
line.long 0x150 "INST42_0,"
line.long 0x154 "INST42_1,"
hexmask.long.byte 0x154 25.--31. 1. "NU2,"
rbitfld.long 0x154 24. "NU1," "0,1"
bitfld.long 0x154 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x154 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x154 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x154 0.--7. 1. "PARAM,"
line.long 0x158 "INST43_0,"
line.long 0x15C "INST43_1,"
hexmask.long.byte 0x15C 25.--31. 1. "NU2,"
rbitfld.long 0x15C 24. "NU1," "0,1"
bitfld.long 0x15C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x15C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x15C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x15C 0.--7. 1. "PARAM,"
line.long 0x160 "INST44_0,"
line.long 0x164 "INST44_1,"
hexmask.long.byte 0x164 25.--31. 1. "NU2,"
rbitfld.long 0x164 24. "NU1," "0,1"
bitfld.long 0x164 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x164 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x164 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x164 0.--7. 1. "PARAM,"
line.long 0x168 "INST45_0,"
line.long 0x16C "INST45_1,"
hexmask.long.byte 0x16C 25.--31. 1. "NU2,"
rbitfld.long 0x16C 24. "NU1," "0,1"
bitfld.long 0x16C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x16C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x16C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x16C 0.--7. 1. "PARAM,"
line.long 0x170 "INST46_0,"
line.long 0x174 "INST46_1,"
hexmask.long.byte 0x174 25.--31. 1. "NU2,"
rbitfld.long 0x174 24. "NU1," "0,1"
bitfld.long 0x174 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x174 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x174 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x174 0.--7. 1. "PARAM,"
line.long 0x178 "INST47_0,"
line.long 0x17C "INST47_1,"
hexmask.long.byte 0x17C 25.--31. 1. "NU2,"
rbitfld.long 0x17C 24. "NU1," "0,1"
bitfld.long 0x17C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x17C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x17C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x17C 0.--7. 1. "PARAM,"
line.long 0x180 "INST48_0,"
line.long 0x184 "INST48_1,"
hexmask.long.byte 0x184 25.--31. 1. "NU2,"
rbitfld.long 0x184 24. "NU1," "0,1"
bitfld.long 0x184 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x184 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x184 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x184 0.--7. 1. "PARAM,"
line.long 0x188 "INST49_0,"
line.long 0x18C "INST49_1,"
hexmask.long.byte 0x18C 25.--31. 1. "NU2,"
rbitfld.long 0x18C 24. "NU1," "0,1"
bitfld.long 0x18C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x18C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x18C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x18C 0.--7. 1. "PARAM,"
line.long 0x190 "INST50_0,"
line.long 0x194 "INST50_1,"
hexmask.long.byte 0x194 25.--31. 1. "NU2,"
rbitfld.long 0x194 24. "NU1," "0,1"
bitfld.long 0x194 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x194 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x194 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x194 0.--7. 1. "PARAM,"
line.long 0x198 "INST51_0,"
line.long 0x19C "INST51_1,"
hexmask.long.byte 0x19C 25.--31. 1. "NU2,"
rbitfld.long 0x19C 24. "NU1," "0,1"
bitfld.long 0x19C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x19C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x19C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x19C 0.--7. 1. "PARAM,"
line.long 0x1A0 "INST52_0,"
line.long 0x1A4 "INST52_1,"
hexmask.long.byte 0x1A4 25.--31. 1. "NU2,"
rbitfld.long 0x1A4 24. "NU1," "0,1"
bitfld.long 0x1A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1A4 0.--7. 1. "PARAM,"
line.long 0x1A8 "INST53_0,"
line.long 0x1AC "INST53_1,"
hexmask.long.byte 0x1AC 25.--31. 1. "NU2,"
rbitfld.long 0x1AC 24. "NU1," "0,1"
bitfld.long 0x1AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1AC 0.--7. 1. "PARAM,"
line.long 0x1B0 "INST54_0,"
line.long 0x1B4 "INST54_1,"
hexmask.long.byte 0x1B4 25.--31. 1. "NU2,"
rbitfld.long 0x1B4 24. "NU1," "0,1"
bitfld.long 0x1B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1B4 0.--7. 1. "PARAM,"
line.long 0x1B8 "INST55_0,"
line.long 0x1BC "INST55_1,"
hexmask.long.byte 0x1BC 25.--31. 1. "NU2,"
rbitfld.long 0x1BC 24. "NU1," "0,1"
bitfld.long 0x1BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1BC 0.--7. 1. "PARAM,"
line.long 0x1C0 "INST56_0,"
line.long 0x1C4 "INST56_1,"
hexmask.long.byte 0x1C4 25.--31. 1. "NU2,"
rbitfld.long 0x1C4 24. "NU1," "0,1"
bitfld.long 0x1C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1C4 0.--7. 1. "PARAM,"
line.long 0x1C8 "INST57_0,"
line.long 0x1CC "INST57_1,"
hexmask.long.byte 0x1CC 25.--31. 1. "NU2,"
rbitfld.long 0x1CC 24. "NU1," "0,1"
bitfld.long 0x1CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1CC 0.--7. 1. "PARAM,"
line.long 0x1D0 "INST58_0,"
line.long 0x1D4 "INST58_1,"
hexmask.long.byte 0x1D4 25.--31. 1. "NU2,"
rbitfld.long 0x1D4 24. "NU1," "0,1"
bitfld.long 0x1D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1D4 0.--7. 1. "PARAM,"
line.long 0x1D8 "INST59_0,"
line.long 0x1DC "INST59_1,"
hexmask.long.byte 0x1DC 25.--31. 1. "NU2,"
rbitfld.long 0x1DC 24. "NU1," "0,1"
bitfld.long 0x1DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1DC 0.--7. 1. "PARAM,"
line.long 0x1E0 "INST60_0,"
line.long 0x1E4 "INST60_1,"
hexmask.long.byte 0x1E4 25.--31. 1. "NU2,"
rbitfld.long 0x1E4 24. "NU1," "0,1"
bitfld.long 0x1E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1E4 0.--7. 1. "PARAM,"
line.long 0x1E8 "INST61_0,"
line.long 0x1EC "INST61_1,"
hexmask.long.byte 0x1EC 25.--31. 1. "NU2,"
rbitfld.long 0x1EC 24. "NU1," "0,1"
bitfld.long 0x1EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1EC 0.--7. 1. "PARAM,"
line.long 0x1F0 "INST62_0,"
line.long 0x1F4 "INST62_1,"
hexmask.long.byte 0x1F4 25.--31. 1. "NU2,"
rbitfld.long 0x1F4 24. "NU1," "0,1"
bitfld.long 0x1F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1F4 0.--7. 1. "PARAM,"
line.long 0x1F8 "INST63_0,"
line.long 0x1FC "INST63_1,"
hexmask.long.byte 0x1FC 25.--31. 1. "NU2,"
rbitfld.long 0x1FC 24. "NU1," "0,1"
bitfld.long 0x1FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1FC 0.--7. 1. "PARAM,"
line.long 0x200 "INST64_0,"
line.long 0x204 "INST64_1,"
hexmask.long.byte 0x204 25.--31. 1. "NU2,"
rbitfld.long 0x204 24. "NU1," "0,1"
bitfld.long 0x204 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x204 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x204 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x204 0.--7. 1. "PARAM,"
line.long 0x208 "INST65_0,"
line.long 0x20C "INST65_1,"
hexmask.long.byte 0x20C 25.--31. 1. "NU2,"
rbitfld.long 0x20C 24. "NU1," "0,1"
bitfld.long 0x20C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x20C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x20C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x20C 0.--7. 1. "PARAM,"
line.long 0x210 "INST66_0,"
line.long 0x214 "INST66_1,"
hexmask.long.byte 0x214 25.--31. 1. "NU2,"
rbitfld.long 0x214 24. "NU1," "0,1"
bitfld.long 0x214 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x214 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x214 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x214 0.--7. 1. "PARAM,"
line.long 0x218 "INST67_0,"
line.long 0x21C "INST67_1,"
hexmask.long.byte 0x21C 25.--31. 1. "NU2,"
rbitfld.long 0x21C 24. "NU1," "0,1"
bitfld.long 0x21C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x21C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x21C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x21C 0.--7. 1. "PARAM,"
line.long 0x220 "INST68_0,"
line.long 0x224 "INST68_1,"
hexmask.long.byte 0x224 25.--31. 1. "NU2,"
rbitfld.long 0x224 24. "NU1," "0,1"
bitfld.long 0x224 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x224 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x224 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x224 0.--7. 1. "PARAM,"
line.long 0x228 "INST69_0,"
line.long 0x22C "INST69_1,"
hexmask.long.byte 0x22C 25.--31. 1. "NU2,"
rbitfld.long 0x22C 24. "NU1," "0,1"
bitfld.long 0x22C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x22C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x22C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x22C 0.--7. 1. "PARAM,"
line.long 0x230 "INST70_0,"
line.long 0x234 "INST70_1,"
hexmask.long.byte 0x234 25.--31. 1. "NU2,"
rbitfld.long 0x234 24. "NU1," "0,1"
bitfld.long 0x234 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x234 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x234 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x234 0.--7. 1. "PARAM,"
line.long 0x238 "INST71_0,"
line.long 0x23C "INST71_1,"
hexmask.long.byte 0x23C 25.--31. 1. "NU2,"
rbitfld.long 0x23C 24. "NU1," "0,1"
bitfld.long 0x23C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x23C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x23C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x23C 0.--7. 1. "PARAM,"
line.long 0x240 "INST72_0,"
line.long 0x244 "INST72_1,"
hexmask.long.byte 0x244 25.--31. 1. "NU2,"
rbitfld.long 0x244 24. "NU1," "0,1"
bitfld.long 0x244 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x244 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x244 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x244 0.--7. 1. "PARAM,"
line.long 0x248 "INST73_0,"
line.long 0x24C "INST73_1,"
hexmask.long.byte 0x24C 25.--31. 1. "NU2,"
rbitfld.long 0x24C 24. "NU1," "0,1"
bitfld.long 0x24C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x24C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x24C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x24C 0.--7. 1. "PARAM,"
line.long 0x250 "INST74_0,"
line.long 0x254 "INST74_1,"
hexmask.long.byte 0x254 25.--31. 1. "NU2,"
rbitfld.long 0x254 24. "NU1," "0,1"
bitfld.long 0x254 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x254 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x254 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x254 0.--7. 1. "PARAM,"
line.long 0x258 "INST75_0,"
line.long 0x25C "INST75_1,"
hexmask.long.byte 0x25C 25.--31. 1. "NU2,"
rbitfld.long 0x25C 24. "NU1," "0,1"
bitfld.long 0x25C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x25C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x25C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x25C 0.--7. 1. "PARAM,"
line.long 0x260 "INST76_0,"
line.long 0x264 "INST76_1,"
hexmask.long.byte 0x264 25.--31. 1. "NU2,"
rbitfld.long 0x264 24. "NU1," "0,1"
bitfld.long 0x264 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x264 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x264 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x264 0.--7. 1. "PARAM,"
line.long 0x268 "INST77_0,"
line.long 0x26C "INST77_1,"
hexmask.long.byte 0x26C 25.--31. 1. "NU2,"
rbitfld.long 0x26C 24. "NU1," "0,1"
bitfld.long 0x26C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x26C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x26C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x26C 0.--7. 1. "PARAM,"
line.long 0x270 "INST78_0,"
line.long 0x274 "INST78_1,"
hexmask.long.byte 0x274 25.--31. 1. "NU2,"
rbitfld.long 0x274 24. "NU1," "0,1"
bitfld.long 0x274 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x274 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x274 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x274 0.--7. 1. "PARAM,"
line.long 0x278 "INST79_0,"
line.long 0x27C "INST79_1,"
hexmask.long.byte 0x27C 25.--31. 1. "NU2,"
rbitfld.long 0x27C 24. "NU1," "0,1"
bitfld.long 0x27C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x27C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x27C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x27C 0.--7. 1. "PARAM,"
line.long 0x280 "INST80_0,"
line.long 0x284 "INST80_1,"
hexmask.long.byte 0x284 25.--31. 1. "NU2,"
rbitfld.long 0x284 24. "NU1," "0,1"
bitfld.long 0x284 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x284 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x284 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x284 0.--7. 1. "PARAM,"
line.long 0x288 "INST81_0,"
line.long 0x28C "INST81_1,"
hexmask.long.byte 0x28C 25.--31. 1. "NU2,"
rbitfld.long 0x28C 24. "NU1," "0,1"
bitfld.long 0x28C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x28C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x28C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x28C 0.--7. 1. "PARAM,"
line.long 0x290 "INST82_0,"
line.long 0x294 "INST82_1,"
hexmask.long.byte 0x294 25.--31. 1. "NU2,"
rbitfld.long 0x294 24. "NU1," "0,1"
bitfld.long 0x294 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x294 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x294 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x294 0.--7. 1. "PARAM,"
line.long 0x298 "INST83_0,"
line.long 0x29C "INST83_1,"
hexmask.long.byte 0x29C 25.--31. 1. "NU2,"
rbitfld.long 0x29C 24. "NU1," "0,1"
bitfld.long 0x29C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x29C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x29C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x29C 0.--7. 1. "PARAM,"
line.long 0x2A0 "INST84_0,"
line.long 0x2A4 "INST84_1,"
hexmask.long.byte 0x2A4 25.--31. 1. "NU2,"
rbitfld.long 0x2A4 24. "NU1," "0,1"
bitfld.long 0x2A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2A4 0.--7. 1. "PARAM,"
line.long 0x2A8 "INST85_0,"
line.long 0x2AC "INST85_1,"
hexmask.long.byte 0x2AC 25.--31. 1. "NU2,"
rbitfld.long 0x2AC 24. "NU1," "0,1"
bitfld.long 0x2AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2AC 0.--7. 1. "PARAM,"
line.long 0x2B0 "INST86_0,"
line.long 0x2B4 "INST86_1,"
hexmask.long.byte 0x2B4 25.--31. 1. "NU2,"
rbitfld.long 0x2B4 24. "NU1," "0,1"
bitfld.long 0x2B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2B4 0.--7. 1. "PARAM,"
line.long 0x2B8 "INST87_0,"
line.long 0x2BC "INST87_1,"
hexmask.long.byte 0x2BC 25.--31. 1. "NU2,"
rbitfld.long 0x2BC 24. "NU1," "0,1"
bitfld.long 0x2BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2BC 0.--7. 1. "PARAM,"
line.long 0x2C0 "INST88_0,"
line.long 0x2C4 "INST88_1,"
hexmask.long.byte 0x2C4 25.--31. 1. "NU2,"
rbitfld.long 0x2C4 24. "NU1," "0,1"
bitfld.long 0x2C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2C4 0.--7. 1. "PARAM,"
line.long 0x2C8 "INST89_0,"
line.long 0x2CC "INST89_1,"
hexmask.long.byte 0x2CC 25.--31. 1. "NU2,"
rbitfld.long 0x2CC 24. "NU1," "0,1"
bitfld.long 0x2CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2CC 0.--7. 1. "PARAM,"
line.long 0x2D0 "INST90_0,"
line.long 0x2D4 "INST90_1,"
hexmask.long.byte 0x2D4 25.--31. 1. "NU2,"
rbitfld.long 0x2D4 24. "NU1," "0,1"
bitfld.long 0x2D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2D4 0.--7. 1. "PARAM,"
line.long 0x2D8 "INST91_0,"
line.long 0x2DC "INST91_1,"
hexmask.long.byte 0x2DC 25.--31. 1. "NU2,"
rbitfld.long 0x2DC 24. "NU1," "0,1"
bitfld.long 0x2DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2DC 0.--7. 1. "PARAM,"
line.long 0x2E0 "INST92_0,"
line.long 0x2E4 "INST92_1,"
hexmask.long.byte 0x2E4 25.--31. 1. "NU2,"
rbitfld.long 0x2E4 24. "NU1," "0,1"
bitfld.long 0x2E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2E4 0.--7. 1. "PARAM,"
line.long 0x2E8 "INST93_0,"
line.long 0x2EC "INST93_1,"
hexmask.long.byte 0x2EC 25.--31. 1. "NU2,"
rbitfld.long 0x2EC 24. "NU1," "0,1"
bitfld.long 0x2EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2EC 0.--7. 1. "PARAM,"
line.long 0x2F0 "INST94_0,"
line.long 0x2F4 "INST94_1,"
hexmask.long.byte 0x2F4 25.--31. 1. "NU2,"
rbitfld.long 0x2F4 24. "NU1," "0,1"
bitfld.long 0x2F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2F4 0.--7. 1. "PARAM,"
line.long 0x2F8 "INST95_0,"
line.long 0x2FC "INST95_1,"
hexmask.long.byte 0x2FC 25.--31. 1. "NU2,"
rbitfld.long 0x2FC 24. "NU1," "0,1"
bitfld.long 0x2FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2FC 0.--7. 1. "PARAM,"
line.long 0x300 "INST96_0,"
line.long 0x304 "INST96_1,"
hexmask.long.byte 0x304 25.--31. 1. "NU2,"
rbitfld.long 0x304 24. "NU1," "0,1"
bitfld.long 0x304 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x304 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x304 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x304 0.--7. 1. "PARAM,"
line.long 0x308 "INST97_0,"
line.long 0x30C "INST97_1,"
hexmask.long.byte 0x30C 25.--31. 1. "NU2,"
rbitfld.long 0x30C 24. "NU1," "0,1"
bitfld.long 0x30C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x30C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x30C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x30C 0.--7. 1. "PARAM,"
line.long 0x310 "INST98_0,"
line.long 0x314 "INST98_1,"
hexmask.long.byte 0x314 25.--31. 1. "NU2,"
rbitfld.long 0x314 24. "NU1," "0,1"
bitfld.long 0x314 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x314 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x314 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x314 0.--7. 1. "PARAM,"
line.long 0x318 "INST99_0,"
line.long 0x31C "INST99_1,"
hexmask.long.byte 0x31C 25.--31. 1. "NU2,"
rbitfld.long 0x31C 24. "NU1," "0,1"
bitfld.long 0x31C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x31C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x31C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x31C 0.--7. 1. "PARAM,"
line.long 0x320 "INST100_0,"
line.long 0x324 "INST100_1,"
hexmask.long.byte 0x324 25.--31. 1. "NU2,"
rbitfld.long 0x324 24. "NU1," "0,1"
bitfld.long 0x324 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x324 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x324 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x324 0.--7. 1. "PARAM,"
line.long 0x328 "INST101_0,"
line.long 0x32C "INST101_1,"
hexmask.long.byte 0x32C 25.--31. 1. "NU2,"
rbitfld.long 0x32C 24. "NU1," "0,1"
bitfld.long 0x32C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x32C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x32C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x32C 0.--7. 1. "PARAM,"
line.long 0x330 "INST102_0,"
line.long 0x334 "INST102_1,"
hexmask.long.byte 0x334 25.--31. 1. "NU2,"
rbitfld.long 0x334 24. "NU1," "0,1"
bitfld.long 0x334 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x334 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x334 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x334 0.--7. 1. "PARAM,"
line.long 0x338 "INST103_0,"
line.long 0x33C "INST103_1,"
hexmask.long.byte 0x33C 25.--31. 1. "NU2,"
rbitfld.long 0x33C 24. "NU1," "0,1"
bitfld.long 0x33C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x33C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x33C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x33C 0.--7. 1. "PARAM,"
line.long 0x340 "INST104_0,"
line.long 0x344 "INST104_1,"
hexmask.long.byte 0x344 25.--31. 1. "NU2,"
rbitfld.long 0x344 24. "NU1," "0,1"
bitfld.long 0x344 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x344 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x344 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x344 0.--7. 1. "PARAM,"
line.long 0x348 "INST105_0,"
line.long 0x34C "INST105_1,"
hexmask.long.byte 0x34C 25.--31. 1. "NU2,"
rbitfld.long 0x34C 24. "NU1," "0,1"
bitfld.long 0x34C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x34C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x34C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x34C 0.--7. 1. "PARAM,"
line.long 0x350 "INST106_0,"
line.long 0x354 "INST106_1,"
hexmask.long.byte 0x354 25.--31. 1. "NU2,"
rbitfld.long 0x354 24. "NU1," "0,1"
bitfld.long 0x354 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x354 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x354 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x354 0.--7. 1. "PARAM,"
line.long 0x358 "INST107_0,"
line.long 0x35C "INST107_1,"
hexmask.long.byte 0x35C 25.--31. 1. "NU2,"
rbitfld.long 0x35C 24. "NU1," "0,1"
bitfld.long 0x35C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x35C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x35C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x35C 0.--7. 1. "PARAM,"
line.long 0x360 "INST108_0,"
line.long 0x364 "INST108_1,"
hexmask.long.byte 0x364 25.--31. 1. "NU2,"
rbitfld.long 0x364 24. "NU1," "0,1"
bitfld.long 0x364 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x364 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x364 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x364 0.--7. 1. "PARAM,"
line.long 0x368 "INST109_0,"
line.long 0x36C "INST109_1,"
hexmask.long.byte 0x36C 25.--31. 1. "NU2,"
rbitfld.long 0x36C 24. "NU1," "0,1"
bitfld.long 0x36C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x36C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x36C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x36C 0.--7. 1. "PARAM,"
line.long 0x370 "INST110_0,"
line.long 0x374 "INST110_1,"
hexmask.long.byte 0x374 25.--31. 1. "NU2,"
rbitfld.long 0x374 24. "NU1," "0,1"
bitfld.long 0x374 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x374 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x374 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x374 0.--7. 1. "PARAM,"
line.long 0x378 "INST111_0,"
line.long 0x37C "INST111_1,"
hexmask.long.byte 0x37C 25.--31. 1. "NU2,"
rbitfld.long 0x37C 24. "NU1," "0,1"
bitfld.long 0x37C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x37C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x37C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x37C 0.--7. 1. "PARAM,"
line.long 0x380 "INST112_0,"
line.long 0x384 "INST112_1,"
hexmask.long.byte 0x384 25.--31. 1. "NU2,"
rbitfld.long 0x384 24. "NU1," "0,1"
bitfld.long 0x384 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x384 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x384 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x384 0.--7. 1. "PARAM,"
line.long 0x388 "INST113_0,"
line.long 0x38C "INST113_1,"
hexmask.long.byte 0x38C 25.--31. 1. "NU2,"
rbitfld.long 0x38C 24. "NU1," "0,1"
bitfld.long 0x38C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x38C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x38C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x38C 0.--7. 1. "PARAM,"
line.long 0x390 "INST114_0,"
line.long 0x394 "INST114_1,"
hexmask.long.byte 0x394 25.--31. 1. "NU2,"
rbitfld.long 0x394 24. "NU1," "0,1"
bitfld.long 0x394 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x394 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x394 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x394 0.--7. 1. "PARAM,"
line.long 0x398 "INST115_0,"
line.long 0x39C "INST115_1,"
hexmask.long.byte 0x39C 25.--31. 1. "NU2,"
rbitfld.long 0x39C 24. "NU1," "0,1"
bitfld.long 0x39C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x39C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x39C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x39C 0.--7. 1. "PARAM,"
line.long 0x3A0 "INST116_0,"
line.long 0x3A4 "INST116_1,"
hexmask.long.byte 0x3A4 25.--31. 1. "NU2,"
rbitfld.long 0x3A4 24. "NU1," "0,1"
bitfld.long 0x3A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3A4 0.--7. 1. "PARAM,"
line.long 0x3A8 "INST117_0,"
line.long 0x3AC "INST117_1,"
hexmask.long.byte 0x3AC 25.--31. 1. "NU2,"
rbitfld.long 0x3AC 24. "NU1," "0,1"
bitfld.long 0x3AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3AC 0.--7. 1. "PARAM,"
line.long 0x3B0 "INST118_0,"
line.long 0x3B4 "INST118_1,"
hexmask.long.byte 0x3B4 25.--31. 1. "NU2,"
rbitfld.long 0x3B4 24. "NU1," "0,1"
bitfld.long 0x3B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3B4 0.--7. 1. "PARAM,"
line.long 0x3B8 "INST119_0,"
line.long 0x3BC "INST119_1,"
hexmask.long.byte 0x3BC 25.--31. 1. "NU2,"
rbitfld.long 0x3BC 24. "NU1," "0,1"
bitfld.long 0x3BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3BC 0.--7. 1. "PARAM,"
line.long 0x3C0 "INST120_0,"
line.long 0x3C4 "INST120_1,"
hexmask.long.byte 0x3C4 25.--31. 1. "NU2,"
rbitfld.long 0x3C4 24. "NU1," "0,1"
bitfld.long 0x3C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3C4 0.--7. 1. "PARAM,"
line.long 0x3C8 "INST121_0,"
line.long 0x3CC "INST121_1,"
hexmask.long.byte 0x3CC 25.--31. 1. "NU2,"
rbitfld.long 0x3CC 24. "NU1," "0,1"
bitfld.long 0x3CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3CC 0.--7. 1. "PARAM,"
line.long 0x3D0 "INST122_0,"
line.long 0x3D4 "INST122_1,"
hexmask.long.byte 0x3D4 25.--31. 1. "NU2,"
rbitfld.long 0x3D4 24. "NU1," "0,1"
bitfld.long 0x3D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3D4 0.--7. 1. "PARAM,"
line.long 0x3D8 "INST123_0,"
line.long 0x3DC "INST123_1,"
hexmask.long.byte 0x3DC 25.--31. 1. "NU2,"
rbitfld.long 0x3DC 24. "NU1," "0,1"
bitfld.long 0x3DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3DC 0.--7. 1. "PARAM,"
line.long 0x3E0 "INST124_0,"
line.long 0x3E4 "INST124_1,"
hexmask.long.byte 0x3E4 25.--31. 1. "NU2,"
rbitfld.long 0x3E4 24. "NU1," "0,1"
bitfld.long 0x3E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3E4 0.--7. 1. "PARAM,"
line.long 0x3E8 "INST125_0,"
line.long 0x3EC "INST125_1,"
hexmask.long.byte 0x3EC 25.--31. 1. "NU2,"
rbitfld.long 0x3EC 24. "NU1," "0,1"
bitfld.long 0x3EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3EC 0.--7. 1. "PARAM,"
line.long 0x3F0 "INST126_0,"
line.long 0x3F4 "INST126_1,"
hexmask.long.byte 0x3F4 25.--31. 1. "NU2,"
rbitfld.long 0x3F4 24. "NU1," "0,1"
bitfld.long 0x3F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3F4 0.--7. 1. "PARAM,"
line.long 0x3F8 "INST127_0,"
line.long 0x3FC "INST127_1,"
hexmask.long.byte 0x3FC 25.--31. 1. "NU2,"
rbitfld.long 0x3FC 24. "NU1," "0,1"
bitfld.long 0x3FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3FC 0.--7. 1. "PARAM,"
line.long 0x400 "INST128_0,"
line.long 0x404 "INST128_1,"
hexmask.long.byte 0x404 25.--31. 1. "NU2,"
rbitfld.long 0x404 24. "NU1," "0,1"
bitfld.long 0x404 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x404 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x404 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x404 0.--7. 1. "PARAM,"
line.long 0x408 "INST129_0,"
line.long 0x40C "INST129_1,"
hexmask.long.byte 0x40C 25.--31. 1. "NU2,"
rbitfld.long 0x40C 24. "NU1," "0,1"
bitfld.long 0x40C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x40C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x40C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x40C 0.--7. 1. "PARAM,"
line.long 0x410 "INST130_0,"
line.long 0x414 "INST130_1,"
hexmask.long.byte 0x414 25.--31. 1. "NU2,"
rbitfld.long 0x414 24. "NU1," "0,1"
bitfld.long 0x414 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x414 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x414 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x414 0.--7. 1. "PARAM,"
line.long 0x418 "INST131_0,"
line.long 0x41C "INST131_1,"
hexmask.long.byte 0x41C 25.--31. 1. "NU2,"
rbitfld.long 0x41C 24. "NU1," "0,1"
bitfld.long 0x41C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x41C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x41C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x41C 0.--7. 1. "PARAM,"
line.long 0x420 "INST132_0,"
line.long 0x424 "INST132_1,"
hexmask.long.byte 0x424 25.--31. 1. "NU2,"
rbitfld.long 0x424 24. "NU1," "0,1"
bitfld.long 0x424 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x424 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x424 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x424 0.--7. 1. "PARAM,"
line.long 0x428 "INST133_0,"
line.long 0x42C "INST133_1,"
hexmask.long.byte 0x42C 25.--31. 1. "NU2,"
rbitfld.long 0x42C 24. "NU1," "0,1"
bitfld.long 0x42C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x42C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x42C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x42C 0.--7. 1. "PARAM,"
line.long 0x430 "INST134_0,"
line.long 0x434 "INST134_1,"
hexmask.long.byte 0x434 25.--31. 1. "NU2,"
rbitfld.long 0x434 24. "NU1," "0,1"
bitfld.long 0x434 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x434 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x434 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x434 0.--7. 1. "PARAM,"
line.long 0x438 "INST135_0,"
line.long 0x43C "INST135_1,"
hexmask.long.byte 0x43C 25.--31. 1. "NU2,"
rbitfld.long 0x43C 24. "NU1," "0,1"
bitfld.long 0x43C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x43C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x43C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x43C 0.--7. 1. "PARAM,"
line.long 0x440 "INST136_0,"
line.long 0x444 "INST136_1,"
hexmask.long.byte 0x444 25.--31. 1. "NU2,"
rbitfld.long 0x444 24. "NU1," "0,1"
bitfld.long 0x444 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x444 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x444 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x444 0.--7. 1. "PARAM,"
line.long 0x448 "INST137_0,"
line.long 0x44C "INST137_1,"
hexmask.long.byte 0x44C 25.--31. 1. "NU2,"
rbitfld.long 0x44C 24. "NU1," "0,1"
bitfld.long 0x44C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x44C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x44C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x44C 0.--7. 1. "PARAM,"
line.long 0x450 "INST138_0,"
line.long 0x454 "INST138_1,"
hexmask.long.byte 0x454 25.--31. 1. "NU2,"
rbitfld.long 0x454 24. "NU1," "0,1"
bitfld.long 0x454 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x454 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x454 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x454 0.--7. 1. "PARAM,"
line.long 0x458 "INST139_0,"
line.long 0x45C "INST139_1,"
hexmask.long.byte 0x45C 25.--31. 1. "NU2,"
rbitfld.long 0x45C 24. "NU1," "0,1"
bitfld.long 0x45C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x45C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x45C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x45C 0.--7. 1. "PARAM,"
line.long 0x460 "INST140_0,"
line.long 0x464 "INST140_1,"
hexmask.long.byte 0x464 25.--31. 1. "NU2,"
rbitfld.long 0x464 24. "NU1," "0,1"
bitfld.long 0x464 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x464 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x464 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x464 0.--7. 1. "PARAM,"
line.long 0x468 "INST141_0,"
line.long 0x46C "INST141_1,"
hexmask.long.byte 0x46C 25.--31. 1. "NU2,"
rbitfld.long 0x46C 24. "NU1," "0,1"
bitfld.long 0x46C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x46C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x46C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x46C 0.--7. 1. "PARAM,"
line.long 0x470 "INST142_0,"
line.long 0x474 "INST142_1,"
hexmask.long.byte 0x474 25.--31. 1. "NU2,"
rbitfld.long 0x474 24. "NU1," "0,1"
bitfld.long 0x474 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x474 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x474 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x474 0.--7. 1. "PARAM,"
line.long 0x478 "INST143_0,"
line.long 0x47C "INST143_1,"
hexmask.long.byte 0x47C 25.--31. 1. "NU2,"
rbitfld.long 0x47C 24. "NU1," "0,1"
bitfld.long 0x47C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x47C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x47C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x47C 0.--7. 1. "PARAM,"
line.long 0x480 "INST144_0,"
line.long 0x484 "INST144_1,"
hexmask.long.byte 0x484 25.--31. 1. "NU2,"
rbitfld.long 0x484 24. "NU1," "0,1"
bitfld.long 0x484 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x484 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x484 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x484 0.--7. 1. "PARAM,"
line.long 0x488 "INST145_0,"
line.long 0x48C "INST145_1,"
hexmask.long.byte 0x48C 25.--31. 1. "NU2,"
rbitfld.long 0x48C 24. "NU1," "0,1"
bitfld.long 0x48C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x48C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x48C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x48C 0.--7. 1. "PARAM,"
line.long 0x490 "INST146_0,"
line.long 0x494 "INST146_1,"
hexmask.long.byte 0x494 25.--31. 1. "NU2,"
rbitfld.long 0x494 24. "NU1," "0,1"
bitfld.long 0x494 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x494 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x494 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x494 0.--7. 1. "PARAM,"
line.long 0x498 "INST147_0,"
line.long 0x49C "INST147_1,"
hexmask.long.byte 0x49C 25.--31. 1. "NU2,"
rbitfld.long 0x49C 24. "NU1," "0,1"
bitfld.long 0x49C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x49C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x49C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x49C 0.--7. 1. "PARAM,"
line.long 0x4A0 "INST148_0,"
line.long 0x4A4 "INST148_1,"
hexmask.long.byte 0x4A4 25.--31. 1. "NU2,"
rbitfld.long 0x4A4 24. "NU1," "0,1"
bitfld.long 0x4A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4A4 0.--7. 1. "PARAM,"
line.long 0x4A8 "INST149_0,"
line.long 0x4AC "INST149_1,"
hexmask.long.byte 0x4AC 25.--31. 1. "NU2,"
rbitfld.long 0x4AC 24. "NU1," "0,1"
bitfld.long 0x4AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4AC 0.--7. 1. "PARAM,"
line.long 0x4B0 "INST150_0,"
line.long 0x4B4 "INST150_1,"
hexmask.long.byte 0x4B4 25.--31. 1. "NU2,"
rbitfld.long 0x4B4 24. "NU1," "0,1"
bitfld.long 0x4B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4B4 0.--7. 1. "PARAM,"
line.long 0x4B8 "INST151_0,"
line.long 0x4BC "INST151_1,"
hexmask.long.byte 0x4BC 25.--31. 1. "NU2,"
rbitfld.long 0x4BC 24. "NU1," "0,1"
bitfld.long 0x4BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4BC 0.--7. 1. "PARAM,"
line.long 0x4C0 "INST152_0,"
line.long 0x4C4 "INST152_1,"
hexmask.long.byte 0x4C4 25.--31. 1. "NU2,"
rbitfld.long 0x4C4 24. "NU1," "0,1"
bitfld.long 0x4C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4C4 0.--7. 1. "PARAM,"
line.long 0x4C8 "INST153_0,"
line.long 0x4CC "INST153_1,"
hexmask.long.byte 0x4CC 25.--31. 1. "NU2,"
rbitfld.long 0x4CC 24. "NU1," "0,1"
bitfld.long 0x4CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4CC 0.--7. 1. "PARAM,"
line.long 0x4D0 "INST154_0,"
line.long 0x4D4 "INST154_1,"
hexmask.long.byte 0x4D4 25.--31. 1. "NU2,"
rbitfld.long 0x4D4 24. "NU1," "0,1"
bitfld.long 0x4D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4D4 0.--7. 1. "PARAM,"
line.long 0x4D8 "INST155_0,"
line.long 0x4DC "INST155_1,"
hexmask.long.byte 0x4DC 25.--31. 1. "NU2,"
rbitfld.long 0x4DC 24. "NU1," "0,1"
bitfld.long 0x4DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4DC 0.--7. 1. "PARAM,"
line.long 0x4E0 "INST156_0,"
line.long 0x4E4 "INST156_1,"
hexmask.long.byte 0x4E4 25.--31. 1. "NU2,"
rbitfld.long 0x4E4 24. "NU1," "0,1"
bitfld.long 0x4E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4E4 0.--7. 1. "PARAM,"
line.long 0x4E8 "INST157_0,"
line.long 0x4EC "INST157_1,"
hexmask.long.byte 0x4EC 25.--31. 1. "NU2,"
rbitfld.long 0x4EC 24. "NU1," "0,1"
bitfld.long 0x4EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4EC 0.--7. 1. "PARAM,"
line.long 0x4F0 "INST158_0,"
line.long 0x4F4 "INST158_1,"
hexmask.long.byte 0x4F4 25.--31. 1. "NU2,"
rbitfld.long 0x4F4 24. "NU1," "0,1"
bitfld.long 0x4F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4F4 0.--7. 1. "PARAM,"
line.long 0x4F8 "INST159_0,"
line.long 0x4FC "INST159_1,"
hexmask.long.byte 0x4FC 25.--31. 1. "NU2,"
rbitfld.long 0x4FC 24. "NU1," "0,1"
bitfld.long 0x4FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4FC 0.--7. 1. "PARAM,"
line.long 0x500 "INST160_0,"
line.long 0x504 "INST160_1,"
hexmask.long.byte 0x504 25.--31. 1. "NU2,"
rbitfld.long 0x504 24. "NU1," "0,1"
bitfld.long 0x504 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x504 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x504 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x504 0.--7. 1. "PARAM,"
line.long 0x508 "INST161_0,"
line.long 0x50C "INST161_1,"
hexmask.long.byte 0x50C 25.--31. 1. "NU2,"
rbitfld.long 0x50C 24. "NU1," "0,1"
bitfld.long 0x50C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x50C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x50C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x50C 0.--7. 1. "PARAM,"
line.long 0x510 "INST162_0,"
line.long 0x514 "INST162_1,"
hexmask.long.byte 0x514 25.--31. 1. "NU2,"
rbitfld.long 0x514 24. "NU1," "0,1"
bitfld.long 0x514 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x514 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x514 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x514 0.--7. 1. "PARAM,"
line.long 0x518 "INST163_0,"
line.long 0x51C "INST163_1,"
hexmask.long.byte 0x51C 25.--31. 1. "NU2,"
rbitfld.long 0x51C 24. "NU1," "0,1"
bitfld.long 0x51C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x51C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x51C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x51C 0.--7. 1. "PARAM,"
line.long 0x520 "INST164_0,"
line.long 0x524 "INST164_1,"
hexmask.long.byte 0x524 25.--31. 1. "NU2,"
rbitfld.long 0x524 24. "NU1," "0,1"
bitfld.long 0x524 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x524 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x524 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x524 0.--7. 1. "PARAM,"
line.long 0x528 "INST165_0,"
line.long 0x52C "INST165_1,"
hexmask.long.byte 0x52C 25.--31. 1. "NU2,"
rbitfld.long 0x52C 24. "NU1," "0,1"
bitfld.long 0x52C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x52C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x52C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x52C 0.--7. 1. "PARAM,"
line.long 0x530 "INST166_0,"
line.long 0x534 "INST166_1,"
hexmask.long.byte 0x534 25.--31. 1. "NU2,"
rbitfld.long 0x534 24. "NU1," "0,1"
bitfld.long 0x534 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x534 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x534 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x534 0.--7. 1. "PARAM,"
line.long 0x538 "INST167_0,"
line.long 0x53C "INST167_1,"
hexmask.long.byte 0x53C 25.--31. 1. "NU2,"
rbitfld.long 0x53C 24. "NU1," "0,1"
bitfld.long 0x53C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x53C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x53C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x53C 0.--7. 1. "PARAM,"
line.long 0x540 "INST168_0,"
line.long 0x544 "INST168_1,"
hexmask.long.byte 0x544 25.--31. 1. "NU2,"
rbitfld.long 0x544 24. "NU1," "0,1"
bitfld.long 0x544 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x544 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x544 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x544 0.--7. 1. "PARAM,"
line.long 0x548 "INST169_0,"
line.long 0x54C "INST169_1,"
hexmask.long.byte 0x54C 25.--31. 1. "NU2,"
rbitfld.long 0x54C 24. "NU1," "0,1"
bitfld.long 0x54C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x54C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x54C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x54C 0.--7. 1. "PARAM,"
line.long 0x550 "INST170_0,"
line.long 0x554 "INST170_1,"
hexmask.long.byte 0x554 25.--31. 1. "NU2,"
rbitfld.long 0x554 24. "NU1," "0,1"
bitfld.long 0x554 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x554 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x554 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x554 0.--7. 1. "PARAM,"
line.long 0x558 "INST171_0,"
line.long 0x55C "INST171_1,"
hexmask.long.byte 0x55C 25.--31. 1. "NU2,"
rbitfld.long 0x55C 24. "NU1," "0,1"
bitfld.long 0x55C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x55C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x55C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x55C 0.--7. 1. "PARAM,"
line.long 0x560 "INST172_0,"
line.long 0x564 "INST172_1,"
hexmask.long.byte 0x564 25.--31. 1. "NU2,"
rbitfld.long 0x564 24. "NU1," "0,1"
bitfld.long 0x564 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x564 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x564 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x564 0.--7. 1. "PARAM,"
line.long 0x568 "INST173_0,"
line.long 0x56C "INST173_1,"
hexmask.long.byte 0x56C 25.--31. 1. "NU2,"
rbitfld.long 0x56C 24. "NU1," "0,1"
bitfld.long 0x56C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x56C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x56C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x56C 0.--7. 1. "PARAM,"
line.long 0x570 "INST174_0,"
line.long 0x574 "INST174_1,"
hexmask.long.byte 0x574 25.--31. 1. "NU2,"
rbitfld.long 0x574 24. "NU1," "0,1"
bitfld.long 0x574 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x574 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x574 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x574 0.--7. 1. "PARAM,"
line.long 0x578 "INST175_0,"
line.long 0x57C "INST175_1,"
hexmask.long.byte 0x57C 25.--31. 1. "NU2,"
rbitfld.long 0x57C 24. "NU1," "0,1"
bitfld.long 0x57C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x57C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x57C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x57C 0.--7. 1. "PARAM,"
line.long 0x580 "INST176_0,"
line.long 0x584 "INST176_1,"
hexmask.long.byte 0x584 25.--31. 1. "NU2,"
rbitfld.long 0x584 24. "NU1," "0,1"
bitfld.long 0x584 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x584 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x584 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x584 0.--7. 1. "PARAM,"
line.long 0x588 "INST177_0,"
line.long 0x58C "INST177_1,"
hexmask.long.byte 0x58C 25.--31. 1. "NU2,"
rbitfld.long 0x58C 24. "NU1," "0,1"
bitfld.long 0x58C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x58C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x58C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x58C 0.--7. 1. "PARAM,"
line.long 0x590 "INST178_0,"
line.long 0x594 "INST178_1,"
hexmask.long.byte 0x594 25.--31. 1. "NU2,"
rbitfld.long 0x594 24. "NU1," "0,1"
bitfld.long 0x594 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x594 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x594 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x594 0.--7. 1. "PARAM,"
line.long 0x598 "INST179_0,"
line.long 0x59C "INST179_1,"
hexmask.long.byte 0x59C 25.--31. 1. "NU2,"
rbitfld.long 0x59C 24. "NU1," "0,1"
bitfld.long 0x59C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x59C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x59C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x59C 0.--7. 1. "PARAM,"
line.long 0x5A0 "INST180_0,"
line.long 0x5A4 "INST180_1,"
hexmask.long.byte 0x5A4 25.--31. 1. "NU2,"
rbitfld.long 0x5A4 24. "NU1," "0,1"
bitfld.long 0x5A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5A4 0.--7. 1. "PARAM,"
line.long 0x5A8 "INST181_0,"
line.long 0x5AC "INST181_1,"
hexmask.long.byte 0x5AC 25.--31. 1. "NU2,"
rbitfld.long 0x5AC 24. "NU1," "0,1"
bitfld.long 0x5AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5AC 0.--7. 1. "PARAM,"
line.long 0x5B0 "INST182_0,"
line.long 0x5B4 "INST182_1,"
hexmask.long.byte 0x5B4 25.--31. 1. "NU2,"
rbitfld.long 0x5B4 24. "NU1," "0,1"
bitfld.long 0x5B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5B4 0.--7. 1. "PARAM,"
line.long 0x5B8 "INST183_0,"
line.long 0x5BC "INST183_1,"
hexmask.long.byte 0x5BC 25.--31. 1. "NU2,"
rbitfld.long 0x5BC 24. "NU1," "0,1"
bitfld.long 0x5BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5BC 0.--7. 1. "PARAM,"
line.long 0x5C0 "INST184_0,"
line.long 0x5C4 "INST184_1,"
hexmask.long.byte 0x5C4 25.--31. 1. "NU2,"
rbitfld.long 0x5C4 24. "NU1," "0,1"
bitfld.long 0x5C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5C4 0.--7. 1. "PARAM,"
line.long 0x5C8 "INST185_0,"
line.long 0x5CC "INST185_1,"
hexmask.long.byte 0x5CC 25.--31. 1. "NU2,"
rbitfld.long 0x5CC 24. "NU1," "0,1"
bitfld.long 0x5CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5CC 0.--7. 1. "PARAM,"
line.long 0x5D0 "INST186_0,"
line.long 0x5D4 "INST186_1,"
hexmask.long.byte 0x5D4 25.--31. 1. "NU2,"
rbitfld.long 0x5D4 24. "NU1," "0,1"
bitfld.long 0x5D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5D4 0.--7. 1. "PARAM,"
line.long 0x5D8 "INST187_0,"
line.long 0x5DC "INST187_1,"
hexmask.long.byte 0x5DC 25.--31. 1. "NU2,"
rbitfld.long 0x5DC 24. "NU1," "0,1"
bitfld.long 0x5DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5DC 0.--7. 1. "PARAM,"
line.long 0x5E0 "INST188_0,"
line.long 0x5E4 "INST188_1,"
hexmask.long.byte 0x5E4 25.--31. 1. "NU2,"
rbitfld.long 0x5E4 24. "NU1," "0,1"
bitfld.long 0x5E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5E4 0.--7. 1. "PARAM,"
line.long 0x5E8 "INST189_0,"
line.long 0x5EC "INST189_1,"
hexmask.long.byte 0x5EC 25.--31. 1. "NU2,"
rbitfld.long 0x5EC 24. "NU1," "0,1"
bitfld.long 0x5EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5EC 0.--7. 1. "PARAM,"
line.long 0x5F0 "INST190_0,"
line.long 0x5F4 "INST190_1,"
hexmask.long.byte 0x5F4 25.--31. 1. "NU2,"
rbitfld.long 0x5F4 24. "NU1," "0,1"
bitfld.long 0x5F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5F4 0.--7. 1. "PARAM,"
line.long 0x5F8 "INST191_0,"
line.long 0x5FC "INST191_1,"
hexmask.long.byte 0x5FC 25.--31. 1. "NU2,"
rbitfld.long 0x5FC 24. "NU1," "0,1"
bitfld.long 0x5FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5FC 0.--7. 1. "PARAM,"
line.long 0x600 "INST192_0,"
line.long 0x604 "INST192_1,"
hexmask.long.byte 0x604 25.--31. 1. "NU2,"
rbitfld.long 0x604 24. "NU1," "0,1"
bitfld.long 0x604 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x604 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x604 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x604 0.--7. 1. "PARAM,"
line.long 0x608 "INST193_0,"
line.long 0x60C "INST193_1,"
hexmask.long.byte 0x60C 25.--31. 1. "NU2,"
rbitfld.long 0x60C 24. "NU1," "0,1"
bitfld.long 0x60C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x60C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x60C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x60C 0.--7. 1. "PARAM,"
line.long 0x610 "INST194_0,"
line.long 0x614 "INST194_1,"
hexmask.long.byte 0x614 25.--31. 1. "NU2,"
rbitfld.long 0x614 24. "NU1," "0,1"
bitfld.long 0x614 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x614 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x614 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x614 0.--7. 1. "PARAM,"
line.long 0x618 "INST195_0,"
line.long 0x61C "INST195_1,"
hexmask.long.byte 0x61C 25.--31. 1. "NU2,"
rbitfld.long 0x61C 24. "NU1," "0,1"
bitfld.long 0x61C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x61C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x61C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x61C 0.--7. 1. "PARAM,"
line.long 0x620 "INST196_0,"
line.long 0x624 "INST196_1,"
hexmask.long.byte 0x624 25.--31. 1. "NU2,"
rbitfld.long 0x624 24. "NU1," "0,1"
bitfld.long 0x624 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x624 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x624 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x624 0.--7. 1. "PARAM,"
line.long 0x628 "INST197_0,"
line.long 0x62C "INST197_1,"
hexmask.long.byte 0x62C 25.--31. 1. "NU2,"
rbitfld.long 0x62C 24. "NU1," "0,1"
bitfld.long 0x62C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x62C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x62C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x62C 0.--7. 1. "PARAM,"
line.long 0x630 "INST198_0,"
line.long 0x634 "INST198_1,"
hexmask.long.byte 0x634 25.--31. 1. "NU2,"
rbitfld.long 0x634 24. "NU1," "0,1"
bitfld.long 0x634 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x634 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x634 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x634 0.--7. 1. "PARAM,"
line.long 0x638 "INST199_0,"
line.long 0x63C "INST199_1,"
hexmask.long.byte 0x63C 25.--31. 1. "NU2,"
rbitfld.long 0x63C 24. "NU1," "0,1"
bitfld.long 0x63C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x63C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x63C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x63C 0.--7. 1. "PARAM,"
line.long 0x640 "INST200_0,"
line.long 0x644 "INST200_1,"
hexmask.long.byte 0x644 25.--31. 1. "NU2,"
rbitfld.long 0x644 24. "NU1," "0,1"
bitfld.long 0x644 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x644 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x644 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x644 0.--7. 1. "PARAM,"
line.long 0x648 "INST201_0,"
line.long 0x64C "INST201_1,"
hexmask.long.byte 0x64C 25.--31. 1. "NU2,"
rbitfld.long 0x64C 24. "NU1," "0,1"
bitfld.long 0x64C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x64C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x64C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x64C 0.--7. 1. "PARAM,"
line.long 0x650 "INST202_0,"
line.long 0x654 "INST202_1,"
hexmask.long.byte 0x654 25.--31. 1. "NU2,"
rbitfld.long 0x654 24. "NU1," "0,1"
bitfld.long 0x654 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x654 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x654 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x654 0.--7. 1. "PARAM,"
line.long 0x658 "INST203_0,"
line.long 0x65C "INST203_1,"
hexmask.long.byte 0x65C 25.--31. 1. "NU2,"
rbitfld.long 0x65C 24. "NU1," "0,1"
bitfld.long 0x65C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x65C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x65C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x65C 0.--7. 1. "PARAM,"
line.long 0x660 "INST204_0,"
line.long 0x664 "INST204_1,"
hexmask.long.byte 0x664 25.--31. 1. "NU2,"
rbitfld.long 0x664 24. "NU1," "0,1"
bitfld.long 0x664 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x664 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x664 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x664 0.--7. 1. "PARAM,"
line.long 0x668 "INST205_0,"
line.long 0x66C "INST205_1,"
hexmask.long.byte 0x66C 25.--31. 1. "NU2,"
rbitfld.long 0x66C 24. "NU1," "0,1"
bitfld.long 0x66C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x66C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x66C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x66C 0.--7. 1. "PARAM,"
line.long 0x670 "INST206_0,"
line.long 0x674 "INST206_1,"
hexmask.long.byte 0x674 25.--31. 1. "NU2,"
rbitfld.long 0x674 24. "NU1," "0,1"
bitfld.long 0x674 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x674 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x674 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x674 0.--7. 1. "PARAM,"
line.long 0x678 "INST207_0,"
line.long 0x67C "INST207_1,"
hexmask.long.byte 0x67C 25.--31. 1. "NU2,"
rbitfld.long 0x67C 24. "NU1," "0,1"
bitfld.long 0x67C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x67C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x67C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x67C 0.--7. 1. "PARAM,"
line.long 0x680 "INST208_0,"
line.long 0x684 "INST208_1,"
hexmask.long.byte 0x684 25.--31. 1. "NU2,"
rbitfld.long 0x684 24. "NU1," "0,1"
bitfld.long 0x684 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x684 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x684 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x684 0.--7. 1. "PARAM,"
line.long 0x688 "INST209_0,"
line.long 0x68C "INST209_1,"
hexmask.long.byte 0x68C 25.--31. 1. "NU2,"
rbitfld.long 0x68C 24. "NU1," "0,1"
bitfld.long 0x68C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x68C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x68C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x68C 0.--7. 1. "PARAM,"
line.long 0x690 "INST210_0,"
line.long 0x694 "INST210_1,"
hexmask.long.byte 0x694 25.--31. 1. "NU2,"
rbitfld.long 0x694 24. "NU1," "0,1"
bitfld.long 0x694 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x694 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x694 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x694 0.--7. 1. "PARAM,"
line.long 0x698 "INST211_0,"
line.long 0x69C "INST211_1,"
hexmask.long.byte 0x69C 25.--31. 1. "NU2,"
rbitfld.long 0x69C 24. "NU1," "0,1"
bitfld.long 0x69C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x69C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x69C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x69C 0.--7. 1. "PARAM,"
line.long 0x6A0 "INST212_0,"
line.long 0x6A4 "INST212_1,"
hexmask.long.byte 0x6A4 25.--31. 1. "NU2,"
rbitfld.long 0x6A4 24. "NU1," "0,1"
bitfld.long 0x6A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6A4 0.--7. 1. "PARAM,"
line.long 0x6A8 "INST213_0,"
line.long 0x6AC "INST213_1,"
hexmask.long.byte 0x6AC 25.--31. 1. "NU2,"
rbitfld.long 0x6AC 24. "NU1," "0,1"
bitfld.long 0x6AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6AC 0.--7. 1. "PARAM,"
line.long 0x6B0 "INST214_0,"
line.long 0x6B4 "INST214_1,"
hexmask.long.byte 0x6B4 25.--31. 1. "NU2,"
rbitfld.long 0x6B4 24. "NU1," "0,1"
bitfld.long 0x6B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6B4 0.--7. 1. "PARAM,"
line.long 0x6B8 "INST215_0,"
line.long 0x6BC "INST215_1,"
hexmask.long.byte 0x6BC 25.--31. 1. "NU2,"
rbitfld.long 0x6BC 24. "NU1," "0,1"
bitfld.long 0x6BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6BC 0.--7. 1. "PARAM,"
line.long 0x6C0 "INST216_0,"
line.long 0x6C4 "INST216_1,"
hexmask.long.byte 0x6C4 25.--31. 1. "NU2,"
rbitfld.long 0x6C4 24. "NU1," "0,1"
bitfld.long 0x6C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6C4 0.--7. 1. "PARAM,"
line.long 0x6C8 "INST217_0,"
line.long 0x6CC "INST217_1,"
hexmask.long.byte 0x6CC 25.--31. 1. "NU2,"
rbitfld.long 0x6CC 24. "NU1," "0,1"
bitfld.long 0x6CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6CC 0.--7. 1. "PARAM,"
line.long 0x6D0 "INST218_0,"
line.long 0x6D4 "INST218_1,"
hexmask.long.byte 0x6D4 25.--31. 1. "NU2,"
rbitfld.long 0x6D4 24. "NU1," "0,1"
bitfld.long 0x6D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6D4 0.--7. 1. "PARAM,"
line.long 0x6D8 "INST219_0,"
line.long 0x6DC "INST219_1,"
hexmask.long.byte 0x6DC 25.--31. 1. "NU2,"
rbitfld.long 0x6DC 24. "NU1," "0,1"
bitfld.long 0x6DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6DC 0.--7. 1. "PARAM,"
line.long 0x6E0 "INST220_0,"
line.long 0x6E4 "INST220_1,"
hexmask.long.byte 0x6E4 25.--31. 1. "NU2,"
rbitfld.long 0x6E4 24. "NU1," "0,1"
bitfld.long 0x6E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6E4 0.--7. 1. "PARAM,"
line.long 0x6E8 "INST221_0,"
line.long 0x6EC "INST221_1,"
hexmask.long.byte 0x6EC 25.--31. 1. "NU2,"
rbitfld.long 0x6EC 24. "NU1," "0,1"
bitfld.long 0x6EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6EC 0.--7. 1. "PARAM,"
line.long 0x6F0 "INST222_0,"
line.long 0x6F4 "INST222_1,"
hexmask.long.byte 0x6F4 25.--31. 1. "NU2,"
rbitfld.long 0x6F4 24. "NU1," "0,1"
bitfld.long 0x6F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6F4 0.--7. 1. "PARAM,"
line.long 0x6F8 "INST223_0,"
line.long 0x6FC "INST223_1,"
hexmask.long.byte 0x6FC 25.--31. 1. "NU2,"
rbitfld.long 0x6FC 24. "NU1," "0,1"
bitfld.long 0x6FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6FC 0.--7. 1. "PARAM,"
line.long 0x700 "INST224_0,"
line.long 0x704 "INST224_1,"
hexmask.long.byte 0x704 25.--31. 1. "NU2,"
rbitfld.long 0x704 24. "NU1," "0,1"
bitfld.long 0x704 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x704 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x704 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x704 0.--7. 1. "PARAM,"
line.long 0x708 "INST225_0,"
line.long 0x70C "INST225_1,"
hexmask.long.byte 0x70C 25.--31. 1. "NU2,"
rbitfld.long 0x70C 24. "NU1," "0,1"
bitfld.long 0x70C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x70C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x70C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x70C 0.--7. 1. "PARAM,"
line.long 0x710 "INST226_0,"
line.long 0x714 "INST226_1,"
hexmask.long.byte 0x714 25.--31. 1. "NU2,"
rbitfld.long 0x714 24. "NU1," "0,1"
bitfld.long 0x714 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x714 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x714 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x714 0.--7. 1. "PARAM,"
line.long 0x718 "INST227_0,"
line.long 0x71C "INST227_1,"
hexmask.long.byte 0x71C 25.--31. 1. "NU2,"
rbitfld.long 0x71C 24. "NU1," "0,1"
bitfld.long 0x71C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x71C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x71C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x71C 0.--7. 1. "PARAM,"
line.long 0x720 "INST228_0,"
line.long 0x724 "INST228_1,"
hexmask.long.byte 0x724 25.--31. 1. "NU2,"
rbitfld.long 0x724 24. "NU1," "0,1"
bitfld.long 0x724 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x724 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x724 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x724 0.--7. 1. "PARAM,"
line.long 0x728 "INST229_0,"
line.long 0x72C "INST229_1,"
hexmask.long.byte 0x72C 25.--31. 1. "NU2,"
rbitfld.long 0x72C 24. "NU1," "0,1"
bitfld.long 0x72C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x72C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x72C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x72C 0.--7. 1. "PARAM,"
line.long 0x730 "INST230_0,"
line.long 0x734 "INST230_1,"
hexmask.long.byte 0x734 25.--31. 1. "NU2,"
rbitfld.long 0x734 24. "NU1," "0,1"
bitfld.long 0x734 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x734 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x734 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x734 0.--7. 1. "PARAM,"
line.long 0x738 "INST231_0,"
line.long 0x73C "INST231_1,"
hexmask.long.byte 0x73C 25.--31. 1. "NU2,"
rbitfld.long 0x73C 24. "NU1," "0,1"
bitfld.long 0x73C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x73C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x73C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x73C 0.--7. 1. "PARAM,"
line.long 0x740 "INST232_0,"
line.long 0x744 "INST232_1,"
hexmask.long.byte 0x744 25.--31. 1. "NU2,"
rbitfld.long 0x744 24. "NU1," "0,1"
bitfld.long 0x744 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x744 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x744 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x744 0.--7. 1. "PARAM,"
line.long 0x748 "INST233_0,"
line.long 0x74C "INST233_1,"
hexmask.long.byte 0x74C 25.--31. 1. "NU2,"
rbitfld.long 0x74C 24. "NU1," "0,1"
bitfld.long 0x74C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x74C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x74C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x74C 0.--7. 1. "PARAM,"
line.long 0x750 "INST234_0,"
line.long 0x754 "INST234_1,"
hexmask.long.byte 0x754 25.--31. 1. "NU2,"
rbitfld.long 0x754 24. "NU1," "0,1"
bitfld.long 0x754 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x754 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x754 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x754 0.--7. 1. "PARAM,"
line.long 0x758 "INST235_0,"
line.long 0x75C "INST235_1,"
hexmask.long.byte 0x75C 25.--31. 1. "NU2,"
rbitfld.long 0x75C 24. "NU1," "0,1"
bitfld.long 0x75C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x75C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x75C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x75C 0.--7. 1. "PARAM,"
line.long 0x760 "INST236_0,"
line.long 0x764 "INST236_1,"
hexmask.long.byte 0x764 25.--31. 1. "NU2,"
rbitfld.long 0x764 24. "NU1," "0,1"
bitfld.long 0x764 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x764 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x764 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x764 0.--7. 1. "PARAM,"
line.long 0x768 "INST237_0,"
line.long 0x76C "INST237_1,"
hexmask.long.byte 0x76C 25.--31. 1. "NU2,"
rbitfld.long 0x76C 24. "NU1," "0,1"
bitfld.long 0x76C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x76C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x76C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x76C 0.--7. 1. "PARAM,"
line.long 0x770 "INST238_0,"
line.long 0x774 "INST238_1,"
hexmask.long.byte 0x774 25.--31. 1. "NU2,"
rbitfld.long 0x774 24. "NU1," "0,1"
bitfld.long 0x774 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x774 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x774 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x774 0.--7. 1. "PARAM,"
line.long 0x778 "INST239_0,"
line.long 0x77C "INST239_1,"
hexmask.long.byte 0x77C 25.--31. 1. "NU2,"
rbitfld.long 0x77C 24. "NU1," "0,1"
bitfld.long 0x77C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x77C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x77C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x77C 0.--7. 1. "PARAM,"
line.long 0x780 "INST240_0,"
line.long 0x784 "INST240_1,"
hexmask.long.byte 0x784 25.--31. 1. "NU2,"
rbitfld.long 0x784 24. "NU1," "0,1"
bitfld.long 0x784 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x784 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x784 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x784 0.--7. 1. "PARAM,"
line.long 0x788 "INST241_0,"
line.long 0x78C "INST241_1,"
hexmask.long.byte 0x78C 25.--31. 1. "NU2,"
rbitfld.long 0x78C 24. "NU1," "0,1"
bitfld.long 0x78C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x78C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x78C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x78C 0.--7. 1. "PARAM,"
line.long 0x790 "INST242_0,"
line.long 0x794 "INST242_1,"
hexmask.long.byte 0x794 25.--31. 1. "NU2,"
rbitfld.long 0x794 24. "NU1," "0,1"
bitfld.long 0x794 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x794 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x794 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x794 0.--7. 1. "PARAM,"
line.long 0x798 "INST243_0,"
line.long 0x79C "INST243_1,"
hexmask.long.byte 0x79C 25.--31. 1. "NU2,"
rbitfld.long 0x79C 24. "NU1," "0,1"
bitfld.long 0x79C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x79C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x79C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x79C 0.--7. 1. "PARAM,"
line.long 0x7A0 "INST244_0,"
line.long 0x7A4 "INST244_1,"
hexmask.long.byte 0x7A4 25.--31. 1. "NU2,"
rbitfld.long 0x7A4 24. "NU1," "0,1"
bitfld.long 0x7A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7A4 0.--7. 1. "PARAM,"
line.long 0x7A8 "INST245_0,"
line.long 0x7AC "INST245_1,"
hexmask.long.byte 0x7AC 25.--31. 1. "NU2,"
rbitfld.long 0x7AC 24. "NU1," "0,1"
bitfld.long 0x7AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7AC 0.--7. 1. "PARAM,"
line.long 0x7B0 "INST246_0,"
line.long 0x7B4 "INST246_1,"
hexmask.long.byte 0x7B4 25.--31. 1. "NU2,"
rbitfld.long 0x7B4 24. "NU1," "0,1"
bitfld.long 0x7B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7B4 0.--7. 1. "PARAM,"
line.long 0x7B8 "INST247_0,"
line.long 0x7BC "INST247_1,"
hexmask.long.byte 0x7BC 25.--31. 1. "NU2,"
rbitfld.long 0x7BC 24. "NU1," "0,1"
bitfld.long 0x7BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7BC 0.--7. 1. "PARAM,"
line.long 0x7C0 "INST248_0,"
line.long 0x7C4 "INST248_1,"
hexmask.long.byte 0x7C4 25.--31. 1. "NU2,"
rbitfld.long 0x7C4 24. "NU1," "0,1"
bitfld.long 0x7C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7C4 0.--7. 1. "PARAM,"
line.long 0x7C8 "INST249_0,"
line.long 0x7CC "INST249_1,"
hexmask.long.byte 0x7CC 25.--31. 1. "NU2,"
rbitfld.long 0x7CC 24. "NU1," "0,1"
bitfld.long 0x7CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7CC 0.--7. 1. "PARAM,"
line.long 0x7D0 "INST250_0,"
line.long 0x7D4 "INST250_1,"
hexmask.long.byte 0x7D4 25.--31. 1. "NU2,"
rbitfld.long 0x7D4 24. "NU1," "0,1"
bitfld.long 0x7D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7D4 0.--7. 1. "PARAM,"
line.long 0x7D8 "INST251_0,"
line.long 0x7DC "INST251_1,"
hexmask.long.byte 0x7DC 25.--31. 1. "NU2,"
rbitfld.long 0x7DC 24. "NU1," "0,1"
bitfld.long 0x7DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7DC 0.--7. 1. "PARAM,"
line.long 0x7E0 "INST252_0,"
line.long 0x7E4 "INST252_1,"
hexmask.long.byte 0x7E4 25.--31. 1. "NU2,"
rbitfld.long 0x7E4 24. "NU1," "0,1"
bitfld.long 0x7E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7E4 0.--7. 1. "PARAM,"
line.long 0x7E8 "INST253_0,"
line.long 0x7EC "INST253_1,"
hexmask.long.byte 0x7EC 25.--31. 1. "NU2,"
rbitfld.long 0x7EC 24. "NU1," "0,1"
bitfld.long 0x7EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7EC 0.--7. 1. "PARAM,"
line.long 0x7F0 "INST254_0,"
line.long 0x7F4 "INST254_1,"
hexmask.long.byte 0x7F4 25.--31. 1. "NU2,"
rbitfld.long 0x7F4 24. "NU1," "0,1"
bitfld.long 0x7F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7F4 0.--7. 1. "PARAM,"
line.long 0x7F8 "INST255_0,"
line.long 0x7FC "INST255_1,"
hexmask.long.byte 0x7FC 25.--31. 1. "NU2,"
rbitfld.long 0x7FC 24. "NU1," "0,1"
bitfld.long 0x7FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7FC 0.--7. 1. "PARAM,"
width 0x0B
tree.end
tree "MSS_GPADC_REG (MSS GPADC REG Module Registers)"
base ad:0x53F79800
group.long 0x00++0x4F
line.long 0x00 "REG0,gpadc modes and enable"
hexmask.long.word 0x00 17.--31. 1. "NU3,TI reserved"
bitfld.long 0x00 16. "GPADC_DEBUG_MODE_ENABLE," "0,1"
rbitfld.long 0x00 12.--15. "NU2,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9.--11. "GPADC2ADCBUF_PATH_EN,TI reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "GPADC_FSM_CLK_ENABLE,Enable the clock to gpadc fsm" "0,1"
rbitfld.long 0x00 2.--7. "NU1,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "DCBIST_MODE," "0,1,2,3"
line.long 0x04 "REG1,gpadc start trigger for Inter frame mode"
hexmask.long.byte 0x04 25.--31. 1. "NU4,TI reserved"
bitfld.long 0x04 24. "GPADC_START_BYP_VAL," "0,1"
hexmask.long.byte 0x04 17.--23. 1. "NU3,TI reserved"
bitfld.long 0x04 16. "GPADC_FSM_BYPASS," "0,1"
newline
hexmask.long.byte 0x04 9.--15. 1. "NU2,TI reserved"
bitfld.long 0x04 8. "GPADC_INIT,Resets the FSM and clears the data RAM" "0,1"
hexmask.long.byte 0x04 1.--7. 1. "NU1,TI reserved"
bitfld.long 0x04 0. "GPADC_TRIGGER,Generates a single cycle pulse to trigger the IFM mode" "0,1"
line.long 0x08 "REG2,gpadc config for IFM"
line.long 0x0C "REG3,gpadc param. skip samples and collect samples for IFM"
hexmask.long.word 0x0C 23.--31. 1. "NU,"
hexmask.long.byte 0x0C 16.--22. 1. "SKIP_SAMPLES_IFM,number of GPADC clocks to skip after trigger"
hexmask.long.byte 0x0C 8.--15. 1. "COLLECT_SAMPLES_IFM,number of GPADC readings to collect"
hexmask.long.byte 0x0C 0.--7. 1. "PARAM_VAL_IFM,Param value to be passed to analog in IFM mode(after one hot encoding)"
line.long 0x10 "REG4,Base address for Chirp profile 0 in instruction packet RAM"
hexmask.long.byte 0x10 24.--31. 1. "PKT_RAM_BASE_ADDR_CP3,TI reserved"
hexmask.long.byte 0x10 16.--23. 1. "PKT_RAM_BASE_ADDR_CP2,TI reserved"
hexmask.long.byte 0x10 8.--15. 1. "PKT_RAM_BASE_ADDR_CP1,(End-Address + 1) of instruction-ram in CTM mode"
hexmask.long.byte 0x10 0.--7. 1. "PKT_RAM_BASE_ADDR_CP0,Start Address of instruction-ram in CTM mode"
line.long 0x14 "REG5,Base address for Chirp profile 1 in instruction packet RAM"
hexmask.long.byte 0x14 24.--31. 1. "PKT_RAM_BASE_ADDR_CP7,TI reserved"
hexmask.long.byte 0x14 16.--23. 1. "PKT_RAM_BASE_ADDR_CP6,TI reserved"
hexmask.long.byte 0x14 8.--15. 1. "PKT_RAM_BASE_ADDR_CP5,TI reserved"
hexmask.long.byte 0x14 0.--7. 1. "PKT_RAM_BASE_ADDR_CP4,TI reserved"
line.long 0x18 "REG6,Base address for Chirp profile 2 in instruction packet RAM"
hexmask.long.byte 0x18 24.--31. 1. "PKT_RAM_BASE_ADDR_CP11,TI reserved"
hexmask.long.byte 0x18 16.--23. 1. "PKT_RAM_BASE_ADDR_CP10,TI reserved"
hexmask.long.byte 0x18 8.--15. 1. "PKT_RAM_BASE_ADDR_CP9,TI reserved"
hexmask.long.byte 0x18 0.--7. 1. "PKT_RAM_BASE_ADDR_CP8,TI reserved"
line.long 0x1C "REG7,Base address for Chirp profile 3 in instruction packet RAM"
hexmask.long.byte 0x1C 24.--31. 1. "PKT_RAM_BASE_ADDR_CP15,TI reserved"
hexmask.long.byte 0x1C 16.--23. 1. "PKT_RAM_BASE_ADDR_CP14,TI reserved"
hexmask.long.byte 0x1C 8.--15. 1. "PKT_RAM_BASE_ADDR_CP13,TI reserved"
hexmask.long.byte 0x1C 0.--7. 1. "PKT_RAM_BASE_ADDR_CP12,TI reserved"
line.long 0x20 "REG8,"
hexmask.long.tbyte 0x20 9.--31. 1. "NU,"
bitfld.long 0x20 8. "GPADC_CLK_ENABLE,TI reserved" "0,1"
hexmask.long.byte 0x20 0.--7. 1. "GPADC_CLK_DIV,TI reserved"
line.long 0x24 "REG9,"
line.long 0x28 "REG10,"
line.long 0x2C "REG11,"
line.long 0x30 "REG12,"
hexmask.long.byte 0x30 24.--31. 1. "DRAM_REPAIRED_BIT,TI reserved"
hexmask.long.byte 0x30 16.--23. 1. "DRAM_ECC_ERR_ADDR,TI reserved"
hexmask.long.byte 0x30 9.--15. 1. "NU2,TI reserved"
bitfld.long 0x30 8. "DRAM_ECC_ERR_CLR,TI reserved" "0,1"
newline
hexmask.long.byte 0x30 1.--7. 1. "NU1,TI reserved"
bitfld.long 0x30 0. "DRAM_ECC_ENABLE," "0,1"
line.long 0x34 "REG13,"
line.long 0x38 "REG14,Sum of GP ADC readings"
hexmask.long.word 0x38 20.--31. 1. "NU,TI reserved"
hexmask.long.tbyte 0x38 0.--19. 1. "SUM_IFM,Sum of GP ADC readings"
line.long 0x3C "REG15,Min and Max of GP ADC readings"
bitfld.long 0x3C 26.--31. "NU2,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x3C 16.--25. 1. "MAX_GPADC,Max of GPADC readings"
bitfld.long 0x3C 10.--15. "NU1,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x3C 0.--9. 1. "MIN_GPADC,Min of GPADC readings"
line.long 0x40 "REG16,"
hexmask.long 0x40 1.--31. 1. "NU,TI reserved"
bitfld.long 0x40 0. "GPADC_MEM_INIT_DONE_STAT,Status for Data Mem init done.Used for FW polling .Will read '0' when init process is under progress" "0,1"
line.long 0x44 "REG17,"
hexmask.long 0x44 1.--31. 1. "NU,TI reserved"
bitfld.long 0x44 0. "GPADC_IFM_DONE_STATUS,Test completion status in IFM mode.Used for FW polling" "0,1"
line.long 0x48 "REG18,"
hexmask.long 0x48 1.--31. 1. "NU,TI reserved"
bitfld.long 0x48 0. "GPADC_IFM_DONE_CLR,Clear 'ifm_done_status'" "0,1"
line.long 0x4C "REG19,"
hexmask.long.word 0x4C 16.--31. 1. "NU,TI reserved"
hexmask.long.word 0x4C 0.--15. 1. "GPADC_SAMPLES_FRAME,Total number of GPADC samples collected in a frame"
group.long 0x58++0x03
line.long 0x00 "REG22,"
repeat 2. (list 20. 21. )(list 0x00 0x04 )
rgroup.long ($2+0x50)++0x03
line.long 0x00 "REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_I2C (MSS I2C Module Registers)"
base ad:0x52F7B000
group.long 0x00++0x3F
line.long 0x00 "ICOAR,I2C Own Address register"
hexmask.long.tbyte 0x00 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x00 0.--9. 1. "A9_A0,Own address"
line.long 0x04 "ICIMR,I2C Interrupt Mask/Status register"
hexmask.long 0x04 7.--31. 1. "NU,Reserved"
bitfld.long 0x04 6. "AAS,Address As Slave interrupt mask bit" "0,1"
newline
bitfld.long 0x04 5. "SCD,Stop Condition Detection mask bit" "0,1"
bitfld.long 0x04 4. "ICXRDY,Transmit Data Ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 3. "ICRRDY,Receive Data Ready interrupt mask bit" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 1. "NACK,No Acknowledgement interrupt mask bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration Lost interrupt mask bit" "0,1"
line.long 0x08 "ICSTR,I2C Interrupt Status register"
hexmask.long.tbyte 0x08 15.--31. 1. "NU2,Reserved"
bitfld.long 0x08 14. "SDIR,Slave Direction" "0,1"
newline
bitfld.long 0x08 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'" "0,1"
bitfld.long 0x08 12. "BB,Bus Busy" "0,1"
newline
bitfld.long 0x08 11. "RSFULL,Receive shift full" "0,1"
bitfld.long 0x08 10. "XSMT,Transmit shift empty not" "0,1"
newline
bitfld.long 0x08 9. "AAS,Address As Slave" "0,1"
bitfld.long 0x08 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call)" "0,1"
newline
bitfld.long 0x08 6.--7. "NU1,Reserved" "0,1,2,3"
bitfld.long 0x08 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition" "0,1"
newline
bitfld.long 0x08 4. "ICXRDY,Transmit Data Ready interrupt flag bit" "0,1"
bitfld.long 0x08 3. "ICRRDY,Receive Data Ready interrupt flag bit" "0,1"
newline
bitfld.long 0x08 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
bitfld.long 0x08 1. "NACK,No-Acknowledgement interrupt flag bit" "0,1"
newline
bitfld.long 0x08 0. "AL,Arbitration-Lost interrupt flag bit" "0,1"
line.long 0x0C "ICCLKL,I2C Clock Divider Low register"
hexmask.long.word 0x0C 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "ICCL15_ICCL0,Low time I2C SCL Clock Division Factor"
line.long 0x10 "ICCLKH,I2C Clock Divider High register"
hexmask.long.word 0x10 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I2C SCL Clock Division Factor"
line.long 0x14 "ICCNT,I2C Data Count register"
hexmask.long.word 0x14 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count"
line.long 0x18 "ICDRR,I2C Data Receive register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data"
line.long 0x1C "ICSAR,I2C Slave Address register"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address"
line.long 0x20 "ICDXR,I2C Data Transmit register"
hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data"
line.long 0x24 "ICMDR,I2C Mode register"
hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved"
bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode" "0,1"
newline
bitfld.long 0x24 14. "FREE,Free Running" "0,1"
bitfld.long 0x24 13. "STT,Start Condition (Master only mode)" "0,1"
newline
bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509)" "0,1"
bitfld.long 0x24 11. "STP,Stop Condition (Master mode only)" "0,1"
newline
bitfld.long 0x24 10. "MST,Master" "0,1"
bitfld.long 0x24 9. "TRX,Transmitter" "0,1"
newline
bitfld.long 0x24 8. "XA,Expanded Address" "0,1"
bitfld.long 0x24 7. "RM,Repeat Mode" "0,1"
newline
bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only)" "0,1"
bitfld.long 0x24 5. "IRS,I2C Reset Not" "0,1"
newline
bitfld.long 0x24 4. "STB,Start Byte (Master only mode)" "0,1"
bitfld.long 0x24 3. "FDF,Free Data Format" "0,1"
newline
bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted" "0,1,2,3,4,5,6,7"
line.long 0x28 "ICIVR,I2C Interrupt Vector register"
hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved"
bitfld.long 0x28 8.--11. "TESTMD,Reserved for internal testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 3.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--2. "INTCODE,Interrupt code" "0,1,2,3,4,5,6,7"
line.long 0x2C "ICEMDR,I2C Extended Mode register"
hexmask.long 0x2C 2.--31. 1. "NU,Reserved"
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave" "0,1"
newline
bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode" "0,1"
line.long 0x30 "ICPSC,I2C Prescaler register"
hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module"
line.long 0x34 "ICPID1,I2C Peripheral ID register 1"
hexmask.long.word 0x34 16.--31. 1. "NU,Reserved"
hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral"
newline
hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C"
line.long 0x38 "ICPID2,I2C Peripheral ID register 2"
hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral"
line.long 0x3C "ICDMAC,I2C DMA Control Register"
hexmask.long 0x3C 2.--31. 1. "NU,Reserved"
bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable" "0,1"
newline
bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable" "0,1"
group.long 0x48++0x1B
line.long 0x00 "ICPFUNC,I2C Pin Function register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved"
bitfld.long 0x00 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins" "Pins function as SCL and SDA,Pins functions as GPIO"
line.long 0x04 "ICPDIR,I2C Pin Direction register"
hexmask.long 0x04 2.--31. 1. "NU,Reserved"
bitfld.long 0x04 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO" "SDA pin functions as input,SDA pin functions as output"
newline
bitfld.long 0x04 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO" "SCL pin functions as input,SCL pin functions as output"
line.long 0x08 "ICPDIN,I2C Pin Data In register"
hexmask.long 0x08 2.--31. 1. "NU,Reserved"
bitfld.long 0x08 1. "PDIN1,Indicates the logic level present on the SDA pin" "Logic low present at SDA pin regardless of PFUNC..,Logic high present at SDA pin regardless of.."
newline
bitfld.long 0x08 0. "PDIN0,Indicates the logic level present on the SCL pin" "Logic low present at SCL pin regardless of PFUNC..,Logic high present at SCL pin regardless of.."
line.long 0x0C "ICPDOUT,I2C Pin Data Out register"
hexmask.long 0x0C 2.--31. 1. "NU,Reserved"
bitfld.long 0x0C 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output" "SDA pin driven low,SDA pin driven high"
newline
bitfld.long 0x0C 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output" "SCL pin driven low,SCL pin driven high"
line.long 0x10 "ICPDSET,I2C Pin Data Set register"
hexmask.long 0x10 2.--31. 1. "NU,Reserved"
bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin" "no effect,PDOUT[1] bit is set to.."
newline
bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin" "no effect,PDOUT[0] bit is set to.."
line.long 0x14 "ICPDCLR,I2C Pin Data Clear register"
hexmask.long 0x14 2.--31. 1. "NU,Reserved"
bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin" "no effect,PDOUT[1] bit is cleared.."
newline
bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin" "no effect,PDOUT[0] bit is cleared.."
line.long 0x18 "ICPDRV,I2C Pin Driver Mode Register"
hexmask.long 0x18 2.--31. 1. "NU,Reserved"
bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin" "I2C mode,GPIO mode"
newline
bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin" "I2C mode,GPIO mode"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "I2C_RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_IOMUX (MSS IOMUX Module Registers)"
base ad:0x520C0000
group.long 0x00++0x1DF
line.long 0x00 "PADAA_cfg_reg,"
hexmask.long.tbyte 0x00 11.--31. 1. "NU,Reserved"
bitfld.long 0x00 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x00 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x00 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x00 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x00 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x00 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x00 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x00 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PADAB_cfg_reg,"
hexmask.long.tbyte 0x04 11.--31. 1. "NU,Reserved"
bitfld.long 0x04 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x04 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x04 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x04 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x04 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x04 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x04 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x04 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "PADAC_cfg_reg,"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved"
bitfld.long 0x08 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x08 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x08 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x08 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x08 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x08 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x08 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x08 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "PADAD_cfg_reg,"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved"
bitfld.long 0x0C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x0C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x0C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x0C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x0C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x0C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x0C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x0C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "PADAE_cfg_reg,"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved"
bitfld.long 0x10 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x10 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x10 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x10 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x10 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x10 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x10 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x10 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "PADAF_cfg_reg,"
hexmask.long.tbyte 0x14 11.--31. 1. "NU,Reserved"
bitfld.long 0x14 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x14 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x14 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x14 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x14 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x14 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x14 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x14 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "PADAG_cfg_reg,"
hexmask.long.tbyte 0x18 11.--31. 1. "NU,Reserved"
bitfld.long 0x18 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x18 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x18 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x18 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x18 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x18 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x18 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x18 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "PADAH_cfg_reg,"
hexmask.long.tbyte 0x1C 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "PADAI_cfg_reg,"
hexmask.long.tbyte 0x20 11.--31. 1. "NU,Reserved"
bitfld.long 0x20 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x20 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x20 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x20 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x20 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x20 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x20 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x20 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "PADAJ_cfg_reg,"
hexmask.long.tbyte 0x24 11.--31. 1. "NU,Reserved"
bitfld.long 0x24 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x24 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x24 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x24 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x24 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x24 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x24 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x24 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "PADAK_cfg_reg,"
hexmask.long.tbyte 0x28 11.--31. 1. "NU,Reserved"
bitfld.long 0x28 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x28 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x28 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x28 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x28 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x28 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x28 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x28 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "PADAL_cfg_reg,"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU,Reserved"
bitfld.long 0x2C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x2C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x2C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x2C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x2C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x2C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x2C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x2C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "PADAM_cfg_reg,"
hexmask.long.tbyte 0x30 11.--31. 1. "NU,Reserved"
bitfld.long 0x30 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x30 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x30 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x30 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x30 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x30 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x30 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x30 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "PADAN_cfg_reg,"
hexmask.long.tbyte 0x34 11.--31. 1. "NU,Reserved"
bitfld.long 0x34 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x34 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x34 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x34 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x34 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x34 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x34 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x34 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "PADAO_cfg_reg,"
hexmask.long.tbyte 0x38 11.--31. 1. "NU,Reserved"
bitfld.long 0x38 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x38 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x38 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x38 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x38 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x38 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x38 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x38 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "PADAP_cfg_reg,"
hexmask.long.tbyte 0x3C 11.--31. 1. "NU,Reserved"
bitfld.long 0x3C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x3C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x3C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x3C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x3C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x3C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x3C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x3C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "PADAQ_cfg_reg,"
hexmask.long.tbyte 0x40 11.--31. 1. "NU,Reserved"
bitfld.long 0x40 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x40 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x40 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x40 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x40 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x40 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x40 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x40 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "PADAR_cfg_reg,"
hexmask.long.tbyte 0x44 11.--31. 1. "NU,Reserved"
bitfld.long 0x44 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x44 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x44 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x44 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x44 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x44 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x44 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x44 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "PADAS_cfg_reg,"
hexmask.long.tbyte 0x48 11.--31. 1. "NU,Reserved"
bitfld.long 0x48 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x48 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x48 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x48 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x48 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x48 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x48 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x48 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "PADAT_cfg_reg,"
hexmask.long.tbyte 0x4C 11.--31. 1. "NU,Reserved"
bitfld.long 0x4C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x4C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x4C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x4C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x4C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x4C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x4C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x4C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "PADAU_cfg_reg,"
hexmask.long.tbyte 0x50 11.--31. 1. "NU,Reserved"
bitfld.long 0x50 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x50 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x50 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x50 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x50 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x50 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x50 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x50 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "PADAV_cfg_reg,"
hexmask.long.tbyte 0x54 11.--31. 1. "NU,Reserved"
bitfld.long 0x54 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x54 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x54 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x54 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x54 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x54 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x54 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x54 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "PADAW_cfg_reg,"
hexmask.long.tbyte 0x58 11.--31. 1. "NU,Reserved"
bitfld.long 0x58 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x58 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x58 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x58 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x58 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x58 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x58 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x58 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "PADAX_cfg_reg,"
hexmask.long.tbyte 0x5C 11.--31. 1. "NU,Reserved"
bitfld.long 0x5C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x5C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x5C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x5C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x5C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x5C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x5C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x5C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x60 "PADAY_cfg_reg,"
hexmask.long.tbyte 0x60 11.--31. 1. "NU,Reserved"
bitfld.long 0x60 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x60 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x60 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x60 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x60 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x60 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x60 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x60 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "PADAZ_cfg_reg,"
hexmask.long.tbyte 0x64 11.--31. 1. "NU,Reserved"
bitfld.long 0x64 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x64 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x64 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x64 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x64 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x64 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x64 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x64 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "PADBA_cfg_reg,"
hexmask.long.tbyte 0x68 11.--31. 1. "NU,Reserved"
bitfld.long 0x68 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x68 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x68 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x68 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x68 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x68 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x68 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x68 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "PADBB_cfg_reg,"
hexmask.long.tbyte 0x6C 11.--31. 1. "NU,Reserved"
bitfld.long 0x6C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x6C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x6C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x6C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x6C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x6C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x6C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x6C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "PADBC_cfg_reg,"
hexmask.long.tbyte 0x70 11.--31. 1. "NU,Reserved"
bitfld.long 0x70 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x70 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x70 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x70 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x70 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x70 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x70 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x70 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x74 "PADBD_cfg_reg,"
hexmask.long.tbyte 0x74 11.--31. 1. "NU,Reserved"
bitfld.long 0x74 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x74 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x74 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x74 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x74 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x74 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x74 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x74 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x78 "PADBE_cfg_reg,"
hexmask.long.tbyte 0x78 11.--31. 1. "NU,Reserved"
bitfld.long 0x78 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x78 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x78 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x78 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x78 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x78 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x78 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x78 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x7C "PADBF_cfg_reg,"
hexmask.long.tbyte 0x7C 11.--31. 1. "NU,Reserved"
bitfld.long 0x7C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x7C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x7C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x7C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x7C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x7C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x7C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x7C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x80 "PADBG_cfg_reg,"
hexmask.long.tbyte 0x80 11.--31. 1. "NU,Reserved"
bitfld.long 0x80 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x80 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x80 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x80 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x80 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x80 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x80 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x80 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "PADBH_cfg_reg,"
hexmask.long.tbyte 0x84 11.--31. 1. "NU,Reserved"
bitfld.long 0x84 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x84 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x84 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x84 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x84 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x84 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x84 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x84 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "PADBI_cfg_reg,"
hexmask.long.tbyte 0x88 11.--31. 1. "NU,Reserved"
bitfld.long 0x88 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x88 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x88 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x88 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x88 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x88 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x88 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x88 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "PADBJ_cfg_reg,"
hexmask.long.tbyte 0x8C 11.--31. 1. "NU,Reserved"
bitfld.long 0x8C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x8C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x8C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x8C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x8C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x8C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x8C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x8C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "PADBK_cfg_reg,"
hexmask.long.tbyte 0x90 11.--31. 1. "NU,Reserved"
bitfld.long 0x90 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x90 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x90 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x90 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x90 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x90 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x90 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x90 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x94 "PADBL_cfg_reg,"
hexmask.long.tbyte 0x94 11.--31. 1. "NU,Reserved"
bitfld.long 0x94 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x94 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x94 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x94 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x94 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x94 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x94 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x94 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x98 "PADBM_cfg_reg,"
hexmask.long.tbyte 0x98 11.--31. 1. "NU,Reserved"
bitfld.long 0x98 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x98 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x98 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x98 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x98 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x98 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x98 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x98 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "PADBN_cfg_reg,"
hexmask.long.tbyte 0x9C 11.--31. 1. "NU,Reserved"
bitfld.long 0x9C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x9C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x9C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x9C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x9C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x9C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x9C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x9C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA0 "PADBO_cfg_reg,"
hexmask.long.tbyte 0xA0 11.--31. 1. "NU,Reserved"
bitfld.long 0xA0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xA0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xA0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xA0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xA0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xA0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xA0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xA0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "PADBP_cfg_reg,"
hexmask.long.tbyte 0xA4 11.--31. 1. "NU,Reserved"
bitfld.long 0xA4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xA4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xA4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xA4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xA4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xA4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xA4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xA4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA8 "PADBQ_cfg_reg,"
hexmask.long.tbyte 0xA8 11.--31. 1. "NU,Reserved"
bitfld.long 0xA8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xA8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xA8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xA8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xA8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xA8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xA8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xA8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xAC "PADBR_cfg_reg,"
hexmask.long.tbyte 0xAC 11.--31. 1. "NU,Reserved"
bitfld.long 0xAC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xAC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xAC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xAC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xAC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xAC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xAC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xAC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB0 "PADBS_cfg_reg,"
hexmask.long.tbyte 0xB0 11.--31. 1. "NU,Reserved"
bitfld.long 0xB0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xB0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xB0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xB0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xB0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xB0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xB0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xB0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB4 "PADBT_cfg_reg,"
hexmask.long.tbyte 0xB4 11.--31. 1. "NU,Reserved"
bitfld.long 0xB4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xB4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xB4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xB4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xB4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xB4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xB4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xB4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "PADBU_cfg_reg,"
hexmask.long.tbyte 0xB8 11.--31. 1. "NU,Reserved"
bitfld.long 0xB8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xB8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xB8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xB8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xB8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xB8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xB8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xB8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xBC "PADBV_cfg_reg,"
hexmask.long.tbyte 0xBC 11.--31. 1. "NU,Reserved"
bitfld.long 0xBC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xBC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xBC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xBC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xBC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xBC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xBC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xBC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC0 "PADBW_cfg_reg,"
hexmask.long.tbyte 0xC0 11.--31. 1. "NU,Reserved"
bitfld.long 0xC0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xC0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xC0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xC0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xC0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xC0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xC0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xC0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "PADBX_cfg_reg,"
hexmask.long.tbyte 0xC4 11.--31. 1. "NU,Reserved"
bitfld.long 0xC4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xC4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xC4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xC4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xC4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xC4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xC4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xC4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "PADBY_cfg_reg,"
hexmask.long.tbyte 0xC8 11.--31. 1. "NU,Reserved"
bitfld.long 0xC8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xC8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xC8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xC8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xC8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xC8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xC8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xC8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "PADBZ_cfg_reg,"
hexmask.long.tbyte 0xCC 11.--31. 1. "NU,Reserved"
bitfld.long 0xCC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xCC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xCC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xCC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xCC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xCC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xCC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xCC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD0 "PADCA_cfg_reg,"
hexmask.long.tbyte 0xD0 11.--31. 1. "NU,Reserved"
bitfld.long 0xD0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xD0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xD0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xD0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xD0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xD0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xD0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xD0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "PADCB_cfg_reg,"
hexmask.long.tbyte 0xD4 11.--31. 1. "NU,Reserved"
bitfld.long 0xD4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xD4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xD4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xD4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xD4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xD4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xD4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xD4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD8 "PADCC_cfg_reg,"
hexmask.long.tbyte 0xD8 11.--31. 1. "NU,Reserved"
bitfld.long 0xD8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xD8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xD8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xD8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xD8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xD8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xD8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xD8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "PADCD_cfg_reg,"
hexmask.long.tbyte 0xDC 11.--31. 1. "NU,Reserved"
bitfld.long 0xDC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xDC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xDC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xDC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xDC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xDC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xDC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xDC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE0 "PADCE_cfg_reg,"
hexmask.long.tbyte 0xE0 11.--31. 1. "NU,Reserved"
bitfld.long 0xE0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xE0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xE0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xE0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xE0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xE0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xE0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xE0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "PADCF_cfg_reg,"
hexmask.long.tbyte 0xE4 11.--31. 1. "NU,Reserved"
bitfld.long 0xE4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xE4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xE4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xE4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xE4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xE4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xE4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xE4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE8 "PADCG_cfg_reg,"
hexmask.long.tbyte 0xE8 11.--31. 1. "NU,Reserved"
bitfld.long 0xE8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xE8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xE8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xE8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xE8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xE8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xE8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xE8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "PADCH_cfg_reg,"
hexmask.long.tbyte 0xEC 11.--31. 1. "NU,Reserved"
bitfld.long 0xEC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xEC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xEC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xEC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xEC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xEC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xEC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xEC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF0 "PADCI_cfg_reg,"
hexmask.long.tbyte 0xF0 11.--31. 1. "NU,Reserved"
bitfld.long 0xF0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xF0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xF0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xF0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xF0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xF0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xF0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xF0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "PADCJ_cfg_reg,"
hexmask.long.tbyte 0xF4 11.--31. 1. "NU,Reserved"
bitfld.long 0xF4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xF4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xF4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xF4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xF4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xF4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xF4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xF4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF8 "PADCK_cfg_reg,"
hexmask.long.tbyte 0xF8 11.--31. 1. "NU,Reserved"
bitfld.long 0xF8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xF8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xF8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xF8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xF8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xF8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xF8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xF8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "PADCL_cfg_reg,"
hexmask.long.tbyte 0xFC 11.--31. 1. "NU,Reserved"
bitfld.long 0xFC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xFC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xFC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xFC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xFC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xFC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xFC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xFC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x100 "PADCM_cfg_reg,"
hexmask.long.tbyte 0x100 11.--31. 1. "NU,Reserved"
bitfld.long 0x100 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x100 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x100 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x100 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x100 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x100 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x100 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x100 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "PADCN_cfg_reg,"
hexmask.long.tbyte 0x104 11.--31. 1. "NU,Reserved"
bitfld.long 0x104 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x104 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x104 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x104 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x104 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x104 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x104 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x104 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x108 "PADCO_cfg_reg,"
hexmask.long.tbyte 0x108 11.--31. 1. "NU,Reserved"
bitfld.long 0x108 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x108 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x108 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x108 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x108 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x108 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x108 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x108 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10C "PADCP_cfg_reg,"
hexmask.long.tbyte 0x10C 11.--31. 1. "NU,Reserved"
bitfld.long 0x10C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x10C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x10C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x10C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x10C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x10C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x10C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x10C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x110 "PADCQ_cfg_reg,"
hexmask.long.tbyte 0x110 11.--31. 1. "NU,Reserved"
bitfld.long 0x110 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x110 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x110 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x110 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x110 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x110 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x110 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x110 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x114 "PADCR_cfg_reg,"
hexmask.long.tbyte 0x114 11.--31. 1. "NU,Reserved"
bitfld.long 0x114 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x114 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x114 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x114 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x114 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x114 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x114 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x114 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x118 "PADCS_cfg_reg,"
hexmask.long.tbyte 0x118 11.--31. 1. "NU,Reserved"
bitfld.long 0x118 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x118 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x118 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x118 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x118 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x118 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x118 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x118 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x11C "PADCT_cfg_reg,"
hexmask.long.tbyte 0x11C 11.--31. 1. "NU,Reserved"
bitfld.long 0x11C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x11C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x11C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x11C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x11C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x11C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x11C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x11C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x120 "PADCU_cfg_reg,"
hexmask.long.tbyte 0x120 11.--31. 1. "NU,Reserved"
bitfld.long 0x120 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x120 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x120 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x120 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x120 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x120 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x120 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x120 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "PADCV_cfg_reg,"
hexmask.long.tbyte 0x124 11.--31. 1. "NU,Reserved"
bitfld.long 0x124 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x124 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x124 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x124 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x124 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x124 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x124 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x124 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x128 "PADCW_cfg_reg,"
hexmask.long.tbyte 0x128 11.--31. 1. "NU,Reserved"
bitfld.long 0x128 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x128 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x128 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x128 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x128 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x128 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x128 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x128 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x12C "PADCX_cfg_reg,"
hexmask.long.tbyte 0x12C 11.--31. 1. "NU,Reserved"
bitfld.long 0x12C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x12C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x12C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x12C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x12C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x12C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x12C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x12C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x130 "PADCY_cfg_reg,"
hexmask.long.tbyte 0x130 11.--31. 1. "NU,Reserved"
bitfld.long 0x130 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x130 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x130 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x130 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x130 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x130 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x130 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x130 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x134 "PADCZ_cfg_reg,"
hexmask.long.tbyte 0x134 11.--31. 1. "NU,Reserved"
bitfld.long 0x134 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x134 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x134 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x134 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x134 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x134 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x134 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x134 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x138 "PADDA_cfg_reg,"
hexmask.long.tbyte 0x138 11.--31. 1. "NU,Reserved"
bitfld.long 0x138 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x138 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x138 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x138 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x138 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x138 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x138 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x138 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x13C "PADDB_cfg_reg,"
hexmask.long.tbyte 0x13C 11.--31. 1. "NU,Reserved"
bitfld.long 0x13C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x13C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x13C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x13C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x13C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x13C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x13C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x13C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x140 "PADDC_cfg_reg,"
hexmask.long.tbyte 0x140 11.--31. 1. "NU,Reserved"
bitfld.long 0x140 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x140 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x140 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x140 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x140 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x140 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x140 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x140 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "PADDD_cfg_reg,"
hexmask.long.tbyte 0x144 11.--31. 1. "NU,Reserved"
bitfld.long 0x144 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x144 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x144 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x144 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x144 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x144 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x144 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x144 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x148 "PADDE_cfg_reg,"
hexmask.long.tbyte 0x148 11.--31. 1. "NU,Reserved"
bitfld.long 0x148 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x148 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x148 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x148 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x148 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x148 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x148 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x148 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14C "PADDF_cfg_reg,"
hexmask.long.tbyte 0x14C 11.--31. 1. "NU,Reserved"
bitfld.long 0x14C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x14C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x14C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x14C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x14C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x14C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x14C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x14C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x150 "PADDG_cfg_reg,"
hexmask.long.tbyte 0x150 11.--31. 1. "NU,Reserved"
bitfld.long 0x150 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x150 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x150 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x150 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x150 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x150 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x150 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x150 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x154 "PADDH_cfg_reg,"
hexmask.long.tbyte 0x154 11.--31. 1. "NU,Reserved"
bitfld.long 0x154 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x154 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x154 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x154 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x154 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x154 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x154 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x154 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x158 "PADDI_cfg_reg,"
hexmask.long.tbyte 0x158 11.--31. 1. "NU,Reserved"
bitfld.long 0x158 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x158 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x158 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x158 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x158 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x158 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x158 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x158 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x15C "PADDJ_cfg_reg,"
hexmask.long.tbyte 0x15C 11.--31. 1. "NU,Reserved"
bitfld.long 0x15C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x15C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x15C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x15C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x15C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x15C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x15C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x15C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x160 "PADDK_cfg_reg,"
hexmask.long.tbyte 0x160 11.--31. 1. "NU,Reserved"
bitfld.long 0x160 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x160 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x160 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x160 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x160 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x160 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x160 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x160 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "PADDL_cfg_reg,"
hexmask.long.tbyte 0x164 11.--31. 1. "NU,Reserved"
bitfld.long 0x164 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x164 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x164 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x164 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x164 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x164 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x164 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x164 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x168 "PADDM_cfg_reg,"
hexmask.long.tbyte 0x168 11.--31. 1. "NU,Reserved"
bitfld.long 0x168 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x168 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x168 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x168 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x168 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x168 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x168 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x168 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "PADDN_cfg_reg,"
hexmask.long.tbyte 0x16C 11.--31. 1. "NU,Reserved"
bitfld.long 0x16C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x16C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x16C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x16C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x16C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x16C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x16C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x16C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x170 "PADDO_cfg_reg,"
hexmask.long.tbyte 0x170 11.--31. 1. "NU,Reserved"
bitfld.long 0x170 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x170 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x170 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x170 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x170 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x170 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x170 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x170 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "PADDP_cfg_reg,"
hexmask.long.tbyte 0x174 11.--31. 1. "NU,Reserved"
bitfld.long 0x174 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x174 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x174 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x174 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x174 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x174 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x174 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x174 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x178 "PADDQ_cfg_reg,"
hexmask.long.tbyte 0x178 11.--31. 1. "NU,Reserved"
bitfld.long 0x178 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x178 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x178 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x178 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x178 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x178 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x178 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x178 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "PADDR_cfg_reg,"
hexmask.long.tbyte 0x17C 11.--31. 1. "NU,Reserved"
bitfld.long 0x17C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x17C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x17C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x17C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x17C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x17C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x17C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x17C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x180 "PADDS_cfg_reg,"
hexmask.long.tbyte 0x180 11.--31. 1. "NU,Reserved"
bitfld.long 0x180 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x180 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x180 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x180 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x180 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x180 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x180 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x180 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "PADDT_cfg_reg,"
hexmask.long.tbyte 0x184 11.--31. 1. "NU,Reserved"
bitfld.long 0x184 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x184 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x184 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x184 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x184 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x184 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x184 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x184 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x188 "PADDU_cfg_reg,"
hexmask.long.tbyte 0x188 11.--31. 1. "NU,Reserved"
bitfld.long 0x188 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x188 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x188 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x188 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x188 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x188 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x188 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x188 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "PADDV_cfg_reg,"
hexmask.long.tbyte 0x18C 11.--31. 1. "NU,Reserved"
bitfld.long 0x18C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x18C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x18C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x18C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x18C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x18C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x18C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x18C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "PADDW_cfg_reg,"
hexmask.long.tbyte 0x190 11.--31. 1. "NU,Reserved"
bitfld.long 0x190 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x190 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x190 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x190 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x190 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x190 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x190 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x190 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "PADDX_cfg_reg,"
hexmask.long.tbyte 0x194 11.--31. 1. "NU,Reserved"
bitfld.long 0x194 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x194 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x194 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x194 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x194 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x194 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x194 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x194 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x198 "PADDY_cfg_reg,"
hexmask.long.tbyte 0x198 11.--31. 1. "NU,Reserved"
bitfld.long 0x198 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x198 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x198 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x198 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x198 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x198 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x198 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x198 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "PADDZ_cfg_reg,"
hexmask.long.tbyte 0x19C 11.--31. 1. "NU,Reserved"
bitfld.long 0x19C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x19C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x19C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x19C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x19C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x19C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x19C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x19C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "PADEA_cfg_reg,"
hexmask.long.tbyte 0x1A0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1A0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1A0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1A0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1A0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1A0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1A0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1A0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1A0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "PADEB_cfg_reg,"
hexmask.long.tbyte 0x1A4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1A4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1A4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1A4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1A4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1A4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1A4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1A4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1A4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "PADEC_cfg_reg,"
hexmask.long.tbyte 0x1A8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1A8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1A8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1A8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1A8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1A8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1A8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1A8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1A8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "PADED_cfg_reg,"
hexmask.long.tbyte 0x1AC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1AC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1AC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1AC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1AC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1AC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1AC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1AC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1AC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "PADEE_cfg_reg,"
hexmask.long.tbyte 0x1B0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1B0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1B0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1B0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1B0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1B0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1B0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1B0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1B0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "PADEF_cfg_reg,"
hexmask.long.tbyte 0x1B4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1B4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1B4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1B4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1B4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1B4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1B4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1B4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1B4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B8 "PADEG_cfg_reg,"
hexmask.long.tbyte 0x1B8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1B8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1B8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1B8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1B8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1B8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1B8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1B8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1B8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "PADEH_cfg_reg,"
hexmask.long.tbyte 0x1BC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1BC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1BC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1BC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1BC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1BC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1BC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1BC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1BC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C0 "PADEI_cfg_reg,"
hexmask.long.tbyte 0x1C0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "PADEJ_cfg_reg,"
hexmask.long.tbyte 0x1C4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C8 "PADEK_cfg_reg,"
hexmask.long.tbyte 0x1C8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "PADEL_cfg_reg,"
hexmask.long.tbyte 0x1CC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1CC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1CC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1CC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1CC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1CC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1CC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1CC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1CC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "PADEM_cfg_reg,"
hexmask.long.tbyte 0x1D0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1D0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1D0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1D0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1D0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1D0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1D0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1D0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1D0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "PADEN_cfg_reg,"
hexmask.long.tbyte 0x1D4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1D4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1D4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1D4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1D4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1D4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1D4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1D4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1D4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D8 "PADEO_cfg_reg,"
hexmask.long.tbyte 0x1D8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1D8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1D8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1D8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1D8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1D8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1D8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1D8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1D8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "PADEP_cfg_reg,"
hexmask.long.tbyte 0x1DC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1DC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1DC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1DC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1DC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1DC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1DC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1DC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1DC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1F0++0x0F
line.long 0x00 "USERMODEEN,"
line.long 0x04 "PADGLBLCFGREG,"
line.long 0x08 "IOCFGKICK0,"
line.long 0x0C "IOCFGKICK1,"
width 0x0B
tree.end
tree "MSS_MCANA_CFG (MSS MCANA Configuration Module Registers)"
base ad:0x52F7FC00
rgroup.long 0x00++0x2B
line.long 0x00 "SS_PID,SS_PID"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SS_CTRL,SS_CTRL"
hexmask.long 0x04 7.--31. 1. "NU0,Reserved"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
bitfld.long 0x04 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1"
newline
rbitfld.long 0x04 0.--2. "NU,Reserved" "0,1,2,3,4,5,6,7"
line.long 0x08 "SS_STAT,SS_STAT"
hexmask.long 0x08 3.--31. 1. "NU1,Reserved"
bitfld.long 0x08 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MMI_DONE," "0,1"
bitfld.long 0x08 0. "NU,Reserved" "0,1"
line.long 0x0C "SS_ICS,SS_ICS"
hexmask.long 0x0C 1.--31. 1. "NU2,Reserved"
bitfld.long 0x0C 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x10 "SS_IRS,SS_IRS"
hexmask.long 0x10 1.--31. 1. "NU3,Reserved"
bitfld.long 0x10 0. "IRS,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x14 "SS_IECS,SS_IECS"
hexmask.long 0x14 1.--31. 1. "NU4,Reserved"
bitfld.long 0x14 0. "IECS,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x18 "SS_IE,SS_IE"
hexmask.long 0x18 1.--31. 1. "NU5,Reserved"
bitfld.long 0x18 0. "IE,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x1C "SS_IES,SS_IES"
hexmask.long 0x1C 1.--31. 1. "NU6,Reserved"
bitfld.long 0x1C 0. "IES,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "SS_EOI,SS_EOI"
hexmask.long.tbyte 0x20 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targeted interrupt"
line.long 0x24 "SS_EXT_TS_PS,SS_EXT_TS_PS"
hexmask.long.byte 0x24 24.--31. 1. "NU8,Reserved"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value"
line.long 0x28 "SS_EXT_TS_USIC,SS_EXT_TS_USIC"
hexmask.long 0x28 5.--31. 1. "NU9,Reserved"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x200++0x2F
line.long 0x00 "CREL,CREL"
bitfld.long 0x00 28.--31. "REL,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month"
newline
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x04 "ENDN,ENDN"
line.long 0x08 "CUST,CUST"
line.long 0x0C "DBTP,DBTP"
hexmask.long.byte 0x0C 24.--31. 1. "NU13,Reserved"
bitfld.long 0x0C 23. "TDC,Transmitter Delay Compensation" "0,1"
rbitfld.long 0x0C 21.--22. "NU12,Reserved" "0,1,2,3"
bitfld.long 0x0C 16.--20. "DBRP,Data Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x0C 13.--15. "NU11,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8.--12. "DTSEG1,Data time segment before smaple point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "DSJW,Data resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "TEST,TEST"
hexmask.long.tbyte 0x10 8.--31. 1. "NU15,Reserved"
rbitfld.long 0x10 7. "RX,Receive Pin" "0,1"
bitfld.long 0x10 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x10 4. "LBCK,Loop Back Mode" "0,1"
rbitfld.long 0x10 0.--3. "NU14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "RWD,RWD"
hexmask.long.word 0x14 16.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x14 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x14 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x18 "CCCR,CCCR"
hexmask.long.tbyte 0x18 15.--31. 1. "NU18,Reserved"
bitfld.long 0x18 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x18 13. "EFBI,Edge Filtering durign Bus Integration" "0,1"
bitfld.long 0x18 12. "PXHD,Protocol Exception Handling Disable" "0,1"
rbitfld.long 0x18 10.--11. "NU17,Reserved" "0,1,2,3"
newline
bitfld.long 0x18 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x18 8. "FDOE,FD Operation Enable" "0,1"
bitfld.long 0x18 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x18 6. "DAR,Disable Automatic Regransmission" "0,1"
bitfld.long 0x18 5. "MON,Bus Monitoring Mode" "0,1"
newline
bitfld.long 0x18 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x18 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x18 2. "ASM,Restriced Operation Mode" "0,1"
bitfld.long 0x18 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x18 0. "INIT,Initialization" "0,1"
line.long 0x1C "NBTP,NBTP"
hexmask.long.byte 0x1C 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x1C 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x1C 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
rbitfld.long 0x1C 7. "NU19,Reserved" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x20 "TSCC,TSCC"
hexmask.long.word 0x20 20.--31. 1. "NU21,Reserved"
bitfld.long 0x20 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 2.--15. 1. "NU20,Reserved"
bitfld.long 0x20 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x24 "TSCV,TSCV"
hexmask.long.word 0x24 16.--31. 1. "NU22,Reserved"
hexmask.long.word 0x24 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x28 "TOCC,TOCC"
hexmask.long.word 0x28 16.--31. 1. "TOP,Timeout Period"
hexmask.long.word 0x28 3.--15. 1. "NU23,Reserved"
bitfld.long 0x28 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x28 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x2C "TOCV,TOCV"
hexmask.long.word 0x2C 16.--31. 1. "NU24,Reserved"
hexmask.long.word 0x2C 0.--15. 1. "TOC,Timeout Counter"
rgroup.long 0x240++0x0B
line.long 0x00 "ECR,ECR"
hexmask.long.byte 0x00 24.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x00 15. "RP,Recieve Error Passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Recieve Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x04 "PSR,PSR"
hexmask.long.word 0x04 23.--31. 1. "NU27,Reserved"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x04 15. "NU26,Reserved" "0,1"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x04 13. "RFDF,Recieved a CAN FD Message" "0,1"
newline
bitfld.long 0x04 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x04 6. "EW,Warning Status" "0,1"
newline
bitfld.long 0x04 5. "EP,Error Passive" "0,1"
bitfld.long 0x04 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
line.long 0x08 "TDCR,TDCR"
hexmask.long.tbyte 0x08 15.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
rbitfld.long 0x08 7. "NU28,Reserved" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x250++0x0F
line.long 0x00 "IR,IR"
rbitfld.long 0x00 30.--31. "NU30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0,1"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning Status" "0,1"
bitfld.long 0x00 23. "EP,Error Passive" "0,1"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0,1"
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0,1"
newline
bitfld.long 0x00 20. "BEC,Bit Error Corrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0,1"
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0,1"
newline
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0,1"
newline
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission Complete" "0,1"
bitfld.long 0x00 8. "HPM,High Priority Message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0,1"
newline
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0x04 "IE,IE"
rbitfld.long 0x04 30.--31. "NU31,Reserved" "0,1,2,3"
bitfld.long 0x04 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "0,1"
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
newline
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
newline
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
newline
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1"
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x04 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0x04 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
newline
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x08 "ILS,ILS"
rbitfld.long 0x08 30.--31. "NU32,Reserved" "0,1,2,3"
bitfld.long 0x08 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "0,1"
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
newline
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
newline
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
newline
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x08 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x08 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
newline
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x0C "ILE,ILE"
hexmask.long 0x0C 2.--31. 1. "NU33,Reserved"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "0,1"
group.long 0x280++0x0B
line.long 0x00 "GFC,GFC"
hexmask.long 0x00 6.--31. 1. "NU34,Reserved"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,reject Remote Frames Standard" "0,1"
bitfld.long 0x00 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x04 "SIDFC,SIDFC"
hexmask.long.byte 0x04 24.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "LSS_S,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA_S,Filter List Standard Start Address"
rbitfld.long 0x04 0.--1. "NU35,Reserved" "0,1,2,3"
line.long 0x08 "XIDFC,XIDFC"
hexmask.long.byte 0x08 24.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x08 16.--23. 1. "LSS_X,List Size Standard"
hexmask.long.word 0x08 2.--15. 1. "FLSSA_X,Filter List Standard Start Address"
rbitfld.long 0x08 0.--1. "NU37,Reserved" "0,1,2,3"
group.long 0x290++0x57
line.long 0x00 "XIDAM,XIDAM"
rbitfld.long 0x00 29.--31. "NU39,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
line.long 0x04 "HPMS,HPMS"
hexmask.long.word 0x04 16.--31. 1. "NU40,Reserved"
bitfld.long 0x04 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x04 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "NDAT1,NDAT1"
line.long 0x0C "NDAT2,NDAT2"
line.long 0x10 "RXF0C,RXF0C"
bitfld.long 0x10 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
rbitfld.long 0x10 23. "NU42_1,Reserved" "0,1"
hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size"
rbitfld.long 0x10 15. "NU42,Reserved" "0,1"
newline
hexmask.long.word 0x10 2.--14. 1. "F0SA,Rx FIFO 0 Start Address"
rbitfld.long 0x10 0.--1. "NU41,Reserved" "0,1,2,3"
line.long 0x14 "RXF0S,RXF0S"
bitfld.long 0x14 26.--31. "NU46,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x14 22.--23. "NU45,Reserved" "0,1,2,3"
bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 14.--15. "NU44,Reserved" "0,1,2,3"
bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 7. "NU43,Reserved" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
line.long 0x18 "RXF0A,RXF0A"
hexmask.long 0x18 6.--31. 1. "NU47,Reserved"
bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "RXBC,RXBC"
hexmask.long.word 0x1C 16.--31. 1. "NU49,Reserved"
hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address"
rbitfld.long 0x1C 0.--1. "NU48,Reserved" "0,1,2,3"
line.long 0x20 "RXF1C,RXF1C"
bitfld.long 0x20 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 0 Watermark"
rbitfld.long 0x20 23. "NU50_1,Reserved" "0,1"
hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 0 Size"
rbitfld.long 0x20 15. "NU50,Reserved" "0,1"
newline
hexmask.long.word 0x20 2.--14. 1. "F1SA,Rx FIFO 0 Start Address"
rbitfld.long 0x20 0.--1. "NU499,Reserved" "0,1,2,3"
line.long 0x24 "RXF1S,RXF1S"
bitfld.long 0x24 26.--31. "NU54,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 25. "RF1L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x24 24. "F1F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x24 22.--23. "NU53,Reserved" "0,1,2,3"
bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 14.--15. "NU52,Reserved" "0,1,2,3"
bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 7. "NU51,Reserved" "0,1"
hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level"
line.long 0x28 "RXF1A,RXF1A"
hexmask.long 0x28 6.--31. 1. "NU55,Reserved"
bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "RXESC,RXESC"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU58,Reserved"
bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 7. "NU57,Reserved" "0,1"
bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 3. "NU56,Reserved" "0,1"
newline
bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x30 "TXBC,TXBC"
bitfld.long 0x30 31. "NU61,Reserved" "0,1"
bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x30 22.--23. "NU60,Reserved" "0,1,2,3"
bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address"
bitfld.long 0x30 0.--1. "NU59,Reserved" "0,1,2,3"
line.long 0x34 "TXFQS,TXFQS"
hexmask.long.word 0x34 22.--31. 1. "NU64,Reserved"
bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "0,1"
bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 13.--15. "NU63,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x34 8.--12. "TFGI,Tx Queue Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 6.--7. "NU62,Reserved" "0,1,2,3"
bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "TXESC,TXESC"
hexmask.long 0x38 3.--31. 1. "NU65,Reserved"
bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x3C "TXBRP,TXBRP"
line.long 0x40 "TXBAR,TXBAR"
line.long 0x44 "TXBCR,TXBCR"
line.long 0x48 "TXBTO,TXBTO"
line.long 0x4C "TXBCF,TXBCF"
line.long 0x50 "TXBTIE,TXBTIE"
line.long 0x54 "TXBCIE,TXBCIE"
group.long 0x2F0++0x0F
line.long 0x00 "TXEFC,TXEFC"
bitfld.long 0x00 30.--31. "NU68,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 22.--23. "NU67,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
newline
bitfld.long 0x00 0.--1. "NU66,Reserved" "0,1,2,3"
line.long 0x04 "TXEFS,TXEFS"
bitfld.long 0x04 26.--31. "NU72,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x04 24. "EFF,Event FIFO Full" "0,1"
bitfld.long 0x04 21.--23. "NU71,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 13.--15. "NU70,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--7. "NU69,Reserved" "0,1,2,3"
bitfld.long 0x04 0.--5. "EFFL,Event FIFO FIll Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "TXEFA,TXEFA"
hexmask.long 0x08 5.--31. 1. "NU73,Reserved"
bitfld.long 0x08 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "RES16,RES16"
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C 0xB8 0xBC )
rgroup.long ($2+0x230)++0x03
line.long 0x00 "RES$1,RES00"
repeat.end
width 0x0B
tree.end
tree "MSS_MCANA_ECC (MSS MCANA ECC Module Registers)"
base ad:0x52F7F800
rgroup.long 0x00++0x03
line.long 0x00 "REV,Aggregator Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "VECTOR,ECC Vector Register"
hexmask.long.byte 0x00 25.--31. 1. "NU1,Reserved"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDR,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
rbitfld.long 0x00 11.--14. "NU0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "STAT,Misc Status"
hexmask.long.tbyte 0x04 11.--31. 1. "NU2,Reserved"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x14++0x17
line.long 0x00 "CTRL,CTRL"
hexmask.long.tbyte 0x00 9.--31. 1. "NU3,TI Internal : Reserved"
bitfld.long 0x00 8. "CHECK TIMEOUT,TI Internal : Check timeout" "0,1"
bitfld.long 0x00 7. "CHECK PARITY,TI Internal : Check Parity" "0,1"
bitfld.long 0x00 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1"
newline
bitfld.long 0x00 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM" "0,1"
bitfld.long 0x00 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1"
bitfld.long 0x00 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1"
bitfld.long 0x00 2. "EN_RMW,TI Internal : Enable rmw" "0,1"
newline
bitfld.long 0x00 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1"
bitfld.long 0x00 0. "ECC_EN,TI Internal : Enable ECC" "0,1"
line.long 0x04 "ERR_CTRL1,ERR_CTRL1"
line.long 0x08 "ERR_CTRL2,ERR_CTRL2"
hexmask.long.word 0x08 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x08 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set"
line.long 0x0C "ERR_STAT1,ERR_STAT1"
hexmask.long.word 0x0C 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error"
bitfld.long 0x0C 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status" "0,1"
bitfld.long 0x0C 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status" "0,1,2,3"
bitfld.long 0x0C 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status" "0,1"
newline
bitfld.long 0x0C 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt" "0,1"
bitfld.long 0x0C 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt" "0,1,2,3"
newline
bitfld.long 0x0C 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt" "0,1"
bitfld.long 0x0C 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt" "0,1,2,3"
bitfld.long 0x0C 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt" "0,1,2,3"
line.long 0x10 "ERR_STAT2,ERR_STAT2"
line.long 0x14 "ERR_STAT3,ERR_STAT3"
hexmask.long.tbyte 0x14 10.--31. 1. "NU6,TI Internal : Reserved"
bitfld.long 0x14 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1"
hexmask.long.byte 0x14 2.--8. 1. "NU5,TI Internal : Reserved"
bitfld.long 0x14 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1"
newline
rbitfld.long 0x14 0. "NU4,TI Internal : Reserved" "0,1"
group.long 0x3C++0x07
line.long 0x00 "SEC_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU7,Reserved"
bitfld.long 0x00 0. "SEC_EOI_WR,EOI Register" "0,1"
line.long 0x04 "SEC_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU8,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU9,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU10,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DED_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU11,Reserved"
bitfld.long 0x00 0. "DED_EOI_WR,EOI Register" "0,1"
line.long 0x04 "DED_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU12,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "DED_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU13,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU14,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "AGGR_ENABLE_SET,AGGR interrupt enable set Register"
hexmask.long 0x00 2.--31. 1. "NU15,Reserved"
bitfld.long 0x00 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt Enable Set Register for parity errors" "0,1"
line.long 0x04 "AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
hexmask.long 0x04 2.--31. 1. "NU16,Reserved"
bitfld.long 0x04 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt Enable Clear for parity errors" "0,1"
line.long 0x08 "AGGR_STATUS_SET,AGGR interrupt status set Register"
hexmask.long 0x08 4.--31. 1. "NU17,Reserved"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "AGGR_STATUS_CLR,AGGR interrupt status clear Register"
hexmask.long 0x0C 4.--31. 1. "NU18,Reserved"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_MCANB_CFG (MSS MCANB Configuration Module Registers)"
base ad:0x53F7FC00
rgroup.long 0x00++0x2B
line.long 0x00 "SS_PID,SS_PID"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SS_CTRL,SS_CTRL"
hexmask.long 0x04 7.--31. 1. "NU0,Reserved"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
bitfld.long 0x04 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1"
newline
rbitfld.long 0x04 0.--2. "NU,Reserved" "0,1,2,3,4,5,6,7"
line.long 0x08 "SS_STAT,SS_STAT"
hexmask.long 0x08 3.--31. 1. "NU1,Reserved"
bitfld.long 0x08 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MMI_DONE," "0,1"
bitfld.long 0x08 0. "NU,Reserved" "0,1"
line.long 0x0C "SS_ICS,SS_ICS"
hexmask.long 0x0C 1.--31. 1. "NU2,Reserved"
bitfld.long 0x0C 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x10 "SS_IRS,SS_IRS"
hexmask.long 0x10 1.--31. 1. "NU3,Reserved"
bitfld.long 0x10 0. "IRS,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x14 "SS_IECS,SS_IECS"
hexmask.long 0x14 1.--31. 1. "NU4,Reserved"
bitfld.long 0x14 0. "IECS,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x18 "SS_IE,SS_IE"
hexmask.long 0x18 1.--31. 1. "NU5,Reserved"
bitfld.long 0x18 0. "IE,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x1C "SS_IES,SS_IES"
hexmask.long 0x1C 1.--31. 1. "NU6,Reserved"
bitfld.long 0x1C 0. "IES,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "SS_EOI,SS_EOI"
hexmask.long.tbyte 0x20 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targeted interrupt"
line.long 0x24 "SS_EXT_TS_PS,SS_EXT_TS_PS"
hexmask.long.byte 0x24 24.--31. 1. "NU8,Reserved"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value"
line.long 0x28 "SS_EXT_TS_USIC,SS_EXT_TS_USIC"
hexmask.long 0x28 5.--31. 1. "NU9,Reserved"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x200++0x2F
line.long 0x00 "CREL,CREL"
bitfld.long 0x00 28.--31. "REL,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month"
newline
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x04 "ENDN,ENDN"
line.long 0x08 "CUST,CUST"
line.long 0x0C "DBTP,DBTP"
hexmask.long.byte 0x0C 24.--31. 1. "NU13,Reserved"
bitfld.long 0x0C 23. "TDC,Transmitter Delay Compensation" "0,1"
rbitfld.long 0x0C 21.--22. "NU12,Reserved" "0,1,2,3"
bitfld.long 0x0C 16.--20. "DBRP,Data Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x0C 13.--15. "NU11,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8.--12. "DTSEG1,Data time segment before smaple point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "DSJW,Data resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "TEST,TEST"
hexmask.long.tbyte 0x10 8.--31. 1. "NU15,Reserved"
rbitfld.long 0x10 7. "RX,Receive Pin" "0,1"
bitfld.long 0x10 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x10 4. "LBCK,Loop Back Mode" "0,1"
rbitfld.long 0x10 0.--3. "NU14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "RWD,RWD"
hexmask.long.word 0x14 16.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x14 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x14 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x18 "CCCR,CCCR"
hexmask.long.tbyte 0x18 15.--31. 1. "NU18,Reserved"
bitfld.long 0x18 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x18 13. "EFBI,Edge Filtering durign Bus Integration" "0,1"
bitfld.long 0x18 12. "PXHD,Protocol Exception Handling Disable" "0,1"
rbitfld.long 0x18 10.--11. "NU17,Reserved" "0,1,2,3"
newline
bitfld.long 0x18 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x18 8. "FDOE,FD Operation Enable" "0,1"
bitfld.long 0x18 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x18 6. "DAR,Disable Automatic Regransmission" "0,1"
bitfld.long 0x18 5. "MON,Bus Monitoring Mode" "0,1"
newline
bitfld.long 0x18 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x18 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x18 2. "ASM,Restriced Operation Mode" "0,1"
bitfld.long 0x18 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x18 0. "INIT,Initialization" "0,1"
line.long 0x1C "NBTP,NBTP"
hexmask.long.byte 0x1C 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x1C 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x1C 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
rbitfld.long 0x1C 7. "NU19,Reserved" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x20 "TSCC,TSCC"
hexmask.long.word 0x20 20.--31. 1. "NU21,Reserved"
bitfld.long 0x20 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 2.--15. 1. "NU20,Reserved"
bitfld.long 0x20 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x24 "TSCV,TSCV"
hexmask.long.word 0x24 16.--31. 1. "NU22,Reserved"
hexmask.long.word 0x24 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x28 "TOCC,TOCC"
hexmask.long.word 0x28 16.--31. 1. "TOP,Timeout Period"
hexmask.long.word 0x28 3.--15. 1. "NU23,Reserved"
bitfld.long 0x28 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x28 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x2C "TOCV,TOCV"
hexmask.long.word 0x2C 16.--31. 1. "NU24,Reserved"
hexmask.long.word 0x2C 0.--15. 1. "TOC,Timeout Counter"
rgroup.long 0x240++0x0B
line.long 0x00 "ECR,ECR"
hexmask.long.byte 0x00 24.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x00 15. "RP,Recieve Error Passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Recieve Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x04 "PSR,PSR"
hexmask.long.word 0x04 23.--31. 1. "NU27,Reserved"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x04 15. "NU26,Reserved" "0,1"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x04 13. "RFDF,Recieved a CAN FD Message" "0,1"
newline
bitfld.long 0x04 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x04 6. "EW,Warning Status" "0,1"
newline
bitfld.long 0x04 5. "EP,Error Passive" "0,1"
bitfld.long 0x04 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
line.long 0x08 "TDCR,TDCR"
hexmask.long.tbyte 0x08 15.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
rbitfld.long 0x08 7. "NU28,Reserved" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x250++0x0F
line.long 0x00 "IR,IR"
rbitfld.long 0x00 30.--31. "NU30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0,1"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning Status" "0,1"
bitfld.long 0x00 23. "EP,Error Passive" "0,1"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0,1"
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0,1"
newline
bitfld.long 0x00 20. "BEC,Bit Error Corrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0,1"
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0,1"
newline
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0,1"
newline
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission Complete" "0,1"
bitfld.long 0x00 8. "HPM,High Priority Message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0,1"
newline
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0x04 "IE,IE"
rbitfld.long 0x04 30.--31. "NU31,Reserved" "0,1,2,3"
bitfld.long 0x04 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "0,1"
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
newline
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
newline
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
newline
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1"
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x04 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0x04 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
newline
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x08 "ILS,ILS"
rbitfld.long 0x08 30.--31. "NU32,Reserved" "0,1,2,3"
bitfld.long 0x08 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "0,1"
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
newline
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
newline
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
newline
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x08 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x08 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
newline
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x0C "ILE,ILE"
hexmask.long 0x0C 2.--31. 1. "NU33,Reserved"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "0,1"
group.long 0x280++0x0B
line.long 0x00 "GFC,GFC"
hexmask.long 0x00 6.--31. 1. "NU34,Reserved"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,reject Remote Frames Standard" "0,1"
bitfld.long 0x00 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x04 "SIDFC,SIDFC"
hexmask.long.byte 0x04 24.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "LSS_S,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA_S,Filter List Standard Start Address"
rbitfld.long 0x04 0.--1. "NU35,Reserved" "0,1,2,3"
line.long 0x08 "XIDFC,XIDFC"
hexmask.long.byte 0x08 24.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x08 16.--23. 1. "LSS_X,List Size Standard"
hexmask.long.word 0x08 2.--15. 1. "FLSSA_X,Filter List Standard Start Address"
rbitfld.long 0x08 0.--1. "NU37,Reserved" "0,1,2,3"
group.long 0x290++0x57
line.long 0x00 "XIDAM,XIDAM"
rbitfld.long 0x00 29.--31. "NU39,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
line.long 0x04 "HPMS,HPMS"
hexmask.long.word 0x04 16.--31. 1. "NU40,Reserved"
bitfld.long 0x04 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x04 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "NDAT1,NDAT1"
line.long 0x0C "NDAT2,NDAT2"
line.long 0x10 "RXF0C,RXF0C"
bitfld.long 0x10 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
rbitfld.long 0x10 23. "NU42_1,Reserved" "0,1"
hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size"
rbitfld.long 0x10 15. "NU42,Reserved" "0,1"
newline
hexmask.long.word 0x10 2.--14. 1. "F0SA,Rx FIFO 0 Start Address"
rbitfld.long 0x10 0.--1. "NU41,Reserved" "0,1,2,3"
line.long 0x14 "RXF0S,RXF0S"
bitfld.long 0x14 26.--31. "NU46,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x14 22.--23. "NU45,Reserved" "0,1,2,3"
bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 14.--15. "NU44,Reserved" "0,1,2,3"
bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 7. "NU43,Reserved" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
line.long 0x18 "RXF0A,RXF0A"
hexmask.long 0x18 6.--31. 1. "NU47,Reserved"
bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "RXBC,RXBC"
hexmask.long.word 0x1C 16.--31. 1. "NU49,Reserved"
hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address"
rbitfld.long 0x1C 0.--1. "NU48,Reserved" "0,1,2,3"
line.long 0x20 "RXF1C,RXF1C"
bitfld.long 0x20 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 0 Watermark"
rbitfld.long 0x20 23. "NU50_1,Reserved" "0,1"
hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 0 Size"
rbitfld.long 0x20 15. "NU50,Reserved" "0,1"
newline
hexmask.long.word 0x20 2.--14. 1. "F1SA,Rx FIFO 0 Start Address"
rbitfld.long 0x20 0.--1. "NU499,Reserved" "0,1,2,3"
line.long 0x24 "RXF1S,RXF1S"
bitfld.long 0x24 26.--31. "NU54,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 25. "RF1L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x24 24. "F1F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x24 22.--23. "NU53,Reserved" "0,1,2,3"
bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 14.--15. "NU52,Reserved" "0,1,2,3"
bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 7. "NU51,Reserved" "0,1"
hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level"
line.long 0x28 "RXF1A,RXF1A"
hexmask.long 0x28 6.--31. 1. "NU55,Reserved"
bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "RXESC,RXESC"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU58,Reserved"
bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 7. "NU57,Reserved" "0,1"
bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 3. "NU56,Reserved" "0,1"
newline
bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x30 "TXBC,TXBC"
bitfld.long 0x30 31. "NU61,Reserved" "0,1"
bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x30 22.--23. "NU60,Reserved" "0,1,2,3"
bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address"
bitfld.long 0x30 0.--1. "NU59,Reserved" "0,1,2,3"
line.long 0x34 "TXFQS,TXFQS"
hexmask.long.word 0x34 22.--31. 1. "NU64,Reserved"
bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "0,1"
bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 13.--15. "NU63,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x34 8.--12. "TFGI,Tx Queue Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 6.--7. "NU62,Reserved" "0,1,2,3"
bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "TXESC,TXESC"
hexmask.long 0x38 3.--31. 1. "NU65,Reserved"
bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x3C "TXBRP,TXBRP"
line.long 0x40 "TXBAR,TXBAR"
line.long 0x44 "TXBCR,TXBCR"
line.long 0x48 "TXBTO,TXBTO"
line.long 0x4C "TXBCF,TXBCF"
line.long 0x50 "TXBTIE,TXBTIE"
line.long 0x54 "TXBCIE,TXBCIE"
group.long 0x2F0++0x0F
line.long 0x00 "TXEFC,TXEFC"
bitfld.long 0x00 30.--31. "NU68,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 22.--23. "NU67,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
newline
bitfld.long 0x00 0.--1. "NU66,Reserved" "0,1,2,3"
line.long 0x04 "TXEFS,TXEFS"
bitfld.long 0x04 26.--31. "NU72,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x04 24. "EFF,Event FIFO Full" "0,1"
bitfld.long 0x04 21.--23. "NU71,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 13.--15. "NU70,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--7. "NU69,Reserved" "0,1,2,3"
bitfld.long 0x04 0.--5. "EFFL,Event FIFO FIll Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "TXEFA,TXEFA"
hexmask.long 0x08 5.--31. 1. "NU73,Reserved"
bitfld.long 0x08 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "RES16,RES16"
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C 0xB8 0xBC )
rgroup.long ($2+0x230)++0x03
line.long 0x00 "RES$1,RES00"
repeat.end
width 0x0B
tree.end
tree "MSS_MCANB_ECC (MSS MCANB ECC Module Registers)"
base ad:0x53F7F800
rgroup.long 0x00++0x03
line.long 0x00 "REV,Aggregator Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "VECTOR,ECC Vector Register"
hexmask.long.byte 0x00 25.--31. 1. "NU1,Reserved"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDR,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
rbitfld.long 0x00 11.--14. "NU0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "STAT,Misc Status"
hexmask.long.tbyte 0x04 11.--31. 1. "NU2,Reserved"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x14++0x17
line.long 0x00 "CTRL,CTRL"
hexmask.long.tbyte 0x00 9.--31. 1. "NU3,TI Internal : Reserved"
bitfld.long 0x00 8. "CHECK TIMEOUT,TI Internal : Check timeout" "0,1"
bitfld.long 0x00 7. "CHECK PARITY,TI Internal : Check Parity" "0,1"
bitfld.long 0x00 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1"
newline
bitfld.long 0x00 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM" "0,1"
bitfld.long 0x00 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1"
bitfld.long 0x00 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1"
bitfld.long 0x00 2. "EN_RMW,TI Internal : Enable rmw" "0,1"
newline
bitfld.long 0x00 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1"
bitfld.long 0x00 0. "ECC_EN,TI Internal : Enable ECC" "0,1"
line.long 0x04 "ERR_CTRL1,ERR_CTRL1"
line.long 0x08 "ERR_CTRL2,ERR_CTRL2"
hexmask.long.word 0x08 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x08 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set"
line.long 0x0C "ERR_STAT1,ERR_STAT1"
hexmask.long.word 0x0C 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error"
bitfld.long 0x0C 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status" "0,1"
bitfld.long 0x0C 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status" "0,1,2,3"
bitfld.long 0x0C 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status" "0,1"
newline
bitfld.long 0x0C 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt" "0,1"
bitfld.long 0x0C 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt" "0,1,2,3"
newline
bitfld.long 0x0C 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt" "0,1"
bitfld.long 0x0C 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt" "0,1,2,3"
bitfld.long 0x0C 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt" "0,1,2,3"
line.long 0x10 "ERR_STAT2,ERR_STAT2"
line.long 0x14 "ERR_STAT3,ERR_STAT3"
hexmask.long.tbyte 0x14 10.--31. 1. "NU6,TI Internal : Reserved"
bitfld.long 0x14 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1"
hexmask.long.byte 0x14 2.--8. 1. "NU5,TI Internal : Reserved"
bitfld.long 0x14 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1"
newline
rbitfld.long 0x14 0. "NU4,TI Internal : Reserved" "0,1"
group.long 0x3C++0x07
line.long 0x00 "SEC_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU7,Reserved"
bitfld.long 0x00 0. "SEC_EOI_WR,EOI Register" "0,1"
line.long 0x04 "SEC_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU8,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU9,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU10,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DED_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU11,Reserved"
bitfld.long 0x00 0. "DED_EOI_WR,EOI Register" "0,1"
line.long 0x04 "DED_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU12,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "DED_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU13,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU14,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "AGGR_ENABLE_SET,AGGR interrupt enable set Register"
hexmask.long 0x00 2.--31. 1. "NU15,Reserved"
bitfld.long 0x00 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt Enable Set Register for parity errors" "0,1"
line.long 0x04 "AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
hexmask.long 0x04 2.--31. 1. "NU16,Reserved"
bitfld.long 0x04 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt Enable Clear for parity errors" "0,1"
line.long 0x08 "AGGR_STATUS_SET,AGGR interrupt status set Register"
hexmask.long 0x08 4.--31. 1. "NU17,Reserved"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "AGGR_STATUS_CLR,AGGR interrupt status clear Register"
hexmask.long 0x0C 4.--31. 1. "NU18,Reserved"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_MCRC (MSS MCRC Module Registers)"
base ad:0xC5020000
group.long 0x00++0x03
line.long 0x00 "CRC_CTRL0,Contains sw reset control bit to reset PSA"
rbitfld.long 0x00 31. "NU12,Reserved" "0,1"
rbitfld.long 0x00 30. "NU11,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "NU10,Reserved" "0,1"
rbitfld.long 0x00 27.--28. "NU9,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 25.--26. "NU8,Reserved" "0,1,2,3"
rbitfld.long 0x00 24. "NU7,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "NU6,Reserved" "0,1"
rbitfld.long 0x00 22. "NU5,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "NU4,Reserved" "0,1"
rbitfld.long 0x00 19.--20. "NU3,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 17.--18. "NU2,Reserved" "0,1,2,3"
rbitfld.long 0x00 16. "NU1,Reserved" "0,1"
newline
bitfld.long 0x00 15. "CH2_CRC_SEL2,Refer 'CH2_DW_SEL' field description" "0,1"
bitfld.long 0x00 14. "CH2_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 13. "CH2_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 11.--12. "CH2_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 9.--10. "CH2_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 8. "CH2_PSA_SWREST,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 7. "CH1_CRC_SEL2,Refer 'CH1_DW_SEL' field description" "0,1"
bitfld.long 0x00 6. "CH1_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 5. "CH1_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 3.--4. "CH1_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 1.--2. "CH1_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 0. "CH1_PSA_SWREST,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
group.long 0x08++0x03
line.long 0x00 "CRC_CTRL1,Contains power down control bit"
hexmask.long 0x00 1.--31. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode"
group.long 0x10++0x03
line.long 0x00 "CRC_CTRL2,Contains channel mode. data trace enable control bits"
rbitfld.long 0x00 26.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "NU14,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 18.--23. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 16.--17. "NU13,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 10.--15. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode: 0" "reserved 1,Full-CPU mode,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved2,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable" "Data Trace disable,Data Trace enable"
newline
rbitfld.long 0x00 2.--3. "Reserved1,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode: 0" "reserved 1,Full-CPU mode,?..."
group.long 0x18++0x03
line.long 0x00 "CRC_INTS,Write one to a bit to enable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU22,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU21,Reserved" "0,1"
rbitfld.long 0x00 26. "NU20,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU19,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU18,Reserved" "0,1"
rbitfld.long 0x00 19. "NU17,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU16,Reserved" "0,1"
rbitfld.long 0x00 17. "NU15,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENS,Channel 2 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENS,Channel 1 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
bitfld.long 0x00 1. "CH1_CRCFAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x20++0x03
line.long 0x00 "CRC_INTR,Write one to a bit to disable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU30,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU29,Reserved" "0,1"
rbitfld.long 0x00 26. "NU28,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU27,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU26,Reserved" "0,1"
rbitfld.long 0x00 19. "NU25,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU24,Reserved" "0,1"
rbitfld.long 0x00 17. "NU23,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENR,Channel 2 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
newline
bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENR,Channel 1 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
newline
bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
bitfld.long 0x00 1. "CH1_CRCFAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x28++0x03
line.long 0x00 "CRC_STATUS_REG,Contains interrupt flags for different types of interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU38,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU37,Reserved" "0,1"
rbitfld.long 0x00 26. "NU36,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU35,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU34,Reserved" "0,1"
rbitfld.long 0x00 19. "NU33,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU32,Reserved" "0,1"
rbitfld.long 0x00 17. "NU31,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUT,Channel 2 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 9. "CH2_CRCFAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUT,Channel 1 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
bitfld.long 0x00 1. "CH1_CRCFAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x30++0x03
line.long 0x00 "CRC_INT_OFFSET_REG,Contains the interrupt offset vector address"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "OFSTREG,CRC Interrupt Offset"
rgroup.long 0x38++0x03
line.long 0x00 "CRC_BUSY,Contains the busy flag for each channel"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "NU40,Reserved" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved3,Reserved"
bitfld.long 0x00 16. "NU39,Reserved" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved2,Reserved"
bitfld.long 0x00 8. "Ch2_BUSY,Ch2_BUSY" "0,1"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "CH1_BUSY,CH1_BUSY" "0,1"
group.long 0x40++0x13
line.long 0x00 "CRC_PCOUNT_REG1,Channel 1 preload register for the pattern count"
hexmask.long.word 0x00 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register"
line.long 0x04 "CRC_SCOUNT_REG1,Channel 1 preload register for the sector count"
hexmask.long.word 0x04 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register"
line.long 0x08 "CRC_CURSEC_REG1,Channel 1 current sector register contains the sector number which causes CRC failure"
hexmask.long.word 0x08 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register"
line.long 0x0C "CRC_WDTOPLD1,Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register"
line.long 0x10 "CRC_BCTOPLD1,Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x10 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Regis- ter"
group.long 0x60++0x33
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA signature low register"
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA signature high register"
line.long 0x08 "CRC_REGL1,Channel 1 CRC value low register"
line.long 0x0C "CRC_REGH1,Channel 1 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL1,Channel 1 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH1,Channel 1 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL1,Channel 1 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH1,Channel 1 un-compressed raw data high register"
line.long 0x20 "CRC_PCOUNT_REG2,Channel 2 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,Channel 2 Pattern Counter Preload Register"
line.long 0x24 "CRC_SCOUNT_REG2,Channel 2 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register"
line.long 0x28 "CRC_CURSEC_REG2,Channel 2 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register"
line.long 0x2C "CRC_WDTOPLD2,Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register"
line.long 0x30 "CRC_BCTOPLD2,Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Regis- ter"
group.long 0xA0++0x33
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA signature low register"
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA signature high register"
line.long 0x08 "CRC_REGL2,Channel 2 CRC value low register"
line.long 0x0C "CRC_REGH2,Channel 2 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL2,Channel 2 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH2,Channel 2 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL2,Channel 2 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH2,Channel 2 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG3,Channel 3 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU41,Reserved"
line.long 0x24 "CRC_SCOUNT_REG3,Channel 3 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU42,Reserved"
line.long 0x28 "CRC_CURSEC_REG3,Channel 3 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU43,Reserved"
line.long 0x2C "CRC_WDTOPLD3,Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU44,Reserved"
line.long 0x30 "CRC_BCTOPLD3,Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU45,Reserved"
rgroup.long 0xE0++0x33
line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA signature low register"
line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA signature high register"
line.long 0x08 "CRC_REGL3,Channel 3 CRC value low register"
line.long 0x0C "CRC_REGH3,Channel 3 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL3,Channel 3 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH3,Channel 3 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL3,Channel 3 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH3,Channel 3 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG4,Channel 4 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU54,Reserved"
line.long 0x24 "CRC_SCOUNT_REG4,Channel 4 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU55,Reserved"
line.long 0x28 "CRC_CURSEC_REG4,Channel 4 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU56,Reserved"
line.long 0x2C "CRC_WDTOPLD4,Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU57,Reserved"
line.long 0x30 "CRC_BCTOPLD4,Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU58,Reserved"
rgroup.long 0x120++0x27
line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA signature low register"
line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA signature high register"
line.long 0x08 "CRC_REGL4,Channel 4 CRC value low register"
line.long 0x0C "CRC_REGH4,Channel 4 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL4,Channel 4 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH4,Channel 4 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL4,Channel 4 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH4,Channel 4 un-compressed raw data high Register"
line.long 0x20 "MCRC_BUS_SEL,Disables either or all tracing of data buses"
hexmask.long 0x20 3.--31. 1. "NU67,Reserved"
bitfld.long 0x20 2. "MEn,MEn" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled"
newline
bitfld.long 0x20 1. "DTCMEn,DTCMEn" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.."
bitfld.long 0x20 0. "ITCMEn,ITCMEn" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled"
line.long 0x24 "MCRC_RESERVED,0x144 to 0x1FF is reserved area"
width 0x0B
tree.end
tree "MSS_PCR1 (MSS PCR1 Module Registers)"
base ad:0x52F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "MSS_PCR2 (MSS PCR2 Module Registers)"
base ad:0x53F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
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abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "MSS_QSPI (MSS QSPI Module Registers)"
base ad:0xC8000000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID"
bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3"
bitfld.long 0x00 28.--29. "Reserved,Always read as 0" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,The function of the module being used"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Release Number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom IP" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "SYSCONFIG,SYSCONFIG"
hexmask.long 0x00 6.--31. 1. "Reserved3,Always read as 0"
rbitfld.long 0x00 4.--5. "Reserved2,Always read as 0" "0,1,2,3"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode"
newline
rbitfld.long 0x00 0.--1. "Reserved1,Always read as 0" "0,1,2,3"
group.long 0x20++0x13
line.long 0x00 "INTR_STATUS_RAW_SET,INTR Interrupt Status Raw/Set Register"
hexmask.long 0x00 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x00 1. "WIRQ_RAW,Word Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.."
bitfld.long 0x00 0. "FIRQ_RAW,Frame Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.."
line.long 0x04 "INTR_STATUS_ENABLED_CLEAR,INTR Interrupt Status Enabled/Clear Register"
hexmask.long 0x04 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x04 1. "WIRQ_ENA,Word Interrupt Enabled Status Read indicates enabled status" "inactive,active Writing 1 will.."
bitfld.long 0x04 0. "FIRQ_ENA,Frame Interrupt Enabled Status Read indicates enabled status" "inactive,active Writing 1 will.."
line.long 0x08 "INTR_ENABLE_SET,INTR Interrupt Enable/Set Register"
hexmask.long 0x08 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x08 1. "WIRQ_ENA_SET,Word Interrupt Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
bitfld.long 0x08 0. "FIRQ_ENA_SET,Frame Interrupt Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
line.long 0x0C "INTR_ENABLE_CLEAR,INTR Interrupt Enable/Clear Register"
hexmask.long 0x0C 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x0C 1. "WIRQ_ENA_CLR,Word Interrupt Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
bitfld.long 0x0C 0. "FIRQ_ENA_CLR,Frame Interrupt Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
line.long 0x10 "INTC_EOI,EOI Register"
group.long 0x40++0x27
line.long 0x00 "SPI_CLOCK_CNTRL,SPI Clock Control Register (SPICC)"
bitfld.long 0x00 31. "CLKEN,Clock Enable" "0,1"
hexmask.long.word 0x00 16.--30. 1. "Reserved,Always read as 0"
hexmask.long.word 0x00 0.--15. 1. "DCLK_DIV,Serial data clock divide by ratio"
line.long 0x04 "SPI_DC,SPI Data Control Register (SPIDC)"
rbitfld.long 0x04 29.--31. "Reserved4,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 27.--28. "DD3,Data delay for chip select 3 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
bitfld.long 0x04 26. "CKPH3,Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out.." "0,1"
newline
bitfld.long 0x04 25. "CSP3,Chip select polarity for chip select 3 0- Active low 1- Active high" "0,1"
bitfld.long 0x04 24. "CKP3,Clock polarity for chip select 3 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
rbitfld.long 0x04 21.--23. "Reserved3,Always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 19.--20. "DD2,Data delay for chip select 2 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
bitfld.long 0x04 18. "CKPH2,Clock phase for chip select 2" "0,1"
bitfld.long 0x04 17. "CSP2,Chip select polarity for chip select 2 0- Active low 1- Active high" "0,1"
newline
bitfld.long 0x04 16. "CKP2,Clock polarity for chip select 2 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
rbitfld.long 0x04 13.--15. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11.--12. "DD1,Data delay for chip select 1 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
newline
bitfld.long 0x04 10. "CKPH1,Clock phase for chip select 1" "0,1"
bitfld.long 0x04 9. "CSP1,Chip select polarity for chip select 1 0- Active low 1- Active high" "0,1"
bitfld.long 0x04 8. "CKP1,Clock polarity for chip select 1 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
newline
rbitfld.long 0x04 5.--7. "Reserved1,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3.--4. "DD0,Data delay for chip select 0 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
bitfld.long 0x04 2. "CKPH0,Clock phase for chip select 0" "0,1"
newline
bitfld.long 0x04 1. "CSP0,Chip select polarity for chip select 0 0- Active low 1- Active high" "0,1"
bitfld.long 0x04 0. "CKP0,Clock polarity for chip select 0 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
line.long 0x08 "SPI_CMD,SPI Command Register (SPICR)"
rbitfld.long 0x08 30.--31. "Reserved3,Always read as 0" "0,1,2,3"
bitfld.long 0x08 28.--29. "CSNUM,Device select" "0,1,2,3"
rbitfld.long 0x08 26.--27. "Reserved2,Always read as 0" "0,1,2,3"
newline
hexmask.long.byte 0x08 19.--25. 1. "WLEN,Word length"
bitfld.long 0x08 16.--18. "CMD,Transfer command 000- Reserved 001- 4 pin Read Single 010- 4 pin Write Single 011- 4 pin Read Dual 100 - Reserved 101 - 3 pin Read Single 110 - 3 pin Write Single 111 - 6 pin Read Quad" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 15. "FIRQ,Frame count interrupt enable" "0,1"
newline
bitfld.long 0x08 14. "WIRQ,Word count interrupt enable" "0,1"
rbitfld.long 0x08 12.--13. "Reserved1,Always read as 0" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "FLEN,Frame Length 0- 1 word 1- 2 words ... 4095 - 4096 words"
line.long 0x0C "SPI_STATUS,SPI Status Register (SPISR)"
bitfld.long 0x0C 28.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 16.--27. 1. "WDCNT,Word count"
hexmask.long.word 0x0C 3.--15. 1. "Reserved1,Always read as 0"
newline
bitfld.long 0x0C 2. "FC,Frame complete" "0,1"
bitfld.long 0x0C 1. "WC,Word complete" "0,1"
bitfld.long 0x0C 0. "BUSY,Busy bit" "0,1"
line.long 0x10 "SPI_DATA,SPI Data Register (SPIDR)"
line.long 0x14 "SPI_SETUP0,Memory Mapped SPI Setup0 Register"
rbitfld.long 0x14 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x14 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x14 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x14 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x14 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x14 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x14 0.--7. 1. "RCMD,Read Command"
line.long 0x18 "SPI_SETUP1,Memory Mapped SPI Setup1 Register"
rbitfld.long 0x18 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x18 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x18 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x18 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x18 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x18 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x18 0.--7. 1. "RCMD,Read Command"
line.long 0x1C "SPI_SETUP2,Memory Mapped SPI Setup2 Register"
rbitfld.long 0x1C 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x1C 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x1C 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x1C 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x1C 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x1C 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x1C 0.--7. 1. "RCMD,Read Command"
line.long 0x20 "SPI_SETUP3,Memory Mapped SPI Setup3 Register"
rbitfld.long 0x20 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x20 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x20 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x20 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x20 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x20 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x20 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x20 0.--7. 1. "RCMD,Read Command"
line.long 0x24 "SPI_SWITCH,Memory Mapped SPI Switch Register"
hexmask.long 0x24 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x24 1. "MM_INT_EN,Memory Mapped mode interrupt enable" "0,1"
bitfld.long 0x24 0. "MMPT_S,MMPT select" "0,1"
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
group.long ($2+0x68)++0x03
line.long 0x00 "SPI_DATA$1,SPI Data Register (SPIDR1)"
repeat.end
repeat 9. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x10 0x14 0x18 0x30 0x34 0x38 )
rgroup.long ($2+0x04)++0x03
line.long 0x00 "MSS_QSPI_Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_R5SS_STC (MSS R5SS STC Module Registers)"
base ad:0x52F79800
group.long 0x00++0x11B
line.long 0x00 "STCGCR0,Self test Global control Reg0"
hexmask.long.word 0x00 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run"
newline
rbitfld.long 0x00 11.--15. "NU0,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval" "Continue NSTC run from previous interval,Restart NSTC run from ROM address 0 1X = Start..,?..."
line.long 0x04 "STCGCR1,Self test Global control Reg1"
hexmask.long.tbyte 0x04 12.--31. 1. "NU2,Reserved bits"
newline
bitfld.long 0x04 8.--11. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x04 7. "NU3,Reserved bits" "0,1"
newline
bitfld.long 0x04 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode" "XOR mode,Spread mode"
newline
bitfld.long 0x04 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration" "Operates in Normal Scan Mode,Operates in Low Power Scan Mode"
newline
bitfld.long 0x04 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
newline
bitfld.long 0x04 0.--3. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "STCTPR,Time out counter preload register"
line.long 0x0C "STC_CADDR,Current Address register for CORE1"
line.long 0x10 "STCCICR,Current Interval count register"
hexmask.long.word 0x10 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well"
newline
hexmask.long.word 0x10 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run"
line.long 0x14 "STCGSTAT,Global Status Register"
hexmask.long.tbyte 0x14 12.--31. 1. "NU4,Reserved bits"
newline
bitfld.long 0x14 8.--11. "ST_ACTIVE,Tells whether self test is currently active or not" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 2.--7. "NU5,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)" "Self test run has not failed,SelfTest run has failed"
newline
bitfld.long 0x14 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)" "Not completed,SelfTest run Completed"
line.long 0x18 "STCFSTAT,Fail Status Register"
hexmask.long 0x18 5.--31. 1. "NU6,Reserved bits"
newline
bitfld.long 0x18 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur" "Failure on Segment 0,Failure on Segment 1,Failure on Segment 2,Failure on Segment 3"
newline
bitfld.long 0x18 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)" "No time out error occurred,SelfTest run failed due to a timeout error"
newline
bitfld.long 0x18 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)" "No MISR mismatch for CORE2,Self test run failed due to MISR mismatch for.."
newline
bitfld.long 0x18 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments" "No MISR mismatch for CORE1,Self test run failed due to MISR mismatch for.."
line.long 0x1C "STCSCSCR,Signature compare Self Check Register"
hexmask.long 0x1C 5.--31. 1. "NU7,Reserved bits"
newline
bitfld.long 0x1C 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)" "No fault insertion,Inserts fault in the logic unedr test which will.."
newline
bitfld.long 0x1C 0.--3. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "STC_CADDR2,Current Address register for CORE2"
line.long 0x24 "STC_CLKDIV,Clock Divider Register"
rbitfld.long 0x24 27.--31. "NU8,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 19.--23. "NU9,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 11.--15. "NU10,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 3.--7. "NU11,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
line.long 0x28 "STC_SEGPLR,Segment 1st interval Preload Register"
hexmask.long 0x28 2.--31. 1. "NU12,Reserved bits"
newline
bitfld.long 0x28 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter" "Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of.."
line.long 0x2C "SEG0_START_ADDR,ROM Start address for Segment0"
hexmask.long.word 0x2C 20.--31. 1. "NU13,Reserved bits"
newline
hexmask.long.tbyte 0x2C 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x30 "SEG1_START_ADDR,ROM Start address for Segment1"
hexmask.long.word 0x30 20.--31. 1. "NU14,Reserved bits"
newline
hexmask.long.tbyte 0x30 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x34 "SEG2_START_ADDR,ROM Start address for Segment2"
hexmask.long.word 0x34 20.--31. 1. "NU15,Reserved bits"
newline
hexmask.long.tbyte 0x34 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x38 "SEG3_START_ADDR,ROM Start address for Segment3"
hexmask.long.word 0x38 20.--31. 1. "NU16,Reserved bits"
newline
hexmask.long.tbyte 0x38 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x3C "CORE1_CURMISR_0,Holds the MISR signature for CORE1"
line.long 0x40 "CORE1_CURMISR_1,Holds the MISR signature for CORE1"
line.long 0x44 "CORE1_CURMISR_2,Holds the MISR signature for CORE1"
line.long 0x48 "CORE1_CURMISR_3,Holds the MISR signature for CORE1"
line.long 0x4C "CORE1_CURMISR_4,Holds the MISR signature for CORE1"
line.long 0x50 "CORE1_CURMISR_5,Holds the MISR signature for CORE1"
line.long 0x54 "CORE1_CURMISR_6,Holds the MISR signature for CORE1"
line.long 0x58 "CORE1_CURMISR_7,Holds the MISR signature for CORE1"
line.long 0x5C "CORE1_CURMISR_8,Holds the MISR signature for CORE1"
line.long 0x60 "CORE1_CURMISR_9,Holds the MISR signature for CORE1"
line.long 0x64 "CORE1_CURMISR_10,Holds the MISR signature for CORE1"
line.long 0x68 "CORE1_CURMISR_11,Holds the MISR signature for CORE1"
line.long 0x6C "CORE1_CURMISR_12,Holds the MISR signature for CORE1"
line.long 0x70 "CORE1_CURMISR_13,Holds the MISR signature for CORE1"
line.long 0x74 "CORE1_CURMISR_14,Holds the MISR signature for CORE1"
line.long 0x78 "CORE1_CURMISR_15,Holds the MISR signature for CORE1"
line.long 0x7C "CORE1_CURMISR_16,Holds the MISR signature for CORE1"
line.long 0x80 "CORE1_CURMISR_17,Holds the MISR signature for CORE1"
line.long 0x84 "CORE1_CURMISR_18,Holds the MISR signature for CORE1"
line.long 0x88 "CORE1_CURMISR_19,Holds the MISR signature for CORE1"
line.long 0x8C "CORE1_CURMISR_20,Holds the MISR signature for CORE1"
line.long 0x90 "CORE1_CURMISR_21,Holds the MISR signature for CORE1"
line.long 0x94 "CORE1_CURMISR_22,Holds the MISR signature for CORE1"
line.long 0x98 "CORE1_CURMISR_23,Holds the MISR signature for CORE1"
line.long 0x9C "CORE1_CURMISR_24,Holds the MISR signature for CORE1"
line.long 0xA0 "CORE1_CURMISR_25,Holds the MISR signature for CORE1"
line.long 0xA4 "CORE1_CURMISR_26,Holds the MISR signature for CORE1"
line.long 0xA8 "CORE1_CURMISR_27,Holds the MISR signature for CORE1"
line.long 0xAC "CORE2_CURMISR_0,Holds the MISR signature for CORE2"
line.long 0xB0 "CORE2_CURMISR_1,Holds the MISR signature for CORE2"
line.long 0xB4 "CORE2_CURMISR_2,Holds the MISR signature for CORE2"
line.long 0xB8 "CORE2_CURMISR_3,Holds the MISR signature for CORE2"
line.long 0xBC "CORE2_CURMISR_4,Holds the MISR signature for CORE2"
line.long 0xC0 "CORE2_CURMISR_5,Holds the MISR signature for CORE2"
line.long 0xC4 "CORE2_CURMISR_6,Holds the MISR signature for CORE2"
line.long 0xC8 "CORE2_CURMISR_7,Holds the MISR signature for CORE2"
line.long 0xCC "CORE2_CURMISR_8,Holds the MISR signature for CORE2"
line.long 0xD0 "CORE2_CURMISR_9,Holds the MISR signature for CORE2"
line.long 0xD4 "CORE2_CURMISR_10,Holds the MISR signature for CORE2"
line.long 0xD8 "CORE2_CURMISR_11,Holds the MISR signature for CORE2"
line.long 0xDC "CORE2_CURMISR_12,Holds the MISR signature for CORE2"
line.long 0xE0 "CORE2_CURMISR_13,Holds the MISR signature for CORE2"
line.long 0xE4 "CORE2_CURMISR_14,Holds the MISR signature for CORE2"
line.long 0xE8 "CORE2_CURMISR_15,Holds the MISR signature for CORE2"
line.long 0xEC "CORE2_CURMISR_16,Holds the MISR signature for CORE2"
line.long 0xF0 "CORE2_CURMISR_17,Holds the MISR signature for CORE2"
line.long 0xF4 "CORE2_CURMISR_18,Holds the MISR signature for CORE2"
line.long 0xF8 "CORE2_CURMISR_19,Holds the MISR signature for CORE2"
line.long 0xFC "CORE2_CURMISR_20,Holds the MISR signature for CORE2"
line.long 0x100 "CORE2_CURMISR_21,Holds the MISR signature for CORE2"
line.long 0x104 "CORE2_CURMISR_22,Holds the MISR signature for CORE2"
line.long 0x108 "CORE2_CURMISR_23,Holds the MISR signature for CORE2"
line.long 0x10C "CORE2_CURMISR_24,Holds the MISR signature for CORE2"
line.long 0x110 "CORE2_CURMISR_25,Holds the MISR signature for CORE2"
line.long 0x114 "CORE2_CURMISR_26,Holds the MISR signature for CORE2"
line.long 0x118 "CORE2_CURMISR_27,Holds the MISR signature for CORE2"
width 0x0B
tree.end
tree "MSS_RCM (MSS RCM Module Registers)"
base ad:0x52100000
rgroup.long 0x00++0x1CB
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MSS_RST_CAUSE_CLR,"
bitfld.long 0x04 0.--2. "clr,Write pulse bit field: Clear bit for rst cause register (writing '111' will clear the rst cause register)" "0,1,2,3,4,5,6,7"
line.long 0x08 "MSS_RST_STATUS,"
hexmask.long.word 0x08 0.--15. 1. "cause,Has the status because of which reset has happened"
line.long 0x0C "SYSRST_BY_DBG_RST,"
bitfld.long 0x0C 16.--18. "r5b,writing '000' will block debug reset request from CR5B toggling globally reset for CR5B" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0.--2. "r5a,writing '000' will block debug reset request from CR5A toggling globally reset for CR5A" "0,1,2,3,4,5,6,7"
line.long 0x10 "RST_ASSERDLY,"
hexmask.long.byte 0x10 0.--7. 1. "common,Value decides number of cycles reset should be asserted for CR5SS related resets"
line.long 0x14 "RST2ASSERTDLY,"
hexmask.long.byte 0x14 24.--31. 1. "r5b,Value decides number of cycles should be held before asserting reset for r5ss local reset for CR5B"
hexmask.long.byte 0x14 16.--23. 1. "r5a,Value decides number of cycles should be held before asserting reset for r5ss local reset for CR5A"
hexmask.long.byte 0x14 8.--15. 1. "r5ssb,Value decides number of cycles should be held before asserting reset for r5ss global reset for CR5B"
newline
hexmask.long.byte 0x14 0.--7. 1. "r5ssa,Value decides number of cycles should be held before asserting reset for r5ss global reset for CR5A"
line.long 0x18 "RST_WFICHECK,"
bitfld.long 0x18 24.--26. "r5b,writing '000' will disable check for WFI before local reset assertion of CR5A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 16.--18. "r5a,writing '000' will disable check for WFI before local reset assertion of CR5A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 8.--10. "r5ssb,writing '000' will disable check for WFI before global reset assertion of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 0.--2. "r5ssa,writing '000' will disable check for WFI before global reset assertion of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x1C "MSS_MCANA_CLK_SRC_SEL,"
hexmask.long.word 0x1C 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCANA.Data should be loaded as multibit"
line.long 0x20 "MSS_MCANB_CLK_SRC_SEL,"
hexmask.long.word 0x20 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCANB.Data should be loaded as multibit"
line.long 0x24 "MSS_QSPI_CLK_SRC_SEL,"
hexmask.long.word 0x24 0.--11. 1. "clksrcsel,Select line for selecting source clock for QSPI.Data should be loaded as multibit"
line.long 0x28 "MSS_RTIA_CLK_SRC_SEL,"
hexmask.long.word 0x28 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIA.Data should be loaded as multibit"
line.long 0x2C "MSS_RTIB_CLK_SRC_SEL,"
hexmask.long.word 0x2C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIB.Data should be loaded as multibit"
line.long 0x30 "MSS_RTIC_CLK_SRC_SEL,"
hexmask.long.word 0x30 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIC.Data should be loaded as multibit"
line.long 0x34 "MSS_WDT_CLK_SRC_SEL,"
hexmask.long.word 0x34 0.--11. 1. "clksrcsel,Select line for selecting source clock for WDT.Data should be loaded as multibit"
line.long 0x38 "MSS_SPIA_CLK_SRC_SEL,"
hexmask.long.word 0x38 0.--11. 1. "clksrcsel,Select line for selecting source clock for SPIA.Data should be loaded as multibit"
line.long 0x3C "MSS_SPIB_CLK_SRC_SEL,"
hexmask.long.word 0x3C 0.--11. 1. "clksrcsel,Select line for selecting source clock for SPIB.Data should be loaded as multibit"
line.long 0x40 "MSS_I2C_CLK_SRC_SEL,"
hexmask.long.word 0x40 0.--11. 1. "clksrcsel,Select line for selecting source clock for I2C.Data should be loaded as multibit"
line.long 0x44 "MSS_SCIA_CLK_SRC_SEL,"
hexmask.long.word 0x44 0.--11. 1. "clksrcsel,Select line for selecting source clock for SCIA.Data should be loaded as multibit"
line.long 0x48 "MSS_SCIB_CLK_SRC_SEL,"
hexmask.long.word 0x48 0.--11. 1. "clksrcsel,Select line for selecting source clock for SCIB.Data should be loaded as multibit"
line.long 0x4C "MSS_CPTS_CLK_SRC_SEL,"
hexmask.long.word 0x4C 0.--11. 1. "clksrcsel,Select line for selecting source clock for CPTS.Data should be loaded as multibit"
line.long 0x50 "MSS_CPSW_CLK_SRC_SEL,"
hexmask.long.word 0x50 0.--11. 1. "clksrcsel,Select line for selecting source clock for CPSW.Data should be loaded as multibit"
line.long 0x54 "MSS_MCANA_CLK_DIV_VAL,"
hexmask.long.word 0x54 0.--11. 1. "clkdivr,Divider value MCANA selected clock.Data should be loaded as multibit"
line.long 0x58 "MSS_MCANB_CLK_DIV_VAL,"
hexmask.long.word 0x58 0.--11. 1. "clkdivr,Divider value MCANB selected clock.Data should be loaded as multibit"
line.long 0x5C "MSS_QSPI_CLK_DIV_VAL,"
hexmask.long.word 0x5C 0.--11. 1. "clkdivr,Divider value QSPI selected clock.Data should be loaded as multibit"
line.long 0x60 "MSS_RTIA_CLK_DIV_VAL,"
hexmask.long.word 0x60 0.--11. 1. "clkdivr,Divider value RTIA selected clock.Data should be loaded as multibit"
line.long 0x64 "MSS_RTIB_CLK_DIV_VAL,"
hexmask.long.word 0x64 0.--11. 1. "clkdivr,Divider value RTIB selected clock.Data should be loaded as multibit"
line.long 0x68 "MSS_RTIC_CLK_DIV_VAL,"
hexmask.long.word 0x68 0.--11. 1. "clkdivr,Divider value RTIC selected clock.Data should be loaded as multibit"
line.long 0x6C "MSS_WDT_CLK_DIV_VAL,"
hexmask.long.word 0x6C 0.--11. 1. "clkdivr,Divider value WDT selected clock.Data should be loaded as multibit"
line.long 0x70 "MSS_SPIA_CLK_DIV_VAL,"
hexmask.long.word 0x70 0.--11. 1. "clkdivr,Divider value SPIA selected clock.Data should be loaded as multibit"
line.long 0x74 "MSS_SPIB_CLK_DIV_VAL,"
hexmask.long.word 0x74 0.--11. 1. "clkdivr,Divider value SPIB selected clock.Data should be loaded as multibit"
line.long 0x78 "MSS_I2C_CLK_DIV_VAL,"
hexmask.long.word 0x78 0.--11. 1. "clkdivr,Divider value I2C selected clock.Data should be loaded as multibit"
line.long 0x7C "MSS_SCIA_CLK_DIV_VAL,"
hexmask.long.word 0x7C 0.--11. 1. "clkdivr,Divider value SCIA selected clock.Data should be loaded as multibit"
line.long 0x80 "MSS_SCIB_CLK_DIV_VAL,"
hexmask.long.word 0x80 0.--11. 1. "clkdivr,Divider value SCIB selected clock.Data should be loaded as multibit"
line.long 0x84 "MSS_CPTS_CLK_DIV_VAL,"
hexmask.long.word 0x84 0.--11. 1. "clkdivr,Divider value CPTS selected clock.Data should be loaded as multibit"
line.long 0x88 "MSS_CPSW_CLK_DIV_VAL,"
hexmask.long.word 0x88 0.--11. 1. "clkdivr,Divider value CPSW selected clock.Data should be loaded as multibit"
line.long 0x8C "MSS_RGMII_CLK_DIV_VAL,"
hexmask.long.word 0x8C 0.--11. 1. "clkdivr,Divider value RGMII selected clock.Data should be loaded as multibit"
line.long 0x90 "MSS_MII100_CLK_DIV_VAL,"
hexmask.long.word 0x90 0.--11. 1. "clkdivr,Divider value MII100 selected clock.Data should be loaded as multibit"
line.long 0x94 "MSS_MII10_CLK_DIV_VAL,"
hexmask.long.tbyte 0x94 0.--23. 1. "clkdivr,Divider value MII10 selected clock.Data should be loaded as multibit"
line.long 0x98 "MSS_GPADC_CLK_DIV_VAL,"
hexmask.long.tbyte 0x98 0.--23. 1. "clkdivr,Divider value GPADC selected clock.Data should be loaded as multibit"
line.long 0x9C "MSS_MCANA_CLK_GATE,"
bitfld.long 0x9C 0.--2. "gated,writing '111' will gate clock for MCANA" "0,1,2,3,4,5,6,7"
line.long 0xA0 "MSS_MCANB_CLK_GATE,"
bitfld.long 0xA0 0.--2. "gated,writing '111' will gate clock for MCANB" "0,1,2,3,4,5,6,7"
line.long 0xA4 "MSS_QSPI_CLK_GATE,"
bitfld.long 0xA4 0.--2. "gated,writing '111' will gate clock for QSPI" "0,1,2,3,4,5,6,7"
line.long 0xA8 "MSS_RTIA_CLK_GATE,"
bitfld.long 0xA8 0.--2. "gated,writing '111' will gate clock for RTIA" "0,1,2,3,4,5,6,7"
line.long 0xAC "MSS_RTIB_CLK_GATE,"
bitfld.long 0xAC 0.--2. "gated,writing '111' will gate clock for RTIB" "0,1,2,3,4,5,6,7"
line.long 0xB0 "MSS_RTIC_CLK_GATE,"
bitfld.long 0xB0 0.--2. "gated,writing '111' will gate clock for RTIC" "0,1,2,3,4,5,6,7"
line.long 0xB4 "MSS_WDT_CLK_GATE,"
bitfld.long 0xB4 0.--2. "gated,writing '111' will gate clock for WDT" "0,1,2,3,4,5,6,7"
line.long 0xB8 "MSS_SPIA_CLK_GATE,"
bitfld.long 0xB8 0.--2. "gated,writing '111' will gate clock for SPIA" "0,1,2,3,4,5,6,7"
line.long 0xBC "MSS_SPIB_CLK_GATE,"
bitfld.long 0xBC 0.--2. "gated,writing '111' will gate clock for SPIB" "0,1,2,3,4,5,6,7"
line.long 0xC0 "MSS_I2C_CLK_GATE,"
bitfld.long 0xC0 0.--2. "gated,writing '111' will gate clock for I2C" "0,1,2,3,4,5,6,7"
line.long 0xC4 "MSS_SCIA_CLK_GATE,"
bitfld.long 0xC4 0.--2. "gated,writing '111' will gate clock for SCIA" "0,1,2,3,4,5,6,7"
line.long 0xC8 "MSS_SCIB_CLK_GATE,"
bitfld.long 0xC8 0.--2. "gated,writing '111' will gate clock for SCIB" "0,1,2,3,4,5,6,7"
line.long 0xCC "MSS_CPTS_CLK_GATE,"
bitfld.long 0xCC 0.--2. "gated,writing '111' will gate clock for CPTS" "0,1,2,3,4,5,6,7"
line.long 0xD0 "MSS_CPSW_CLK_GATE,"
bitfld.long 0xD0 0.--2. "gated,writing '111' will gate clock for CPSW" "0,1,2,3,4,5,6,7"
line.long 0xD4 "MSS_RGMII_CLK_GATE,"
bitfld.long 0xD4 0.--2. "gated,writing '111' will gate clock for RGMII" "0,1,2,3,4,5,6,7"
line.long 0xD8 "MSS_MII100_CLK_GATE,"
bitfld.long 0xD8 0.--2. "gated,writing '111' will gate clock for MII100" "0,1,2,3,4,5,6,7"
line.long 0xDC "MSS_MII10_CLK_GATE,"
bitfld.long 0xDC 0.--2. "gated,writing '111' will gate clock for MII10" "0,1,2,3,4,5,6,7"
line.long 0xE0 "MSS_GPADC_CLK_GATE,"
bitfld.long 0xE0 0.--2. "gated,writing '111' will gate clock for MSS GPADC" "0,1,2,3,4,5,6,7"
line.long 0xE4 "MSS_MCANA_CLK_STATUS,"
hexmask.long.byte 0xE4 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCANA"
hexmask.long.byte 0xE4 0.--7. 1. "clkinuse,Status shows the source clock slected for MCANA"
line.long 0xE8 "MSS_MCANB_CLK_STATUS,"
hexmask.long.byte 0xE8 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCANB"
hexmask.long.byte 0xE8 0.--7. 1. "clkinuse,Status shows the source clock slected for MCANB"
line.long 0xEC "MSS_QSPI_CLK_STATUS,"
hexmask.long.byte 0xEC 8.--15. 1. "currdivider,Status shows the current divider value choosen for QSPI"
hexmask.long.byte 0xEC 0.--7. 1. "clkinuse,Status shows the source clock slected for QSPI"
line.long 0xF0 "MSS_RTIA_CLK_STATUS,"
hexmask.long.byte 0xF0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIA"
hexmask.long.byte 0xF0 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIA"
line.long 0xF4 "MSS_RTIB_CLK_STATUS,"
hexmask.long.byte 0xF4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIB"
hexmask.long.byte 0xF4 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIB"
line.long 0xF8 "MSS_RTIC_CLK_STATUS,"
hexmask.long.byte 0xF8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIC"
hexmask.long.byte 0xF8 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIC"
line.long 0xFC "MSS_WDT_CLK_STATUS,"
hexmask.long.byte 0xFC 8.--15. 1. "currdivider,Status shows the current divider value choosen for WDT"
hexmask.long.byte 0xFC 0.--7. 1. "clkinuse,Status shows the source clock slected for WDT"
line.long 0x100 "MSS_SPIA_CLK_STATUS,"
hexmask.long.byte 0x100 8.--15. 1. "currdivider,Status shows the current divider value choosen for SPIA"
hexmask.long.byte 0x100 0.--7. 1. "clkinuse,Status shows the source clock slected for SPIA"
line.long 0x104 "MSS_SPIB_CLK_STATUS,"
hexmask.long.byte 0x104 8.--15. 1. "currdivider,Status shows the current divider value choosen for SPIB"
hexmask.long.byte 0x104 0.--7. 1. "clkinuse,Status shows the source clock slected for SPIB"
line.long 0x108 "MSS_I2C_CLK_STATUS,"
hexmask.long.byte 0x108 8.--15. 1. "currdivider,Status shows the current divider value choosen for I2C"
hexmask.long.byte 0x108 0.--7. 1. "clkinuse,Status shows the source clock slected for I2C"
line.long 0x10C "MSS_SCIA_CLK_STATUS,"
hexmask.long.byte 0x10C 8.--15. 1. "currdivider,Status shows the current divider value choosen for SCIA"
hexmask.long.byte 0x10C 0.--7. 1. "clkinuse,Status shows the source clock slected for SCIA"
line.long 0x110 "MSS_SCIB_CLK_STATUS,"
hexmask.long.byte 0x110 8.--15. 1. "currdivider,Status shows the current divider value choosen for SCIB"
hexmask.long.byte 0x110 0.--7. 1. "clkinuse,Status shows the source clock slected for SCIB"
line.long 0x114 "MSS_CPTS_CLK_STATUS,"
hexmask.long.byte 0x114 8.--15. 1. "currdivider,Status shows the current divider value choosen for CPTS"
hexmask.long.byte 0x114 0.--7. 1. "clkinuse,Status shows the source clock slected for CPTS"
line.long 0x118 "MSS_CPSW_CLK_STATUS,"
hexmask.long.byte 0x118 8.--15. 1. "currdivider,Status shows the current divider value choosen for CPSW"
hexmask.long.byte 0x118 0.--7. 1. "clkinuse,Status shows the source clock slected for CPSW"
line.long 0x11C "MSS_RGMII_CLK_STATUS,"
hexmask.long.byte 0x11C 8.--15. 1. "currdivider,Status shows the current divider value choosen for RGMII"
line.long 0x120 "MSS_MII100_CLK_STATUS,"
hexmask.long.byte 0x120 8.--15. 1. "currdivider,Status shows the current divider value choosen for MII100"
line.long 0x124 "MSS_MII10_CLK_STATUS,"
hexmask.long.byte 0x124 8.--15. 1. "currdivider,Status shows the current divider value choosen for MII10"
line.long 0x128 "MSS_GPADC_CLK_STATUS,"
hexmask.long.byte 0x128 8.--15. 1. "currdivider,Status shows the current divider value choosen for GPADC"
line.long 0x12C "MSS_CR5SS_POR_RST_CTRL,"
bitfld.long 0x12C 0.--2. "assert,write pulse bit field: writing '111' will assert por reset to R5SS" "0,1,2,3,4,5,6,7"
line.long 0x130 "MSS_CR5SSA_RST_CTRL,"
bitfld.long 0x130 0.--2. "assert,write pulse bit field: writing '111' will reset CR5A and MSS_CR5A_VIM" "0,1,2,3,4,5,6,7"
line.long 0x134 "MSS_CR5SSB_RST_CTRL,"
bitfld.long 0x134 0.--2. "assert,write pulse bit field: writing '111' will reset CR5B and MSS_CR5B_VIM" "0,1,2,3,4,5,6,7"
line.long 0x138 "MSS_CR5A_RST_CTRL,"
bitfld.long 0x138 0.--2. "assert,write pulse bit field: writing '111' will reset CR5A only" "0,1,2,3,4,5,6,7"
line.long 0x13C "MSS_CR5B_RST_CTRL,"
bitfld.long 0x13C 0.--2. "assert,write pulse bit field: writing '111' will reset CR5B only" "0,1,2,3,4,5,6,7"
line.long 0x140 "MSS_VIMA_RST_CTRL,"
bitfld.long 0x140 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x144 "MSS_VIMB_RST_CTRL,"
bitfld.long 0x144 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x148 "MSS_CRC_RST_CTRL,"
bitfld.long 0x148 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x14C "MSS_RTIA_RST_CTRL,"
bitfld.long 0x14C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x150 "MSS_RTIB_RST_CTRL,"
bitfld.long 0x150 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x154 "MSS_RTIC_RST_CTRL,"
bitfld.long 0x154 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x158 "MSS_WDT_RST_CTRL,"
bitfld.long 0x158 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x15C "MSS_ESM_RST_CTRL,"
bitfld.long 0x15C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x160 "MSS_DCCA_RST_CTRL,"
bitfld.long 0x160 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x164 "MSS_DCCB_RST_CTRL,"
bitfld.long 0x164 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x168 "MSS_DCCC_RST_CTRL,"
bitfld.long 0x168 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x16C "MSS_DCCD_RST_CTRL,"
bitfld.long 0x16C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x170 "MSS_GIO_RST_CTRL,"
bitfld.long 0x170 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x174 "MSS_SPIA_RST_CTRL,"
bitfld.long 0x174 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x178 "MSS_SPIB_RST_CTRL,"
bitfld.long 0x178 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x17C "MSS_QSPI_RST_CTRL,"
bitfld.long 0x17C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x180 "MSS_PWM1_RST_CTRL,"
bitfld.long 0x180 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x184 "MSS_PWM2_RST_CTRL,"
bitfld.long 0x184 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x188 "MSS_PWM3_RST_CTRL,"
bitfld.long 0x188 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x18C "MSS_MCANA_RST_CTRL,"
bitfld.long 0x18C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x190 "MSS_MCANB_RST_CTRL,"
bitfld.long 0x190 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x194 "MSS_I2C_RST_CTRL,"
bitfld.long 0x194 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x198 "MSS_SCIA_RST_CTRL,"
bitfld.long 0x198 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x19C "MSS_SCIB_RST_CTRL,"
bitfld.long 0x19C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1A0 "MSS_EDMA_RST_CTRL,"
bitfld.long 0x1A0 24.--26. "tptcb0_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 16.--18. "tpccb_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 12.--14. "tptca1_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A0 8.--10. "tptca0_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 4.--6. "tpcca_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1A4 "MSS_INFRA_RST_CTRL,"
bitfld.long 0x1A4 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "MSS_CPSW_RST_CTRL,"
bitfld.long 0x1A8 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1AC "MSS_GPADC_RST_CTRL,"
bitfld.long 0x1AC 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "MSS_DMM_RST_CTRL,"
bitfld.long 0x1B0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "R5_COREA_GATE,"
bitfld.long 0x1B4 0.--2. "clkgate,writing '111' will gate clock to CR5A related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7"
line.long 0x1B8 "R5_COREB_GATE,"
bitfld.long 0x1B8 0.--2. "clkgate,writing '111' will gate clock to CR5B related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7"
line.long 0x1BC "MSS_L2_BANKA_PD_CTRL,"
bitfld.long 0x1BC 8.--10. "agoodin,SW control for power signal 'AGOODIN' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
bitfld.long 0x1BC 4.--6. "aonin,SW control for power signal 'AONIN' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
bitfld.long 0x1BC 0.--2. "iso,SW control for power signal 'ISO' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "MSS_L2_BANKB_PD_CTRL,"
bitfld.long 0x1C0 8.--10. "agoodin,SW control for power signal 'AGOODIN' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C0 4.--6. "aonin,SW control for power signal 'AONIN' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C0 0.--2. "iso,SW control for power signal 'ISO' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "MSS_L2_BANKA_PD_STATUS,"
bitfld.long 0x1C4 1. "agoodout,SW status indicating the 'pgoodin' of MSS_L2_BANKA" "0,1"
bitfld.long 0x1C4 0. "aonout,SW status indicating the 'ponin' of MSS_L2_BANKA" "0,1"
line.long 0x1C8 "MSS_L2_BANKB_PD_STATUS,"
bitfld.long 0x1C8 1. "agoodout,SW status indicating the 'pgoodin' of MSS_L2_BANKB" "0,1"
bitfld.long 0x1C8 0. "aonout,SW status indicating the 'ponin' of MSS_L2_BANKB" "0,1"
group.long 0x1D4++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x400++0x4F
line.long 0x00 "HSM_RTIA_CLK_SRC_SEL,"
hexmask.long.word 0x00 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_RTIA.Data should be loaded as multibit"
line.long 0x04 "HSM_WDT_CLK_SRC_SEL,"
hexmask.long.word 0x04 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_WDT.Data should be loaded as multibit"
line.long 0x08 "HSM_RTC_CLK_SRC_SEL,"
hexmask.long.word 0x08 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_RTC.Data should be loaded as multibit"
line.long 0x0C "HSM_DMTA_CLK_SRC_SEL,"
hexmask.long.word 0x0C 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_DMTA.Data should be loaded as multibit"
line.long 0x10 "HSM_DMTB_CLK_SRC_SEL,"
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_DMTB.Data should be loaded as multibit"
line.long 0x14 "HSM_RTI_CLK_DIV_VAL,"
hexmask.long.word 0x14 0.--11. 1. "clkdivr,Divider value HSM RTI selected clock.Data should be loaded as multibit"
line.long 0x18 "HSM_WDT_CLK_DIV_VAL,"
hexmask.long.word 0x18 0.--11. 1. "clkdivr,Divider value HSM WDT selected clock.Data should be loaded as multibit"
line.long 0x1C "HSM_RTC_CLK_DIV_VAL,"
hexmask.long.word 0x1C 0.--11. 1. "clkdivr,Divider value HSM RTC selected clock.Data should be loaded as multibit"
line.long 0x20 "HSM_DMTA_CLK_DIV_VAL,"
hexmask.long.word 0x20 0.--11. 1. "clkdivr,Divider value HSM DMTA selected clock.Data should be loaded as multibit"
line.long 0x24 "HSM_DMTB_CLK_DIV_VAL,"
hexmask.long.word 0x24 0.--11. 1. "clkdivr,Divider value HSM DMTB selected clock.Data should be loaded as multibit"
line.long 0x28 "HSM_RTI_CLK_GATE,"
bitfld.long 0x28 0.--2. "gated,writing '111' will gate clock for HSM RTI" "0,1,2,3,4,5,6,7"
line.long 0x2C "HSM_WDT_CLK_GATE,"
bitfld.long 0x2C 0.--2. "gated,writing '111' will gate clock for HSM WDT" "0,1,2,3,4,5,6,7"
line.long 0x30 "HSM_RTC_CLK_GATE,"
bitfld.long 0x30 0.--2. "gated,writing '111' will gate clock for HSM RTC" "0,1,2,3,4,5,6,7"
line.long 0x34 "HSM_DMTA_CLK_GATE,"
bitfld.long 0x34 0.--2. "gated,writing '111' will gate clock for HSM DMTA" "0,1,2,3,4,5,6,7"
line.long 0x38 "HSM_DMTB_CLK_GATE,"
bitfld.long 0x38 0.--2. "gated,writing '111' will gate clock for HSM DMTB" "0,1,2,3,4,5,6,7"
line.long 0x3C "HSM_RTI_CLK_STATUS,"
hexmask.long.byte 0x3C 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_RTI"
hexmask.long.byte 0x3C 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_RTI"
line.long 0x40 "HSM_WDT_CLK_STATUS,"
hexmask.long.byte 0x40 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_WDT"
hexmask.long.byte 0x40 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_WDT"
line.long 0x44 "HSM_RTC_CLK_STATUS,"
hexmask.long.byte 0x44 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_RTC"
hexmask.long.byte 0x44 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_RTC"
line.long 0x48 "HSM_DMTA_CLK_STATUS,"
hexmask.long.byte 0x48 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_DMTA"
hexmask.long.byte 0x48 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_DMTA"
line.long 0x4C "HSM_DMTB_CLK_STATUS,"
hexmask.long.byte 0x4C 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_DMTB"
hexmask.long.byte 0x4C 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_DMTB"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x1CC)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_RTIA (MSS RTIA Module Registers)"
base ad:0x52F7A000
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "MSS_RTIB (MSS RTIB Module Registers)"
base ad:0x52F7A100
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "MSS_RTIC (MSS RTIC Module Registers)"
base ad:0x52F7A200
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "MSS_SCIA (MSS SCIA Module Registers)"
base ad:0x52F7EC00
group.long 0x00++0x5F
line.long 0x00 "SCIGCR0,The SCIGCR0 register defines the module reset"
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
newline
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
line.long 0x04 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
rbitfld.long 0x04 26.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
newline
bitfld.long 0x04 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
newline
rbitfld.long 0x04 18.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
newline
bitfld.long 0x04 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
newline
rbitfld.long 0x04 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
newline
bitfld.long 0x04 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function" "0,1"
newline
bitfld.long 0x04 7. "SW_nRESET,Software reset (active low)" "0,1"
newline
rbitfld.long 0x04 6. "RESERVED1,Reserved" "0,1"
newline
bitfld.long 0x04 5. "CLOCK,SCI internal clock enable" "0,1"
newline
bitfld.long 0x04 4. "STOP,SCI number of stop bits" "0,1"
newline
bitfld.long 0x04 3. "PARITY,SCI parity odd/even selection" "0,1"
newline
bitfld.long 0x04 2. "PARITY_ENA,SCI parity enable" "0,1"
newline
bitfld.long 0x04 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0,1"
newline
bitfld.long 0x04 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0,1"
line.long 0x08 "RESERVED1,Reserved"
line.long 0x0C "SCISETINT,SCI Set Interrupt Register"
rbitfld.long 0x0C 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request for address and data frames"
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bitfld.long 0x0C 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set" "leaves the corresponding bit unchanged,enable DMA request"
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bitfld.long 0x0C 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 8. "SET_TX_INT,Set Transmitter interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 0. "SET_BRKDT_INT,Set Break-detect interrupt" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x10 "SCICLEARINT,SCI Clear Interrupt Register"
rbitfld.long 0x10 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 25. "CLR_OE_INT,Clear Overrun-Error Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 24. "CLR_PE_INT,Clear Parity Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x10 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 18. "CLR_RX_DMA_ALL,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request for address frames"
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bitfld.long 0x10 17. "CLR_RX_DMA,Clear RX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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bitfld.long 0x10 16. "CLR_TX_DMA,Clear TX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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rbitfld.long 0x10 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 9. "CLR_RX_INT,Clear Receiver interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 8. "CLR_TX_INT,Clear Transmitter interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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rbitfld.long 0x10 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 0. "CLR_BRKDT_INT,Clear Break-detect interrupt" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x14 "SCISETINTLVL,SCI Set Interrupt Level Register"
rbitfld.long 0x14 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read)" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x14 15. "SET_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x14 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
line.long 0x18 "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
rbitfld.long 0x18 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x18 15. "CLR_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x18 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x18 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
line.long 0x1C "SCIFLR,SCI Flags Register"
rbitfld.long 0x1C 27.--31. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 26. "FE,SCI framing error flag Read" "No effect,Clears this bit to 0"
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rbitfld.long 0x1C 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
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rbitfld.long 0x1C 24. "PE,SCI parity error flag" "0,1"
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hexmask.long.word 0x1C 13.--23. 1. "RESERVED2,Reserved"
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rbitfld.long 0x1C 12. "RXWAKE,Receiver wake-up detect flag" "0,1"
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rbitfld.long 0x1C 11. "TX_EMPTY,Transmitter empty flag" "0,1"
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bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wake-up method select" "0,1"
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rbitfld.long 0x1C 9. "RXRDY,SCI receiver ready flag" "0,1"
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rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag" "0,1"
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rbitfld.long 0x1C 4.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame" "0,1"
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rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state" "0,1"
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rbitfld.long 0x1C 1. "WAKEUP,Wake-up flag" "0,1"
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rbitfld.long 0x1C 0. "BRKDT,SCI break-detect flag" "0,1"
line.long 0x20 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x20 0.--3. "INTVECT0,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x24 0.--3. "INTVECT1,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "SCICHAR,SCI Character Control Register"
hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x28 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
line.long 0x2C "SCIBAUD,SCI Baud Rate Selection Register"
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED,Reserved"
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hexmask.long.tbyte 0x2C 0.--23. 1. "BAUD,SCI 24-bit baud selection"
line.long 0x30 "SCIED,Receiver Emulation Data Buffer"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x30 0.--7. 1. "ED,Receiver Emulation Data Buffer"
line.long 0x34 "SCIRD,Receiver Data Buffer"
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x34 0.--7. 1. "RD,Contains received data"
line.long 0x38 "SCITD,Transmit Data Buffer Register"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x38 0.--7. 1. "TD,Contains Data to be transmitted"
line.long 0x3C "SCIPIO0,SCI Pin I/O Control Register 0"
hexmask.long 0x3C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x3C 2. "TX_FUNC,Defines the function of pin SCITX" "SCIRX is a general-purpose digital I/O pin,SCIRX is the SCI receive pin"
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bitfld.long 0x3C 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x3C 0. "CLK_FUNC,Clock function" "SCICLK is a general-purpose digital I/O pin,SCICLK is the SCI serial clock pin"
line.long 0x40 "SCIPIO1,SCI Pin I/O Control Register 1"
hexmask.long 0x40 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x40 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0)" "SCITX is a general-purpose input pin,SCITX is a general-purpose output pin"
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bitfld.long 0x40 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x40 0. "CLK_DIR,Clock data direction" "0,1"
line.long 0x44 "SCIPIO2,SCI Pin I/O Control Register 2"
hexmask.long 0x44 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x44 2. "TX_DATA_IN,Contains current value on the SCITX pin" "SCITX value is logic low,SCITX value is logic high"
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bitfld.long 0x44 1. "RX_DATA_IN,Contains current value on the SCIRX pin" "SCIRX value is logic low,SCIRX value is logic high"
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bitfld.long 0x44 0. "CLK_DATA_IN,Contains the current value on pin SCICLK" "Pin SCICLK value is logic low,Pin SCICLK value is logic high"
line.long 0x48 "SCIPIO3,SCI Pin I/O Control Register 3"
hexmask.long 0x48 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x48 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "Output value on SCITX is a 0 (logic low),Output value on SCITX is a 1 (logic high)"
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bitfld.long 0x48 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "Output value on SCIRX is 0 (logic low),Output value on SCIRX is 1 (logic high)"
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bitfld.long 0x48 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "Output value on SCICLK is a 0 (logic low),Output value on SCICLK is a 1 (logic high)"
line.long 0x4C "SCIPIO4,SCI Pin I/O Control Register 4"
hexmask.long 0x4C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4C 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
line.long 0x50 "SCIPIO5,SCI Pin I/O Control Register 5"
hexmask.long 0x50 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x50 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
line.long 0x54 "SCIPIO6,SCI Pin I/O Control Register 6"
hexmask.long 0x54 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x54 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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bitfld.long 0x54 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x54 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
line.long 0x58 "SCIPIO7,SCI Pin I/O Control Register 7"
hexmask.long 0x58 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x58 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX" "Pull Control on SCITX pin is enabled,Pull Control on SCITX pin is disabled"
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bitfld.long 0x58 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX" "Pull Control on SCIRX pin is enabled,Pull Control on SCIRX pin is disabled"
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bitfld.long 0x58 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK" "Pull Control on SCICLK pin is enabled,Pull Control on SCICLK pin is disabled"
line.long 0x5C "SCIPIO8,SCI Pin I/O Control Register 8"
hexmask.long 0x5C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x5C 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX" "Pull-Down is on SCITX pin,Pull-Up is on SCITX pin"
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bitfld.long 0x5C 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX" "Pull-Down is on SCIRX pin,Pull-Up is on SCIRX pin"
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bitfld.long 0x5C 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK" "Pull-Down is on SCICLK pin,Pull-Up is on SCICLK pin"
group.long 0x80++0x03
line.long 0x00 "SCIPIO9,SCI Pin I/O Control Register 9"
hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 2. "TX_SL,This bit controls the slew rate for the SCITX pin" "The normal output buffer is used for SCITX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 1. "RX_SL,This bit controls the slew rate for the SCIRX pin" "The normal output buffer is used for SCIRX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin" "The normal output buffer is used for SCICLK pin,The output buffer with slew control is used for.."
group.long 0x90++0x03
line.long 0x00 "SCIIODCTRL,SCI IO DFT Control"
rbitfld.long 0x00 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 26. "FEN,Frame Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 25. "PEN,Parity Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 24. "BRKDT_ENA,Break Detect Error Enable" "No effect,This bit is used to.."
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rbitfld.long 0x00 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry" "0,1,2,3"
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bitfld.long 0x00 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 12.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "LBP_ENA,Module loopback enable" "Digital loopback is enabled,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x00 0. "RXP_ENA,Module Analog loopback through receive pin enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
repeat 8. (list 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_SCIB (MSS SCIB Module Registers)"
base ad:0x52F7ED00
group.long 0x00++0x5F
line.long 0x00 "SCIGCR0,The SCIGCR0 register defines the module reset"
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
line.long 0x04 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
rbitfld.long 0x04 26.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
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bitfld.long 0x04 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
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rbitfld.long 0x04 18.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
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bitfld.long 0x04 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
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rbitfld.long 0x04 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
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bitfld.long 0x04 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function" "0,1"
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bitfld.long 0x04 7. "SW_nRESET,Software reset (active low)" "0,1"
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rbitfld.long 0x04 6. "RESERVED1,Reserved" "0,1"
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bitfld.long 0x04 5. "CLOCK,SCI internal clock enable" "0,1"
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bitfld.long 0x04 4. "STOP,SCI number of stop bits" "0,1"
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bitfld.long 0x04 3. "PARITY,SCI parity odd/even selection" "0,1"
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bitfld.long 0x04 2. "PARITY_ENA,SCI parity enable" "0,1"
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bitfld.long 0x04 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0,1"
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bitfld.long 0x04 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0,1"
line.long 0x08 "RESERVED1,Reserved"
line.long 0x0C "SCISETINT,SCI Set Interrupt Register"
rbitfld.long 0x0C 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request for address and data frames"
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bitfld.long 0x0C 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set" "leaves the corresponding bit unchanged,enable DMA request"
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bitfld.long 0x0C 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 8. "SET_TX_INT,Set Transmitter interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 0. "SET_BRKDT_INT,Set Break-detect interrupt" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x10 "SCICLEARINT,SCI Clear Interrupt Register"
rbitfld.long 0x10 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 25. "CLR_OE_INT,Clear Overrun-Error Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 24. "CLR_PE_INT,Clear Parity Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x10 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 18. "CLR_RX_DMA_ALL,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request for address frames"
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bitfld.long 0x10 17. "CLR_RX_DMA,Clear RX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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bitfld.long 0x10 16. "CLR_TX_DMA,Clear TX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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rbitfld.long 0x10 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 9. "CLR_RX_INT,Clear Receiver interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 8. "CLR_TX_INT,Clear Transmitter interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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rbitfld.long 0x10 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 0. "CLR_BRKDT_INT,Clear Break-detect interrupt" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x14 "SCISETINTLVL,SCI Set Interrupt Level Register"
rbitfld.long 0x14 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read)" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x14 15. "SET_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x14 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
line.long 0x18 "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
rbitfld.long 0x18 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x18 15. "CLR_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x18 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x18 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
line.long 0x1C "SCIFLR,SCI Flags Register"
rbitfld.long 0x1C 27.--31. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 26. "FE,SCI framing error flag Read" "No effect,Clears this bit to 0"
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rbitfld.long 0x1C 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
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rbitfld.long 0x1C 24. "PE,SCI parity error flag" "0,1"
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hexmask.long.word 0x1C 13.--23. 1. "RESERVED2,Reserved"
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rbitfld.long 0x1C 12. "RXWAKE,Receiver wake-up detect flag" "0,1"
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rbitfld.long 0x1C 11. "TX_EMPTY,Transmitter empty flag" "0,1"
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bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wake-up method select" "0,1"
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rbitfld.long 0x1C 9. "RXRDY,SCI receiver ready flag" "0,1"
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rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag" "0,1"
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rbitfld.long 0x1C 4.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame" "0,1"
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rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state" "0,1"
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rbitfld.long 0x1C 1. "WAKEUP,Wake-up flag" "0,1"
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rbitfld.long 0x1C 0. "BRKDT,SCI break-detect flag" "0,1"
line.long 0x20 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x20 0.--3. "INTVECT0,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x24 0.--3. "INTVECT1,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "SCICHAR,SCI Character Control Register"
hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x28 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
line.long 0x2C "SCIBAUD,SCI Baud Rate Selection Register"
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED,Reserved"
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hexmask.long.tbyte 0x2C 0.--23. 1. "BAUD,SCI 24-bit baud selection"
line.long 0x30 "SCIED,Receiver Emulation Data Buffer"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x30 0.--7. 1. "ED,Receiver Emulation Data Buffer"
line.long 0x34 "SCIRD,Receiver Data Buffer"
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x34 0.--7. 1. "RD,Contains received data"
line.long 0x38 "SCITD,Transmit Data Buffer Register"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x38 0.--7. 1. "TD,Contains Data to be transmitted"
line.long 0x3C "SCIPIO0,SCI Pin I/O Control Register 0"
hexmask.long 0x3C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x3C 2. "TX_FUNC,Defines the function of pin SCITX" "SCIRX is a general-purpose digital I/O pin,SCIRX is the SCI receive pin"
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bitfld.long 0x3C 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x3C 0. "CLK_FUNC,Clock function" "SCICLK is a general-purpose digital I/O pin,SCICLK is the SCI serial clock pin"
line.long 0x40 "SCIPIO1,SCI Pin I/O Control Register 1"
hexmask.long 0x40 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x40 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0)" "SCITX is a general-purpose input pin,SCITX is a general-purpose output pin"
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bitfld.long 0x40 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x40 0. "CLK_DIR,Clock data direction" "0,1"
line.long 0x44 "SCIPIO2,SCI Pin I/O Control Register 2"
hexmask.long 0x44 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x44 2. "TX_DATA_IN,Contains current value on the SCITX pin" "SCITX value is logic low,SCITX value is logic high"
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bitfld.long 0x44 1. "RX_DATA_IN,Contains current value on the SCIRX pin" "SCIRX value is logic low,SCIRX value is logic high"
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bitfld.long 0x44 0. "CLK_DATA_IN,Contains the current value on pin SCICLK" "Pin SCICLK value is logic low,Pin SCICLK value is logic high"
line.long 0x48 "SCIPIO3,SCI Pin I/O Control Register 3"
hexmask.long 0x48 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x48 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "Output value on SCITX is a 0 (logic low),Output value on SCITX is a 1 (logic high)"
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bitfld.long 0x48 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "Output value on SCIRX is 0 (logic low),Output value on SCIRX is 1 (logic high)"
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bitfld.long 0x48 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "Output value on SCICLK is a 0 (logic low),Output value on SCICLK is a 1 (logic high)"
line.long 0x4C "SCIPIO4,SCI Pin I/O Control Register 4"
hexmask.long 0x4C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4C 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
line.long 0x50 "SCIPIO5,SCI Pin I/O Control Register 5"
hexmask.long 0x50 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x50 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
line.long 0x54 "SCIPIO6,SCI Pin I/O Control Register 6"
hexmask.long 0x54 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x54 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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bitfld.long 0x54 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x54 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
line.long 0x58 "SCIPIO7,SCI Pin I/O Control Register 7"
hexmask.long 0x58 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x58 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX" "Pull Control on SCITX pin is enabled,Pull Control on SCITX pin is disabled"
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bitfld.long 0x58 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX" "Pull Control on SCIRX pin is enabled,Pull Control on SCIRX pin is disabled"
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bitfld.long 0x58 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK" "Pull Control on SCICLK pin is enabled,Pull Control on SCICLK pin is disabled"
line.long 0x5C "SCIPIO8,SCI Pin I/O Control Register 8"
hexmask.long 0x5C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x5C 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX" "Pull-Down is on SCITX pin,Pull-Up is on SCITX pin"
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bitfld.long 0x5C 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX" "Pull-Down is on SCIRX pin,Pull-Up is on SCIRX pin"
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bitfld.long 0x5C 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK" "Pull-Down is on SCICLK pin,Pull-Up is on SCICLK pin"
group.long 0x80++0x03
line.long 0x00 "SCIPIO9,SCI Pin I/O Control Register 9"
hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 2. "TX_SL,This bit controls the slew rate for the SCITX pin" "The normal output buffer is used for SCITX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 1. "RX_SL,This bit controls the slew rate for the SCIRX pin" "The normal output buffer is used for SCIRX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin" "The normal output buffer is used for SCICLK pin,The output buffer with slew control is used for.."
group.long 0x90++0x03
line.long 0x00 "SCIIODCTRL,SCI IO DFT Control"
rbitfld.long 0x00 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 26. "FEN,Frame Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 25. "PEN,Parity Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 24. "BRKDT_ENA,Break Detect Error Enable" "No effect,This bit is used to.."
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rbitfld.long 0x00 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry" "0,1,2,3"
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bitfld.long 0x00 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 12.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "LBP_ENA,Module loopback enable" "Digital loopback is enabled,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x00 0. "RXP_ENA,Module Analog loopback through receive pin enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
repeat 8. (list 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_SPIA (MSS SPIA Module Registers)"
base ad:0x52F7E800
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
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rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
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bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
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bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
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bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
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rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
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abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
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rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
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abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
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abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
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abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
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bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
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abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
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rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
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bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
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bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
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rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
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rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
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bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
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bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
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hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
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bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
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rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "MSS_SPIB (MSS SPIB Module Registers)"
base ad:0x52F7EA00
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
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rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
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bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
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bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
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bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
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rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
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abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
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rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
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abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
newline
rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
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bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
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abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
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rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
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bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
newline
bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
newline
rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
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rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
newline
bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
newline
bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
newline
bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
newline
hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
newline
bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
newline
rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "MSS_TOPRCM (MSS TOPRCM Module Registers)"
base ad:0x52140000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x17
line.long 0x00 "HSI_CLK_SRC_SEL,"
hexmask.long.word 0x00 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSI"
line.long 0x04 "CSIRX_CLK_SRC_SEL,"
hexmask.long.word 0x04 0.--11. 1. "clksrcsel,Select line for selecting source clock for CSI Rx Data should be loaded as multibit"
line.long 0x08 "MCUCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x08 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCU Clkout Data should be loaded as multibit"
line.long 0x0C "PMICCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x0C 0.--11. 1. "clksrcsel,Select line for selecting source clock for PMIC Clkout Data should be loaded as multibit"
line.long 0x10 "OBSCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for OBS Clkout Data should be loaded as multibit"
line.long 0x14 "TRCCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for TRC Clkout Data should be loaded as multibit"
group.long 0x40++0x17
line.long 0x00 "HSI_DIV_VAL,"
hexmask.long.word 0x00 0.--11. 1. "clkdiv,Divider value for HSI selected clock"
line.long 0x04 "CSIRX_DIV_VAL,"
hexmask.long.word 0x04 0.--11. 1. "clkdiv,Divider value for CSI Rx selected clock"
line.long 0x08 "MCUCLKOUT_DIV_VAL,"
hexmask.long.word 0x08 0.--11. 1. "clkdiv,Divider value for MCU Clkout selected clock"
line.long 0x0C "PMICCLKOUT_DIV_VAL,"
hexmask.long.word 0x0C 0.--11. 1. "clkdiv,Divider value for PMIC Clkout selected clock"
line.long 0x10 "OBSCLKOUT_DIV_VAL,"
hexmask.long.word 0x10 0.--11. 1. "clkdiv,Divider value for OBS Clkout selected clock"
line.long 0x14 "TRCCLKOUT_DIV_VAL,"
hexmask.long.word 0x14 0.--11. 1. "clkdiv,Divider value for TRC Clkout selected clock"
group.long 0x80++0x1B
line.long 0x00 "HSI_CLK_GATE,"
bitfld.long 0x00 0.--2. "gated,Clock gatring config for HSI" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x04 "CSIRX_CLK_GATE,"
bitfld.long 0x04 0.--2. "gated,Clock gatring config for CSI Rx" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x08 "MCUCLKOUT_CLK_GATE,"
bitfld.long 0x08 0.--2. "gated,Clock gatring config for MCU Clkout" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x0C "PMICCLKOUT_CLK_GATE,"
bitfld.long 0x0C 0.--2. "gated,Clock gatring config for PMIC Clkout Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x10 "OBSCLKOUT_CLK_GATE,"
bitfld.long 0x10 0.--2. "gated,Clock gatring config for OBS Clkout Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x14 "TRCCLKOUT_CLK_GATE,"
bitfld.long 0x14 0.--2. "gated,Clock gatring config for TRC Clkout Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x18 "DSS_CLK_GATE,"
bitfld.long 0x18 0.--2. "gated,Clock gatring config for DSP Subsystem System Clock Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
rgroup.long 0xC0++0x17
line.long 0x00 "HSI_CLK_STATUS,"
hexmask.long.byte 0x00 8.--15. 1. "currdivider,Status shows the current divider value choosen for CortexR5 Clock"
newline
hexmask.long.byte 0x00 0.--7. 1. "clkinuse,Status shows the source clock slected for CortexR5 Clock"
line.long 0x04 "CSIRX_CLK_STATUS,"
hexmask.long.byte 0x04 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSI Clock"
newline
hexmask.long.byte 0x04 0.--7. 1. "clkinuse,Status shows the source clock slected for HSI Clock"
line.long 0x08 "MCUCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x08 8.--15. 1. "currdivider,Status shows the current divider value choosen for CSI Rx Clock"
newline
hexmask.long.byte 0x08 0.--7. 1. "clkinuse,Status shows the source clock slected for CSI Rx Clock"
line.long 0x0C "PMICCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x0C 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCU Clkout Clock"
newline
hexmask.long.byte 0x0C 0.--7. 1. "clkinuse,Status shows the source clock slected for MCU Clkout Clock"
line.long 0x10 "OBSCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x10 8.--15. 1. "currdivider,Status shows the current divider value choosen for PMIC Clkout Clock"
newline
hexmask.long.byte 0x10 0.--7. 1. "clkinuse,Status shows the source clock slected for PMIC Clkout Clock"
line.long 0x14 "TRCCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x14 8.--15. 1. "currdivider,Status shows the current divider value choosen for PMIC Clkout Clock"
newline
hexmask.long.byte 0x14 0.--7. 1. "clkinuse,Status shows the source clock slected for PMIC Clkout Clock"
group.long 0x100++0x0F
line.long 0x00 "WARM_RESET_CONFIG,"
bitfld.long 0x00 16.--18. "wdog_rst_en,Data should be loaded as multibit" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "sw_rst,Data should be loaded as multibit" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "pad_bypass,Bypass the Warm reset from Pad Input Data should be loaded as multibit" "Reset is not asserted by SW (multibit 000),?,?,?,?,?,?,Reset is asserted by SW (multibit 111)"
line.long 0x04 "SYS_RST_CAUSE,"
bitfld.long 0x04 0.--4. "cause,System Reset Cause register" "?,?,?,?,?,?,?,?,External Pad reset,POR reset,Warm reset due to MSS_WDT,?,Warm reset due to TOP_RMC,?,?,?,?,?,?,?,?,?,?,?,Warm reset due to HSM_WDT,?..."
line.long 0x08 "SYS_RST_CAUSE_CLR,"
bitfld.long 0x08 0. "clear,Write pulse bit field: System Reset Cause register Clear" "0,1"
line.long 0x0C "DSS_RST_CTRL,"
bitfld.long 0x0C 0.--2. "assert,Reset control for DSP Subsystem Data should be loaded as multibit" "Reset is not asserted by SW (multibit 000),?,?,?,?,?,?,Reset is asserted by SW (multibit 111)"
group.long 0x204++0x23
line.long 0x00 "RS232_BITINTERVAL,"
line.long 0x04 "LVDS_PAD_CTRL0,"
line.long 0x08 "LVDS_PAD_CTRL1,"
line.long 0x0C "DFT_DMLED_EXEC,"
line.long 0x10 "DFT_DMLED_STATUS,"
line.long 0x14 "LIMP_MODE_EN,"
bitfld.long 0x14 8.--10. "force_rcclk_en,Force the RCCLK on when limp mode is detected" "The RCCLK will not be forced on when limp mode..,?,?,?,?,?,?,The RCCLK will be forced on when limp mode is.."
newline
bitfld.long 0x14 4.--6. "ccca_en,Enable MSS_CCCA Error to generate Limp mode" "MSS_CCCA Error will not generate Limp mode..,?,?,?,?,?,?,MSS_CCCA Error will generate Limp mode (multibit.."
newline
bitfld.long 0x14 0.--2. "dcca_en,Enable MSS_DCCA Error to generate Limp mode" "MSS_DCCA Error will not generate Limp mode..,?,?,?,?,?,?,MSS_DCCA Error will generate Limp mode (multibit.."
line.long 0x18 "PMICCLKOUT_DCDC_CTRL,"
hexmask.long.byte 0x18 16.--23. 1. "max_freq_thr,PMIC Clockout DCDC Maximum Frequency Threshold"
newline
hexmask.long.byte 0x18 8.--15. 1. "min_freq_thr,PMIC Clockout DCDC Minimum Frequency Threshold"
newline
bitfld.long 0x18 4.--6. "reset_assert,Reset control for PMIC DCDC Data should be loaded as multibit" "Reset is not asserted by SW (multibit 000),?,?,?,?,?,?,Reset is asserted by SW (multibit 111)"
newline
bitfld.long 0x18 2. "freq_acc_mode,PMIC Clockout DCDC Freq Acc Enable" "0,1"
newline
bitfld.long 0x18 1. "dither_en,PMIC Clockout DCDC Clock Dither Enable" "0,1"
newline
bitfld.long 0x18 0. "dcdc_clk_en,PMIC Clockout DCDC Clock Enable" "0,1"
line.long 0x1C "PMICCLKOUT_DCDC_SLOPE,"
hexmask.long 0x1C 0.--26. 1. "slope_val,PMIC Clockout DCDC Slope Config Value"
line.long 0x20 "RCOSC32K_CTRL,"
bitfld.long 0x20 0.--2. "stoposc,Stop 32KHz RCOSC" "0,1,2,3,4,5,6,7"
group.long 0x400++0x5F
line.long 0x00 "PLL_CORE_PWRCTRL,"
bitfld.long 0x00 5. "PONIN,ON/OFF control of the weak power switch digital" "0,1"
newline
bitfld.long 0x00 4. "PGOODIN,ON/OFF control of the strong power switch digital" "0,1"
newline
bitfld.long 0x00 3. "RET,Save/Restore control for Retention mode" "0,1"
newline
bitfld.long 0x00 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
newline
bitfld.long 0x00 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins" "0,1"
newline
bitfld.long 0x00 0. "OFFMODE,Used to switch OFF the logic on VDDA" "0,1"
line.long 0x04 "PLL_CORE_CLKCTRL,"
bitfld.long 0x04 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK" "0,1"
newline
bitfld.long 0x04 30. "ENSSC,Controls Clock Spreading" "0,1"
newline
bitfld.long 0x04 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO" "synchronously disables CLKDCOLDO,synchronously enables CLKDCOLDO"
newline
bitfld.long 0x04 24.--28. "NWELLTRIM,Trim value for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 23. "IDLE,Sets PLL to Idle mode" "When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL.."
newline
bitfld.long 0x04 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module" "0,1"
newline
bitfld.long 0x04 21. "STBYRET,Standby retention control" "prepares ADPLLLJ for relock when out of..,prepares ADPLLLJ for retention by gating all the.."
newline
bitfld.long 0x04 20. "CLKOUTEN,CLKOUT enable or disable" "synchronously disables CLKOUT,synchronously enables CLKOUT"
newline
bitfld.long 0x04 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO" "synchronously disables CLKOUTLDO,synchronously enables CLKOUTLDO"
newline
bitfld.long 0x04 18. "ULOWCLKEN,Select CLKOUT source in bypass" "When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1),When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW"
newline
bitfld.long 0x04 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p" "0,1"
newline
bitfld.long 0x04 16. "M2PWDNZ,M2 divider power down mode" "Asynchronous power down for M2 divider,M2 divider is functional"
newline
bitfld.long 0x04 14. "STOPMODE,When in Lossclk/Stbyret" "Limp mode,Stopmode"
newline
bitfld.long 0x04 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector" "Reserved,?,HS2,Reserved,HS1,Reserved,?..."
newline
bitfld.long 0x04 8. "RELAXED_LOCK,Decides when FREQLOCK asserted" "FREQLOCK asserted when DC frequency error less..,FREQLOCK asserted when DC frequency error less.."
newline
bitfld.long 0x04 1. "SSCTYPE,SSC Type" "0,1"
newline
bitfld.long 0x04 0. "TINTZ,PLL core soft reset" "0,1"
line.long 0x08 "PLL_CORE_TENABLE,"
bitfld.long 0x08 0. "TENABLE,M N" "0,1"
line.long 0x0C "PLL_CORE_TENABLEDIV,"
bitfld.long 0x0C 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
line.long 0x10 "PLL_CORE_M2NDIV,"
hexmask.long.byte 0x10 16.--22. 1. "M2,Post-divider is REGM2"
newline
hexmask.long.byte 0x10 0.--7. 1. "N,Pre-divider is REGN+1"
line.long 0x14 "PLL_CORE_MN2DIV,"
bitfld.long 0x14 16.--19. "N2,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 0.--11. 1. "M,Feedback Multiplier is REGM"
line.long 0x18 "PLL_CORE_FRACDIV,"
hexmask.long.byte 0x18 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance"
newline
hexmask.long.tbyte 0x18 0.--17. 1. "FRACTIONALM,Fractional part of the M divider"
line.long 0x1C "PLL_CORE_BWCTRL,"
bitfld.long 0x1C 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
newline
bitfld.long 0x1C 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth" "decrease BW,increase BW"
line.long 0x20 "PLL_CORE_FRACCTRL,"
bitfld.long 0x20 31. "DOWNSPREAD,Controls frequency spread" "enables both side frequency spread about the..,enables low frequency spread only"
newline
bitfld.long 0x20 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
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bitfld.long 0x20 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
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hexmask.long.tbyte 0x20 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
line.long 0x24 "PLL_CORE_STATUS,"
bitfld.long 0x24 31. "PONOUT,Status of the weak power-switch" "indicates the/OFF status of the weak..,ndicates the ON status of the weak power-switch.."
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bitfld.long 0x24 30. "PGOODOUT,Status of the strong power-switch" "indicates the/OFF status of the strong..,ndicates the ON status of the strong.."
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bitfld.long 0x24 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down" "0,1"
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bitfld.long 0x24 28. "RECAL_BSTATUS3,Recalibration status flag" "0,1"
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bitfld.long 0x24 27. "RECAL_OPPIN,Recalibration status flag" "0,1"
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bitfld.long 0x24 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x24 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
newline
bitfld.long 0x24 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
newline
bitfld.long 0x24 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
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bitfld.long 0x24 7. "STBYRETACK,Standby and retention status" "indicates to SOC that all internal clocks in..,indicates to SOC that all internal clocks in.."
newline
bitfld.long 0x24 6. "LOSSREF,Reference input loss" "0,1"
newline
bitfld.long 0x24 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN" "CLKOUT gating completed,CLKOUT enabling completed"
newline
bitfld.long 0x24 4. "LOCK2,ADPLL internal loop lock status" "0,1"
newline
bitfld.long 0x24 3. "M2CHANGEACK,Acknowledge for change to M2 divider" "0,1"
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bitfld.long 0x24 2. "SSCACK,Spread Spectrum status" "Spread-spectrum Clocking is disabled on output..,Spread-spectrum Clocking is enabled on output.."
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bitfld.long 0x24 1. "HIGHJITTER,1 indicates jitter" "0,1"
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bitfld.long 0x24 0. "BYPASS,Bypass status signal" "0,1"
line.long 0x28 "PLL_CORE_HSDIVIDER,"
rbitfld.long 0x28 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
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rbitfld.long 0x28 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
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bitfld.long 0x28 2. "TENABLEDIV,Tenable Div" "0,1"
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bitfld.long 0x28 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x28 0. "BYPASS,HSDIVIDER Bypass" "0,1"
line.long 0x2C "PLL_CORE_HSDIVIDER_CLKOUT0,"
bitfld.long 0x2C 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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rbitfld.long 0x2C 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x2C 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x2C 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x2C 0.--4. "DIV,DPLL post-divider factor M4 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x30 "PLL_CORE_HSDIVIDER_CLKOUT1,"
bitfld.long 0x30 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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rbitfld.long 0x30 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x30 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x30 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x30 0.--4. "DIV,DPLL post-divider factor M5 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "PLL_CORE_HSDIVIDER_CLKOUT2,"
bitfld.long 0x34 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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rbitfld.long 0x34 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x34 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x34 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x34 0.--4. "DIV,DPLL post-divider factor M6 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "PLL_CORE_HSDIVIDER_CLKOUT3,"
bitfld.long 0x38 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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rbitfld.long 0x38 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x38 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x38 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x38 0.--4. "DIV,DPLL post-divider factor M7 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "MSS_CR5_CLK_SRC_SEL,"
hexmask.long.word 0x3C 0.--11. 1. "clksrcsel,Select line for selecting source clock for MSS Coretex R5 and System bus Clock"
line.long 0x40 "MSS_CR5_DIV_VAL,"
hexmask.long.word 0x40 0.--11. 1. "clkdiv,Divider value for Cortex R5 selected clock"
line.long 0x44 "SYS_CLK_DIV_VAL,"
hexmask.long.word 0x44 0.--11. 1. "clkdiv,Divider value for System Clock selected clock"
line.long 0x48 "MSS_CR5_CLK_GATE,"
bitfld.long 0x48 0.--2. "gated,Only for debug- Functionality not guaranteed Clock gating config for MSS Coretex R5" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x4C "SYS_CLK_GATE,"
bitfld.long 0x4C 0.--2. "gated,Only for debug- Functionality not guaranteed Clock gating config for System Clock Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x50 "SYS_CLK_STATUS,"
hexmask.long.byte 0x50 8.--15. 1. "currdivider,Status shows the current divider value choosen for Sys Clock"
line.long 0x54 "MSS_CR5_CLK_STATUS,"
hexmask.long.byte 0x54 8.--15. 1. "currdivider,Status shows the current divider value choosen for CortexR5 Clock"
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hexmask.long.byte 0x54 0.--7. 1. "clkinuse,Status shows the source clock slected for CortexR5 Clock"
line.long 0x58 "PLL_CORE_RSTCTRL,"
bitfld.long 0x58 0.--2. "assert,SW Reset override for the PLL" "0,1,2,3,4,5,6,7"
line.long 0x5C "PLL_CORE_HSDIVIDER_RSTCTRL,"
bitfld.long 0x5C 0.--2. "assert,SW Reset override for the HSDIVIDER" "0,1,2,3,4,5,6,7"
group.long 0x800++0x87
line.long 0x00 "PLL_DSP_PWRCTRL,"
bitfld.long 0x00 5. "PONIN,ON/OFF control of the weak power switch digital" "0,1"
newline
bitfld.long 0x00 4. "PGOODIN,ON/OFF control of the strong power switch digital" "0,1"
newline
bitfld.long 0x00 3. "RET,Save/Restore control for Retention mode" "0,1"
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bitfld.long 0x00 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
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bitfld.long 0x00 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins" "0,1"
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bitfld.long 0x00 0. "OFFMODE,Used to switch OFF the logic on VDDA" "0,1"
line.long 0x04 "PLL_DSP_CLKCTRL,"
bitfld.long 0x04 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK" "0,1"
newline
bitfld.long 0x04 30. "ENSSC,Controls Clock Spreading" "0,1"
newline
bitfld.long 0x04 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO" "synchronously disables CLKDCOLDO,synchronously enables CLKDCOLDO"
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bitfld.long 0x04 24.--28. "NWELLTRIM,Trim value for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 23. "IDLE,Sets PLL to Idle mode" "When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL.."
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bitfld.long 0x04 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module" "0,1"
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bitfld.long 0x04 21. "STBYRET,Standby retention control" "prepares ADPLLLJ for relock when out of..,prepares ADPLLLJ for retention by gating all the.."
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bitfld.long 0x04 20. "CLKOUTEN,CLKOUT enable or disable" "synchronously disables CLKOUT,synchronously enables CLKOUT"
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bitfld.long 0x04 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO" "synchronously disables CLKOUTLDO,synchronously enables CLKOUTLDO"
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bitfld.long 0x04 18. "ULOWCLKEN,Select CLKOUT source in bypass" "When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1),When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW"
newline
bitfld.long 0x04 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p" "0,1"
newline
bitfld.long 0x04 16. "M2PWDNZ,M2 divider power down mode" "Asynchronous power down for M2 divider,M2 divider is functional"
newline
bitfld.long 0x04 14. "STOPMODE,When in Lossclk/Stbyret" "Limp mode,Stopmode"
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bitfld.long 0x04 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector" "Reserved,?,HS2,Reserved,HS1,Reserved,?..."
newline
bitfld.long 0x04 8. "RELAXED_LOCK,Decides when FREQLOCK asserted" "FREQLOCK asserted when DC frequency error less..,FREQLOCK asserted when DC frequency error less.."
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bitfld.long 0x04 1. "SSCTYPE,SSC Type" "0,1"
newline
bitfld.long 0x04 0. "TINTZ,PLL core soft reset" "0,1"
line.long 0x08 "PLL_DSP_TENABLE,"
bitfld.long 0x08 0. "TENABLE,M N" "0,1"
line.long 0x0C "PLL_DSP_TENABLEDIV,"
bitfld.long 0x0C 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
line.long 0x10 "PLL_DSP_M2NDIV,"
hexmask.long.byte 0x10 16.--22. 1. "M2,Post-divider is REGM2"
newline
hexmask.long.byte 0x10 0.--7. 1. "N,Pre-divider is REGN+1"
line.long 0x14 "PLL_DSP_MN2DIV,"
bitfld.long 0x14 16.--19. "N2,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 0.--11. 1. "M,Feedback Multiplier is REGM"
line.long 0x18 "PLL_DSP_FRACDIV,"
hexmask.long.byte 0x18 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance"
newline
hexmask.long.tbyte 0x18 0.--17. 1. "FRACTIONALM,Fractional part of the M divider"
line.long 0x1C "PLL_DSP_BWCTRL,"
bitfld.long 0x1C 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
newline
bitfld.long 0x1C 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth" "decrease BW,increase BW"
line.long 0x20 "PLL_DSP_FRACCTRL,"
bitfld.long 0x20 31. "DOWNSPREAD,Controls frequency spread" "enables both side frequency spread about the..,enables low frequency spread only"
newline
bitfld.long 0x20 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x20 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
newline
bitfld.long 0x20 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
newline
hexmask.long.tbyte 0x20 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
line.long 0x24 "PLL_DSP_STATUS,"
bitfld.long 0x24 31. "PONOUT,Status of the weak power-switch" "indicates the/OFF status of the weak..,ndicates the ON status of the weak power-switch.."
newline
bitfld.long 0x24 30. "PGOODOUT,Status of the strong power-switch" "indicates the/OFF status of the strong..,ndicates the ON status of the strong.."
newline
bitfld.long 0x24 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down" "0,1"
newline
bitfld.long 0x24 28. "RECAL_BSTATUS3,Recalibration status flag" "0,1"
newline
bitfld.long 0x24 27. "RECAL_OPPIN,Recalibration status flag" "0,1"
newline
bitfld.long 0x24 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
newline
bitfld.long 0x24 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
newline
bitfld.long 0x24 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
newline
bitfld.long 0x24 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
newline
bitfld.long 0x24 7. "STBYRETACK,Standby and retention status" "indicates to SOC that all internal clocks in..,indicates to SOC that all internal clocks in.."
newline
bitfld.long 0x24 6. "LOSSREF,Reference input loss" "0,1"
newline
bitfld.long 0x24 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN" "CLKOUT gating completed,CLKOUT enabling completed"
newline
bitfld.long 0x24 4. "LOCK2,ADPLL internal loop lock status" "0,1"
newline
bitfld.long 0x24 3. "M2CHANGEACK,Acknowledge for change to M2 divider" "0,1"
newline
bitfld.long 0x24 2. "SSCACK,Spread Spectrum status" "Spread-spectrum Clocking is disabled on output..,Spread-spectrum Clocking is enabled on output.."
newline
bitfld.long 0x24 1. "HIGHJITTER,1 indicates jitter" "0,1"
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bitfld.long 0x24 0. "BYPASS,Bypass status signal" "0,1"
line.long 0x28 "PLL_DSP_HSDIVIDER,"
rbitfld.long 0x28 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
newline
rbitfld.long 0x28 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
newline
bitfld.long 0x28 2. "TENABLEDIV,Tenable Div" "0,1"
newline
bitfld.long 0x28 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x28 0. "BYPASS,HSDIVIDER Bypass" "0,1"
line.long 0x2C "PLL_DSP_HSDIVIDER_CLKOUT0,"
bitfld.long 0x2C 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
newline
rbitfld.long 0x2C 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x2C 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x2C 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x2C 0.--4. "DIV,DPLL post-divider factor M4 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x30 "PLL_DSP_HSDIVIDER_CLKOUT1,"
bitfld.long 0x30 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
newline
rbitfld.long 0x30 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
newline
bitfld.long 0x30 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x30 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
newline
bitfld.long 0x30 0.--4. "DIV,DPLL post-divider factor M5 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "PLL_DSP_HSDIVIDER_CLKOUT2,"
bitfld.long 0x34 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
newline
rbitfld.long 0x34 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
newline
bitfld.long 0x34 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x34 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
newline
bitfld.long 0x34 0.--4. "DIV,DPLL post-divider factor M6 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "PLL_DSP_HSDIVIDER_CLKOUT3,"
bitfld.long 0x38 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
newline
rbitfld.long 0x38 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
newline
bitfld.long 0x38 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x38 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
newline
bitfld.long 0x38 0.--4. "DIV,DPLL post-divider factor M7 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "PLL_PER_PWRCTRL,"
bitfld.long 0x3C 5. "PONIN,ON/OFF control of the weak power switch digital" "0,1"
newline
bitfld.long 0x3C 4. "PGOODIN,ON/OFF control of the strong power switch digital" "0,1"
newline
bitfld.long 0x3C 3. "RET,Save/Restore control for Retention mode" "0,1"
newline
bitfld.long 0x3C 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
newline
bitfld.long 0x3C 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins" "0,1"
newline
bitfld.long 0x3C 0. "OFFMODE,Used to switch OFF the logic on VDDA" "0,1"
line.long 0x40 "PLL_PER_CLKCTRL,"
bitfld.long 0x40 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK" "0,1"
newline
bitfld.long 0x40 30. "ENSSC,Controls Clock Spreading" "0,1"
newline
bitfld.long 0x40 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO" "synchronously disables CLKDCOLDO,synchronously enables CLKDCOLDO"
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bitfld.long 0x40 24.--28. "NWELLTRIM,Trim value for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 23. "IDLE,Sets PLL to Idle mode" "When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL.."
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bitfld.long 0x40 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module" "0,1"
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bitfld.long 0x40 21. "STBYRET,Standby retention control" "prepares ADPLLLJ for relock when out of..,prepares ADPLLLJ for retention by gating all the.."
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bitfld.long 0x40 20. "CLKOUTEN,CLKOUT enable or disable" "synchronously disables CLKOUT,synchronously enables CLKOUT"
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bitfld.long 0x40 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO" "synchronously disables CLKOUTLDO,synchronously enables CLKOUTLDO"
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bitfld.long 0x40 18. "ULOWCLKEN,Select CLKOUT source in bypass" "When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1),When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW"
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bitfld.long 0x40 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p" "0,1"
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bitfld.long 0x40 16. "M2PWDNZ,M2 divider power down mode" "Asynchronous power down for M2 divider,M2 divider is functional"
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bitfld.long 0x40 14. "STOPMODE,When in Lossclk/Stbyret" "Limp mode,Stopmode"
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bitfld.long 0x40 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector" "Reserved,?,HS2,Reserved,HS1,Reserved,?..."
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bitfld.long 0x40 8. "RELAXED_LOCK,Decides when FREQLOCK asserted" "FREQLOCK asserted when DC frequency error less..,FREQLOCK asserted when DC frequency error less.."
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bitfld.long 0x40 1. "SSCTYPE,SSC Type" "0,1"
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bitfld.long 0x40 0. "TINTZ,PLL core soft reset" "0,1"
line.long 0x44 "PLL_PER_TENABLE,"
bitfld.long 0x44 0. "TENABLE,M N" "0,1"
line.long 0x48 "PLL_PER_TENABLEDIV,"
bitfld.long 0x48 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
line.long 0x4C "PLL_PER_M2NDIV,"
hexmask.long.byte 0x4C 16.--22. 1. "M2,Post-divider is REGM2"
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hexmask.long.byte 0x4C 0.--7. 1. "N,Pre-divider is REGN+1"
line.long 0x50 "PLL_PER_MN2DIV,"
bitfld.long 0x50 16.--19. "N2,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x50 0.--11. 1. "M,Feedback Multiplier is REGM"
line.long 0x54 "PLL_PER_FRACDIV,"
hexmask.long.byte 0x54 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance"
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hexmask.long.tbyte 0x54 0.--17. 1. "FRACTIONALM,Fractional part of the M divider"
line.long 0x58 "PLL_PER_BWCTRL,"
bitfld.long 0x58 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
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bitfld.long 0x58 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth" "decrease BW,increase BW"
line.long 0x5C "PLL_PER_FRACCTRL,"
bitfld.long 0x5C 31. "DOWNSPREAD,Controls frequency spread" "enables both side frequency spread about the..,enables low frequency spread only"
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bitfld.long 0x5C 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x5C 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
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bitfld.long 0x5C 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
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hexmask.long.tbyte 0x5C 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
line.long 0x60 "PLL_PER_STATUS,"
bitfld.long 0x60 31. "PONOUT,Status of the weak power-switch" "indicates the/OFF status of the weak..,ndicates the ON status of the weak power-switch.."
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bitfld.long 0x60 30. "PGOODOUT,Status of the strong power-switch" "indicates the/OFF status of the strong..,ndicates the ON status of the strong.."
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bitfld.long 0x60 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down" "0,1"
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bitfld.long 0x60 28. "RECAL_BSTATUS3,Recalibration status flag" "0,1"
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bitfld.long 0x60 27. "RECAL_OPPIN,Recalibration status flag" "0,1"
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bitfld.long 0x60 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x60 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x60 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
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bitfld.long 0x60 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
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bitfld.long 0x60 7. "STBYRETACK,Standby and retention status" "indicates to SOC that all internal clocks in..,indicates to SOC that all internal clocks in.."
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bitfld.long 0x60 6. "LOSSREF,Reference input loss" "0,1"
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bitfld.long 0x60 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN" "CLKOUT gating completed,CLKOUT enabling completed"
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bitfld.long 0x60 4. "LOCK2,ADPLL internal loop lock status" "0,1"
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bitfld.long 0x60 3. "M2CHANGEACK,Acknowledge for change to M2 divider" "0,1"
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bitfld.long 0x60 2. "SSCACK,Spread Spectrum status" "Spread-spectrum Clocking is disabled on output..,Spread-spectrum Clocking is enabled on output.."
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bitfld.long 0x60 1. "HIGHJITTER,1 indicates jitter" "0,1"
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bitfld.long 0x60 0. "BYPASS,Bypass status signal" "0,1"
line.long 0x64 "PLL_PER_HSDIVIDER,"
rbitfld.long 0x64 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
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rbitfld.long 0x64 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
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bitfld.long 0x64 2. "TENABLEDIV,Tenable Div" "0,1"
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bitfld.long 0x64 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x64 0. "BYPASS,HSDIVIDER Bypass" "0,1"
line.long 0x68 "PLL_PER_HSDIVIDER_CLKOUT0,"
bitfld.long 0x68 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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rbitfld.long 0x68 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x68 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x68 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x68 0.--4. "DIV,DPLL post-divider factor M4 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x6C "PLL_PER_HSDIVIDER_CLKOUT1,"
bitfld.long 0x6C 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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rbitfld.long 0x6C 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x6C 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x6C 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x6C 0.--4. "DIV,DPLL post-divider factor M5 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x70 "PLL_PER_HSDIVIDER_CLKOUT2,"
bitfld.long 0x70 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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rbitfld.long 0x70 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x70 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x70 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x70 0.--4. "DIV,DPLL post-divider factor M6 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x74 "PLL_PER_HSDIVIDER_CLKOUT3,"
bitfld.long 0x74 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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rbitfld.long 0x74 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x74 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x74 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x74 0.--4. "DIV,DPLL post-divider factor M7 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x78 "PLL_DSP_RSTCTRL,"
bitfld.long 0x78 0.--2. "assert,SW Reset override for the PLL" "0,1,2,3,4,5,6,7"
line.long 0x7C "PLL_DSP_HSDIVIDER_RSTCTRL,"
bitfld.long 0x7C 0.--2. "assert,SW Reset override for the HSDIVIDER" "0,1,2,3,4,5,6,7"
line.long 0x80 "PLL_PER_RSTCTRL,"
bitfld.long 0x80 0.--2. "assert,SW Reset override for the PLL" "0,1,2,3,4,5,6,7"
line.long 0x84 "PLL_PER_HSDIVIDER_RSTCTRL,"
bitfld.long 0x84 0.--2. "assert,SW Reset override for the HSDIVIDER" "0,1,2,3,4,5,6,7"
group.long 0xC00++0x13
line.long 0x00 "ANA_REG_CLK_CTRL_REG1_XO_SLICER,"
bitfld.long 0x00 31. "OSC_CLKOUT_EN,OSC_CLKOUT Enable Enables the Slicer clock to drive the OSC_CLKOUT output buffer" "Functional Reset,Clock Enabled"
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bitfld.long 0x00 29.--30. "OSC_CLKOUT_FREQ_SEL,OSC_CLKOUT Frequency Selection Selects the output frequency as a division of the XTAL (or externally driven CLKP) frequency" "Functional Reset,?,XTAL/1,XTAL/4"
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bitfld.long 0x00 28. "OSC_CLKOUT_CLRZ_DIV,OSC_CLKOUT Divider ClearZ This active low signal permits the output frequency dividers to be properly cleared before enabling" "All dividers cleared,Functional Reset"
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bitfld.long 0x00 24.--27. "OSC_CLKOUT_DRV,OSC_CLKOUT Drive This bit controls the drive strength of the OSC_CLKOUT buffer" "No Test Output Hi-Z Output Drive Ctrl =..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Functional Reset"
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hexmask.long.word 0x00 13.--23. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x00 12. "XTAL_DETECT_XO_SLICER,XTAL Detect Enable This bit connects a pullup and sense circuitry to CLKM to detect the presence or absence of a crystal" "Functional Reset,XTAL sense function enabled (pullup and sense.."
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bitfld.long 0x00 11. "SLICER_DCCPL_XO_SLICER,Slicer DC-Coupled Mode" "Functional Reset,DC-couple CLKP to internal slicer to CLKP"
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bitfld.long 0x00 10. "SLICER_HIPWR_XO_SLICER,Slicer High-power Mode This bit bypasses the input clock slicer current-starving/filtering circuitry to increase gain and reduce device phase-noise at the expense of power and reduced supply noise rejection" "Functional Reset,High-power/high-speed test mode"
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bitfld.long 0x00 9. "FASTCHARGEZ_BIAS_XO_SLICER,Bias Fast-charge Enable (Active Low) This bit bypasses the RC filtering on the XOSC/SLICER Bias to permit more rapid power-up" "Bias fast-charge,Functional Reset"
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bitfld.long 0x00 4.--8. "XOSC_DRIVE_XO_SLICER,Crystal Oscillator Output Drive Binary-weighted oscillator drive control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--3. "RTRIM_BIAS_XO_SLICER,Crystal Oscillator and Slicer Bias RTrim Binary-weighted bias control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ANA_REG_CLK_CTRL_REG1_CLKTOP,"
hexmask.long 0x04 3.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x04 2. "ENABLE_XOSC,Enable Crystal Oscillator" "Disabled,Functional Reset"
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bitfld.long 0x04 1. "ENABLE_SLICER_CLKP,Enable CLKP Input Slicer" "Disabled,Functional Reset"
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bitfld.long 0x04 0. "ENABLE_BIAS_XO_SLICER,Enable Bias for Crystal Oscillator and Slicer" "Disabled,Functional Reset"
line.long 0x08 "ANA_REG_CLK_CTRL_REG2_CLKTOP,"
bitfld.long 0x08 31. "CTRL_DC_BIST_BUFEN,Disable for CLK_TOP DC BIST BUFFER" "Functional Reset,CLK TOP DC BIST BUFFER DISABLED"
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hexmask.long 0x08 0.--30. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
line.long 0x0C "ANA_REG_CLK_CTRL_REG1_LDO_CLKTOP,"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED1,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x0C 7. "CLK_BIST_DISABLE_LDO,DC BIST Disable for LDO" "Functional Reset,DC BIST Disabled"
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bitfld.long 0x0C 1.--6. "RESERVED0,Reserved Reads return 0x0 and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 0. "EN_SLICER_LDO,Slicer LDO Enable" "Slicer LDO Disabled,Functional Reset"
line.long 0x10 "ANA_REG_CLK_CTRL_REG2_LDO_CLKTOP,"
hexmask.long.byte 0x10 24.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x10 20.--23. "BISTMUX_CTRL,SLICER LDO BIST MUX CONTROL (ONE HOT) Analog MUX enables to BIST output port" "HI-Z Output,VBG_0P9*10/9 =1.0 V,VDD18*0.5 = 0.9V,?,Functional Reset,?,?,?,Floating WARNING: Enabling more than one bit..,?..."
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bitfld.long 0x10 16.--19. "TESTMUX_CTRL,SLICER LDO TEST MUX CONTROL (ONE HOT) Analog MUX enables to test output port" "Functional Reset,0.6 * VLDO_OUT,VDD18*0.5 = 0.9V,?,VSSA,?,?,?,LDO Test Current (12.5uA) WARNING:..,?..."
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bitfld.long 0x10 13.--15. "TLOAD_CTRL,SLICER LDO TLOAD CONTROL updated description needed" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 12. "ENABLE_PMOS_PULLDOWN,SLICER LDO PMOS PULL DOWN ENABLE" "Functional Reset,Slicer LDO PMOS Pull Down enabled"
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bitfld.long 0x10 11. "SCPRT_IBIAS_CTRL,SLICER LDO SHORT CKT PROTECTION IBIAS CONTROL" "Functional Reset,2X Nominal short circuit bias with higher.."
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bitfld.long 0x10 8.--10. "LDO_BW_CTRL,SLICER LDO BANDWIDTH CONTROL need updated description" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 7. "EN_BYPASS,SLICER LDO BYPASS ENABLE" "Functional Reset,Slicer LDO Bypassed with external voltage"
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bitfld.long 0x10 6. "EN_SHRT_CKT,SLICER LDO SHORT CKT PROTECTION ENABLE" "Functional Reset,Slicer LDO Short Ckt Protection Enabled"
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bitfld.long 0x10 5. "EN_TEST_MODE,SLICER LDO TEST MODE ENABLE" "Functional Reset,Slicer LDO TEST MODE Enabled"
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bitfld.long 0x10 4. "ENZ_LOW_BW_CAP,SLICER LDO LOW BW MODE DISABLE" "Slicer LDO Low BW mode Disabled,Functional Reset"
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bitfld.long 0x10 0.--3. "LDO_VOUT_CTRL,SLICER LDO VOUT TRIM NEEDS updated description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xC18++0x2F
line.long 0x00 "ANA_REG_CLK_STATUS_REG,"
hexmask.long 0x00 1.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x00 0. "SLICER_LDO_SC_OUT,SLICER LDO SHORT CIRCUIT INDICATOR" "Normal operation,LDO Output Short Circuit Detected"
line.long 0x04 "ANA_REG_REFSYS_CTRL_REG_LOWV,"
bitfld.long 0x04 31. "RESERVED2,Reserved" "0,1"
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bitfld.long 0x04 27.--30. "FTRIM_3_0,Filter TRIM Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 26. "RESERVED1,<7> Unused" "0,1"
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bitfld.long 0x04 25. "IDIODE_EN,<6> Idiode Active Low Control --> Unused in TPR Reserved for AWR <0> - Enable <1> - Disable" "0,1"
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bitfld.long 0x04 24. "REFSYS_V2I_BYPASS_EN,<5> REFSYS V2I By-Pass Enable" "0,1"
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bitfld.long 0x04 23. "TX_TOP_IBIAS_EN,<4> TX TOP IBIAS EN--> Unused in TPR Reserved for AWR" "0,1"
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bitfld.long 0x04 22. "LODIST_IBIAS_EN,<3> LO DIST BIAS EN --> Unused in TPR Reserved for AWR" "0,1"
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bitfld.long 0x04 21. "CLKTOP_IBIAS_EN,<2> CLK TOP IBIAS EN" "0,1"
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bitfld.long 0x04 20. "V2I_STARTUP,<1> V2I Startup" "0,1"
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bitfld.long 0x04 19. "BGAP_ISW,<0> BGAP ISW STARTUP" "0,1"
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bitfld.long 0x04 14.--18. "IREF_TRIM_4_0,Default Resistor Trim for NOM LOT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 9.--13. "MAG_TRIM_4_0,Default Magnitude Trim for NOM LOT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 4.--8. "SLOPE_TRIM_4_0,Default Slope Trim for NOM LOT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 3. "REFSYS_PRE_CHARGE,REFSYS Pre Charge Control" "Functional Reset,Enable Pre Charge Block"
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bitfld.long 0x04 2. "REFSYS_CAP_SW_CTRLZ,REFSYS Cap Switch Control" "Functional Reset,Disconnect External Cap to Reference output"
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bitfld.long 0x04 1. "REFSYS_V2I_EN_CTRL,REFSYS Enable Control" "Disable V2I REFSYS,Functional Reset"
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bitfld.long 0x04 0. "REFSYS_BGAP_EN_CTRL,REFSYS Enable Control" "Disable REFSYS,Functional Reset"
line.long 0x08 "ANA_REG_REFSYS_TMUX_CTRL_LOWV,"
bitfld.long 0x08 31. "REFSYS_CTRL_8,REFSYS Test Mux Enable" "Functional Reset,TMUX Enabled"
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hexmask.long.word 0x08 16.--30. 1. "RESERVED1,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x08 15. "LO_IBIASP_20u,<15> LO IBG BIASP 20uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 14. "TX_IBIASP_20u,<14> TX IBG BIASP 20uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 13. "BYPASS_MIRR_VPBIAS,VPBIAS Control for IREF Gen Test Mode V2I By-Pass Feature" "0,1"
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bitfld.long 0x08 12. "I2V_SENSE,Sense Voltage from the BIST I2V cinversion of 20u and 6u bias current paths Sense voltage of 1V for BIST select<6> Sense voltage of 0.3V for BIST select<7>" "0,1"
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bitfld.long 0x08 11. "VSSA_REF,<11> VSSA REF (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 10. "IREFP_10UA,<10> IREFP 10uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 9. "IDIODEP_100U,<9> Idiode BIASP 100uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 8. "RESERVED4,Unused" "0,1"
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bitfld.long 0x08 7. "IBIASP_TS_6U,<7> IBG BIASP TS 6uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 6. "IBIASP_20U,<6> CLK IBG BIASP 20uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 5. "RESERVED3,Unused" "0,1"
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bitfld.long 0x08 4. "VBE_WEAK,<4> - VBE Weak (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 3. "RESERVED2,Unused" "0,1"
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bitfld.long 0x08 2. "VBG_1P22V,<2> - VBG 1.22V (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 1. "VREF_0P9V,<1> - VREF 0P9V (Cap Node) (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 0. "VREF_0P45V,<0> - VREF 0P45 (TMUX One-Hot)" "0,1"
line.long 0x0C "ANA_REG_REFSYS_SPARE_REG_LOWV,"
bitfld.long 0x0C 31. "ANALOGTEST_TMUX_ESD_CTRL,ANALOGTEST TMUX ESD CTRL in Pad-Frame (formerly RX_REFSYS_TMUX_SPARE_CTRL_LOWV<31> in AWR/IWR devices but RX does not exist in TPR)" "0,1"
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hexmask.long.word 0x0C 22.--30. 1. "REFSYS_SPARE_30_22,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x0C 21. "VDD_OV_RSET_EN,If asserted VDD_OV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 20. "VDD_UV_RSET_EN,If asserted VDD_UV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 19. "VDDA_OSC_UV_RSET_EN,If asserted VDDA_OSC_UV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 18. "VIOIN_UV_RSET_EN,If asserted VIOIN_UV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 16.--17. "VDD_OV_SR_SEL,Final level of VDD 1.2V VMON OV Reference Selection See definition in REFSYS_SPARE_REG<15:14>" "0,1,2,3"
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bitfld.long 0x0C 14.--15. "VDD_OV_IR_DROP_COMP_SEL,VDD 1.2V VMON OV Reference Selection Reference selection is dependent on REFSYS_SPARE_REG<17:16> programming If REFSYS_SPARE_REG<17:16> = 0x0" "Functional..,0.58V,0.57V,0.56V"
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bitfld.long 0x0C 13. "RESERVED1,Reserved Reserved in case VIOIN OV VMON and self test is ever implemented" "0,1"
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bitfld.long 0x0C 12. "VDDS_3P3V_UV_SELF_TEST_SEL,Enable VIOIN Strict UV VMON Self Test If Self-test mode is enabled VIOIN UV VMON reference is programmed as follows for REFSYS_SPARE_REG<3:2>" "Functional..,0.64V"
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bitfld.long 0x0C 11. "RESERVED0,Reserved Reserved in case VDDA_OSC OV VMON and self test is ever implemented" "0,1"
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bitfld.long 0x0C 10. "VDDA_OSC_UV_SELF_TEST_SEL,Enable VDDA_OSC Strict UV VMON Self Test If Self-test mode is enabled VDDA_OSC UV VMON reference is programmed as follows for REFSYS_SPARE_REG<5:4>" "Functional..,0.64V"
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bitfld.long 0x0C 9. "VDD_OV_SELF_TEST_SEL,Enable 1.2V VDD Strict OV VMON Self Test If Self-test mode is enabled VDD 1.2V VMON OV reference is programmed based on REFSYS_SPARE_REG<1:0> as follows: If REFSYS_SPARE_REG<7:6> = 0x0 REFSYS_SPARE_REG<1:0>" "Functional..,0.5V"
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bitfld.long 0x0C 8. "VDD_UV_SELF_TEST_SEL,Enable 1.2V VDD Strict UV VMON Self Test If Self-test mode is enabled VDD 1.2V VMON UV reference is programmed based on REFSYS_SPARE_REG<15:14> as follows: If REFSYS_SPARE_REG<17:16> = 0x0 REFSYS_SPARE_REG<15:14>" "Functional..,0.58V"
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bitfld.long 0x0C 6.--7. "VDD_SR_SEL,Final level of VDD 1.2V VMON UV Reference Selection See definition in REFSYS_SPARE_REG<1:0>" "0,1,2,3"
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bitfld.long 0x0C 4.--5. "VDDA_OSC_IR_DROP_COMP_SEL,VDDA_OSC UV VMON Reference Selection" "Functional..,0.54V,0.52V,0.5V"
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bitfld.long 0x0C 2.--3. "VDDS_3P3V_IR_DROP_COMP_SEL,VIOIN VMON UV Reference Selection" "Functional..,0.54V,0.52V,0.5V"
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bitfld.long 0x0C 0.--1. "VDD_IR_DROP_COMP_SEL,VDD 1.2V VMON UV Reference Selection Reference selection is dependent on REFSYS_SPARE_REG<7:6> programming If REFSYS_SPARE_REG<7:6> = 0x0" "Functional..,0.5V,0.49V,0.48V"
line.long 0x10 "ANA_REG_WU_CTRL_REG_LOWV,"
bitfld.long 0x10 31. "RESERVED0,Reserved Reads return 0x0 and writes have no effect" "0,1"
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bitfld.long 0x10 29.--30. "WU_SPARE_IN_2,WU Spare Control" "0,1,2,3"
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bitfld.long 0x10 28. "WU_VDD_OV_VMON_EN,WU VDD OV VMON Enable Control" "Functional Reset,VDD OV Detect Enabled"
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bitfld.long 0x10 27. "WU_VDD_UV_VMON_EN,WU VDD UV VMON Enable Control" "Functional Reset,VDD UV Detect Enabled"
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bitfld.long 0x10 26. "WU_VDDA_OSC_UV_VMON_EN,WU VDDA OSC UV VMON Enable Control" "Functional Reset,VDDA OSC UV Detect Enabled"
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bitfld.long 0x10 25. "WU_VDDS_3P3V_UV_VMON_EN,WU VDDS 3.3V UV VMON Enable Control" "Functional Reset,VDDS 3.3V UV Detect Enabled"
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bitfld.long 0x10 23.--24. "WU_SPARE_IN,WU Spare Control Change for 1642 ES2P0 Change Name : Newly added OR gates to provide options to bypass crude VDD DET (also refer to <11>) Bit <0> of this field when HIGH over rides the crude VDD_DET this control is using firmware Bit<0> of.." "0,1,2,3"
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bitfld.long 0x10 22. "WU_SUPP_DET_CTRL,WU VMON Detect Status Override Disable in Functional Test SOP" "VMON Det Status Override Disabled,Functional Reset"
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bitfld.long 0x10 21. "WU_VRAM_VMON_EN,WU VRAM VMON Enable Control" "SRAM UV Detect Disabled,Functional Reset"
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bitfld.long 0x10 20. "WU_SUPP_VMON_EN,WU VMON Enable Control" "VMON Control Disabled,Functional Reset"
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bitfld.long 0x10 19. "WU_XTAL_DLY_CTRL,Introduce additional delay for XTAL settling" "Functional Reset,Introduce additional delay as per WU-SEQ"
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bitfld.long 0x10 18. "WU_OV_DET_CTRL,WU Over Voltage Detect Control Changed for 1243 ES3P0 (Metal only change from 1642 ES2P0) Change Name : FW control of VDD OV DET EN" "OV Detect is Enabled,Functional Reset"
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bitfld.long 0x10 17. "WU_UV_DET_CTRL,WU Under Voltage Detect Control" "UV Detect is disabled,Functional Reset"
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bitfld.long 0x10 16. "XTAL_EN_OVERRIDE,XTAL EN Override (WU-SEQ) Control" "Functional Reset,Override XTAL Enable if disabled by default"
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bitfld.long 0x10 15. "WU_CPU_CLK_CTRL,WU CLK Control" "CLK Monitor Function in Dig Sequencer is..,Functional Reset"
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bitfld.long 0x10 11.--14. "INT_CLK_FREQ_SEL_3_0,WU Internal Clock (RCOSC) Frequency Select Bit<3> is used as override for VMON on Untrimmed devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 3.--10. 1. "INT_CLK_TRIM_7_0,WU lnternal Clock (RCOSC) Trim"
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bitfld.long 0x10 2. "INT_CLK_SW_SEL,WU Internal Clock (RCOSC) SW_SEL" "TBD,.."
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bitfld.long 0x10 1. "INT_CLK_STOP,WU Internal Clock (RCOSC) STOP" "Functional Reset,Internal CLK is OFF"
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bitfld.long 0x10 0. "INT_CLK_EN,WU Internal Clock (RCOSC) ENABLE" "Internal CLK Disabled,Functional Reset"
line.long 0x14 "ANA_REG_WU_TMUX_CTRL_LOWV,"
bitfld.long 0x14 31. "WU_TMUX_EN,WU TMUX Enable" "Functional Reset,TMUX Enabled"
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hexmask.long.word 0x14 21.--30. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x14 20. "VDDSINT18,VIOIN scaled supply for VIOIN Detect Scaling Factor: VIOIN*(52/90)" "0,1"
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bitfld.long 0x14 19. "SCALED_VDDA_OSC,Scaled VDDA_OSC supply for crude supply detect Scaling Factor: VDDA_OSC*(22/39)" "0,1"
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bitfld.long 0x14 18. "VFB_0P85V,Scaled VDD 1.2V used as reference for VDDA_OSC crude supply detect" "0,1"
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bitfld.long 0x14 17. "VDDA_OSC_UV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 16. "VDD_SR_UV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 15. "VT_DIG_SIG_OV,Test Mux Control" "0,1"
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bitfld.long 0x14 14. "VT_DIG_SIG_UV,Test Mux Control" "0,1"
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bitfld.long 0x14 13. "VT_ANA_SIG,Test Mux Control" "0,1"
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bitfld.long 0x14 12. "VDDA14_2_INT,Test Mux Control" "0,1"
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bitfld.long 0x14 11. "SCALED_VDDA_LVDS_1P8V_1P2,Test Mux Control" "0,1"
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bitfld.long 0x14 10. "VDDA14_INT,Test Mux Control" "0,1"
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bitfld.long 0x14 9. "VIOIN_UV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 8. "SCALED_VDDA18,Test Mux Control" "0,1"
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bitfld.long 0x14 7. "VREF_0P9V,Test Mux Control" "0,1"
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bitfld.long 0x14 6. "VDD_SR_OV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 5. "SCALED_VDDA_LVDS_1P8V,Test Mux Control" "0,1"
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bitfld.long 0x14 4. "SCALED_VIOIN,Test Mux Control" "0,1"
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bitfld.long 0x14 3. "VFB_0P6V,Test Mux Control" "0,1"
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bitfld.long 0x14 2. "SCALED_VDDS18,Test Mux Control" "0,1"
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bitfld.long 0x14 1. "SCALED_VIO3318,Test Mux Control" "0,1"
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bitfld.long 0x14 0. "SCALED_VDDA_OSC_UV,Test Mux Control" "0,1"
line.long 0x18 "ANA_REG_TW_CTRL_REG_LOWV,"
hexmask.long.word 0x18 20.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x18 15.--19. "RTRIM_TW_4_0,RTRIM value to TW routed to BIST MUX IN REFSYS for I2V" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 14. "ANA_TMUX_BUF_EN,TW ANA TMUX Buffer Enabled" "Functional Reset,ANA TMUX Buffer Enabled"
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bitfld.long 0x18 13. "ANA_TMUX_BUF_BYPASS,TW ANA TMUX Buffer Bypass" "Functional Reset,ANA TMUX Buffer By-pass Enabled"
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bitfld.long 0x18 12. "VIN_EXT_CTRL,TW VIN Control from External Source" "Functional Reset,External VIN Control Enabled"
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bitfld.long 0x18 11. "VREF_EXT_CTRL,TW VREF Control from External SOurce" "Functional Reset,External VREF Control Enabled"
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bitfld.long 0x18 10. "IFORCE_EXT_CTRL,TW Iforce Control from External Source" "Functional Reset,IFORCE Control Enabled"
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bitfld.long 0x18 9. "TS_SE_INP_BUF_EN,TW ADC TS SE Inp Buffer Enable" "Functional Reset,Input Buffer Enabled"
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bitfld.long 0x18 8. "TS_DIFF_INP_BUF_EN,TW ADC TS DIFF Inp Buffer Enable" "Input Buffer disabled,Functional Reset"
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bitfld.long 0x18 5.--7. "ADC_REF_SEL_2_0,TW ADC Reference Select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 4. "ADC_REF_BUF_EN,TW ADC Reference Buffer Enable" "Input Buffer disabled,Functional Reset"
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bitfld.long 0x18 3. "ADC_INP_BUF_EN,TW ADC Input Buffer Enable" "Input Buffer disabled,Functional Reset"
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bitfld.long 0x18 2. "ADC_RESET,TW ADC Reset (Active High)" "ADC Out of Reset,Functional Reset"
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bitfld.long 0x18 1. "ADC_START_CONV,TW ADC Start Conversion" "0,1"
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bitfld.long 0x18 0. "ADC_EN,TW ADC Control" "Functional Reset,ADC Enable"
line.long 0x1C "ANA_REG_TW_ANA_TMUX_CTRL_LOWV,"
bitfld.long 0x1C 31. "ANA_TEST_EN,TW ANA Test MUX Enabled" "Functional Reset,ANA TMUX Control Enabled"
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bitfld.long 0x1C 30. "CLK_TMUX_ESD_CTRL,CLK TMUX ESD CTRL in Pad-Frame" "0,1"
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hexmask.long.word 0x1C 19.--29. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x1C 18. "ATESTV_VSLDO,Enable Output of ATESTV of VSLDO" "0,1"
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bitfld.long 0x1C 17. "TMUX_BUF_OUT_EN,Enable Output of TMUX buffer" "0,1"
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bitfld.long 0x1C 16. "I2V_SENSE,I2V Sense Voltage of External IREF Forced" "0,1"
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bitfld.long 0x1C 15. "BIST_MUX_OUT_1P8V,BIST Mux output pre ADC input Buffer" "0,1"
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bitfld.long 0x1C 14. "ODP,Ibias current from Top Refsys for measurement on Test Pin" "0,1"
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bitfld.long 0x1C 13. "VBE_TS_WEAK,Single PNP Sense voltage for TSENSE selected" "0,1"
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bitfld.long 0x1C 12. "VBE_TS_STRONG,Multi PNP Sense voltage for TSENSE selected" "0,1"
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bitfld.long 0x1C 11. "DELVBE_BUFF_OUT,Difference TSENSE signal delVbe scaled and buffered for chosen TSENSE element" "0,1"
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bitfld.long 0x1C 10. "ADC_REF_BUF_OUT,ADC reference buffer out to Test Pin" "0,1"
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bitfld.long 0x1C 9. "ADC_BUF_OUT_1P8V,Buffered output of ADC inputs to GPADC" "0,1"
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bitfld.long 0x1C 8. "DC_BIST_BUF_INP_1P8V,DC BIST Buffered output of RX TX CLK LO (shorted on to this net)" "0,1"
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bitfld.long 0x1C 7. "VBE_W_BUFF,Buffered value of Weak PNP" "0,1"
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bitfld.long 0x1C 6. "VBE_S_BUFF,Buffered value of Strong PNP" "0,1"
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bitfld.long 0x1C 5. "PM_ANA_INP_5,CLK ANA Test Pin Mapped" "0,1"
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bitfld.long 0x1C 4. "PM_ANA_INP_4,RX ANA Test Mux Control" "0,1"
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bitfld.long 0x1C 3. "PM_ANA_INP_3,LODIST ANA Test Mux Control" "0,1"
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bitfld.long 0x1C 2. "PM_ANA_INP_2,TX PM ANA Test Mux Control" "0,1"
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bitfld.long 0x1C 1. "REFSYS_TEST_OUT_1P8V,Mux Output of Refsys Test Mux" "0,1"
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bitfld.long 0x1C 0. "WU_ANA_TEST_OUT_1P8V,Mux Output of WU Test Mux" "0,1"
line.long 0x20 "ANA_REG_TW_SPARE_LOWV,"
line.long 0x24 "ANA_REG_WU_MODE_REG_LOWV,"
hexmask.long 0x24 7.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x24 2.--6. "SOP_MODE_LAT_4_0,SOP Mode Latched Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 1. "TEST_MODE_DET_SYNC,Latched Output of Test Mode Detect SOP" "0,1"
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bitfld.long 0x24 0. "FUNC_TEST_DET_SYNC,Latched Output of Functional Test Mode SOP" "0,1"
line.long 0x28 "ANA_REG_WU_STATUS_REG_LOWV,"
hexmask.long.word 0x28 19.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x28 18. "VDDS_3P3V_UVDET_LAT,New in TPR: Latched Value of 3.3V IO UV Detect" "UV Detect Not Triggered,UV Detect has Triggered"
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bitfld.long 0x28 17. "VDDA_OSC_UVDET_LAT,Latched value of UV detect of LOMULT 1.8V supply (AWR devices) For TPR Latched Value of UV Detect of VDDA_OSC" "UV Detect Not Triggered,UV Detect has Triggered"
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bitfld.long 0x28 16. "SUPP_OK_APLLVCO18,Supp Detect output of APLL VCO 1.8V" "Supply Not detected,Supply Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 15. "HVMODE,HVMODE Status from VMON" "1.8V VIO,3.3V VIO"
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bitfld.long 0x28 14. "LIMP_MODE_STATUS,Ref CLK status at Wake-up" "REF CLK is present,REF CLK is absent and CPU CLK Switched to RCOSC"
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bitfld.long 0x28 13. "XTAL_DET_STATUS,XTAL Detect status at Wake-up" "XTAL absent,XTAL Present"
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bitfld.long 0x28 12. "RCOSC_CLK_STATUS,RCOSC status at Wake-up" "RCOSC CLK absent,RCOSC CLK Present"
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bitfld.long 0x28 11. "REF_CLK_STATUS,Ref CLK status at Wake-up" "REF CLK absent,REF CLK Present"
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bitfld.long 0x28 10. "SUPP_OK_VDDD18,Supp Detect output of LVDS 1.8V" "Supply Not detected,Supply Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 9. "SUPP_OK_SRAM12,UV Detect Status of SRAM" "UV Not Detected,UV Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 8. "SUPP_OK_RF2_14,Supp Detect output of RF2 1.4V Pin" "Supply Not detected,Supply Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 7. "SUPP_OK_RF14,Updated for 1642 ES2P0 Change name : Mux for VIN_13 OK in LDO bypass mode This output bit is always tied low Tied LO in TPR and AWR/IWR devices" "0,1"
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bitfld.long 0x28 6. "SUPP_OK_RF10,Updated for 1642 ES2P0 Change name : Mux for VIN_13 OK in LDO bypass mode When RF_LDO_BYPASS_EN = 1 this bit will be high when the supply is > 0.75 When RF_LDO_BYPASS_EN = 0 this bit will be high when the supply is > 1.05 Tied LO in TPR.." "0,1"
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bitfld.long 0x28 5. "SUPP_OK_IO33,Supp Detect output of IO 3.3V" "Supply Not detected,Supply Detected"
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bitfld.long 0x28 4. "SUPP_OK_IO18,Supp Detect output of IO 1.8V" "Supply Not detected,Supply Detected"
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bitfld.long 0x28 3. "SUPP_OK_CLK18,Supp Detect output of CLK 1.8V" "Supply Not detected,Supply Detected For TPR Crude detection of.."
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bitfld.long 0x28 2. "SUPP_OK_ANA18,Supp Detect output of Ana 1.8V Tied LO in TPR (unused VMON)" "Supply Not detected,Supply Detected"
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bitfld.long 0x28 1. "CORE_UVDET_LAT,Latched Value of UV Detect" "UV Detect Not Triggered,UV Detect has Triggered"
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bitfld.long 0x28 0. "CORE_OVDET_LAT,Latched Value of OV Detect" "OV Detect Not Triggered,OV Detect has Triggered"
line.long 0x2C "ANA_REG_WU_SPARE_OUT_LOWV,"
hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x2C 7. "CORE_UVDET_LOWV,UV Detect of Core Supply-Unlatched" "0,1"
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bitfld.long 0x2C 6. "CORE_OVDET_LOWV,OV Detect of Core Supply-Unlatched" "0,1"
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bitfld.long 0x2C 5. "INT_OSC_CTRL,Internal Oscillator Control" "0,1"
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bitfld.long 0x2C 4. "SUPPDET_OV_CTRL,Supply Detect Override Bit" "0,1"
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bitfld.long 0x2C 3. "HVMODE,Status of VIO supply" "0,1"
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bitfld.long 0x2C 2. "VDDS18DET,Status of 1.8V IO Bias Supply" "0,1"
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bitfld.long 0x2C 1. "VDDARF_DET,Status of 1.3V RF Supply" "0,1"
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bitfld.long 0x2C 0. "VDDCLK18DET,Status of 1.8V CLK Supply" "0,1"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_TPCC_A (MSS TPCCA Module Registers)"
base ad:0x53100000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
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bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
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bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
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bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
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bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
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bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
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bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
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bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
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hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
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hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
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bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
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bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
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bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
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bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
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bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
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bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
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bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
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bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
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bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
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bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
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bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
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bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
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bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
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bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
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bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
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bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
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bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
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bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
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bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
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bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
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bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
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bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
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bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
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bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
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bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
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bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
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bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
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bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
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bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
tree "MSS_TPCC_B (MSS TPCCB Module Registers)"
base ad:0x53120000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
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bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
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bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
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bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
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bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
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bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
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bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
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hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
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hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
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bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
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bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
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bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
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bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
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bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
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bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
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bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
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bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
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bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
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bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
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bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
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bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
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bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
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bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
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bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
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bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
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bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
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bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
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bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
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bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
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bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
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bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
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bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
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bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
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bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
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bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
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bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
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bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
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bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
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bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
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bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
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bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
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bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
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bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
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bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
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bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
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bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
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bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
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bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
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bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x53140000 ad:0x53160000 )
tree "MSS_TPTC_A$1 (MSS TPTC A$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
tree "MSS_TPTC_B0 (MSS TPTC B0 Module Registers)"
base ad:0x53180000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
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bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
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bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
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bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
tree "MSS_VIM_R5A (MSS VIM CR5 CORE A)"
base ad:0x52080000
rgroup.long 0x00++0x27
line.long 0x00 "PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INFO,The Info Register gives the configuration Inforrmation of this VIM"
hexmask.long.tbyte 0x04 11.--31. 1. "RES1,RESERVE FIELD"
hexmask.long.word 0x04 0.--10. 1. "INTERRUPTS,Total number of Interrupts"
line.long 0x08 "PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ"
bitfld.long 0x08 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x08 20.--30. 1. "RES2,RESERVE FIELD"
bitfld.long 0x08 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 10.--15. "RES3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 0.--9. 1. "NUM,Number of the highest priority pending IRQ"
line.long 0x0C "PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ"
bitfld.long 0x0C 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x0C 20.--30. 1. "RES4,RESERVE FIELD"
bitfld.long 0x0C 16.--19. "PRI,Priority of the highest priority pending FIQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 10.--15. "RES5,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x0C 0.--9. 1. "NUM,Number of the highest priority pending FIQ"
line.long 0x10 "IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts"
line.long 0x14 "FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts"
line.long 0x18 "IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ"
hexmask.long 0x18 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x18 0.--1. "RES21,RESERVE FIELD" "0,1,2,3"
line.long 0x1C "FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ"
hexmask.long 0x1C 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x1C 0.--1. "RES22,RESERVE FIELD" "0,1,2,3"
line.long 0x20 "ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ"
bitfld.long 0x20 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x20 20.--30. 1. "RES6,RESERVE FIELD"
bitfld.long 0x20 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 10.--15. "RES7,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "NUM,Number of the currently active IRQ"
line.long 0x24 "ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ"
bitfld.long 0x24 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x24 20.--30. 1. "RES8,RESERVE FIELD"
bitfld.long 0x24 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 10.--15. "RES9,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x24 0.--9. 1. "NUM,Number of the currently active FIQ"
group.long 0x30++0x03
line.long 0x00 "DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ"
hexmask.long 0x00 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x00 0.--1. "RES23,RESERVE FIELD" "0,1,2,3"
group.long 0x400++0xFF
line.long 0x00 "RAW,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x04 "STS,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x08 "INTR_EN_SET,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x0C "INTER_EN_CLR,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x10 "IRQSTS,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x14 "FIQSTS,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x18 "INTMAP,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x1C "INTTYPE,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x20 "RAW_1,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x24 "STS_1,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x28 "INTR_EN_SET_1,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x2C "INTER_EN_CLR_1,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x30 "IRQSTS_1,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x34 "FIQSTS_1,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x38 "INTMAP_1,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x3C "INTTYPE_1,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x40 "RAW_2,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x44 "STS_2,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x48 "INTR_EN_SET_2,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x4C "INTER_EN_CLR_2,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x50 "IRQSTS_2,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x54 "FIQSTS_2,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x58 "INTMAP_2,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x5C "INTTYPE_2,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x60 "RAW_3,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x64 "STS_3,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x68 "INTR_EN_SET_3,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x6C "INTER_EN_CLR_3,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x70 "IRQSTS_3,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x74 "FIQSTS_3,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x78 "INTMAP_3,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x7C "INTTYPE_3,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x80 "RAW_4,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x84 "STS_4,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x88 "INTR_EN_SET_4,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x8C "INTER_EN_CLR_4,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x90 "IRQSTS_4,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x94 "FIQSTS_4,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x98 "INTMAP_4,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x9C "INTTYPE_4,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xA0 "RAW_5,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xA4 "STS_5,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xA8 "INTR_EN_SET_5,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xAC "INTER_EN_CLR_5,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xB0 "IRQSTS_5,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xB4 "FIQSTS_5,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xB8 "INTMAP_5,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xBC "INTTYPE_5,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xC0 "RAW_6,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xC4 "STS_6,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xC8 "INTR_EN_SET_6,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xCC "INTER_EN_CLR_6,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xD0 "IRQSTS_6,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xD4 "FIQSTS_6,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xD8 "INTMAP_6,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xDC "INTTYPE_6,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xE0 "RAW_7,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xE4 "STS_7,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xE8 "INTR_EN_SET_7,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xEC "INTER_EN_CLR_7,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xF0 "IRQSTS_7,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xF4 "FIQSTS_7,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xF8 "INTMAP_7,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xFC "INTTYPE_7,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
group.long 0x1000++0x3FF
line.long 0x00 "INTPRIORITY,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h4"
hexmask.long 0x00 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x00 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTPRIORITY_1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
hexmask.long 0x04 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x04 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "INTPRIORITY_2,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h6"
hexmask.long 0x08 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x08 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "INTPRIORITY_3,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h7"
hexmask.long 0x0C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x0C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "INTPRIORITY_4,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h8"
hexmask.long 0x10 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "INTPRIORITY_5,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h9"
hexmask.long 0x14 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "INTPRIORITY_6,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h10"
hexmask.long 0x18 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "INTPRIORITY_7,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h11"
hexmask.long 0x1C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "INTPRIORITY_8,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h12"
hexmask.long 0x20 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "INTPRIORITY_9,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h13"
hexmask.long 0x24 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "INTPRIORITY_10,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h14"
hexmask.long 0x28 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "INTPRIORITY_11,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h15"
hexmask.long 0x2C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "INTPRIORITY_12,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h16"
hexmask.long 0x30 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "INTPRIORITY_13,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h17"
hexmask.long 0x34 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "INTPRIORITY_14,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h18"
hexmask.long 0x38 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "INTPRIORITY_15,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h19"
hexmask.long 0x3C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "INTPRIORITY_16,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h20"
hexmask.long 0x40 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x40 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "INTPRIORITY_17,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h21"
hexmask.long 0x44 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x44 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "INTPRIORITY_18,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h22"
hexmask.long 0x48 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x48 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "INTPRIORITY_19,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h23"
hexmask.long 0x4C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x4C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "INTPRIORITY_20,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h24"
hexmask.long 0x50 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x50 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "INTPRIORITY_21,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h25"
hexmask.long 0x54 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x54 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "INTPRIORITY_22,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h26"
hexmask.long 0x58 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x58 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "INTPRIORITY_23,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h27"
hexmask.long 0x5C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x5C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x60 "INTPRIORITY_24,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h28"
hexmask.long 0x60 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x60 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "INTPRIORITY_25,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h29"
hexmask.long 0x64 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x64 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "INTPRIORITY_26,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h30"
hexmask.long 0x68 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x68 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "INTPRIORITY_27,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h31"
hexmask.long 0x6C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x6C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "INTPRIORITY_28,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h32"
hexmask.long 0x70 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x70 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x74 "INTPRIORITY_29,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h33"
hexmask.long 0x74 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x74 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x78 "INTPRIORITY_30,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h34"
hexmask.long 0x78 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x78 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x7C "INTPRIORITY_31,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h35"
hexmask.long 0x7C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x7C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x80 "INTPRIORITY_32,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h36"
hexmask.long 0x80 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x80 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "INTPRIORITY_33,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h37"
hexmask.long 0x84 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x84 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "INTPRIORITY_34,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h38"
hexmask.long 0x88 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x88 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "INTPRIORITY_35,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h39"
hexmask.long 0x8C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x8C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "INTPRIORITY_36,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h40"
hexmask.long 0x90 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x90 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x94 "INTPRIORITY_37,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h41"
hexmask.long 0x94 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x94 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x98 "INTPRIORITY_38,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h42"
hexmask.long 0x98 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x98 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "INTPRIORITY_39,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h43"
hexmask.long 0x9C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x9C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA0 "INTPRIORITY_40,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h44"
hexmask.long 0xA0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "INTPRIORITY_41,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h45"
hexmask.long 0xA4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA8 "INTPRIORITY_42,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h46"
hexmask.long 0xA8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xAC "INTPRIORITY_43,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h47"
hexmask.long 0xAC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xAC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB0 "INTPRIORITY_44,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h48"
hexmask.long 0xB0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB4 "INTPRIORITY_45,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h49"
hexmask.long 0xB4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "INTPRIORITY_46,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h50"
hexmask.long 0xB8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xBC "INTPRIORITY_47,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h51"
hexmask.long 0xBC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xBC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC0 "INTPRIORITY_48,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h52"
hexmask.long 0xC0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "INTPRIORITY_49,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h53"
hexmask.long 0xC4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "INTPRIORITY_50,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h54"
hexmask.long 0xC8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "INTPRIORITY_51,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h55"
hexmask.long 0xCC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xCC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD0 "INTPRIORITY_52,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h56"
hexmask.long 0xD0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "INTPRIORITY_53,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h57"
hexmask.long 0xD4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD8 "INTPRIORITY_54,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h58"
hexmask.long 0xD8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "INTPRIORITY_55,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h59"
hexmask.long 0xDC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xDC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE0 "INTPRIORITY_56,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h60"
hexmask.long 0xE0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "INTPRIORITY_57,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h61"
hexmask.long 0xE4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE8 "INTPRIORITY_58,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h62"
hexmask.long 0xE8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "INTPRIORITY_59,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h63"
hexmask.long 0xEC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xEC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF0 "INTPRIORITY_60,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h64"
hexmask.long 0xF0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "INTPRIORITY_61,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h65"
hexmask.long 0xF4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF8 "INTPRIORITY_62,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h66"
hexmask.long 0xF8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "INTPRIORITY_63,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h67"
hexmask.long 0xFC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xFC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x100 "INTPRIORITY_64,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h68"
hexmask.long 0x100 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x100 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "INTPRIORITY_65,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h69"
hexmask.long 0x104 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x104 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x108 "INTPRIORITY_66,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h70"
hexmask.long 0x108 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x108 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10C "INTPRIORITY_67,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h71"
hexmask.long 0x10C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x110 "INTPRIORITY_68,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h72"
hexmask.long 0x110 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x110 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x114 "INTPRIORITY_69,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h73"
hexmask.long 0x114 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x114 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x118 "INTPRIORITY_70,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h74"
hexmask.long 0x118 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x118 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x11C "INTPRIORITY_71,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h75"
hexmask.long 0x11C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x11C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x120 "INTPRIORITY_72,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h76"
hexmask.long 0x120 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x120 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "INTPRIORITY_73,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h77"
hexmask.long 0x124 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x124 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x128 "INTPRIORITY_74,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h78"
hexmask.long 0x128 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x128 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x12C "INTPRIORITY_75,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h79"
hexmask.long 0x12C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x12C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x130 "INTPRIORITY_76,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h80"
hexmask.long 0x130 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x130 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x134 "INTPRIORITY_77,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h81"
hexmask.long 0x134 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x134 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x138 "INTPRIORITY_78,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h82"
hexmask.long 0x138 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x138 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x13C "INTPRIORITY_79,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h83"
hexmask.long 0x13C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x13C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x140 "INTPRIORITY_80,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h84"
hexmask.long 0x140 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x140 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "INTPRIORITY_81,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h85"
hexmask.long 0x144 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x144 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x148 "INTPRIORITY_82,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h86"
hexmask.long 0x148 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x148 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14C "INTPRIORITY_83,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h87"
hexmask.long 0x14C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x150 "INTPRIORITY_84,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h88"
hexmask.long 0x150 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x150 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x154 "INTPRIORITY_85,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h89"
hexmask.long 0x154 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x154 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x158 "INTPRIORITY_86,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h90"
hexmask.long 0x158 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x158 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x15C "INTPRIORITY_87,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h91"
hexmask.long 0x15C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x15C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x160 "INTPRIORITY_88,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h92"
hexmask.long 0x160 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x160 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "INTPRIORITY_89,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h93"
hexmask.long 0x164 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x164 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x168 "INTPRIORITY_90,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h94"
hexmask.long 0x168 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x168 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "INTPRIORITY_91,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h95"
hexmask.long 0x16C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x16C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x170 "INTPRIORITY_92,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h96"
hexmask.long 0x170 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x170 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "INTPRIORITY_93,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h97"
hexmask.long 0x174 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x174 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x178 "INTPRIORITY_94,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h98"
hexmask.long 0x178 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x178 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "INTPRIORITY_95,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h99"
hexmask.long 0x17C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x17C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x180 "INTPRIORITY_96,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h100"
hexmask.long 0x180 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x180 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "INTPRIORITY_97,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h101"
hexmask.long 0x184 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x184 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x188 "INTPRIORITY_98,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h102"
hexmask.long 0x188 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x188 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "INTPRIORITY_99,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h103"
hexmask.long 0x18C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "INTPRIORITY_100,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h104"
hexmask.long 0x190 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x190 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "INTPRIORITY_101,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h105"
hexmask.long 0x194 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x194 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x198 "INTPRIORITY_102,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h106"
hexmask.long 0x198 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x198 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "INTPRIORITY_103,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h107"
hexmask.long 0x19C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x19C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "INTPRIORITY_104,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h108"
hexmask.long 0x1A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "INTPRIORITY_105,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h109"
hexmask.long 0x1A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "INTPRIORITY_106,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h110"
hexmask.long 0x1A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "INTPRIORITY_107,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h111"
hexmask.long 0x1AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "INTPRIORITY_108,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h112"
hexmask.long 0x1B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "INTPRIORITY_109,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h113"
hexmask.long 0x1B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B8 "INTPRIORITY_110,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h114"
hexmask.long 0x1B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "INTPRIORITY_111,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h115"
hexmask.long 0x1BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C0 "INTPRIORITY_112,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h116"
hexmask.long 0x1C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "INTPRIORITY_113,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h117"
hexmask.long 0x1C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C8 "INTPRIORITY_114,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h118"
hexmask.long 0x1C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "INTPRIORITY_115,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h119"
hexmask.long 0x1CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "INTPRIORITY_116,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h120"
hexmask.long 0x1D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "INTPRIORITY_117,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h121"
hexmask.long 0x1D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D8 "INTPRIORITY_118,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h122"
hexmask.long 0x1D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "INTPRIORITY_119,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h123"
hexmask.long 0x1DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E0 "INTPRIORITY_120,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h124"
hexmask.long 0x1E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "INTPRIORITY_121,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h125"
hexmask.long 0x1E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E8 "INTPRIORITY_122,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h126"
hexmask.long 0x1E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1EC "INTPRIORITY_123,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h127"
hexmask.long 0x1EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F0 "INTPRIORITY_124,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h128"
hexmask.long 0x1F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F4 "INTPRIORITY_125,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h129"
hexmask.long 0x1F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F8 "INTPRIORITY_126,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h130"
hexmask.long 0x1F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1FC "INTPRIORITY_127,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h131"
hexmask.long 0x1FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x200 "INTPRIORITY_128,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h132"
hexmask.long 0x200 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x200 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x204 "INTPRIORITY_129,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h133"
hexmask.long 0x204 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x204 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x208 "INTPRIORITY_130,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h134"
hexmask.long 0x208 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x208 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20C "INTPRIORITY_131,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h135"
hexmask.long 0x20C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "INTPRIORITY_132,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h136"
hexmask.long 0x210 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x210 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x214 "INTPRIORITY_133,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h137"
hexmask.long 0x214 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x214 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x218 "INTPRIORITY_134,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h138"
hexmask.long 0x218 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x218 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x21C "INTPRIORITY_135,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h139"
hexmask.long 0x21C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x21C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x220 "INTPRIORITY_136,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h140"
hexmask.long 0x220 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x220 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x224 "INTPRIORITY_137,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h141"
hexmask.long 0x224 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x224 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x228 "INTPRIORITY_138,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h142"
hexmask.long 0x228 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x228 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x22C "INTPRIORITY_139,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h143"
hexmask.long 0x22C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x22C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x230 "INTPRIORITY_140,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h144"
hexmask.long 0x230 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x230 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x234 "INTPRIORITY_141,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h145"
hexmask.long 0x234 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x234 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x238 "INTPRIORITY_142,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h146"
hexmask.long 0x238 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x238 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x23C "INTPRIORITY_143,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h147"
hexmask.long 0x23C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x23C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x240 "INTPRIORITY_144,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h148"
hexmask.long 0x240 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x240 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x244 "INTPRIORITY_145,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h149"
hexmask.long 0x244 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x244 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x248 "INTPRIORITY_146,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h150"
hexmask.long 0x248 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x248 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24C "INTPRIORITY_147,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h151"
hexmask.long 0x24C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x250 "INTPRIORITY_148,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h152"
hexmask.long 0x250 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x250 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x254 "INTPRIORITY_149,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h153"
hexmask.long 0x254 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x254 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x258 "INTPRIORITY_150,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h154"
hexmask.long 0x258 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x258 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x25C "INTPRIORITY_151,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h155"
hexmask.long 0x25C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x25C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x260 "INTPRIORITY_152,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h156"
hexmask.long 0x260 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x260 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x264 "INTPRIORITY_153,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h157"
hexmask.long 0x264 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x264 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x268 "INTPRIORITY_154,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h158"
hexmask.long 0x268 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x268 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x26C "INTPRIORITY_155,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h159"
hexmask.long 0x26C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x26C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x270 "INTPRIORITY_156,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h160"
hexmask.long 0x270 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x270 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x274 "INTPRIORITY_157,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h161"
hexmask.long 0x274 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x274 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x278 "INTPRIORITY_158,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h162"
hexmask.long 0x278 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x278 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x27C "INTPRIORITY_159,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h163"
hexmask.long 0x27C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x27C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x280 "INTPRIORITY_160,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h164"
hexmask.long 0x280 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x280 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x284 "INTPRIORITY_161,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h165"
hexmask.long 0x284 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x284 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x288 "INTPRIORITY_162,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h166"
hexmask.long 0x288 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x288 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28C "INTPRIORITY_163,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h167"
hexmask.long 0x28C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x290 "INTPRIORITY_164,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h168"
hexmask.long 0x290 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x290 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x294 "INTPRIORITY_165,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h169"
hexmask.long 0x294 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x294 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x298 "INTPRIORITY_166,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h170"
hexmask.long 0x298 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x298 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x29C "INTPRIORITY_167,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h171"
hexmask.long 0x29C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x29C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A0 "INTPRIORITY_168,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h172"
hexmask.long 0x2A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A4 "INTPRIORITY_169,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h173"
hexmask.long 0x2A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A8 "INTPRIORITY_170,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h174"
hexmask.long 0x2A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2AC "INTPRIORITY_171,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h175"
hexmask.long 0x2AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B0 "INTPRIORITY_172,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h176"
hexmask.long 0x2B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B4 "INTPRIORITY_173,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h177"
hexmask.long 0x2B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B8 "INTPRIORITY_174,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h178"
hexmask.long 0x2B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2BC "INTPRIORITY_175,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h179"
hexmask.long 0x2BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C0 "INTPRIORITY_176,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h180"
hexmask.long 0x2C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C4 "INTPRIORITY_177,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h181"
hexmask.long 0x2C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C8 "INTPRIORITY_178,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h182"
hexmask.long 0x2C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2CC "INTPRIORITY_179,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h183"
hexmask.long 0x2CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D0 "INTPRIORITY_180,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h184"
hexmask.long 0x2D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D4 "INTPRIORITY_181,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h185"
hexmask.long 0x2D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D8 "INTPRIORITY_182,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h186"
hexmask.long 0x2D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2DC "INTPRIORITY_183,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h187"
hexmask.long 0x2DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E0 "INTPRIORITY_184,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h188"
hexmask.long 0x2E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E4 "INTPRIORITY_185,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h189"
hexmask.long 0x2E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E8 "INTPRIORITY_186,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h190"
hexmask.long 0x2E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2EC "INTPRIORITY_187,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h191"
hexmask.long 0x2EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F0 "INTPRIORITY_188,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h192"
hexmask.long 0x2F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F4 "INTPRIORITY_189,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h193"
hexmask.long 0x2F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F8 "INTPRIORITY_190,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h194"
hexmask.long 0x2F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2FC "INTPRIORITY_191,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h195"
hexmask.long 0x2FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x300 "INTPRIORITY_192,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h196"
hexmask.long 0x300 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x300 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x304 "INTPRIORITY_193,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h197"
hexmask.long 0x304 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x304 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x308 "INTPRIORITY_194,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h198"
hexmask.long 0x308 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x308 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30C "INTPRIORITY_195,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h199"
hexmask.long 0x30C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x310 "INTPRIORITY_196,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h200"
hexmask.long 0x310 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x310 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x314 "INTPRIORITY_197,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h201"
hexmask.long 0x314 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x314 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x318 "INTPRIORITY_198,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h202"
hexmask.long 0x318 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x318 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x31C "INTPRIORITY_199,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h203"
hexmask.long 0x31C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x31C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x320 "INTPRIORITY_200,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h204"
hexmask.long 0x320 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x320 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x324 "INTPRIORITY_201,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h205"
hexmask.long 0x324 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x324 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x328 "INTPRIORITY_202,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h206"
hexmask.long 0x328 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x328 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x32C "INTPRIORITY_203,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h207"
hexmask.long 0x32C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x32C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x330 "INTPRIORITY_204,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h208"
hexmask.long 0x330 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x330 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x334 "INTPRIORITY_205,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h209"
hexmask.long 0x334 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x334 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x338 "INTPRIORITY_206,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h210"
hexmask.long 0x338 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x338 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x33C "INTPRIORITY_207,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h211"
hexmask.long 0x33C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x33C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x340 "INTPRIORITY_208,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h212"
hexmask.long 0x340 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x340 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x344 "INTPRIORITY_209,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h213"
hexmask.long 0x344 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x344 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x348 "INTPRIORITY_210,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h214"
hexmask.long 0x348 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x348 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34C "INTPRIORITY_211,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h215"
hexmask.long 0x34C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x350 "INTPRIORITY_212,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h216"
hexmask.long 0x350 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x350 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x354 "INTPRIORITY_213,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h217"
hexmask.long 0x354 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x354 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x358 "INTPRIORITY_214,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h218"
hexmask.long 0x358 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x358 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x35C "INTPRIORITY_215,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h219"
hexmask.long 0x35C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x35C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x360 "INTPRIORITY_216,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h220"
hexmask.long 0x360 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x360 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x364 "INTPRIORITY_217,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h221"
hexmask.long 0x364 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x364 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x368 "INTPRIORITY_218,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h222"
hexmask.long 0x368 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x368 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x36C "INTPRIORITY_219,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h223"
hexmask.long 0x36C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x36C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x370 "INTPRIORITY_220,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h224"
hexmask.long 0x370 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x370 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x374 "INTPRIORITY_221,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h225"
hexmask.long 0x374 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x374 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x378 "INTPRIORITY_222,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h226"
hexmask.long 0x378 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x378 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x37C "INTPRIORITY_223,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h227"
hexmask.long 0x37C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x37C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x380 "INTPRIORITY_224,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h228"
hexmask.long 0x380 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x380 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x384 "INTPRIORITY_225,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h229"
hexmask.long 0x384 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x384 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x388 "INTPRIORITY_226,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h230"
hexmask.long 0x388 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x388 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38C "INTPRIORITY_227,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h231"
hexmask.long 0x38C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x390 "INTPRIORITY_228,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h232"
hexmask.long 0x390 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x390 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x394 "INTPRIORITY_229,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h233"
hexmask.long 0x394 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x394 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x398 "INTPRIORITY_230,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h234"
hexmask.long 0x398 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x398 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x39C "INTPRIORITY_231,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h235"
hexmask.long 0x39C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x39C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A0 "INTPRIORITY_232,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h236"
hexmask.long 0x3A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A4 "INTPRIORITY_233,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h237"
hexmask.long 0x3A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A8 "INTPRIORITY_234,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h238"
hexmask.long 0x3A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3AC "INTPRIORITY_235,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h239"
hexmask.long 0x3AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B0 "INTPRIORITY_236,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h240"
hexmask.long 0x3B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B4 "INTPRIORITY_237,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h241"
hexmask.long 0x3B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B8 "INTPRIORITY_238,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h242"
hexmask.long 0x3B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3BC "INTPRIORITY_239,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h243"
hexmask.long 0x3BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C0 "INTPRIORITY_240,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h244"
hexmask.long 0x3C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C4 "INTPRIORITY_241,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h245"
hexmask.long 0x3C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C8 "INTPRIORITY_242,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h246"
hexmask.long 0x3C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3CC "INTPRIORITY_243,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h247"
hexmask.long 0x3CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D0 "INTPRIORITY_244,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h248"
hexmask.long 0x3D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D4 "INTPRIORITY_245,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h249"
hexmask.long 0x3D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D8 "INTPRIORITY_246,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h250"
hexmask.long 0x3D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3DC "INTPRIORITY_247,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h251"
hexmask.long 0x3DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E0 "INTPRIORITY_248,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h252"
hexmask.long 0x3E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E4 "INTPRIORITY_249,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h253"
hexmask.long 0x3E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E8 "INTPRIORITY_250,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h254"
hexmask.long 0x3E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3EC "INTPRIORITY_251,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h255"
hexmask.long 0x3EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F0 "INTPRIORITY_252,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h256"
hexmask.long 0x3F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F4 "INTPRIORITY_253,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h257"
hexmask.long 0x3F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F8 "INTPRIORITY_254,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h258"
hexmask.long 0x3F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3FC "INTPRIORITY_255,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h259"
hexmask.long 0x3FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x3FF
line.long 0x00 "INTVECTOR,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h4"
hexmask.long 0x00 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x00 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x04 "INTVECTOR_1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
hexmask.long 0x04 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x04 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x08 "INTVECTOR_2,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h6"
hexmask.long 0x08 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x08 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x0C "INTVECTOR_3,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h7"
hexmask.long 0x0C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x0C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10 "INTVECTOR_4,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h8"
hexmask.long 0x10 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14 "INTVECTOR_5,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h9"
hexmask.long 0x14 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18 "INTVECTOR_6,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h10"
hexmask.long 0x18 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C "INTVECTOR_7,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h11"
hexmask.long 0x1C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20 "INTVECTOR_8,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h12"
hexmask.long 0x20 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24 "INTVECTOR_9,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h13"
hexmask.long 0x24 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28 "INTVECTOR_10,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h14"
hexmask.long 0x28 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C "INTVECTOR_11,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h15"
hexmask.long 0x2C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30 "INTVECTOR_12,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h16"
hexmask.long 0x30 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34 "INTVECTOR_13,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h17"
hexmask.long 0x34 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38 "INTVECTOR_14,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h18"
hexmask.long 0x38 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C "INTVECTOR_15,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h19"
hexmask.long 0x3C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x40 "INTVECTOR_16,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h20"
hexmask.long 0x40 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x40 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x44 "INTVECTOR_17,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h21"
hexmask.long 0x44 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x44 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x48 "INTVECTOR_18,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h22"
hexmask.long 0x48 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x48 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x4C "INTVECTOR_19,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h23"
hexmask.long 0x4C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x4C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x50 "INTVECTOR_20,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h24"
hexmask.long 0x50 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x50 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x54 "INTVECTOR_21,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h25"
hexmask.long 0x54 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x54 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x58 "INTVECTOR_22,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h26"
hexmask.long 0x58 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x58 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x5C "INTVECTOR_23,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h27"
hexmask.long 0x5C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x5C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x60 "INTVECTOR_24,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h28"
hexmask.long 0x60 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x60 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x64 "INTVECTOR_25,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h29"
hexmask.long 0x64 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x64 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x68 "INTVECTOR_26,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h30"
hexmask.long 0x68 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x68 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x6C "INTVECTOR_27,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h31"
hexmask.long 0x6C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x6C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x70 "INTVECTOR_28,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h32"
hexmask.long 0x70 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x70 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x74 "INTVECTOR_29,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h33"
hexmask.long 0x74 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x74 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x78 "INTVECTOR_30,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h34"
hexmask.long 0x78 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x78 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x7C "INTVECTOR_31,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h35"
hexmask.long 0x7C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x7C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x80 "INTVECTOR_32,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h36"
hexmask.long 0x80 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x80 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x84 "INTVECTOR_33,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h37"
hexmask.long 0x84 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x84 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x88 "INTVECTOR_34,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h38"
hexmask.long 0x88 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x88 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x8C "INTVECTOR_35,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h39"
hexmask.long 0x8C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x8C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x90 "INTVECTOR_36,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h40"
hexmask.long 0x90 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x90 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x94 "INTVECTOR_37,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h41"
hexmask.long 0x94 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x94 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x98 "INTVECTOR_38,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h42"
hexmask.long 0x98 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x98 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x9C "INTVECTOR_39,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h43"
hexmask.long 0x9C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x9C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA0 "INTVECTOR_40,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h44"
hexmask.long 0xA0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA4 "INTVECTOR_41,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h45"
hexmask.long 0xA4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA8 "INTVECTOR_42,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h46"
hexmask.long 0xA8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xAC "INTVECTOR_43,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h47"
hexmask.long 0xAC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xAC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB0 "INTVECTOR_44,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h48"
hexmask.long 0xB0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB4 "INTVECTOR_45,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h49"
hexmask.long 0xB4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB8 "INTVECTOR_46,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h50"
hexmask.long 0xB8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xBC "INTVECTOR_47,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h51"
hexmask.long 0xBC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xBC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC0 "INTVECTOR_48,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h52"
hexmask.long 0xC0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC4 "INTVECTOR_49,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h53"
hexmask.long 0xC4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC8 "INTVECTOR_50,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h54"
hexmask.long 0xC8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xCC "INTVECTOR_51,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h55"
hexmask.long 0xCC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xCC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD0 "INTVECTOR_52,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h56"
hexmask.long 0xD0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD4 "INTVECTOR_53,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h57"
hexmask.long 0xD4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD8 "INTVECTOR_54,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h58"
hexmask.long 0xD8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xDC "INTVECTOR_55,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h59"
hexmask.long 0xDC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xDC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE0 "INTVECTOR_56,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h60"
hexmask.long 0xE0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE4 "INTVECTOR_57,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h61"
hexmask.long 0xE4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE8 "INTVECTOR_58,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h62"
hexmask.long 0xE8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xEC "INTVECTOR_59,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h63"
hexmask.long 0xEC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xEC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF0 "INTVECTOR_60,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h64"
hexmask.long 0xF0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF4 "INTVECTOR_61,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h65"
hexmask.long 0xF4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF8 "INTVECTOR_62,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h66"
hexmask.long 0xF8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xFC "INTVECTOR_63,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h67"
hexmask.long 0xFC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xFC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x100 "INTVECTOR_64,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h68"
hexmask.long 0x100 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x100 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x104 "INTVECTOR_65,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h69"
hexmask.long 0x104 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x104 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x108 "INTVECTOR_66,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h70"
hexmask.long 0x108 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x108 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10C "INTVECTOR_67,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h71"
hexmask.long 0x10C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x110 "INTVECTOR_68,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h72"
hexmask.long 0x110 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x110 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x114 "INTVECTOR_69,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h73"
hexmask.long 0x114 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x114 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x118 "INTVECTOR_70,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h74"
hexmask.long 0x118 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x118 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x11C "INTVECTOR_71,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h75"
hexmask.long 0x11C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x11C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x120 "INTVECTOR_72,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h76"
hexmask.long 0x120 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x120 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x124 "INTVECTOR_73,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h77"
hexmask.long 0x124 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x124 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x128 "INTVECTOR_74,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h78"
hexmask.long 0x128 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x128 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x12C "INTVECTOR_75,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h79"
hexmask.long 0x12C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x12C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x130 "INTVECTOR_76,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h80"
hexmask.long 0x130 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x130 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x134 "INTVECTOR_77,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h81"
hexmask.long 0x134 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x134 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x138 "INTVECTOR_78,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h82"
hexmask.long 0x138 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x138 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x13C "INTVECTOR_79,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h83"
hexmask.long 0x13C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x13C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x140 "INTVECTOR_80,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h84"
hexmask.long 0x140 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x140 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x144 "INTVECTOR_81,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h85"
hexmask.long 0x144 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x144 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x148 "INTVECTOR_82,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h86"
hexmask.long 0x148 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x148 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14C "INTVECTOR_83,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h87"
hexmask.long 0x14C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x150 "INTVECTOR_84,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h88"
hexmask.long 0x150 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x150 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x154 "INTVECTOR_85,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h89"
hexmask.long 0x154 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x154 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x158 "INTVECTOR_86,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h90"
hexmask.long 0x158 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x158 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x15C "INTVECTOR_87,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h91"
hexmask.long 0x15C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x15C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x160 "INTVECTOR_88,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h92"
hexmask.long 0x160 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x160 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x164 "INTVECTOR_89,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h93"
hexmask.long 0x164 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x164 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x168 "INTVECTOR_90,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h94"
hexmask.long 0x168 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x168 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x16C "INTVECTOR_91,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h95"
hexmask.long 0x16C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x16C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x170 "INTVECTOR_92,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h96"
hexmask.long 0x170 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x170 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x174 "INTVECTOR_93,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h97"
hexmask.long 0x174 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x174 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x178 "INTVECTOR_94,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h98"
hexmask.long 0x178 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x178 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x17C "INTVECTOR_95,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h99"
hexmask.long 0x17C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x17C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x180 "INTVECTOR_96,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h100"
hexmask.long 0x180 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x180 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x184 "INTVECTOR_97,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h101"
hexmask.long 0x184 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x184 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x188 "INTVECTOR_98,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h102"
hexmask.long 0x188 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x188 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18C "INTVECTOR_99,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h103"
hexmask.long 0x18C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x190 "INTVECTOR_100,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h104"
hexmask.long 0x190 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x190 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x194 "INTVECTOR_101,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h105"
hexmask.long 0x194 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x194 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x198 "INTVECTOR_102,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h106"
hexmask.long 0x198 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x198 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x19C "INTVECTOR_103,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h107"
hexmask.long 0x19C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x19C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A0 "INTVECTOR_104,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h108"
hexmask.long 0x1A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A4 "INTVECTOR_105,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h109"
hexmask.long 0x1A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A8 "INTVECTOR_106,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h110"
hexmask.long 0x1A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1AC "INTVECTOR_107,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h111"
hexmask.long 0x1AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B0 "INTVECTOR_108,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h112"
hexmask.long 0x1B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B4 "INTVECTOR_109,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h113"
hexmask.long 0x1B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B8 "INTVECTOR_110,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h114"
hexmask.long 0x1B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1BC "INTVECTOR_111,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h115"
hexmask.long 0x1BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C0 "INTVECTOR_112,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h116"
hexmask.long 0x1C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C4 "INTVECTOR_113,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h117"
hexmask.long 0x1C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C8 "INTVECTOR_114,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h118"
hexmask.long 0x1C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1CC "INTVECTOR_115,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h119"
hexmask.long 0x1CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D0 "INTVECTOR_116,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h120"
hexmask.long 0x1D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D4 "INTVECTOR_117,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h121"
hexmask.long 0x1D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D8 "INTVECTOR_118,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h122"
hexmask.long 0x1D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1DC "INTVECTOR_119,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h123"
hexmask.long 0x1DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E0 "INTVECTOR_120,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h124"
hexmask.long 0x1E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E4 "INTVECTOR_121,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h125"
hexmask.long 0x1E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E8 "INTVECTOR_122,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h126"
hexmask.long 0x1E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1EC "INTVECTOR_123,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h127"
hexmask.long 0x1EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F0 "INTVECTOR_124,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h128"
hexmask.long 0x1F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F4 "INTVECTOR_125,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h129"
hexmask.long 0x1F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F8 "INTVECTOR_126,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h130"
hexmask.long 0x1F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1FC "INTVECTOR_127,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h131"
hexmask.long 0x1FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x200 "INTVECTOR_128,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h132"
hexmask.long 0x200 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x200 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x204 "INTVECTOR_129,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h133"
hexmask.long 0x204 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x204 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x208 "INTVECTOR_130,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h134"
hexmask.long 0x208 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x208 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20C "INTVECTOR_131,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h135"
hexmask.long 0x20C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x210 "INTVECTOR_132,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h136"
hexmask.long 0x210 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x210 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x214 "INTVECTOR_133,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h137"
hexmask.long 0x214 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x214 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x218 "INTVECTOR_134,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h138"
hexmask.long 0x218 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x218 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x21C "INTVECTOR_135,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h139"
hexmask.long 0x21C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x21C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x220 "INTVECTOR_136,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h140"
hexmask.long 0x220 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x220 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x224 "INTVECTOR_137,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h141"
hexmask.long 0x224 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x224 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x228 "INTVECTOR_138,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h142"
hexmask.long 0x228 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x228 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x22C "INTVECTOR_139,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h143"
hexmask.long 0x22C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x22C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x230 "INTVECTOR_140,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h144"
hexmask.long 0x230 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x230 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x234 "INTVECTOR_141,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h145"
hexmask.long 0x234 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x234 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x238 "INTVECTOR_142,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h146"
hexmask.long 0x238 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x238 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x23C "INTVECTOR_143,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h147"
hexmask.long 0x23C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x23C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x240 "INTVECTOR_144,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h148"
hexmask.long 0x240 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x240 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x244 "INTVECTOR_145,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h149"
hexmask.long 0x244 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x244 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x248 "INTVECTOR_146,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h150"
hexmask.long 0x248 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x248 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24C "INTVECTOR_147,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h151"
hexmask.long 0x24C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x250 "INTVECTOR_148,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h152"
hexmask.long 0x250 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x250 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x254 "INTVECTOR_149,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h153"
hexmask.long 0x254 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x254 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x258 "INTVECTOR_150,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h154"
hexmask.long 0x258 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x258 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x25C "INTVECTOR_151,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h155"
hexmask.long 0x25C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x25C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x260 "INTVECTOR_152,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h156"
hexmask.long 0x260 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x260 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x264 "INTVECTOR_153,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h157"
hexmask.long 0x264 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x264 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x268 "INTVECTOR_154,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h158"
hexmask.long 0x268 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x268 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x26C "INTVECTOR_155,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h159"
hexmask.long 0x26C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x26C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x270 "INTVECTOR_156,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h160"
hexmask.long 0x270 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x270 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x274 "INTVECTOR_157,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h161"
hexmask.long 0x274 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x274 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x278 "INTVECTOR_158,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h162"
hexmask.long 0x278 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x278 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x27C "INTVECTOR_159,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h163"
hexmask.long 0x27C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x27C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x280 "INTVECTOR_160,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h164"
hexmask.long 0x280 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x280 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x284 "INTVECTOR_161,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h165"
hexmask.long 0x284 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x284 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x288 "INTVECTOR_162,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h166"
hexmask.long 0x288 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x288 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28C "INTVECTOR_163,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h167"
hexmask.long 0x28C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x290 "INTVECTOR_164,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h168"
hexmask.long 0x290 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x290 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x294 "INTVECTOR_165,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h169"
hexmask.long 0x294 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x294 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x298 "INTVECTOR_166,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h170"
hexmask.long 0x298 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x298 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x29C "INTVECTOR_167,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h171"
hexmask.long 0x29C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x29C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A0 "INTVECTOR_168,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h172"
hexmask.long 0x2A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A4 "INTVECTOR_169,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h173"
hexmask.long 0x2A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A8 "INTVECTOR_170,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h174"
hexmask.long 0x2A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2AC "INTVECTOR_171,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h175"
hexmask.long 0x2AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B0 "INTVECTOR_172,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h176"
hexmask.long 0x2B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B4 "INTVECTOR_173,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h177"
hexmask.long 0x2B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B8 "INTVECTOR_174,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h178"
hexmask.long 0x2B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2BC "INTVECTOR_175,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h179"
hexmask.long 0x2BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C0 "INTVECTOR_176,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h180"
hexmask.long 0x2C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C4 "INTVECTOR_177,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h181"
hexmask.long 0x2C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C8 "INTVECTOR_178,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h182"
hexmask.long 0x2C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2CC "INTVECTOR_179,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h183"
hexmask.long 0x2CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D0 "INTVECTOR_180,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h184"
hexmask.long 0x2D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D4 "INTVECTOR_181,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h185"
hexmask.long 0x2D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D8 "INTVECTOR_182,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h186"
hexmask.long 0x2D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2DC "INTVECTOR_183,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h187"
hexmask.long 0x2DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E0 "INTVECTOR_184,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h188"
hexmask.long 0x2E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E4 "INTVECTOR_185,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h189"
hexmask.long 0x2E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E8 "INTVECTOR_186,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h190"
hexmask.long 0x2E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2EC "INTVECTOR_187,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h191"
hexmask.long 0x2EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F0 "INTVECTOR_188,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h192"
hexmask.long 0x2F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F4 "INTVECTOR_189,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h193"
hexmask.long 0x2F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F8 "INTVECTOR_190,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h194"
hexmask.long 0x2F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2FC "INTVECTOR_191,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h195"
hexmask.long 0x2FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x300 "INTVECTOR_192,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h196"
hexmask.long 0x300 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x300 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x304 "INTVECTOR_193,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h197"
hexmask.long 0x304 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x304 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x308 "INTVECTOR_194,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h198"
hexmask.long 0x308 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x308 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30C "INTVECTOR_195,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h199"
hexmask.long 0x30C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x310 "INTVECTOR_196,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h200"
hexmask.long 0x310 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x310 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x314 "INTVECTOR_197,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h201"
hexmask.long 0x314 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x314 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x318 "INTVECTOR_198,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h202"
hexmask.long 0x318 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x318 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x31C "INTVECTOR_199,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h203"
hexmask.long 0x31C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x31C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x320 "INTVECTOR_200,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h204"
hexmask.long 0x320 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x320 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x324 "INTVECTOR_201,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h205"
hexmask.long 0x324 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x324 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x328 "INTVECTOR_202,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h206"
hexmask.long 0x328 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x328 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x32C "INTVECTOR_203,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h207"
hexmask.long 0x32C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x32C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x330 "INTVECTOR_204,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h208"
hexmask.long 0x330 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x330 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x334 "INTVECTOR_205,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h209"
hexmask.long 0x334 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x334 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x338 "INTVECTOR_206,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h210"
hexmask.long 0x338 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x338 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x33C "INTVECTOR_207,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h211"
hexmask.long 0x33C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x33C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x340 "INTVECTOR_208,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h212"
hexmask.long 0x340 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x340 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x344 "INTVECTOR_209,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h213"
hexmask.long 0x344 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x344 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x348 "INTVECTOR_210,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h214"
hexmask.long 0x348 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x348 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34C "INTVECTOR_211,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h215"
hexmask.long 0x34C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x350 "INTVECTOR_212,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h216"
hexmask.long 0x350 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x350 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x354 "INTVECTOR_213,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h217"
hexmask.long 0x354 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x354 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x358 "INTVECTOR_214,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h218"
hexmask.long 0x358 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x358 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x35C "INTVECTOR_215,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h219"
hexmask.long 0x35C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x35C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x360 "INTVECTOR_216,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h220"
hexmask.long 0x360 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x360 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x364 "INTVECTOR_217,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h221"
hexmask.long 0x364 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x364 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x368 "INTVECTOR_218,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h222"
hexmask.long 0x368 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x368 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x36C "INTVECTOR_219,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h223"
hexmask.long 0x36C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x36C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x370 "INTVECTOR_220,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h224"
hexmask.long 0x370 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x370 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x374 "INTVECTOR_221,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h225"
hexmask.long 0x374 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x374 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x378 "INTVECTOR_222,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h226"
hexmask.long 0x378 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x378 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x37C "INTVECTOR_223,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h227"
hexmask.long 0x37C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x37C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x380 "INTVECTOR_224,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h228"
hexmask.long 0x380 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x380 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x384 "INTVECTOR_225,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h229"
hexmask.long 0x384 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x384 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x388 "INTVECTOR_226,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h230"
hexmask.long 0x388 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x388 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38C "INTVECTOR_227,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h231"
hexmask.long 0x38C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x390 "INTVECTOR_228,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h232"
hexmask.long 0x390 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x390 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x394 "INTVECTOR_229,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h233"
hexmask.long 0x394 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x394 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x398 "INTVECTOR_230,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h234"
hexmask.long 0x398 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x398 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x39C "INTVECTOR_231,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h235"
hexmask.long 0x39C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x39C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A0 "INTVECTOR_232,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h236"
hexmask.long 0x3A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A4 "INTVECTOR_233,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h237"
hexmask.long 0x3A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A8 "INTVECTOR_234,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h238"
hexmask.long 0x3A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3AC "INTVECTOR_235,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h239"
hexmask.long 0x3AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B0 "INTVECTOR_236,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h240"
hexmask.long 0x3B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B4 "INTVECTOR_237,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h241"
hexmask.long 0x3B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B8 "INTVECTOR_238,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h242"
hexmask.long 0x3B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3BC "INTVECTOR_239,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h243"
hexmask.long 0x3BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C0 "INTVECTOR_240,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h244"
hexmask.long 0x3C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C4 "INTVECTOR_241,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h245"
hexmask.long 0x3C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C8 "INTVECTOR_242,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h246"
hexmask.long 0x3C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3CC "INTVECTOR_243,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h247"
hexmask.long 0x3CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D0 "INTVECTOR_244,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h248"
hexmask.long 0x3D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D4 "INTVECTOR_245,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h249"
hexmask.long 0x3D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D8 "INTVECTOR_246,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h250"
hexmask.long 0x3D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3DC "INTVECTOR_247,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h251"
hexmask.long 0x3DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E0 "INTVECTOR_248,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h252"
hexmask.long 0x3E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E4 "INTVECTOR_249,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h253"
hexmask.long 0x3E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E8 "INTVECTOR_250,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h254"
hexmask.long 0x3E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3EC "INTVECTOR_251,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h255"
hexmask.long 0x3EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F0 "INTVECTOR_252,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h256"
hexmask.long 0x3F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F4 "INTVECTOR_253,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h257"
hexmask.long 0x3F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F8 "INTVECTOR_254,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h258"
hexmask.long 0x3F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3FC "INTVECTOR_255,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h259"
hexmask.long 0x3FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3FC 0.--1. "RES20,Reserved" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_VIM_R5B (MSS VIM CR5 CORE B)"
base ad:0x520A0000
rgroup.long 0x00++0x27
line.long 0x00 "PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INFO,The Info Register gives the configuration Inforrmation of this VIM"
hexmask.long.tbyte 0x04 11.--31. 1. "RES1,RESERVE FIELD"
hexmask.long.word 0x04 0.--10. 1. "INTERRUPTS,Total number of Interrupts"
line.long 0x08 "PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ"
bitfld.long 0x08 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x08 20.--30. 1. "RES2,RESERVE FIELD"
bitfld.long 0x08 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 10.--15. "RES3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 0.--9. 1. "NUM,Number of the highest priority pending IRQ"
line.long 0x0C "PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ"
bitfld.long 0x0C 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x0C 20.--30. 1. "RES4,RESERVE FIELD"
bitfld.long 0x0C 16.--19. "PRI,Priority of the highest priority pending FIQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 10.--15. "RES5,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x0C 0.--9. 1. "NUM,Number of the highest priority pending FIQ"
line.long 0x10 "IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts"
line.long 0x14 "FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts"
line.long 0x18 "IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ"
hexmask.long 0x18 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x18 0.--1. "RES21,RESERVE FIELD" "0,1,2,3"
line.long 0x1C "FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ"
hexmask.long 0x1C 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x1C 0.--1. "RES22,RESERVE FIELD" "0,1,2,3"
line.long 0x20 "ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ"
bitfld.long 0x20 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x20 20.--30. 1. "RES6,RESERVE FIELD"
bitfld.long 0x20 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 10.--15. "RES7,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "NUM,Number of the currently active IRQ"
line.long 0x24 "ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ"
bitfld.long 0x24 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x24 20.--30. 1. "RES8,RESERVE FIELD"
bitfld.long 0x24 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 10.--15. "RES9,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x24 0.--9. 1. "NUM,Number of the currently active FIQ"
group.long 0x30++0x03
line.long 0x00 "DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ"
hexmask.long 0x00 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x00 0.--1. "RES23,RESERVE FIELD" "0,1,2,3"
group.long 0x400++0xFF
line.long 0x00 "RAW,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x04 "STS,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x08 "INTR_EN_SET,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x0C "INTER_EN_CLR,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x10 "IRQSTS,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x14 "FIQSTS,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x18 "INTMAP,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x1C "INTTYPE,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x20 "RAW_1,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x24 "STS_1,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x28 "INTR_EN_SET_1,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x2C "INTER_EN_CLR_1,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x30 "IRQSTS_1,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x34 "FIQSTS_1,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x38 "INTMAP_1,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x3C "INTTYPE_1,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x40 "RAW_2,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x44 "STS_2,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x48 "INTR_EN_SET_2,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x4C "INTER_EN_CLR_2,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x50 "IRQSTS_2,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x54 "FIQSTS_2,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x58 "INTMAP_2,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x5C "INTTYPE_2,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x60 "RAW_3,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x64 "STS_3,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x68 "INTR_EN_SET_3,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x6C "INTER_EN_CLR_3,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x70 "IRQSTS_3,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x74 "FIQSTS_3,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x78 "INTMAP_3,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x7C "INTTYPE_3,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x80 "RAW_4,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x84 "STS_4,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x88 "INTR_EN_SET_4,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x8C "INTER_EN_CLR_4,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x90 "IRQSTS_4,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x94 "FIQSTS_4,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x98 "INTMAP_4,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x9C "INTTYPE_4,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xA0 "RAW_5,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xA4 "STS_5,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xA8 "INTR_EN_SET_5,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xAC "INTER_EN_CLR_5,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xB0 "IRQSTS_5,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xB4 "FIQSTS_5,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xB8 "INTMAP_5,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xBC "INTTYPE_5,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xC0 "RAW_6,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xC4 "STS_6,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xC8 "INTR_EN_SET_6,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xCC "INTER_EN_CLR_6,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xD0 "IRQSTS_6,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xD4 "FIQSTS_6,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xD8 "INTMAP_6,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xDC "INTTYPE_6,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xE0 "RAW_7,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xE4 "STS_7,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xE8 "INTR_EN_SET_7,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xEC "INTER_EN_CLR_7,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xF0 "IRQSTS_7,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xF4 "FIQSTS_7,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xF8 "INTMAP_7,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xFC "INTTYPE_7,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
group.long 0x1000++0x3FF
line.long 0x00 "INTPRIORITY,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h4"
hexmask.long 0x00 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x00 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTPRIORITY_1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
hexmask.long 0x04 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x04 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "INTPRIORITY_2,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h6"
hexmask.long 0x08 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x08 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "INTPRIORITY_3,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h7"
hexmask.long 0x0C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x0C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "INTPRIORITY_4,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h8"
hexmask.long 0x10 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "INTPRIORITY_5,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h9"
hexmask.long 0x14 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "INTPRIORITY_6,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h10"
hexmask.long 0x18 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "INTPRIORITY_7,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h11"
hexmask.long 0x1C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "INTPRIORITY_8,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h12"
hexmask.long 0x20 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "INTPRIORITY_9,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h13"
hexmask.long 0x24 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "INTPRIORITY_10,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h14"
hexmask.long 0x28 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "INTPRIORITY_11,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h15"
hexmask.long 0x2C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "INTPRIORITY_12,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h16"
hexmask.long 0x30 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "INTPRIORITY_13,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h17"
hexmask.long 0x34 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "INTPRIORITY_14,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h18"
hexmask.long 0x38 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "INTPRIORITY_15,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h19"
hexmask.long 0x3C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "INTPRIORITY_16,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h20"
hexmask.long 0x40 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x40 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "INTPRIORITY_17,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h21"
hexmask.long 0x44 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x44 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "INTPRIORITY_18,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h22"
hexmask.long 0x48 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x48 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "INTPRIORITY_19,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h23"
hexmask.long 0x4C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x4C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "INTPRIORITY_20,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h24"
hexmask.long 0x50 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x50 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "INTPRIORITY_21,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h25"
hexmask.long 0x54 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x54 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "INTPRIORITY_22,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h26"
hexmask.long 0x58 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x58 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "INTPRIORITY_23,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h27"
hexmask.long 0x5C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x5C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x60 "INTPRIORITY_24,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h28"
hexmask.long 0x60 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x60 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "INTPRIORITY_25,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h29"
hexmask.long 0x64 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x64 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "INTPRIORITY_26,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h30"
hexmask.long 0x68 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x68 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "INTPRIORITY_27,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h31"
hexmask.long 0x6C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x6C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "INTPRIORITY_28,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h32"
hexmask.long 0x70 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x70 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x74 "INTPRIORITY_29,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h33"
hexmask.long 0x74 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x74 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x78 "INTPRIORITY_30,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h34"
hexmask.long 0x78 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x78 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x7C "INTPRIORITY_31,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h35"
hexmask.long 0x7C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x7C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x80 "INTPRIORITY_32,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h36"
hexmask.long 0x80 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x80 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "INTPRIORITY_33,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h37"
hexmask.long 0x84 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x84 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "INTPRIORITY_34,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h38"
hexmask.long 0x88 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x88 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "INTPRIORITY_35,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h39"
hexmask.long 0x8C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x8C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "INTPRIORITY_36,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h40"
hexmask.long 0x90 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x90 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x94 "INTPRIORITY_37,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h41"
hexmask.long 0x94 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x94 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x98 "INTPRIORITY_38,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h42"
hexmask.long 0x98 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x98 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "INTPRIORITY_39,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h43"
hexmask.long 0x9C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x9C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA0 "INTPRIORITY_40,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h44"
hexmask.long 0xA0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "INTPRIORITY_41,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h45"
hexmask.long 0xA4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA8 "INTPRIORITY_42,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h46"
hexmask.long 0xA8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xAC "INTPRIORITY_43,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h47"
hexmask.long 0xAC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xAC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB0 "INTPRIORITY_44,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h48"
hexmask.long 0xB0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB4 "INTPRIORITY_45,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h49"
hexmask.long 0xB4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "INTPRIORITY_46,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h50"
hexmask.long 0xB8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xBC "INTPRIORITY_47,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h51"
hexmask.long 0xBC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xBC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC0 "INTPRIORITY_48,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h52"
hexmask.long 0xC0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "INTPRIORITY_49,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h53"
hexmask.long 0xC4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "INTPRIORITY_50,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h54"
hexmask.long 0xC8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "INTPRIORITY_51,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h55"
hexmask.long 0xCC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xCC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD0 "INTPRIORITY_52,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h56"
hexmask.long 0xD0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "INTPRIORITY_53,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h57"
hexmask.long 0xD4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD8 "INTPRIORITY_54,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h58"
hexmask.long 0xD8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "INTPRIORITY_55,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h59"
hexmask.long 0xDC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xDC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE0 "INTPRIORITY_56,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h60"
hexmask.long 0xE0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "INTPRIORITY_57,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h61"
hexmask.long 0xE4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE8 "INTPRIORITY_58,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h62"
hexmask.long 0xE8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "INTPRIORITY_59,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h63"
hexmask.long 0xEC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xEC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF0 "INTPRIORITY_60,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h64"
hexmask.long 0xF0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "INTPRIORITY_61,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h65"
hexmask.long 0xF4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF8 "INTPRIORITY_62,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h66"
hexmask.long 0xF8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "INTPRIORITY_63,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h67"
hexmask.long 0xFC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xFC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x100 "INTPRIORITY_64,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h68"
hexmask.long 0x100 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x100 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "INTPRIORITY_65,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h69"
hexmask.long 0x104 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x104 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x108 "INTPRIORITY_66,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h70"
hexmask.long 0x108 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x108 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10C "INTPRIORITY_67,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h71"
hexmask.long 0x10C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x110 "INTPRIORITY_68,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h72"
hexmask.long 0x110 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x110 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x114 "INTPRIORITY_69,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h73"
hexmask.long 0x114 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x114 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x118 "INTPRIORITY_70,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h74"
hexmask.long 0x118 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x118 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x11C "INTPRIORITY_71,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h75"
hexmask.long 0x11C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x11C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x120 "INTPRIORITY_72,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h76"
hexmask.long 0x120 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x120 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "INTPRIORITY_73,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h77"
hexmask.long 0x124 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x124 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x128 "INTPRIORITY_74,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h78"
hexmask.long 0x128 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x128 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x12C "INTPRIORITY_75,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h79"
hexmask.long 0x12C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x12C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x130 "INTPRIORITY_76,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h80"
hexmask.long 0x130 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x130 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x134 "INTPRIORITY_77,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h81"
hexmask.long 0x134 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x134 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x138 "INTPRIORITY_78,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h82"
hexmask.long 0x138 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x138 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x13C "INTPRIORITY_79,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h83"
hexmask.long 0x13C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x13C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x140 "INTPRIORITY_80,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h84"
hexmask.long 0x140 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x140 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "INTPRIORITY_81,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h85"
hexmask.long 0x144 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x144 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x148 "INTPRIORITY_82,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h86"
hexmask.long 0x148 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x148 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14C "INTPRIORITY_83,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h87"
hexmask.long 0x14C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x150 "INTPRIORITY_84,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h88"
hexmask.long 0x150 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x150 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x154 "INTPRIORITY_85,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h89"
hexmask.long 0x154 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x154 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x158 "INTPRIORITY_86,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h90"
hexmask.long 0x158 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x158 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x15C "INTPRIORITY_87,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h91"
hexmask.long 0x15C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x15C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x160 "INTPRIORITY_88,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h92"
hexmask.long 0x160 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x160 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "INTPRIORITY_89,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h93"
hexmask.long 0x164 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x164 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x168 "INTPRIORITY_90,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h94"
hexmask.long 0x168 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x168 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "INTPRIORITY_91,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h95"
hexmask.long 0x16C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x16C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x170 "INTPRIORITY_92,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h96"
hexmask.long 0x170 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x170 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "INTPRIORITY_93,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h97"
hexmask.long 0x174 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x174 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x178 "INTPRIORITY_94,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h98"
hexmask.long 0x178 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x178 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "INTPRIORITY_95,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h99"
hexmask.long 0x17C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x17C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x180 "INTPRIORITY_96,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h100"
hexmask.long 0x180 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x180 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "INTPRIORITY_97,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h101"
hexmask.long 0x184 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x184 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x188 "INTPRIORITY_98,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h102"
hexmask.long 0x188 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x188 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "INTPRIORITY_99,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h103"
hexmask.long 0x18C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "INTPRIORITY_100,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h104"
hexmask.long 0x190 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x190 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "INTPRIORITY_101,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h105"
hexmask.long 0x194 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x194 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x198 "INTPRIORITY_102,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h106"
hexmask.long 0x198 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x198 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "INTPRIORITY_103,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h107"
hexmask.long 0x19C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x19C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "INTPRIORITY_104,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h108"
hexmask.long 0x1A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "INTPRIORITY_105,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h109"
hexmask.long 0x1A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "INTPRIORITY_106,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h110"
hexmask.long 0x1A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "INTPRIORITY_107,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h111"
hexmask.long 0x1AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "INTPRIORITY_108,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h112"
hexmask.long 0x1B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "INTPRIORITY_109,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h113"
hexmask.long 0x1B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B8 "INTPRIORITY_110,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h114"
hexmask.long 0x1B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "INTPRIORITY_111,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h115"
hexmask.long 0x1BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C0 "INTPRIORITY_112,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h116"
hexmask.long 0x1C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "INTPRIORITY_113,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h117"
hexmask.long 0x1C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C8 "INTPRIORITY_114,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h118"
hexmask.long 0x1C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "INTPRIORITY_115,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h119"
hexmask.long 0x1CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "INTPRIORITY_116,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h120"
hexmask.long 0x1D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "INTPRIORITY_117,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h121"
hexmask.long 0x1D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D8 "INTPRIORITY_118,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h122"
hexmask.long 0x1D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "INTPRIORITY_119,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h123"
hexmask.long 0x1DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E0 "INTPRIORITY_120,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h124"
hexmask.long 0x1E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "INTPRIORITY_121,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h125"
hexmask.long 0x1E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E8 "INTPRIORITY_122,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h126"
hexmask.long 0x1E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1EC "INTPRIORITY_123,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h127"
hexmask.long 0x1EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F0 "INTPRIORITY_124,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h128"
hexmask.long 0x1F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F4 "INTPRIORITY_125,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h129"
hexmask.long 0x1F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F8 "INTPRIORITY_126,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h130"
hexmask.long 0x1F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1FC "INTPRIORITY_127,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h131"
hexmask.long 0x1FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x200 "INTPRIORITY_128,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h132"
hexmask.long 0x200 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x200 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x204 "INTPRIORITY_129,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h133"
hexmask.long 0x204 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x204 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x208 "INTPRIORITY_130,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h134"
hexmask.long 0x208 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x208 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20C "INTPRIORITY_131,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h135"
hexmask.long 0x20C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "INTPRIORITY_132,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h136"
hexmask.long 0x210 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x210 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x214 "INTPRIORITY_133,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h137"
hexmask.long 0x214 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x214 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x218 "INTPRIORITY_134,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h138"
hexmask.long 0x218 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x218 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x21C "INTPRIORITY_135,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h139"
hexmask.long 0x21C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x21C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x220 "INTPRIORITY_136,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h140"
hexmask.long 0x220 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x220 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x224 "INTPRIORITY_137,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h141"
hexmask.long 0x224 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x224 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x228 "INTPRIORITY_138,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h142"
hexmask.long 0x228 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x228 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x22C "INTPRIORITY_139,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h143"
hexmask.long 0x22C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x22C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x230 "INTPRIORITY_140,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h144"
hexmask.long 0x230 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x230 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x234 "INTPRIORITY_141,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h145"
hexmask.long 0x234 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x234 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x238 "INTPRIORITY_142,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h146"
hexmask.long 0x238 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x238 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x23C "INTPRIORITY_143,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h147"
hexmask.long 0x23C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x23C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x240 "INTPRIORITY_144,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h148"
hexmask.long 0x240 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x240 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x244 "INTPRIORITY_145,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h149"
hexmask.long 0x244 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x244 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x248 "INTPRIORITY_146,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h150"
hexmask.long 0x248 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x248 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24C "INTPRIORITY_147,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h151"
hexmask.long 0x24C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x250 "INTPRIORITY_148,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h152"
hexmask.long 0x250 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x250 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x254 "INTPRIORITY_149,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h153"
hexmask.long 0x254 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x254 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x258 "INTPRIORITY_150,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h154"
hexmask.long 0x258 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x258 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x25C "INTPRIORITY_151,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h155"
hexmask.long 0x25C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x25C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x260 "INTPRIORITY_152,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h156"
hexmask.long 0x260 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x260 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x264 "INTPRIORITY_153,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h157"
hexmask.long 0x264 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x264 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x268 "INTPRIORITY_154,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h158"
hexmask.long 0x268 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x268 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x26C "INTPRIORITY_155,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h159"
hexmask.long 0x26C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x26C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x270 "INTPRIORITY_156,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h160"
hexmask.long 0x270 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x270 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x274 "INTPRIORITY_157,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h161"
hexmask.long 0x274 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x274 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x278 "INTPRIORITY_158,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h162"
hexmask.long 0x278 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x278 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x27C "INTPRIORITY_159,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h163"
hexmask.long 0x27C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x27C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x280 "INTPRIORITY_160,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h164"
hexmask.long 0x280 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x280 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x284 "INTPRIORITY_161,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h165"
hexmask.long 0x284 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x284 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x288 "INTPRIORITY_162,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h166"
hexmask.long 0x288 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x288 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28C "INTPRIORITY_163,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h167"
hexmask.long 0x28C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x290 "INTPRIORITY_164,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h168"
hexmask.long 0x290 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x290 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x294 "INTPRIORITY_165,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h169"
hexmask.long 0x294 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x294 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x298 "INTPRIORITY_166,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h170"
hexmask.long 0x298 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x298 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x29C "INTPRIORITY_167,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h171"
hexmask.long 0x29C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x29C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A0 "INTPRIORITY_168,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h172"
hexmask.long 0x2A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A4 "INTPRIORITY_169,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h173"
hexmask.long 0x2A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A8 "INTPRIORITY_170,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h174"
hexmask.long 0x2A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2AC "INTPRIORITY_171,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h175"
hexmask.long 0x2AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B0 "INTPRIORITY_172,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h176"
hexmask.long 0x2B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B4 "INTPRIORITY_173,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h177"
hexmask.long 0x2B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B8 "INTPRIORITY_174,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h178"
hexmask.long 0x2B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2BC "INTPRIORITY_175,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h179"
hexmask.long 0x2BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C0 "INTPRIORITY_176,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h180"
hexmask.long 0x2C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C4 "INTPRIORITY_177,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h181"
hexmask.long 0x2C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C8 "INTPRIORITY_178,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h182"
hexmask.long 0x2C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2CC "INTPRIORITY_179,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h183"
hexmask.long 0x2CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D0 "INTPRIORITY_180,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h184"
hexmask.long 0x2D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D4 "INTPRIORITY_181,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h185"
hexmask.long 0x2D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D8 "INTPRIORITY_182,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h186"
hexmask.long 0x2D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2DC "INTPRIORITY_183,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h187"
hexmask.long 0x2DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E0 "INTPRIORITY_184,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h188"
hexmask.long 0x2E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E4 "INTPRIORITY_185,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h189"
hexmask.long 0x2E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E8 "INTPRIORITY_186,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h190"
hexmask.long 0x2E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2EC "INTPRIORITY_187,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h191"
hexmask.long 0x2EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F0 "INTPRIORITY_188,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h192"
hexmask.long 0x2F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F4 "INTPRIORITY_189,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h193"
hexmask.long 0x2F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F8 "INTPRIORITY_190,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h194"
hexmask.long 0x2F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2FC "INTPRIORITY_191,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h195"
hexmask.long 0x2FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x300 "INTPRIORITY_192,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h196"
hexmask.long 0x300 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x300 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x304 "INTPRIORITY_193,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h197"
hexmask.long 0x304 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x304 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x308 "INTPRIORITY_194,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h198"
hexmask.long 0x308 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x308 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30C "INTPRIORITY_195,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h199"
hexmask.long 0x30C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x310 "INTPRIORITY_196,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h200"
hexmask.long 0x310 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x310 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x314 "INTPRIORITY_197,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h201"
hexmask.long 0x314 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x314 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x318 "INTPRIORITY_198,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h202"
hexmask.long 0x318 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x318 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x31C "INTPRIORITY_199,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h203"
hexmask.long 0x31C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x31C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x320 "INTPRIORITY_200,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h204"
hexmask.long 0x320 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x320 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x324 "INTPRIORITY_201,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h205"
hexmask.long 0x324 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x324 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x328 "INTPRIORITY_202,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h206"
hexmask.long 0x328 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x328 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x32C "INTPRIORITY_203,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h207"
hexmask.long 0x32C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x32C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x330 "INTPRIORITY_204,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h208"
hexmask.long 0x330 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x330 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x334 "INTPRIORITY_205,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h209"
hexmask.long 0x334 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x334 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x338 "INTPRIORITY_206,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h210"
hexmask.long 0x338 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x338 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x33C "INTPRIORITY_207,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h211"
hexmask.long 0x33C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x33C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x340 "INTPRIORITY_208,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h212"
hexmask.long 0x340 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x340 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x344 "INTPRIORITY_209,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h213"
hexmask.long 0x344 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x344 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x348 "INTPRIORITY_210,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h214"
hexmask.long 0x348 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x348 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34C "INTPRIORITY_211,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h215"
hexmask.long 0x34C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x350 "INTPRIORITY_212,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h216"
hexmask.long 0x350 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x350 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x354 "INTPRIORITY_213,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h217"
hexmask.long 0x354 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x354 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x358 "INTPRIORITY_214,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h218"
hexmask.long 0x358 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x358 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x35C "INTPRIORITY_215,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h219"
hexmask.long 0x35C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x35C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x360 "INTPRIORITY_216,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h220"
hexmask.long 0x360 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x360 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x364 "INTPRIORITY_217,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h221"
hexmask.long 0x364 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x364 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x368 "INTPRIORITY_218,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h222"
hexmask.long 0x368 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x368 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x36C "INTPRIORITY_219,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h223"
hexmask.long 0x36C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x36C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x370 "INTPRIORITY_220,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h224"
hexmask.long 0x370 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x370 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x374 "INTPRIORITY_221,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h225"
hexmask.long 0x374 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x374 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x378 "INTPRIORITY_222,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h226"
hexmask.long 0x378 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x378 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x37C "INTPRIORITY_223,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h227"
hexmask.long 0x37C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x37C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x380 "INTPRIORITY_224,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h228"
hexmask.long 0x380 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x380 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x384 "INTPRIORITY_225,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h229"
hexmask.long 0x384 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x384 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x388 "INTPRIORITY_226,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h230"
hexmask.long 0x388 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x388 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38C "INTPRIORITY_227,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h231"
hexmask.long 0x38C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x390 "INTPRIORITY_228,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h232"
hexmask.long 0x390 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x390 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x394 "INTPRIORITY_229,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h233"
hexmask.long 0x394 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x394 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x398 "INTPRIORITY_230,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h234"
hexmask.long 0x398 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x398 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x39C "INTPRIORITY_231,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h235"
hexmask.long 0x39C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x39C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A0 "INTPRIORITY_232,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h236"
hexmask.long 0x3A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A4 "INTPRIORITY_233,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h237"
hexmask.long 0x3A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A8 "INTPRIORITY_234,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h238"
hexmask.long 0x3A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3AC "INTPRIORITY_235,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h239"
hexmask.long 0x3AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B0 "INTPRIORITY_236,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h240"
hexmask.long 0x3B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B4 "INTPRIORITY_237,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h241"
hexmask.long 0x3B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B8 "INTPRIORITY_238,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h242"
hexmask.long 0x3B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3BC "INTPRIORITY_239,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h243"
hexmask.long 0x3BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C0 "INTPRIORITY_240,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h244"
hexmask.long 0x3C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C4 "INTPRIORITY_241,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h245"
hexmask.long 0x3C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C8 "INTPRIORITY_242,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h246"
hexmask.long 0x3C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3CC "INTPRIORITY_243,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h247"
hexmask.long 0x3CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D0 "INTPRIORITY_244,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h248"
hexmask.long 0x3D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D4 "INTPRIORITY_245,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h249"
hexmask.long 0x3D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D8 "INTPRIORITY_246,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h250"
hexmask.long 0x3D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3DC "INTPRIORITY_247,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h251"
hexmask.long 0x3DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E0 "INTPRIORITY_248,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h252"
hexmask.long 0x3E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E4 "INTPRIORITY_249,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h253"
hexmask.long 0x3E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E8 "INTPRIORITY_250,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h254"
hexmask.long 0x3E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3EC "INTPRIORITY_251,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h255"
hexmask.long 0x3EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F0 "INTPRIORITY_252,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h256"
hexmask.long 0x3F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F4 "INTPRIORITY_253,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h257"
hexmask.long 0x3F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F8 "INTPRIORITY_254,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h258"
hexmask.long 0x3F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3FC "INTPRIORITY_255,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h259"
hexmask.long 0x3FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x3FF
line.long 0x00 "INTVECTOR,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h4"
hexmask.long 0x00 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x00 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x04 "INTVECTOR_1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
hexmask.long 0x04 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x04 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x08 "INTVECTOR_2,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h6"
hexmask.long 0x08 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x08 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x0C "INTVECTOR_3,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h7"
hexmask.long 0x0C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x0C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10 "INTVECTOR_4,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h8"
hexmask.long 0x10 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14 "INTVECTOR_5,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h9"
hexmask.long 0x14 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18 "INTVECTOR_6,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h10"
hexmask.long 0x18 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C "INTVECTOR_7,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h11"
hexmask.long 0x1C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20 "INTVECTOR_8,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h12"
hexmask.long 0x20 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24 "INTVECTOR_9,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h13"
hexmask.long 0x24 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28 "INTVECTOR_10,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h14"
hexmask.long 0x28 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C "INTVECTOR_11,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h15"
hexmask.long 0x2C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30 "INTVECTOR_12,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h16"
hexmask.long 0x30 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34 "INTVECTOR_13,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h17"
hexmask.long 0x34 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38 "INTVECTOR_14,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h18"
hexmask.long 0x38 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C "INTVECTOR_15,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h19"
hexmask.long 0x3C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x40 "INTVECTOR_16,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h20"
hexmask.long 0x40 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x40 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x44 "INTVECTOR_17,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h21"
hexmask.long 0x44 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x44 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x48 "INTVECTOR_18,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h22"
hexmask.long 0x48 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x48 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x4C "INTVECTOR_19,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h23"
hexmask.long 0x4C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x4C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x50 "INTVECTOR_20,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h24"
hexmask.long 0x50 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x50 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x54 "INTVECTOR_21,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h25"
hexmask.long 0x54 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x54 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x58 "INTVECTOR_22,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h26"
hexmask.long 0x58 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x58 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x5C "INTVECTOR_23,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h27"
hexmask.long 0x5C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x5C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x60 "INTVECTOR_24,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h28"
hexmask.long 0x60 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x60 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x64 "INTVECTOR_25,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h29"
hexmask.long 0x64 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x64 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x68 "INTVECTOR_26,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h30"
hexmask.long 0x68 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x68 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x6C "INTVECTOR_27,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h31"
hexmask.long 0x6C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x6C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x70 "INTVECTOR_28,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h32"
hexmask.long 0x70 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x70 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x74 "INTVECTOR_29,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h33"
hexmask.long 0x74 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x74 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x78 "INTVECTOR_30,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h34"
hexmask.long 0x78 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x78 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x7C "INTVECTOR_31,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h35"
hexmask.long 0x7C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x7C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x80 "INTVECTOR_32,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h36"
hexmask.long 0x80 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x80 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x84 "INTVECTOR_33,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h37"
hexmask.long 0x84 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x84 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x88 "INTVECTOR_34,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h38"
hexmask.long 0x88 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x88 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x8C "INTVECTOR_35,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h39"
hexmask.long 0x8C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x8C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x90 "INTVECTOR_36,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h40"
hexmask.long 0x90 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x90 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x94 "INTVECTOR_37,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h41"
hexmask.long 0x94 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x94 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x98 "INTVECTOR_38,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h42"
hexmask.long 0x98 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x98 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x9C "INTVECTOR_39,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h43"
hexmask.long 0x9C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x9C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA0 "INTVECTOR_40,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h44"
hexmask.long 0xA0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA4 "INTVECTOR_41,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h45"
hexmask.long 0xA4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA8 "INTVECTOR_42,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h46"
hexmask.long 0xA8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xAC "INTVECTOR_43,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h47"
hexmask.long 0xAC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xAC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB0 "INTVECTOR_44,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h48"
hexmask.long 0xB0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB4 "INTVECTOR_45,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h49"
hexmask.long 0xB4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB8 "INTVECTOR_46,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h50"
hexmask.long 0xB8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xBC "INTVECTOR_47,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h51"
hexmask.long 0xBC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xBC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC0 "INTVECTOR_48,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h52"
hexmask.long 0xC0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC4 "INTVECTOR_49,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h53"
hexmask.long 0xC4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC8 "INTVECTOR_50,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h54"
hexmask.long 0xC8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xCC "INTVECTOR_51,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h55"
hexmask.long 0xCC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xCC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD0 "INTVECTOR_52,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h56"
hexmask.long 0xD0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD4 "INTVECTOR_53,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h57"
hexmask.long 0xD4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD8 "INTVECTOR_54,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h58"
hexmask.long 0xD8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xDC "INTVECTOR_55,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h59"
hexmask.long 0xDC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xDC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE0 "INTVECTOR_56,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h60"
hexmask.long 0xE0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE4 "INTVECTOR_57,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h61"
hexmask.long 0xE4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE8 "INTVECTOR_58,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h62"
hexmask.long 0xE8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xEC "INTVECTOR_59,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h63"
hexmask.long 0xEC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xEC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF0 "INTVECTOR_60,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h64"
hexmask.long 0xF0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF4 "INTVECTOR_61,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h65"
hexmask.long 0xF4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF8 "INTVECTOR_62,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h66"
hexmask.long 0xF8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xFC "INTVECTOR_63,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h67"
hexmask.long 0xFC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xFC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x100 "INTVECTOR_64,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h68"
hexmask.long 0x100 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x100 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x104 "INTVECTOR_65,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h69"
hexmask.long 0x104 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x104 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x108 "INTVECTOR_66,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h70"
hexmask.long 0x108 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x108 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10C "INTVECTOR_67,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h71"
hexmask.long 0x10C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x110 "INTVECTOR_68,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h72"
hexmask.long 0x110 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x110 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x114 "INTVECTOR_69,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h73"
hexmask.long 0x114 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x114 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x118 "INTVECTOR_70,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h74"
hexmask.long 0x118 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x118 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x11C "INTVECTOR_71,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h75"
hexmask.long 0x11C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x11C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x120 "INTVECTOR_72,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h76"
hexmask.long 0x120 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x120 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x124 "INTVECTOR_73,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h77"
hexmask.long 0x124 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x124 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x128 "INTVECTOR_74,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h78"
hexmask.long 0x128 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x128 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x12C "INTVECTOR_75,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h79"
hexmask.long 0x12C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x12C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x130 "INTVECTOR_76,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h80"
hexmask.long 0x130 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x130 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x134 "INTVECTOR_77,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h81"
hexmask.long 0x134 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x134 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x138 "INTVECTOR_78,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h82"
hexmask.long 0x138 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x138 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x13C "INTVECTOR_79,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h83"
hexmask.long 0x13C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x13C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x140 "INTVECTOR_80,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h84"
hexmask.long 0x140 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x140 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x144 "INTVECTOR_81,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h85"
hexmask.long 0x144 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x144 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x148 "INTVECTOR_82,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h86"
hexmask.long 0x148 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x148 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14C "INTVECTOR_83,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h87"
hexmask.long 0x14C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x150 "INTVECTOR_84,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h88"
hexmask.long 0x150 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x150 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x154 "INTVECTOR_85,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h89"
hexmask.long 0x154 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x154 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x158 "INTVECTOR_86,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h90"
hexmask.long 0x158 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x158 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x15C "INTVECTOR_87,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h91"
hexmask.long 0x15C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x15C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x160 "INTVECTOR_88,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h92"
hexmask.long 0x160 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x160 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x164 "INTVECTOR_89,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h93"
hexmask.long 0x164 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x164 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x168 "INTVECTOR_90,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h94"
hexmask.long 0x168 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x168 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x16C "INTVECTOR_91,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h95"
hexmask.long 0x16C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x16C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x170 "INTVECTOR_92,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h96"
hexmask.long 0x170 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x170 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x174 "INTVECTOR_93,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h97"
hexmask.long 0x174 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x174 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x178 "INTVECTOR_94,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h98"
hexmask.long 0x178 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x178 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x17C "INTVECTOR_95,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h99"
hexmask.long 0x17C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x17C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x180 "INTVECTOR_96,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h100"
hexmask.long 0x180 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x180 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x184 "INTVECTOR_97,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h101"
hexmask.long 0x184 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x184 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x188 "INTVECTOR_98,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h102"
hexmask.long 0x188 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x188 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18C "INTVECTOR_99,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h103"
hexmask.long 0x18C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x190 "INTVECTOR_100,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h104"
hexmask.long 0x190 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x190 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x194 "INTVECTOR_101,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h105"
hexmask.long 0x194 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x194 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x198 "INTVECTOR_102,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h106"
hexmask.long 0x198 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x198 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x19C "INTVECTOR_103,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h107"
hexmask.long 0x19C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x19C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A0 "INTVECTOR_104,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h108"
hexmask.long 0x1A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A4 "INTVECTOR_105,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h109"
hexmask.long 0x1A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A8 "INTVECTOR_106,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h110"
hexmask.long 0x1A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1AC "INTVECTOR_107,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h111"
hexmask.long 0x1AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B0 "INTVECTOR_108,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h112"
hexmask.long 0x1B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B4 "INTVECTOR_109,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h113"
hexmask.long 0x1B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B8 "INTVECTOR_110,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h114"
hexmask.long 0x1B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1BC "INTVECTOR_111,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h115"
hexmask.long 0x1BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C0 "INTVECTOR_112,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h116"
hexmask.long 0x1C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C4 "INTVECTOR_113,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h117"
hexmask.long 0x1C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C8 "INTVECTOR_114,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h118"
hexmask.long 0x1C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1CC "INTVECTOR_115,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h119"
hexmask.long 0x1CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D0 "INTVECTOR_116,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h120"
hexmask.long 0x1D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D4 "INTVECTOR_117,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h121"
hexmask.long 0x1D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D8 "INTVECTOR_118,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h122"
hexmask.long 0x1D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1DC "INTVECTOR_119,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h123"
hexmask.long 0x1DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E0 "INTVECTOR_120,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h124"
hexmask.long 0x1E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E4 "INTVECTOR_121,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h125"
hexmask.long 0x1E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E8 "INTVECTOR_122,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h126"
hexmask.long 0x1E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1EC "INTVECTOR_123,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h127"
hexmask.long 0x1EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F0 "INTVECTOR_124,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h128"
hexmask.long 0x1F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F4 "INTVECTOR_125,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h129"
hexmask.long 0x1F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F8 "INTVECTOR_126,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h130"
hexmask.long 0x1F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1FC "INTVECTOR_127,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h131"
hexmask.long 0x1FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x200 "INTVECTOR_128,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h132"
hexmask.long 0x200 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x200 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x204 "INTVECTOR_129,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h133"
hexmask.long 0x204 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x204 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x208 "INTVECTOR_130,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h134"
hexmask.long 0x208 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x208 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20C "INTVECTOR_131,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h135"
hexmask.long 0x20C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x210 "INTVECTOR_132,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h136"
hexmask.long 0x210 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x210 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x214 "INTVECTOR_133,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h137"
hexmask.long 0x214 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x214 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x218 "INTVECTOR_134,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h138"
hexmask.long 0x218 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x218 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x21C "INTVECTOR_135,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h139"
hexmask.long 0x21C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x21C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x220 "INTVECTOR_136,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h140"
hexmask.long 0x220 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x220 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x224 "INTVECTOR_137,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h141"
hexmask.long 0x224 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x224 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x228 "INTVECTOR_138,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h142"
hexmask.long 0x228 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x228 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x22C "INTVECTOR_139,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h143"
hexmask.long 0x22C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x22C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x230 "INTVECTOR_140,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h144"
hexmask.long 0x230 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x230 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x234 "INTVECTOR_141,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h145"
hexmask.long 0x234 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x234 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x238 "INTVECTOR_142,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h146"
hexmask.long 0x238 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x238 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x23C "INTVECTOR_143,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h147"
hexmask.long 0x23C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x23C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x240 "INTVECTOR_144,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h148"
hexmask.long 0x240 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x240 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x244 "INTVECTOR_145,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h149"
hexmask.long 0x244 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x244 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x248 "INTVECTOR_146,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h150"
hexmask.long 0x248 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x248 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24C "INTVECTOR_147,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h151"
hexmask.long 0x24C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x250 "INTVECTOR_148,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h152"
hexmask.long 0x250 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x250 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x254 "INTVECTOR_149,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h153"
hexmask.long 0x254 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x254 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x258 "INTVECTOR_150,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h154"
hexmask.long 0x258 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x258 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x25C "INTVECTOR_151,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h155"
hexmask.long 0x25C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x25C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x260 "INTVECTOR_152,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h156"
hexmask.long 0x260 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x260 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x264 "INTVECTOR_153,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h157"
hexmask.long 0x264 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x264 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x268 "INTVECTOR_154,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h158"
hexmask.long 0x268 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x268 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x26C "INTVECTOR_155,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h159"
hexmask.long 0x26C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x26C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x270 "INTVECTOR_156,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h160"
hexmask.long 0x270 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x270 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x274 "INTVECTOR_157,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h161"
hexmask.long 0x274 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x274 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x278 "INTVECTOR_158,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h162"
hexmask.long 0x278 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x278 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x27C "INTVECTOR_159,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h163"
hexmask.long 0x27C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x27C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x280 "INTVECTOR_160,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h164"
hexmask.long 0x280 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x280 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x284 "INTVECTOR_161,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h165"
hexmask.long 0x284 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x284 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x288 "INTVECTOR_162,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h166"
hexmask.long 0x288 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x288 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28C "INTVECTOR_163,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h167"
hexmask.long 0x28C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x290 "INTVECTOR_164,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h168"
hexmask.long 0x290 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x290 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x294 "INTVECTOR_165,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h169"
hexmask.long 0x294 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x294 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x298 "INTVECTOR_166,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h170"
hexmask.long 0x298 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x298 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x29C "INTVECTOR_167,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h171"
hexmask.long 0x29C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x29C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A0 "INTVECTOR_168,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h172"
hexmask.long 0x2A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A4 "INTVECTOR_169,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h173"
hexmask.long 0x2A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A8 "INTVECTOR_170,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h174"
hexmask.long 0x2A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2AC "INTVECTOR_171,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h175"
hexmask.long 0x2AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B0 "INTVECTOR_172,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h176"
hexmask.long 0x2B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B4 "INTVECTOR_173,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h177"
hexmask.long 0x2B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B8 "INTVECTOR_174,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h178"
hexmask.long 0x2B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2BC "INTVECTOR_175,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h179"
hexmask.long 0x2BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C0 "INTVECTOR_176,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h180"
hexmask.long 0x2C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C4 "INTVECTOR_177,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h181"
hexmask.long 0x2C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C8 "INTVECTOR_178,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h182"
hexmask.long 0x2C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2CC "INTVECTOR_179,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h183"
hexmask.long 0x2CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D0 "INTVECTOR_180,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h184"
hexmask.long 0x2D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D4 "INTVECTOR_181,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h185"
hexmask.long 0x2D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D8 "INTVECTOR_182,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h186"
hexmask.long 0x2D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2DC "INTVECTOR_183,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h187"
hexmask.long 0x2DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E0 "INTVECTOR_184,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h188"
hexmask.long 0x2E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E4 "INTVECTOR_185,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h189"
hexmask.long 0x2E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E8 "INTVECTOR_186,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h190"
hexmask.long 0x2E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2EC "INTVECTOR_187,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h191"
hexmask.long 0x2EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F0 "INTVECTOR_188,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h192"
hexmask.long 0x2F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F4 "INTVECTOR_189,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h193"
hexmask.long 0x2F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F8 "INTVECTOR_190,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h194"
hexmask.long 0x2F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2FC "INTVECTOR_191,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h195"
hexmask.long 0x2FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x300 "INTVECTOR_192,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h196"
hexmask.long 0x300 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x300 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x304 "INTVECTOR_193,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h197"
hexmask.long 0x304 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x304 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x308 "INTVECTOR_194,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h198"
hexmask.long 0x308 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x308 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30C "INTVECTOR_195,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h199"
hexmask.long 0x30C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x310 "INTVECTOR_196,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h200"
hexmask.long 0x310 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x310 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x314 "INTVECTOR_197,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h201"
hexmask.long 0x314 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x314 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x318 "INTVECTOR_198,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h202"
hexmask.long 0x318 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x318 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x31C "INTVECTOR_199,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h203"
hexmask.long 0x31C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x31C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x320 "INTVECTOR_200,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h204"
hexmask.long 0x320 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x320 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x324 "INTVECTOR_201,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h205"
hexmask.long 0x324 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x324 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x328 "INTVECTOR_202,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h206"
hexmask.long 0x328 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x328 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x32C "INTVECTOR_203,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h207"
hexmask.long 0x32C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x32C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x330 "INTVECTOR_204,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h208"
hexmask.long 0x330 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x330 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x334 "INTVECTOR_205,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h209"
hexmask.long 0x334 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x334 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x338 "INTVECTOR_206,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h210"
hexmask.long 0x338 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x338 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x33C "INTVECTOR_207,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h211"
hexmask.long 0x33C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x33C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x340 "INTVECTOR_208,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h212"
hexmask.long 0x340 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x340 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x344 "INTVECTOR_209,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h213"
hexmask.long 0x344 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x344 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x348 "INTVECTOR_210,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h214"
hexmask.long 0x348 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x348 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34C "INTVECTOR_211,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h215"
hexmask.long 0x34C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x350 "INTVECTOR_212,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h216"
hexmask.long 0x350 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x350 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x354 "INTVECTOR_213,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h217"
hexmask.long 0x354 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x354 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x358 "INTVECTOR_214,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h218"
hexmask.long 0x358 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x358 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x35C "INTVECTOR_215,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h219"
hexmask.long 0x35C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x35C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x360 "INTVECTOR_216,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h220"
hexmask.long 0x360 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x360 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x364 "INTVECTOR_217,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h221"
hexmask.long 0x364 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x364 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x368 "INTVECTOR_218,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h222"
hexmask.long 0x368 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x368 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x36C "INTVECTOR_219,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h223"
hexmask.long 0x36C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x36C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x370 "INTVECTOR_220,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h224"
hexmask.long 0x370 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x370 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x374 "INTVECTOR_221,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h225"
hexmask.long 0x374 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x374 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x378 "INTVECTOR_222,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h226"
hexmask.long 0x378 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x378 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x37C "INTVECTOR_223,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h227"
hexmask.long 0x37C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x37C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x380 "INTVECTOR_224,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h228"
hexmask.long 0x380 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x380 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x384 "INTVECTOR_225,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h229"
hexmask.long 0x384 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x384 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x388 "INTVECTOR_226,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h230"
hexmask.long 0x388 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x388 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38C "INTVECTOR_227,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h231"
hexmask.long 0x38C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x390 "INTVECTOR_228,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h232"
hexmask.long 0x390 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x390 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x394 "INTVECTOR_229,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h233"
hexmask.long 0x394 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x394 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x398 "INTVECTOR_230,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h234"
hexmask.long 0x398 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x398 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x39C "INTVECTOR_231,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h235"
hexmask.long 0x39C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x39C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A0 "INTVECTOR_232,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h236"
hexmask.long 0x3A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A4 "INTVECTOR_233,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h237"
hexmask.long 0x3A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A8 "INTVECTOR_234,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h238"
hexmask.long 0x3A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3AC "INTVECTOR_235,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h239"
hexmask.long 0x3AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B0 "INTVECTOR_236,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h240"
hexmask.long 0x3B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B4 "INTVECTOR_237,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h241"
hexmask.long 0x3B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B8 "INTVECTOR_238,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h242"
hexmask.long 0x3B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3BC "INTVECTOR_239,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h243"
hexmask.long 0x3BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C0 "INTVECTOR_240,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h244"
hexmask.long 0x3C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C4 "INTVECTOR_241,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h245"
hexmask.long 0x3C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C8 "INTVECTOR_242,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h246"
hexmask.long 0x3C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3CC "INTVECTOR_243,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h247"
hexmask.long 0x3CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D0 "INTVECTOR_244,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h248"
hexmask.long 0x3D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D4 "INTVECTOR_245,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h249"
hexmask.long 0x3D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D8 "INTVECTOR_246,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h250"
hexmask.long 0x3D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3DC "INTVECTOR_247,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h251"
hexmask.long 0x3DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E0 "INTVECTOR_248,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h252"
hexmask.long 0x3E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E4 "INTVECTOR_249,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h253"
hexmask.long 0x3E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E8 "INTVECTOR_250,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h254"
hexmask.long 0x3E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3EC "INTVECTOR_251,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h255"
hexmask.long 0x3EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F0 "INTVECTOR_252,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h256"
hexmask.long 0x3F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F4 "INTVECTOR_253,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h257"
hexmask.long 0x3F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F8 "INTVECTOR_254,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h258"
hexmask.long 0x3F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3FC "INTVECTOR_255,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h259"
hexmask.long 0x3FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3FC 0.--1. "RES20,Reserved" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_WDT (MSS WDT Module Registers)"
base ad:0x52F7A300
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "RCSS_ATL (RCSS ATL Module Registers)"
base ad:0x55240000
rgroup.long 0x00++0x03
line.long 0x00 "REVISION,Peripheral Revision Register"
bitfld.long 0x00 30.--31. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x00 28.--29. "UNDEFINED_NAME," "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 11.--15. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "UNDEFINED_NAME," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x200++0x0B
line.long 0x00 "ATL0_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL0_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL0_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x210++0x0F
line.long 0x00 "ATL0_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL0_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL0_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL0_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
group.long 0x280++0x0B
line.long 0x00 "ATL1_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL1_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL1_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x290++0x0F
line.long 0x00 "ATL1_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL1_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL1_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL1_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
group.long 0x300++0x0B
line.long 0x00 "ATL2_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL2_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL2_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x310++0x0F
line.long 0x00 "ATL2_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL2_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL2_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL2_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
group.long 0x380++0x0B
line.long 0x00 "ATL3_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL3_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL3_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x390++0x0F
line.long 0x00 "ATL3_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL3_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL3_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL3_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
width 0x0B
tree.end
tree "RCSS_CSI2A (RCSS CSI2A Module Registers)"
base ad:0x55080000
rgroup.long 0x00++0x03
line.long 0x00 "CSI2_REVISION,MODULE REVISION This register contains the IP revision code in binary coded digital"
hexmask.long.tbyte 0x00 8.--31. 1. "RES1,RESERVE FIELD"
newline
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision"
group.long 0x10++0x0F
line.long 0x00 "CSI2_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES2,RESERVE FIELD"
newline
bitfld.long 0x00 12.--13. "MSTANDBY_MODE,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--11. 1. "RES3,RESERVE FIELD"
newline
bitfld.long 0x00 1. "SOFT_RESET,Software reset" "Normal mode,The module is reset"
newline
bitfld.long 0x00 0. "AUTO_IDLE,Internal OCP gating strategy" "OCP clock is free-running,Automatic OCP clock gating strategy is applied.."
line.long 0x04 "CSI2_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module excluding the interrupt status register"
hexmask.long 0x04 1.--31. 1. "RES4,RESERVE FIELD"
newline
bitfld.long 0x04 0. "RESET_DONE,Internal reset monitoring" "Internal module reset is on going,Reset completed"
line.long 0x08 "CSI2_IRQSTATUS,INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt"
hexmask.long.tbyte 0x08 15.--31. 1. "RES5,RESERVE FIELD"
newline
bitfld.long 0x08 14. "OCP_ERR_IRQ,OCP Error Interrupt" "READS,READS"
newline
bitfld.long 0x08 13. "SHORT_PACKET_IRQ,Short packet reception status (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "READS,READS"
newline
bitfld.long 0x08 12. "ECC_CORRECTION_IRQ,ECC has been used to do the correction of the only 1-bit error status (short packet only)" "READS,READS"
newline
bitfld.long 0x08 11. "ECC_NO_CORRECTION_IRQ,ECC error status (short and long packets)" "READS,READS"
newline
rbitfld.long 0x08 10. "COMPLEXIO2_ERR_IRQ,RESERVE FIELD" "0,1"
newline
bitfld.long 0x08 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: status of the PHY errors received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "READS,READS"
newline
bitfld.long 0x08 8. "FIFO_OVF_IRQ,FIFO overflow error status" "READS,READS"
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bitfld.long 0x08 7. "CONTEXT7,Context 7" "READS,READS"
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bitfld.long 0x08 6. "CONTEXT6,Context 6" "READS,READS"
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bitfld.long 0x08 5. "CONTEXT5,Context 5" "READS,READS"
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bitfld.long 0x08 4. "CONTEXT4,Context 4" "READS,READS"
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bitfld.long 0x08 3. "CONTEXT3,Context 3" "READS,READS"
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bitfld.long 0x08 2. "CONTEXT2,Context 2" "READS,READS"
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bitfld.long 0x08 1. "CONTEXT1,Context 1" "READS,READS"
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bitfld.long 0x08 0. "CONTEXT0,Context 0" "READS,READS"
line.long 0x0C "CSI2_IRQENABLE,INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually"
hexmask.long.tbyte 0x0C 15.--31. 1. "RES6,RESERVE FIELD"
newline
bitfld.long 0x0C 14. "OCP_ERR_IRQ,OCP Error Interrupt" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 13. "SHORT_PACKET_IRQ,Short packet reception (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 12. "ECC_CORRECTION_IRQ,ECC has been used to correct the only 1-bit error (short packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 11. "ECC_NO_CORRECTION_IRQ,ECC error (short and long packets)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 10. "COMPLEXIO2_ERR_IRQ,RESERVED" "0,1"
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bitfld.long 0x0C 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: the interrupt is triggered when any error is received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 8. "FIFO_OVF_IRQ,FIFO overflow enable" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 7. "CONTEXT7,Context 7" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 6. "CONTEXT6,Context 6" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 5. "CONTEXT5,Context 5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 4. "CONTEXT4,Context 4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 3. "CONTEXT3,Context 3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 2. "CONTEXT2,Context 2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 1. "CONTEXT1,Context 1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 0. "CONTEXT0,Context 0" "Event is masked,Event generates an interrupt when it occurs"
group.long 0x40++0x14B
line.long 0x00 "CSI2_CTRL,GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module"
hexmask.long.word 0x00 23.--31. 1. "RES7,RESERVE FIELD"
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bitfld.long 0x00 20.--22. "MFLAG_LEVH,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "MFLAG_LEVL,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "BURST_SIZE_EXPAND,Sets the DMA burst size on the L3 interconnect" "Use the burst size defined in the BURST_SIZE..,Allow generation of 16x64-bit bursts"
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bitfld.long 0x00 15. "VP_CLK_EN,RESERVE FIELD" "0,1"
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bitfld.long 0x00 14. "STREAMING,Streaming mode" "Disable,Enable"
newline
bitfld.long 0x00 13. "NON_POSTED_WRITE,Not Posted Writes" "Disable,Enable"
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rbitfld.long 0x00 12. "RES8,RESERVE FIELD" "0,1"
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bitfld.long 0x00 11. "VP_ONLY_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 10. "STREAMING_32_BIT,Indicates if 64-bit or 32-bit streaming burst is used" "0,1"
newline
bitfld.long 0x00 8.--9. "VP_OUT_CTRL,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 7. "DBG_EN,Enables the debug mode" "Disable,Enable"
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bitfld.long 0x00 5.--6. "BURST_SIZE,Sets the DMA burst size on the L3 interconnect" "1x64 OCP writes,2x64 OCP writes,4x64 OCP writes,8x64 OCP writes"
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bitfld.long 0x00 4. "ENDIANNESS,Select endianness for YUV422 8 bit and YUV420 legacy formats" "Use native MIPI CSI2 endianness,Store all pixel formats little endian"
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bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "If IF_EN = 0 the interface is disabled immediately,If IF_EN = 1 the interface is disabled after all.."
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bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "Disabled,Enabled"
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bitfld.long 0x00 1. "SECURE,RESERVE FIELD" "0,1"
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bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "The interface is disabled,The interface is enabled immediately the data.."
line.long 0x04 "CSI2_DBG_H,DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x08 "CSI2_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design"
hexmask.long 0x08 6.--31. 1. "RES9,RESERVE FIELD"
newline
bitfld.long 0x08 2.--5. "FIFODEPTH,Output FIFO size in multiple of 68 bits" "?,?,8x 68 bits,16x 68 bits,32x 68 bits,64x 68 bits,128 x 68 bits,256 x 68 bits,?..."
newline
bitfld.long 0x08 0.--1. "NBCONTEXTS,Number of contexts supported by the module" "1 Context,2 Contexts,4 Contexts,8 Contexts"
line.long 0x0C "CSI2_COMPLEXIO_CFG2,COMPLEX IO CONFIGURATION REGISTER for the complex IO #2 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x0C 31. "RES10,RESERVE FIELD" "0,1"
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bitfld.long 0x0C 30. "RESET_CTRL,RESERVE FIELD" "0,1"
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rbitfld.long 0x0C 29. "RESET_DONE,RESERVE FIELD" "0,1"
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bitfld.long 0x0C 27.--28. "PWR_CMD,RESERVE FIELD" "0,1,2,3"
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rbitfld.long 0x0C 25.--26. "PWR_STATUS,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x0C 24. "PWR_AUTO,RESERVE FIELD" "0,1"
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rbitfld.long 0x0C 20.--23. "RES11,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 19. "DATA4_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 16.--18. "DATA4_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 15. "DATA3_POL,RESERVE FIELD" "0,1"
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bitfld.long 0x0C 12.--14. "DATA3_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 11. "DATA2_POL,RESERVE FIELD" "0,1"
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bitfld.long 0x0C 8.--10. "DATA2_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 7. "DATA1_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 4.--6. "DATA1_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 3. "CLOCK_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 0.--2. "CLOCK_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
line.long 0x10 "CSI2_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex IO #1 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x10 31. "RES12,RESERVE FIELD" "0,1"
newline
bitfld.long 0x10 30. "RESET_CTRL,Controls the reset of the complex IO" "Complex IO reset active,Complex IO reset de-asserted"
newline
bitfld.long 0x10 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io" "Internal module reset is on going,Reset completed"
newline
bitfld.long 0x10 27.--28. "PWR_CMD,Command for power control of the complex io" "Command to change to OFF state,Command to change to ON state,Command to change to Ultra Low Power state,?..."
newline
bitfld.long 0x10 25.--26. "PWR_STATUS,Status of the power control of the complex io" "Complex IO in OFF state,Complex IO in ON state,Complex IO in Ultra Low Power state,?..."
newline
bitfld.long 0x10 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "Disable,Enable"
newline
rbitfld.long 0x10 20.--23. "RES13,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "Not used/connected,Data lane 4 is at the position 1,Data lane 4 is at the position 2,Data lane 4 is at the position 3,Data lane 4 is at the position 4,Data lane 4 is at the position 5,?..."
newline
bitfld.long 0x10 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "Not used/connected,Data lane 3 is at the position 1,Data lane 3 is at the position 2,Data lane 3 is at the position 3,Data lane 3 is at the position 4,Data lane 3 is at the position 5,?..."
newline
bitfld.long 0x10 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "Not used/connected,Data lane 2 is at the position 1,Data lane 2 is at the position 2,Data lane 2 is at the position 3,Data lane 2 is at the position 4,Data lane 2 is at the position 5,?..."
newline
bitfld.long 0x10 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,Data lane 1 is at the position 1,Data lane 1 is at the position 2,Data lane 1 is at the position 3,Data lane 1 is at the position 4,Data lane 1 is at the position 5,?..."
newline
bitfld.long 0x10 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,Clock lane is at the position 1,Clock lane is at the position 2,Clock lane is at the position 3,Clock lane is at the position 4,Clock lane is at the position 5,?..."
line.long 0x14 "CSI2_COMPLEXIO1_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #1"
rbitfld.long 0x14 27.--31. "RES14,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "READS,READS"
newline
bitfld.long 0x14 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "READS,READS"
newline
bitfld.long 0x14 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 19. "ERRCONTROL5,Control error for lane #5" "READS,READS"
newline
bitfld.long 0x14 18. "ERRCONTROL4,Control error for lane #4" "READS,READS"
newline
bitfld.long 0x14 17. "ERRCONTROL3,Control error for lane #3" "READS,READS"
newline
bitfld.long 0x14 16. "ERRCONTROL2,Control error for lane #2" "READS,READS"
newline
bitfld.long 0x14 15. "ERRCONTROL1,Control error for lane #1" "READS,READS"
newline
bitfld.long 0x14 14. "ERRESC5,Escape entry error for lane #5" "READS,READS"
newline
bitfld.long 0x14 13. "ERRESC4,Escape entry error for lane #4" "READS,READS"
newline
bitfld.long 0x14 12. "ERRESC3,Escape entry error for lane #3" "READS,READS"
newline
bitfld.long 0x14 11. "ERRESC2,Escape entry error for lane #2" "READS,READS"
newline
bitfld.long 0x14 10. "ERRESC1,Escape entry error for lane #1" "READS,READS"
newline
bitfld.long 0x14 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "READS,READS"
newline
bitfld.long 0x14 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "READS,READS"
newline
bitfld.long 0x14 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "READS,READS"
newline
bitfld.long 0x14 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "READS,READS"
newline
bitfld.long 0x14 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "READS,READS"
newline
bitfld.long 0x14 4. "ERRSOTHS5,Start of transmission error for lane #5" "READS,READS"
newline
bitfld.long 0x14 3. "ERRSOTHS4,Start of transmission error for lane #4" "READS,READS"
newline
bitfld.long 0x14 2. "ERRSOTHS3,Start of transmission error for lane #3" "READS,READS"
newline
bitfld.long 0x14 1. "ERRSOTHS2,Start of transmission error for lane #2" "READS,READS"
newline
bitfld.long 0x14 0. "ERRSOTHS1,Start of transmission error for lane #1" "READS,READS"
line.long 0x18 "CSI2_COMPLEXIO2_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #2"
rbitfld.long 0x18 27.--31. "RES15,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 24. "STATEULPM5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 23. "STATEULPM4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 21. "STATEULPM2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 20. "STATEULPM1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 14. "ERRESC5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 13. "ERRESC4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 12. "ERRESC3,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 11. "ERRESC2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 10. "ERRESC1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x1C "CSI2_SHORT_PACKET,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F"
hexmask.long.byte 0x1C 24.--31. 1. "RES16,RESERVE FIELD"
newline
hexmask.long.tbyte 0x1C 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD"
line.long 0x20 "CSI2_COMPLEXIO1_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #1"
rbitfld.long 0x20 27.--31. "RES17,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x20 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 19. "ERRCONTROL5,Control error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 18. "ERRCONTROL4,Control error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 17. "ERRCONTROL3,Control error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 16. "ERRCONTROL2,Control error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 15. "ERRCONTROL1,Control error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 14. "ERRESC5,Escape entry error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 13. "ERRESC4,Escape entry error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 12. "ERRESC3,Escape entry error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 11. "ERRESC2,Escape entry error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 10. "ERRESC1,Escape entry error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 4. "ERRSOTHS5,Start of transmission error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 3. "ERRSOTHS4,Start of transmission error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 2. "ERRSOTHS3,Start of transmission error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 1. "ERRSOTHS2,Start of transmission error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 0. "ERRSOTHS1,Start of transmission error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x24 "CSI2_COMPLEXIO2_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #2"
rbitfld.long 0x24 27.--31. "RES18,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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bitfld.long 0x24 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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bitfld.long 0x24 24. "STATEULPM5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 23. "STATEULPM4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 21. "STATEULPM2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 20. "STATEULPM1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 14. "ERRESC5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 13. "ERRESC4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 12. "ERRESC3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 11. "ERRESC2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 10. "ERRESC1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x28 "CSI2_DBG_P,DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x2C "CSI2_TIMING,TIMING REGISTER This register controls the CSI2 RECEIVER module"
bitfld.long 0x2C 31. "FORCE_RX_MODE_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 30. "STOP_STATE_X16_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 29. "STOP_STATE_X4_IO2,RESERVE FIELD" "0,1"
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hexmask.long.word 0x2C 16.--28. 1. "STOP_STATE_COUNTER_IO2,RESERVE FIELD"
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bitfld.long 0x2C 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal" "De-assertion of ForceRxMode,Assertion of ForceRxMode"
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bitfld.long 0x2C 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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bitfld.long 0x2C 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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hexmask.long.word 0x2C 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring"
line.long 0x30 "CSI2_CTX0_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x30 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x30 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x30 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x30 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x30 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x30 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x30 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x30 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x30 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x30 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x30 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x30 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x30 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x30 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x30 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x34 "CSI2_CTX0_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x34 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x34 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x34 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
newline
bitfld.long 0x34 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
newline
bitfld.long 0x34 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x34 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x38 "CSI2_CTX0_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x38 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x38 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
newline
rbitfld.long 0x38 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "CSI2_CTX0_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x3C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x3C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x40 "CSI2_CTX0_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x40 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x40 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "CSI2_CTX0_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x44 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x44 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x44 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x44 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x48 "CSI2_CTX0_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x48 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x48 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x48 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x48 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x48 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x48 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x48 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x48 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x48 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x48 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x4C "CSI2_CTX0_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x4C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x4C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x4C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x50 "CSI2_CTX1_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x50 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x50 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0x50 29. "RES19,RESERVE FIELD" "0,1"
newline
bitfld.long 0x50 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
newline
bitfld.long 0x50 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x50 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x50 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0x50 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0x50 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0x50 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0x50 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
newline
bitfld.long 0x50 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
newline
bitfld.long 0x50 2. "VP_FORCE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x50 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
newline
bitfld.long 0x50 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x54 "CSI2_CTX1_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x54 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x54 15. "RES20,RESERVE FIELD" "0,1"
newline
bitfld.long 0x54 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
newline
bitfld.long 0x54 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
newline
bitfld.long 0x54 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
newline
abitfld.long 0x54 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x58 "CSI2_CTX1_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x58 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x58 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x5C "CSI2_CTX1_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x5C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x5C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x60 "CSI2_CTX1_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x60 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x60 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "CSI2_CTX1_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x64 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x64 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x64 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x64 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x68 "CSI2_CTX1_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x68 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x68 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x68 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x68 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x68 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x68 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x68 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x68 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x68 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x68 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x6C "CSI2_CTX1_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x6C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x6C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x6C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x70 "CSI2_CTX2_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x70 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x70 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x70 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x70 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x70 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x70 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x70 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x70 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x70 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x70 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x70 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x70 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x70 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x70 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x70 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x74 "CSI2_CTX2_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x74 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x74 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x74 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x74 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x74 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x74 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x78 "CSI2_CTX2_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x78 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x78 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x7C "CSI2_CTX2_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x7C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x7C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x80 "CSI2_CTX2_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x80 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x80 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x84 "CSI2_CTX2_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x84 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x84 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x84 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x84 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x88 "CSI2_CTX2_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x88 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x88 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x88 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x88 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x88 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x88 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x88 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x88 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x88 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x88 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x8C "CSI2_CTX2_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x8C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x8C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x8C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x90 "CSI2_CTX3_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x90 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x90 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0x90 29. "RES19,RESERVE FIELD" "0,1"
newline
bitfld.long 0x90 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
newline
bitfld.long 0x90 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x90 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x90 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0x90 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0x90 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0x90 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0x90 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x90 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x90 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x90 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x90 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x94 "CSI2_CTX3_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x94 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x94 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x94 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x94 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x94 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x94 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x98 "CSI2_CTX3_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x98 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x98 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x9C "CSI2_CTX3_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x9C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x9C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA0 "CSI2_CTX3_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xA0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xA0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA4 "CSI2_CTX3_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xA4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0xA4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xA4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xA8 "CSI2_CTX3_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA8 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xA8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0xA8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0xA8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0xA8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0xA8 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xA8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0xA8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0xA8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0xA8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xAC "CSI2_CTX3_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xAC 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xAC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xAC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xB0 "CSI2_CTX4_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xB0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0xB0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xB0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xB0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xB0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xB0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xB0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xB0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xB0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xB0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xB0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xB0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xB0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xB4 "CSI2_CTX4_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xB4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xB4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xB4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xB4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xB4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xB4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xB8 "CSI2_CTX4_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xB8 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0xB8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xBC "CSI2_CTX4_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xBC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xBC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC0 "CSI2_CTX4_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xC0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xC0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC4 "CSI2_CTX4_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xC4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0xC4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xC4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xC8 "CSI2_CTX4_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC8 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0xC8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0xC8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0xC8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0xC8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0xC8 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0xC8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0xC8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0xC8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0xC8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xCC "CSI2_CTX4_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xCC 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0xCC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0xCC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xD0 "CSI2_CTX5_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xD0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0xD0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xD0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xD0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xD0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xD0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xD0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xD0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xD0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xD0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xD0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xD0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xD0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xD4 "CSI2_CTX5_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xD4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xD4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xD4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xD4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xD4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xD4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xD8 "CSI2_CTX5_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xD8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xD8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xDC "CSI2_CTX5_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xDC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xDC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE0 "CSI2_CTX5_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xE0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xE0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE4 "CSI2_CTX5_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xE4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0xE4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xE4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xE8 "CSI2_CTX5_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE8 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xE8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0xE8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0xE8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0xE8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0xE8 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xE8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0xE8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0xE8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0xE8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xEC "CSI2_CTX5_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xEC 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xEC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xEC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xF0 "CSI2_CTX6_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xF0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0xF0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xF0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xF0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xF0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xF0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xF0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xF0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xF0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xF0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xF0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xF0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xF0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xF0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xF0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xF4 "CSI2_CTX6_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xF4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xF4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xF4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xF4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xF4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xF4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xF8 "CSI2_CTX6_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xF8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xF8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xFC "CSI2_CTX6_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xFC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xFC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x100 "CSI2_CTX6_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x100 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x100 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x104 "CSI2_CTX6_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x104 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x104 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x104 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x104 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x108 "CSI2_CTX6_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x108 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x108 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x108 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x108 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x108 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x108 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x108 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x108 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x108 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x108 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x10C "CSI2_CTX6_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x10C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x10C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x10C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x110 "CSI2_CTX7_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x110 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x110 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x110 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x110 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x110 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x110 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x110 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x110 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x110 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x110 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x110 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x110 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x110 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x110 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x110 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x114 "CSI2_CTX7_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x114 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x114 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x114 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x114 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x114 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x114 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x118 "CSI2_CTX7_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x118 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x118 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x11C "CSI2_CTX7_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x11C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x11C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x120 "CSI2_CTX7_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x120 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x120 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x124 "CSI2_CTX7_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x124 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x124 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x124 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x124 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x128 "CSI2_CTX7_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x128 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x128 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x128 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x128 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x128 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x128 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x128 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x128 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x128 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x128 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x12C "CSI2_CTX7_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x12C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x12C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x12C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x130 "CSI2_PHY_CFG_REG0,"
hexmask.long.byte 0x130 24.--31. 1. "HS_CLK_CONFIG,Disable clock missing detector"
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hexmask.long.byte 0x130 16.--23. 1. "RESERVED,RESERVED"
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hexmask.long.byte 0x130 8.--15. 1. "THS_TERM,Ths-term timing parameter in multiples of DDR clock"
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hexmask.long.byte 0x130 0.--7. 1. "THS_SETTLE,THS-SETTLE timing parameter in multiples on DDR clock frequency"
line.long 0x134 "CSI2_PHY_CFG_REG1,"
bitfld.long 0x134 30.--31. "RSVD2,Reserved" "0,1,2,3"
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rbitfld.long 0x134 29. "RESETDONECTRLCLK,RESETDONECTRLCLK" "0,1"
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rbitfld.long 0x134 28. "RESETDONERXBYTECLK,RESETDONERXBYTECLK" "0,1"
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bitfld.long 0x134 26.--27. "RSVD1,Reserved" "0,1,2,3"
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rbitfld.long 0x134 25. "CLK_MISS_DET," "0,1"
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hexmask.long.byte 0x134 18.--24. 1. "TCLK_TERM,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + TCLK_TERM + ~ (1-15) ns Programmed value = ceil(9.5.."
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hexmask.long.byte 0x134 10.--17. 1. "D_PHY_HS_SYNC_PAT,DPHY mode HS sync pattern in byte order (reverse of RW 0xB8 received order) D-PHY mode sync pattern"
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bitfld.long 0x134 8.--9. "CTRLCLK_DIV_FACT,Divide factor for CTRLCLK for CLKMISS detector" "0,1,2,3"
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hexmask.long.byte 0x134 0.--7. 1. "TCLK_SETTLE,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~(1-2)* CTRLCLK + Tclk-settle + ~ (1 -15) ns Programmed value = max[3 ceil(155.."
line.long 0x138 "CSI2_PHY_CFG_REG2,"
bitfld.long 0x138 30.--31. "RXTRIGGERESC0,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "0,1,2,3"
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bitfld.long 0x138 28.--29. "RXTRIGGERESC1,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "0,1,2,3"
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bitfld.long 0x138 26.--27. "RXTRIGGERESC2,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2" "0,1,2,3"
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bitfld.long 0x138 24.--25. "RXTRIGGERESC3,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "0,1,2,3"
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hexmask.long.tbyte 0x138 0.--23. 1. "CCP2_SYNC_PAT,CCP2 mode sync pattern in byte order (reverse of received order)"
line.long 0x13C "CSI2_PHY_CFG_REG3,"
bitfld.long 0x13C 31. "OVR_ENHSRX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 26.--30. "ENHSRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 25. "OVR_ENRXTERM,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 20.--24. "ENRXTERM,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 19. "OVR_ENLPRX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 14.--18. "ENLPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 9.--13. "ENULPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 8. "OVR_ENLDO,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 7. "ENLDO,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 6. "OVR_ENBIAS,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 5. "ENBIAS,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 4. "OVR_ENCCP_TO_ANAT,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 3. "OVR_ENCCP_TO_HSRX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 2. "RSVD1,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 1. "RECAL_HS_RX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 0. "RECAL_BIAS,RESERVE FIELD" "0,1"
line.long 0x140 "CSI2_PHY_CFG_REG4,"
bitfld.long 0x140 27.--31. "TRIM_BIAS_GEN,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 22.--26. "TRIM_TERM_LANE4,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 17.--21. "TRIM_TERM_LANE3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 12.--16. "TRIM_TERM_LANE2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 7.--11. "TRIM_TERM_LANE1,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 2.--6. "TRIM_TERM_LANE0,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 1. "BYPASS_EFUSE,RESERVE FIELD" "0,1"
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bitfld.long 0x140 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x144 "CSI2_PHY_CFG_REG5,"
bitfld.long 0x144 26.--31. "TRIM_OFFSET_LANE4_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 20.--25. "TRIM_OFFSET_LANE3_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 14.--19. "TRIM_OFFSET_LANE2_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 8.--13. "TRIM_OFFSET_LANE1_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 2.--7. "TRIM_OFFSET_LANE0_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 1. "BYPASS_CALIB_OFFSET,RESERVE FIELD" "0,1"
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bitfld.long 0x144 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x148 "CSI2_PHY_CFG_REG6,"
hexmask.long.word 0x148 21.--31. 1. "RSVD2,RESERVE FIELD"
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bitfld.long 0x148 20. "OVR_AFE_LANE_ADR_POL,RESERVE FIELD" "0,1"
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hexmask.long.byte 0x148 12.--19. 1. "AFE_LANE_SEL,RESERVE FIELD"
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bitfld.long 0x148 11. "AFE_LANE_POL,RESERVE FIELD" "0,1"
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bitfld.long 0x148 10. "HSCOMOOUT,RESERVE FIELD" "0,1"
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bitfld.long 0x148 9. "BYPASS_LDO_REG,RESERVE FIELD" "0,1"
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bitfld.long 0x148 8. "OBSV_LDO_VOLT_DYA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 7. "OBSV_BIAS_CURR_DXA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 6. "RSVD1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 5. "BIASGEN_CAL_OVR,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 0.--4. "BIASGEN_CAL_OVR_VAL,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C0++0x3F
line.long 0x00 "CSI2_CTX0_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x00 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x00 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x04 "CSI2_CTX0_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x04 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x04 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x08 "CSI2_CTX1_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x08 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x08 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x0C "CSI2_CTX1_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x0C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x0C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x10 "CSI2_CTX2_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x10 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x10 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x14 "CSI2_CTX2_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x14 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x14 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x18 "CSI2_CTX3_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x18 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x18 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x1C "CSI2_CTX3_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x1C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x1C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x20 "CSI2_CTX4_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x20 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x20 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x24 "CSI2_CTX4_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x24 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x24 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x28 "CSI2_CTX5_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x28 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x28 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x2C "CSI2_CTX5_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x2C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x2C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x30 "CSI2_CTX6_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x30 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x30 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x34 "CSI2_CTX6_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x34 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x34 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x38 "CSI2_CTX7_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x38 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x38 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x3C "CSI2_CTX7_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x3C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x3C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
width 0x0B
tree.end
tree "RCSS_CSI2B (RCSS CSI2B Module Registers)"
base ad:0x550A0000
rgroup.long 0x00++0x03
line.long 0x00 "CSI2_REVISION,MODULE REVISION This register contains the IP revision code in binary coded digital"
hexmask.long.tbyte 0x00 8.--31. 1. "RES1,RESERVE FIELD"
newline
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision"
group.long 0x10++0x0F
line.long 0x00 "CSI2_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES2,RESERVE FIELD"
newline
bitfld.long 0x00 12.--13. "MSTANDBY_MODE,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--11. 1. "RES3,RESERVE FIELD"
newline
bitfld.long 0x00 1. "SOFT_RESET,Software reset" "Normal mode,The module is reset"
newline
bitfld.long 0x00 0. "AUTO_IDLE,Internal OCP gating strategy" "OCP clock is free-running,Automatic OCP clock gating strategy is applied.."
line.long 0x04 "CSI2_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module excluding the interrupt status register"
hexmask.long 0x04 1.--31. 1. "RES4,RESERVE FIELD"
newline
bitfld.long 0x04 0. "RESET_DONE,Internal reset monitoring" "Internal module reset is on going,Reset completed"
line.long 0x08 "CSI2_IRQSTATUS,INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt"
hexmask.long.tbyte 0x08 15.--31. 1. "RES5,RESERVE FIELD"
newline
bitfld.long 0x08 14. "OCP_ERR_IRQ,OCP Error Interrupt" "READS,READS"
newline
bitfld.long 0x08 13. "SHORT_PACKET_IRQ,Short packet reception status (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "READS,READS"
newline
bitfld.long 0x08 12. "ECC_CORRECTION_IRQ,ECC has been used to do the correction of the only 1-bit error status (short packet only)" "READS,READS"
newline
bitfld.long 0x08 11. "ECC_NO_CORRECTION_IRQ,ECC error status (short and long packets)" "READS,READS"
newline
rbitfld.long 0x08 10. "COMPLEXIO2_ERR_IRQ,RESERVE FIELD" "0,1"
newline
bitfld.long 0x08 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: status of the PHY errors received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "READS,READS"
newline
bitfld.long 0x08 8. "FIFO_OVF_IRQ,FIFO overflow error status" "READS,READS"
newline
bitfld.long 0x08 7. "CONTEXT7,Context 7" "READS,READS"
newline
bitfld.long 0x08 6. "CONTEXT6,Context 6" "READS,READS"
newline
bitfld.long 0x08 5. "CONTEXT5,Context 5" "READS,READS"
newline
bitfld.long 0x08 4. "CONTEXT4,Context 4" "READS,READS"
newline
bitfld.long 0x08 3. "CONTEXT3,Context 3" "READS,READS"
newline
bitfld.long 0x08 2. "CONTEXT2,Context 2" "READS,READS"
newline
bitfld.long 0x08 1. "CONTEXT1,Context 1" "READS,READS"
newline
bitfld.long 0x08 0. "CONTEXT0,Context 0" "READS,READS"
line.long 0x0C "CSI2_IRQENABLE,INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually"
hexmask.long.tbyte 0x0C 15.--31. 1. "RES6,RESERVE FIELD"
newline
bitfld.long 0x0C 14. "OCP_ERR_IRQ,OCP Error Interrupt" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 13. "SHORT_PACKET_IRQ,Short packet reception (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 12. "ECC_CORRECTION_IRQ,ECC has been used to correct the only 1-bit error (short packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 11. "ECC_NO_CORRECTION_IRQ,ECC error (short and long packets)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 10. "COMPLEXIO2_ERR_IRQ,RESERVED" "0,1"
newline
bitfld.long 0x0C 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: the interrupt is triggered when any error is received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 8. "FIFO_OVF_IRQ,FIFO overflow enable" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 7. "CONTEXT7,Context 7" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 6. "CONTEXT6,Context 6" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 5. "CONTEXT5,Context 5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 4. "CONTEXT4,Context 4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 3. "CONTEXT3,Context 3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 2. "CONTEXT2,Context 2" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 1. "CONTEXT1,Context 1" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 0. "CONTEXT0,Context 0" "Event is masked,Event generates an interrupt when it occurs"
group.long 0x40++0x14B
line.long 0x00 "CSI2_CTRL,GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module"
hexmask.long.word 0x00 23.--31. 1. "RES7,RESERVE FIELD"
newline
bitfld.long 0x00 20.--22. "MFLAG_LEVH,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--19. "MFLAG_LEVL,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16. "BURST_SIZE_EXPAND,Sets the DMA burst size on the L3 interconnect" "Use the burst size defined in the BURST_SIZE..,Allow generation of 16x64-bit bursts"
newline
bitfld.long 0x00 15. "VP_CLK_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 14. "STREAMING,Streaming mode" "Disable,Enable"
newline
bitfld.long 0x00 13. "NON_POSTED_WRITE,Not Posted Writes" "Disable,Enable"
newline
rbitfld.long 0x00 12. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 11. "VP_ONLY_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 10. "STREAMING_32_BIT,Indicates if 64-bit or 32-bit streaming burst is used" "0,1"
newline
bitfld.long 0x00 8.--9. "VP_OUT_CTRL,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x00 7. "DBG_EN,Enables the debug mode" "Disable,Enable"
newline
bitfld.long 0x00 5.--6. "BURST_SIZE,Sets the DMA burst size on the L3 interconnect" "1x64 OCP writes,2x64 OCP writes,4x64 OCP writes,8x64 OCP writes"
newline
bitfld.long 0x00 4. "ENDIANNESS,Select endianness for YUV422 8 bit and YUV420 legacy formats" "Use native MIPI CSI2 endianness,Store all pixel formats little endian"
newline
bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "If IF_EN = 0 the interface is disabled immediately,If IF_EN = 1 the interface is disabled after all.."
newline
bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SECURE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "The interface is disabled,The interface is enabled immediately the data.."
line.long 0x04 "CSI2_DBG_H,DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x08 "CSI2_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design"
hexmask.long 0x08 6.--31. 1. "RES9,RESERVE FIELD"
newline
bitfld.long 0x08 2.--5. "FIFODEPTH,Output FIFO size in multiple of 68 bits" "?,?,8x 68 bits,16x 68 bits,32x 68 bits,64x 68 bits,128 x 68 bits,256 x 68 bits,?..."
newline
bitfld.long 0x08 0.--1. "NBCONTEXTS,Number of contexts supported by the module" "1 Context,2 Contexts,4 Contexts,8 Contexts"
line.long 0x0C "CSI2_COMPLEXIO_CFG2,COMPLEX IO CONFIGURATION REGISTER for the complex IO #2 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x0C 31. "RES10,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 30. "RESET_CTRL,RESERVE FIELD" "0,1"
newline
rbitfld.long 0x0C 29. "RESET_DONE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 27.--28. "PWR_CMD,RESERVE FIELD" "0,1,2,3"
newline
rbitfld.long 0x0C 25.--26. "PWR_STATUS,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x0C 24. "PWR_AUTO,RESERVE FIELD" "0,1"
newline
rbitfld.long 0x0C 20.--23. "RES11,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 19. "DATA4_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 16.--18. "DATA4_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 15. "DATA3_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 12.--14. "DATA3_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 11. "DATA2_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 8.--10. "DATA2_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 7. "DATA1_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 4.--6. "DATA1_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 3. "CLOCK_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 0.--2. "CLOCK_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
line.long 0x10 "CSI2_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex IO #1 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x10 31. "RES12,RESERVE FIELD" "0,1"
newline
bitfld.long 0x10 30. "RESET_CTRL,Controls the reset of the complex IO" "Complex IO reset active,Complex IO reset de-asserted"
newline
bitfld.long 0x10 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io" "Internal module reset is on going,Reset completed"
newline
bitfld.long 0x10 27.--28. "PWR_CMD,Command for power control of the complex io" "Command to change to OFF state,Command to change to ON state,Command to change to Ultra Low Power state,?..."
newline
bitfld.long 0x10 25.--26. "PWR_STATUS,Status of the power control of the complex io" "Complex IO in OFF state,Complex IO in ON state,Complex IO in Ultra Low Power state,?..."
newline
bitfld.long 0x10 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "Disable,Enable"
newline
rbitfld.long 0x10 20.--23. "RES13,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "Not used/connected,Data lane 4 is at the position 1,Data lane 4 is at the position 2,Data lane 4 is at the position 3,Data lane 4 is at the position 4,Data lane 4 is at the position 5,?..."
newline
bitfld.long 0x10 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "Not used/connected,Data lane 3 is at the position 1,Data lane 3 is at the position 2,Data lane 3 is at the position 3,Data lane 3 is at the position 4,Data lane 3 is at the position 5,?..."
newline
bitfld.long 0x10 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "Not used/connected,Data lane 2 is at the position 1,Data lane 2 is at the position 2,Data lane 2 is at the position 3,Data lane 2 is at the position 4,Data lane 2 is at the position 5,?..."
newline
bitfld.long 0x10 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,Data lane 1 is at the position 1,Data lane 1 is at the position 2,Data lane 1 is at the position 3,Data lane 1 is at the position 4,Data lane 1 is at the position 5,?..."
newline
bitfld.long 0x10 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,Clock lane is at the position 1,Clock lane is at the position 2,Clock lane is at the position 3,Clock lane is at the position 4,Clock lane is at the position 5,?..."
line.long 0x14 "CSI2_COMPLEXIO1_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #1"
rbitfld.long 0x14 27.--31. "RES14,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "READS,READS"
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bitfld.long 0x14 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "READS,READS"
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bitfld.long 0x14 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 19. "ERRCONTROL5,Control error for lane #5" "READS,READS"
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bitfld.long 0x14 18. "ERRCONTROL4,Control error for lane #4" "READS,READS"
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bitfld.long 0x14 17. "ERRCONTROL3,Control error for lane #3" "READS,READS"
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bitfld.long 0x14 16. "ERRCONTROL2,Control error for lane #2" "READS,READS"
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bitfld.long 0x14 15. "ERRCONTROL1,Control error for lane #1" "READS,READS"
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bitfld.long 0x14 14. "ERRESC5,Escape entry error for lane #5" "READS,READS"
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bitfld.long 0x14 13. "ERRESC4,Escape entry error for lane #4" "READS,READS"
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bitfld.long 0x14 12. "ERRESC3,Escape entry error for lane #3" "READS,READS"
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bitfld.long 0x14 11. "ERRESC2,Escape entry error for lane #2" "READS,READS"
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bitfld.long 0x14 10. "ERRESC1,Escape entry error for lane #1" "READS,READS"
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bitfld.long 0x14 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "READS,READS"
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bitfld.long 0x14 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "READS,READS"
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bitfld.long 0x14 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "READS,READS"
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bitfld.long 0x14 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "READS,READS"
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bitfld.long 0x14 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "READS,READS"
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bitfld.long 0x14 4. "ERRSOTHS5,Start of transmission error for lane #5" "READS,READS"
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bitfld.long 0x14 3. "ERRSOTHS4,Start of transmission error for lane #4" "READS,READS"
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bitfld.long 0x14 2. "ERRSOTHS3,Start of transmission error for lane #3" "READS,READS"
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bitfld.long 0x14 1. "ERRSOTHS2,Start of transmission error for lane #2" "READS,READS"
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bitfld.long 0x14 0. "ERRSOTHS1,Start of transmission error for lane #1" "READS,READS"
line.long 0x18 "CSI2_COMPLEXIO2_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #2"
rbitfld.long 0x18 27.--31. "RES15,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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bitfld.long 0x18 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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bitfld.long 0x18 24. "STATEULPM5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 23. "STATEULPM4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 21. "STATEULPM2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 20. "STATEULPM1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 14. "ERRESC5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 13. "ERRESC4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 12. "ERRESC3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 11. "ERRESC2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 10. "ERRESC1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x1C "CSI2_SHORT_PACKET,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F"
hexmask.long.byte 0x1C 24.--31. 1. "RES16,RESERVE FIELD"
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hexmask.long.tbyte 0x1C 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD"
line.long 0x20 "CSI2_COMPLEXIO1_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #1"
rbitfld.long 0x20 27.--31. "RES17,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 19. "ERRCONTROL5,Control error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 18. "ERRCONTROL4,Control error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 17. "ERRCONTROL3,Control error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 16. "ERRCONTROL2,Control error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 15. "ERRCONTROL1,Control error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 14. "ERRESC5,Escape entry error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 13. "ERRESC4,Escape entry error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 12. "ERRESC3,Escape entry error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 11. "ERRESC2,Escape entry error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 10. "ERRESC1,Escape entry error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 4. "ERRSOTHS5,Start of transmission error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 3. "ERRSOTHS4,Start of transmission error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 2. "ERRSOTHS3,Start of transmission error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 1. "ERRSOTHS2,Start of transmission error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 0. "ERRSOTHS1,Start of transmission error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x24 "CSI2_COMPLEXIO2_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #2"
rbitfld.long 0x24 27.--31. "RES18,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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bitfld.long 0x24 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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bitfld.long 0x24 24. "STATEULPM5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 23. "STATEULPM4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 21. "STATEULPM2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 20. "STATEULPM1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 14. "ERRESC5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 13. "ERRESC4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 12. "ERRESC3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 11. "ERRESC2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 10. "ERRESC1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x28 "CSI2_DBG_P,DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x2C "CSI2_TIMING,TIMING REGISTER This register controls the CSI2 RECEIVER module"
bitfld.long 0x2C 31. "FORCE_RX_MODE_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 30. "STOP_STATE_X16_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 29. "STOP_STATE_X4_IO2,RESERVE FIELD" "0,1"
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hexmask.long.word 0x2C 16.--28. 1. "STOP_STATE_COUNTER_IO2,RESERVE FIELD"
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bitfld.long 0x2C 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal" "De-assertion of ForceRxMode,Assertion of ForceRxMode"
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bitfld.long 0x2C 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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bitfld.long 0x2C 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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hexmask.long.word 0x2C 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring"
line.long 0x30 "CSI2_CTX0_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x30 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x30 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x30 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x30 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x30 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x30 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x30 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x30 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x30 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x30 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x30 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x30 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x30 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x30 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x30 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x34 "CSI2_CTX0_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x34 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x34 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x34 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x34 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x34 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x34 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x38 "CSI2_CTX0_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x38 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x38 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
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rbitfld.long 0x38 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "CSI2_CTX0_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x3C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x3C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x40 "CSI2_CTX0_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x40 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x40 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "CSI2_CTX0_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x44 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x44 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x44 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x44 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x48 "CSI2_CTX0_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x48 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x48 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x48 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x48 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x48 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x48 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x48 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x48 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x48 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x48 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x4C "CSI2_CTX0_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x4C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x4C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x4C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x50 "CSI2_CTX1_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x50 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x50 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x50 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x50 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x50 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x50 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x50 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x50 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x50 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x50 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x50 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x50 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x50 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x50 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x50 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x54 "CSI2_CTX1_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x54 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x54 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x54 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x54 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x54 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x54 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x58 "CSI2_CTX1_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x58 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x58 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x5C "CSI2_CTX1_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x5C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x5C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x60 "CSI2_CTX1_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x60 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x60 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "CSI2_CTX1_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x64 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x64 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x64 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x64 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x68 "CSI2_CTX1_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x68 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x68 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x68 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x68 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x68 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x68 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x68 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x68 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x68 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x68 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x6C "CSI2_CTX1_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x6C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x6C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x6C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x70 "CSI2_CTX2_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x70 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x70 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0x70 29. "RES19,RESERVE FIELD" "0,1"
newline
bitfld.long 0x70 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
newline
bitfld.long 0x70 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x70 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x70 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0x70 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0x70 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0x70 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0x70 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
newline
bitfld.long 0x70 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
newline
bitfld.long 0x70 2. "VP_FORCE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x70 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
newline
bitfld.long 0x70 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x74 "CSI2_CTX2_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x74 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x74 15. "RES20,RESERVE FIELD" "0,1"
newline
bitfld.long 0x74 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
newline
bitfld.long 0x74 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
newline
bitfld.long 0x74 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
newline
abitfld.long 0x74 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x78 "CSI2_CTX2_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x78 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x78 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x7C "CSI2_CTX2_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x7C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x7C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x80 "CSI2_CTX2_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x80 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x80 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x84 "CSI2_CTX2_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x84 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x84 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x84 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x84 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x88 "CSI2_CTX2_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x88 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x88 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x88 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x88 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x88 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x88 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x88 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x88 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x88 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x88 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x8C "CSI2_CTX2_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x8C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x8C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x8C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x90 "CSI2_CTX3_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x90 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x90 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x90 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x90 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x90 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x90 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x90 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x90 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x90 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x90 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x90 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x90 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x90 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x90 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x90 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x94 "CSI2_CTX3_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x94 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x94 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x94 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x94 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x94 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x94 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x98 "CSI2_CTX3_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x98 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x98 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x9C "CSI2_CTX3_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x9C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x9C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA0 "CSI2_CTX3_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xA0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xA0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA4 "CSI2_CTX3_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xA4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0xA4 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0xA4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xA8 "CSI2_CTX3_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA8 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0xA8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0xA8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0xA8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0xA8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0xA8 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0xA8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0xA8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0xA8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0xA8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xAC "CSI2_CTX3_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xAC 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0xAC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xAC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xB0 "CSI2_CTX4_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xB0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0xB0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0xB0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xB0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0xB0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0xB0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0xB0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0xB0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0xB0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0xB0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xB0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xB0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xB0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xB4 "CSI2_CTX4_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xB4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xB4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xB4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xB4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xB4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xB4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xB8 "CSI2_CTX4_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xB8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xB8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xBC "CSI2_CTX4_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xBC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xBC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC0 "CSI2_CTX4_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xC0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xC0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC4 "CSI2_CTX4_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xC4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0xC4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xC4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xC8 "CSI2_CTX4_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC8 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xC8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0xC8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0xC8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0xC8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0xC8 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xC8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0xC8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0xC8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0xC8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xCC "CSI2_CTX4_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xCC 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xCC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xCC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xD0 "CSI2_CTX5_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xD0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0xD0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xD0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xD0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xD0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xD0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xD0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xD0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xD0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xD0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xD0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xD0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xD0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xD4 "CSI2_CTX5_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xD4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xD4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xD4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xD4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xD4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xD4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xD8 "CSI2_CTX5_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xD8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xD8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xDC "CSI2_CTX5_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xDC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xDC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE0 "CSI2_CTX5_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xE0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xE0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE4 "CSI2_CTX5_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xE4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0xE4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xE4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xE8 "CSI2_CTX5_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE8 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0xE8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0xE8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0xE8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0xE8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0xE8 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0xE8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0xE8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0xE8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0xE8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xEC "CSI2_CTX5_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xEC 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0xEC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0xEC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xF0 "CSI2_CTX6_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xF0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0xF0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xF0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xF0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xF0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0xF0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xF0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xF0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xF0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xF0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0xF0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xF0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xF0 2. "VP_FORCE,RESERVE FIELD" "0,1"
newline
bitfld.long 0xF0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xF0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xF4 "CSI2_CTX6_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xF4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xF4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xF4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xF4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xF4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xF4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xF8 "CSI2_CTX6_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xF8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xF8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xFC "CSI2_CTX6_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xFC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xFC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x100 "CSI2_CTX6_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x100 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x100 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x104 "CSI2_CTX6_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x104 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x104 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x104 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x104 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x104 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x104 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x108 "CSI2_CTX6_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x108 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x108 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x108 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x108 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x108 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x108 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x108 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x108 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x108 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x108 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x10C "CSI2_CTX6_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x10C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x10C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x10C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x110 "CSI2_CTX7_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x110 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x110 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x110 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x110 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x110 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x110 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x110 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x110 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x110 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x110 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x110 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x110 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x110 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x110 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x110 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x114 "CSI2_CTX7_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x114 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x114 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x114 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x114 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x114 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
newline
abitfld.long 0x114 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x118 "CSI2_CTX7_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x118 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x118 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x11C "CSI2_CTX7_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x11C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x11C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x120 "CSI2_CTX7_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x120 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x120 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x124 "CSI2_CTX7_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x124 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x124 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x124 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x124 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x128 "CSI2_CTX7_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x128 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x128 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x128 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x128 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x128 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x128 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x128 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x128 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x128 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x128 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x12C "CSI2_CTX7_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x12C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x12C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x12C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x130 "CSI2_PHY_CFG_REG0,"
hexmask.long.byte 0x130 24.--31. 1. "HS_CLK_CONFIG,Disable clock missing detector"
newline
hexmask.long.byte 0x130 16.--23. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x130 8.--15. 1. "THS_TERM,Ths-term timing parameter in multiples of DDR clock"
newline
hexmask.long.byte 0x130 0.--7. 1. "THS_SETTLE,THS-SETTLE timing parameter in multiples on DDR clock frequency"
line.long 0x134 "CSI2_PHY_CFG_REG1,"
bitfld.long 0x134 30.--31. "RSVD2,Reserved" "0,1,2,3"
newline
rbitfld.long 0x134 29. "RESETDONECTRLCLK,RESETDONECTRLCLK" "0,1"
newline
rbitfld.long 0x134 28. "RESETDONERXBYTECLK,RESETDONERXBYTECLK" "0,1"
newline
bitfld.long 0x134 26.--27. "RSVD1,Reserved" "0,1,2,3"
newline
rbitfld.long 0x134 25. "CLK_MISS_DET," "0,1"
newline
hexmask.long.byte 0x134 18.--24. 1. "TCLK_TERM,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + TCLK_TERM + ~ (1-15) ns Programmed value = ceil(9.5.."
newline
hexmask.long.byte 0x134 10.--17. 1. "D_PHY_HS_SYNC_PAT,DPHY mode HS sync pattern in byte order (reverse of RW 0xB8 received order) D-PHY mode sync pattern"
newline
bitfld.long 0x134 8.--9. "CTRLCLK_DIV_FACT,Divide factor for CTRLCLK for CLKMISS detector" "0,1,2,3"
newline
hexmask.long.byte 0x134 0.--7. 1. "TCLK_SETTLE,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~(1-2)* CTRLCLK + Tclk-settle + ~ (1 -15) ns Programmed value = max[3 ceil(155.."
line.long 0x138 "CSI2_PHY_CFG_REG2,"
bitfld.long 0x138 30.--31. "RXTRIGGERESC0,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "0,1,2,3"
newline
bitfld.long 0x138 28.--29. "RXTRIGGERESC1,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "0,1,2,3"
newline
bitfld.long 0x138 26.--27. "RXTRIGGERESC2,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2" "0,1,2,3"
newline
bitfld.long 0x138 24.--25. "RXTRIGGERESC3,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "0,1,2,3"
newline
hexmask.long.tbyte 0x138 0.--23. 1. "CCP2_SYNC_PAT,CCP2 mode sync pattern in byte order (reverse of received order)"
line.long 0x13C "CSI2_PHY_CFG_REG3,"
bitfld.long 0x13C 31. "OVR_ENHSRX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 26.--30. "ENHSRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 25. "OVR_ENRXTERM,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 20.--24. "ENRXTERM,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 19. "OVR_ENLPRX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 14.--18. "ENLPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 9.--13. "ENULPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 8. "OVR_ENLDO,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 7. "ENLDO,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 6. "OVR_ENBIAS,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 5. "ENBIAS,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 4. "OVR_ENCCP_TO_ANAT,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 3. "OVR_ENCCP_TO_HSRX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 2. "RSVD1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 1. "RECAL_HS_RX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 0. "RECAL_BIAS,RESERVE FIELD" "0,1"
line.long 0x140 "CSI2_PHY_CFG_REG4,"
bitfld.long 0x140 27.--31. "TRIM_BIAS_GEN,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 22.--26. "TRIM_TERM_LANE4,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 17.--21. "TRIM_TERM_LANE3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 12.--16. "TRIM_TERM_LANE2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 7.--11. "TRIM_TERM_LANE1,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 2.--6. "TRIM_TERM_LANE0,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 1. "BYPASS_EFUSE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x140 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x144 "CSI2_PHY_CFG_REG5,"
bitfld.long 0x144 26.--31. "TRIM_OFFSET_LANE4_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 20.--25. "TRIM_OFFSET_LANE3_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 14.--19. "TRIM_OFFSET_LANE2_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 8.--13. "TRIM_OFFSET_LANE1_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 2.--7. "TRIM_OFFSET_LANE0_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 1. "BYPASS_CALIB_OFFSET,RESERVE FIELD" "0,1"
newline
bitfld.long 0x144 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x148 "CSI2_PHY_CFG_REG6,"
hexmask.long.word 0x148 21.--31. 1. "RSVD2,RESERVE FIELD"
newline
bitfld.long 0x148 20. "OVR_AFE_LANE_ADR_POL,RESERVE FIELD" "0,1"
newline
hexmask.long.byte 0x148 12.--19. 1. "AFE_LANE_SEL,RESERVE FIELD"
newline
bitfld.long 0x148 11. "AFE_LANE_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 10. "HSCOMOOUT,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 9. "BYPASS_LDO_REG,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 8. "OBSV_LDO_VOLT_DYA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 7. "OBSV_BIAS_CURR_DXA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 6. "RSVD1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 5. "BIASGEN_CAL_OVR,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 0.--4. "BIASGEN_CAL_OVR_VAL,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C0++0x3F
line.long 0x00 "CSI2_CTX0_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x00 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x00 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x04 "CSI2_CTX0_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x04 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x04 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x08 "CSI2_CTX1_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x08 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x08 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x0C "CSI2_CTX1_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x0C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x0C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x10 "CSI2_CTX2_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x10 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x10 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x14 "CSI2_CTX2_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x14 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x14 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x18 "CSI2_CTX3_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x18 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x18 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x1C "CSI2_CTX3_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x1C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x1C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x20 "CSI2_CTX4_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x20 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x20 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x24 "CSI2_CTX4_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x24 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x24 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x28 "CSI2_CTX5_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x28 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x28 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x2C "CSI2_CTX5_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x2C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x2C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x30 "CSI2_CTX6_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x30 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x30 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x34 "CSI2_CTX6_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x34 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x34 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x38 "CSI2_CTX7_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x38 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x38 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x3C "CSI2_CTX7_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x3C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x3C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
width 0x0B
tree.end
tree "RCSS_CTRL (RCSS Control Module Registers)"
base ad:0x55020000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x257
line.long 0x00 "RCSS_TPCC_A_ERRAGG_MASK,"
bitfld.long 0x00 26. "tptc_a1_read_access_error,Mask Error from RCSS_TPTC_A1 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 25. "tptc_a0_read_access_error,Mask Error from RCSS_TPTC_A0 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 24. "tpcc_a_read_access_error,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 18. "tptc_a1_write_access_error,Mask Error from RCSS_TPTC_A1 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 17. "tptc_a0_write_access_error,Mask Error from RCSS_TPTC_A0 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 16. "tpcc_a_write_access_error,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 8. "tpcc_a_parity_err,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 3. "tptc_a1_err,Mask Error from RCSS_TPTC_A1 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 2. "tptc_a0_err,Mask Error from RCSS_TPTC_A0 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 1. "tpcc_a_mpint,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 0. "tpcc_a_errint,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x04 "RCSS_TPCC_A_ERRAGG_STATUS,"
bitfld.long 0x04 26. "tptc_a1_read_access_error,Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x04 25. "tptc_a0_read_access_error,Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x04 24. "tpcc_a_read_access_error,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 18. "tptc_a1_write_access_error,Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x04 17. "tptc_a0_write_access_error,Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x04 16. "tpcc_a_write_access_error,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 8. "tpcc_a_parity_err,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 3. "tptc_a1_err,Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x04 2. "tptc_a0_err,Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x04 1. "tpcc_a_mpint,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 0. "tpcc_a_errint,Status of Error from RCSS_TPCC_A" "0,1"
line.long 0x08 "RCSS_TPCC_A_ERRAGG_STATUS_RAW,"
bitfld.long 0x08 26. "tptc_a1_read_access_error,Raw Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 25. "tptc_a0_read_access_error,Raw Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 24. "tpcc_a_read_access_error,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 18. "tptc_a1_write_access_error,Raw Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 17. "tptc_a0_write_access_error,Raw Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 16. "tpcc_a_write_access_error,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 8. "tpcc_a_parity_err,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 3. "tptc_a1_err,Raw Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 2. "tptc_a0_err,Raw Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 1. "tpcc_a_mpint,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 0. "tpcc_a_errint,Raw Status of Error from RCSS_TPCC_A" "0,1"
line.long 0x0C "RCSS_TPCC_A_INTAGG_MASK,"
bitfld.long 0x0C 17. "tptc_a1,Mask Interrupt from TPTC A1 to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 16. "tptc_a0,Mask Interrupt from TPTC A0 to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 8. "tpcc_a_int7,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 7. "tpcc_a_int6,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 6. "tpcc_a_int5,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 5. "tpcc_a_int4,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 4. "tpcc_a_int3,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 3. "tpcc_a_int2,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 2. "tpcc_a_int1,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 1. "tpcc_a_int0,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 0. "tpcc_a_intg,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x10 "RCSS_TPCC_A_INTAGG_STATUS,"
bitfld.long 0x10 17. "tptc_a1,Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x10 16. "tptc_a0,Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x10 8. "tpcc_a_int7,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 7. "tpcc_a_int6,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 6. "tpcc_a_int5,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 5. "tpcc_a_int4,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 4. "tpcc_a_int3,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 3. "tpcc_a_int2,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 2. "tpcc_a_int1,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 1. "tpcc_a_int0,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 0. "tpcc_a_intg,Status of Interrupt from RCSS_TPCC_A" "0,1"
line.long 0x14 "RCSS_TPCC_A_INTAGG_STATUS_RAW,"
bitfld.long 0x14 17. "tptc_a1,Raw Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x14 16. "tptc_a0,Raw Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x14 8. "tpcc_a_int7,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 7. "tpcc_a_int6,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 6. "tpcc_a_int5,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 5. "tpcc_a_int4,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 4. "tpcc_a_int3,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 3. "tpcc_a_int2,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 2. "tpcc_a_int1,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 1. "tpcc_a_int0,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 0. "tpcc_a_intg,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
line.long 0x18 "RCSS_SPI_TRIG_SRC,"
hexmask.long.word 0x18 16.--27. 1. "trig_spib,Trigger sources for RCSS SPIB"
newline
hexmask.long.word 0x18 0.--11. 1. "trig_spia,Trigger sources for RCSS SPIA"
line.long 0x1C "RCSS_SPIA_MEMINIT,"
bitfld.long 0x1C 0. "mem0_init,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x20 "RCSS_SPIA_MEMINIT_DONE,"
bitfld.long 0x20 0. "mem0_done,Status field" "0,1"
line.long 0x24 "RCSS_SPIA_MEMINIT_STATUS,"
bitfld.long 0x24 0. "mem0_status,Status field" "0,1"
line.long 0x28 "RCSS_SPIB_MEMINIT,"
bitfld.long 0x28 0. "mem0_init,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x2C "RCSS_SPIB_MEMINIT_DONE,"
bitfld.long 0x2C 0. "mem0_done,Status field" "0,1"
line.long 0x30 "RCSS_SPIB_MEMINIT_STATUS,"
bitfld.long 0x30 0. "mem0_status,Status field" "0,1"
line.long 0x34 "RCSS_TPCC_MEMINIT_START,"
bitfld.long 0x34 0. "tpcc_a_meminit_start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x38 "RCSS_TPCC_MEMINIT_DONE,"
bitfld.long 0x38 0. "tpcc_a_meminit_done,Status field" "0,1"
line.long 0x3C "RCSS_TPCC_MEMINIT_STATUS,"
bitfld.long 0x3C 0. "tpcc_a_meminit_status,Status field" "0,1"
line.long 0x40 "RCSS_SPIA_CFG,"
bitfld.long 0x40 24. "spia_int_trig_polarity,Trigger source polarity select" "Polarity 0,Polarity 1"
newline
bitfld.long 0x40 16. "spia_trig_gate_en,Trigger Gate Enable" "0,1"
newline
bitfld.long 0x40 8. "spia_cs_trigsrc_en,Chip Select Trigger SRC enable Wrie 0x1 to Use CS as trigger source" "0,1"
newline
bitfld.long 0x40 0.--2. "spiasync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x44 "RCSS_SPIB_CFG,"
bitfld.long 0x44 24. "spib_int_trig_polarity,Trigger source polarity select" "Polarity 0,Polarity 1"
newline
bitfld.long 0x44 16. "spib_trig_gate_en,Trigger Gate Enable" "0,1"
newline
bitfld.long 0x44 8. "spib_cs_trigsrc_en,Chip Select Trigger SRC enable Wrie 0x1 to Use CS as trigger source" "0,1"
newline
bitfld.long 0x44 0.--2. "spibsync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x48 "RCSS_SPIA_IOCFG,"
bitfld.long 0x48 16.--18. "miso_oen_by_cs,SPI MISO Output Enable Control based on Chip select CS" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
newline
bitfld.long 0x48 8.--10. "cs_pol,SPI CS polarity-slave mode" "Active low,Active high,?..."
newline
bitfld.long 0x48 0.--2. "cs_deact,Chip Select Deactivate" "0,1,2,3,4,5,6,7"
line.long 0x4C "RCSS_SPIB_IOCFG,"
bitfld.long 0x4C 16.--18. "miso_oen_by_cs,SPI MISO Output Enable Control based on Chip select CS" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
newline
bitfld.long 0x4C 8.--10. "cs_pol,SPI CS polarity-slave mode" "Active low,Active high,?..."
newline
bitfld.long 0x4C 0.--2. "cs_deact,Chip Select Deactivate" "0,1,2,3,4,5,6,7"
line.long 0x50 "RCSS_SPI_HOST_IRQ,"
bitfld.long 0x50 0.--2. "host_irq,TI internal reserved for R&D" "0,1,2,3,4,5,6,7"
line.long 0x54 "TPTC_DBS_CFG,"
bitfld.long 0x54 2.--3. "tptc_a1,Max Burst size tieoff value for TPTC A1" "0,1,2,3"
newline
bitfld.long 0x54 0.--1. "tptc_a0,Max Burst size tieoff value for TPTC A0" "0,1,2,3"
line.long 0x58 "RCSS_TPCC_A_PARITY_CTRL,"
bitfld.long 0x58 2. "parity_err_clr,Write pulse bit field: Write 0x1 to clear the Parit Error status for TPCC" "0,1"
newline
bitfld.long 0x58 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
newline
bitfld.long 0x58 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x5C "RCSS_TPCC_A_PARITY_STATUS,"
hexmask.long.byte 0x5C 8.--15. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x60 "RCSS_CSI2A_CFG,"
bitfld.long 0x60 28.--30. "sof_intr1_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2A_SOF_INT1" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x60 24.--26. "sof_intr0_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2A_SOF_INT0" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x60 20.--22. "eof_intr1_sel,Select the End of Frame Contx to be sent as RCSS_CSI2A_EOF_INT1" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x60 17.--19. "eof_intr0_sel,Select the End of Frame Contx to be sent as RCSS_CSI2A_EOF_INT0" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x60 16. "sign_ext_en,Sign Extention Enable for CSI2 A" "0,1"
newline
bitfld.long 0x60 8. "mwait,Power Idle Protocol related Mwait Port" "0,1"
newline
bitfld.long 0x60 0.--4. "lane_enable,Lane enable for CSI2 A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "RCSS_CSI2B_CFG,"
bitfld.long 0x64 28.--30. "sof_intr1_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2B_SOF_INT1" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x64 24.--26. "sof_intr0_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2B_SOF_INT0" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x64 20.--22. "eof_intr1_sel,Select the End of Frame Contx to be sent as RCSS_CSI2B_EOF_INT1" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x64 17.--19. "eof_intr0_sel,Select the End of Frame Contx to be sent as RCSS_CSI2B_EOF_INT0" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x64 16. "sign_ext_en,Sign Extention Enable for CSI2 B" "0,1"
newline
bitfld.long 0x64 8. "mwait,Power Idle Protocol related Mwait Port" "0,1"
newline
bitfld.long 0x64 0.--4. "lane_enable,Lane enable for CSI2 B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x68 "RCSS_CSI2A_CTX0_LINE_PING_PONG,"
bitfld.long 0x68 16. "enable,Enable line based ping pong toggle for Context 0" "Diabled,Enabled"
newline
hexmask.long.word 0x68 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 0"
line.long 0x6C "RCSS_CSI2A_CTX1_LINE_PING_PONG,"
bitfld.long 0x6C 16. "enable,Enable line based ping pong toggle for Context 1" "Diabled,Enabled"
newline
hexmask.long.word 0x6C 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 1"
line.long 0x70 "RCSS_CSI2A_CTX2_LINE_PING_PONG,"
bitfld.long 0x70 16. "enable,Enable line based ping pong toggle for Context 2" "Diabled,Enabled"
newline
hexmask.long.word 0x70 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 2"
line.long 0x74 "RCSS_CSI2A_CTX3_LINE_PING_PONG,"
bitfld.long 0x74 16. "enable,Enable line based ping pong toggle for Context 3" "Diabled,Enabled"
newline
hexmask.long.word 0x74 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 3"
line.long 0x78 "RCSS_CSI2A_CTX4_LINE_PING_PONG,"
bitfld.long 0x78 16. "enable,Enable line based ping pong toggle for Context 4" "Diabled,Enabled"
newline
hexmask.long.word 0x78 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 4"
line.long 0x7C "RCSS_CSI2A_CTX5_LINE_PING_PONG,"
bitfld.long 0x7C 16. "enable,Enable line based ping pong toggle for Context 5" "Diabled,Enabled"
newline
hexmask.long.word 0x7C 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 5"
line.long 0x80 "RCSS_CSI2A_CTX6_LINE_PING_PONG,"
bitfld.long 0x80 16. "enable,Enable line based ping pong toggle for Context 6" "Diabled,Enabled"
newline
hexmask.long.word 0x80 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 6"
line.long 0x84 "RCSS_CSI2A_CTX7_LINE_PING_PONG,"
bitfld.long 0x84 16. "enable,Enable line based ping pong toggle for Context 7" "Diabled,Enabled"
newline
hexmask.long.word 0x84 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 7"
line.long 0x88 "RCSS_CSI2A_PARITY_CTRL,"
bitfld.long 0x88 16. "fifo_parity_en,Enable Parity for CSI2 FIFO Memory" "0,1"
newline
bitfld.long 0x88 0. "ctx_parity_en,Enable Parity for CSI2 CTX Memory" "0,1"
line.long 0x8C "RCSS_CSI2A_PARITY_STATUS,"
hexmask.long.byte 0x8C 16.--22. 1. "fifo_parity_addr,CSI2 FIFO Memory Error Address at which Parity Error occurred"
newline
bitfld.long 0x8C 0.--3. "ctx_parity_addr,CSI2 CTX Memory Error Address at which Parity Error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "RCSS_CSI2B_CTX0_LINE_PING_PONG,"
bitfld.long 0x90 16. "enable,Enable line based ping pong toggle for Context 0" "Diabled,Enabled"
newline
hexmask.long.word 0x90 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 0"
line.long 0x94 "RCSS_CSI2B_CTX1_LINE_PING_PONG,"
bitfld.long 0x94 16. "enable,Enable line based ping pong toggle for Context 1" "Diabled,Enabled"
newline
hexmask.long.word 0x94 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 1"
line.long 0x98 "RCSS_CSI2B_CTX2_LINE_PING_PONG,"
bitfld.long 0x98 16. "enable,Enable line based ping pong toggle for Context 2" "Diabled,Enabled"
newline
hexmask.long.word 0x98 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 2"
line.long 0x9C "RCSS_CSI2B_CTX3_LINE_PING_PONG,"
bitfld.long 0x9C 16. "enable,Enable line based ping pong toggle for Context 3" "Diabled,Enabled"
newline
hexmask.long.word 0x9C 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 3"
line.long 0xA0 "RCSS_CSI2B_CTX4_LINE_PING_PONG,"
bitfld.long 0xA0 16. "enable,Enable line based ping pong toggle for Context 4" "Diabled,Enabled"
newline
hexmask.long.word 0xA0 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 4"
line.long 0xA4 "RCSS_CSI2B_CTX5_LINE_PING_PONG,"
bitfld.long 0xA4 16. "enable,Enable line based ping pong toggle for Context 5" "Diabled,Enabled"
newline
hexmask.long.word 0xA4 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 5"
line.long 0xA8 "RCSS_CSI2B_CTX6_LINE_PING_PONG,"
bitfld.long 0xA8 16. "enable,Enable line based ping pong toggle for Context 6" "Diabled,Enabled"
newline
hexmask.long.word 0xA8 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 6"
line.long 0xAC "RCSS_CSI2B_CTX7_LINE_PING_PONG,"
bitfld.long 0xAC 16. "enable,Enable line based ping pong toggle for Context 7" "Diabled,Enabled"
newline
hexmask.long.word 0xAC 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 7"
line.long 0xB0 "RCSS_CSI2B_PARITY_CTRL,"
bitfld.long 0xB0 16. "fifo_parity_en,Enable Parity for CSI2 FIFO Memory" "0,1"
newline
bitfld.long 0xB0 0. "ctx_parity_en,Enable Parity for CSI2 CTX Memory" "0,1"
line.long 0xB4 "RCSS_CSI2B_PARITY_STATUS,"
hexmask.long.byte 0xB4 16.--22. 1. "fifo_parity_addr,CSI2 FIFO Memory Error Address at which Parity Error occurred"
newline
bitfld.long 0xB4 0.--3. "ctx_parity_addr,CSI2 CTX Memory Error Address at which Parity Error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "RCSS_CSI2A_LANE0_CFG,"
rbitfld.long 0xB8 19. "dy0_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xB8 18. "dy0_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xB8 17. "dy0_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xB8 16. "dy0_in,Pad DY Input" "0,1"
newline
bitfld.long 0xB8 15. "dy0_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xB8 14. "dy0_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xB8 13. "dx0_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xB8 12. "dx0_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xB8 11. "dx0_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xB8 10. "dx0_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xB8 9. "dx0_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xB8 8. "dx0_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xB8 7. "dx0_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xB8 6. "dx0_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xB8 5. "dx0_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xB8 4. "dx0_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xB8 3. "dx0_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xB8 2. "dx0_in,Pad DX Input" "0,1"
newline
bitfld.long 0xB8 1. "dx0_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xB8 0. "dx0_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xBC "RCSS_CSI2A_LANE1_CFG,"
rbitfld.long 0xBC 19. "dy1_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xBC 18. "dy1_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xBC 17. "dy1_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xBC 16. "dy1_in,Pad DY Input" "0,1"
newline
bitfld.long 0xBC 15. "dy1_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xBC 14. "dy1_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xBC 13. "dx1_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xBC 12. "dx1_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xBC 11. "dx1_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xBC 10. "dx1_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xBC 9. "dx1_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xBC 8. "dx1_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xBC 7. "dx1_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xBC 6. "dx1_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xBC 5. "dx1_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xBC 4. "dx1_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xBC 3. "dx1_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xBC 2. "dx1_in,Pad DX Input" "0,1"
newline
bitfld.long 0xBC 1. "dx1_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xBC 0. "dx1_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xC0 "RCSS_CSI2A_LANE2_CFG,"
rbitfld.long 0xC0 19. "dy2_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xC0 18. "dy2_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xC0 17. "dy2_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC0 16. "dy2_in,Pad DY Input" "0,1"
newline
bitfld.long 0xC0 15. "dy2_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xC0 14. "dy2_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xC0 9. "dx2_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xC0 8. "dx2_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xC0 7. "dx2_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xC0 6. "dx2_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xC0 5. "dx2_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xC0 4. "dx2_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xC0 3. "dx2_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC0 2. "dx2_in,Pad DX Input" "0,1"
newline
bitfld.long 0xC0 1. "dx2_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xC0 0. "dx2_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xC4 "RCSS_CSI2A_LANE3_CFG,"
rbitfld.long 0xC4 19. "dy3_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xC4 18. "dy3_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xC4 17. "dy3_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC4 16. "dy3_in,Pad DY Input" "0,1"
newline
bitfld.long 0xC4 15. "dy3_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xC4 14. "dy3_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xC4 13. "dx3_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xC4 12. "dx3_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xC4 11. "dx3_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xC4 10. "dx3_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xC4 9. "dx3_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xC4 8. "dx3_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xC4 7. "dx3_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xC4 6. "dx3_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xC4 5. "dx3_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xC4 4. "dx3_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xC4 3. "dx3_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC4 2. "dx3_in,Pad DX Input" "0,1"
newline
bitfld.long 0xC4 1. "dx3_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xC4 0. "dx3_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xC8 "RCSS_CSI2A_LANE4_CFG,"
rbitfld.long 0xC8 19. "dy4_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xC8 18. "dy4_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xC8 17. "dy4_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC8 16. "dy4_in,Pad DY Input" "0,1"
newline
bitfld.long 0xC8 15. "dy4_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xC8 14. "dy4_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xC8 13. "dx4_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xC8 12. "dx4_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xC8 11. "dx4_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xC8 10. "dx4_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xC8 9. "dx4_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xC8 8. "dx4_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xC8 7. "dx4_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xC8 6. "dx4_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xC8 5. "dx4_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xC8 4. "dx4_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xC8 3. "dx4_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC8 2. "dx4_in,Pad DX Input" "0,1"
newline
bitfld.long 0xC8 1. "dx4_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xC8 0. "dx4_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xCC "RCSS_CSI2B_LANE0_CFG,"
rbitfld.long 0xCC 19. "dy0_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xCC 18. "dy0_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xCC 17. "dy0_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xCC 16. "dy0_in,Pad DY Input" "0,1"
newline
bitfld.long 0xCC 15. "dy0_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xCC 14. "dy0_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xCC 13. "dx0_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xCC 12. "dx0_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xCC 11. "dx0_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xCC 10. "dx0_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xCC 9. "dx0_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xCC 8. "dx0_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xCC 7. "dx0_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xCC 6. "dx0_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xCC 5. "dx0_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xCC 4. "dx0_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xCC 3. "dx0_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xCC 2. "dx0_in,Pad DX Input" "0,1"
newline
bitfld.long 0xCC 1. "dx0_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xCC 0. "dx0_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xD0 "RCSS_CSI2B_LANE1_CFG,"
rbitfld.long 0xD0 19. "dy1_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xD0 18. "dy1_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xD0 17. "dy1_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD0 16. "dy1_in,Pad DY Input" "0,1"
newline
bitfld.long 0xD0 15. "dy1_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xD0 14. "dy1_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xD0 13. "dx1_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xD0 12. "dx1_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xD0 11. "dx1_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xD0 10. "dx1_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xD0 9. "dx1_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xD0 8. "dx1_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xD0 7. "dx1_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xD0 6. "dx1_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xD0 5. "dx1_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xD0 4. "dx1_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xD0 3. "dx1_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD0 2. "dx1_in,Pad DX Input" "0,1"
newline
bitfld.long 0xD0 1. "dx1_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xD0 0. "dx1_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xD4 "RCSS_CSI2B_LANE2_CFG,"
rbitfld.long 0xD4 19. "dy2_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xD4 18. "dy2_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xD4 17. "dy2_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD4 16. "dy2_in,Pad DY Input" "0,1"
newline
bitfld.long 0xD4 15. "dy2_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xD4 14. "dy2_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xD4 9. "dx2_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xD4 8. "dx2_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xD4 7. "dx2_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xD4 6. "dx2_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xD4 5. "dx2_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xD4 4. "dx2_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xD4 3. "dx2_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD4 2. "dx2_in,Pad DX Input" "0,1"
newline
bitfld.long 0xD4 1. "dx2_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xD4 0. "dx2_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xD8 "RCSS_CSI2B_LANE3_CFG,"
rbitfld.long 0xD8 19. "dy3_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xD8 18. "dy3_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xD8 17. "dy3_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD8 16. "dy3_in,Pad DY Input" "0,1"
newline
bitfld.long 0xD8 15. "dy3_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xD8 14. "dy3_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xD8 13. "dx3_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xD8 12. "dx3_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xD8 11. "dx3_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xD8 10. "dx3_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xD8 9. "dx3_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xD8 8. "dx3_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xD8 7. "dx3_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xD8 6. "dx3_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xD8 5. "dx3_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xD8 4. "dx3_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xD8 3. "dx3_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD8 2. "dx3_in,Pad DX Input" "0,1"
newline
bitfld.long 0xD8 1. "dx3_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xD8 0. "dx3_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xDC "RCSS_CSI2B_LANE4_CFG,"
rbitfld.long 0xDC 19. "dy4_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xDC 18. "dy4_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xDC 17. "dy4_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xDC 16. "dy4_in,Pad DY Input" "0,1"
newline
bitfld.long 0xDC 15. "dy4_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xDC 14. "dy4_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xDC 13. "dx4_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xDC 12. "dx4_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xDC 11. "dx4_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xDC 10. "dx4_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xDC 9. "dx4_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xDC 8. "dx4_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xDC 7. "dx4_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xDC 6. "dx4_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xDC 5. "dx4_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xDC 4. "dx4_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xDC 3. "dx4_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xDC 2. "dx4_in,Pad DX Input" "0,1"
newline
bitfld.long 0xDC 1. "dx4_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xDC 0. "dx4_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xE0 "RCSS_CSI2A_FIFO_MEMINIT,"
bitfld.long 0xE0 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0xE4 "RCSS_CSI2A_FIFO_MEMINIT_DONE,"
bitfld.long 0xE4 0. "done,Status field" "0,1"
line.long 0xE8 "RCSS_CSI2A_FIFO_MEMINIT_STATUS,"
bitfld.long 0xE8 0. "status,Status field" "0,1"
line.long 0xEC "RCSS_CSI2A_CTX_MEMINIT,"
bitfld.long 0xEC 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0xF0 "RCSS_CSI2A_CTX_MEMINIT_DONE,"
bitfld.long 0xF0 0. "done,Status field" "0,1"
line.long 0xF4 "RCSS_CSI2A_CTX_MEMINIT_STATUS,"
bitfld.long 0xF4 0. "status,Status field" "0,1"
line.long 0xF8 "RCSS_CSI2B_FIFO_MEMINIT,"
bitfld.long 0xF8 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0xFC "RCSS_CSI2B_FIFO_MEMINIT_DONE,"
bitfld.long 0xFC 0. "done,Status field" "0,1"
line.long 0x100 "RCSS_CSI2B_FIFO_MEMINIT_STATUS,"
bitfld.long 0x100 0. "status,Status field" "0,1"
line.long 0x104 "RCSS_CSI2B_CTX_MEMINIT,"
bitfld.long 0x104 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x108 "RCSS_CSI2B_CTX_MEMINIT_DONE,"
bitfld.long 0x108 0. "done,Status field" "0,1"
line.long 0x10C "RCSS_CSI2B_CTX_MEMINIT_STATUS,"
bitfld.long 0x10C 0. "status,Status field" "0,1"
line.long 0x110 "RCSS_BUS_SAFETY_CTRL,"
bitfld.long 0x110 4.--6. "clk_disable,Option to clock gate the safety infrastructure is Safety is disabled" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x110 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x114 "RCSS_BUS_SAFETY_SEC_ERR_STAT0,"
bitfld.long 0x114 9. "RCSS_TPTC_A1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 8. "RCSS_TPTC_A0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 7. "RCSS_TPTC_A1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 6. "RCSS_TPTC_A0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 5. "RCSS_MCASPC,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 4. "RCSS_MCASPB,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 3. "RCSS_MCASPA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 2. "RCSS_PCR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 1. "RCSS_CSI2B_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 0. "RCSS_CSI2A_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x118 "RCSS_TPTCA0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x118 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x118 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x118 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x11C "RCSS_TPTCA0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x11C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x11C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x11C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x11C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x120 "RCSS_TPTCA0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x120 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x120 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x120 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x120 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x124 "RCSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x124 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x124 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x128 "RCSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x12C "RCSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x130 "RCSS_TPTCA1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x130 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x130 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x130 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x134 "RCSS_TPTCA1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x134 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x134 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x134 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x134 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x138 "RCSS_TPTCA1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x138 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x138 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x138 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x138 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x13C "RCSS_TPTCA1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x13C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x13C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x140 "RCSS_TPTCA1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x144 "RCSS_TPTCA1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x148 "RCSS_TPTCA0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x148 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x148 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x148 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14C "RCSS_TPTCA0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x14C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x150 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x150 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x150 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x150 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x150 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x154 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x154 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x154 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x158 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x15C "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x160 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x164 "RCSS_TPTCA1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x164 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x164 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x164 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x168 "RCSS_TPTCA1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x168 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x168 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x168 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x168 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x16C "RCSS_TPTCA1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x16C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x16C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x16C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x16C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x170 "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x170 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x170 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x174 "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x178 "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x17C "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x180 "RCSS_CSI2A_MDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x180 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x180 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x180 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x184 "RCSS_CSI2A_MDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x184 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x184 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x184 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x184 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x188 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x188 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x188 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x188 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x188 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x18C "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x18C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x190 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x194 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x198 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x19C "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1A0 "RCSS_CSI2B_MDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1A0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1A4 "RCSS_CSI2B_MDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x1A4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1A8 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1A8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1AC "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1AC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B0 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1B4 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1B8 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1BC "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1C0 "RCSS_PCR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1C0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "RCSS_PCR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1C4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1C8 "RCSS_PCR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1C8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1CC "RCSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1CC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1CC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1D0 "RCSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1D4 "RCSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1D8 "RCSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1DC "RCSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1E0 "RCSS_MCASPA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1E0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1E4 "RCSS_MCASPA_BUS_SAFETY_FI,"
hexmask.long.byte 0x1E4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1E8 "RCSS_MCASPA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1E8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1EC "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1EC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1F0 "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1F4 "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1F8 "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1FC "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x200 "RCSS_MCASPB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x200 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x200 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x200 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x204 "RCSS_MCASPB_BUS_SAFETY_FI,"
hexmask.long.byte 0x204 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x204 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x208 "RCSS_MCASPB_BUS_SAFETY_ERR,"
hexmask.long.byte 0x208 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x20C "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x20C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x210 "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x214 "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x218 "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x21C "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x220 "RCSS_MCASPC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x220 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x220 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x224 "RCSS_MCASPC_BUS_SAFETY_FI,"
hexmask.long.byte 0x224 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x224 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x228 "RCSS_MCASPC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x228 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x22C "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x22C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x22C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x230 "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x234 "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x238 "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x23C "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x240 "RCSS_SCIA_CTRL,"
bitfld.long 0x240 4. "DMA_RX_CLR,RCSS_SCIA RX DMA Clear" "0,1"
newline
bitfld.long 0x240 0. "DMA_TX_CLR,RCSS_SCIA TX DMA Clear" "0,1"
line.long 0x244 "RCSS_GIO_CFG,"
line.long 0x248 "RCSS_TPTC_BOUNDARY_CFG,"
bitfld.long 0x248 8.--13. "tptc_a1_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x248 0.--5. "tptc_a0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24C "RCSS_TPTC_XID_REORDER_CFG,"
bitfld.long 0x24C 8. "tptc_a1_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
newline
bitfld.long 0x24C 0. "tptc_a0_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
line.long 0x250 "DBG_ACK_CPU_CTRL,"
bitfld.long 0x250 0. "sel,Select the Processor Suspend that is used to Suspend the DSS Peripehrals" "DSP,MSS CR5"
line.long 0x254 "DBG_ACK_CTL0,"
bitfld.long 0x254 8.--10. "RCSS_ECAP,Enable Suspend of the peripheral" "Peripheral not suspended,Peripehal Suspended,?..."
newline
bitfld.long 0x254 4.--6. "RCSS_I2CB,Enable Suspend of the peripheral" "Peripheral not suspended,Peripehal Suspended,?..."
newline
bitfld.long 0x254 0.--2. "RCSS_I2CA,Enable Suspend of the peripheral" "Peripheral not suspended,Peripehal Suspended,?..."
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
width 0x0B
tree.end
tree "RCSS_ECAP (RCSS ECAP Module Registers)"
base ad:0x55F79C00
group.long 0x00++0x17
line.long 0x00 "TSCTR,Time-Stamp Counter"
line.long 0x04 "CTRPHS,Counter Phase Offset Value Register"
line.long 0x08 "CAP1,Capture 1 Register"
line.long 0x0C "CAP2,Capture 2 Register"
line.long 0x10 "CAP3,Capture 3 Register"
line.long 0x14 "CAP4,Capture 4 Register"
group.long 0x24++0x0F
line.long 0x00 "ECCTL0,Capture Control Register 0"
hexmask.long 0x00 7.--31. 1. "NU_1,Reserved"
hexmask.long.byte 0x00 0.--6. 1. "INPUTSEL,Capture input source select bits[[br]]0000000 capture input is ECAPxINPUT[0] [[br]]0000001 capture input is ECAPxINPUT[1] [[br]]0000010 capture input is ECAPxINPUT[2][[br]]"
line.long 0x04 "ECCTL1_ECCTL2,Capture Control Register 1 & Capture Control Register 2"
rbitfld.long 0x04 30.--31. "MODCNTRSTS,This bit field reads current status on modulo counter[[br]]00b (R) = CAP1 register gets loaded on next capture event.[[br]]01b (R) = CAP2 register gets loaded on next capture event.[[br]]10b (R) = CAP3 register gets loaded on next capture.." "0,1,2,3"
bitfld.long 0x04 28.--29. "DMAEVTSEL,DMA event select[[br]]00b (R/W) = DMA interrupt source is CEVT1[[br]]01b (R/W) = DMA interrupt source is CEVT2[[br]]10b (R/W) = DMA interrupt source is CEVT3[[br]]11b (R/W) = DMA interrupt source is CEVT4" "0,1,2,3"
bitfld.long 0x04 27. "CTRFILTRESET,Reset Bit[[br]]0h (R) = No effect[[br]]1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags[[br]] [[br]]Note: This provides an ability start capture module from known state in case spurious inputs.." "0,1"
bitfld.long 0x04 26. "APWMPOL,APWM output polarity select" "0,1"
newline
bitfld.long 0x04 25. "CAP_APWM,CAP/APWM operating mode select 0 ECAP_MODULE ECAP module operates in capture mode" "0,1"
bitfld.long 0x04 24. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer" "0,1"
bitfld.long 0x04 22.--23. "SYNCO_SEL,Sync-Out Select 0x0 SWSYNC sync out signal is SWSYNC 0x1 ECAP_CTR_PRD_TO_SYNCOUT Select CTR = PRD event to be the sync-out signal 0x2 ECAP_DISABLE_SYNC_OUT Disable sync out signal 0x3 ECAP_DISABLE_SYNC_OUT Disable sync out signal" "0,1,2,3"
bitfld.long 0x04 21. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 ECAP_DISABLE_SYNC_IN Disable sync-in option 1 ECAP_ENABLE_COUNTER_REGISTER Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event" "0,1"
newline
bitfld.long 0x04 20. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 ECAP_TSCTR_STOPPED TSCTR stopped 1 ECAP_TSCTR_FREE_RUNNING TSCTR free-running" "0,1"
bitfld.long 0x04 19. "REARM,Re-Arming Control" "0,1"
bitfld.long 0x04 17.--18. "STOP_WRAP,Stop value for one-shot mode" "0,1,2,3"
bitfld.long 0x04 16. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 ECAP_OPP_CONT Operate in continuous mode 1 ECAP_OPP_ONE Operate in one-Shot mode" "0,1"
newline
bitfld.long 0x04 14.--15. "FREE_SOFT,Emulation Control" "ECAP_STOP_EMU TSCTR counter stops immediately on..,ECAP_RUNS_UNTIL TSCTR counter runs until = 0,ECAP_UNAF_EMU_SUS TSCTR counter is unaffected by..,ECAP_UNAF_EMU_SUS2 TSCTR counter is unaffected.."
bitfld.long 0x04 9.--13. "PRESCALE,Event Filter prescale select 0x00 ECAP_DIV1 Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 ECAP_DIV2 Divide by 2 0x02 ECAP_DIV4 Divide by 4 0x03 ECAP_DIV6 Divide by 6 0x04 ECAP_DIV8 Divide by 8 0x05 ECAP_DIV10 Divide by 10 0x1E.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event" "0,1"
bitfld.long 0x04 7. "CTRRST4,Counter Reset on Capture Event 4 0 ECAP_DO_NOT_RESET_EVENT4 Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 ECAP_RESET_EVENT4 Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode.." "0,1"
newline
bitfld.long 0x04 6. "CAP4POL,Capture Event 4 Polarity select 0 ECAP_CAP_EVENT4_RISE Capture Event 4 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT4_FALL Capture Event 4 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x04 5. "CTRRST3,Counter Reset on Capture Event 3 0 ECAP_DO_NOT_RESET_EVENT3 Do not reset counter on Capture Event 3 (absolute time stamp) 1 ECAP_RESET_EVENT3 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x04 4. "CAP3POL,Capture Event 3 Polarity select 0 ECAP_CAP_EVENT3_RISE Capture Event 3 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT3_FALL Capture Event 3 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x04 3. "CTRRST2,Counter Reset on Capture Event 2 0 ECAP_DO_NOT_RESET_EVENT2 Do not reset counter on Capture Event 2 (absolute time stamp) 1 ECAP_RESET_EVENT2 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1"
newline
bitfld.long 0x04 2. "CAP2POL,Capture Event 2 Polarity select 0 ECAP_CAP_EVENT2_RISE Capture Event 2 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT2_FALL Capture Event 2 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x04 1. "CTRRST1,Counter Reset on Capture Event 1 0 ECAP_DO_NOT_RESET_EVENT1 Do not reset counter on Capture Event 1 (absolute time stamp) 1 ECAP_RESET_EVENT1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x04 0. "CAP1POL,Capture Event 1 Polarity select 0 ECAP_CAP_EVENT1_RISE Capture Event 1 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT1_FALL Capture Event 1 triggered on a falling edge (FE)" "0,1"
line.long 0x08 "ECEINT_ECFLG,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt"
hexmask.long.byte 0x08 25.--31. 1. "NU_4,Reserved"
rbitfld.long 0x08 24. "HRERROR_FLG,High resolution error status flag Read 0 ECAP_INDICATE_NO_EVENT Indicates no event occurred Read 1 ECAP_INDICATE_HIGH_RESOLUTION_ERROR Indicates the High resolution Error occurred" "0,1"
rbitfld.long 0x08 23. "CTR_CMP_FLG,Compare Equal Compare Status Flag" "0,1"
rbitfld.long 0x08 22. "CTR_PRD_FLG,Counter Equal Period Status Flag" "0,1"
newline
rbitfld.long 0x08 21. "CTROVF_FLG,Counter Overflow Status Flag" "0,1"
rbitfld.long 0x08 20. "CEVT4_FLG,Capture Event 4 Status Flag This flag is only active in CAP mode" "0,1"
rbitfld.long 0x08 19. "CEVT3_FLG,Capture Event 3 Status Flag" "0,1"
rbitfld.long 0x08 18. "CEVT2_FLG,Capture Event 2 Status Flag" "0,1"
newline
rbitfld.long 0x08 17. "CEVT1_FLG,Capture Event 1 Status Flag" "0,1"
rbitfld.long 0x08 16. "INT_FLG,Global Interrupt Status Flag Read 0 ECAP_INDICATE_NO_EVENT Indicates no event occurred Read 1 ECAP_INDICATE_INTERRUPT Indicates that an interrupt was generated" "0,1"
hexmask.long.byte 0x08 9.--15. 1. "NU_3,Reserved"
bitfld.long 0x08 8. "HRERROR,High resolution error interrupt enable 0 ECAP_DISAB_HRERROR_INTERRUPT Disable High Resolution Error as an Interrupt source 1 ECAP_ENAB_HRERROR_INTERRUPT Enable High Resolution Error as an Interrupt source" "0,1"
newline
bitfld.long 0x08 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 ECAP_DISAB_CE_INTERRUPT Disable Compare Equal as an Interrupt source 1 ECAP_ENAB_CE_INTERRUPT Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x08 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 ECAP_DISAB_PE_INTERRUPT Disable Period Equal as an Interrupt source 1 ECAP_ENAB_PE_INTERRUPT Enable Period Equal as an Interrupt source" "0,1"
bitfld.long 0x08 5. "CTROVF,Counter Overflow Interrupt Enable 0 ECAP_DISAB_CO_INTERRUPT Disabled counter Overflow as an Interrupt source 1 ECAP_ENAB_CO_INTERRUPT Enable counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x08 4. "CEVT4,Capture Event 4 Interrupt Enable 0 ECAP_DISAB_CAP4_INTERRUPT Disable Capture Event 4 as an Interrupt source 1 ECAP_ENAB_CAP4_INTERRUPT Capture Event 4 Interrupt Enable" "0,1"
newline
bitfld.long 0x08 3. "CEVT3,Capture Event 3 Interrupt Enable 0 ECAP_DISAB_CAP3_INTERRUPT Disable Capture Event 3 as an Interrupt source 1 ECAP_ENAB_CAP3_INTERRUPT Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x08 2. "CEVT2,Capture Event 2 Interrupt Enable 0 ECAP_DISAB_CAP2_INTERRUPT Disable Capture Event 2 as an Interrupt source 1 ECAP_ENAB_CAP2_INTERRUPT Enable Capture Event 2 as an Interrupt source" "0,1"
bitfld.long 0x08 1. "CEVT1,Capture Event 1 Interrupt Enable 0 ECAP_DISAB_CAP1_INTERRUPT Disable Capture Event 1 as an Interrupt source 1 ECAP_ENAB_CAP1_INTERRUPT Enable Capture Event 1 as an Interrupt source" "0,1"
rbitfld.long 0x08 0. "NU_2,Reserved" "0,1"
line.long 0x0C "ECCLR_ECFRC,Capture Interrupt Clear Register & Capture Interrupt Force Register"
hexmask.long.byte 0x0C 25.--31. 1. "NU_6,Reserved"
bitfld.long 0x0C 24. "HRERROR_FRC,High resolution error Force interrupt 0 ECAP_NO_EFFECT_0 No effect" "0,1"
bitfld.long 0x0C 23. "CTR_CMP_FRC,Force Counter Equal Compare Interrupt" "0,1"
bitfld.long 0x0C 22. "CTR_PRD_FRC,Force Counter Equal Period Interrupt" "0,1"
newline
bitfld.long 0x0C 21. "CTROVF_FRC,Force Counter Overflow 0 ECAP_NO_EFFECT_0 No effect" "0,1"
bitfld.long 0x0C 20. "CEVT4_FRC,Force Capture Event 4" "0,1"
bitfld.long 0x0C 19. "CEVT3_FRC,Force Capture Event 3" "0,1"
bitfld.long 0x0C 18. "CEVT2_FRC,Force Capture Event 2" "0,1"
newline
bitfld.long 0x0C 17. "CEVT1_FRC,Force Capture Event 1" "0,1"
hexmask.long.byte 0x0C 9.--16. 1. "NU_5,Reserved"
bitfld.long 0x0C 8. "HRERROR,High resolution error status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 7. "CTR_CMP,Counter Equal Compare Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
newline
bitfld.long 0x0C 6. "CTR_PRD,Counter Equal Period Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 5. "CTROVF,Counter Overflow Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 4. "CEVT4,Capture Event 4 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 3. "CEVT3,Capture Event 3 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
newline
bitfld.long 0x0C 2. "CEVT2,Capture Event 2 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 1. "CEVT1,Capture Event 1 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 0. "INT,ECAP Global Interrupt Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
group.long 0x3C++0x03
line.long 0x00 "ECAPSYNCINSEL,SYNC source select register"
hexmask.long 0x00 5.--31. 1. "NU_7,Reserved"
bitfld.long 0x00 0.--4. "SEL,These bits determines the source of SYNCIN signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "RCSS_GIO (RCSS GIO Module Registers)"
base ad:0x55F7B400
group.long 0x00++0x03
line.long 0x00 "GIOGCR,GIO reset"
hexmask.long 0x00 1.--31. 1. "NU0,Reserved"
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "GIOPWDN,GIO power down mode register"
bitfld.long 0x00 0. "GIOPWDN,Writing to the GIOPWDN bit is only allowed in privilege mode" "Normal operation; clocks enabled to GIO..,Power-down mode"
group.long 0x08++0x14B
line.long 0x00 "GIOINTDET,Interrupt detection select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x00 24.--31. 1. "GIOINTDET_3,Interrupt detection select for pins GIOD[7:0]"
hexmask.long.byte 0x00 16.--23. 1. "GIOINTDET_2,Interrupt detection select for pins GIOC[7:0]"
hexmask.long.byte 0x00 8.--15. 1. "GIOINTDET_1,Interrupt detection select for pins GIOB[7:0]"
hexmask.long.byte 0x00 0.--7. 1. "GIOINTDET_0,Interrupt detection select for pins GIOA[7:0]"
line.long 0x04 "GIOPOL,Interrupt polarity select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x04 24.--31. 1. "GIOPOL_3,Interrupt polarity select for pins GIOD[7:0]"
hexmask.long.byte 0x04 16.--23. 1. "GIOPOL_2,Interrupt polarity select for pins GIOC[7:0]"
hexmask.long.byte 0x04 8.--15. 1. "GIOPOL_1,Interrupt polarity select for pins GIOB[7:0]"
hexmask.long.byte 0x04 0.--7. 1. "GIOPOL_0,Interrupt polarity select for pins GIOA[7:0]"
line.long 0x08 "GIOENASET,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x08 24.--31. 1. "GIOENASET_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x08 16.--23. 1. "GIOENASET_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x08 8.--15. 1. "GIOENASET_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x08 0.--7. 1. "GIOENASET_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x0C "GIOENACLR,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x0C 24.--31. 1. "GIOENACLR_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x0C 16.--23. 1. "GIOENACLR_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x0C 8.--15. 1. "GIOENACLR_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x0C 0.--7. 1. "GIOENACLR_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x10 "GIOLVLSET,GIO high priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x10 24.--31. 1. "GIOLVLSET_3,GIO high priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x10 16.--23. 1. "GIOLVLSET_2,GIO high priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x10 8.--15. 1. "GIOLVLSET_1,GIO high priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x10 0.--7. 1. "GIOLVLSET_0,GIO high priority interrupt for pins GIOA[7:0]"
line.long 0x14 "GIOLVLCLR,GIO low priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x14 24.--31. 1. "GIOLVLCLR_3,GIO low priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x14 16.--23. 1. "GIOLVLCLR_2,GIO low priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x14 8.--15. 1. "GIOLVLCLR_1,GIO low priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x14 0.--7. 1. "GIOLVLCLR_0,GIO low priority interrupt for pins GIOA[7:0]"
line.long 0x18 "GIOFLG,GIO flag for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x18 24.--31. 1. "GIOFLG_3,GIO flag for pins GIOD[7:0]"
hexmask.long.byte 0x18 16.--23. 1. "GIOFLG_2,GIO flag for pins GIOC[7:0]"
hexmask.long.byte 0x18 8.--15. 1. "GIOFLG_1,GIO flag for pins GIOB[7:0]"
hexmask.long.byte 0x18 0.--7. 1. "GIOFLG_0,GIO flag for pins GIOA[7:0]"
line.long 0x1C "GIOOFFA,Index bits for currently pending high-priority interrupt Register A"
hexmask.long 0x1C 6.--31. 1. "NU1,Reserved"
bitfld.long 0x1C 0.--5. "GIOOFFA,Index bits for currently pending high-priority interrupt Register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "GIOOFFB,Index bits for currently pending high-priority interrupt Register B"
hexmask.long 0x20 6.--31. 1. "NU2,Reserved"
bitfld.long 0x20 0.--5. "GIOOFFB,Index bits for currently pending high-priority interrupt Register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "GIOEMUA,GIO emulation register A"
hexmask.long 0x24 6.--31. 1. "NU3,Reserved"
bitfld.long 0x24 0.--5. "GIOEMUA,GIO emulation register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "GIOEMUB,GIO emulation register B"
hexmask.long 0x28 6.--31. 1. "NU4,Reserved"
bitfld.long 0x28 0.--5. "GIOEMUB,GIO emulation register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "GIODIRA,GIO data direction of pins in Port A"
hexmask.long.tbyte 0x2C 8.--31. 1. "NU5,Reserved"
hexmask.long.byte 0x2C 0.--7. 1. "GIODIRA,GIO data direction of pins in Port A"
line.long 0x30 "GIODINA,GIO data input for pins in port A"
hexmask.long.tbyte 0x30 8.--31. 1. "NU11,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "GIODINA,GIO data input for pins in port A"
line.long 0x34 "GIODOUTA,GIO data output for pins in port A"
hexmask.long.tbyte 0x34 8.--31. 1. "NU17,Reserved"
hexmask.long.byte 0x34 0.--7. 1. "GIODOUTA,GIO data output for pins in port A"
line.long 0x38 "GIOSETA,GIO data set for port A"
hexmask.long.tbyte 0x38 8.--31. 1. "NU23,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "GIODSETA,GIO data set for port A"
line.long 0x3C "GIOCLRA,GIO data clear for port A"
hexmask.long.tbyte 0x3C 8.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x3C 0.--7. 1. "GIODCLRA,GIO data clear for port A"
line.long 0x40 "GIOPDRA,GIO open drain for port A"
hexmask.long.tbyte 0x40 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x40 0.--7. 1. "GIOPDRA,GIO open drain for port A"
line.long 0x44 "GIOPULDISA,GIO pul disable for port A"
hexmask.long.tbyte 0x44 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x44 0.--7. 1. "GIOPULDISA,GIO pull disable for port A"
line.long 0x48 "GIOPSLA,GIO pul select for port A"
hexmask.long.tbyte 0x48 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x48 0.--7. 1. "GIOPSLA,GIO pull select for port A"
line.long 0x4C "GIODIRB,GIO data direction of pins in Port B"
hexmask.long.tbyte 0x4C 8.--31. 1. "NU6,Reserved"
hexmask.long.byte 0x4C 0.--7. 1. "GIODIRB,GIO data direction of pins in Port B"
line.long 0x50 "GIODINB,GIO data input for pins in port B"
hexmask.long.tbyte 0x50 8.--31. 1. "NU12,Reserved"
hexmask.long.byte 0x50 0.--7. 1. "GIODINB,GIO data input for pins in port B"
line.long 0x54 "GIODOUTB,GIO data output for pins in port B"
hexmask.long.tbyte 0x54 8.--31. 1. "NU18,Reserved"
hexmask.long.byte 0x54 0.--7. 1. "GIODOUTB,GIO data output for pins in port B"
line.long 0x58 "GIOSETB,GIO data set for port B"
hexmask.long.tbyte 0x58 8.--31. 1. "NU24,Reserved"
hexmask.long.byte 0x58 0.--7. 1. "GIODSETB,GIO data set for port B"
line.long 0x5C "GIOCLRB,GIO data clear for port B"
hexmask.long.tbyte 0x5C 8.--31. 1. "NU30,Reserved"
hexmask.long.byte 0x5C 0.--7. 1. "GIODCLRB,GIO data clear for port B"
line.long 0x60 "GIOPDRB,GIO open drain for port B"
hexmask.long.tbyte 0x60 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x60 0.--7. 1. "GIOPDRB,GIO open drain for port B"
line.long 0x64 "GIOPULDISB,GIO pul disable for port B"
hexmask.long.tbyte 0x64 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x64 0.--7. 1. "GIOPULDISB,GIO pull disable for port B"
line.long 0x68 "GIOPSLB,GIO pul select for port B"
hexmask.long.tbyte 0x68 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x68 0.--7. 1. "GIOPSLB,GIO pull select for port B"
line.long 0x6C "GIODIRC,GIO data direction of pins in Port C"
hexmask.long.tbyte 0x6C 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x6C 0.--7. 1. "GIODIRC,GIO data direction of pins in Port C"
line.long 0x70 "GIODINC,GIO data input for pins in port C"
hexmask.long.tbyte 0x70 8.--31. 1. "NU13,Reserved"
hexmask.long.byte 0x70 0.--7. 1. "GIODINC,GIO data input for pins in port C"
line.long 0x74 "GIODOUTC,GIO data output for pins in port C"
hexmask.long.tbyte 0x74 8.--31. 1. "NU19,Reserved"
hexmask.long.byte 0x74 0.--7. 1. "GIODOUTC,GIO data output for pins in port C"
line.long 0x78 "GIOSETC,GIO data set for port C"
hexmask.long.tbyte 0x78 8.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x78 0.--7. 1. "GIODSETC,GIO data set for port C"
line.long 0x7C "GIOCLRC,GIO data clear for port C"
hexmask.long.tbyte 0x7C 8.--31. 1. "NU31,Reserved"
hexmask.long.byte 0x7C 0.--7. 1. "GIODCLRC,GIO data clear for port C"
line.long 0x80 "GIOPDRC,GIO open drain for port C"
hexmask.long.tbyte 0x80 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x80 0.--7. 1. "GIOPDRC,GIO open drain for port C"
line.long 0x84 "GIOPULDISC,GIO pul disable for port C"
hexmask.long.tbyte 0x84 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x84 0.--7. 1. "GIOPULDISC,GIO pull disable for port C"
line.long 0x88 "GIOPSLC,GIO pul select for port C"
hexmask.long.tbyte 0x88 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x88 0.--7. 1. "GIOPSLC,GIO pull select for port C"
line.long 0x8C "GIODIRD,GIO data direction of pins in Port D"
hexmask.long.tbyte 0x8C 8.--31. 1. "NU8,Reserved"
hexmask.long.byte 0x8C 0.--7. 1. "GIODIRD,GIO data direction of pins in Port D"
line.long 0x90 "GIODIND,GIO data input for pins in port D"
hexmask.long.tbyte 0x90 8.--31. 1. "NU14,Reserved"
hexmask.long.byte 0x90 0.--7. 1. "GIODIND,GIO data input for pins in port D"
line.long 0x94 "GIODOUTD,GIO data output for pins in port D"
hexmask.long.tbyte 0x94 8.--31. 1. "NU20,Reserved"
hexmask.long.byte 0x94 0.--7. 1. "GIODOUTD,GIO data output for pins in port D"
line.long 0x98 "GIOSETD,GIO data set for port D"
hexmask.long.tbyte 0x98 8.--31. 1. "NU26,Reserved"
hexmask.long.byte 0x98 0.--7. 1. "GIODSETD,GIO data set for port D"
line.long 0x9C "GIOCLRD,GIO data clear for port D"
hexmask.long.tbyte 0x9C 8.--31. 1. "NU32,Reserved"
hexmask.long.byte 0x9C 0.--7. 1. "GIODCLRD,GIO data clear for port D"
line.long 0xA0 "GIOPDRD,GIO open drain for port D"
hexmask.long.tbyte 0xA0 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA0 0.--7. 1. "GIOPDRD,GIO open drain for port D"
line.long 0xA4 "GIOPULDISD,GIO pul disable for port D"
hexmask.long.tbyte 0xA4 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA4 0.--7. 1. "GIOPULDISD,GIO pull disable for port D"
line.long 0xA8 "GIOPSLD,GIO pul select for port D"
hexmask.long.tbyte 0xA8 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA8 0.--7. 1. "GIOPSLD,GIO pull select for port D"
line.long 0xAC "GIODIRE,GIO data direction of pins in Port E"
hexmask.long.tbyte 0xAC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xAC 0.--7. 1. "GIODIRE,GIO data direction of pins in Port E"
line.long 0xB0 "GIODINE,GIO data input for pins in port E"
hexmask.long.tbyte 0xB0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xB0 0.--7. 1. "GIODINE,GIO data input for pins in port E"
line.long 0xB4 "GIODOUTE,GIO data output for pins in port E"
hexmask.long.tbyte 0xB4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xB4 0.--7. 1. "GIODOUTE,GIO data output for pins in port E"
line.long 0xB8 "GIOSETE,GIO data set for port E"
hexmask.long.tbyte 0xB8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xB8 0.--7. 1. "GIODSETE,GIO data set for port E"
line.long 0xBC "GIOCLRE,GIO data clear for port E"
hexmask.long.tbyte 0xBC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xBC 0.--7. 1. "GIODCLRE,GIO data clear for port E"
line.long 0xC0 "GIOPDRE,GIO open drain for port E"
hexmask.long.tbyte 0xC0 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC0 0.--7. 1. "GIOPDRE,GIO open drain for port E"
line.long 0xC4 "GIOPULDISE,GIO pul disable for port E"
hexmask.long.tbyte 0xC4 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC4 0.--7. 1. "GIOPULDISE,GIO pull disable for port E"
line.long 0xC8 "GIOPSLE,GIO pul select for port E"
hexmask.long.tbyte 0xC8 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC8 0.--7. 1. "GIOPSLE,GIO pull select for port E"
line.long 0xCC "GIODIRF,GIO data direction of pins in Port F"
hexmask.long.tbyte 0xCC 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0xCC 0.--7. 1. "GIODIRF,GIO data direction of pins in Port F"
line.long 0xD0 "GIODINF,GIO data input for pins in Port F"
hexmask.long.tbyte 0xD0 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0xD0 0.--7. 1. "GIODINF,GIO data input for pins in port F"
line.long 0xD4 "GIODOUTF,GIO data output for pins in Port F"
hexmask.long.tbyte 0xD4 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0xD4 0.--7. 1. "GIODOUTF,GIO data output for pins in port F"
line.long 0xD8 "GIOSETF,GIO data set for Port F"
hexmask.long.tbyte 0xD8 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0xD8 0.--7. 1. "GIODSETF,GIO data set for port F"
line.long 0xDC "GIOCLRF,GIO data clear for Port F"
hexmask.long.tbyte 0xDC 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0xDC 0.--7. 1. "GIODCLRF,GIO data clear for port F"
line.long 0xE0 "GIOPDRF,GIO open drain for Port F"
hexmask.long.tbyte 0xE0 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE0 0.--7. 1. "GIOPDRF,GIO open drain for port F"
line.long 0xE4 "GIOPULDISF,GIO pul disable for port F"
hexmask.long.tbyte 0xE4 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE4 0.--7. 1. "GIOPULDISF,GIO pull disable for port F"
line.long 0xE8 "GIOPSLF,GIO pul select for port F"
hexmask.long.tbyte 0xE8 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE8 0.--7. 1. "GIOPSLF,GIO pull select for port F"
line.long 0xEC "GIODIRG,GIO data direction of pins in Port G"
hexmask.long.tbyte 0xEC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xEC 0.--7. 1. "GIODIRG,GIO data direction of pins in Port G"
line.long 0xF0 "GIODING,GIO data input for pins in port G"
hexmask.long.tbyte 0xF0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xF0 0.--7. 1. "GIODING,GIO data input for pins in port G"
line.long 0xF4 "GIODOUTG,GIO data output for pins in port G"
hexmask.long.tbyte 0xF4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xF4 0.--7. 1. "GIODOUTG,GIO data output for pins in port G"
line.long 0xF8 "GIOSETG,GIO data set for port G"
hexmask.long.tbyte 0xF8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xF8 0.--7. 1. "GIODSETG,GIO data set for port G"
line.long 0xFC "GIOCLRG,GIO data clear for port G"
hexmask.long.tbyte 0xFC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xFC 0.--7. 1. "GIODCLRG,GIO data clear for port G"
line.long 0x100 "GIOPDRG,GIO open drain for port G"
hexmask.long.tbyte 0x100 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x100 0.--7. 1. "GIOPDRG,GIO open drain for port G"
line.long 0x104 "GIOPULDISG,GIO pul disable for port G"
hexmask.long.tbyte 0x104 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x104 0.--7. 1. "GIOPULDISG,GIO pull disable for port G"
line.long 0x108 "GIOPSLG,GIO pul select for port G"
hexmask.long.tbyte 0x108 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x108 0.--7. 1. "GIOPSLG,GIO pull select for port G"
line.long 0x10C "GIODIRH,GIO data direction of pins in Port H"
hexmask.long.tbyte 0x10C 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0x10C 0.--7. 1. "GIODIRH,GIO data direction of pins in Port H"
line.long 0x110 "GIODINH,GIO data input for pins in Port H"
hexmask.long.tbyte 0x110 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x110 0.--7. 1. "GIODINH,GIO data input for pins in port H"
line.long 0x114 "GIODOUTH,GIO data output for pins in Port H"
hexmask.long.tbyte 0x114 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0x114 0.--7. 1. "GIODOUTH,GIO data output for pins in port H"
line.long 0x118 "GIOSETH,GIO data set for Port H"
hexmask.long.tbyte 0x118 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0x118 0.--7. 1. "GIODSETH,GIO data set for port H"
line.long 0x11C "GIOCLRH,GIO data clear for Port H"
hexmask.long.tbyte 0x11C 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0x11C 0.--7. 1. "GIODCLRH,GIO data clear for port H"
line.long 0x120 "GIOPDRH,GIO open drain for Port H"
hexmask.long.tbyte 0x120 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x120 0.--7. 1. "GIOPDRH,GIO open drain for port H"
line.long 0x124 "GIOPULDISH,GIO pul disable for port H"
hexmask.long.tbyte 0x124 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x124 0.--7. 1. "GIOPULDISH,GIO pull disable for port H"
line.long 0x128 "GIOPSLH,GIO pul select for port H"
hexmask.long.tbyte 0x128 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x128 0.--7. 1. "GIOPSLH,GIO pull select for port H"
line.long 0x12C "GIOSRCA,GIO slew rate select for port A"
hexmask.long.tbyte 0x12C 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x12C 0.--7. 1. "GIOSRCA,GIO slew rate control for port A"
line.long 0x130 "GIOSRCB,GIO slew rate select for port B"
hexmask.long.tbyte 0x130 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x130 0.--7. 1. "GIOSRCB,GIO slew rate control for port B"
line.long 0x134 "GIOSRCC,GIO slew rate select for port C"
hexmask.long.tbyte 0x134 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x134 0.--7. 1. "GIOSRCC,GIO slew rate control for port C"
line.long 0x138 "GIOSRCD,GIO slew rate select for port D"
hexmask.long.tbyte 0x138 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x138 0.--7. 1. "GIOSRCD,GIO slew rate control for port D"
line.long 0x13C "GIOSRCE,GIO slew rate select for port E"
hexmask.long.tbyte 0x13C 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x13C 0.--7. 1. "GIOSRCE,GIO slew rate control for port E"
line.long 0x140 "GIOSRCF,GIO slew rate select for port F"
hexmask.long.tbyte 0x140 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x140 0.--7. 1. "GIOSRCF,GIO slew rate control for port F"
line.long 0x144 "GIOSRCG,GIO slew rate select for port G"
hexmask.long.tbyte 0x144 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x144 0.--7. 1. "GIOSRCG,GIO slew rate control for port G"
line.long 0x148 "GIOSRCH,GIO slew rate select for port H"
hexmask.long.tbyte 0x148 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x148 0.--7. 1. "GIOSRCH,GIO slew rate control for port H"
width 0x0B
tree.end
tree "RCSS_I2CA (RCSS I2CA Module Registers)"
base ad:0x55F7EC00
group.long 0x00++0x3F
line.long 0x00 "ICOAR,I2C Own Address register"
hexmask.long.tbyte 0x00 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x00 0.--9. 1. "A9_A0,Own address"
line.long 0x04 "ICIMR,I2C Interrupt Mask/Status register"
hexmask.long 0x04 7.--31. 1. "NU,Reserved"
bitfld.long 0x04 6. "AAS,Address As Slave interrupt mask bit" "0,1"
newline
bitfld.long 0x04 5. "SCD,Stop Condition Detection mask bit" "0,1"
bitfld.long 0x04 4. "ICXRDY,Transmit Data Ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 3. "ICRRDY,Receive Data Ready interrupt mask bit" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 1. "NACK,No Acknowledgement interrupt mask bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration Lost interrupt mask bit" "0,1"
line.long 0x08 "ICSTR,I2C Interrupt Status register"
hexmask.long.tbyte 0x08 15.--31. 1. "NU2,Reserved"
bitfld.long 0x08 14. "SDIR,Slave Direction" "0,1"
newline
bitfld.long 0x08 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'" "0,1"
bitfld.long 0x08 12. "BB,Bus Busy" "0,1"
newline
bitfld.long 0x08 11. "RSFULL,Receive shift full" "0,1"
bitfld.long 0x08 10. "XSMT,Transmit shift empty not" "0,1"
newline
bitfld.long 0x08 9. "AAS,Address As Slave" "0,1"
bitfld.long 0x08 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call)" "0,1"
newline
bitfld.long 0x08 6.--7. "NU1,Reserved" "0,1,2,3"
bitfld.long 0x08 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition" "0,1"
newline
bitfld.long 0x08 4. "ICXRDY,Transmit Data Ready interrupt flag bit" "0,1"
bitfld.long 0x08 3. "ICRRDY,Receive Data Ready interrupt flag bit" "0,1"
newline
bitfld.long 0x08 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
bitfld.long 0x08 1. "NACK,No-Acknowledgement interrupt flag bit" "0,1"
newline
bitfld.long 0x08 0. "AL,Arbitration-Lost interrupt flag bit" "0,1"
line.long 0x0C "ICCLKL,I2C Clock Divider Low register"
hexmask.long.word 0x0C 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "ICCL15_ICCL0,Low time I2C SCL Clock Division Factor"
line.long 0x10 "ICCLKH,I2C Clock Divider High register"
hexmask.long.word 0x10 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I2C SCL Clock Division Factor"
line.long 0x14 "ICCNT,I2C Data Count register"
hexmask.long.word 0x14 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count"
line.long 0x18 "ICDRR,I2C Data Receive register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data"
line.long 0x1C "ICSAR,I2C Slave Address register"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address"
line.long 0x20 "ICDXR,I2C Data Transmit register"
hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data"
line.long 0x24 "ICMDR,I2C Mode register"
hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved"
bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode" "0,1"
newline
bitfld.long 0x24 14. "FREE,Free Running" "0,1"
bitfld.long 0x24 13. "STT,Start Condition (Master only mode)" "0,1"
newline
bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509)" "0,1"
bitfld.long 0x24 11. "STP,Stop Condition (Master mode only)" "0,1"
newline
bitfld.long 0x24 10. "MST,Master" "0,1"
bitfld.long 0x24 9. "TRX,Transmitter" "0,1"
newline
bitfld.long 0x24 8. "XA,Expanded Address" "0,1"
bitfld.long 0x24 7. "RM,Repeat Mode" "0,1"
newline
bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only)" "0,1"
bitfld.long 0x24 5. "IRS,I2C Reset Not" "0,1"
newline
bitfld.long 0x24 4. "STB,Start Byte (Master only mode)" "0,1"
bitfld.long 0x24 3. "FDF,Free Data Format" "0,1"
newline
bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted" "0,1,2,3,4,5,6,7"
line.long 0x28 "ICIVR,I2C Interrupt Vector register"
hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved"
bitfld.long 0x28 8.--11. "TESTMD,Reserved for internal testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 3.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--2. "INTCODE,Interrupt code" "0,1,2,3,4,5,6,7"
line.long 0x2C "ICEMDR,I2C Extended Mode register"
hexmask.long 0x2C 2.--31. 1. "NU,Reserved"
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave" "0,1"
newline
bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode" "0,1"
line.long 0x30 "ICPSC,I2C Prescaler register"
hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module"
line.long 0x34 "ICPID1,I2C Peripheral ID register 1"
hexmask.long.word 0x34 16.--31. 1. "NU,Reserved"
hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral"
newline
hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C"
line.long 0x38 "ICPID2,I2C Peripheral ID register 2"
hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral"
line.long 0x3C "ICDMAC,I2C DMA Control Register"
hexmask.long 0x3C 2.--31. 1. "NU,Reserved"
bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable" "0,1"
newline
bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable" "0,1"
group.long 0x48++0x1B
line.long 0x00 "ICPFUNC,I2C Pin Function register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved"
bitfld.long 0x00 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins" "Pins function as SCL and SDA,Pins functions as GPIO"
line.long 0x04 "ICPDIR,I2C Pin Direction register"
hexmask.long 0x04 2.--31. 1. "NU,Reserved"
bitfld.long 0x04 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO" "SDA pin functions as input,SDA pin functions as output"
newline
bitfld.long 0x04 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO" "SCL pin functions as input,SCL pin functions as output"
line.long 0x08 "ICPDIN,I2C Pin Data In register"
hexmask.long 0x08 2.--31. 1. "NU,Reserved"
bitfld.long 0x08 1. "PDIN1,Indicates the logic level present on the SDA pin" "Logic low present at SDA pin regardless of PFUNC..,Logic high present at SDA pin regardless of.."
newline
bitfld.long 0x08 0. "PDIN0,Indicates the logic level present on the SCL pin" "Logic low present at SCL pin regardless of PFUNC..,Logic high present at SCL pin regardless of.."
line.long 0x0C "ICPDOUT,I2C Pin Data Out register"
hexmask.long 0x0C 2.--31. 1. "NU,Reserved"
bitfld.long 0x0C 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output" "SDA pin driven low,SDA pin driven high"
newline
bitfld.long 0x0C 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output" "SCL pin driven low,SCL pin driven high"
line.long 0x10 "ICPDSET,I2C Pin Data Set register"
hexmask.long 0x10 2.--31. 1. "NU,Reserved"
bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin" "no effect,PDOUT[1] bit is set to.."
newline
bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin" "no effect,PDOUT[0] bit is set to.."
line.long 0x14 "ICPDCLR,I2C Pin Data Clear register"
hexmask.long 0x14 2.--31. 1. "NU,Reserved"
bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin" "no effect,PDOUT[1] bit is cleared.."
newline
bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin" "no effect,PDOUT[0] bit is cleared.."
line.long 0x18 "ICPDRV,I2C Pin Driver Mode Register"
hexmask.long 0x18 2.--31. 1. "NU,Reserved"
bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin" "I2C mode,GPIO mode"
newline
bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin" "I2C mode,GPIO mode"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "I2C_RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "RCSS_I2CB (RCSS I2CB Module Registers)"
base ad:0x55F7F000
group.long 0x00++0x3F
line.long 0x00 "ICOAR,I2C Own Address register"
hexmask.long.tbyte 0x00 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x00 0.--9. 1. "A9_A0,Own address"
line.long 0x04 "ICIMR,I2C Interrupt Mask/Status register"
hexmask.long 0x04 7.--31. 1. "NU,Reserved"
bitfld.long 0x04 6. "AAS,Address As Slave interrupt mask bit" "0,1"
newline
bitfld.long 0x04 5. "SCD,Stop Condition Detection mask bit" "0,1"
bitfld.long 0x04 4. "ICXRDY,Transmit Data Ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 3. "ICRRDY,Receive Data Ready interrupt mask bit" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 1. "NACK,No Acknowledgement interrupt mask bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration Lost interrupt mask bit" "0,1"
line.long 0x08 "ICSTR,I2C Interrupt Status register"
hexmask.long.tbyte 0x08 15.--31. 1. "NU2,Reserved"
bitfld.long 0x08 14. "SDIR,Slave Direction" "0,1"
newline
bitfld.long 0x08 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'" "0,1"
bitfld.long 0x08 12. "BB,Bus Busy" "0,1"
newline
bitfld.long 0x08 11. "RSFULL,Receive shift full" "0,1"
bitfld.long 0x08 10. "XSMT,Transmit shift empty not" "0,1"
newline
bitfld.long 0x08 9. "AAS,Address As Slave" "0,1"
bitfld.long 0x08 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call)" "0,1"
newline
bitfld.long 0x08 6.--7. "NU1,Reserved" "0,1,2,3"
bitfld.long 0x08 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition" "0,1"
newline
bitfld.long 0x08 4. "ICXRDY,Transmit Data Ready interrupt flag bit" "0,1"
bitfld.long 0x08 3. "ICRRDY,Receive Data Ready interrupt flag bit" "0,1"
newline
bitfld.long 0x08 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
bitfld.long 0x08 1. "NACK,No-Acknowledgement interrupt flag bit" "0,1"
newline
bitfld.long 0x08 0. "AL,Arbitration-Lost interrupt flag bit" "0,1"
line.long 0x0C "ICCLKL,I2C Clock Divider Low register"
hexmask.long.word 0x0C 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "ICCL15_ICCL0,Low time I2C SCL Clock Division Factor"
line.long 0x10 "ICCLKH,I2C Clock Divider High register"
hexmask.long.word 0x10 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I2C SCL Clock Division Factor"
line.long 0x14 "ICCNT,I2C Data Count register"
hexmask.long.word 0x14 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count"
line.long 0x18 "ICDRR,I2C Data Receive register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data"
line.long 0x1C "ICSAR,I2C Slave Address register"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address"
line.long 0x20 "ICDXR,I2C Data Transmit register"
hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data"
line.long 0x24 "ICMDR,I2C Mode register"
hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved"
bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode" "0,1"
newline
bitfld.long 0x24 14. "FREE,Free Running" "0,1"
bitfld.long 0x24 13. "STT,Start Condition (Master only mode)" "0,1"
newline
bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509)" "0,1"
bitfld.long 0x24 11. "STP,Stop Condition (Master mode only)" "0,1"
newline
bitfld.long 0x24 10. "MST,Master" "0,1"
bitfld.long 0x24 9. "TRX,Transmitter" "0,1"
newline
bitfld.long 0x24 8. "XA,Expanded Address" "0,1"
bitfld.long 0x24 7. "RM,Repeat Mode" "0,1"
newline
bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only)" "0,1"
bitfld.long 0x24 5. "IRS,I2C Reset Not" "0,1"
newline
bitfld.long 0x24 4. "STB,Start Byte (Master only mode)" "0,1"
bitfld.long 0x24 3. "FDF,Free Data Format" "0,1"
newline
bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted" "0,1,2,3,4,5,6,7"
line.long 0x28 "ICIVR,I2C Interrupt Vector register"
hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved"
bitfld.long 0x28 8.--11. "TESTMD,Reserved for internal testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 3.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--2. "INTCODE,Interrupt code" "0,1,2,3,4,5,6,7"
line.long 0x2C "ICEMDR,I2C Extended Mode register"
hexmask.long 0x2C 2.--31. 1. "NU,Reserved"
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave" "0,1"
newline
bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode" "0,1"
line.long 0x30 "ICPSC,I2C Prescaler register"
hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module"
line.long 0x34 "ICPID1,I2C Peripheral ID register 1"
hexmask.long.word 0x34 16.--31. 1. "NU,Reserved"
hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral"
newline
hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C"
line.long 0x38 "ICPID2,I2C Peripheral ID register 2"
hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral"
line.long 0x3C "ICDMAC,I2C DMA Control Register"
hexmask.long 0x3C 2.--31. 1. "NU,Reserved"
bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable" "0,1"
newline
bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable" "0,1"
group.long 0x48++0x1B
line.long 0x00 "ICPFUNC,I2C Pin Function register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved"
bitfld.long 0x00 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins" "Pins function as SCL and SDA,Pins functions as GPIO"
line.long 0x04 "ICPDIR,I2C Pin Direction register"
hexmask.long 0x04 2.--31. 1. "NU,Reserved"
bitfld.long 0x04 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO" "SDA pin functions as input,SDA pin functions as output"
newline
bitfld.long 0x04 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO" "SCL pin functions as input,SCL pin functions as output"
line.long 0x08 "ICPDIN,I2C Pin Data In register"
hexmask.long 0x08 2.--31. 1. "NU,Reserved"
bitfld.long 0x08 1. "PDIN1,Indicates the logic level present on the SDA pin" "Logic low present at SDA pin regardless of PFUNC..,Logic high present at SDA pin regardless of.."
newline
bitfld.long 0x08 0. "PDIN0,Indicates the logic level present on the SCL pin" "Logic low present at SCL pin regardless of PFUNC..,Logic high present at SCL pin regardless of.."
line.long 0x0C "ICPDOUT,I2C Pin Data Out register"
hexmask.long 0x0C 2.--31. 1. "NU,Reserved"
bitfld.long 0x0C 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output" "SDA pin driven low,SDA pin driven high"
newline
bitfld.long 0x0C 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output" "SCL pin driven low,SCL pin driven high"
line.long 0x10 "ICPDSET,I2C Pin Data Set register"
hexmask.long 0x10 2.--31. 1. "NU,Reserved"
bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin" "no effect,PDOUT[1] bit is set to.."
newline
bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin" "no effect,PDOUT[0] bit is set to.."
line.long 0x14 "ICPDCLR,I2C Pin Data Clear register"
hexmask.long 0x14 2.--31. 1. "NU,Reserved"
bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin" "no effect,PDOUT[1] bit is cleared.."
newline
bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin" "no effect,PDOUT[0] bit is cleared.."
line.long 0x18 "ICPDRV,I2C Pin Driver Mode Register"
hexmask.long 0x18 2.--31. 1. "NU,Reserved"
bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin" "I2C mode,GPIO mode"
newline
bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin" "I2C mode,GPIO mode"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "I2C_RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "RCSS_MCASP_A (RCSS McASP A Module Registers)"
base ad:0x551E0000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 2.--5. "UNDEFINED_NAME,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Power management Configuration of the local target state management mode" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x10++0x13
line.long 0x00 "PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "UNDEFINED_NAME,Determines if AFSR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 28. "UNDEFINED_NAME,Determines if AFSX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x00 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x00 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x04 "PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "UNDEFINED_NAME,Determines if AFSR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 28. "UNDEFINED_NAME,Determines if AFSX pin functions as an input or output" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as an input or output" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x04 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x04 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as an input or output" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x08 "PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "UNDEFINED_NAME,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 30. "UNDEFINED_NAME,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x08 29. "UNDEFINED_NAME,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 28. "UNDEFINED_NAME,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x08 27. "UNDEFINED_NAME,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 26. "UNDEFINED_NAME,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x08 25. "UNDEFINED_NAME,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x08 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x08 0.--3. "UNDEFINED_NAME,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x0C "PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "UNDEFINED_NAME,Logic level on AFSR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 30. "UNDEFINED_NAME,Logic level on AHCLKR pin" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 29. "UNDEFINED_NAME,Logic level on ACLKR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 28. "UNDEFINED_NAME,Logic level on AFSX pin" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 27. "UNDEFINED_NAME,Logic level on AHCLKX pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 26. "UNDEFINED_NAME,Logic level on ACLKX pin" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 25. "UNDEFINED_NAME,Logic level on AMUTE pin" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x0C 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x0C 0.--3. "UNDEFINED_NAME,Logic level on AXR[n] pin" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x10 "PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "UNDEFINED_NAME,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 30. "UNDEFINED_NAME,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 29. "UNDEFINED_NAME,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 28. "UNDEFINED_NAME,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 27. "UNDEFINED_NAME,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 26. "UNDEFINED_NAME,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 25. "UNDEFINED_NAME,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x10 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x10 0.--3. "UNDEFINED_NAME,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
group.long 0x44++0x0F
line.long 0x00 "GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 12. "UNDEFINED_NAME,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 11. "UNDEFINED_NAME,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 10. "UNDEFINED_NAME,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 9. "UNDEFINED_NAME,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 8. "UNDEFINED_NAME,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 7. "UNDEFINED_NAME,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 6. "UNDEFINED_NAME,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 5. "UNDEFINED_NAME,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x04 4. "UNDEFINED_NAME,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 3. "UNDEFINED_NAME,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2. "UNDEFINED_NAME,Audio mute in [AMUTEIN] polarity select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 0.--1. "UNDEFINED_NAME,AMUTE pin enable bit [unless overridden by GPIO registers]" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Loopback generator mode bits" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 1. "UNDEFINED_NAME,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Loopback mode enable bit" "en_1_0x0,en_2_0x1"
line.long 0x0C "DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Valid bit for odd time slots [DIT right subframe]" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 2. "UNDEFINED_NAME,Valid bit for even time slots [DIT left subframe]" "en_1_0x0,en_2_0x1"
rbitfld.long 0x0C 1. "UNDEFINED_NAME," "0,1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,DIT mode enable bit" "en_1_0x0,en_2_0x1"
group.long 0x60++0x2F
line.long 0x00 "RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "0,1"
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rbitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "0,1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Receive bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 15. "UNDEFINED_NAME,Receive serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to the word" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 8.--12. "UNDEFINED_NAME,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Receive slot size" "en_7_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_5_0xA,en_1_0xB,en_4_0xC,en_2_0xD,en_6_0xE,en_3_0xF"
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bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for receive rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Receive frame sync mode select bits"
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rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Receive frame sync generation select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,Receive frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Receive bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Receive bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Receive high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Receive bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Receive start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Receive data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Receive last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Receive DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Receive clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected receive frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Receiver overrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Receive DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Receive start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Receive data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Receive last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of RSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Receive clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected receive frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Receiver overrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--8. 1. "UNDEFINED_NAME,"
line.long 0x28 "RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Receive clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Receive clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Receive data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0xA0++0x2F
line.long 0x00 "XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "0,1"
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rbitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Transmit sync bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 15. "UNDEFINED_NAME,Transmit serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to word defined by XMASK" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 8.--12. "UNDEFINED_NAME,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Transmit slot size" "en_2_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_7_0xA,en_5_0xB,en_6_0xC,en_3_0xD,en_1_0xE,en_4_0xF"
newline
bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for transmit rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Transmit frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Transmit frame sync generation select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,Transmit frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Transmit bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 6. "UNDEFINED_NAME,Transmit/receive operation asynchronous enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Transmit bit clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Transmit high-frequency clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x14 14. "UNDEFINED_NAME,Transmit bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Transmit start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Transmit data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Transmit DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 2. "UNDEFINED_NAME,Transmit clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected transmit frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 0. "UNDEFINED_NAME,Transmitter underrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 7. "UNDEFINED_NAME,Transmit DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Transmit start of frame flag" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 5. "UNDEFINED_NAME,Transmit data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Transmit last slot flag" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of XSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Transmit clock failure flag" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected transmit frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Transmitter underrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--9. 1. "UNDEFINED_NAME,Current transmit time slot count"
line.long 0x28 "XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Transmit clock maximum boundary"
newline
hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Transmit clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Transmit data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
group.long 0x180++0x3F
line.long 0x00 "SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x00 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x00 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x04 "SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x04 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x04 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x08 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x08 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x08 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x0C "SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x0C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x0C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x0C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x10 "SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x10 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x10 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x10 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x10 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x14 "SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x14 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x14 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x14 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x14 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x14 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x18 "SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x18 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x18 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x18 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x18 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x18 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x1C "SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x1C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x1C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x1C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x20 "SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x20 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x20 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x20 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x20 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x24 "SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x24 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x24 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x24 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x24 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x24 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x28 "SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x28 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x28 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x28 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x28 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x28 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x2C "SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x2C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x2C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x2C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x2C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x2C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x30 "SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x30 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x30 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x30 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x30 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x30 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x34 "SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x34 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x34 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x34 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x34 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x34 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x38 "SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x38 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x38 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x38 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x38 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x38 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x3C "SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x3C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x3C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x3C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x3C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x3C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x1000++0x0F
line.long 0x00 "WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 16. "UNDEFINED_NAME,Write FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
hexmask.long.byte 0x00 8.--15. 1. "UNDEFINED_NAME,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "UNDEFINED_NAME,Write word count per transfer [32 bit words]"
line.long 0x04 "WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x04 0.--7. "UNDEFINED_NAME,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16. "UNDEFINED_NAME,Read FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
abitfld.long 0x08 8.--15. "UNDEFINED_NAME,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "UNDEFINED_NAME,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x0C 0.--7. "UNDEFINED_NAME,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
width 0x0B
tree.end
tree "RCSS_MCASP_B (RCSS McASP B Module Registers)"
base ad:0x55200000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 2.--5. "UNDEFINED_NAME,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Power management Configuration of the local target state management mode" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x10++0x13
line.long 0x00 "PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "UNDEFINED_NAME,Determines if AFSR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 28. "UNDEFINED_NAME,Determines if AFSX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x00 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x00 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x04 "PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "UNDEFINED_NAME,Determines if AFSR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 28. "UNDEFINED_NAME,Determines if AFSX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as an input or output" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x04 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as an input or output" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x08 "PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "UNDEFINED_NAME,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 30. "UNDEFINED_NAME,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 29. "UNDEFINED_NAME,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 28. "UNDEFINED_NAME,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 27. "UNDEFINED_NAME,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 26. "UNDEFINED_NAME,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 25. "UNDEFINED_NAME,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x08 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x0C "PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "UNDEFINED_NAME,Logic level on AFSR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 30. "UNDEFINED_NAME,Logic level on AHCLKR pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 29. "UNDEFINED_NAME,Logic level on ACLKR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 28. "UNDEFINED_NAME,Logic level on AFSX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 27. "UNDEFINED_NAME,Logic level on AHCLKX pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 26. "UNDEFINED_NAME,Logic level on ACLKX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 25. "UNDEFINED_NAME,Logic level on AMUTE pin" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x0C 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x0C 0.--3. "UNDEFINED_NAME,Logic level on AXR[n] pin" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x10 "PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "UNDEFINED_NAME,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 30. "UNDEFINED_NAME,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 29. "UNDEFINED_NAME,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 28. "UNDEFINED_NAME,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 27. "UNDEFINED_NAME,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 26. "UNDEFINED_NAME,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 25. "UNDEFINED_NAME,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x10 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x10 0.--3. "UNDEFINED_NAME,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
group.long 0x44++0x0F
line.long 0x00 "GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 12. "UNDEFINED_NAME,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 11. "UNDEFINED_NAME,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 10. "UNDEFINED_NAME,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 9. "UNDEFINED_NAME,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 8. "UNDEFINED_NAME,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 7. "UNDEFINED_NAME,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 6. "UNDEFINED_NAME,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 5. "UNDEFINED_NAME,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x04 4. "UNDEFINED_NAME,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 3. "UNDEFINED_NAME,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2. "UNDEFINED_NAME,Audio mute in [AMUTEIN] polarity select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,AMUTE pin enable bit [unless overridden by GPIO registers]" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Loopback generator mode bits" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 1. "UNDEFINED_NAME,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Loopback mode enable bit" "en_1_0x0,en_2_0x1"
line.long 0x0C "DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Valid bit for odd time slots [DIT right subframe]" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 2. "UNDEFINED_NAME,Valid bit for even time slots [DIT left subframe]" "en_1_0x0,en_2_0x1"
rbitfld.long 0x0C 1. "UNDEFINED_NAME," "0,1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,DIT mode enable bit" "en_1_0x0,en_2_0x1"
group.long 0x60++0x2F
line.long 0x00 "RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Receive bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 15. "UNDEFINED_NAME,Receive serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to the word" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 8.--12. "UNDEFINED_NAME,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Receive slot size" "en_7_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_5_0xA,en_1_0xB,en_4_0xC,en_2_0xD,en_6_0xE,en_3_0xF"
newline
bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for receive rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Receive frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Receive frame sync generation select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,Receive frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Receive bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x10 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Receive bit clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Receive high-frequency clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x14 14. "UNDEFINED_NAME,Receive bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Receive start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Receive data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 4. "UNDEFINED_NAME,Receive last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Receive DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 2. "UNDEFINED_NAME,Receive clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected receive frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 0. "UNDEFINED_NAME,Receiver overrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 7. "UNDEFINED_NAME,Receive DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Receive start of frame flag" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 5. "UNDEFINED_NAME,Receive data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Receive last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of RSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Receive clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected receive frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Receiver overrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--8. 1. "UNDEFINED_NAME,"
line.long 0x28 "RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Receive clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Receive clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Receive data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0xA0++0x2F
line.long 0x00 "XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "0,1"
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rbitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Transmit sync bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 15. "UNDEFINED_NAME,Transmit serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to word defined by XMASK" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 8.--12. "UNDEFINED_NAME,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Transmit slot size" "en_2_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_7_0xA,en_5_0xB,en_6_0xC,en_3_0xD,en_1_0xE,en_4_0xF"
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bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for transmit rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Transmit frame sync mode select bits"
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rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Transmit frame sync generation select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,Transmit frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Transmit bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 6. "UNDEFINED_NAME,Transmit/receive operation asynchronous enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Transmit bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Transmit high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Transmit bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Transmit start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Transmit data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Transmit DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Transmit clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected transmit frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Transmitter underrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Transmit DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Transmit start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Transmit data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Transmit last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of XSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Transmit clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected transmit frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Transmitter underrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--9. 1. "UNDEFINED_NAME,Current transmit time slot count"
line.long 0x28 "XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Transmit clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Transmit clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Transmit data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
group.long 0x180++0x3F
line.long 0x00 "SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x00 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x04 "SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x04 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x04 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x08 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x08 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x08 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x0C "SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x0C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x0C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x0C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x10 "SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x10 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x10 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x10 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x14 "SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x14 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x14 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x14 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x14 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x14 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x18 "SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x18 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x18 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x18 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x18 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x18 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x1C "SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x1C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x1C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x1C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x20 "SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x20 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x20 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x20 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x20 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x24 "SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x24 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x24 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x24 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x24 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x24 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x28 "SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x28 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x28 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x28 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x28 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x28 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x2C "SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x2C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x2C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x2C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x2C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x2C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x30 "SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x30 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x30 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x30 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x30 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x30 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x34 "SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x34 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x34 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x34 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x34 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x34 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x38 "SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x38 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x38 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x38 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x38 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x38 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x3C "SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x3C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x3C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x3C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x3C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x3C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x1000++0x0F
line.long 0x00 "WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 16. "UNDEFINED_NAME,Write FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
hexmask.long.byte 0x00 8.--15. 1. "UNDEFINED_NAME,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "UNDEFINED_NAME,Write word count per transfer [32 bit words]"
line.long 0x04 "WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x04 0.--7. "UNDEFINED_NAME,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16. "UNDEFINED_NAME,Read FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
abitfld.long 0x08 8.--15. "UNDEFINED_NAME,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "UNDEFINED_NAME,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x0C 0.--7. "UNDEFINED_NAME,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
width 0x0B
tree.end
tree "RCSS_MCASP_C (RCSS McASP C Module Registers)"
base ad:0x55220000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 2.--5. "UNDEFINED_NAME,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Power management Configuration of the local target state management mode" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x10++0x13
line.long 0x00 "PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "UNDEFINED_NAME,Determines if AFSR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 28. "UNDEFINED_NAME,Determines if AFSX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x00 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x00 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x04 "PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "UNDEFINED_NAME,Determines if AFSR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 28. "UNDEFINED_NAME,Determines if AFSX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as an input or output" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x04 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as an input or output" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x08 "PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "UNDEFINED_NAME,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 30. "UNDEFINED_NAME,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 29. "UNDEFINED_NAME,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 28. "UNDEFINED_NAME,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 27. "UNDEFINED_NAME,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 26. "UNDEFINED_NAME,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 25. "UNDEFINED_NAME,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x08 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x0C "PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "UNDEFINED_NAME,Logic level on AFSR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 30. "UNDEFINED_NAME,Logic level on AHCLKR pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 29. "UNDEFINED_NAME,Logic level on ACLKR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 28. "UNDEFINED_NAME,Logic level on AFSX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 27. "UNDEFINED_NAME,Logic level on AHCLKX pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 26. "UNDEFINED_NAME,Logic level on ACLKX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 25. "UNDEFINED_NAME,Logic level on AMUTE pin" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x0C 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x0C 0.--3. "UNDEFINED_NAME,Logic level on AXR[n] pin" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x10 "PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "UNDEFINED_NAME,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 30. "UNDEFINED_NAME,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 29. "UNDEFINED_NAME,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 28. "UNDEFINED_NAME,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 27. "UNDEFINED_NAME,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 26. "UNDEFINED_NAME,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 25. "UNDEFINED_NAME,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x10 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x10 0.--3. "UNDEFINED_NAME,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
group.long 0x44++0x0F
line.long 0x00 "GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 12. "UNDEFINED_NAME,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 11. "UNDEFINED_NAME,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 10. "UNDEFINED_NAME,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 9. "UNDEFINED_NAME,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 8. "UNDEFINED_NAME,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 7. "UNDEFINED_NAME,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 6. "UNDEFINED_NAME,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 5. "UNDEFINED_NAME,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x04 4. "UNDEFINED_NAME,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 3. "UNDEFINED_NAME,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2. "UNDEFINED_NAME,Audio mute in [AMUTEIN] polarity select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,AMUTE pin enable bit [unless overridden by GPIO registers]" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Loopback generator mode bits" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 1. "UNDEFINED_NAME,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Loopback mode enable bit" "en_1_0x0,en_2_0x1"
line.long 0x0C "DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Valid bit for odd time slots [DIT right subframe]" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 2. "UNDEFINED_NAME,Valid bit for even time slots [DIT left subframe]" "en_1_0x0,en_2_0x1"
rbitfld.long 0x0C 1. "UNDEFINED_NAME," "0,1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,DIT mode enable bit" "en_1_0x0,en_2_0x1"
group.long 0x60++0x2F
line.long 0x00 "RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Receive bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 15. "UNDEFINED_NAME,Receive serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to the word" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 8.--12. "UNDEFINED_NAME,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Receive slot size" "en_7_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_5_0xA,en_1_0xB,en_4_0xC,en_2_0xD,en_6_0xE,en_3_0xF"
newline
bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for receive rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Receive frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Receive frame sync generation select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,Receive frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Receive bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Receive bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Receive high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Receive bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Receive start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Receive data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Receive last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Receive DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Receive clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected receive frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Receiver overrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Receive DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Receive start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Receive data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Receive last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of RSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Receive clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected receive frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Receiver overrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--8. 1. "UNDEFINED_NAME,"
line.long 0x28 "RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Receive clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Receive clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Receive data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0xA0++0x2F
line.long 0x00 "XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "0,1"
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rbitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Transmit sync bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 15. "UNDEFINED_NAME,Transmit serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to word defined by XMASK" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 8.--12. "UNDEFINED_NAME,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Transmit slot size" "en_2_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_7_0xA,en_5_0xB,en_6_0xC,en_3_0xD,en_1_0xE,en_4_0xF"
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bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for transmit rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Transmit frame sync mode select bits"
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rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Transmit frame sync generation select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,Transmit frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Transmit bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 6. "UNDEFINED_NAME,Transmit/receive operation asynchronous enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Transmit bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Transmit high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Transmit bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Transmit start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Transmit data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Transmit DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Transmit clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected transmit frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Transmitter underrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Transmit DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Transmit start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Transmit data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Transmit last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of XSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Transmit clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected transmit frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Transmitter underrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--9. 1. "UNDEFINED_NAME,Current transmit time slot count"
line.long 0x28 "XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Transmit clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Transmit clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Transmit data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
group.long 0x180++0x3F
line.long 0x00 "SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x00 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x04 "SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x04 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x04 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x08 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x08 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x08 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x0C "SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x0C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x0C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x0C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x10 "SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x10 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x10 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x10 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x14 "SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x14 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x14 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x14 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x14 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x14 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x18 "SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x18 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x18 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x18 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x18 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x18 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x1C "SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x1C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x1C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x1C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x20 "SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x20 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x20 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x20 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x24 "SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x24 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x24 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x24 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x24 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x24 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x28 "SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x28 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x28 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x28 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x28 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x28 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x2C "SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x2C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x2C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x2C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x2C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x2C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x30 "SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x30 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x30 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x30 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x30 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x30 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x34 "SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x34 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x34 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x34 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x34 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x34 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x38 "SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x38 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x38 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x38 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x38 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x38 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x3C "SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x3C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x3C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x3C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x3C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x3C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x1000++0x0F
line.long 0x00 "WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 16. "UNDEFINED_NAME,Write FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
hexmask.long.byte 0x00 8.--15. 1. "UNDEFINED_NAME,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "UNDEFINED_NAME,Write word count per transfer [32 bit words]"
line.long 0x04 "WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x04 0.--7. "UNDEFINED_NAME,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16. "UNDEFINED_NAME,Read FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
abitfld.long 0x08 8.--15. "UNDEFINED_NAME,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "UNDEFINED_NAME,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x0C 0.--7. "UNDEFINED_NAME,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
width 0x0B
tree.end
tree "RCSS_PCR (RCSS PCR Module Registers)"
base ad:0x55F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "RCSS_RCM (RCSS RCM Module Registers)"
base ad:0x55000000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x12F
line.long 0x00 "RCSS_I2CA_CLK_SRC_SEL,"
hexmask.long.word 0x00 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS_I2CA"
line.long 0x04 "RCSS_I2CB_CLK_SRC_SEL,"
hexmask.long.word 0x04 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS I2CB"
line.long 0x08 "RCSS_SCIA_CLK_SRC_SEL,"
hexmask.long.word 0x08 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS SCIA"
line.long 0x0C "RCSS_SPIA_CLK_SRC_SEL,"
hexmask.long.word 0x0C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS_SPIA"
line.long 0x10 "RCSS_SPIB_CLK_SRC_SEL,"
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS SPIB"
line.long 0x14 "RCSS_ATL_CLK_SRC_SEL,"
hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS ATL CLK Data should be loaded as multibit"
line.long 0x18 "RCSS_MCASPA_REF0_CLK_SRC_SEL,"
hexmask.long.word 0x18 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPA REF0 CLK Data should be loaded as multibit"
line.long 0x1C "RCSS_MCASPA_REF1_CLK_SRC_SEL,"
hexmask.long.word 0x1C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPA REF1 CLK"
line.long 0x20 "RCSS_MCASPA_AUX_CLK_SRC_SEL,"
hexmask.long.word 0x20 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPA AUX CLK Data should be loaded as multibit"
line.long 0x24 "RCSS_MCASPB_REF0_CLK_SRC_SEL,"
hexmask.long.word 0x24 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPB REF0 CLK Data should be loaded as multibit"
line.long 0x28 "RCSS_MCASPB_REF1_CLK_SRC_SEL,"
hexmask.long.word 0x28 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPB REF1 CLK"
line.long 0x2C "RCSS_MCASPB_AUX_CLK_SRC_SEL,"
hexmask.long.word 0x2C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPB AUX CLK Data should be loaded as multibit"
line.long 0x30 "RCSS_MCASPC_REF0_CLK_SRC_SEL,"
hexmask.long.word 0x30 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPC REF0 CLK Data should be loaded as multibit"
line.long 0x34 "RCSS_MCASPC_REF1_CLK_SRC_SEL,"
hexmask.long.word 0x34 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPC REF1 CLK"
line.long 0x38 "RCSS_MCASPC_AUX_CLK_SRC_SEL,"
hexmask.long.word 0x38 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPC AUX CLK Data should be loaded as multibit"
line.long 0x3C "RCSS_I2CA_CLK_DIV_VAL,"
hexmask.long.word 0x3C 0.--11. 1. "clkdiv,Divider value for RCSS I2CA selected clock"
line.long 0x40 "RCSS_I2CB_CLK_DIV_VAL,"
hexmask.long.word 0x40 0.--11. 1. "clkdiv,Divider value for RCSS I2CB selected clock"
line.long 0x44 "RCSS_SCIA_CLK_DIV_VAL,"
hexmask.long.word 0x44 0.--11. 1. "clkdiv,Divider value for RCSS SCIA selected clock"
line.long 0x48 "RCSS_SPIA_CLK_DIV_VAL,"
hexmask.long.word 0x48 0.--11. 1. "clkdiv,Divider value for RCSS SPIA selected clock"
line.long 0x4C "RCSS_SPIB_CLK_DIV_VAL,"
hexmask.long.word 0x4C 0.--11. 1. "clkdiv,Divider value for RCSS SPIB selected clock"
line.long 0x50 "RCSS_ATL_CLK_DIV_VAL,"
hexmask.long.word 0x50 0.--11. 1. "clkdiv,Divider value for RCSS ATL CLK selected clock"
line.long 0x54 "RCSS_MCASPA_REF0_CLK_DIV_VAL,"
hexmask.long.word 0x54 0.--11. 1. "clkdiv,Divider value for RCSS MCASPA REF0 CLK selected clock"
line.long 0x58 "RCSS_MCASPA_REF1_CLK_DIV_VAL,"
hexmask.long.word 0x58 0.--11. 1. "clkdiv,Divider value for RCSS MCASPA REF1 CLK selected clock"
line.long 0x5C "RCSS_MCASPA_AUX_CLK_DIV_VAL,"
hexmask.long.word 0x5C 0.--11. 1. "clkdiv,Divider value for RCSS MCASPA AUX CLK selected clock"
line.long 0x60 "RCSS_MCASPB_REF0_CLK_DIV_VAL,"
hexmask.long.word 0x60 0.--11. 1. "clkdiv,Divider value for RCSS MCASPB REF0 CLK selected clock"
line.long 0x64 "RCSS_MCASPB_REF1_CLK_DIV_VAL,"
hexmask.long.word 0x64 0.--11. 1. "clkdiv,Divider value for RCSS MCASPB REF1 CLK selected clock"
line.long 0x68 "RCSS_MCASPB_AUX_CLK_DIV_VAL,"
hexmask.long.word 0x68 0.--11. 1. "clkdiv,Divider value for RCSS MCASPB AUX CLK selected clock"
line.long 0x6C "RCSS_MCASPC_REF0_CLK_DIV_VAL,"
hexmask.long.word 0x6C 0.--11. 1. "clkdiv,Divider value for RCSS MCASPC REF0 CLK selected clock"
line.long 0x70 "RCSS_MCASPC_REF1_CLK_DIV_VAL,"
hexmask.long.word 0x70 0.--11. 1. "clkdiv,Divider value for RCSS MCASPC REF1 CLK selected clock"
line.long 0x74 "RCSS_MCASPC_AUX_CLK_DIV_VAL,"
hexmask.long.word 0x74 0.--11. 1. "clkdiv,Divider value for RCSS MCASPC AUX CLK selected clock"
line.long 0x78 "RCSS_I2CA_CLK_GATE,"
bitfld.long 0x78 0.--2. "gated,Clock gatring config for RCSS I2CA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x7C "RCSS_I2CB_CLK_GATE,"
bitfld.long 0x7C 0.--2. "gated,Clock gatring config for RCSS I2CB Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x80 "RCSS_SCIA_CLK_GATE,"
bitfld.long 0x80 0.--2. "gated,Clock gatring config for RCSS SCIA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x84 "RCSS_SPIA_CLK_GATE,"
bitfld.long 0x84 0.--2. "gated,Clock gatring config for RCSS SPIA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x88 "RCSS_SPIB_CLK_GATE,"
bitfld.long 0x88 0.--2. "gated,Clock gatring config for RCSS SPIB Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x8C "RCSS_ATL_CLK_GATE,"
bitfld.long 0x8C 0.--2. "gated,Clock gatring config for RCSS ATL CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x90 "RCSS_MCASPA_REF0_CLK_GATE,"
bitfld.long 0x90 0.--2. "gated,Clock gatring config for RCSS MCASPA REF0 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x94 "RCSS_MCASPA_REF1_CLK_GATE,"
bitfld.long 0x94 0.--2. "gated,Clock gatring config for RCSS MCASPA REF1 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x98 "RCSS_MCASPA_AUX_CLK_GATE,"
bitfld.long 0x98 0.--2. "gated,Clock gatring config for RCSS MCASPA AUX CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x9C "RCSS_MCASPB_REF0_CLK_GATE,"
bitfld.long 0x9C 0.--2. "gated,Clock gatring config for RCSS MCASPB REF0 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xA0 "RCSS_MCASPB_REF1_CLK_GATE,"
bitfld.long 0xA0 0.--2. "gated,Clock gatring config for RCSS MCASPB REF1 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xA4 "RCSS_MCASPB_AUX_CLK_GATE,"
bitfld.long 0xA4 0.--2. "gated,Clock gatring config for RCSS MCASPB AUX CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xA8 "RCSS_MCASPC_REF0_CLK_GATE,"
bitfld.long 0xA8 0.--2. "gated,Clock gatring config for RCSS MCASPC REF0 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xAC "RCSS_MCASPC_REF1_CLK_GATE,"
bitfld.long 0xAC 0.--2. "gated,Clock gatring config for RCSS MCASPC REF1 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xB0 "RCSS_MCASPC_AUX_CLK_GATE,"
bitfld.long 0xB0 0.--2. "gated,Clock gatring config for RCSS MCASPC AUX CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xB4 "RCSS_ECAP_SYS_CLK_GATE,"
bitfld.long 0xB4 0.--2. "gated,Clock gatring config for RCSS ECAP Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xB8 "RCSS_CSI2A_SYS_CLK_GATE,"
bitfld.long 0xB8 0.--2. "gated,Clock gatring config for RCSS CSI2A Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xBC "RCSS_CSI2B_SYS_CLK_GATE,"
bitfld.long 0xBC 0.--2. "gated,Clock gatring config for RCSS CSI2B Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xC0 "RCSS_I2CA_CLK_STATUS,"
hexmask.long.byte 0xC0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS I2CA Clock"
hexmask.long.byte 0xC0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS I2CA Clock"
line.long 0xC4 "RCSS_I2CB_CLK_STATUS,"
hexmask.long.byte 0xC4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS I2CB Clock"
hexmask.long.byte 0xC4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS I2CB Clock"
line.long 0xC8 "RCSS_SCIA_CLK_STATUS,"
hexmask.long.byte 0xC8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS SCIA Clock"
hexmask.long.byte 0xC8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS SCIA Clock"
line.long 0xCC "RCSS_SPIA_CLK_STATUS,"
hexmask.long.byte 0xCC 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS SPIA Clock"
hexmask.long.byte 0xCC 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS SPIA Clock"
line.long 0xD0 "RCSS_SPIB_CLK_STATUS,"
hexmask.long.byte 0xD0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS SPIB Clock"
hexmask.long.byte 0xD0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS SPIB Clock"
line.long 0xD4 "RCSS_ATL_CLK_STATUS,"
hexmask.long.byte 0xD4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS ATL_CLK Clock"
hexmask.long.byte 0xD4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS ATL_CLK Clock"
line.long 0xD8 "RCSS_MCASPA_REF0_CLK_STATUS,"
hexmask.long.byte 0xD8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPA_REF0_CLK Clock"
hexmask.long.byte 0xD8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPA_REF0_CLK Clock"
line.long 0xDC "RCSS_MCASPA_REF1_CLK_STATUS,"
hexmask.long.byte 0xDC 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPA_REF1_CLK Clock"
hexmask.long.byte 0xDC 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPA_REF1_CLK Clock"
line.long 0xE0 "RCSS_MCASPA_AUX_CLK_STATUS,"
hexmask.long.byte 0xE0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPA_AUX_CLK Clock"
hexmask.long.byte 0xE0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPA_AUX_CLK Clock"
line.long 0xE4 "RCSS_MCASPB_REF0_CLK_STATUS,"
hexmask.long.byte 0xE4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPB_REF0_CLK Clock"
hexmask.long.byte 0xE4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPB_REF0_CLK Clock"
line.long 0xE8 "RCSS_MCASPB_REF1_CLK_STATUS,"
hexmask.long.byte 0xE8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPB_REF1_CLK Clock"
hexmask.long.byte 0xE8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPB_REF1_CLK Clock"
line.long 0xEC "RCSS_MCASPB_AUX_CLK_STATUS,"
hexmask.long.byte 0xEC 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPB_AUX_CLK Clock"
hexmask.long.byte 0xEC 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPB_AUX_CLK Clock"
line.long 0xF0 "RCSS_MCASPC_REF0_CLK_STATUS,"
hexmask.long.byte 0xF0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPC_REF0_CLK Clock"
hexmask.long.byte 0xF0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPC_REF0_CLK Clock"
line.long 0xF4 "RCSS_MCASPC_REF1_CLK_STATUS,"
hexmask.long.byte 0xF4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPC_REF1_CLK Clock"
hexmask.long.byte 0xF4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPC_REF1_CLK Clock"
line.long 0xF8 "RCSS_MCASPC_AUX_CLK_STATUS,"
hexmask.long.byte 0xF8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPC_AUX_CLK Clock"
hexmask.long.byte 0xF8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPC_AUX_CLK Clock"
line.long 0xFC "RCSS_ECAP_RST_CTRL,"
bitfld.long 0xFC 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x100 "RCSS_CSI2A_RST_CTRL,"
bitfld.long 0x100 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x104 "RCSS_CSI2B_RST_CTRL,"
bitfld.long 0x104 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x108 "RCSS_I2CA_RST_CTRL,"
bitfld.long 0x108 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x10C "RCSS_I2CB_RST_CTRL,"
bitfld.long 0x10C 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x110 "RCSS_SCIA_RST_CTRL,"
bitfld.long 0x110 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x114 "RCSS_SPIA_RST_CTRL,"
bitfld.long 0x114 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x118 "RCSS_SPIB_RST_CTRL,"
bitfld.long 0x118 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x11C "RCSS_MCASPA_RST_CTRL,"
bitfld.long 0x11C 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x120 "RCSS_MCASPB_RST_CTRL,"
bitfld.long 0x120 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x124 "RCSS_MCASPC_RST_CTRL,"
bitfld.long 0x124 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x128 "RCSS_GIO_RST_CTRL,"
bitfld.long 0x128 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x12C "RCSS_EDMA_RST_CTRL,"
bitfld.long 0x12C 12.--14. "tptca1_assert,writing '111' will reset MSS_TPTCA0" "0,1,2,3,4,5,6,7"
bitfld.long 0x12C 8.--10. "tptca0_assert,writing '111' will reset MSS_TPCCA" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x12C 4.--6. "tpcca_assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
bitfld.long 0x12C 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "RCSS_SCI_A (RCSS SCIA Module Registers)"
base ad:0x550C0000
group.long 0x00++0x07
line.long 0x00 "UARTDR,Data Register. UARTDR"
hexmask.long.tbyte 0x00 12.--31. 1. "NU0,Reserved"
bitfld.long 0x00 11. "OE,Overrun error" "0,1"
newline
bitfld.long 0x00 10. "BE,Break error" "0,1"
bitfld.long 0x00 9. "PE,Parity error" "0,1"
newline
bitfld.long 0x00 8. "FE,Framing error" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive data character & Transmit data character"
line.long 0x04 "UARTRSR_ECR,Receive Status Register/Error Clear Register."
hexmask.long 0x04 4.--31. 1. "NU1,Reserved unpredictable when"
bitfld.long 0x04 3. "OE,Overrun error" "0,1"
newline
bitfld.long 0x04 2. "BE,Break error" "0,1"
bitfld.long 0x04 1. "PE,Parity error" "0,1"
newline
bitfld.long 0x04 0. "FE,Framing error" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "UARTFR,Flag Register. UARTFR"
hexmask.long.tbyte 0x00 9.--31. 1. "NU2,Reserved do not modify read as zero"
bitfld.long 0x00 8. "RI,Ring indicator" "0,1"
newline
bitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1"
bitfld.long 0x00 6. "RXFF,Receive FIFO full" "0,1"
newline
bitfld.long 0x00 5. "TXFF,Transmit FIFO full" "0,1"
bitfld.long 0x00 4. "RXFE,Receive FIFO empty" "0,1"
newline
bitfld.long 0x00 3. "BUSY,UART busy" "0,1"
bitfld.long 0x00 2. "DCD,Data carrier detect" "0,1"
newline
bitfld.long 0x00 1. "DSR,Data set ready" "0,1"
bitfld.long 0x00 0. "CTS,Clear to send" "0,1"
group.long 0x20++0x2B
line.long 0x00 "UARTILPR,IrDA Low-Power Counter Register. UARTILPR"
hexmask.long.tbyte 0x00 8.--31. 1. "NU3,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "ILPDVSR,8-bit low-power divisor value"
line.long 0x04 "UARTIBRD,Integer Baud Rate Register. UARTIBRD"
hexmask.long.tbyte 0x04 8.--31. 1. "NU4,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "BAUD_DIVINT,The fractional baud rate divisor"
line.long 0x08 "UARTFBRD,Fractional Baud Rate Register. UARTFBRD"
hexmask.long 0x08 6.--31. 1. "NU5,Reserved"
bitfld.long 0x08 0.--5. "BAUD_DIVFRAC,The fractional baud rate divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "UARTLCR_H,Line Control Register. UARTLCR_H"
hexmask.long.tbyte 0x0C 8.--31. 1. "NU6,Reserved do not modify read as zero"
bitfld.long 0x0C 7. "SPS,Stick parity select" "stick parity is disabled,if the EPS bit is 0 then the parity bit is.."
newline
bitfld.long 0x0C 5.--6. "WLEN,Word length" "5 bits,6 bits,7 bits,8 bits"
bitfld.long 0x0C 4. "FEN,Enable FIFOs" "FIFOs are disabled (character mode) that is the..,transmit and receive FIFO buffers are enabled.."
newline
bitfld.long 0x0C 3. "STP2,Two stop bits select" "0,1"
bitfld.long 0x0C 2. "EPS,Even parity select" "odd parity,even parity"
newline
bitfld.long 0x0C 1. "PEN,Parity enable" "parity is disabled and no parity bit added to..,parity checking and generation is enabled"
bitfld.long 0x0C 0. "BRK,Send break" "0,1"
line.long 0x10 "UARTCR,Control Register. UARTCR"
hexmask.long.word 0x10 16.--31. 1. "NU7,Reserved do not modify read as zero"
bitfld.long 0x10 15. "CTSEn,CTS hardware flow control enable" "0,1"
newline
bitfld.long 0x10 14. "RTSEn,RTS hardware flow control enable" "0,1"
bitfld.long 0x10 13. "Out2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output" "0,1"
newline
bitfld.long 0x10 12. "Out1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output" "0,1"
bitfld.long 0x10 11. "RTS,Request to send" "0,1"
newline
bitfld.long 0x10 10. "DTR,Data transmit ready" "0,1"
bitfld.long 0x10 9. "RXE,Receive enable" "0,1"
newline
bitfld.long 0x10 8. "TXE,Transmit enable" "0,1"
bitfld.long 0x10 7. "LBE,Loopback enable" "0,1"
newline
rbitfld.long 0x10 3.--6. "NU6,Reserved do not modify read as zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 2. "SIRLP,SIR low-power IrDA mode" "0,1"
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bitfld.long 0x10 1. "SIREN,SIR enable" "IrDA SIR ENDEC is disabled,IrDA SIR ENDEC is enabled"
bitfld.long 0x10 0. "UARTEN,UART enable" "UART is disabled,the UART is enabled"
line.long 0x14 "UARTIFLS,Interrupt FIFO Level Select Register. UARTIFLS"
hexmask.long 0x14 6.--31. 1. "NU8,Reserved do not modify read as zero"
bitfld.long 0x14 3.--5. "RXIFLSEL,Receive interrupt FIFO level select" "Receive FIFO becomes >= 1/8 full,Receive FIFO becomes >= 1/4 full,Receive FIFO becomes >= 1/2 full,Receive FIFO becomes >= 3/4 full,Receive FIFO becomes >= 7/8 full b101-b111 =..,?..."
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bitfld.long 0x14 0.--2. "TXIFLSEL,Transmit interrupt FIFO level select" "Transmit FIFO becomes <= 1/8 full,Transmit FIFO becomes <= 1/4 full,Transmit FIFO becomes <= 1/2 full,Transmit FIFO becomes <= 3/4 full,Transmit FIFO becomes <= 7/8 full b101-b111 =..,?..."
line.long 0x18 "UARTIMSC,Interrupt Mask Set/Clear Register. UARTIMSC"
hexmask.long.tbyte 0x18 11.--31. 1. "NU9,Reserved read as zero do not modify"
bitfld.long 0x18 10. "OEIM,Overrun error interrupt mask" "0,1"
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bitfld.long 0x18 9. "BEIM,Break error interrupt mask" "0,1"
bitfld.long 0x18 8. "PEIM,Parity error interrupt mask" "0,1"
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bitfld.long 0x18 7. "FEIM,Framing error interrupt mask" "0,1"
bitfld.long 0x18 6. "RTIM,Receive timeout interrupt mask" "0,1"
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bitfld.long 0x18 5. "TXIM,Transmit interrupt mask" "0,1"
bitfld.long 0x18 4. "RXIM,Receive interrupt mask" "0,1"
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bitfld.long 0x18 3. "DSRMIM,nUARTDSR modem interrupt mask" "0,1"
bitfld.long 0x18 2. "DCDMIM,nUARTDCD modem interrupt mask" "0,1"
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bitfld.long 0x18 1. "CTSMIM,nUARTCTS modem interrupt mask" "0,1"
bitfld.long 0x18 0. "RIMIM,nUARTRI modem interrupt mask" "0,1"
line.long 0x1C "UARTRIS,Raw Interrupt Status Register. UARTRIS"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU10,Reserved read as zero do not modify"
bitfld.long 0x1C 9. "OERIS,Overrun error interrupt status" "0,1"
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bitfld.long 0x1C 8. "PERIS,Parity error interrupt status" "0,1"
bitfld.long 0x1C 7. "FERIS,Framing error interrupt status" "0,1"
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bitfld.long 0x1C 6. "RTRIS,Receive timeout interrupt status" "0,1"
bitfld.long 0x1C 5. "TXRIS,Transmit interrupt status" "0,1"
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bitfld.long 0x1C 4. "RXRIS,Receive interrupt status" "0,1"
bitfld.long 0x1C 3. "DSRRMIS,nUARTDSR modem interrupt status" "0,1"
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bitfld.long 0x1C 2. "DCDRMIS,nUARTDCD modem interrupt status" "0,1"
bitfld.long 0x1C 1. "CTSRMIS,nUARTCTS modem interrupt status" "0,1"
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bitfld.long 0x1C 0. "RIRMIS,nUARTRI modem interrupt status" "0,1"
line.long 0x20 "UARTMIS,Masked Interrupt Status Register. UARTMIS"
hexmask.long.tbyte 0x20 11.--31. 1. "NU11,Reserved read as zero do not modify"
bitfld.long 0x20 10. "OEMIS,Overrun error masked interrupt status" "0,1"
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bitfld.long 0x20 9. "BEMIS,Break error masked interrupt status" "0,1"
bitfld.long 0x20 8. "PEMIS,Parity error masked interrupt status" "0,1"
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bitfld.long 0x20 7. "FEMIS,Framing error masked interrupt status" "0,1"
bitfld.long 0x20 6. "RTMIS,Receive timeout masked interrupt status" "0,1"
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bitfld.long 0x20 5. "TXMIS,Transmit masked interrupt status" "0,1"
bitfld.long 0x20 4. "RXMIS,Receive masked interrupt status" "0,1"
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bitfld.long 0x20 3. "DSRMMIS,nUARTDSR modem masked interrupt status" "0,1"
bitfld.long 0x20 2. "DCDMMIS,nUARTDCD modem masked interrupt status" "0,1"
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bitfld.long 0x20 1. "CTSMMIS,nUARTCTS modem masked interrupt status" "0,1"
bitfld.long 0x20 0. "RIMMIS,nUARTRI modem masked" "0,1"
line.long 0x24 "UARTICR,Interrupt Clear Register. UARTICR"
hexmask.long.tbyte 0x24 11.--31. 1. "NU12,Reserved read as zero do not modify"
bitfld.long 0x24 10. "OEIC,Overrun error interrupt clear" "0,1"
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bitfld.long 0x24 9. "BEIC,Break error interrupt clear" "0,1"
bitfld.long 0x24 8. "PEIC,Parity error interrupt clear" "0,1"
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bitfld.long 0x24 7. "FEIC,Framing error interrupt clear" "0,1"
bitfld.long 0x24 6. "RTIC,Receive timeout interrupt clear" "0,1"
newline
bitfld.long 0x24 5. "TXIC,Transmit interrupt clear" "0,1"
bitfld.long 0x24 4. "RXIC,Receive interrupt clear" "0,1"
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bitfld.long 0x24 3. "DSRMIC,nUARTDSR modem interrupt clear" "0,1"
bitfld.long 0x24 2. "DCDMIC,nUARTDCD modem interrupt clear" "0,1"
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bitfld.long 0x24 1. "CTSMIC,nUARTCTS modem interrupt clear" "0,1"
bitfld.long 0x24 0. "RIMIC,nUARTRI modem interrupt clear" "0,1"
line.long 0x28 "UARTDMACR,DMA Control Register. UARTDMACR"
hexmask.long 0x28 3.--31. 1. "NU13,Reserved read as zero do not modify"
bitfld.long 0x28 2. "DMAONERR,DMA on error" "0,1"
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bitfld.long 0x28 1. "TXDMAE,Transmit DMA enable" "0,1"
bitfld.long 0x28 0. "RXDMAE,Receive DMA enable" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFF0)++0x03
line.long 0x00 "UARTPCellID$1,PrimeCell Identification Registers UARTPCellID0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "UARTPeriphID$1,Peripheral Identification Registers UARTPeriphID0"
repeat.end
width 0x0B
tree.end
tree "RCSS_SPIA (RCSS SPIA Module Registers)"
base ad:0x55F7E800
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
newline
rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
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bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
newline
bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
newline
bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
newline
rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
newline
bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
newline
bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
newline
hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
newline
bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
newline
bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
newline
rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
newline
bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
newline
rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
newline
bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
newline
bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
newline
bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
newline
bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
newline
bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
newline
abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
newline
rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
newline
bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
newline
bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
newline
bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
newline
abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
newline
abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
newline
rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
newline
bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
newline
bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
newline
bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
newline
abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
newline
bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
newline
bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
newline
bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
newline
bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
newline
abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
newline
rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
newline
bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
newline
bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
newline
bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
newline
abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
newline
rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
newline
bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
newline
bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
newline
bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
newline
abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
newline
rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
newline
bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
newline
bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
newline
bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
newline
abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
newline
abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
newline
rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
newline
bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
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bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
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rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
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rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
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bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
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bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
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hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
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bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
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rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "RCSS_SPIB (RCSS SPIB Module Registers)"
base ad:0x55F7EA00
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
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rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
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bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
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bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
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bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
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rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
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abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
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rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
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abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
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abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
newline
bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
newline
bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
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abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
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rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
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bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
newline
bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
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rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
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rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
newline
bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
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bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
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hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
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bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
newline
rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "RCSS_TPCC_A (RCSS TPCCA Module Registers)"
base ad:0x55100000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
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bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
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bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
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bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
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bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
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bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
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bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
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bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
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bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
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bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
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bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
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bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
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bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
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bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
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bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
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bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
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bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
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bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
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bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
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bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
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bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
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bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
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bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
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bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
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hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
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hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
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bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
newline
bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
newline
bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
newline
bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
newline
bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
newline
bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
newline
bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
newline
bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
newline
bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
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bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
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bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
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bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
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bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
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bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
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bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
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bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
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bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
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bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
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bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
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bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
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bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x55160000 ad:0x55180000 )
tree "RCSS_TPTC_A$1 (RCSS TPTC A$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
tree "TOP_AURORA_TX (TOP AURORA TX Module Registers)"
base ad:0x53060000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
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bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
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bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x0F
line.long 0x00 "AURORA_TX_CONFIG,"
bitfld.long 0x00 16.--18. "NUM_LANES,Selects the number of lanes for trasnmission" "1 Lane,2 Lanes,?,?,?,?,?,8Lanes"
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bitfld.long 0x00 2. "STRICT_ALIGN,Enable Aurora Strict Alingment Rules" "0,1"
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bitfld.long 0x00 1. "PROTOCOL_SEL,Selects if the IP is in 8b/10b OR 64b/66b mode" "8b/10b,64b/66b"
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bitfld.long 0x00 0. "ENABLE,Selects if the IP is in 8b/10b OR 64b/66b mode" "8b/10b,64b/66b"
line.long 0x04 "AURORA_TX_LANE_MAP,"
bitfld.long 0x04 28.--31. "LANE7_MAP,These 3 bits determine the logical lane that is transported over the physical lane 7" "Logical lane 0 is transported over physical lane 7,Logical lane 1 is transported over physical lane 7,?,?,?,?,?,Logical lane 7 is transported over physical lane 7,?..."
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bitfld.long 0x04 24.--27. "LANE6_MAP,These 3 bits determine the logical lane that is transported over the physical lane 6" "Logical lane 0 is transported over physical lane 6,Logical lane 1 is transported over physical lane 6,?,?,?,?,?,Logical lane 7 is transported over physical lane 6,?..."
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bitfld.long 0x04 20.--23. "LANE5_MAP,These 3 bits determine the logical lane that is transported over the physical lane 5" "Logical lane 0 is transported over physical lane 5,Logical lane 1 is transported over physical lane 5,?,?,?,?,?,Logical lane 7 is transported over physical lane 5,?..."
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bitfld.long 0x04 16.--19. "LANE4_MAP,These 3 bits determine the logical lane that is transported over the physical lane 4" "Logical lane 0 is transported over physical lane 4,Logical lane 1 is transported over physical lane 4,?,?,?,?,?,Logical lane 7 is transported over physical lane 4,?..."
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bitfld.long 0x04 12.--15. "LANE3_MAP,These 3 bits determine the logical lane that is transported over the physical lane 3" "Logical lane 0 is transported over physical lane 3,Logical lane 1 is transported over physical lane 3,?,?,?,?,?,Logical lane 7 is transported over physical lane 3,?..."
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bitfld.long 0x04 8.--11. "LANE2_MAP,These 3 bits determine the logical lane that is transported over the physical lane 2" "Logical lane 0 is transported over physical lane 2,Logical lane 1 is transported over physical lane 2,?,?,?,?,?,Logical lane 7 is transported over physical lane 2,?..."
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bitfld.long 0x04 4.--7. "LANE1_MAP,These 3 bits determine the logical lane that is transported over the physical lane 1" "Logical lane 0 is transported over physical lane 1,Logical lane 1 is transported over physical lane 1,?,?,?,?,?,Logical lane 7 is transported over physical lane 1,?..."
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bitfld.long 0x04 0.--3. "LANE0_MAP,These 3 bits determine the logical lane that is transported over the physical lane 0" "Logical lane 0 is transported over physical lane 0,Logical lane 0 is transported over physical lane 1,?,?,?,?,?,Logical lane 7 is transported over physical lane 0,?..."
line.long 0x08 "AURORA_TX_UDP_CONFIG,"
bitfld.long 0x08 16.--20. "FRAME_HEADER_EN,Header Enable configuration" "Disable Header transmission,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Number of 32 bit Header to be transmmited,?..."
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bitfld.long 0x08 8. "BYPASS_EN,Writing a value of" "Normal Mode - Framing is done as per aurora..,Bypass the aurora protocol"
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bitfld.long 0x08 7. "TEST_PATTERN_EN,Writing a value of" "0,1"
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bitfld.long 0x08 6. "TWP_SYNC_COMPRESSION_EN,Writing a value of" "Disable the TWP padding packet filter,Enables the compression of incoming.."
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bitfld.long 0x08 5. "CRC_EN,Writing a value of" "Disable UDP CRC calculation,Enable the UDP CRC calculation"
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bitfld.long 0x08 4. "TWP_IDLE_FILTER_EN,Writing a value of" "Disable the TWP padding packet filter,Filters out the incoming TWP Padding Packet from.."
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bitfld.long 0x08 0.--1. "PACK_MODE_SEL,Configure to select AURORATX_UDP_SIZE format" "Number of TWP Packets,Number of Bytes,?,SW only"
line.long 0x0C "AURORA_TX_UDP_SIZE,"
group.long 0x64++0x0F
line.long 0x00 "AURORA_TX_UFC_MSG_CTRL,"
bitfld.long 0x00 0. "UFC_MSG_SENT_STS,This bit indicates that the message send triggered by the SEND_MSG bit has been completed" "No effect,Clears this bit"
line.long 0x04 "AURORA_TX_UFC_MESSAGE0,"
line.long 0x08 "AURORA_TX_UFC_MESSAGE1,"
line.long 0x0C "AURORA_TX_TWP_SYNC_CNT,"
hexmask.long.word 0x0C 0.--9. 1. "SYNC_CNT,Number of TWP Sync Packet that would be sent if AURORA_TX_UDP_CONFIG::A_TX_UDP_CONFIG_TWP_SYNC_COMPRESSION_EN is 0x1"
group.long 0x80++0x1F
line.long 0x00 "AURORA_TX_INITIALIZE_REQ,"
bitfld.long 0x00 1. "TX_INIT,The single bit input to trigger the initialization sequence" "0,1"
line.long 0x04 "AURORA_TX_UFC_MSG_REQ,"
bitfld.long 0x04 0. "SEND_MSG,The bit that triggers the controller to send the MESSAGE0 and MESSAGE1 register contents as a UFC packet" "0,1"
line.long 0x08 "AURORA_TX_FLUSH_REQ,"
bitfld.long 0x08 0. "TRIGGER,Selects the number of lanes for trasnmission" "1 Lane,2 Lanes"
line.long 0x0C "AURORA_TX_EOP_REQ,"
bitfld.long 0x0C 0. "TRIGGER,SW End of Packet trigger to aurora dataframer" "0,1"
line.long 0x10 "AURORA_TX_DATA_START_REQ,"
bitfld.long 0x10 1. "DATA_START,The single bit input to trigger the initialization sequence" "0,1"
line.long 0x14 "AURORA_TX_DATA_STOP_REQ,"
bitfld.long 0x14 1. "DATA_STOP,The single bit input to trigger the Start of Data Transmission" "0,1"
line.long 0x18 "AURORA_TX_TESTPATTERN_START_REQ,"
bitfld.long 0x18 1. "TEST_PATTERN_START,The single bit input to trigger the Stop of Data Transmission" "0,1"
line.long 0x1C "AURORA_TX_TESTPATTERN_STOP_REQ,"
bitfld.long 0x1C 1. "TEST_PATTERN_STOP,The single bit input to trigger the Start of TestPattern Transmission" "0,1"
group.long 0x100++0x1F
line.long 0x00 "AURORA_TX_OVERRIDE,"
bitfld.long 0x00 22. "CC1_OVR_TYP,This read write bit indicates whether the CC1_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 21. "CC0_OVR_TYP,This read write bit indicates whether the CC0_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 20. "INIT_V3_OVR_TYP,This read write bit indicates whether the INIT_V3_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 19. "INIT_V2_OVR_TYP,This read write bit indicates whether the INIT_V2_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 18. "INIT_V1_OVR_TYP,This read write bit indicates whether the INIT_V1_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 17. "INIT_V0_OVR_TYP,This read write bit indicates whether the INIT_V0_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 16. "INIT_SP3_OVR_TYP,This read write bit indicates whether the INIT_SP3_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 15. "INIT_SP2_OVR_TYP,This read write bit indicates whether the INIT_SP2_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 14. "INIT_SP1_OVR_TYP,This read write bit indicates whether the INIT_SP1_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 13. "INIT_SP0_OVR_TYP,This read write bit indicates whether the INIT_SP0_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 12. "UFC_SUF_OVR_TYP,This read write bit indicates whether the UFC_SUF_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 11. "I2_OVR_TYP,This read write bit indicates whether the I2_OVR symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 10. "I1_OVR_TYP,This read write bit indicates whether the I1_OVR symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 9. "I0_OVR_TYP,This read write bit indicates whether the I0_OVR symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 8. "SYM_OVR_EN,This read write bit allows the symbols used in the various sequences to be overridden with the values used in the AURORA_TX_SYM register" "0,1"
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bitfld.long 0x00 4.--7. "TX_STATE_OVR_VAL,These bits take effect to enforce a certain transmission state if the TX_ST_OVR_EN bit is set" "Reset no transmission,Initialization,Clock Compensation,Idle,UFC,Run (data),Test (data),Reserved,?,?,?,?,?,?,?,Reserved"
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bitfld.long 0x00 0. "TX_STATE_OVR_EN,This read write bit allows the user to force the IP to remain in a given transmission state" "0,1"
line.long 0x04 "AURORA_TX_8B10B_OVERRIDE0,"
hexmask.long.byte 0x04 24.--31. 1. "UFC_SUF,The 8B/10B protocol defines Start of User Flow Control PDU symbol /SUF/"
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hexmask.long.byte 0x04 16.--23. 1. "I2,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence"
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hexmask.long.byte 0x04 8.--15. 1. "I1,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence"
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hexmask.long.byte 0x04 0.--7. 1. "I0,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence"
line.long 0x08 "AURORA_TX_8B10B_OVERRIDE1,"
hexmask.long.byte 0x08 24.--31. 1. "SP3,The 8B/10B protocol defines the /D10.2/ as the fourth octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
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hexmask.long.byte 0x08 16.--23. 1. "SP2,The 8B/10B protocol defines the /D10.2/ as the third octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
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hexmask.long.byte 0x08 8.--15. 1. "SP1,The 8B/10B protocol defines the /D10.2/ as the second octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
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hexmask.long.byte 0x08 0.--7. 1. "SP0,The 8B/10B protocol defines the /K28.5/ as the first octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
line.long 0x0C "AURORA_TX_8B10B_OVERRIDE2,"
hexmask.long.byte 0x0C 24.--31. 1. "V3,The 8B/10B protocol defines the /D8.7/ as the fourth octet to be used in the Verification sequence during lane initialization"
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hexmask.long.byte 0x0C 16.--23. 1. "V2,The 8B/10B protocol defines the /D8.7/ as the third octet to be used in the Verification sequence during lane initialization"
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hexmask.long.byte 0x0C 8.--15. 1. "V1,The 8B/10B protocol defines the /D8.7/ as the second octet to be used in the Verification sequence during lane inititialization"
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hexmask.long.byte 0x0C 0.--7. 1. "V0,The 8B/10B protocol defines the /K28.5/ as the first octet to be used in the Verification sequence during lane inititialization"
line.long 0x10 "AURORA_TX_8B10B_OVERRIDE3,"
hexmask.long.byte 0x10 8.--15. 1. "CC1,The 8B/10B protocol defines the /K23.7/ as the second octet to be used in the Clock Compensation sequence"
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hexmask.long.byte 0x10 0.--7. 1. "CC0,The 8B/10B protocol defines the /K23.7/ as the first octet to be used in the Clock Compensation sequence"
line.long 0x14 "AURORA_TX_64B66B_OVERRIDE1,"
hexmask.long.byte 0x14 24.--31. 1. "CB_BITS,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Idle Blocks"
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hexmask.long.byte 0x14 16.--23. 1. "CB_BTF,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks"
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hexmask.long.byte 0x14 8.--15. 1. "IDLE_BITS,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Idle Blocks"
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hexmask.long.byte 0x14 0.--7. 1. "IDLE_BTF,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks"
line.long 0x18 "AURORA_TX_64B66B_OVERRIDE2,"
hexmask.long.byte 0x18 16.--23. 1. "CC_BITS,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Channel Bonding Blocks"
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hexmask.long.byte 0x18 8.--15. 1. "CC_BTF,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks"
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hexmask.long.byte 0x18 0.--7. 1. "UFC_BTF,The 64B/66B protocol defines the value of 0x2D as the BTF for the UFC code block"
line.long 0x1C "AURORA_TX_64B66B_OVERRIDE2,"
hexmask.long.byte 0x1C 8.--15. 1. "SEP7_BTF,The 64B/66B protocol defines the value of 0xE1 as the BTF for the Separator-7"
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hexmask.long.byte 0x1C 0.--7. 1. "SEP_BTF,The 64B/66B protocol defines the value of 0x1E as the BTF for the Separator"
group.long 0x124++0x57
line.long 0x00 "AURORA_TX_INIT_CNT_LRC,"
line.long 0x04 "AURORA_TX_INIT_CNT_ALIGN,"
bitfld.long 0x04 16.--19. "ALIGN_MUL,Alignment pattern multiplier" "Alignment pattern multiplier is 32,Reserved,Reserved,Reserved,Reserved,?..."
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hexmask.long.word 0x04 0.--12. 1. "ALIGN_LEN,The number of times the Aurora alignment pattern is sent"
line.long 0x08 "AURORA_TX_INIT_CNT_BONDING,"
abitfld.long 0x08 20.--27. "rw,The 64B standard mentions that There must be at least four Idle blocks between each Channel Bonding block" "0x01=No of Idle Blocks between Channel Bonding..,0x02=No of Idle Blocks between Channel Bonding..,0xFF=No of Idle Blocks between Channel Bonding.."
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bitfld.long 0x08 16.--19. "BOND_MUL,Bond pattern multiplier" "Bond pattern multiplier is 4,Reserved,?..."
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hexmask.long.word 0x08 0.--8. 1. "BOND_LEN,The number of times the Aurora bonding pattern is sent"
line.long 0x0C "AURORA_TX_INIT_CNT_VERIFY,"
bitfld.long 0x0C 16.--19. "VERIFY_MUL,Verify pattern multiplier" "Verify pattern multiplier is 4,Reserved,?..."
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hexmask.long.word 0x0C 0.--8. 1. "VERIFY_LEN,The number of times the Aurora verification pattern is sent"
line.long 0x10 "AURORA_TX_INIT_CTRL,"
bitfld.long 0x10 2. "TX_VERIFIED,The single bit input to trigger the transition from the verification state to the channel ready state" "0,1"
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bitfld.long 0x10 1. "TX_BONDED,The single bit input to trigger the transition from the bonding to the verification state" "0,1"
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bitfld.long 0x10 0. "TX_ALIGNED,The single bit input to trigger the Stop of TestPattern Transmission" "0,1"
line.long 0x14 "AURORA_TX_IDLE_CTRL,"
bitfld.long 0x14 2.--5. "SEED,The 4-bit value used to seed the pseudo random integer used in the idle sequence generator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "AURORA_TX_IDLE_REQ,"
bitfld.long 0x18 0. "SEND_IDLE,This bit is used to trigger the insertion of the IDLE sequence by the software" "0,1"
line.long 0x1C "AURORA_TX_CC_REQ,"
bitfld.long 0x1C 1. "SEND_CC,The single bit input that can trigger a CC sequence" "0,1"
line.long 0x20 "AURORA_TX_CC_CNT,"
hexmask.long.word 0x20 0.--15. 1. "SYNC_COUNT,The 16-bit count value used to indicate the number of code group octets after which the CC sequence should be transmitted"
line.long 0x24 "AURORA_TX_CB_STATUS,"
bitfld.long 0x24 0. "CB_COMP,This bit reflects the state of the Channel Bonding FSM" "No effect,Clears the bit"
line.long 0x28 "AURORA_TX_CB_REQ,"
bitfld.long 0x28 1. "SEND_CB,The single bit input that can trigger a Channel Bonding Block" "0,1"
line.long 0x2C "AURORA_TX_CB_CNT,"
hexmask.long.word 0x2C 0.--15. 1. "CB_COUNT,The 16-bit count value used to indicate the number of data blocks after which the Channel Bonding sequence should be transmitted"
line.long 0x30 "AURORA_TX_RESET_REQ,"
bitfld.long 0x30 0. "TX_RESET,The single bit input to reset the Tx process" "0,1"
line.long 0x34 "AURORA_TX_SERIALIZER_OVERRIDE0,"
line.long 0x38 "AURORA_TX_SERIALIZER_OVERRIDE1,"
line.long 0x3C "AURORA_TX_DATA_BYTE_REVERSE,"
bitfld.long 0x3C 1. "crc_byte_reverse_en,Enable Byte reversal on the CRC value" "0,1"
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bitfld.long 0x3C 0. "byte_reverse_en,Enable Byte reversal on the input data" "0,1"
line.long 0x40 "AURORA_TX_64B66B_SCRAMBLER_INIT0,"
line.long 0x44 "AURORA_TX_64B66B_SCRAMBLER_INIT1,"
bitfld.long 0x44 31. "load,Write 0x1 to loaf the scrambler lfsr init value" "0,1"
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hexmask.long 0x44 0.--25. 1. "val,Initial value in the LFSR scrambler bits[57:32]"
line.long 0x48 "AURORA_TX_TESTPATTERN_CTRL,"
bitfld.long 0x48 0. "ramp_en,Enable a ramp patten as the testpattern" "0,1"
line.long 0x4C "AURORA_TX_CC_SEQ_CNT,"
bitfld.long 0x4C 16.--19. "count_64b66b,Configure the number of 64b66b Clock Compensation block to be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x4C 0.--3. "count_8b10b,Configure the number of 8b10b Clock Compensation octets to be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "AURORA_TX_EOP_DELAY,"
bitfld.long 0x50 16. "enable,Write 0x1 to this fiel to enable the delay configured in AURORA_TX_EOP_DEALY::DELAY" "0,1"
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hexmask.long.word 0x50 0.--15. 1. "delay,Internal Delay between the Data Framer and the Controller Block to stall data to the controller and force IDLES to be inserted by the controller after an ECP of a UDP"
line.long 0x54 "AURORA_TX_FLUSH_DELAY,"
hexmask.long.byte 0x54 0.--7. 1. "delay,Write 0x1 to this fiel to enable the delay configured in AURORA_TX_EOP_DEALY::DELAY"
rgroup.long 0x200++0x27
line.long 0x00 "AURORA_TX_STATUS,"
abitfld.long 0x00 16.--31. "DATAFRAMER,Dataframer Status fields Bit" "0x0000=OFF,0x0001=INIT DONE,0x000A=TEST MODE,0x000B=DATA MODE,0x0010=Write on Full FIFO Bit,0x0011=Read on Empty FIFO Bits [20:18],0x0064=WAITING FOR GLOBAL FLUSH DONE,0x0065=FLUSH IN PROGRESS Bits [26:21]"
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bitfld.long 0x00 0.--3. "TX_STATE,These read only bits indicate the state of the transmitter in 8B/10B and 64B/66B" "Reset no transmission,Initialization,Clock Compensation,Idle,UFC,Run (data),Test (data),Reserved,?,?,?,?,?,?,?,Reserved The user must note.."
line.long 0x04 "AURORA_TX_INIT_STATUS,"
bitfld.long 0x04 4. "TX_CH_RDY,The status bit that indicates that the channel ready state has been reached" "0,1"
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bitfld.long 0x04 3. "TX_TXCB0,The status bit that indicates that the TX_ TXCB0 state has been completed" "0,1"
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bitfld.long 0x04 2. "TX_INIT0,The status bit that indicates that the TX_INIT0 state has been completed" "0,1"
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bitfld.long 0x04 1. "TX_RESET1,The status bit that indicates that the TX_RESET1 state has been completed" "0,1"
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bitfld.long 0x04 0. "TX_RESET0,The status bit that indicates that the TX_RESET0 state has been completed" "0,1"
line.long 0x08 "AURORA_TX_CC_STATUS,"
bitfld.long 0x08 0. "CC_COMP,This bit reflects the state of the CC FSM" "No effect,Clears the bit"
line.long 0x0C "AURORA_TX_IDLE_STATUS,"
bitfld.long 0x0C 0. "IDLE_COMP,This bit reflects the state of the IDLE FSM" "No effect,Clears the bit"
line.long 0x10 "AURORA_TX_INTAGG_MASK,"
bitfld.long 0x10 15. "int15,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 14. "int14,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 13. "int13,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 12. "int12,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 11. "int11,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 10. "int10,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 9. "int9,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 8. "int8,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 7. "int7,Mask Interrupt AURORA_TX_HEADER_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 6. "int6,Mask Interrupt AURORA_TX_EOP_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 5. "int5,Mask Interrupt DATA_STOP_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 4. "int4,Mask Interrupt AURORA_TX_CC_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 3. "int3,Mask Interrupt AURORA_TX_UFC_SENT" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 2. "int2,Mask Interrupt AURORA_TX_EXT_FLUSH_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 1. "int1,Mask Interrupt AURORA_TX_FLUSH_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 0. "int0,Mask Interrupt AURORA_TX_INIT_DONE" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x14 "AURORA_TX_INTAGG_STATUS,"
bitfld.long 0x14 15. "int15,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 14. "int14,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 13. "int13,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 12. "int12,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 11. "int11,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 10. "int10,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 9. "int9,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 8. "int8,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 7. "int7,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 6. "int6,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 5. "int5,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 4. "int4,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 3. "int3,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 2. "int2,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 1. "int1,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 0. "int0,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
line.long 0x18 "AURORA_TX_INTAGG_STATUS_RAW,"
bitfld.long 0x18 15. "int15,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 14. "int14,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 13. "int13,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 12. "int12,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 11. "int11,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 10. "int10,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 9. "int9,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 8. "int8,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 7. "int7,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 6. "int6,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 5. "int5,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 4. "int4,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 3. "int3,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 2. "int2,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 1. "int1,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 0. "int0,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
line.long 0x1C "AURORA_TX_ERRAGG_MASK,"
bitfld.long 0x1C 15. "err15,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 14. "err14,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 13. "err13,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 12. "err12,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 11. "err11,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 10. "err10,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 9. "err9,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 8. "err8,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 7. "err7,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 6. "err6,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 5. "err5,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 4. "err4,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 3. "err3,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 2. "err2,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 1. "err1,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 0. "err0,Mask error AURORA_TX_UFC_ERR" "Error is Unmasked,Error is Masked"
line.long 0x20 "AURORA_TX_ERRAGG_STATUS,"
bitfld.long 0x20 15. "err15,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 14. "err14,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 13. "err13,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 12. "err12,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 11. "err11,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 10. "err10,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 9. "err9,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 8. "err8,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 7. "err7,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 6. "err6,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 5. "err5,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 4. "err4,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 3. "err3,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 2. "err2,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 1. "err1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 0. "err0,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
line.long 0x24 "AURORA_TX_ERRAGG_STATUS_RAW,"
bitfld.long 0x24 15. "err15,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 14. "err14,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 13. "err13,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 12. "err12,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 11. "err11,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 10. "err10,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 9. "err9,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 8. "err8,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 7. "err7,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 6. "err6,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 5. "err5,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 4. "err4,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 3. "err3,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 2. "err2,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 1. "err1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 0. "err0,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
rgroup.long 0x230++0x03
line.long 0x00 "AURORA_TX_TPIU_DATA_PACKED,"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x228)++0x03
line.long 0x00 "AURORA_TX_SERIALIZER_STATUS$1,"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x24)++0x03
line.long 0x00 "AURORA_TX_UDP_FRAME_HEADER$1,"
repeat.end
width 0x0B
tree.end
tree "TOP_CTRL (TOP Control Module Registers)"
base ad:0x530E0000
rgroup.long 0x00++0x0F
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MDO_CTRL,"
bitfld.long 0x04 4. "SRC_SELECT,Select the source IP of LVDS Data" "Aurora on LVDS,CBUFF on LVDS"
bitfld.long 0x04 0. "AURORATX_SRC_SELECT,Select the TPIU source to TOP_AURORATX IP" "Measurement Data,Trace Data"
line.long 0x08 "PROBE_BUS_SEL0,"
line.long 0x0C "PROBE_BUS_SEL1,"
rgroup.long 0x21C++0x0B
line.long 0x00 "EFUSE_UID3,"
hexmask.long.tbyte 0x00 0.--23. 1. "val,EFUSE UID[120:96]"
line.long 0x04 "EFUSE_DEVICE_TYPE,"
hexmask.long.word 0x04 0.--15. 1. "val,EFUSE Device Type"
line.long 0x08 "EFUSE_FROM0_CHECKSUM,"
rgroup.long 0x400++0xA7
line.long 0x00 "EFUSE0_ROW_61,"
hexmask.long 0x00 0.--25. 1. "EFUSE0_ROW_61,Captures the EFUSE Value"
line.long 0x04 "EFUSE0_ROW_62,"
hexmask.long 0x04 0.--25. 1. "EFUSE0_ROW_62,Captures the EFUSE Value"
line.long 0x08 "EFUSE0_ROW_63,"
hexmask.long 0x08 0.--25. 1. "EFUSE0_ROW_63,Captures the EFUSE Value"
line.long 0x0C "EFUSE1_ROW_5,"
hexmask.long 0x0C 0.--25. 1. "EFUSE1_ROW_5,Captures the EFUSE Value"
line.long 0x10 "EFUSE1_ROW_6,"
hexmask.long 0x10 0.--25. 1. "EFUSE1_ROW_6,Captures the EFUSE Value"
line.long 0x14 "EFUSE1_ROW_7,"
hexmask.long 0x14 0.--25. 1. "EFUSE1_ROW_7,Captures the EFUSE Value"
line.long 0x18 "EFUSE1_ROW_8,"
hexmask.long 0x18 0.--25. 1. "EFUSE1_ROW_8,Captures the EFUSE Value"
line.long 0x1C "EFUSE1_ROW_9,"
hexmask.long 0x1C 0.--25. 1. "EFUSE1_ROW_9,Captures the EFUSE Value"
line.long 0x20 "EFUSE1_ROW_10,"
hexmask.long 0x20 0.--25. 1. "EFUSE1_ROW_10,Captures the EFUSE Value"
line.long 0x24 "EFUSE1_ROW_11,"
hexmask.long 0x24 0.--25. 1. "EFUSE1_ROW_11,Captures the EFUSE Value"
line.long 0x28 "EFUSE1_ROW_12,"
hexmask.long 0x28 0.--25. 1. "EFUSE1_ROW_12,Captures the EFUSE Value"
line.long 0x2C "EFUSE1_ROW_13,"
hexmask.long 0x2C 0.--25. 1. "EFUSE1_ROW_13,Captures the EFUSE Value"
line.long 0x30 "EFUSE1_ROW_14,"
hexmask.long 0x30 0.--25. 1. "EFUSE1_ROW_14,Captures the EFUSE Value"
line.long 0x34 "EFUSE1_ROW_15,"
hexmask.long 0x34 0.--25. 1. "EFUSE1_ROW_15,Captures the EFUSE Value"
line.long 0x38 "EFUSE1_ROW_16,"
hexmask.long 0x38 0.--25. 1. "EFUSE1_ROW_16,Captures the EFUSE Value"
line.long 0x3C "EFUSE1_ROW_17,"
hexmask.long 0x3C 0.--25. 1. "EFUSE1_ROW_17,Captures the EFUSE Value"
line.long 0x40 "EFUSE1_ROW_18,"
hexmask.long 0x40 0.--25. 1. "EFUSE1_ROW_18,Captures the EFUSE Value"
line.long 0x44 "EFUSE1_ROW_19,"
hexmask.long 0x44 0.--25. 1. "EFUSE1_ROW_19,Captures the EFUSE Value"
line.long 0x48 "EFUSE1_ROW_20,"
hexmask.long 0x48 0.--25. 1. "EFUSE1_ROW_20,Captures the EFUSE Value"
line.long 0x4C "EFUSE1_ROW_21,"
hexmask.long 0x4C 0.--25. 1. "EFUSE1_ROW_21,Captures the EFUSE Value"
line.long 0x50 "EFUSE1_ROW_22,"
hexmask.long 0x50 0.--25. 1. "EFUSE1_ROW_22,Captures the EFUSE Value"
line.long 0x54 "EFUSE1_ROW_23,"
hexmask.long 0x54 0.--25. 1. "EFUSE1_ROW_23,Captures the EFUSE Value"
line.long 0x58 "EFUSE1_ROW_24,"
hexmask.long 0x58 0.--25. 1. "EFUSE1_ROW_24,Captures the EFUSE Value"
line.long 0x5C "EFUSE1_ROW_25,"
hexmask.long 0x5C 0.--25. 1. "EFUSE1_ROW_25,Captures the EFUSE Value"
line.long 0x60 "EFUSE1_ROW_26,"
hexmask.long 0x60 0.--25. 1. "EFUSE1_ROW_26,Captures the EFUSE Value"
line.long 0x64 "EFUSE1_ROW_27,"
hexmask.long 0x64 0.--25. 1. "EFUSE1_ROW_27,Captures the EFUSE Value"
line.long 0x68 "EFUSE1_ROW_28,"
hexmask.long 0x68 0.--25. 1. "EFUSE1_ROW_28,Captures the EFUSE Value"
line.long 0x6C "EFUSE1_ROW_29,"
hexmask.long 0x6C 0.--25. 1. "EFUSE1_ROW_29,Captures the EFUSE Value"
line.long 0x70 "EFUSE1_ROW_30,"
hexmask.long 0x70 0.--25. 1. "EFUSE1_ROW_30,Captures the EFUSE Value"
line.long 0x74 "EFUSE1_ROW_31,"
hexmask.long 0x74 0.--25. 1. "EFUSE1_ROW_31,Captures the EFUSE Value"
line.long 0x78 "EFUSE1_ROW_32,"
hexmask.long 0x78 0.--25. 1. "EFUSE1_ROW_32,Captures the EFUSE Value"
line.long 0x7C "EFUSE1_ROW_33,"
hexmask.long 0x7C 0.--25. 1. "EFUSE1_ROW_33,Captures the EFUSE Value"
line.long 0x80 "EFUSE1_ROW_34,"
hexmask.long 0x80 0.--25. 1. "EFUSE1_ROW_34,Captures the EFUSE Value"
line.long 0x84 "EFUSE1_ROW_35,"
hexmask.long 0x84 0.--25. 1. "EFUSE1_ROW_35,Captures the EFUSE Value"
line.long 0x88 "EFUSE1_ROW_36,"
hexmask.long 0x88 0.--25. 1. "EFUSE1_ROW_36,Captures the EFUSE Value"
line.long 0x8C "EFUSE1_ROW_37,"
hexmask.long 0x8C 0.--25. 1. "EFUSE1_ROW_37,Captures the EFUSE Value"
line.long 0x90 "EFUSE1_ROW_38,"
hexmask.long 0x90 0.--25. 1. "EFUSE1_ROW_38,Captures the EFUSE Value"
line.long 0x94 "EFUSE1_ROW_39,"
hexmask.long 0x94 0.--25. 1. "EFUSE1_ROW_39,Captures the EFUSE Value"
line.long 0x98 "EFUSE1_ROW_40,"
hexmask.long 0x98 0.--25. 1. "EFUSE1_ROW_40,Captures the EFUSE Value"
line.long 0x9C "EFUSE1_ROW_41,"
hexmask.long 0x9C 0.--25. 1. "EFUSE1_ROW_41,Captures the EFUSE Value"
line.long 0xA0 "EFUSE1_ROW_42,"
hexmask.long 0xA0 0.--25. 1. "EFUSE1_ROW_42,Captures the EFUSE Value"
line.long 0xA4 "EFUSE1_ROW_43,"
hexmask.long 0xA4 0.--25. 1. "EFUSE1_ROW_43,Captures the EFUSE Value"
group.long 0x800++0x4B
line.long 0x00 "EFUSE_OVERRIDE_HSM_HALT_ON_ROM_ECC_ERR_EN,"
bitfld.long 0x00 4. "override_val,Override MMR value" "0,1"
bitfld.long 0x00 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x04 "EFUSE_OVERRIDE_MEM_MARGINCTRL,"
bitfld.long 0x04 28.--29. "brg_margin,Override MMR value" "0,1,2,3"
bitfld.long 0x04 24.--26. "brg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
newline
bitfld.long 0x04 20.--21. "byg_margin,Override MMR value" "0,1,2,3"
bitfld.long 0x04 16.--18. "byg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
newline
bitfld.long 0x04 12.--15. "gwg_margin,Override MMR value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 8.--10. "gwg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
newline
bitfld.long 0x04 4.--5. "glg_margin,Override MMR value" "0,1,2,3"
bitfld.long 0x04 0.--2. "glg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x08 "EFUSE_OVERRIDE_LVDS_BGAP_TRIM,"
bitfld.long 0x08 4.--9. "override_val,Override MMR value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x0C "EFUSE_OVERRIDE_XTAL_STABLIZATION_WAIT,"
bitfld.long 0x0C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x10 "EFUSE_OVERRIDE_SLICER_BIAS_RTRIM,"
bitfld.long 0x10 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x14 "EFUSE_OVERRIDE_XO_OUTPUT_DRIVE,"
bitfld.long 0x14 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x18 "EFUSE_OVERRIDE_RCOSC_TRIM_CODE,"
bitfld.long 0x18 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x1C "EFUSE_OVERRIDE_IP1_BG1_RTRIM,"
bitfld.long 0x1C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x20 "EFUSE_OVERRIDE_IP1_BG1_SLOPE,"
bitfld.long 0x20 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x24 "EFUSE_OVERRIDE_IP1_BG1_MAG,"
bitfld.long 0x24 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x28 "EFUSE_OVERRIDE_RS232_CLKMODE,"
bitfld.long 0x28 4. "override_val,Override value for RS232 Clock Mode" "Autobaud,Fixed Interval"
bitfld.long 0x28 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x2C "EFUSE_OVERRIDE_VMON_VDD_OV_UV_TRIM,"
bitfld.long 0x2C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x30 "EFUSE_OVERRIDE_VMON_VDDS_3P3_UV_TRIM,"
bitfld.long 0x30 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x34 "EFUSE_OVERRIDE_VMON_VDDA_OSC_TRIM,"
bitfld.long 0x34 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x38 "EFUSE_OVERRIDE_VDD_VT_DET,"
bitfld.long 0x38 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x3C "EFUSE_OVERRIDE_MASK_CPU_CLK_OUT_CTRL_LOWV_VAL,"
bitfld.long 0x3C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x40 "EFUSE_OVERRIDE_MASK_CPU_CLK_OUT_CTRL_LOWV_SEL,"
bitfld.long 0x40 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x44 "EFUSE_OVERRIDE_EN_VOL_MON_FUNC,"
bitfld.long 0x44 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x48 "EFUSE_OVERRIDE_BYPASS_HOLDBUFFER_ENABLE,"
bitfld.long 0x48 4. "override_val,Override value for Hold Buffer Enable" "Disabled,Enabled"
bitfld.long 0x48 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
rgroup.long ($2+0x228)++0x03
line.long 0x00 "EFUSE_ROM_SEQ_UPDATE$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x210)++0x03
line.long 0x00 "EFUSE_UID$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x200)++0x03
line.long 0x00 "EFUSE_DIEID$1,"
repeat.end
width 0x0B
tree.end
tree "TOP_MDO_INFRA (TOP MDO INFRA Module Registers)"
base ad:0x53080000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x14F
line.long 0x00 "SRC0_CTRL,"
bitfld.long 0x00 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x00 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x00 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x00 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x00 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x04 "SRC0_RANGE_START0,"
line.long 0x08 "SRC0_RANGE_END0,"
line.long 0x0C "SRC0_RANGE_START1,"
line.long 0x10 "SRC0_RANGE_END1,"
line.long 0x14 "SRC0_RANGE_START2,"
line.long 0x18 "SRC0_RANGE_END2,"
line.long 0x1C "SRC0_RANGE_START3,"
line.long 0x20 "SRC0_RANGE_END3,"
line.long 0x24 "SRC0_SW_TRIGGER,"
bitfld.long 0x24 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x24 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x28 "SRC0_THRESHOLD,"
hexmask.long.word 0x28 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x2C "SRC0_BW_CTRL,"
bitfld.long 0x2C 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x2C 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x2C 0. "write_mode," "0,1"
line.long 0x30 "SRC0_CHANNEL,"
line.long 0x34 "SRC0_CHANNEL_CFG,"
bitfld.long 0x34 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x34 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x34 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x34 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x34 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0x38 "SRC1_CTRL,"
bitfld.long 0x38 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x38 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x38 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x38 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x38 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x38 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x38 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x3C "SRC1_RANGE_START0,"
line.long 0x40 "SRC1_RANGE_END0,"
line.long 0x44 "SRC1_RANGE_START1,"
line.long 0x48 "SRC1_RANGE_END1,"
line.long 0x4C "SRC1_RANGE_START2,"
line.long 0x50 "SRC1_RANGE_END2,"
line.long 0x54 "SRC1_RANGE_START3,"
line.long 0x58 "SRC1_RANGE_END3,"
line.long 0x5C "SRC1_SW_TRIGGER,"
bitfld.long 0x5C 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x5C 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x60 "SRC1_THRESHOLD,"
hexmask.long.word 0x60 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x64 "SRC1_BW_CTRL,"
bitfld.long 0x64 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x64 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x64 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x64 0. "write_mode," "0,1"
line.long 0x68 "SRC1_CHANNEL,"
line.long 0x6C "SRC1_CHANNEL_CFG,"
bitfld.long 0x6C 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x6C 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x6C 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x6C 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x6C 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0x70 "SRC2_CTRL,"
bitfld.long 0x70 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x70 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x70 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x70 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x70 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x70 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x70 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x74 "SRC2_RANGE_START0,"
line.long 0x78 "SRC2_RANGE_END0,"
line.long 0x7C "SRC2_RANGE_START1,"
line.long 0x80 "SRC2_RANGE_END1,"
line.long 0x84 "SRC2_RANGE_START2,"
line.long 0x88 "SRC2_RANGE_END2,"
line.long 0x8C "SRC2_RANGE_START3,"
line.long 0x90 "SRC2_RANGE_END3,"
line.long 0x94 "SRC2_SW_TRIGGER,"
bitfld.long 0x94 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x94 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x98 "SRC2_THRESHOLD,"
hexmask.long.word 0x98 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x9C "SRC2_BW_CTRL,"
bitfld.long 0x9C 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x9C 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x9C 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x9C 0. "write_mode," "0,1"
line.long 0xA0 "SRC2_CHANNEL,"
line.long 0xA4 "SRC2_CHANNEL_CFG,"
bitfld.long 0xA4 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xA4 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0xA4 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xA4 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0xA4 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0xA8 "SRC3_CTRL,"
bitfld.long 0xA8 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0xA8 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0xA8 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xA8 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0xA8 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0xA8 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0xA8 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0xAC "SRC3_RANGE_START0,"
line.long 0xB0 "SRC3_RANGE_END0,"
line.long 0xB4 "SRC3_RANGE_START1,"
line.long 0xB8 "SRC3_RANGE_END1,"
line.long 0xBC "SRC3_RANGE_START2,"
line.long 0xC0 "SRC3_RANGE_END2,"
line.long 0xC4 "SRC3_RANGE_START3,"
line.long 0xC8 "SRC3_RANGE_END3,"
line.long 0xCC "SRC3_SW_TRIGGER,"
bitfld.long 0xCC 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0xCC 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0xD0 "SRC3_THRESHOLD,"
hexmask.long.word 0xD0 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0xD4 "SRC3_BW_CTRL,"
bitfld.long 0xD4 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0xD4 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0xD4 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0xD4 0. "write_mode," "0,1"
line.long 0xD8 "SRC3_CHANNEL,"
line.long 0xDC "SRC3_CHANNEL_CFG,"
bitfld.long 0xDC 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xDC 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0xDC 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xDC 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0xDC 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0xE0 "SRC4_CTRL,"
bitfld.long 0xE0 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0xE0 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0xE0 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xE0 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0xE0 4. "port_sel,Select which bus to capture" "DSS_HWA_DMA0,DSS_HWA_DMA1"
bitfld.long 0xE0 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
newline
bitfld.long 0xE0 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
bitfld.long 0xE0 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0xE4 "SRC4_RANGE_START0,"
line.long 0xE8 "SRC4_RANGE_END0,"
line.long 0xEC "SRC4_RANGE_START1,"
line.long 0xF0 "SRC4_RANGE_END1,"
line.long 0xF4 "SRC4_RANGE_START2,"
line.long 0xF8 "SRC4_RANGE_END2,"
line.long 0xFC "SRC4_RANGE_START3,"
line.long 0x100 "SRC4_RANGE_END3,"
line.long 0x104 "SRC4_SW_TRIGGER,"
bitfld.long 0x104 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x104 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x108 "SRC4_THRESHOLD,"
hexmask.long.word 0x108 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x10C "SRC4_BW_CTRL,"
bitfld.long 0x10C 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x10C 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x10C 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x10C 0. "write_mode," "0,1"
line.long 0x110 "SRC4_CHANNEL,"
line.long 0x114 "SRC4_CHANNEL_CFG,"
bitfld.long 0x114 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x114 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x114 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x114 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x114 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0x118 "SRC5_CTRL,"
bitfld.long 0x118 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x118 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x118 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x118 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x118 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x118 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x118 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x11C "SRC5_RANGE_START0,"
line.long 0x120 "SRC5_RANGE_END0,"
line.long 0x124 "SRC5_RANGE_START1,"
line.long 0x128 "SRC5_RANGE_END1,"
line.long 0x12C "SRC5_RANGE_START2,"
line.long 0x130 "SRC5_RANGE_END2,"
line.long 0x134 "SRC5_RANGE_START3,"
line.long 0x138 "SRC5_RANGE_END3,"
line.long 0x13C "SRC5_SW_TRIGGER,"
bitfld.long 0x13C 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x13C 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x140 "SRC5_THRESHOLD,"
hexmask.long.word 0x140 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x144 "SRC5_BW_CTRL,"
bitfld.long 0x144 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x144 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x144 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x144 0. "write_mode," "0,1"
line.long 0x148 "SRC5_CHANNEL,"
line.long 0x14C "SRC5_CHANNEL_CFG,"
bitfld.long 0x14C 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x14C 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x14C 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x14C 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x14C 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
group.long 0x1D4++0x1B
line.long 0x00 "SRC0_STATUS,"
hexmask.long.word 0x00 16.--31. 1. "status,Status of the Sniffer for Source 0"
bitfld.long 0x00 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x00 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x00 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x00 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x04 "SRC1_STATUS,"
hexmask.long.word 0x04 16.--31. 1. "status,Status of the Sniffer for Source 1"
bitfld.long 0x04 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x04 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x04 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x04 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x08 "SRC2_STATUS,"
hexmask.long.word 0x08 16.--31. 1. "status,Status of the Sniffer for Source 2"
bitfld.long 0x08 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x08 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x08 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x08 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x0C "SRC3_STATUS,"
hexmask.long.word 0x0C 16.--31. 1. "status,Status of the Sniffer for Source 3"
bitfld.long 0x0C 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x0C 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x0C 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x0C 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x10 "SRC4_STATUS,"
hexmask.long.word 0x10 16.--31. 1. "status,Status of the Sniffer for Source 4"
bitfld.long 0x10 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x10 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x10 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x10 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x14 "SRC5_STATUS,"
hexmask.long.word 0x14 16.--31. 1. "status,Status of the Sniffer for Source 5"
bitfld.long 0x14 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x14 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x14 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x14 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x18 "INTERRUPT_MASK,"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "proxy_err,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "addr_err,Addressing violation error" "0,1"
bitfld.long 0x08 0. "prot_err,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "enabled_proxy_err,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "enabled_kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "enabled_addr_err,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "fault_ns,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "fault_type,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "fault_xid,XID"
hexmask.long.word 0x24 8.--19. 1. "fault_routeid,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "fault_privid,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "fault_clr,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "TOP_PBIST (TOP PBIST Module Registers)"
base ad:0x52F79400
hgroup.long 0x120++0x07
hide.long 0x00 "PBIST_DD10,DD0 Data Register 16 (D0)"
hide.long 0x04 "PBIST_DE10,DE0 Data Register 16 (D0)"
group.long 0x160++0x03
line.long 0x00 "PBIST_RAMT,RAM Configuration (RAMT -RAM)"
hexmask.long.byte 0x00 24.--31. 1. "RGS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 16.--23. 1. "RDS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 8.--15. 1. "DWR,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 0.--7. 1. "RAM,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
group.word 0x164++0x01
line.word 0x00 "PBIST_DLR,Datalogger 0"
hexmask.word.byte 0x00 8.--15. 1. "DLR1,Datalogger Register [8] : Reserevd [9] : Default Testing Mode"
hexmask.word.byte 0x00 0.--7. 1. "DLR0,Datalogger Register [1:0] : Reserved [2] : ROM-based testing mode"
group.byte 0x168++0x00
line.byte 0x00 "PBIST_CMS,Clock mux select"
bitfld.byte 0x00 0.--3. "PBIST_CMS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x16C++0x00
line.byte 0x00 "PBIST_PC,Program Control"
bitfld.byte 0x00 0.--4. "PBIST_PC,TI Internal Register.Reserved for HW RnD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x178++0x03
line.long 0x00 "PBIST_CS,Chip Select 0"
hexmask.long.byte 0x00 24.--31. 1. "CS3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "CS2,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 8.--15. 1. "CS1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "CS0,TI Internal Register.Reserved for HW RnD"
group.byte 0x17C++0x00
line.byte 0x00 "PBIST_FDLY,Fail Delay"
group.byte 0x180++0x00
line.byte 0x00 "PBIST_PACT,Pbist Active"
bitfld.byte 0x00 0. "PBIST_PACT,Pbist Active/ROM Clock Enable Register [0]: This bit must be set to turn on internal PBIST clocks" "Disable internal PBIST clocks Value,Enable internal PBIST clocks"
group.byte 0x184++0x00
line.byte 0x00 "PBIST_ID,PBIST ID"
bitfld.byte 0x00 0.--4. "PBIST_ID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hgroup.long 0x188++0x03
hide.long 0x00 "PBIST_OVR,PBIST Overrides"
rgroup.byte 0x190++0x00
line.byte 0x00 "PBIST_FSFR0,Fail status fail - port 0"
bitfld.byte 0x00 0. "PBIST_FSFR0,Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x194++0x00
line.byte 0x00 "PBIST_FSFR1,Fail status fail - port 1"
bitfld.byte 0x00 0. "PBIST_FSFR1,Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x198++0x00
line.byte 0x00 "PBIST_FSRCR0,Fail Count fail - port 0"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR0,Fail Status Count - Port 0 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x19C++0x00
line.byte 0x00 "PBIST_FSRCR1,Fail Count fail - port 1"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR1,Fail Status Count - Port 1 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1A0++0x03
hide.long 0x00 "PBIST_FSRA0,Fail status address - port 0"
rgroup.word 0x1A4++0x01
line.word 0x00 "PBIST_FSRA1,Fail status address - port 1"
hgroup.long 0x1B4++0x0B
hide.long 0x00 "PBIST_MARGIN,Margin Mode"
hide.long 0x04 "PBIST_WRENZ,WRENZ"
hide.long 0x08 "PBIST_PGS,PAGE/PGS"
group.byte 0x1C0++0x00
line.byte 0x00 "PBIST_ROM,Rom Mask"
bitfld.byte 0x00 0.--1. "PBIST_ROM,Rom Mask" "No information is used from ROM Value,Only RAM Group information from ROM Vaule,Only Algorithm information from ROM Value,Both Algorithm and RAM information from ROM"
group.long 0x1C4++0x0B
line.long 0x00 "PBIST_ALGO,ROM Algorithm Mask 0"
hexmask.long.byte 0x00 24.--31. 1. "ALGO3,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 16.--23. 1. "ALGO2,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 8.--15. 1. "ALGO1,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 0.--7. 1. "ALGO0,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
line.long 0x04 "PBIST_RINFOL,RAM Info Mask Lower 0"
hexmask.long.byte 0x04 24.--31. 1. "RINFOL3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 16.--23. 1. "RINFOL2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 8.--15. 1. "RINFOL1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 0.--7. 1. "RINFOL0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
line.long 0x08 "PBIST_RINFOU,RAM Info Mask Upper 0"
hexmask.long.byte 0x08 24.--31. 1. "RINFOU3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 16.--23. 1. "RINFOU2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 8.--15. 1. "RINFOU1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 0.--7. 1. "RINFOU0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
repeat 2. (list 0. 1. )(list 0x00 0x08 )
rgroup.long ($2+0x1A8)++0x03
line.long 0x00 "PBIST_FSRDL$1,Fail status Data - port 0"
repeat.end
repeat 2. (list 1. 4. )(list 0x00 0x04 )
group.long ($2+0x170)++0x03
line.long 0x00 "PBIST_SCR$1,Address Scramble 0 -3"
hexmask.long.byte 0x00 24.--31. 1. "SCR3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "SCR2,TI Internal Register.Reserved for HW RnD"
newline
hexmask.long.byte 0x00 8.--15. 1. "SCR1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "SCR0,TI Internal Register.Reserved for HW RnD"
repeat.end
repeat 2. (list 2. 3. )(list 0x00 0x04 )
group.word ($2+0x158)++0x01
line.word 0x00 "PBIST_CI$1,Constant Increment Register2"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
hgroup.long ($2+0x150)++0x03
hide.long 0x00 "PBIST_CI$1,Constant Increment Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x140)++0x03
hide.long 0x00 "PBIST_CL$1,Constant Loop Count Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x130)++0x03
hide.long 0x00 "PBIST_CA$1,Constant Address Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x110)++0x03
hide.long 0x00 "PBIST_L$1,Variable Loop Count Register L0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x100)++0x03
hide.long 0x00 "PBIST_A$1,Variable Address Register0"
repeat.end
width 0x0B
tree.end
endif
sif (cpuis("AM2732")||cpuis("AM2732-HWA"))
tree "DSS_CBUFF (DSS CBUFF Module Registers)"
base ad:0x6040000
group.long 0x00++0x1B
line.long 0x00 "CONFIG_REG_0,Basic Config register"
bitfld.long 0x00 28.--31. "dbussel,TI Internal feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 27. "cswcrst,CBUFF controller SW Reset" "RELEASE RESET for CBUFF Controller,RESET the CBUFF Controller"
newline
bitfld.long 0x00 26. "cswlrst,TI Internal Feature" "RELEASE RESET,RESET the FSM"
newline
bitfld.long 0x00 25. "CFG_FRAME_START_TRIG,SW Trigger generation : Write 1 to this bit to generate a Frame Start SW Trigger" "0,1"
newline
bitfld.long 0x00 24. "CFG_CHIRP_AVAIL_TRIG,SW Trigger generation : Write 1 to this bit to generate a Chirp Available SW Trigger" "0,1"
newline
bitfld.long 0x00 20.--23. "CFG_VBUSP_BURST_EN,TI Internal Feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "dbusen,TC2 Mode selection" "Normal,When in TC2 mode.."
newline
bitfld.long 0x00 18. "ccfwpen,TI Internal Feature" "Use the fifo_free_words directly from CSI2 by..,Process the fifo_free_words and use it by.."
newline
bitfld.long 0x00 16.--17. "cvc3en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 3 is..,A VSYNC End packet on Virtual Channel 3 is..,A VSYNC Start packet on Virtual Channel 3 is.."
newline
bitfld.long 0x00 14.--15. "cvc2en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 2 is..,A VSYNC End packet on Virtual Channel 2 is..,A VSYNC Start packet on Virtual Channel 2 is.."
newline
bitfld.long 0x00 12.--13. "cvc1en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 1 is..,A VSYNC End packet on Virtual Channel 1 is..,A VSYNC Start packet on Virtual Channel 1 is.."
newline
bitfld.long 0x00 10.--11. "cvc0en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 0 is..,A VSYNC End packet on Virtual Channel 0 is..,A VSYNC Start packet on Virtual Channel 0 is.."
newline
bitfld.long 0x00 9. "crdthsel,TI Internal Feature" "The read threshold is selected based on the..,The read threshold is selected based on the Read.."
newline
bitfld.long 0x00 8. "ccfwlen,TI Internal Feature" "0,1"
newline
rbitfld.long 0x00 4.--7. "NU1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "CFG_SW_TRIG_EN,Select Chirp Available Trigger Source" "Chirp Available trigger will be generated by HW,Chirp Available trigger will be generated by SW"
newline
bitfld.long 0x00 2. "cftrigen,Select Frame Start Trigger Source" "Frame trigger will be generated by HW,Frame trigger will be generated by SW"
newline
bitfld.long 0x00 1. "CFG_ECC_EN," "0,1"
newline
bitfld.long 0x00 0. "CFG_1LVDS_0CSI," "0,1"
line.long 0x04 "CFG_SPHDR_ADDRESS,Short Packet Header Address"
line.long 0x08 "CFG_CMD_HSVAL,HSYNC Value"
line.long 0x0C "CFG_CMD_HEVAL,HEND Value"
line.long 0x10 "CFG_CMD_VSVAL,VSYNC Value"
line.long 0x14 "CFG_CMD_VEVAL,VEND Value"
line.long 0x18 "CFG_LPHDR_ADDRESS,Long Packet Address"
group.long 0x20++0x1D3
line.long 0x00 "CFG_CHIRPS_PER_FRAME,Number of Chirps per Frame"
line.long 0x04 "CFG_FIFO_FREE_THRESHOLD,CSI2 FIFO threshold for transferring data from CBUFF to CSI2"
hexmask.long.byte 0x04 24.--31. 1. "CFG_FIFO_FREE_THRESHOLD3,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO3 in the CSI Protocol engine"
newline
hexmask.long.byte 0x04 16.--23. 1. "CFG_FIFO_FREE_THRESHOLD2,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO2 in the CSI Protocol engine"
newline
hexmask.long.byte 0x04 8.--15. 1. "CFG_FIFO_FREE_THRESHOLD1,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO1 in the CSI Protocol engine"
newline
hexmask.long.byte 0x04 0.--7. 1. "CFG_FIFO_FREE_THRESHOLD0,CSI2 only Programming : Configure the threshold used to fill the FIFO0 in the CSI Protocol engine"
line.long 0x08 "CFG_LPPYLD_ADDRESS,Long payload Address"
line.long 0x0C "CFG_DELAY_CONFIG,Delay Config Registers"
hexmask.long.byte 0x0C 24.--31. 1. "NU,"
newline
hexmask.long.byte 0x0C 16.--23. 1. "CFG_DATA_WR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Long packet Payload"
newline
hexmask.long.byte 0x0C 8.--15. 1. "CFG_LPHDR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Long packet Header"
newline
hexmask.long.byte 0x0C 0.--7. 1. "CFG_SPHDR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Short packet"
line.long 0x10 "CFG_DATA_LL0,Payload Description : Linked list entry 0"
bitfld.long 0x10 31. "LL0_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10 30. "LL0_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10 29. "LL0_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10 28. "LL0_CRC_EN," "0,1"
newline
bitfld.long 0x10 27. "LL0_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x10 26. "LL0_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x10 23.--25. "LL0_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 9.--22. 1. "LL0_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x10 8. "LL0_FMT_IN," "0,1"
newline
bitfld.long 0x10 7. "LL0_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x10 5.--6. "LL0_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x10 3.--4. "LL0_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x10 2. "LL0_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x10 1. "LL0_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x10 0. "LL0_VALID," "0,1"
line.long 0x14 "CFG_DATA_LL0_LPHDR_VAL,Payload Description : Linked list entry 0"
line.long 0x18 "CFG_DATA_LL0_THRESHOLD,"
hexmask.long.word 0x18 19.--31. 1. "NU3,"
newline
bitfld.long 0x18 16.--18. "ll0dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x18 15. "NU2," "0,1"
newline
hexmask.long.byte 0x18 8.--14. 1. "LL0_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x18 7. "NU1," "0,1"
newline
hexmask.long.byte 0x18 0.--6. 1. "LL0_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x1C "CFG_DATA_LL1,"
bitfld.long 0x1C 31. "LL1_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x1C 30. "LL1_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x1C 29. "LL1_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x1C 28. "LL1_CRC_EN," "0,1"
newline
bitfld.long 0x1C 27. "LL1_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x1C 26. "LL1_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x1C 23.--25. "LL1_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 9.--22. 1. "LL1_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x1C 8. "LL1_FMT_IN," "0,1"
newline
bitfld.long 0x1C 7. "LL1_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x1C 5.--6. "LL1_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x1C 3.--4. "LL1_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x1C 2. "LL1_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x1C 1. "LL1_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x1C 0. "LL1_VALID," "0,1"
line.long 0x20 "CFG_DATA_LL1_LPHDR_VAL,"
line.long 0x24 "CFG_DATA_LL1_THRESHOLD,"
hexmask.long.word 0x24 19.--31. 1. "NU3,"
newline
bitfld.long 0x24 16.--18. "ll1dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x24 15. "NU2," "0,1"
newline
hexmask.long.byte 0x24 8.--14. 1. "LL1_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x24 7. "NU1," "0,1"
newline
hexmask.long.byte 0x24 0.--6. 1. "LL1_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x28 "CFG_DATA_LL2,"
bitfld.long 0x28 31. "LL2_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x28 30. "LL2_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x28 29. "LL2_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x28 28. "LL2_CRC_EN," "0,1"
newline
bitfld.long 0x28 27. "LL2_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x28 26. "LL2_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x28 23.--25. "LL2_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 9.--22. 1. "LL2_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x28 8. "LL2_FMT_IN," "0,1"
newline
bitfld.long 0x28 7. "LL2_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x28 5.--6. "LL2_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x28 3.--4. "LL2_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x28 2. "LL2_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x28 1. "LL2_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x28 0. "LL2_VALID," "0,1"
line.long 0x2C "CFG_DATA_LL2_LPHDR_VAL,"
line.long 0x30 "CFG_DATA_LL2_THRESHOLD,"
hexmask.long.word 0x30 19.--31. 1. "NU3,"
newline
bitfld.long 0x30 16.--18. "ll2dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x30 15. "NU2," "0,1"
newline
hexmask.long.byte 0x30 8.--14. 1. "LL2_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x30 7. "NU1," "0,1"
newline
hexmask.long.byte 0x30 0.--6. 1. "LL2_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x34 "CFG_DATA_LL3,"
bitfld.long 0x34 31. "LL3_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x34 30. "LL3_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x34 29. "LL3_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x34 28. "LL3_CRC_EN," "0,1"
newline
bitfld.long 0x34 27. "LL3_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x34 26. "LL3_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x34 23.--25. "LL3_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 9.--22. 1. "LL3_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x34 8. "LL3_FMT_IN," "0,1"
newline
bitfld.long 0x34 7. "LL3_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x34 5.--6. "LL3_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x34 3.--4. "LL3_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x34 2. "LL3_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x34 1. "LL3_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x34 0. "LL3_VALID," "0,1"
line.long 0x38 "CFG_DATA_LL3_LPHDR_VAL,"
line.long 0x3C "CFG_DATA_LL3_THRESHOLD,"
hexmask.long.word 0x3C 19.--31. 1. "NU3,"
newline
bitfld.long 0x3C 16.--18. "ll3dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x3C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x3C 8.--14. 1. "LL3_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x3C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x3C 0.--6. 1. "LL3_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x40 "CFG_DATA_LL4,"
bitfld.long 0x40 31. "LL4_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x40 30. "LL4_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x40 29. "LL4_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x40 28. "LL4_CRC_EN," "0,1"
newline
bitfld.long 0x40 27. "LL4_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x40 26. "LL4_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x40 23.--25. "LL4_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x40 9.--22. 1. "LL4_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x40 8. "LL4_FMT_IN," "0,1"
newline
bitfld.long 0x40 7. "LL4_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x40 5.--6. "LL4_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x40 3.--4. "LL4_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x40 2. "LL4_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x40 1. "LL4_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x40 0. "LL4_VALID," "0,1"
line.long 0x44 "CFG_DATA_LL4_LPHDR_VAL,"
line.long 0x48 "CFG_DATA_LL4_THRESHOLD,"
hexmask.long.word 0x48 19.--31. 1. "NU3,"
newline
bitfld.long 0x48 16.--18. "ll4dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x48 15. "NU2," "0,1"
newline
hexmask.long.byte 0x48 8.--14. 1. "LL4_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x48 7. "NU1," "0,1"
newline
hexmask.long.byte 0x48 0.--6. 1. "LL4_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x4C "CFG_DATA_LL5,"
bitfld.long 0x4C 31. "LL5_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x4C 30. "LL5_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x4C 29. "LL5_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x4C 28. "LL5_CRC_EN," "0,1"
newline
bitfld.long 0x4C 27. "LL5_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x4C 26. "LL5_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x4C 23.--25. "LL5_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x4C 9.--22. 1. "LL5_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x4C 8. "LL5_FMT_IN," "0,1"
newline
bitfld.long 0x4C 7. "LL5_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x4C 5.--6. "LL5_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x4C 3.--4. "LL5_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x4C 2. "LL5_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x4C 1. "LL5_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x4C 0. "LL5_VALID," "0,1"
line.long 0x50 "CFG_DATA_LL5_LPHDR_VAL,"
line.long 0x54 "CFG_DATA_LL5_THRESHOLD,"
hexmask.long.word 0x54 19.--31. 1. "NU3,"
newline
bitfld.long 0x54 16.--18. "ll5dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x54 15. "NU2," "0,1"
newline
hexmask.long.byte 0x54 8.--14. 1. "LL5_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x54 7. "NU1," "0,1"
newline
hexmask.long.byte 0x54 0.--6. 1. "LL5_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x58 "CFG_DATA_LL6,"
bitfld.long 0x58 31. "LL6_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x58 30. "LL6_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x58 29. "LL6_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x58 28. "LL6_CRC_EN," "0,1"
newline
bitfld.long 0x58 27. "LL6_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x58 26. "LL6_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x58 23.--25. "LL6_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x58 9.--22. 1. "LL6_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x58 8. "LL6_FMT_IN," "0,1"
newline
bitfld.long 0x58 7. "LL6_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x58 5.--6. "LL6_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x58 3.--4. "LL6_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x58 2. "LL6_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x58 1. "LL6_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x58 0. "LL6_VALID," "0,1"
line.long 0x5C "CFG_DATA_LL6_LPHDR_VAL,"
line.long 0x60 "CFG_DATA_LL6_THRESHOLD,"
hexmask.long.word 0x60 19.--31. 1. "NU3,"
newline
bitfld.long 0x60 16.--18. "ll6dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x60 15. "NU2," "0,1"
newline
hexmask.long.byte 0x60 8.--14. 1. "LL6_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x60 7. "NU1," "0,1"
newline
hexmask.long.byte 0x60 0.--6. 1. "LL6_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x64 "CFG_DATA_LL7,"
bitfld.long 0x64 31. "LL7_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x64 30. "LL7_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x64 29. "LL7_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x64 28. "LL7_CRC_EN," "0,1"
newline
bitfld.long 0x64 27. "LL7_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x64 26. "LL7_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x64 23.--25. "LL7_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x64 9.--22. 1. "LL7_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x64 8. "LL7_FMT_IN," "0,1"
newline
bitfld.long 0x64 7. "LL7_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x64 5.--6. "LL7_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x64 3.--4. "LL7_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x64 2. "LL7_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x64 1. "LL7_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x64 0. "LL7_VALID," "0,1"
line.long 0x68 "CFG_DATA_LL7_LPHDR_VAL,"
line.long 0x6C "CFG_DATA_LL7_THRESHOLD,"
hexmask.long.word 0x6C 19.--31. 1. "NU3,"
newline
bitfld.long 0x6C 16.--18. "ll7dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x6C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x6C 8.--14. 1. "LL7_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x6C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x6C 0.--6. 1. "LL7_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x70 "CFG_DATA_LL8,"
bitfld.long 0x70 31. "LL8_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x70 30. "LL8_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x70 29. "LL8_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x70 28. "LL8_CRC_EN," "0,1"
newline
bitfld.long 0x70 27. "LL8_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x70 26. "LL8_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x70 23.--25. "LL8_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x70 9.--22. 1. "LL8_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x70 8. "LL8_FMT_IN," "0,1"
newline
bitfld.long 0x70 7. "LL8_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x70 5.--6. "LL8_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x70 3.--4. "LL8_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x70 2. "LL8_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x70 1. "LL8_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x70 0. "LL8_VALID," "0,1"
line.long 0x74 "CFG_DATA_LL8_LPHDR_VAL,"
line.long 0x78 "CFG_DATA_LL8_THRESHOLD,"
hexmask.long.word 0x78 19.--31. 1. "NU3,"
newline
bitfld.long 0x78 16.--18. "ll8dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x78 15. "NU2," "0,1"
newline
hexmask.long.byte 0x78 8.--14. 1. "LL8_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x78 7. "NU1," "0,1"
newline
hexmask.long.byte 0x78 0.--6. 1. "LL8_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x7C "CFG_DATA_LL9,"
bitfld.long 0x7C 31. "LL9_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x7C 30. "LL9_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x7C 29. "LL9_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x7C 28. "LL9_CRC_EN," "0,1"
newline
bitfld.long 0x7C 27. "LL9_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x7C 26. "LL9_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x7C 23.--25. "LL9_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x7C 9.--22. 1. "LL9_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x7C 8. "LL9_FMT_IN," "0,1"
newline
bitfld.long 0x7C 7. "LL9_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x7C 5.--6. "LL9_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x7C 3.--4. "LL9_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x7C 2. "LL9_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x7C 1. "LL9_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x7C 0. "LL9_VALID," "0,1"
line.long 0x80 "CFG_DATA_LL9_LPHDR_VAL,"
line.long 0x84 "CFG_DATA_LL9_THRESHOLD,"
hexmask.long.word 0x84 19.--31. 1. "NU3,"
newline
bitfld.long 0x84 16.--18. "ll9dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x84 15. "NU2," "0,1"
newline
hexmask.long.byte 0x84 8.--14. 1. "LL9_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x84 7. "NU1," "0,1"
newline
hexmask.long.byte 0x84 0.--6. 1. "LL9_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x88 "CFG_DATA_LL10,"
bitfld.long 0x88 31. "LL10_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x88 30. "LL10_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x88 29. "LL10_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x88 28. "LL10_CRC_EN," "0,1"
newline
bitfld.long 0x88 27. "LL10_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x88 26. "LL10_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x88 23.--25. "LL10_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x88 9.--22. 1. "LL10_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x88 8. "LL10_FMT_IN," "0,1"
newline
bitfld.long 0x88 7. "LL10_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x88 5.--6. "LL10_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x88 3.--4. "LL10_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x88 2. "LL10_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x88 1. "LL10_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x88 0. "LL10_VALID," "0,1"
line.long 0x8C "CFG_DATA_LL10_LPHDR_VAL,"
line.long 0x90 "CFG_DATA_LL10_THRESHOLD,"
hexmask.long.word 0x90 19.--31. 1. "NU3,"
newline
bitfld.long 0x90 16.--18. "ll10dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x90 15. "NU2," "0,1"
newline
hexmask.long.byte 0x90 8.--14. 1. "LL10_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x90 7. "NU1," "0,1"
newline
hexmask.long.byte 0x90 0.--6. 1. "LL10_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x94 "CFG_DATA_LL11,"
bitfld.long 0x94 31. "LL11_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x94 30. "LL11_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
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bitfld.long 0x94 29. "LL11_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x94 28. "LL11_CRC_EN," "0,1"
newline
bitfld.long 0x94 27. "LL11_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x94 26. "LL11_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x94 23.--25. "LL11_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x94 9.--22. 1. "LL11_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x94 8. "LL11_FMT_IN," "0,1"
newline
bitfld.long 0x94 7. "LL11_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x94 5.--6. "LL11_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x94 3.--4. "LL11_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x94 2. "LL11_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x94 1. "LL11_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
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bitfld.long 0x94 0. "LL11_VALID," "0,1"
line.long 0x98 "CFG_DATA_LL11_LPHDR_VAL,"
line.long 0x9C "CFG_DATA_LL11_THRESHOLD,"
hexmask.long.word 0x9C 19.--31. 1. "NU3,"
newline
bitfld.long 0x9C 16.--18. "ll11dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x9C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x9C 8.--14. 1. "LL11_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x9C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x9C 0.--6. 1. "LL11_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xA0 "CFG_DATA_LL12,"
bitfld.long 0xA0 31. "LL12_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xA0 30. "LL12_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xA0 29. "LL12_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xA0 28. "LL12_CRC_EN," "0,1"
newline
bitfld.long 0xA0 27. "LL12_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xA0 26. "LL12_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xA0 23.--25. "LL12_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xA0 9.--22. 1. "LL12_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xA0 8. "LL12_FMT_IN," "0,1"
newline
bitfld.long 0xA0 7. "LL12_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xA0 5.--6. "LL12_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xA0 3.--4. "LL12_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xA0 2. "LL12_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xA0 1. "LL12_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xA0 0. "LL12_VALID," "0,1"
line.long 0xA4 "CFG_DATA_LL12_LPHDR_VAL,"
line.long 0xA8 "CFG_DATA_LL12_THRESHOLD,"
hexmask.long.word 0xA8 19.--31. 1. "NU3,"
newline
bitfld.long 0xA8 16.--18. "ll12dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xA8 15. "NU2," "0,1"
newline
hexmask.long.byte 0xA8 8.--14. 1. "LL12_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xA8 7. "NU1," "0,1"
newline
hexmask.long.byte 0xA8 0.--6. 1. "LL12_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xAC "CFG_DATA_LL13,"
bitfld.long 0xAC 31. "LL13_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xAC 30. "LL13_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xAC 29. "LL13_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xAC 28. "LL13_CRC_EN," "0,1"
newline
bitfld.long 0xAC 27. "LL13_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xAC 26. "LL13_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xAC 23.--25. "LL13_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xAC 9.--22. 1. "LL13_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xAC 8. "LL13_FMT_IN," "0,1"
newline
bitfld.long 0xAC 7. "LL13_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xAC 5.--6. "LL13_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xAC 3.--4. "LL13_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xAC 2. "LL13_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xAC 1. "LL13_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xAC 0. "LL13_VALID," "0,1"
line.long 0xB0 "CFG_DATA_LL13_LPHDR_VAL,"
line.long 0xB4 "CFG_DATA_LL13_THRESHOLD,"
hexmask.long.word 0xB4 19.--31. 1. "NU3,"
newline
bitfld.long 0xB4 16.--18. "ll13dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xB4 15. "NU2," "0,1"
newline
hexmask.long.byte 0xB4 8.--14. 1. "LL13_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xB4 7. "NU1," "0,1"
newline
hexmask.long.byte 0xB4 0.--6. 1. "LL13_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xB8 "CFG_DATA_LL14,"
bitfld.long 0xB8 31. "LL14_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xB8 30. "LL14_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xB8 29. "LL14_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xB8 28. "LL14_CRC_EN," "0,1"
newline
bitfld.long 0xB8 27. "LL14_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xB8 26. "LL14_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xB8 23.--25. "LL14_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xB8 9.--22. 1. "LL14_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xB8 8. "LL14_FMT_IN," "0,1"
newline
bitfld.long 0xB8 7. "LL14_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xB8 5.--6. "LL14_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xB8 3.--4. "LL14_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xB8 2. "LL14_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xB8 1. "LL14_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xB8 0. "LL14_VALID," "0,1"
line.long 0xBC "CFG_DATA_LL14_LPHDR_VAL,"
line.long 0xC0 "CFG_DATA_LL14_THRESHOLD,"
hexmask.long.word 0xC0 19.--31. 1. "NU3,"
newline
bitfld.long 0xC0 16.--18. "ll14dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xC0 15. "NU2," "0,1"
newline
hexmask.long.byte 0xC0 8.--14. 1. "LL14_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xC0 7. "NU1," "0,1"
newline
hexmask.long.byte 0xC0 0.--6. 1. "LL14_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xC4 "CFG_DATA_LL15,"
bitfld.long 0xC4 31. "LL15_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xC4 30. "LL15_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xC4 29. "LL15_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xC4 28. "LL15_CRC_EN," "0,1"
newline
bitfld.long 0xC4 27. "LL15_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xC4 26. "LL15_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xC4 23.--25. "LL15_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xC4 9.--22. 1. "LL15_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xC4 8. "LL15_FMT_IN," "0,1"
newline
bitfld.long 0xC4 7. "LL15_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xC4 5.--6. "LL15_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xC4 3.--4. "LL15_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xC4 2. "LL15_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xC4 1. "LL15_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xC4 0. "LL15_VALID," "0,1"
line.long 0xC8 "CFG_DATA_LL15_LPHDR_VAL,"
line.long 0xCC "CFG_DATA_LL15_THRESHOLD,"
hexmask.long.word 0xCC 19.--31. 1. "NU3,"
newline
bitfld.long 0xCC 16.--18. "ll15dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xCC 15. "NU2," "0,1"
newline
hexmask.long.byte 0xCC 8.--14. 1. "LL15_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xCC 7. "NU1," "0,1"
newline
hexmask.long.byte 0xCC 0.--6. 1. "LL15_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xD0 "CFG_DATA_LL16,"
bitfld.long 0xD0 31. "LL16_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xD0 30. "LL16_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xD0 29. "LL16_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xD0 28. "LL16_CRC_EN," "0,1"
newline
bitfld.long 0xD0 27. "LL16_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xD0 26. "LL16_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xD0 23.--25. "LL16_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xD0 9.--22. 1. "LL16_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xD0 8. "LL16_FMT_IN," "0,1"
newline
bitfld.long 0xD0 7. "LL16_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xD0 5.--6. "LL16_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xD0 3.--4. "LL16_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xD0 2. "LL16_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xD0 1. "LL16_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xD0 0. "LL16_VALID," "0,1"
line.long 0xD4 "CFG_DATA_LL16_LPHDR_VAL,"
line.long 0xD8 "CFG_DATA_LL16_THRESHOLD,"
hexmask.long.word 0xD8 19.--31. 1. "NU3,"
newline
bitfld.long 0xD8 16.--18. "ll16dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xD8 15. "NU2," "0,1"
newline
hexmask.long.byte 0xD8 8.--14. 1. "LL16_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xD8 7. "NU1," "0,1"
newline
hexmask.long.byte 0xD8 0.--6. 1. "LL16_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xDC "CFG_DATA_LL17,"
bitfld.long 0xDC 31. "LL17_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xDC 30. "LL17_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xDC 29. "LL17_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xDC 28. "LL17_CRC_EN," "0,1"
newline
bitfld.long 0xDC 27. "LL17_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xDC 26. "LL17_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xDC 23.--25. "LL17_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xDC 9.--22. 1. "LL17_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xDC 8. "LL17_FMT_IN," "0,1"
newline
bitfld.long 0xDC 7. "LL17_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xDC 5.--6. "LL17_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xDC 3.--4. "LL17_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xDC 2. "LL17_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xDC 1. "LL17_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xDC 0. "LL17_VALID," "0,1"
line.long 0xE0 "CFG_DATA_LL17_LPHDR_VAL,"
line.long 0xE4 "CFG_DATA_LL17_THRESHOLD,"
hexmask.long.word 0xE4 19.--31. 1. "NU3,"
newline
bitfld.long 0xE4 16.--18. "ll17dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xE4 15. "NU2," "0,1"
newline
hexmask.long.byte 0xE4 8.--14. 1. "LL17_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xE4 7. "NU1," "0,1"
newline
hexmask.long.byte 0xE4 0.--6. 1. "LL17_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xE8 "CFG_DATA_LL18,"
bitfld.long 0xE8 31. "LL18_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xE8 30. "LL18_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xE8 29. "LL18_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xE8 28. "LL18_CRC_EN," "0,1"
newline
bitfld.long 0xE8 27. "LL18_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xE8 26. "LL18_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xE8 23.--25. "LL18_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xE8 9.--22. 1. "LL18_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xE8 8. "LL18_FMT_IN," "0,1"
newline
bitfld.long 0xE8 7. "LL18_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xE8 5.--6. "LL18_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xE8 3.--4. "LL18_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xE8 2. "LL18_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xE8 1. "LL18_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xE8 0. "LL18_VALID," "0,1"
line.long 0xEC "CFG_DATA_LL18_LPHDR_VAL,"
line.long 0xF0 "CFG_DATA_LL18_THRESHOLD,"
hexmask.long.word 0xF0 19.--31. 1. "NU3,"
newline
bitfld.long 0xF0 16.--18. "ll18dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xF0 15. "NU2," "0,1"
newline
hexmask.long.byte 0xF0 8.--14. 1. "LL18_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xF0 7. "NU1," "0,1"
newline
hexmask.long.byte 0xF0 0.--6. 1. "LL18_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xF4 "CFG_DATA_LL19,"
bitfld.long 0xF4 31. "LL19_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xF4 30. "LL19_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xF4 29. "LL19_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xF4 28. "LL19_CRC_EN," "0,1"
newline
bitfld.long 0xF4 27. "LL19_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xF4 26. "LL19_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xF4 23.--25. "LL19_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xF4 9.--22. 1. "LL19_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xF4 8. "LL19_FMT_IN," "0,1"
newline
bitfld.long 0xF4 7. "LL19_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xF4 5.--6. "LL19_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xF4 3.--4. "LL19_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xF4 2. "LL19_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xF4 1. "LL19_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xF4 0. "LL19_VALID," "0,1"
line.long 0xF8 "CFG_DATA_LL19_LPHDR_VAL,"
line.long 0xFC "CFG_DATA_LL19_THRESHOLD,"
hexmask.long.word 0xFC 19.--31. 1. "NU3,"
newline
bitfld.long 0xFC 16.--18. "ll19dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xFC 15. "NU2," "0,1"
newline
hexmask.long.byte 0xFC 8.--14. 1. "LL19_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xFC 7. "NU1," "0,1"
newline
hexmask.long.byte 0xFC 0.--6. 1. "LL19_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x100 "CFG_DATA_LL20,"
bitfld.long 0x100 31. "LL20_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x100 30. "LL20_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x100 29. "LL20_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x100 28. "LL20_CRC_EN," "0,1"
newline
bitfld.long 0x100 27. "LL20_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x100 26. "LL20_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x100 23.--25. "LL20_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x100 9.--22. 1. "LL20_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x100 8. "LL20_FMT_IN," "0,1"
newline
bitfld.long 0x100 7. "LL20_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x100 5.--6. "LL20_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x100 3.--4. "LL20_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x100 2. "LL20_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x100 1. "LL20_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x100 0. "LL20_VALID," "0,1"
line.long 0x104 "CFG_DATA_LL20_LPHDR_VAL,"
line.long 0x108 "CFG_DATA_LL20_THRESHOLD,"
hexmask.long.word 0x108 19.--31. 1. "NU3,"
newline
bitfld.long 0x108 16.--18. "ll20dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x108 15. "NU2," "0,1"
newline
hexmask.long.byte 0x108 8.--14. 1. "LL20_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x108 7. "NU1," "0,1"
newline
hexmask.long.byte 0x108 0.--6. 1. "LL20_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x10C "CFG_DATA_LL21,"
bitfld.long 0x10C 31. "LL21_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10C 30. "LL21_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10C 29. "LL21_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10C 28. "LL21_CRC_EN," "0,1"
newline
bitfld.long 0x10C 27. "LL21_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x10C 26. "LL21_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x10C 23.--25. "LL21_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10C 9.--22. 1. "LL21_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x10C 8. "LL21_FMT_IN," "0,1"
newline
bitfld.long 0x10C 7. "LL21_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x10C 5.--6. "LL21_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x10C 3.--4. "LL21_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x10C 2. "LL21_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x10C 1. "LL21_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x10C 0. "LL21_VALID," "0,1"
line.long 0x110 "CFG_DATA_LL21_LPHDR_VAL,"
line.long 0x114 "CFG_DATA_LL21_THRESHOLD,"
hexmask.long.word 0x114 19.--31. 1. "NU3,"
newline
bitfld.long 0x114 16.--18. "ll21dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x114 15. "NU2," "0,1"
newline
hexmask.long.byte 0x114 8.--14. 1. "LL21_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x114 7. "NU1," "0,1"
newline
hexmask.long.byte 0x114 0.--6. 1. "LL21_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x118 "CFG_DATA_LL22,"
bitfld.long 0x118 31. "LL22_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x118 30. "LL22_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x118 29. "LL22_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x118 28. "LL22_CRC_EN," "0,1"
newline
bitfld.long 0x118 27. "LL22_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x118 26. "LL22_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x118 23.--25. "LL22_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x118 9.--22. 1. "LL22_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x118 8. "LL22_FMT_IN," "0,1"
newline
bitfld.long 0x118 7. "LL22_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x118 5.--6. "LL22_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x118 3.--4. "LL22_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x118 2. "LL22_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x118 1. "LL22_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x118 0. "LL22_VALID," "0,1"
line.long 0x11C "CFG_DATA_LL22_LPHDR_VAL,"
line.long 0x120 "CFG_DATA_LL22_THRESHOLD,"
hexmask.long.word 0x120 19.--31. 1. "NU3,"
newline
bitfld.long 0x120 16.--18. "ll22dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x120 15. "NU2," "0,1"
newline
hexmask.long.byte 0x120 8.--14. 1. "LL22_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x120 7. "NU1," "0,1"
newline
hexmask.long.byte 0x120 0.--6. 1. "LL22_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x124 "CFG_DATA_LL23,"
bitfld.long 0x124 31. "LL23_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x124 30. "LL23_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x124 29. "LL23_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x124 28. "LL23_CRC_EN," "0,1"
newline
bitfld.long 0x124 27. "LL23_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x124 26. "LL23_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x124 23.--25. "LL23_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x124 9.--22. 1. "LL23_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x124 8. "LL23_FMT_IN," "0,1"
newline
bitfld.long 0x124 7. "LL23_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x124 5.--6. "LL23_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x124 3.--4. "LL23_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x124 2. "LL23_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x124 1. "LL23_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x124 0. "LL23_VALID," "0,1"
line.long 0x128 "CFG_DATA_LL23_LPHDR_VAL,"
line.long 0x12C "CFG_DATA_LL23_THRESHOLD,"
hexmask.long.word 0x12C 19.--31. 1. "NU3,"
newline
bitfld.long 0x12C 16.--18. "ll23dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x12C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x12C 8.--14. 1. "LL23_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x12C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x12C 0.--6. 1. "LL23_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x130 "CFG_DATA_LL24,"
bitfld.long 0x130 31. "LL24_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x130 30. "LL24_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x130 29. "LL24_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x130 28. "LL24_CRC_EN," "0,1"
newline
bitfld.long 0x130 27. "LL24_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x130 26. "LL24_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x130 23.--25. "LL24_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x130 9.--22. 1. "LL24_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x130 8. "LL24_FMT_IN," "0,1"
newline
bitfld.long 0x130 7. "LL24_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x130 5.--6. "LL24_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x130 3.--4. "LL24_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x130 2. "LL24_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x130 1. "LL24_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x130 0. "LL24_VALID," "0,1"
line.long 0x134 "CFG_DATA_LL24_LPHDR_VAL,"
line.long 0x138 "CFG_DATA_LL24_THRESHOLD,"
hexmask.long.word 0x138 19.--31. 1. "NU3,"
newline
bitfld.long 0x138 16.--18. "ll24dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x138 15. "NU2," "0,1"
newline
hexmask.long.byte 0x138 8.--14. 1. "LL24_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x138 7. "NU1," "0,1"
newline
hexmask.long.byte 0x138 0.--6. 1. "LL24_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x13C "CFG_DATA_LL25,"
bitfld.long 0x13C 31. "LL25_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x13C 30. "LL25_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x13C 29. "LL25_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x13C 28. "LL25_CRC_EN," "0,1"
newline
bitfld.long 0x13C 27. "LL25_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x13C 26. "LL25_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x13C 23.--25. "LL25_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x13C 9.--22. 1. "LL25_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x13C 8. "LL25_FMT_IN," "0,1"
newline
bitfld.long 0x13C 7. "LL25_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x13C 5.--6. "LL25_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x13C 3.--4. "LL25_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x13C 2. "LL25_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x13C 1. "LL25_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x13C 0. "LL25_VALID," "0,1"
line.long 0x140 "CFG_DATA_LL25_LPHDR_VAL,"
line.long 0x144 "CFG_DATA_LL25_THRESHOLD,"
hexmask.long.word 0x144 19.--31. 1. "NU3,"
newline
bitfld.long 0x144 16.--18. "ll25dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x144 15. "NU2," "0,1"
newline
hexmask.long.byte 0x144 8.--14. 1. "LL25_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x144 7. "NU1," "0,1"
newline
hexmask.long.byte 0x144 0.--6. 1. "LL25_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x148 "CFG_DATA_LL26,"
bitfld.long 0x148 31. "LL26_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x148 30. "LL26_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x148 29. "LL26_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x148 28. "LL26_CRC_EN," "0,1"
newline
bitfld.long 0x148 27. "LL26_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x148 26. "LL26_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x148 23.--25. "LL26_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x148 9.--22. 1. "LL26_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x148 8. "LL26_FMT_IN," "0,1"
newline
bitfld.long 0x148 7. "LL26_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x148 5.--6. "LL26_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x148 3.--4. "LL26_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x148 2. "LL26_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x148 1. "LL26_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x148 0. "LL26_VALID," "0,1"
line.long 0x14C "CFG_DATA_LL26_LPHDR_VAL,"
line.long 0x150 "CFG_DATA_LL26_THRESHOLD,"
hexmask.long.word 0x150 19.--31. 1. "NU3,"
newline
bitfld.long 0x150 16.--18. "ll26dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x150 15. "NU2," "0,1"
newline
hexmask.long.byte 0x150 8.--14. 1. "LL26_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x150 7. "NU1," "0,1"
newline
hexmask.long.byte 0x150 0.--6. 1. "LL26_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x154 "CFG_DATA_LL27,"
bitfld.long 0x154 31. "LL27_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x154 30. "LL27_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x154 29. "LL27_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x154 28. "LL27_CRC_EN," "0,1"
newline
bitfld.long 0x154 27. "LL27_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x154 26. "LL27_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x154 23.--25. "LL27_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x154 9.--22. 1. "LL27_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x154 8. "LL27_FMT_IN," "0,1"
newline
bitfld.long 0x154 7. "LL27_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x154 5.--6. "LL27_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x154 3.--4. "LL27_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x154 2. "LL27_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x154 1. "LL27_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x154 0. "LL27_VALID," "0,1"
line.long 0x158 "CFG_DATA_LL27_LPHDR_VAL,"
line.long 0x15C "CFG_DATA_LL27_THRESHOLD,"
hexmask.long.word 0x15C 19.--31. 1. "NU3,"
newline
bitfld.long 0x15C 16.--18. "ll27dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x15C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x15C 8.--14. 1. "LL27_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x15C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x15C 0.--6. 1. "LL27_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x160 "CFG_DATA_LL28,"
bitfld.long 0x160 31. "LL28_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x160 30. "LL28_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x160 29. "LL28_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x160 28. "LL28_CRC_EN," "0,1"
newline
bitfld.long 0x160 27. "LL28_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x160 26. "LL28_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x160 23.--25. "LL28_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x160 9.--22. 1. "LL28_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x160 8. "LL28_FMT_IN," "0,1"
newline
bitfld.long 0x160 7. "LL28_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x160 5.--6. "LL28_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x160 3.--4. "LL28_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x160 2. "LL28_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x160 1. "LL28_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x160 0. "LL28_VALID," "0,1"
line.long 0x164 "CFG_DATA_LL28_LPHDR_VAL,"
line.long 0x168 "CFG_DATA_LL28_THRESHOLD,"
hexmask.long.word 0x168 19.--31. 1. "NU3,"
newline
bitfld.long 0x168 16.--18. "ll28dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x168 15. "NU2," "0,1"
newline
hexmask.long.byte 0x168 8.--14. 1. "LL28_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x168 7. "NU1," "0,1"
newline
hexmask.long.byte 0x168 0.--6. 1. "LL28_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x16C "CFG_DATA_LL29,"
bitfld.long 0x16C 31. "LL29_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x16C 30. "LL29_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x16C 29. "LL29_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x16C 28. "LL29_CRC_EN," "0,1"
newline
bitfld.long 0x16C 27. "LL29_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x16C 26. "LL29_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x16C 23.--25. "LL29_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x16C 9.--22. 1. "LL29_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x16C 8. "LL29_FMT_IN," "0,1"
newline
bitfld.long 0x16C 7. "LL29_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x16C 5.--6. "LL29_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x16C 3.--4. "LL29_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x16C 2. "LL29_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x16C 1. "LL29_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x16C 0. "LL29_VALID," "0,1"
line.long 0x170 "CFG_DATA_LL29_LPHDR_VAL,"
line.long 0x174 "CFG_DATA_LL29_THRESHOLD,"
hexmask.long.word 0x174 19.--31. 1. "NU3,"
newline
bitfld.long 0x174 16.--18. "ll29dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x174 15. "NU2," "0,1"
newline
hexmask.long.byte 0x174 8.--14. 1. "LL29_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x174 7. "NU1," "0,1"
newline
hexmask.long.byte 0x174 0.--6. 1. "LL29_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x178 "CFG_DATA_LL30,"
bitfld.long 0x178 31. "LL30_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x178 30. "LL30_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x178 29. "LL30_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x178 28. "LL30_CRC_EN," "0,1"
newline
bitfld.long 0x178 27. "LL30_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x178 26. "LL30_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x178 23.--25. "LL30_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x178 9.--22. 1. "LL30_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x178 8. "LL30_FMT_IN," "0,1"
newline
bitfld.long 0x178 7. "LL30_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x178 5.--6. "LL30_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x178 3.--4. "LL30_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x178 2. "LL30_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x178 1. "LL30_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x178 0. "LL30_VALID," "0,1"
line.long 0x17C "CFG_DATA_LL30_LPHDR_VAL,"
line.long 0x180 "CFG_DATA_LL30_THRESHOLD,"
hexmask.long.word 0x180 19.--31. 1. "NU3,"
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bitfld.long 0x180 16.--18. "ll30dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
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rbitfld.long 0x180 15. "NU2," "0,1"
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hexmask.long.byte 0x180 8.--14. 1. "LL30_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
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rbitfld.long 0x180 7. "NU1," "0,1"
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hexmask.long.byte 0x180 0.--6. 1. "LL30_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x184 "CFG_DATA_LL31,"
bitfld.long 0x184 31. "LL31_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
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bitfld.long 0x184 30. "LL31_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
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bitfld.long 0x184 29. "LL31_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
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bitfld.long 0x184 28. "LL31_CRC_EN," "0,1"
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bitfld.long 0x184 27. "LL31_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
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bitfld.long 0x184 26. "LL31_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
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bitfld.long 0x184 23.--25. "LL31_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x184 9.--22. 1. "LL31_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
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bitfld.long 0x184 8. "LL31_FMT_IN," "0,1"
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bitfld.long 0x184 7. "LL31_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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bitfld.long 0x184 5.--6. "LL31_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
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bitfld.long 0x184 3.--4. "LL31_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
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bitfld.long 0x184 2. "LL31_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
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bitfld.long 0x184 1. "LL31_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
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bitfld.long 0x184 0. "LL31_VALID," "0,1"
line.long 0x188 "CFG_DATA_LL31_LPHDR_VAL,"
line.long 0x18C "CFG_DATA_LL31_THRESHOLD,"
hexmask.long.word 0x18C 19.--31. 1. "NU3,"
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bitfld.long 0x18C 16.--18. "ll31dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
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rbitfld.long 0x18C 15. "NU2," "0,1"
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hexmask.long.byte 0x18C 8.--14. 1. "LL31_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
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rbitfld.long 0x18C 7. "NU1," "0,1"
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hexmask.long.byte 0x18C 0.--6. 1. "LL31_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x190 "CFG_LVDS_MAPPING_LANE0_FMT_0,"
bitfld.long 0x190 28.--31. "CFG_LVDS_MAPPING_LANE0_FMT_0_H,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 24.--27. "CFG_LVDS_MAPPING_LANE0_FMT_0_G,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 20.--23. "CFG_LVDS_MAPPING_LANE0_FMT_0_F,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 16.--19. "CFG_LVDS_MAPPING_LANE0_FMT_0_E,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 12.--15. "CFG_LVDS_MAPPING_LANE0_FMT_0_D,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 8.--11. "CFG_LVDS_MAPPING_LANE0_FMT_0_C,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 4.--7. "CFG_LVDS_MAPPING_LANE0_FMT_0_B,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 0.--3. "CFG_LVDS_MAPPING_LANE0_FMT_0_A,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
line.long 0x194 "CFG_LVDS_MAPPING_LANE1_FMT_0,"
bitfld.long 0x194 28.--31. "CFG_LVDS_MAPPING_LANE1_FMT_0_H,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 24.--27. "CFG_LVDS_MAPPING_LANE1_FMT_0_G,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 20.--23. "CFG_LVDS_MAPPING_LANE1_FMT_0_F,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 16.--19. "CFG_LVDS_MAPPING_LANE1_FMT_0_E,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 12.--15. "CFG_LVDS_MAPPING_LANE1_FMT_0_D,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 8.--11. "CFG_LVDS_MAPPING_LANE1_FMT_0_C,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 4.--7. "CFG_LVDS_MAPPING_LANE1_FMT_0_B,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 0.--3. "CFG_LVDS_MAPPING_LANE1_FMT_0_A,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
line.long 0x198 "CFG_LVDS_MAPPING_LANE2_FMT_0,"
bitfld.long 0x198 28.--31. "CFG_LVDS_MAPPING_LANE2_FMT_0_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 24.--27. "CFG_LVDS_MAPPING_LANE2_FMT_0_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 20.--23. "CFG_LVDS_MAPPING_LANE2_FMT_0_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 16.--19. "CFG_LVDS_MAPPING_LANE2_FMT_0_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 12.--15. "CFG_LVDS_MAPPING_LANE2_FMT_0_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 8.--11. "CFG_LVDS_MAPPING_LANE2_FMT_0_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 4.--7. "CFG_LVDS_MAPPING_LANE2_FMT_0_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 0.--3. "CFG_LVDS_MAPPING_LANE2_FMT_0_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "CFG_LVDS_MAPPING_LANE3_FMT_0,"
bitfld.long 0x19C 28.--31. "CFG_LVDS_MAPPING_LANE3_FMT_0_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 24.--27. "CFG_LVDS_MAPPING_LANE3_FMT_0_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 20.--23. "CFG_LVDS_MAPPING_LANE3_FMT_0_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 16.--19. "CFG_LVDS_MAPPING_LANE3_FMT_0_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 12.--15. "CFG_LVDS_MAPPING_LANE3_FMT_0_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 8.--11. "CFG_LVDS_MAPPING_LANE3_FMT_0_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 4.--7. "CFG_LVDS_MAPPING_LANE3_FMT_0_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 0.--3. "CFG_LVDS_MAPPING_LANE3_FMT_0_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "CFG_LVDS_MAPPING_LANE0_FMT_1,"
bitfld.long 0x1A0 28.--31. "CFG_LVDS_MAPPING_LANE0_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 24.--27. "CFG_LVDS_MAPPING_LANE0_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 20.--23. "CFG_LVDS_MAPPING_LANE0_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 16.--19. "CFG_LVDS_MAPPING_LANE0_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 12.--15. "CFG_LVDS_MAPPING_LANE0_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 8.--11. "CFG_LVDS_MAPPING_LANE0_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 4.--7. "CFG_LVDS_MAPPING_LANE0_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 0.--3. "CFG_LVDS_MAPPING_LANE0_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "CFG_LVDS_MAPPING_LANE1_FMT_1,"
bitfld.long 0x1A4 28.--31. "CFG_LVDS_MAPPING_LANE1_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 24.--27. "CFG_LVDS_MAPPING_LANE1_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 20.--23. "CFG_LVDS_MAPPING_LANE1_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 16.--19. "CFG_LVDS_MAPPING_LANE1_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 12.--15. "CFG_LVDS_MAPPING_LANE1_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 8.--11. "CFG_LVDS_MAPPING_LANE1_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 4.--7. "CFG_LVDS_MAPPING_LANE1_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 0.--3. "CFG_LVDS_MAPPING_LANE1_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "CFG_LVDS_MAPPING_LANE2_FMT_1,"
bitfld.long 0x1A8 28.--31. "CFG_LVDS_MAPPING_LANE2_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 24.--27. "CFG_LVDS_MAPPING_LANE2_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 20.--23. "CFG_LVDS_MAPPING_LANE2_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 16.--19. "CFG_LVDS_MAPPING_LANE2_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 12.--15. "CFG_LVDS_MAPPING_LANE2_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 8.--11. "CFG_LVDS_MAPPING_LANE2_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 4.--7. "CFG_LVDS_MAPPING_LANE2_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 0.--3. "CFG_LVDS_MAPPING_LANE2_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "CFG_LVDS_MAPPING_LANE3_FMT_1,"
bitfld.long 0x1AC 28.--31. "CFG_LVDS_MAPPING_LANE3_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 24.--27. "CFG_LVDS_MAPPING_LANE3_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 20.--23. "CFG_LVDS_MAPPING_LANE3_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 16.--19. "CFG_LVDS_MAPPING_LANE3_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 12.--15. "CFG_LVDS_MAPPING_LANE3_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 8.--11. "CFG_LVDS_MAPPING_LANE3_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 4.--7. "CFG_LVDS_MAPPING_LANE3_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 0.--3. "CFG_LVDS_MAPPING_LANE3_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "CFG_LVDS_GEN_0,"
bitfld.long 0x1B0 30.--31. "cpz,LVDS Clock config" "0,1,2,3"
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bitfld.long 0x1B0 29. "cblpen,TI Internal CFG_LASTPULSE_EN" "0,1"
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bitfld.long 0x1B0 28. "cbcrcen,LVDS Frame CRC" "CRC is not sent at the end of LVDS Frame,CRC is sent at the end of the LVDS Frame"
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bitfld.long 0x1B0 24.--27. "cfdly,LVDS FIFO Initial Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1B0 23. "cmsbf," "0,1"
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bitfld.long 0x1B0 22. "cpossel," "0,1"
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bitfld.long 0x1B0 16.--21. "cckdiv,TI Internal feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x1B0 15. "cclksel1,TRM Description" "DDR mode clock mux,SDR mode clock mux TI Restricted Description"
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bitfld.long 0x1B0 14. "cclksel,TI Internal feature" "0,1"
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bitfld.long 0x1B0 12.--13. "ckchar,TI Internal feature" "0,1,2,3"
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bitfld.long 0x1B0 11. "ccsmen,TRM Description : As per alignment TI Restricted Description" "Regular operation,Continuous Streaming Mode Enabled (Not supported.."
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bitfld.long 0x1B0 10. "CFG_BIT_CLK_MODE,Bit Clock Mode" "SDR clocking mode,DDR clocking mode"
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bitfld.long 0x1B0 8.--9. "CFG_LINE_MODE,TI Internal feature" "0,1,2,3"
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bitfld.long 0x1B0 7. "cpkfmt,TI Internal feature" "0,1"
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bitfld.long 0x1B0 6. "cacdsel,TI Internal feature" "If the LVDS clock frequency (SDR) is >= 200MHz,If the LVDS clock frequency (SDR) is < 200MHz"
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bitfld.long 0x1B0 5. "ctc2en,TI Internal feature" "Regular operation,TC2MODE Enable (Not supported internally also in.."
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bitfld.long 0x1B0 4. "CFG_8B10B_EN,TI Internal Feature" "No encoding,8B10B encoding"
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bitfld.long 0x1B0 3. "CFG_LVDS_LANE3_EN,LVDS only programming" "LVDS Lane 3 is disbaled,LVDS Lane 3 is enabled"
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bitfld.long 0x1B0 2. "CFG_LVDS_LANE2_EN,LVDS only programming" "LVDS Lane 2 is disbaled,LVDS Lane 2 is enabled"
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bitfld.long 0x1B0 1. "CFG_LVDS_LANE1_EN,LVDS only programming" "LVDS Lane 1 is disbaled,LVDS Lane 1 is enabled"
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bitfld.long 0x1B0 0. "CFG_LVDS_LANE0_EN,LVDS only programming" "LVDS Lane 0 is disbaled,LVDS Lane 0 is enabled"
line.long 0x1B4 "CFG_LVDS_GEN_1,"
hexmask.long.word 0x1B4 19.--31. 1. "NU2,RESERVED"
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bitfld.long 0x1B4 18. "cgbcen,TI Internal Feature" "Bit clk is free running,Bit clk is valid only during the valid frame"
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bitfld.long 0x1B4 17. "cfcpol,TI Internal Feature" "During IDLE Frame clock will be 0,During IDLE"
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bitfld.long 0x1B4 16. "clfven,TI Internal feature" "Regular Operation,The frame_valid would start early by about 10.."
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bitfld.long 0x1B4 14.--15. "ctpsel3,TI Internal feature" "0,1,2,3"
newline
bitfld.long 0x1B4 12.--13. "ctpsel2,TI Internal feature" "0,1,2,3"
newline
bitfld.long 0x1B4 10.--11. "ctpsel1,TI Internal feature" "0,1,2,3"
newline
bitfld.long 0x1B4 8.--9. "ctpsel0,TI Internal feature" "0,1,2,3"
newline
rbitfld.long 0x1B4 7. "NU1,RESERVED" "0,1"
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bitfld.long 0x1B4 4.--6. "ctiddly,TI Internal feature" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x1B4 3. "NU3," "0,1"
newline
bitfld.long 0x1B4 2. "c3c3l,LVDS Only Programming" "Regular Operation,Enable 3Ch-3Lane mode in LVDS"
newline
bitfld.long 0x1B4 1. "csdrinv,TI Internal feature" "No inversion,Inversion"
newline
bitfld.long 0x1B4 0. "ctpen,TI Internal feature" "Regular Operation,LVDS Testpattern Enable"
line.long 0x1B8 "CFG_LVDS_GEN_2,"
line.long 0x1BC "CFG_MASK_REG0,"
line.long 0x1C0 "CFG_MASK_REG1,"
line.long 0x1C4 "CFG_MASK_REG2,"
line.long 0x1C8 "CFG_MASK_REG3,"
line.long 0x1CC "STAT_CBUFF_REG0,"
hexmask.long.tbyte 0x1CC 13.--31. 1. "STAT_CBUFF_REG0_OTHERS,Reseved for future enhancement"
newline
bitfld.long 0x1CC 12. "S_FRAME_DONE,Indicates that CBUFF has completed sending out data for the current Frame" "0,1"
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bitfld.long 0x1CC 11. "S_CHIRP_DONE,Indicates that CBUFF has completed sending out data for the current Chirp" "0,1"
newline
bitfld.long 0x1CC 6.--10. "S_LL_INDEX,TI Internal Feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1CC 5. "S_CSI_PKT_LP_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Long Data Packet" "0,1"
newline
bitfld.long 0x1CC 4. "S_CSI_PKT_HE_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Hsync End Packet" "0,1"
newline
bitfld.long 0x1CC 3. "S_CSI_PKT_HS_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Hsync Start Packet" "0,1"
newline
bitfld.long 0x1CC 2. "S_CSI_PKT_VE_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Vsync End Packet" "0,1"
newline
bitfld.long 0x1CC 1. "S_CSI_PKT_VS_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Vsync Start Packet" "0,1"
newline
bitfld.long 0x1CC 0. "S_CSI_PKT_RCVD,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine" "0,1"
line.long 0x1D0 "STAT_CBUFF_REG1,"
hexmask.long.word 0x1D0 21.--31. 1. "S1_UNUSED3,"
newline
bitfld.long 0x1D0 20. "S_CBFIFO_READY_IN_FSM,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 19. "S_CBFIFO_EMPTY_IN_FSM,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 18. "S_PKTRCV_ERR,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 17. "S_FRAME_ERR,Indicates the FrameStart arrived before CBUFF has completed sending out data for all the Chirps programmed" "0,1"
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bitfld.long 0x1D0 16. "S_CHIRP_ERR,Indicates tha the chirpAvailable from ADCBuffer arrived before CBUFF has completed sending out the previous Chirp data" "0,1"
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bitfld.long 0x1D0 12.--15. "S1_UNUSED2,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1D0 11. "S_CBFIFO_EMPTY,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 10. "S_CBFIFO_FULL,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 9. "S_CBPUSH_ERR,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 8. "S_CBPOP_ERR,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 3.--7. "S1_UNUSED1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1D0 2. "S_LCLPUSH_ERR,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 1. "S_LCLPOP_ERR,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 0. "S_LCLFSM_ERR,TI Internal Feature" "0,1"
rgroup.long 0x1FC++0x03
line.long 0x00 "STAT_LVDS_REG0,"
group.long 0x20C++0x27
line.long 0x00 "CLR_CBUFF_REG0,"
hexmask.long.tbyte 0x00 13.--31. 1. "CLR_CBUFF_REG0_OTHERS,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0"
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bitfld.long 0x00 12. "C_FRAME_DONE,Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 11. "C_CHIRP_DONE,Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 6.--10. "C_LL_INDEX,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "C_CSI_PKT_LP_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 4. "C_CSI_PKT_HE_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 3. "C_CSI_PKT_HS_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 2. "C_CSI_PKT_VE_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 1. "C_CSI_PKT_VS_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 0. "C_CSI_PKT_RCVD,TI Internal Feature" "0,1"
line.long 0x04 "CLR_CBUFF_REG1,"
line.long 0x08 "CLR_LVDS_REG0,"
line.long 0x0C "CLR_LVDS_REG1,"
line.long 0x10 "STAT_CBUFF_ECC_REG,"
hexmask.long.tbyte 0x10 10.--31. 1. "NU2,"
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bitfld.long 0x10 9. "seccdbe," "0,1"
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bitfld.long 0x10 8. "seccsbe," "0,1"
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bitfld.long 0x10 6.--7. "NU1," "0,1,2,3"
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bitfld.long 0x10 0.--5. "seccadd,6-bit address where the ECC error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "MASK_CBUFF_ECC_REG,"
hexmask.long.tbyte 0x14 10.--31. 1. "NU2,"
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bitfld.long 0x14 9. "meccdbe," "0,1"
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bitfld.long 0x14 8. "meccsbe," "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "NU1,"
line.long 0x18 "CLR_CBUFF_ECC_REG,"
hexmask.long.tbyte 0x18 10.--31. 1. "NU2,"
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bitfld.long 0x18 9. "ceccdbe,Clear Register field corresponding to STAT_CBUFF_ECC" "0,1"
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bitfld.long 0x18 8. "ceccsbe,Clear Register field corresponding to STAT_CBUFF_ECC" "0,1"
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hexmask.long.byte 0x18 1.--7. 1. "NU1,"
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bitfld.long 0x18 0. "ceccadd,Clear Register field corresponding to STAT_CBUFF_ECC" "0,1"
line.long 0x1C "STAT_SAFETY,"
hexmask.long.tbyte 0x1C 9.--31. 1. "SAF_UNUSED1,RESERVED"
newline
bitfld.long 0x1C 8. "SAF_CHIRP_ERR,Safety Error" "0,1"
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abitfld.long 0x1C 0.--7. "SAF_CRC,TRM Desccription : Indicates a CRC error between ADCBuffer and CBUFF" "0x00=CRC for col-0 - [15:0],0x01=CRC for col-1 [31:16],0x02=CRC for col-2 [47:32],0x03=CRC for col-3 [63:48],0x04=CRC for col-4 - [79:64],0x05=CRC for col-5 [95:80],0x06=CRC for col-6 [111 :96,0x07=for col-7 [127:112]"
line.long 0x20 "MASK_SAFETY,"
line.long 0x24 "CLR_SAFETY,"
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x200)++0x03
line.long 0x00 "STAT_LVDS_REG$1,"
repeat.end
repeat 2. (list 2. 3. )(list 0x00 0x04 )
rgroup.long ($2+0x1F4)++0x03
line.long 0x00 "STAT_CBUFF_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_CM4_CTRL (DSS CM4 Control Module Registers)"
base ad:0x48020000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 11.--15. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "UNDEFINED_NAME," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x7F
line.long 0x00 "HWA_CM4_B0_MEMINIT_START,"
bitfld.long 0x00 0. "hwa_cm4_b0_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x04 "HWA_CM4_B0_MEMINIT_STATUS,"
bitfld.long 0x04 0. "hwa_cm4_b0_meminit_status,Status field" "0,1"
line.long 0x08 "HWA_CM4_B0_MEMINIT_DONE,"
bitfld.long 0x08 0. "hwa_cm4_b0_meminit_done,Status field" "0,1"
line.long 0x0C "HWA_CM4_B1_MEMINIT_START,"
bitfld.long 0x0C 0. "hwa_cm4_b1_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x10 "HWA_CM4_B1_MEMINIT_STATUS,"
bitfld.long 0x10 0. "hwa_cm4_b1_meminit_status,Status field" "0,1"
line.long 0x14 "HWA_CM4_B1_MEMINIT_DONE,"
bitfld.long 0x14 0. "hwa_cm4_b1_meminit_done,Status field" "0,1"
line.long 0x18 "HWA_CM4_B2_MEMINIT_START,"
bitfld.long 0x18 0. "hwa_cm4_b2_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x1C "HWA_CM4_B2_MEMINIT_STATUS,"
bitfld.long 0x1C 0. "hwa_cm4_b2_meminit_status,Status field" "0,1"
line.long 0x20 "HWA_CM4_B2_MEMINIT_DONE,"
bitfld.long 0x20 0. "hwa_cm4_b2_meminit_done,Status field" "0,1"
line.long 0x24 "HWA_CM4_MBOX_MEMINIT_START,"
bitfld.long 0x24 0. "hwa_cm4_mbox_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x28 "HWA_CM4_MBOX_MEMINIT_STATUS,"
bitfld.long 0x28 0. "hwa_cm4_mbox_meminit_status,Status field" "0,1"
line.long 0x2C "HWA_CM4_MBOX_MEMINIT_DONE,"
bitfld.long 0x2C 0. "hwa_cm4_mbox_meminit_done,Status field" "0,1"
line.long 0x30 "HWA_CM4_MBOX_WRITE_DONE,"
bitfld.long 0x30 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
bitfld.long 0x30 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
newline
bitfld.long 0x30 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
bitfld.long 0x30 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
newline
bitfld.long 0x30 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
bitfld.long 0x30 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
newline
bitfld.long 0x30 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
bitfld.long 0x30 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0x34 "HWA_CM4_MBOX_READ_REQ,"
bitfld.long 0x34 28. "proc_7,This is request from processor 7 to HSM" "0,1"
bitfld.long 0x34 24. "proc_6,This is request from processor 6 to HSM" "0,1"
newline
bitfld.long 0x34 20. "proc_5,This is request from processor 5 to HSM" "0,1"
bitfld.long 0x34 16. "proc_4,This is request from processor 4 to HSM" "0,1"
newline
bitfld.long 0x34 12. "proc_3,This is request from processor 3 to HSM" "0,1"
bitfld.long 0x34 8. "proc_2,This is request from processor 2 to HSM" "0,1"
newline
bitfld.long 0x34 4. "proc_1,This is request from processor 1 to HSM" "0,1"
bitfld.long 0x34 0. "proc_0,This is request from processor 0 to HSM" "0,1"
line.long 0x38 "HWA_CM4_MBOX_READ_DONE,"
bitfld.long 0x38 28. "proc_7,This register should be written once finishing reading from hsm's mailbox written by proc 7" "0,1"
bitfld.long 0x38 24. "proc_6,This register should be written once finishing reading from hsm's mailbox written by proc 6" "0,1"
newline
bitfld.long 0x38 20. "proc_5,This register should be written once finishing reading from hsm's mailbox written by proc 5" "0,1"
bitfld.long 0x38 16. "proc_4,This register should be written once finishing reading from hsm's mailbox written by proc 4" "0,1"
newline
bitfld.long 0x38 12. "proc_3,This register should be written once finishing reading from hsm's mailbox written by proc 3" "0,1"
bitfld.long 0x38 8. "proc_2,This register should be written once finishing reading from hsm's mailbox written by proc 2" "0,1"
newline
bitfld.long 0x38 4. "proc_1,This register should be written once finishing reading from hsm's mailbox written by proc 1" "0,1"
bitfld.long 0x38 0. "proc_0,This register should be written once finishing reading from hsm's mailbox written by proc 0" "0,1"
line.long 0x3C "HWA_CM4_IRQ_REQ,"
bitfld.long 0x3C 0.--1. "select,Software configration for INT Request" "0,1,2,3"
line.long 0x40 "HWA_CM4_POR_RST_CTRL,"
bitfld.long 0x40 0.--2. "assert,Por reset control for CM4" "0,1,2,3,4,5,6,7"
line.long 0x44 "HWA_CM4_SYS_RST_CTRL,"
bitfld.long 0x44 0.--2. "assert,Reset control for CM4" "0,1,2,3,4,5,6,7"
line.long 0x48 "HWA_CM4_CFG,"
bitfld.long 0x48 12.--14. "cm4_sys_reset_hold,In development mode by default cm4 will be held in reset" "0,1,2,3,4,5,6,7"
bitfld.long 0x48 8. "cm4_clk_gate,CM4 Clock Gate" "Un-gate the clock,Clock gated"
newline
bitfld.long 0x48 2. "wicenreq,WIC mode Request from PMU" "0,1"
bitfld.long 0x48 1. "sleep_hold_reqn,Hold core in sleep mode" "0,1"
newline
bitfld.long 0x48 0. "force_hclk_active,Force HCLK to run overrides GATEHCLK" "0,1"
line.long 0x4C "HWA_CM4_RST_CAUSE_CLR,"
bitfld.long 0x4C 0.--2. "clear,Writing '111' will clear the HWA_CM4_RST_STATUS_REG" "0,1,2,3,4,5,6,7"
line.long 0x50 "HWA_CM4_RST_CAUSE,"
hexmask.long.byte 0x50 0.--7. 1. "status,Reset Cause Register"
line.long 0x54 "HWA_CM4_FSM_RST_CTRL,"
bitfld.long 0x54 28.--30. "rst_fsm_trig,writing '111' will triggger the reset fsm for CM4" "0,1,2,3,4,5,6,7"
bitfld.long 0x54 24.--26. "rst_wficheck,writing '111' will check for WFI before asserting reset to CM4" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x54 16.--23. 1. "rst_assertdly_common,This field the decides number of cycles reset to CM4 should be asserted"
hexmask.long.byte 0x54 8.--15. 1. "rst2assertdly,This field the decides number cycles for which the reset should be held before asserting reset for CM4"
line.long 0x58 "HWA_CM4_WFI_OVERRIDE,"
bitfld.long 0x58 0.--2. "wfi_override,writing '111' will override the wfi signal from CM4" "0,1,2,3,4,5,6,7"
line.long 0x5C "HWA_CM4_PERIPH_ERRAGG_MASK,"
bitfld.long 0x5C 11. "rcss_ctrl_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 10. "rcss_ctrl_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 9. "rcss_rcm_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 8. "rcss_rcm_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 7. "dss_hwa_cfg_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 6. "dss_hwa_cfg_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 5. "dss_cm4_ctrl_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 4. "dss_cm4_ctrl_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 3. "dss_ctrl_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 2. "dss_ctrl_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 1. "dss_rcm_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 0. "dss_rcm_rd,Writing '1' will mask the respective peripheral error line" "0,1"
line.long 0x60 "HWA_CM4_PERIPH_ERRAGG_STATUS,"
bitfld.long 0x60 11. "rcss_ctrl_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 10. "rcss_ctrl_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 9. "rcss_rcm_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 8. "rcss_rcm_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 7. "dss_hwa_cfg_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 6. "dss_hwa_cfg_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 5. "dss_cm4_ctrl_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 4. "dss_cm4_ctrl_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 3. "dss_ctrl_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 2. "dss_ctrl_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 1. "dss_rcm_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 0. "dss_rcm_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
line.long 0x64 "HWA_CM4_PERIPH_ERRAGG_STATUS_RAW,"
bitfld.long 0x64 11. "rcss_ctrl_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 10. "rcss_ctrl_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 9. "rcss_rcm_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 8. "rcss_rcm_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 7. "dss_hwa_cfg_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 6. "dss_hwa_cfg_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 5. "dss_cm4_ctrl_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 4. "dss_cm4_ctrl_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 3. "dss_ctrl_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 2. "dss_ctrl_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 1. "dss_rcm_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 0. "dss_rcm_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
line.long 0x68 "HWA_CM4_AHB_ERRAGG_MASK,"
bitfld.long 0x68 2. "sbus_write,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x68 1. "dbus_write,Writing '1' will mask the respective peripheral error line" "0,1"
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bitfld.long 0x68 0. "ibus_write,Writing '1' will mask the respective peripheral error line" "0,1"
line.long 0x6C "HWA_CM4_AHB_ERRAGG_STATUS,"
bitfld.long 0x6C 2. "sbus_write,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x6C 1. "dbus_write,Indicates the post mask status of the respective peripheral error line" "0,1"
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bitfld.long 0x6C 0. "ibus_write,Indicates the post mask status of the respective peripheral error line" "0,1"
line.long 0x70 "HWA_CM4_AHB_ERRAGG_STATUS_RAW,"
bitfld.long 0x70 2. "sbus_write,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x70 1. "dbus_write,Indicates the pre mask status of the respective peripheral error line" "0,1"
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bitfld.long 0x70 0. "ibus_write,Indicates the pre mask status of the respective peripheral error line" "0,1"
line.long 0x74 "HWA_CM4_ECC_ERRAGG_MASK,"
bitfld.long 0x74 3. "mbox_ded,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x74 2. "bank2_ded,Writing '1' will mask the respective peripheral error line" "0,1"
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bitfld.long 0x74 1. "bank1_ded,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x74 0. "bank0_ded,Writing '1' will mask the respective peripheral error line" "0,1"
line.long 0x78 "HWA_CM4_ECC_ERRAGG_STATUS,"
bitfld.long 0x78 3. "mbox_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x78 2. "bank2_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
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bitfld.long 0x78 1. "bank1_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x78 0. "bank0_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
line.long 0x7C "HWA_CM4_ECC_ERRAGG_STATUS_RAW,"
bitfld.long 0x7C 3. "mbox_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x7C 2. "bank2_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
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bitfld.long 0x7C 1. "bank1_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x7C 0. "bank0_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "UNDEFINED_NAME,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "UNDEFINED_NAME,Kick access violation error" "0,1"
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bitfld.long 0x08 1. "UNDEFINED_NAME,Addressing violation error" "0,1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "UNDEFINED_NAME,Kick access violation error" "0,1"
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bitfld.long 0x0C 1. "UNDEFINED_NAME,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "UNDEFINED_NAME,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "UNDEFINED_NAME,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "UNDEFINED_NAME,Kick access violation error enable" "0,1"
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bitfld.long 0x10 1. "UNDEFINED_NAME,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "UNDEFINED_NAME,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "UNDEFINED_NAME,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "UNDEFINED_NAME,Kick access violation error enable clear" "0,1"
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bitfld.long 0x14 1. "UNDEFINED_NAME,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "UNDEFINED_NAME,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "UNDEFINED_NAME,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "UNDEFINED_NAME,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "UNDEFINED_NAME,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "UNDEFINED_NAME,XID"
hexmask.long.word 0x24 8.--19. 1. "UNDEFINED_NAME,Route ID"
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hexmask.long.byte 0x24 0.--7. 1. "UNDEFINED_NAME,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "UNDEFINED_NAME,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_CM4_STC (DSS DSP STC Module Registers)"
base ad:0x6F79200
group.long 0x00++0x11B
line.long 0x00 "STCGCR0,Self test Global control Reg0"
hexmask.long.word 0x00 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run"
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rbitfld.long 0x00 11.--15. "NU0,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval" "Continue NSTC run from previous interval,Restart NSTC run from ROM address 0 1X = Start..,?..."
line.long 0x04 "STCGCR1,Self test Global control Reg1"
hexmask.long.tbyte 0x04 12.--31. 1. "NU2,Reserved bits"
newline
bitfld.long 0x04 8.--11. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x04 7. "NU3,Reserved bits" "0,1"
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bitfld.long 0x04 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode" "XOR mode,Spread mode"
newline
bitfld.long 0x04 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration" "Operates in Normal Scan Mode,Operates in Low Power Scan Mode"
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bitfld.long 0x04 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
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bitfld.long 0x04 0.--3. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "STCTPR,Time out counter preload register"
line.long 0x0C "STC_CADDR,Current Address register for CORE1"
line.long 0x10 "STCCICR,Current Interval count register"
hexmask.long.word 0x10 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well"
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hexmask.long.word 0x10 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run"
line.long 0x14 "STCGSTAT,Global Status Register"
hexmask.long.tbyte 0x14 12.--31. 1. "NU4,Reserved bits"
newline
bitfld.long 0x14 8.--11. "ST_ACTIVE,Tells whether self test is currently active or not" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 2.--7. "NU5,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)" "Self test run has not failed,SelfTest run has failed"
newline
bitfld.long 0x14 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)" "Not completed,SelfTest run Completed"
line.long 0x18 "STCFSTAT,Fail Status Register"
hexmask.long 0x18 5.--31. 1. "NU6,Reserved bits"
newline
bitfld.long 0x18 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur" "Failure on Segment 0,Failure on Segment 1,Failure on Segment 2,Failure on Segment 3"
newline
bitfld.long 0x18 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)" "No time out error occurred,SelfTest run failed due to a timeout error"
newline
bitfld.long 0x18 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)" "No MISR mismatch for CORE2,Self test run failed due to MISR mismatch for.."
newline
bitfld.long 0x18 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments" "No MISR mismatch for CORE1,Self test run failed due to MISR mismatch for.."
line.long 0x1C "STCSCSCR,Signature compare Self Check Register"
hexmask.long 0x1C 5.--31. 1. "NU7,Reserved bits"
newline
bitfld.long 0x1C 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)" "No fault insertion,Inserts fault in the logic unedr test which will.."
newline
bitfld.long 0x1C 0.--3. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "STC_CADDR2,Current Address register for CORE2"
line.long 0x24 "STC_CLKDIV,Clock Divider Register"
rbitfld.long 0x24 27.--31. "NU8,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 19.--23. "NU9,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 11.--15. "NU10,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 3.--7. "NU11,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
line.long 0x28 "STC_SEGPLR,Segment 1st interval Preload Register"
hexmask.long 0x28 2.--31. 1. "NU12,Reserved bits"
newline
bitfld.long 0x28 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter" "Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of.."
line.long 0x2C "SEG0_START_ADDR,ROM Start address for Segment0"
hexmask.long.word 0x2C 20.--31. 1. "NU13,Reserved bits"
newline
hexmask.long.tbyte 0x2C 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x30 "SEG1_START_ADDR,ROM Start address for Segment1"
hexmask.long.word 0x30 20.--31. 1. "NU14,Reserved bits"
newline
hexmask.long.tbyte 0x30 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x34 "SEG2_START_ADDR,ROM Start address for Segment2"
hexmask.long.word 0x34 20.--31. 1. "NU15,Reserved bits"
newline
hexmask.long.tbyte 0x34 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x38 "SEG3_START_ADDR,ROM Start address for Segment3"
hexmask.long.word 0x38 20.--31. 1. "NU16,Reserved bits"
newline
hexmask.long.tbyte 0x38 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x3C "CORE1_CURMISR_0,Holds the MISR signature for CORE1"
line.long 0x40 "CORE1_CURMISR_1,Holds the MISR signature for CORE1"
line.long 0x44 "CORE1_CURMISR_2,Holds the MISR signature for CORE1"
line.long 0x48 "CORE1_CURMISR_3,Holds the MISR signature for CORE1"
line.long 0x4C "CORE1_CURMISR_4,Holds the MISR signature for CORE1"
line.long 0x50 "CORE1_CURMISR_5,Holds the MISR signature for CORE1"
line.long 0x54 "CORE1_CURMISR_6,Holds the MISR signature for CORE1"
line.long 0x58 "CORE1_CURMISR_7,Holds the MISR signature for CORE1"
line.long 0x5C "CORE1_CURMISR_8,Holds the MISR signature for CORE1"
line.long 0x60 "CORE1_CURMISR_9,Holds the MISR signature for CORE1"
line.long 0x64 "CORE1_CURMISR_10,Holds the MISR signature for CORE1"
line.long 0x68 "CORE1_CURMISR_11,Holds the MISR signature for CORE1"
line.long 0x6C "CORE1_CURMISR_12,Holds the MISR signature for CORE1"
line.long 0x70 "CORE1_CURMISR_13,Holds the MISR signature for CORE1"
line.long 0x74 "CORE1_CURMISR_14,Holds the MISR signature for CORE1"
line.long 0x78 "CORE1_CURMISR_15,Holds the MISR signature for CORE1"
line.long 0x7C "CORE1_CURMISR_16,Holds the MISR signature for CORE1"
line.long 0x80 "CORE1_CURMISR_17,Holds the MISR signature for CORE1"
line.long 0x84 "CORE1_CURMISR_18,Holds the MISR signature for CORE1"
line.long 0x88 "CORE1_CURMISR_19,Holds the MISR signature for CORE1"
line.long 0x8C "CORE1_CURMISR_20,Holds the MISR signature for CORE1"
line.long 0x90 "CORE1_CURMISR_21,Holds the MISR signature for CORE1"
line.long 0x94 "CORE1_CURMISR_22,Holds the MISR signature for CORE1"
line.long 0x98 "CORE1_CURMISR_23,Holds the MISR signature for CORE1"
line.long 0x9C "CORE1_CURMISR_24,Holds the MISR signature for CORE1"
line.long 0xA0 "CORE1_CURMISR_25,Holds the MISR signature for CORE1"
line.long 0xA4 "CORE1_CURMISR_26,Holds the MISR signature for CORE1"
line.long 0xA8 "CORE1_CURMISR_27,Holds the MISR signature for CORE1"
line.long 0xAC "CORE2_CURMISR_0,Holds the MISR signature for CORE2"
line.long 0xB0 "CORE2_CURMISR_1,Holds the MISR signature for CORE2"
line.long 0xB4 "CORE2_CURMISR_2,Holds the MISR signature for CORE2"
line.long 0xB8 "CORE2_CURMISR_3,Holds the MISR signature for CORE2"
line.long 0xBC "CORE2_CURMISR_4,Holds the MISR signature for CORE2"
line.long 0xC0 "CORE2_CURMISR_5,Holds the MISR signature for CORE2"
line.long 0xC4 "CORE2_CURMISR_6,Holds the MISR signature for CORE2"
line.long 0xC8 "CORE2_CURMISR_7,Holds the MISR signature for CORE2"
line.long 0xCC "CORE2_CURMISR_8,Holds the MISR signature for CORE2"
line.long 0xD0 "CORE2_CURMISR_9,Holds the MISR signature for CORE2"
line.long 0xD4 "CORE2_CURMISR_10,Holds the MISR signature for CORE2"
line.long 0xD8 "CORE2_CURMISR_11,Holds the MISR signature for CORE2"
line.long 0xDC "CORE2_CURMISR_12,Holds the MISR signature for CORE2"
line.long 0xE0 "CORE2_CURMISR_13,Holds the MISR signature for CORE2"
line.long 0xE4 "CORE2_CURMISR_14,Holds the MISR signature for CORE2"
line.long 0xE8 "CORE2_CURMISR_15,Holds the MISR signature for CORE2"
line.long 0xEC "CORE2_CURMISR_16,Holds the MISR signature for CORE2"
line.long 0xF0 "CORE2_CURMISR_17,Holds the MISR signature for CORE2"
line.long 0xF4 "CORE2_CURMISR_18,Holds the MISR signature for CORE2"
line.long 0xF8 "CORE2_CURMISR_19,Holds the MISR signature for CORE2"
line.long 0xFC "CORE2_CURMISR_20,Holds the MISR signature for CORE2"
line.long 0x100 "CORE2_CURMISR_21,Holds the MISR signature for CORE2"
line.long 0x104 "CORE2_CURMISR_22,Holds the MISR signature for CORE2"
line.long 0x108 "CORE2_CURMISR_23,Holds the MISR signature for CORE2"
line.long 0x10C "CORE2_CURMISR_24,Holds the MISR signature for CORE2"
line.long 0x110 "CORE2_CURMISR_25,Holds the MISR signature for CORE2"
line.long 0x114 "CORE2_CURMISR_26,Holds the MISR signature for CORE2"
line.long 0x118 "CORE2_CURMISR_27,Holds the MISR signature for CORE2"
width 0x0B
tree.end
tree "DSS_CTRL (DSS CTRL Module Registers)"
base ad:0x6020000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x5B
line.long 0x00 "DSS_SW_INT,"
bitfld.long 0x00 0.--3. "dss_swint,DSS SW Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DSS_TPCC_A_ERRAGG_MASK,"
bitfld.long 0x04 26. "tptc_a1_read_access_error,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 25. "tptc_a0_read_access_error,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 24. "tpcc_a_read_access_error,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 18. "tptc_a1_write_access_error,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPTC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 17. "tptc_a0_write_access_error,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPTC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 16. "tpcc_a_write_access_error,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 8. "tpcc_a_parity_err,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 3. "tptc_a1_err,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 2. "tptc_a0_err,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 1. "tpcc_a_mpint,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 0. "tpcc_a_errint,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x08 "DSS_TPCC_A_ERRAGG_STATUS,"
bitfld.long 0x08 26. "tptc_a1_read_access_error,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 25. "tptc_a0_read_access_error,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 24. "tpcc_a_read_access_error,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 18. "tptc_a1_write_access_error,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 17. "tptc_a0_write_access_error,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 16. "tpcc_a_write_access_error,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 8. "tpcc_a_parity_err,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 3. "tptc_a1_err,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 2. "tptc_a0_err,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 1. "tpcc_a_mpint,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 0. "tpcc_a_errint,Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x0C "DSS_TPCC_A_ERRAGG_STATUS_RAW,"
bitfld.long 0x0C 26. "tptc_a1_read_access_error,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x0C 25. "tptc_a0_read_access_error,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x0C 24. "tpcc_a_read_access_error,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 18. "tptc_a1_write_access_error,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x0C 17. "tptc_a0_write_access_error,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x0C 16. "tpcc_a_write_access_error,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 8. "tpcc_a_parity_err,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 3. "tptc_a1_err,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x0C 2. "tptc_a0_err,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x0C 1. "tpcc_a_mpint,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 0. "tpcc_a_errint,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x10 "DSS_TPCC_A_INTAGG_MASK,"
bitfld.long 0x10 17. "tptc_a1,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 16. "tptc_a0,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 8. "tpcc_a_int7,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 7. "tpcc_a_int6,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 6. "tpcc_a_int5,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 5. "tpcc_a_int4,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 4. "tpcc_a_int3,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 3. "tpcc_a_int2,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 2. "tpcc_a_int1,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 1. "tpcc_a_int0,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 0. "tpcc_a_intg,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x14 "DSS_TPCC_A_INTAGG_STATUS,"
bitfld.long 0x14 17. "tptc_a1,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x14 16. "tptc_a0,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x14 8. "tpcc_a_int7,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 7. "tpcc_a_int6,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 6. "tpcc_a_int5,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 5. "tpcc_a_int4,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 4. "tpcc_a_int3,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 3. "tpcc_a_int2,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 2. "tpcc_a_int1,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 1. "tpcc_a_int0,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 0. "tpcc_a_intg,Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x18 "DSS_TPCC_A_INTAGG_STATUS_RAW,"
bitfld.long 0x18 17. "tptc_a1,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x18 16. "tptc_a0,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x18 8. "tpcc_a_int7,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 7. "tpcc_a_int6,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 6. "tpcc_a_int5,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 5. "tpcc_a_int4,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 4. "tpcc_a_int3,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 3. "tpcc_a_int2,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 2. "tpcc_a_int1,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 1. "tpcc_a_int0,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 0. "tpcc_a_intg,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x1C "DSS_TPCC_B_ERRAGG_MASK,"
bitfld.long 0x1C 26. "tptc_b1_read_access_error,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 25. "tptc_b0_read_access_error,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 24. "tpcc_b_read_access_error,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 18. "tptc_b1_write_access_error,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 17. "tptc_b0_write_access_error,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 16. "tpcc_b_write_access_error,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 8. "tpcc_b_parity_err,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 3. "tptc_b1_err,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 2. "tptc_b0_err,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 1. "tpcc_b_mpint,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 0. "tpcc_b_errint,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x20 "DSS_TPCC_B_ERRAGG_STATUS,"
bitfld.long 0x20 26. "tptc_b1_read_access_error,Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x20 25. "tptc_b0_read_access_error,Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x20 24. "tpcc_b_read_access_error,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 18. "tptc_b1_write_access_error,Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x20 17. "tptc_b0_write_access_error,Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x20 16. "tpcc_b_write_access_error,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 8. "tpcc_b_parity_err,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 3. "tptc_b1_err,Status of Error from DSS_TPCC_B1" "0,1"
newline
bitfld.long 0x20 2. "tptc_b0_err,Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x20 1. "tpcc_b_mpint,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 0. "tpcc_b_errint,Status of Error from DSS_TPCC_B" "0,1"
line.long 0x24 "DSS_TPCC_B_ERRAGG_STATUS_RAW,"
bitfld.long 0x24 26. "tptc_b1_read_access_error,Raw Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x24 25. "tptc_b0_read_access_error,Raw Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x24 24. "tpcc_b_read_access_error,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 18. "tptc_b1_write_access_error,Raw Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x24 17. "tptc_b0_write_access_error,Raw Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x24 16. "tpcc_b_write_access_error,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 8. "tpcc_b_parity_err,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 3. "tptc_b1_err,Raw Status of Error from DSS_TPCC_B1" "0,1"
newline
bitfld.long 0x24 2. "tptc_b0_err,Raw Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x24 1. "tpcc_b_mpint,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 0. "tpcc_b_errint,Raw Status of Error from DSS_TPCC_B" "0,1"
line.long 0x28 "DSS_TPCC_B_INTAGG_MASK,"
bitfld.long 0x28 17. "tptc_b1,Mask Interrupt from DSS_TPTC_B1 to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 16. "tptc_b0,Mask Interrupt from DSS_TPTC_B0 to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 8. "tpcc_b_int7,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 7. "tpcc_b_int6,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 6. "tpcc_b_int5,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 5. "tpcc_b_int4,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 4. "tpcc_b_int3,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 3. "tpcc_b_int2,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 2. "tpcc_b_int1,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 1. "tpcc_b_int0,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 0. "tpcc_b_intg,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x2C "DSS_TPCC_B_INTAGG_STATUS,"
bitfld.long 0x2C 17. "tptc_b1,Status of Interrupt from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x2C 16. "tptc_b0,Status of Interrupt from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x2C 8. "tpcc_b_int7,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 7. "tpcc_b_int6,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 6. "tpcc_b_int5,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 5. "tpcc_b_int4,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 4. "tpcc_b_int3,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 3. "tpcc_b_int2,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 2. "tpcc_b_int1,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 1. "tpcc_b_int0,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 0. "tpcc_b_intg,Status of Interrupt from DSS_TPCC_B" "0,1"
line.long 0x30 "DSS_TPCC_B_INTAGG_STATUS_RAW,"
bitfld.long 0x30 17. "tptc_b1,Raw Status of Interrupt from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x30 16. "tptc_b0,Raw Status of Interrupt from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x30 8. "tpcc_b_int7,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 7. "tpcc_b_int6,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 6. "tpcc_b_int5,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 5. "tpcc_b_int4,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 4. "tpcc_b_int3,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 3. "tpcc_b_int2,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 2. "tpcc_b_int1,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 1. "tpcc_b_int0,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 0. "tpcc_b_intg,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
line.long 0x34 "DSS_TPCC_C_ERRAGG_MASK,"
bitfld.long 0x34 30. "tptc_c5_read_access_error,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 29. "tptc_c4_read_access_error,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 28. "tptc_c3_read_access_error,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 27. "tptc_c2_read_access_error,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 26. "tptc_c1_read_access_error,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 25. "tptc_c0_read_access_error,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 24. "tpcc_c_read_access_error,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 22. "tptc_c5_write_access_error,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 21. "tptc_c4_write_access_error,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 20. "tptc_c3_write_access_error,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 19. "tptc_c2_write_access_error,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 18. "tptc_c1_write_access_error,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 17. "tptc_c0_write_access_error,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 16. "tpcc_c_write_access_error,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 8. "tpcc_c_parity_err,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 7. "tptc_c5_err,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 6. "tptc_c4_err,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 5. "tptc_c3_err,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 4. "tptc_c2_err,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 3. "tptc_c1_err,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 2. "tptc_c0_err,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 1. "tpcc_c_mpint,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 0. "tpcc_c_errint,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x38 "DSS_TPCC_C_ERRAGG_STATUS,"
bitfld.long 0x38 30. "tptc_c5_read_access_error,Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x38 29. "tptc_c4_read_access_error,Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x38 28. "tptc_c3_read_access_error,Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x38 27. "tptc_c2_read_access_error,Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x38 26. "tptc_c1_read_access_error,Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x38 25. "tptc_c0_read_access_error,Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x38 24. "tpcc_c_read_access_error,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 22. "tptc_c5_write_access_error,Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x38 21. "tptc_c4_write_access_error,Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x38 20. "tptc_c3_write_access_error,Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x38 19. "tptc_c2_write_access_error,Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x38 18. "tptc_c1_write_access_error,Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x38 17. "tptc_c0_write_access_error,Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x38 16. "tpcc_c_write_access_error,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 8. "tpcc_c_parity_err,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 7. "tptc_c5_err,Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x38 6. "tptc_c4_err,Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x38 5. "tptc_c3_err,Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x38 4. "tptc_c2_err,Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x38 3. "tptc_c1_err,Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x38 2. "tptc_c0_err,Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x38 1. "tpcc_c_mpint,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 0. "tpcc_c_errint,Status of Error from DSS_TPCC_C" "0,1"
line.long 0x3C "DSS_TPCC_C_ERRAGG_STATUS_RAW,"
bitfld.long 0x3C 30. "tptc_c5_read_access_error,Raw Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x3C 29. "tptc_c4_read_access_error,Raw Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x3C 28. "tptc_c3_read_access_error,Raw Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x3C 27. "tptc_c2_read_access_error,Raw Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x3C 26. "tptc_c1_read_access_error,Raw Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x3C 25. "tptc_c0_read_access_error,Raw Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x3C 24. "tpcc_c_read_access_error,Raw Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x3C 22. "tptc_c5_write_access_error,Raw Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x3C 21. "tptc_c4_write_access_error,Raw Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x3C 20. "tptc_c3_write_access_error,Raw Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x3C 19. "tptc_c2_write_access_error,Raw Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x3C 18. "tptc_c1_write_access_error,Raw Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x3C 17. "tptc_c0_write_access_error,Raw Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x3C 16. "tpcc_c_write_access_error,Raw Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x3C 8. "tpcc_c_parity_err,Raw Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x3C 7. "tptc_c5_err,Raw Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x3C 6. "tptc_c4_err,Raw Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x3C 5. "tptc_c3_err,Raw Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x3C 4. "tptc_c2_err,Raw Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x3C 3. "tptc_c1_err,Raw Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x3C 2. "tptc_c0_err,Raw Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x3C 1. "tpcc_c_mpint,Raw Status of Error from DSS_TPCC_C0" "0,1"
newline
bitfld.long 0x3C 0. "tpcc_c_errint,Raw Status of Error from DSS_TPCC_C" "0,1"
line.long 0x40 "DSS_TPCC_C_INTAGG_MASK,"
bitfld.long 0x40 21. "tptc_c5,Mask Interrupt from DSS_TPTC_C5 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 20. "tptc_c4,Mask Interrupt from DSS_TPTC_C4 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 19. "tptc_c3,Mask Interrupt from DSS_TPTC_C3 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 18. "tptc_c2,Mask Interrupt from DSS_TPTC_C2 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 17. "tptc_c1,Mask Interrupt from DSS_TPTC_C1 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 16. "tptc_c0,Mask Interrupt from DSS_TPTC_C0 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 8. "tpcc_c_int7,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 7. "tpcc_c_int6,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 6. "tpcc_c_int5,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 5. "tpcc_c_int4,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 4. "tpcc_c_int3,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 3. "tpcc_c_int2,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 2. "tpcc_c_int1,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 1. "tpcc_c_int0,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 0. "tpcc_c_intg,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x44 "DSS_TPCC_C_INTAGG_STATUS,"
bitfld.long 0x44 21. "tptc_c5,Status of Interrupt from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x44 20. "tptc_c4,Status of Interrupt from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x44 19. "tptc_c3,Status of Interrupt from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x44 18. "tptc_c2,Status of Interrupt from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x44 17. "tptc_c1,Status of Interrupt from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x44 16. "tptc_c0,Status of Interrupt from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x44 8. "tpcc_c_int7,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 7. "tpcc_c_int6,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 6. "tpcc_c_int5,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 5. "tpcc_c_int4,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 4. "tpcc_c_int3,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 3. "tpcc_c_int2,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 2. "tpcc_c_int1,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 1. "tpcc_c_int0,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 0. "tpcc_c_intg,Status of Interrupt from DSS_TPCC_C" "0,1"
line.long 0x48 "DSS_TPCC_C_INTAGG_STATUS_RAW,"
bitfld.long 0x48 21. "tptc_c5,Raw Status of Interrupt from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x48 20. "tptc_c4,Raw Status of Interrupt from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x48 19. "tptc_c3,Raw Status of Interrupt from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x48 18. "tptc_c2,Raw Status of Interrupt from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x48 17. "tptc_c1,Raw Status of Interrupt from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x48 16. "tptc_c0,Raw Status of Interrupt from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x48 8. "tpcc_c_int7,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 7. "tpcc_c_int6,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 6. "tpcc_c_int5,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 5. "tpcc_c_int4,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 4. "tpcc_c_int3,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 3. "tpcc_c_int2,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 2. "tpcc_c_int1,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 1. "tpcc_c_int0,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 0. "tpcc_c_intg,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
line.long 0x4C "DSS_TPCC_MEMINIT_START,"
bitfld.long 0x4C 2. "tpcc_c_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x4C 1. "tpcc_b_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x4C 0. "tpcc_a_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
line.long 0x50 "DSS_TPCC_MEMINIT_STATUS,"
bitfld.long 0x50 2. "tpcc_c_meminit_status,Status field" "0,1"
newline
bitfld.long 0x50 1. "tpcc_b_meminit_status,Status field" "0,1"
newline
bitfld.long 0x50 0. "tpcc_a_meminit_status,Status field" "0,1"
line.long 0x54 "DSS_TPCC_MEMINIT_DONE,"
bitfld.long 0x54 2. "tpcc_c_meminit_done,Status field" "0,1"
newline
bitfld.long 0x54 1. "tpcc_b_meminit_done,Status field" "0,1"
newline
bitfld.long 0x54 0. "tpcc_a_meminit_done,Status field" "0,1"
line.long 0x58 "DSS_DSP_L2RAM_PARITY_CTRL,"
hexmask.long.byte 0x58 8.--15. 1. "err_clear,Write to bit N to clear L2 Parity Error line N"
newline
hexmask.long.byte 0x58 0.--7. 1. "enable,Write to bit N to enable L2 Parity N"
group.long 0x80++0x23
line.long 0x00 "DSS_DSP_L2RAM_MEMINIT_START,"
bitfld.long 0x00 7. "vb31,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 6. "vb30,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 5. "vb21,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 4. "vb20,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 3. "vb11,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 2. "vb10,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 1. "vb01,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 0. "vb00,Start Memory intialization of DSP L2 memory" "0,1"
line.long 0x04 "DSS_DSP_L2RAM_MEMINIT_STATUS,"
bitfld.long 0x04 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x04 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x04 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x04 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x04 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x04 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x04 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x04 0. "vb00,Status field" "0,1"
line.long 0x08 "DSS_DSP_L2RAM_MEMINIT_DONE,"
bitfld.long 0x08 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x08 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x08 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x08 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x08 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x08 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x08 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x08 0. "vb00,Status field" "0,1"
line.long 0x0C "DSS_DSP_L2RAM_PARITY_MEMINIT_START,"
bitfld.long 0x0C 7. "vb31,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 6. "vb30,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 5. "vb21,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 4. "vb20,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 3. "vb11,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 2. "vb10,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 1. "vb01,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 0. "vb00,Start Memory intialization of DSP L2 Parity memory" "0,1"
line.long 0x10 "DSS_DSP_L2RAM_PARITY_MEMINIT_STATUS,"
bitfld.long 0x10 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x10 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x10 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x10 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x10 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x10 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x10 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x10 0. "vb00,Status field" "0,1"
line.long 0x14 "DSS_DSP_L2RAM_PARITY_MEMINIT_DONE,"
bitfld.long 0x14 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x14 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x14 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x14 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x14 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x14 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x14 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x14 0. "vb00,Status field" "0,1"
line.long 0x18 "DSS_L3RAM_MEMINIT_START,"
bitfld.long 0x18 3. "l3ram3_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x18 2. "l3ram2_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x18 1. "l3ram1_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x18 0. "l3ram0_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
line.long 0x1C "DSS_L3RAM_MEMINIT_STATUS,"
bitfld.long 0x1C 3. "l3ram3_meminit_status,Status field" "0,1"
newline
bitfld.long 0x1C 2. "l3ram2_meminit_status,Status field" "0,1"
newline
bitfld.long 0x1C 1. "l3ram1_meminit_status,Status field" "0,1"
newline
bitfld.long 0x1C 0. "l3ram0_meminit_status,Status field" "0,1"
line.long 0x20 "DSS_L3RAM_MEMINIT_DONE,"
bitfld.long 0x20 3. "l3ram3_meminit_done,Status field" "0,1"
newline
bitfld.long 0x20 2. "l3ram2_meminit_done,Status field" "0,1"
newline
bitfld.long 0x20 1. "l3ram1_meminit_done,Status field" "0,1"
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bitfld.long 0x20 0. "l3ram0_meminit_done,Status field" "0,1"
group.long 0xB0++0x33
line.long 0x00 "DSS_MAILBOX_MEMINIT_START,"
bitfld.long 0x00 0. "meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
line.long 0x04 "DSS_MAILBOX_MEMINIT_STATUS,"
bitfld.long 0x04 0. "meminit_status,Status field" "0,1"
line.long 0x08 "DSS_MAILBOX_MEMINIT_DONE,"
bitfld.long 0x08 0. "meminit_done,Status field" "0,1"
line.long 0x0C "DSS_TPCC_A_PARITY_CTRL,"
bitfld.long 0x0C 2. "parity_err_clr,Write 0x1 to clear the Parit Error status for TPCC" "0,1"
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bitfld.long 0x0C 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
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bitfld.long 0x0C 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x10 "DSS_TPCC_B_PARITY_CTRL,"
bitfld.long 0x10 2. "parity_err_clr,Write 0x1 to clear the Parit Error status for TPCC" "0,1"
newline
bitfld.long 0x10 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
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bitfld.long 0x10 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x14 "DSS_TPCC_C_PARITY_CTRL,"
bitfld.long 0x14 2. "parity_err_clr,Write 0x1 to clear the Parit Error status for TPCC" "0,1"
newline
bitfld.long 0x14 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
newline
bitfld.long 0x14 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x18 "DSS_TPCC_A_PARITY_STATUS,"
hexmask.long.byte 0x18 0.--7. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x1C "DSS_TPCC_B_PARITY_STATUS,"
hexmask.long.byte 0x1C 0.--7. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x20 "DSS_TPCC_C_PARITY_STATUS,"
hexmask.long.word 0x20 0.--8. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x24 "TPTC_DBS_CONFIG,"
bitfld.long 0x24 18.--19. "tptc_c5,Max Burst size tieoff value for TPTC C5" "0,1,2,3"
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bitfld.long 0x24 16.--17. "tptc_c4,Max Burst size tieoff value for TPTC C4" "0,1,2,3"
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bitfld.long 0x24 14.--15. "tptc_c3,Max Burst size tieoff value for TPTC C3" "0,1,2,3"
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bitfld.long 0x24 12.--13. "tptc_c2,Max Burst size tieoff value for TPTC C2" "0,1,2,3"
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bitfld.long 0x24 10.--11. "tptc_c1,Max Burst size tieoff value for TPTC C1" "0,1,2,3"
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bitfld.long 0x24 8.--9. "tptc_c0,Max Burst size tieoff value for TPTC C0" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "tptc_b1,Max Burst size tieoff value for TPTC B0" "0,1,2,3"
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bitfld.long 0x24 4.--5. "tptc_b0,Max Burst size tieoff value for TPTC B0" "0,1,2,3"
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bitfld.long 0x24 2.--3. "tptc_a1,Max Burst size tieoff value for TPTC A1" "0,1,2,3"
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bitfld.long 0x24 0.--1. "tptc_a0,Max Burst size tieoff value for TPTC A0" "0,1,2,3"
line.long 0x28 "DSS_DSP_BOOTCFG,"
bitfld.long 0x28 25. "L1P_CACHE_MODE,DSP Boot Configuration : L1P Cache Mode" "0,1"
newline
bitfld.long 0x28 24. "L1D_CACHE_MODE,DSP Boot Configuration : L1D Cache Mode" "0,1"
newline
hexmask.long.tbyte 0x28 0.--21. 1. "ISTP_RST_VAL,DSP Boot Configuration : Reset Vector"
line.long 0x2C "DSS_DSP_NMI_GATE,"
bitfld.long 0x2C 0.--2. "gate,Write 3'b111 to gate the Non Maskable Interrupt to the DSP" "0,1,2,3,4,5,6,7"
line.long 0x30 "DSS_PBIST_KEY_RESET,"
bitfld.long 0x30 4.--7. "dss_pbist_st_reset,DSS PBIST controller will be brought out of reset when value is 0xA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "dss_pbist_st_key,DSS PBIST Selftest Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xEC++0x17
line.long 0x00 "DSS_TPTC_BOUNDARY_CFG0,"
bitfld.long 0x00 24.--29. "tptc_b1_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--21. "tptc_b0_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "tptc_a1_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "tptc_a0_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DSS_TPTC_BOUNDARY_CFG1,"
bitfld.long 0x04 24.--29. "tptc_c3_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 16.--21. "tptc_c2_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 8.--13. "tptc_c1_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 0.--5. "tptc_c0_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DSS_TPTC_BOUNDARY_CFG2,"
bitfld.long 0x08 8.--13. "tptc_c5_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 0.--5. "tptc_c4_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DSS_TPTC_XID_REORDER_CFG0,"
bitfld.long 0x0C 24. "tptc_b1_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x0C 16. "tptc_b0_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x0C 8. "tptc_a1_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x0C 0. "tptc_a0_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
line.long 0x10 "DSS_TPTC_XID_REORDER_CFG1,"
bitfld.long 0x10 24. "tptc_c3_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x10 16. "tptc_c2_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x10 8. "tptc_c1_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x10 0. "tptc_c0_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
line.long 0x14 "DSS_TPTC_XID_REORDER_CFG2,"
bitfld.long 0x14 8. "tptc_c5_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x14 0. "tptc_c4_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
group.long 0x108++0x0F
line.long 0x00 "ESM_GATING0,"
line.long 0x04 "ESM_GATING1,"
line.long 0x08 "ESM_GATING2,"
line.long 0x0C "ESM_GATING3,"
group.long 0x560++0x37
line.long 0x00 "DSS_PERIPH_ERRAGG_MASK0,"
bitfld.long 0x00 11. "rcss_ctrl_wr,Mask the Write error from RCSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 10. "rcss_ctrl_rd,Mask the Read error from RCSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 9. "rcss_rcm_wr,Mask the Write error from RCSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 8. "rcss_rcm_rd,Mask the Read error from RCSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 7. "dss_hwa_cfg_wr,Mask the Write error from DSS_HWA_CFG space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
newline
bitfld.long 0x00 6. "dss_hwa_cfg_rd,Mask the Read error from DSS_HWA_CFG space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
newline
bitfld.long 0x00 5. "dss_cm4_ctrl_wr,Mask the Write error from DSS_CM4_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 4. "dss_cm4_ctrl_rd,Mask the Read error from DSS_CM4_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 3. "dss_ctrl_wr,Mask the Write error from DSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 2. "dss_ctrl_rd,Mask the Read error from DSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 1. "dss_rcm_wr,Mask the Write error from DSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 0. "dss_rcm_rd,Mask the Read error from DSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
line.long 0x04 "DSS_PERIPH_ERRAGG_STATUS0,"
bitfld.long 0x04 11. "rcss_ctrl_wr,Status of the Write error from RCSS_CTRL space" "0,1"
newline
bitfld.long 0x04 10. "rcss_ctrl_rd,Status of the Read error from RCSS_CTRL space" "0,1"
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bitfld.long 0x04 9. "rcss_rcm_wr,Status of the Write error from RCSS_RCM space" "0,1"
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bitfld.long 0x04 8. "rcss_rcm_rd,Status of the Read error from RCSS_RCM space" "0,1"
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bitfld.long 0x04 7. "dss_hwa_cfg_wr,Status of the Write error from DSS_HWA_CFG space" "0,1"
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bitfld.long 0x04 6. "dss_hwa_cfg_rd,Status of the Read error from DSS_HWA_CFG space" "0,1"
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bitfld.long 0x04 5. "dss_cm4_ctrl_wr,Status of the Write error from DSS_CM4_CTRL space" "0,1"
newline
bitfld.long 0x04 4. "dss_cm4_ctrl_rd,Status of the Read error from DSS_CM4_CTRL space" "0,1"
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bitfld.long 0x04 3. "dss_ctrl_wr,Status of the Write error from DSS_CTRL space" "0,1"
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bitfld.long 0x04 2. "dss_ctrl_rd,Status of the Read error from DSS_CTRL space" "0,1"
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bitfld.long 0x04 1. "dss_rcm_wr,Status of the Write error from DSS_RCM space" "0,1"
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bitfld.long 0x04 0. "dss_rcm_rd,Status of the Read error from DSS_RCM space" "0,1"
line.long 0x08 "DSS_PERIPH_ERRAGG_STATUS_RAW0,"
bitfld.long 0x08 11. "rcss_ctrl_wr,Raw Status of the Write error from RCSS_CTRL space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 10. "rcss_ctrl_rd,Raw Status of the Read error from RCSS_CTRL space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 9. "rcss_rcm_wr,Raw Status of the Write error from RCSS_RCM space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 8. "rcss_rcm_rd,Raw Status of the Read error from RCSS_RCM space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 7. "dss_hwa_cfg_wr,Raw Status of the Write error from DSS_HWA_CFG space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 6. "dss_hwa_cfg_rd,Raw Status of the Read error from DSS_HWA_CFG space irrespective of it being masked" "0,1"
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bitfld.long 0x08 5. "dss_cm4_ctrl_wr,Raw Status of the Write error from DSS_CM4_CTRL space irrespective of it being masked" "0,1"
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bitfld.long 0x08 4. "dss_cm4_ctrl_rd,Raw Status of the Read error from DSS_CM4_CTRL space irrespective of it being masked" "0,1"
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bitfld.long 0x08 3. "dss_ctrl_wr,Raw Status of the Write error from DSS_CTRL space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 2. "dss_ctrl_rd,Raw Status of the Read error from DSS_CTRL space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 1. "dss_rcm_wr,Raw Status of the Write error from DSS_RCM space irrespective of it being masked" "0,1"
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bitfld.long 0x08 0. "dss_rcm_rd,Raw Status of the Read error from DSS_RCM space irrespective of it being masked" "0,1"
line.long 0x0C "DSS_DSP_MBOX_WRITE_DONE,"
bitfld.long 0x0C 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
newline
bitfld.long 0x0C 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
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bitfld.long 0x0C 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
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bitfld.long 0x0C 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
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bitfld.long 0x0C 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
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bitfld.long 0x0C 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
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bitfld.long 0x0C 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
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bitfld.long 0x0C 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0x10 "DSS_DSP_MBOX_READ_REQ,"
bitfld.long 0x10 28. "proc_7,This is request from processor 7 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 24. "proc_6,This is request from processor 6 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 20. "proc_5,This is request from processor 5 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 16. "proc_4,This is request from processor 4 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 12. "proc_3,This is request from processor 3 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 8. "proc_2,This is request from processor 2 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 4. "proc_1,This is request from processor 1 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 0. "proc_0,This is request from processor 0 to DSS_DSP" "0,1"
line.long 0x14 "DSS_DSP_MBOX_READ_DONE,"
bitfld.long 0x14 28. "proc_7,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 7" "0,1"
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bitfld.long 0x14 24. "proc_6,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 6" "0,1"
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bitfld.long 0x14 20. "proc_5,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 5" "0,1"
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bitfld.long 0x14 16. "proc_4,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 4" "0,1"
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bitfld.long 0x14 12. "proc_3,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 3" "0,1"
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bitfld.long 0x14 8. "proc_2,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 2" "0,1"
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bitfld.long 0x14 4. "proc_1,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 1" "0,1"
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bitfld.long 0x14 0. "proc_0,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 0" "0,1"
line.long 0x18 "DSS_WDT_EVENT_CAPTURE_SEL,"
hexmask.long.byte 0x18 8.--14. 1. "cap1,Select the DSS_WDT Capture Event 1 from the DSS DSP Interrupt Map"
newline
hexmask.long.byte 0x18 0.--6. 1. "cap0,Select the DSS_WDT Capture Event 0 from the DSS DSP Interrupt Map"
line.long 0x1C "DSS_RTIA_EVENT_CAPTURE_SEL,"
hexmask.long.byte 0x1C 8.--14. 1. "cap1,Select the DSS_RTIA Capture Event 1 from the DSS DSP Interrupt Map"
newline
hexmask.long.byte 0x1C 0.--6. 1. "cap0,Select the DSS_RTIA Capture Event 0 from the DSS DSP Interrupt Map"
line.long 0x20 "DSS_RTIB_EVENT_CAPTURE_SEL,"
hexmask.long.byte 0x20 8.--14. 1. "cap1,Select the DSS_RTIB Capture Event 1 from the DSS DSP Interrupt Map"
newline
hexmask.long.byte 0x20 0.--6. 1. "cap0,Select the DSS_RTIB Capture Event 0 from the DSS DSP Interrupt Map"
line.long 0x24 "DBG_ACK_CPU_CTRL,"
bitfld.long 0x24 0. "sel,Select the Processor Suspend that is used to Suspend the DSS Peripehrals" "DSP,MSS CR5"
line.long 0x28 "DBG_ACK_CTL0,"
bitfld.long 0x28 20.--22. "DSS_WDT,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 16.--18. "DSS_SCIA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 12.--14. "DSS_RTIB,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 8.--10. "DSS_RTIA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 4.--6. "DSS_DCCB,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x28 0.--2. "DSS_DCCA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x2C "DBG_ACK_CTL1,"
bitfld.long 0x2C 28.--30. "DSS_HWA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x2C 24.--26. "DSS_MCRC,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x30 "DSS_DSP_INT_SEL,"
bitfld.long 0x30 0.--2. "RCSS_CSI2_ICSSM,DSS DSP Interrupt selcet" "CSI2 Interrupts are propagated to DSP,?,?,?,?,?,?,ICSSM Interrupts are propagted to DSP"
line.long 0x34 "DSS_CBUFF_TRIGGER_SEL,"
hexmask.long.byte 0x34 0.--6. 1. "sel,DSS CBUFF HW Trigger select from DSS DSP Interrupt Map"
group.long 0x800++0x17
line.long 0x00 "DSS_BUS_SAFETY_CTRL,"
bitfld.long 0x00 4.--6. "clk_disable,Option to clock gate the safety infrastructure is Safety is disabled" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x04 "DSS_BUS_SAFETY_SEC_ERR_STAT0,"
bitfld.long 0x04 28. "DSS_MDO_FIFO,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 27. "DSS_CBUFF_FIFO,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 26. "DSS_PCR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 25. "DSS_TPTC_C5_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 24. "DSS_TPTC_C4_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 23. "DSS_TPTC_C3_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 22. "DSS_TPTC_C2_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 21. "DSS_TPTC_C1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 20. "DSS_TPTC_C0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 19. "DSS_TPTC_B1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 18. "DSS_TPTC_B0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 17. "DSS_TPTC_A1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 16. "DSS_TPTC_A0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 15. "DSS_TPTC_C5_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 14. "DSS_TPTC_C4_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 13. "DSS_TPTC_C3_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 12. "DSS_TPTC_C2_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 11. "DSS_TPTC_C1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 10. "DSS_TPTC_C0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 9. "DSS_TPTC_B1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 8. "DSS_TPTC_B0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 7. "DSS_TPTC_A1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 6. "DSS_TPTC_A0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 5. "DSS_DSP_SDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 4. "DSS_L3_BANKD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 3. "DSS_L3_BANKC,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 2. "DSS_L3_BANKB,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 1. "DSS_L3_BANKA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0. "DSS_DSP_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x08 "DSS_BUS_SAFETY_SEC_ERR_STAT1,"
bitfld.long 0x08 5. "DSS_MBOX,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 4. "DSS_CM4_S,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 3. "DSS_CM4_M,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 2. "DSS_HWA_DMA1,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 1. "DSS_HWA_DMA0,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 0. "DSS_MCRC,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x0C "DSS_DSP_MDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x0C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x0C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x0C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x10 "DSS_DSP_MDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x10 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x14 "DSS_DSP_MDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x14 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x820++0x1B
line.long 0x00 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKA_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x844++0x1B
line.long 0x00 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKB_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKB_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x868++0x1B
line.long 0x00 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKC_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x88C++0x1B
line.long 0x00 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKD_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x8B0++0x277
line.long 0x00 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_DSP_SDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_DSP_SDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_DSP_SDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1C "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x20 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x24 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x28 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x2C "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x30 "DSS_TPTC_A0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x30 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x30 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x30 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x34 "DSS_TPTC_A0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x34 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x34 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x34 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x34 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x38 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x38 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x38 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x38 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x38 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3C "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x40 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x44 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x48 "DSS_TPTC_A1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x48 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x48 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x48 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4C "DSS_TPTC_A1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x4C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x50 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x50 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x50 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x50 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x50 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x54 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x54 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x54 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x54 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x54 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x58 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x5C "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x60 "DSS_TPTC_B0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x60 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x60 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x60 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x64 "DSS_TPTC_B0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x64 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x64 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x68 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x68 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x6C "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x6C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x70 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x74 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x78 "DSS_TPTC_B1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x78 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x78 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x78 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x7C "DSS_TPTC_B1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x7C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x7C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x7C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x7C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x80 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x80 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x80 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x80 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x80 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x84 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x84 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x88 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x8C "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x90 "DSS_TPTC_C0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x90 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x90 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x90 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x94 "DSS_TPTC_C0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x94 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x94 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x94 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x94 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x98 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x98 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x98 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x98 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x98 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x9C "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x9C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x9C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x9C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x9C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xA0 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xA4 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xA8 "DSS_TPTC_C1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xA8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xAC "DSS_TPTC_C1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xAC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xAC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xB0 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xB0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB4 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xB4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB8 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xBC "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xC0 "DSS_TPTC_C2_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xC0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xC4 "DSS_TPTC_C2_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xC4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xC8 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xC8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xCC "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xCC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xD0 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xD4 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xD8 "DSS_TPTC_C3_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xD8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xD8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xD8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xDC "DSS_TPTC_C3_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xDC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xDC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xDC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xDC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xE0 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xE0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xE4 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xE4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xE8 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xEC "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xF0 "DSS_TPTC_C4_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xF0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xF0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xF4 "DSS_TPTC_C4_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xF4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xF4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xF8 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xF8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xFC "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xFC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xFC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xFC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xFC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x100 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x104 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x108 "DSS_TPTC_C5_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x108 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x108 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x108 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x10C "DSS_TPTC_C5_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x10C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x110 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x110 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x110 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x110 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x110 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x114 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x114 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x114 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x114 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x114 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x118 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x11C "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x120 "DSS_TPTC_A0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x120 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x120 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x120 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x124 "DSS_TPTC_A0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x124 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x124 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x124 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x124 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x128 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x128 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x128 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x128 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x128 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x12C "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x12C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x12C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x12C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x12C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x130 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x134 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x138 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x13C "DSS_TPTC_A1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x13C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x13C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x13C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x140 "DSS_TPTC_A1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x140 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x140 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x140 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x140 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x144 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x144 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x144 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x144 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x144 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x148 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x148 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x148 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x148 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x148 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x14C "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x150 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x154 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x158 "DSS_TPTC_B0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x158 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x158 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x158 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x15C "DSS_TPTC_B0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x15C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x15C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x15C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x15C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x160 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x160 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x160 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x160 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x160 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x164 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x164 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x164 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x164 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x164 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x168 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x16C "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x170 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x174 "DSS_TPTC_B1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x174 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x174 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x174 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x178 "DSS_TPTC_B1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x178 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x178 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x178 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x178 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x17C "DSS_TPTC_B1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x17C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x17C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x17C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x17C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x180 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x180 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x180 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x180 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x180 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x184 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x188 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x18C "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x190 "DSS_TPTC_C0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x190 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x190 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x190 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x194 "DSS_TPTC_C0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x194 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x194 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x194 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x194 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x198 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x198 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x198 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x198 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x198 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x19C "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x19C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x19C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x19C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x19C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1A0 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1A4 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1A8 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1AC "DSS_TPTC_C1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1AC 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1AC 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1AC 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "DSS_TPTC_C1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1B0 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B0 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B0 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1B0 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1B4 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1B4 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B8 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1B8 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1BC "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1C0 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1C4 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1C8 "DSS_TPTC_C2_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1C8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1CC "DSS_TPTC_C2_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1CC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1CC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1CC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1CC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1D0 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1D0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1D4 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1D4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1D8 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1DC "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1E0 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1E4 "DSS_TPTC_C3_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1E4 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E4 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1E8 "DSS_TPTC_C3_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1E8 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E8 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1EC "DSS_TPTC_C3_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1EC 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1F0 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1F0 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F0 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1F4 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1F8 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1FC "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x200 "DSS_TPTC_C4_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x200 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x200 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x200 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x204 "DSS_TPTC_C4_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x204 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x204 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x208 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x208 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x20C "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x20C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x210 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x214 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x218 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x21C "DSS_TPTC_C5_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x21C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x21C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x21C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x220 "DSS_TPTC_C5_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x220 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x220 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x220 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x220 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x224 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x224 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x228 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x228 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x22C "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x230 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x234 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x238 "DSS_MDO_FIFO_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x238 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x238 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x238 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x23C "DSS_MDO_FIFO_BUS_SAFETY_FI,"
hexmask.long.byte 0x23C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x23C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x23C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x23C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x240 "DSS_MDO_FIFO_BUS_SAFETY_ERR,"
hexmask.long.byte 0x240 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x240 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x240 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x240 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x244 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x244 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x244 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x244 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x244 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x248 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x24C "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x250 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x254 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x258 "DSS_CBUFF_FIFO_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x258 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x258 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x258 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x25C "DSS_CBUFF_FIFO_BUS_SAFETY_FI,"
hexmask.long.byte 0x25C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x25C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x25C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x25C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x260 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR,"
hexmask.long.byte 0x260 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x260 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x260 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x260 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x264 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x264 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x264 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x264 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x264 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x268 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x26C "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x270 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x274 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_WRITERESP,"
group.long 0xBC8++0xDF
line.long 0x00 "DSS_MCRC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x00 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x00 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x00 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x04 "DSS_MCRC_BUS_SAFETY_FI,"
hexmask.long.byte 0x04 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x04 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x08 "DSS_MCRC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x08 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x0C "DSS_MCRC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x0C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x10 "DSS_MCRC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x14 "DSS_MCRC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x18 "DSS_MCRC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1C "DSS_MCRC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x20 "DSS_PCR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x20 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x20 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x20 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x24 "DSS_PCR_BUS_SAFETY_FI,"
hexmask.long.byte 0x24 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x24 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x28 "DSS_PCR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x28 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2C "DSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x30 "DSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x34 "DSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x38 "DSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3C "DSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x40 "DSS_HWA_DMA0_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x40 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x40 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x40 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x44 "DSS_HWA_DMA0_BUS_SAFETY_FI,"
hexmask.long.byte 0x44 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x44 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x48 "DSS_HWA_DMA0_BUS_SAFETY_ERR,"
hexmask.long.byte 0x48 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4C "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x50 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x54 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x58 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x5C "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x60 "DSS_HWA_DMA1_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x60 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x60 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x60 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x64 "DSS_HWA_DMA1_BUS_SAFETY_FI,"
hexmask.long.byte 0x64 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x64 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x68 "DSS_HWA_DMA1_BUS_SAFETY_ERR,"
hexmask.long.byte 0x68 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x6C "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x6C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x70 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x74 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x78 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x7C "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x80 "DSS_CM4_M_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x80 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x80 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x80 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x84 "DSS_CM4_M_BUS_SAFETY_FI,"
hexmask.long.byte 0x84 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x84 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x88 "DSS_CM4_M_BUS_SAFETY_ERR,"
hexmask.long.byte 0x88 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x8C "DSS_CM4_M_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x8C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x90 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x94 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x98 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x9C "DSS_CM4_M_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xA0 "DSS_CM4_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xA0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xA4 "DSS_CM4_S_BUS_SAFETY_FI,"
hexmask.long.byte 0xA4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xA8 "DSS_CM4_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0xA8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xAC "DSS_CM4_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xAC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB0 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xB4 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0xB8 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xBC "DSS_CM4_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xC0 "DSS_MBOX_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xC0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xC4 "DSS_MBOX_BUS_SAFETY_FI,"
hexmask.long.byte 0xC4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xC8 "DSS_MBOX_BUS_SAFETY_ERR,"
hexmask.long.byte 0xC8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xCC "DSS_MBOX_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xCC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xD0 "DSS_MBOX_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xD4 "DSS_MBOX_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0xD8 "DSS_MBOX_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xDC "DSS_MBOX_BUS_SAFETY_ERR_STAT_WRITERESP,"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x8A8)++0x03
line.long 0x00 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x884)++0x03
line.long 0x00 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x860)++0x03
line.long 0x00 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x83C)++0x03
line.long 0x00 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x818)++0x03
line.long 0x00 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xE4)++0x03
line.long 0x00 "DSS_PBIST_REG$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x70)++0x03
line.long 0x00 "DSS_DSP_L2RAM_PARITY_ERR_STATUS_VB$1,"
hexmask.long.word 0x00 16.--27. 1. "addr1,Error address 1 for Virtual Bank 0"
hexmask.long.word 0x00 0.--11. 1. "addr0,Error address 0 for Virtual Bank 0"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_DCCA (DSS DCCA Module Registers)"
base ad:0x6F79C00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "DSS_DCCB (DSS DCCB Module Registers)"
base ad:0x6F79D00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "DSS_DSP_PBIST (DSS DSP PBIST Module Registers)"
base ad:0x6F79000
hgroup.long 0x120++0x07
hide.long 0x00 "PBIST_DD10,DD0 Data Register 16 (D0)"
hide.long 0x04 "PBIST_DE10,DE0 Data Register 16 (D0)"
group.long 0x160++0x03
line.long 0x00 "PBIST_RAMT,RAM Configuration (RAMT -RAM)"
hexmask.long.byte 0x00 24.--31. 1. "RGS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 16.--23. 1. "RDS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 8.--15. 1. "DWR,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 0.--7. 1. "RAM,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
group.word 0x164++0x01
line.word 0x00 "PBIST_DLR,Datalogger 0"
hexmask.word.byte 0x00 8.--15. 1. "DLR1,Datalogger Register [8] : Reserevd [9] : Default Testing Mode"
hexmask.word.byte 0x00 0.--7. 1. "DLR0,Datalogger Register [1:0] : Reserved [2] : ROM-based testing mode"
group.byte 0x168++0x00
line.byte 0x00 "PBIST_CMS,Clock mux select"
bitfld.byte 0x00 0.--3. "PBIST_CMS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x16C++0x00
line.byte 0x00 "PBIST_PC,Program Control"
bitfld.byte 0x00 0.--4. "PBIST_PC,TI Internal Register.Reserved for HW RnD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x178++0x03
line.long 0x00 "PBIST_CS,Chip Select 0"
hexmask.long.byte 0x00 24.--31. 1. "CS3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "CS2,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 8.--15. 1. "CS1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "CS0,TI Internal Register.Reserved for HW RnD"
group.byte 0x17C++0x00
line.byte 0x00 "PBIST_FDLY,Fail Delay"
group.byte 0x180++0x00
line.byte 0x00 "PBIST_PACT,Pbist Active"
bitfld.byte 0x00 0. "PBIST_PACT,Pbist Active/ROM Clock Enable Register [0]: This bit must be set to turn on internal PBIST clocks" "Disable internal PBIST clocks Value,Enable internal PBIST clocks"
group.byte 0x184++0x00
line.byte 0x00 "PBIST_ID,PBIST ID"
bitfld.byte 0x00 0.--4. "PBIST_ID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hgroup.long 0x188++0x03
hide.long 0x00 "PBIST_OVR,PBIST Overrides"
rgroup.byte 0x190++0x00
line.byte 0x00 "PBIST_FSFR0,Fail status fail - port 0"
bitfld.byte 0x00 0. "PBIST_FSFR0,Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x194++0x00
line.byte 0x00 "PBIST_FSFR1,Fail status fail - port 1"
bitfld.byte 0x00 0. "PBIST_FSFR1,Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x198++0x00
line.byte 0x00 "PBIST_FSRCR0,Fail Count fail - port 0"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR0,Fail Status Count - Port 0 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x19C++0x00
line.byte 0x00 "PBIST_FSRCR1,Fail Count fail - port 1"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR1,Fail Status Count - Port 1 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1A0++0x03
hide.long 0x00 "PBIST_FSRA0,Fail status address - port 0"
rgroup.word 0x1A4++0x01
line.word 0x00 "PBIST_FSRA1,Fail status address - port 1"
hgroup.long 0x1B4++0x0B
hide.long 0x00 "PBIST_MARGIN,Margin Mode"
hide.long 0x04 "PBIST_WRENZ,WRENZ"
hide.long 0x08 "PBIST_PGS,PAGE/PGS"
group.byte 0x1C0++0x00
line.byte 0x00 "PBIST_ROM,Rom Mask"
bitfld.byte 0x00 0.--1. "PBIST_ROM,Rom Mask" "No information is used from ROM Value,Only RAM Group information from ROM Vaule,Only Algorithm information from ROM Value,Both Algorithm and RAM information from ROM"
group.long 0x1C4++0x0B
line.long 0x00 "PBIST_ALGO,ROM Algorithm Mask 0"
hexmask.long.byte 0x00 24.--31. 1. "ALGO3,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 16.--23. 1. "ALGO2,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 8.--15. 1. "ALGO1,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 0.--7. 1. "ALGO0,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
line.long 0x04 "PBIST_RINFOL,RAM Info Mask Lower 0"
hexmask.long.byte 0x04 24.--31. 1. "RINFOL3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 16.--23. 1. "RINFOL2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 8.--15. 1. "RINFOL1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 0.--7. 1. "RINFOL0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
line.long 0x08 "PBIST_RINFOU,RAM Info Mask Upper 0"
hexmask.long.byte 0x08 24.--31. 1. "RINFOU3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 16.--23. 1. "RINFOU2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 8.--15. 1. "RINFOU1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 0.--7. 1. "RINFOU0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
repeat 2. (list 0. 1. )(list 0x00 0x08 )
rgroup.long ($2+0x1A8)++0x03
line.long 0x00 "PBIST_FSRDL$1,Fail status Data - port 0"
repeat.end
repeat 2. (list 1. 4. )(list 0x00 0x04 )
group.long ($2+0x170)++0x03
line.long 0x00 "PBIST_SCR$1,Address Scramble 0 -3"
hexmask.long.byte 0x00 24.--31. 1. "SCR3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "SCR2,TI Internal Register.Reserved for HW RnD"
newline
hexmask.long.byte 0x00 8.--15. 1. "SCR1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "SCR0,TI Internal Register.Reserved for HW RnD"
repeat.end
repeat 2. (list 2. 3. )(list 0x00 0x04 )
group.word ($2+0x158)++0x01
line.word 0x00 "PBIST_CI$1,Constant Increment Register2"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
hgroup.long ($2+0x150)++0x03
hide.long 0x00 "PBIST_CI$1,Constant Increment Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x140)++0x03
hide.long 0x00 "PBIST_CL$1,Constant Loop Count Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x130)++0x03
hide.long 0x00 "PBIST_CA$1,Constant Address Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x110)++0x03
hide.long 0x00 "PBIST_L$1,Variable Loop Count Register L0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x100)++0x03
hide.long 0x00 "PBIST_A$1,Variable Address Register0"
repeat.end
width 0x0B
tree.end
tree "DSS_DSP_STC (DSS DSP STC Module Registers)"
base ad:0x6F79200
group.long 0x00++0x11B
line.long 0x00 "STCGCR0,Self test Global control Reg0"
hexmask.long.word 0x00 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run"
newline
rbitfld.long 0x00 11.--15. "NU0,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval" "Continue NSTC run from previous interval,Restart NSTC run from ROM address 0 1X = Start..,?..."
line.long 0x04 "STCGCR1,Self test Global control Reg1"
hexmask.long.tbyte 0x04 12.--31. 1. "NU2,Reserved bits"
newline
bitfld.long 0x04 8.--11. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x04 7. "NU3,Reserved bits" "0,1"
newline
bitfld.long 0x04 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode" "XOR mode,Spread mode"
newline
bitfld.long 0x04 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration" "Operates in Normal Scan Mode,Operates in Low Power Scan Mode"
newline
bitfld.long 0x04 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
newline
bitfld.long 0x04 0.--3. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "STCTPR,Time out counter preload register"
line.long 0x0C "STC_CADDR,Current Address register for CORE1"
line.long 0x10 "STCCICR,Current Interval count register"
hexmask.long.word 0x10 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well"
newline
hexmask.long.word 0x10 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run"
line.long 0x14 "STCGSTAT,Global Status Register"
hexmask.long.tbyte 0x14 12.--31. 1. "NU4,Reserved bits"
newline
bitfld.long 0x14 8.--11. "ST_ACTIVE,Tells whether self test is currently active or not" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 2.--7. "NU5,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)" "Self test run has not failed,SelfTest run has failed"
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bitfld.long 0x14 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)" "Not completed,SelfTest run Completed"
line.long 0x18 "STCFSTAT,Fail Status Register"
hexmask.long 0x18 5.--31. 1. "NU6,Reserved bits"
newline
bitfld.long 0x18 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur" "Failure on Segment 0,Failure on Segment 1,Failure on Segment 2,Failure on Segment 3"
newline
bitfld.long 0x18 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)" "No time out error occurred,SelfTest run failed due to a timeout error"
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bitfld.long 0x18 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)" "No MISR mismatch for CORE2,Self test run failed due to MISR mismatch for.."
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bitfld.long 0x18 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments" "No MISR mismatch for CORE1,Self test run failed due to MISR mismatch for.."
line.long 0x1C "STCSCSCR,Signature compare Self Check Register"
hexmask.long 0x1C 5.--31. 1. "NU7,Reserved bits"
newline
bitfld.long 0x1C 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)" "No fault insertion,Inserts fault in the logic unedr test which will.."
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bitfld.long 0x1C 0.--3. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "STC_CADDR2,Current Address register for CORE2"
line.long 0x24 "STC_CLKDIV,Clock Divider Register"
rbitfld.long 0x24 27.--31. "NU8,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 19.--23. "NU9,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 11.--15. "NU10,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 3.--7. "NU11,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
line.long 0x28 "STC_SEGPLR,Segment 1st interval Preload Register"
hexmask.long 0x28 2.--31. 1. "NU12,Reserved bits"
newline
bitfld.long 0x28 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter" "Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of.."
line.long 0x2C "SEG0_START_ADDR,ROM Start address for Segment0"
hexmask.long.word 0x2C 20.--31. 1. "NU13,Reserved bits"
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hexmask.long.tbyte 0x2C 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x30 "SEG1_START_ADDR,ROM Start address for Segment1"
hexmask.long.word 0x30 20.--31. 1. "NU14,Reserved bits"
newline
hexmask.long.tbyte 0x30 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x34 "SEG2_START_ADDR,ROM Start address for Segment2"
hexmask.long.word 0x34 20.--31. 1. "NU15,Reserved bits"
newline
hexmask.long.tbyte 0x34 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x38 "SEG3_START_ADDR,ROM Start address for Segment3"
hexmask.long.word 0x38 20.--31. 1. "NU16,Reserved bits"
newline
hexmask.long.tbyte 0x38 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x3C "CORE1_CURMISR_0,Holds the MISR signature for CORE1"
line.long 0x40 "CORE1_CURMISR_1,Holds the MISR signature for CORE1"
line.long 0x44 "CORE1_CURMISR_2,Holds the MISR signature for CORE1"
line.long 0x48 "CORE1_CURMISR_3,Holds the MISR signature for CORE1"
line.long 0x4C "CORE1_CURMISR_4,Holds the MISR signature for CORE1"
line.long 0x50 "CORE1_CURMISR_5,Holds the MISR signature for CORE1"
line.long 0x54 "CORE1_CURMISR_6,Holds the MISR signature for CORE1"
line.long 0x58 "CORE1_CURMISR_7,Holds the MISR signature for CORE1"
line.long 0x5C "CORE1_CURMISR_8,Holds the MISR signature for CORE1"
line.long 0x60 "CORE1_CURMISR_9,Holds the MISR signature for CORE1"
line.long 0x64 "CORE1_CURMISR_10,Holds the MISR signature for CORE1"
line.long 0x68 "CORE1_CURMISR_11,Holds the MISR signature for CORE1"
line.long 0x6C "CORE1_CURMISR_12,Holds the MISR signature for CORE1"
line.long 0x70 "CORE1_CURMISR_13,Holds the MISR signature for CORE1"
line.long 0x74 "CORE1_CURMISR_14,Holds the MISR signature for CORE1"
line.long 0x78 "CORE1_CURMISR_15,Holds the MISR signature for CORE1"
line.long 0x7C "CORE1_CURMISR_16,Holds the MISR signature for CORE1"
line.long 0x80 "CORE1_CURMISR_17,Holds the MISR signature for CORE1"
line.long 0x84 "CORE1_CURMISR_18,Holds the MISR signature for CORE1"
line.long 0x88 "CORE1_CURMISR_19,Holds the MISR signature for CORE1"
line.long 0x8C "CORE1_CURMISR_20,Holds the MISR signature for CORE1"
line.long 0x90 "CORE1_CURMISR_21,Holds the MISR signature for CORE1"
line.long 0x94 "CORE1_CURMISR_22,Holds the MISR signature for CORE1"
line.long 0x98 "CORE1_CURMISR_23,Holds the MISR signature for CORE1"
line.long 0x9C "CORE1_CURMISR_24,Holds the MISR signature for CORE1"
line.long 0xA0 "CORE1_CURMISR_25,Holds the MISR signature for CORE1"
line.long 0xA4 "CORE1_CURMISR_26,Holds the MISR signature for CORE1"
line.long 0xA8 "CORE1_CURMISR_27,Holds the MISR signature for CORE1"
line.long 0xAC "CORE2_CURMISR_0,Holds the MISR signature for CORE2"
line.long 0xB0 "CORE2_CURMISR_1,Holds the MISR signature for CORE2"
line.long 0xB4 "CORE2_CURMISR_2,Holds the MISR signature for CORE2"
line.long 0xB8 "CORE2_CURMISR_3,Holds the MISR signature for CORE2"
line.long 0xBC "CORE2_CURMISR_4,Holds the MISR signature for CORE2"
line.long 0xC0 "CORE2_CURMISR_5,Holds the MISR signature for CORE2"
line.long 0xC4 "CORE2_CURMISR_6,Holds the MISR signature for CORE2"
line.long 0xC8 "CORE2_CURMISR_7,Holds the MISR signature for CORE2"
line.long 0xCC "CORE2_CURMISR_8,Holds the MISR signature for CORE2"
line.long 0xD0 "CORE2_CURMISR_9,Holds the MISR signature for CORE2"
line.long 0xD4 "CORE2_CURMISR_10,Holds the MISR signature for CORE2"
line.long 0xD8 "CORE2_CURMISR_11,Holds the MISR signature for CORE2"
line.long 0xDC "CORE2_CURMISR_12,Holds the MISR signature for CORE2"
line.long 0xE0 "CORE2_CURMISR_13,Holds the MISR signature for CORE2"
line.long 0xE4 "CORE2_CURMISR_14,Holds the MISR signature for CORE2"
line.long 0xE8 "CORE2_CURMISR_15,Holds the MISR signature for CORE2"
line.long 0xEC "CORE2_CURMISR_16,Holds the MISR signature for CORE2"
line.long 0xF0 "CORE2_CURMISR_17,Holds the MISR signature for CORE2"
line.long 0xF4 "CORE2_CURMISR_18,Holds the MISR signature for CORE2"
line.long 0xF8 "CORE2_CURMISR_19,Holds the MISR signature for CORE2"
line.long 0xFC "CORE2_CURMISR_20,Holds the MISR signature for CORE2"
line.long 0x100 "CORE2_CURMISR_21,Holds the MISR signature for CORE2"
line.long 0x104 "CORE2_CURMISR_22,Holds the MISR signature for CORE2"
line.long 0x108 "CORE2_CURMISR_23,Holds the MISR signature for CORE2"
line.long 0x10C "CORE2_CURMISR_24,Holds the MISR signature for CORE2"
line.long 0x110 "CORE2_CURMISR_25,Holds the MISR signature for CORE2"
line.long 0x114 "CORE2_CURMISR_26,Holds the MISR signature for CORE2"
line.long 0x118 "CORE2_CURMISR_27,Holds the MISR signature for CORE2"
width 0x0B
tree.end
tree "DSS_ECC_AGG (DSS ECC AGG Module Registers)"
base ad:0x60A0000
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 22. "RCSS_TPTC_B1_PEND,Interrupt Pending Status for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x04 21. "RCSS_TPTC_B0_PEND,Interrupt Pending Status for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x04 20. "RCSS_TPTC_A1_PEND,Interrupt Pending Status for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x04 19. "RCSS_TPTC_A0_PEND,Interrupt Pending Status for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x04 18. "DSS_TPTC_C5_PEND,Interrupt Pending Status for dss_tptc_c5_pend" "0,1"
bitfld.long 0x04 17. "DSS_TPTC_C4_PEND,Interrupt Pending Status for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x04 16. "DSS_TPTC_C3_PEND,Interrupt Pending Status for dss_tptc_c3_pend" "0,1"
bitfld.long 0x04 15. "DSS_TPTC_C2_PEND,Interrupt Pending Status for dss_tptc_c2_pend" "0,1"
bitfld.long 0x04 14. "DSS_TPTC_C1_PEND,Interrupt Pending Status for dss_tptc_c1_pend" "0,1"
bitfld.long 0x04 13. "DSS_TPTC_C0_PEND,Interrupt Pending Status for dss_tptc_c0_pend" "0,1"
bitfld.long 0x04 12. "DSS_TPTC_B1_PEND,Interrupt Pending Status for dss_tptc_b1_pend" "0,1"
bitfld.long 0x04 11. "DSS_TPTC_B0_PEND,Interrupt Pending Status for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x04 10. "DSS_TPTC_A1_PEND,Interrupt Pending Status for dss_tptc_a1_pend" "0,1"
bitfld.long 0x04 9. "DSS_TPTC_A0_PEND,Interrupt Pending Status for dss_tptc_a0_pend" "0,1"
bitfld.long 0x04 8. "HWACM4_MAILBOX_PEND,Interrupt Pending Status for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x04 7. "HWACM4_RAM_B2_PEND,Interrupt Pending Status for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x04 6. "HWACM4_RAM_B1_PEND,Interrupt Pending Status for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x04 5. "HWACM4_RAM_B0_PEND,Interrupt Pending Status for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x04 4. "DSS_MAILBOX_PEND,Interrupt Pending Status for dss_mailbox_pend" "0,1"
bitfld.long 0x04 3. "DSS_L3RAM3_PEND,Interrupt Pending Status for dss_l3ram3_pend" "0,1"
bitfld.long 0x04 2. "DSS_L3RAM2_PEND,Interrupt Pending Status for dss_l3ram2_pend" "0,1"
bitfld.long 0x04 1. "DSS_L3RAM1_PEND,Interrupt Pending Status for dss_l3ram1_pend" "0,1"
bitfld.long 0x04 0. "DSS_L3RAM0_PEND,Interrupt Pending Status for dss_l3ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 22. "RCSS_TPTC_B1_PEND,Interrupt Pending Status for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x04 21. "RCSS_TPTC_B0_PEND,Interrupt Pending Status for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x04 20. "RCSS_TPTC_A1_PEND,Interrupt Pending Status for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x04 19. "RCSS_TPTC_A0_PEND,Interrupt Pending Status for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x04 18. "DSS_TPTC_C5_PEND,Interrupt Pending Status for dss_tptc_c5_pend" "0,1"
bitfld.long 0x04 17. "DSS_TPTC_C4_PEND,Interrupt Pending Status for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x04 16. "DSS_TPTC_C3_PEND,Interrupt Pending Status for dss_tptc_c3_pend" "0,1"
bitfld.long 0x04 15. "DSS_TPTC_C2_PEND,Interrupt Pending Status for dss_tptc_c2_pend" "0,1"
bitfld.long 0x04 14. "DSS_TPTC_C1_PEND,Interrupt Pending Status for dss_tptc_c1_pend" "0,1"
bitfld.long 0x04 13. "DSS_TPTC_C0_PEND,Interrupt Pending Status for dss_tptc_c0_pend" "0,1"
bitfld.long 0x04 12. "DSS_TPTC_B1_PEND,Interrupt Pending Status for dss_tptc_b1_pend" "0,1"
bitfld.long 0x04 11. "DSS_TPTC_B0_PEND,Interrupt Pending Status for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x04 10. "DSS_TPTC_A1_PEND,Interrupt Pending Status for dss_tptc_a1_pend" "0,1"
bitfld.long 0x04 9. "DSS_TPTC_A0_PEND,Interrupt Pending Status for dss_tptc_a0_pend" "0,1"
bitfld.long 0x04 8. "HWACM4_MAILBOX_PEND,Interrupt Pending Status for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x04 7. "HWACM4_RAM_B2_PEND,Interrupt Pending Status for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x04 6. "HWACM4_RAM_B1_PEND,Interrupt Pending Status for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x04 5. "HWACM4_RAM_B0_PEND,Interrupt Pending Status for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x04 4. "DSS_MAILBOX_PEND,Interrupt Pending Status for dss_mailbox_pend" "0,1"
bitfld.long 0x04 3. "DSS_L3RAM3_PEND,Interrupt Pending Status for dss_l3ram3_pend" "0,1"
bitfld.long 0x04 2. "DSS_L3RAM2_PEND,Interrupt Pending Status for dss_l3ram2_pend" "0,1"
bitfld.long 0x04 1. "DSS_L3RAM1_PEND,Interrupt Pending Status for dss_l3ram1_pend" "0,1"
bitfld.long 0x04 0. "DSS_L3RAM0_PEND,Interrupt Pending Status for dss_l3ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "DSS_ESM (DSS ESM Module Registers)"
base ad:0x6F7D000
group.long 0x00++0x5B
line.long 0x00 "ESMIEPSR1,ESM Enable ERROR Pin Action/Response Register 1"
line.long 0x04 "ESMIEPCR1,ESM Disable ERROR Pin Action/Response Register 1"
line.long 0x08 "ESMIESR1,ESM Interrupt Enable Set/Status Register 1"
line.long 0x0C "ESMIECR1,ESM Interrupt Enable Clear/Status Register 1"
line.long 0x10 "ESMILSR1,Interrupt Level Set/Status Register 1"
line.long 0x14 "ESMILCR1,Interrupt Level Clear/Status Register 1"
line.long 0x18 "ESMSR1,ESM Status Register 1"
line.long 0x1C "ESMSR2,ESM Status Register 2"
line.long 0x20 "ESMSR3,ESM Status Register 3"
line.long 0x24 "ESMEPSR,ESM ERROR Pin Status Register"
hexmask.long 0x24 1.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EPSF,ERROR Pin Status Flag" "0,1"
line.long 0x28 "ESMIOFFHR,ESM Interrupt Offset High Register"
hexmask.long.tbyte 0x28 9.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x28 0.--8. 1. "INTOFFH,Offset High Level Interrupt"
line.long 0x2C "ESMIOFFLR,ESM Interrupt Offset Low Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x2C 0.--7. 1. "INTOFFL,Offset Low Level Interrupt"
line.long 0x30 "ESMLTCR,ESM Low-Time Counter Register"
hexmask.long.word 0x30 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x30 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin"
line.long 0x34 "ESMLTCPR,ESM Low-Time Counter Preload Register"
hexmask.long.word 0x34 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x34 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter"
line.long 0x38 "ESMEKR,ESM Error Key Register"
hexmask.long 0x38 4.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0.--3. "EKEY,Error Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "ESMSSR2,ESM Status Shadow Register 2"
line.long 0x40 "ESMIEPSR4,ESM Enable ERROR Pin Action/Response Register 4"
line.long 0x44 "ESMIEPCR4,ESM Disable ERROR Pin Action/Response Register 4"
line.long 0x48 "ESMIESR4,ESM Interrupt Enable Set/Status Register 4"
line.long 0x4C "ESMIECR4,ESM Interrupt Enable Clear/Status Register 4"
line.long 0x50 "ESMILSR4,Interrupt Level Set/Status Register 4"
line.long 0x54 "ESMILCR4,Interrupt Level Clear/Status Register 4"
line.long 0x58 "ESMSR4,ESM Status Register 4"
group.long 0x80++0x1B
line.long 0x00 "ESMIEPSR7,ESM Enable ERROR Pin Action/Response Register 7"
line.long 0x04 "ESMIEPCR7,ESM Disable ERROR Pin Action/Response Register 7"
line.long 0x08 "ESMIESR7,ESM Interrupt Enable Set/Status Register 7"
line.long 0x0C "ESMIECR7,ESM Interrupt Enable Clear/Status Register 7"
line.long 0x10 "ESMILSR7,Interrupt Level Set/Status Register 7"
line.long 0x14 "ESMILCR7,Interrupt Level Clear/Status Register 7"
line.long 0x18 "ESMSR7,ESM Status Register 7"
group.long 0xC0++0x1B
line.long 0x00 "ESMIEPSR10,ESM Enable ERROR Pin Action/Response Register 10"
line.long 0x04 "ESMIEPCR10,ESM Disable ERROR Pin Action/Response Register 10"
line.long 0x08 "ESMIESR10,ESM Interrupt Enable Set/Status Register 10"
line.long 0x0C "ESMIECR10,ESM Interrupt Enable Clear/Status Register 10"
line.long 0x10 "ESMILSR10,Interrupt Level Set/Status Register 10"
line.long 0x14 "ESMILCR10,Interrupt Level Clear/Status Register 10"
line.long 0x18 "ESMSR10,ESM Status Register 10"
width 0x0B
tree.end
tree "DSS_HWA_CFG (DSS HWA CFG Module Registers)"
base ad:0x6062000
rgroup.long 0x00++0x457
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
newline
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PARAM_RAM_IDX,"
hexmask.long.word 0x04 16.--25. 1. "param_end_idx,The state machine starts at the parameter-set specified by PARAM_START_IDX and loads each parameter-set one after another and runs the accelerator as per that configuration"
newline
hexmask.long.word 0x04 0.--9. 1. "param_start_idx,The state machine starts at the parameter-set specified by PARAM_START_IDX and loads each parameter-set one after another and runs the accelerator as per that configuration"
line.long 0x08 "PARAM_RAM_LOOP,"
hexmask.long.word 0x08 0.--11. 1. "numloops,Number of loops: This register controls the number of times the State Machine will loop through the parameter-sets (from a programmed start index till a programmed end index) and run them"
line.long 0x0C "PARAM_RAM_IDX_ALT,"
hexmask.long.word 0x0C 16.--25. 1. "param_end_idx,PARAM_END_IDX for alternate thread"
newline
hexmask.long.word 0x0C 0.--9. 1. "param_start_idx,PARAM_START_IDX for alternate thread"
line.long 0x10 "PARAM_RAM_LOOP_ALT,"
hexmask.long.word 0x10 0.--11. 1. "numloops,NUMLOOPS for alternate thread"
line.long 0x14 "PREVIOUS_NAME,"
bitfld.long 0x14 24. "hwa_dyn_clk_en,Dynamic Clock-gating Control: Setting this register bit to '1' enables the capability to clock gate the 4 Radar Accelerator core IPs (FFT datapath CFAR Memory compression Local Maxima) based on the ParamSet being executed" "0,1"
newline
bitfld.long 0x14 16.--18. "hwa_reset,Software Reset Control: This register provides software reset control for the Radar Hardware Accelerator" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 8.--10. "hwa_clk_en,Clock-gating Control: This register controls the enable/disable for the clock of the Radar Accelerator" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0.--2. "hwa_en,Enable/Disable Control: A value of ACC_ENABLE = 111b enables the Radar Hardware Accelerator and any other value of the register keeps the Accelerator Engine in disabled state" "0,1,2,3,4,5,6,7"
line.long 0x18 "CS_CONFIG,"
bitfld.long 0x18 16.--20. "cs_trgsrc,In case of DMA trigger this specifies which DMA channel (which bit in DMA2HWA_TRIG register) to wait for In case of HW-based trigger this specifies which CSI2 trigger signal (out of the 20 possible trigger signals) to wait for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--11. "cs_trigmode,Trigger mode for context switching" "?,?,?,DMA-based trigger (used in conjunction with..,Hardware based trigger (used in conjunction with..,Software trigger (used in conjunction with..,?..."
newline
bitfld.long 0x18 0. "cs_enable,Master enable for the Conxtext switching feature.Setting this bit will allow context switching to ALT thread if it is enabled in the Param set" "0,1"
line.long 0x1C "FW2DMA_TRIG,"
line.long 0x20 "DMA2HWA_TRIG,"
line.long 0x24 "SIGDMACH0DONE,"
line.long 0x28 "SIGDMACH1DONE,"
line.long 0x2C "SIGDMACH2DONE,"
line.long 0x30 "SIGDMACH3DONE,"
line.long 0x34 "SIGDMACH4DONE,"
line.long 0x38 "SIGDMACH5DONE,"
line.long 0x3C "SIGDMACH6DONE,"
line.long 0x40 "SIGDMACH7DONE,"
line.long 0x44 "SIGDMACH8DONE,"
line.long 0x48 "SIGDMACH9DONE,"
line.long 0x4C "SIGDMACH10DONE,"
line.long 0x50 "SIGDMACH11DONE,"
line.long 0x54 "SIGDMACH12DONE,"
line.long 0x58 "SIGDMACH13DONE,"
line.long 0x5C "SIGDMACH14DONE,"
line.long 0x60 "SIGDMACH15DONE,"
line.long 0x64 "SIGDMACH16DONE,"
line.long 0x68 "SIGDMACH17DONE,"
line.long 0x6C "SIGDMACH18DONE,"
line.long 0x70 "SIGDMACH19DONE,"
line.long 0x74 "SIGDMACH20DONE,"
line.long 0x78 "SIGDMACH21DONE,"
line.long 0x7C "SIGDMACH22DONE,"
line.long 0x80 "SIGDMACH23DONE,"
line.long 0x84 "SIGDMACH24DONE,"
line.long 0x88 "SIGDMACH25DONE,"
line.long 0x8C "SIGDMACH26DONE,"
line.long 0x90 "SIGDMACH27DONE,"
line.long 0x94 "SIGDMACH28DONE,"
line.long 0x98 "SIGDMACH29DONE,"
line.long 0x9C "SIGDMACH30DONE,"
line.long 0xA0 "SIGDMACH31DONE,"
line.long 0xA4 "FW2HWA_TRIG_0,"
bitfld.long 0xA4 0. "fw2hwa_trigger_0,Software trigger bit" "0,1"
line.long 0xA8 "FW2HWA_TRIG_1,"
bitfld.long 0xA8 0. "fw2hwa_trigger_1,Software trigger bit" "0,1"
line.long 0xAC "CS_FW2ACC_TRIG,"
bitfld.long 0xAC 0. "fw2hwa_trigger_cs,CPU can set this register bit to trigger a context switch when CS_TRIGMODE = 101b It s a Self clearing bit" "0,1"
line.long 0xB0 "BPM_PATTERN_0,"
line.long 0xB4 "BPM_PATTERN_1,"
line.long 0xB8 "BPM_PATTERN_2,"
line.long 0xBC "BPM_PATTERN_3,"
line.long 0xC0 "BPM_PATTERN_4,"
line.long 0xC4 "BPM_PATTERN_5,"
line.long 0xC8 "BPM_PATTERN_6,"
line.long 0xCC "BPM_PATTERN_7,"
line.long 0xD0 "BPM_RATE,"
hexmask.long.word 0xD0 0.--9. 1. "bpm_rate,BPM rate: Specifies the number of input samples corresponding to each BPM bit"
line.long 0xD4 "PARAM_DONE_SET_STATUS_0,"
line.long 0xD8 "PARAM_DONE_SET_STATUS_1,"
line.long 0xDC "PARAM_DONE_CLR_0,"
line.long 0xE0 "PARAM_DONE_CLR_1,"
line.long 0xE4 "TRIGGER_SET_STATUS_0,"
line.long 0xE8 "TRIGGER_SET_STATUS_1,"
line.long 0xEC "TRIGGER_SET_IN_CLR_0,"
bitfld.long 0xEC 0. "trigger_set_in_clr_0,Clear trigger_set_status : This register-bit when set clears the trigger status register TRIGGER_SET_STATUS_0 described above It s a Self clearing bit" "0,1"
line.long 0xF0 "TRIGGER_SET_IN_CLR_1,"
bitfld.long 0xF0 0. "trigger_set_in_clr_1,Clear trigger_set_status : This register-bit when set clears the trigger status register TRIGGER_SET_STATUS_1 described above It s a Self clearing bit" "0,1"
line.long 0xF4 "DC_EST_RESET_SW,"
bitfld.long 0xF4 0. "dc_est_reset_sw,Reset for all 12 DC estimation accumulators It s a Self clearing bit" "0,1"
line.long 0xF8 "DC_EST_CTRL,"
bitfld.long 0xF8 16.--19. "dc_est_shift,Programmable shift applied to all 12 accumulator outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0xF8 0.--8. 1. "dc_est_scale,9-bit scale applied to all 12 accumulators"
line.long 0xFC "DC_EST_I_0_VAL,"
hexmask.long.tbyte 0xFC 0.--23. 1. "dc_est_i_0_val,This read only register provide the DC estimates I for bcnt= 0"
line.long 0x100 "DC_EST_I_1_VAL,"
hexmask.long.tbyte 0x100 0.--23. 1. "dc_est_i_1_val,This read only register provide the DC estimates I for bcnt= 1"
line.long 0x104 "DC_EST_I_2_VAL,"
hexmask.long.tbyte 0x104 0.--23. 1. "dc_est_i_2_val,This read only register provide the DC estimates I for bcnt= 2"
line.long 0x108 "DC_EST_I_3_VAL,"
hexmask.long.tbyte 0x108 0.--23. 1. "dc_est_i_3_val,This read only register provide the DC estimates I for bcnt= 3"
line.long 0x10C "DC_EST_I_4_VAL,"
hexmask.long.tbyte 0x10C 0.--23. 1. "dc_est_i_4_val,This read only register provide the DC estimates I for bcnt= 4"
line.long 0x110 "DC_EST_I_5_VAL,"
hexmask.long.tbyte 0x110 0.--23. 1. "dc_est_i_5_val,This read only register provide the DC estimates I for bcnt= 5"
line.long 0x114 "DC_EST_I_6_VAL,"
hexmask.long.tbyte 0x114 0.--23. 1. "dc_est_i_6_val,This read only register provide the DC estimates I for bcnt= 6"
line.long 0x118 "DC_EST_I_7_VAL,"
hexmask.long.tbyte 0x118 0.--23. 1. "dc_est_i_7_val,This read only register provide the DC estimates I for bcnt= 7"
line.long 0x11C "DC_EST_I_8_VAL,"
hexmask.long.tbyte 0x11C 0.--23. 1. "dc_est_i_8_val,This read only register provide the DC estimates I for bcnt= 8"
line.long 0x120 "DC_EST_I_9_VAL,"
hexmask.long.tbyte 0x120 0.--23. 1. "dc_est_i_9_val,This read only register provide the DC estimates I for bcnt= 9"
line.long 0x124 "DC_EST_I_10_VAL,"
hexmask.long.tbyte 0x124 0.--23. 1. "dc_est_i_10_val,This read only register provide the DC estimates I for bcnt= 10"
line.long 0x128 "DC_EST_I_11_VAL,"
hexmask.long.tbyte 0x128 0.--23. 1. "dc_est_i_11_val,This read only register provide the DC estimates I for bcnt= 11"
line.long 0x12C "DC_EST_Q_0_VAL,"
hexmask.long.tbyte 0x12C 0.--23. 1. "dc_est_q_0_val,This read only register provide the DC estimates Q for bcnt= 0"
line.long 0x130 "DC_EST_Q_1_VAL,"
hexmask.long.tbyte 0x130 0.--23. 1. "dc_est_q_1_val,This read only register provide the DC estimates Q for bcnt= 1"
line.long 0x134 "DC_EST_Q_2_VAL,"
hexmask.long.tbyte 0x134 0.--23. 1. "dc_est_q_2_val,This read only register provide the DC estimates Q for bcnt= 2"
line.long 0x138 "DC_EST_Q_3_VAL,"
hexmask.long.tbyte 0x138 0.--23. 1. "dc_est_q_3_val,This read only register provide the DC estimates Q for bcnt= 3"
line.long 0x13C "DC_EST_Q_4_VAL,"
hexmask.long.tbyte 0x13C 0.--23. 1. "dc_est_q_4_val,This read only register provide the DC estimates Q for bcnt= 4"
line.long 0x140 "DC_EST_Q_5_VAL,"
hexmask.long.tbyte 0x140 0.--23. 1. "dc_est_q_5_val,This read only register provide the DC estimates Q for bcnt= 5"
line.long 0x144 "DC_EST_Q_6_VAL,"
hexmask.long.tbyte 0x144 0.--23. 1. "dc_est_q_6_val,This read only register provide the DC estimates Q for bcnt= 6"
line.long 0x148 "DC_EST_Q_7_VAL,"
hexmask.long.tbyte 0x148 0.--23. 1. "dc_est_q_7_val,This read only register provide the DC estimates Q for bcnt= 7"
line.long 0x14C "DC_EST_Q_8_VAL,"
hexmask.long.tbyte 0x14C 0.--23. 1. "dc_est_q_8_val,This read only register provide the DC estimates Q for bcnt= 8"
line.long 0x150 "DC_EST_Q_9_VAL,"
hexmask.long.tbyte 0x150 0.--23. 1. "dc_est_q_9_val,This read only register provide the DC estimates Q for bcnt= 9"
line.long 0x154 "DC_EST_Q_10_VAL,"
hexmask.long.tbyte 0x154 0.--23. 1. "dc_est_q_10_val,This read only register provide the DC estimates Q for bcnt= 10"
line.long 0x158 "DC_EST_Q_11_VAL,"
hexmask.long.tbyte 0x158 0.--23. 1. "dc_est_q_11_val,This read only register provide the DC estimates Q for bcnt= 11"
line.long 0x15C "DC_ACC_I_0_VAL_LSB,"
line.long 0x160 "DC_ACC_I_0_VAL_MSB,"
bitfld.long 0x160 0.--3. "dc_acc_i_0_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "DC_ACC_I_1_VAL_LSB,"
line.long 0x168 "DC_ACC_I_1_VAL_MSB,"
bitfld.long 0x168 0.--3. "dc_acc_i_1_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "DC_ACC_I_2_VAL_LSB,"
line.long 0x170 "DC_ACC_I_2_VAL_MSB,"
bitfld.long 0x170 0.--3. "dc_acc_i_2_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "DC_ACC_I_3_VAL_LSB,"
line.long 0x178 "DC_ACC_I_3_VAL_MSB,"
bitfld.long 0x178 0.--3. "dc_acc_i_3_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "DC_ACC_I_4_VAL_LSB,"
line.long 0x180 "DC_ACC_I_4_VAL_MSB,"
bitfld.long 0x180 0.--3. "dc_acc_i_4_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "DC_ACC_I_5_VAL_LSB,"
line.long 0x188 "DC_ACC_I_5_VAL_MSB,"
bitfld.long 0x188 0.--3. "dc_acc_i_5_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "DC_ACC_I_6_VAL_LSB,"
line.long 0x190 "DC_ACC_I_6_VAL_MSB,"
bitfld.long 0x190 0.--3. "dc_acc_i_6_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "DC_ACC_I_7_VAL_LSB,"
line.long 0x198 "DC_ACC_I_7_VAL_MSB,"
bitfld.long 0x198 0.--3. "dc_acc_i_7_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "DC_ACC_I_8_VAL_LSB,"
line.long 0x1A0 "DC_ACC_I_8_VAL_MSB,"
bitfld.long 0x1A0 0.--3. "dc_acc_i_8_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "DC_ACC_I_9_VAL_LSB,"
line.long 0x1A8 "DC_ACC_I_9_VAL_MSB,"
bitfld.long 0x1A8 0.--3. "dc_acc_i_9_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "DC_ACC_I_10_VAL_LSB,"
line.long 0x1B0 "DC_ACC_I_10_VAL_MSB,"
bitfld.long 0x1B0 0.--3. "dc_acc_i_10_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "DC_ACC_I_11_VAL_LSB,"
line.long 0x1B8 "DC_ACC_I_11_VAL_MSB,"
bitfld.long 0x1B8 0.--3. "dc_acc_i_11_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "DC_ACC_Q_0_VAL_LSB,"
line.long 0x1C0 "DC_ACC_Q_0_VAL_MSB,"
bitfld.long 0x1C0 0.--3. "dc_acc_q_0_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "DC_ACC_Q_1_VAL_LSB,"
line.long 0x1C8 "DC_ACC_Q_1_VAL_MSB,"
bitfld.long 0x1C8 0.--3. "dc_acc_q_1_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "DC_ACC_Q_2_VAL_LSB,"
line.long 0x1D0 "DC_ACC_Q_2_VAL_MSB,"
bitfld.long 0x1D0 0.--3. "dc_acc_q_2_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "DC_ACC_Q_3_VAL_LSB,"
line.long 0x1D8 "DC_ACC_Q_3_VAL_MSB,"
bitfld.long 0x1D8 0.--3. "dc_acc_q_3_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "DC_ACC_Q_4_VAL_LSB,"
line.long 0x1E0 "DC_ACC_Q_4_VAL_MSB,"
bitfld.long 0x1E0 0.--3. "dc_acc_q_4_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "DC_ACC_Q_5_VAL_LSB,"
line.long 0x1E8 "DC_ACC_Q_5_VAL_MSB,"
bitfld.long 0x1E8 0.--3. "dc_acc_q_5_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1EC "DC_ACC_Q_6_VAL_LSB,"
line.long 0x1F0 "DC_ACC_Q_6_VAL_MSB,"
bitfld.long 0x1F0 0.--3. "dc_acc_q_6_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F4 "DC_ACC_Q_7_VAL_LSB,"
line.long 0x1F8 "DC_ACC_Q_7_VAL_MSB,"
bitfld.long 0x1F8 0.--3. "dc_acc_q_7_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1FC "DC_ACC_Q_8_VAL_LSB,"
line.long 0x200 "DC_ACC_Q_8_VAL_MSB,"
bitfld.long 0x200 0.--3. "dc_acc_q_8_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x204 "DC_ACC_Q_9_VAL_LSB,"
line.long 0x208 "DC_ACC_Q_9_VAL_MSB,"
bitfld.long 0x208 0.--3. "dc_acc_q_9_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20C "DC_ACC_Q_10_VAL_LSB,"
line.long 0x210 "DC_ACC_Q_10_VAL_MSB,"
bitfld.long 0x210 0.--3. "dc_acc_q_10_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x214 "DC_ACC_Q_11_VAL_LSB,"
line.long 0x218 "DC_ACC_Q_11_VAL_MSB,"
bitfld.long 0x218 0.--3. "dc_acc_q_11_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x21C "DC_ACC_CLIP_STATUS,"
hexmask.long.word 0x21C 0.--11. 1. "dc_acc_clip_status,This register contains the clip status of both I/Q of DC accumulators 0 to 11"
line.long 0x220 "DC_EST_CLIP_STATUS,"
hexmask.long.word 0x220 0.--11. 1. "dc_est_clip_status,This register contains the clip status of DC estimates (both I & Q combined)"
line.long 0x224 "DC_I0_SW,"
hexmask.long.tbyte 0x224 0.--23. 1. "dc_i0_sw,SW programmed DC I value(for bcnt =0 ) used in DC subtraction"
line.long 0x228 "DC_I1_SW,"
hexmask.long.tbyte 0x228 0.--23. 1. "dc_i1_sw,SW programmed DC I value(for bcnt =1) used in DC subtraction"
line.long 0x22C "DC_I2_SW,"
hexmask.long.tbyte 0x22C 0.--23. 1. "dc_i2_sw,SW programmed DC I value(for bcnt =2 ) used in DC subtraction"
line.long 0x230 "DC_I3_SW,"
hexmask.long.tbyte 0x230 0.--23. 1. "dc_i3_sw,SW programmed DC I value(for bcnt =3) used in DC subtraction"
line.long 0x234 "DC_I4_SW,"
hexmask.long.tbyte 0x234 0.--23. 1. "dc_i4_sw,SW programmed DC I value(for bcnt =4 ) used in DC subtraction"
line.long 0x238 "DC_I5_SW,"
hexmask.long.tbyte 0x238 0.--23. 1. "dc_i5_sw,SW programmed DC I value(for bcnt =5 ) used in DC subtraction"
line.long 0x23C "DC_I6_SW,"
hexmask.long.tbyte 0x23C 0.--23. 1. "dc_i6_sw,SW programmed DC I value(for bcnt =6 ) used in DC subtraction"
line.long 0x240 "DC_I7_SW,"
hexmask.long.tbyte 0x240 0.--23. 1. "dc_i7_sw,SW programmed DC I value(for bcnt =7 ) used in DC subtraction"
line.long 0x244 "DC_I8_SW,"
hexmask.long.tbyte 0x244 0.--23. 1. "dc_i8_sw,SW programmed DC I value(for bcnt =8) used in DC subtraction"
line.long 0x248 "DC_I9_SW,"
hexmask.long.tbyte 0x248 0.--23. 1. "dc_i9_sw,SW programmed DC I value(for bcnt =9 ) used in DC subtraction"
line.long 0x24C "DC_I10_SW,"
hexmask.long.tbyte 0x24C 0.--23. 1. "dc_i10_sw,SW programmed DC I value(for bcnt =10 ) used in DC subtraction"
line.long 0x250 "DC_I11_SW,"
hexmask.long.tbyte 0x250 0.--23. 1. "dc_i11_sw,SW programmed DC I value(for bcnt =11) used in DC subtraction"
line.long 0x254 "DC_Q0_SW,"
hexmask.long.tbyte 0x254 0.--23. 1. "dc_q0_sw,SW programmed DC Q value(for bcnt =0 ) used in DC subtraction"
line.long 0x258 "DC_Q1_SW,"
hexmask.long.tbyte 0x258 0.--23. 1. "dc_q1_sw,SW programmed DC Q value(for bcnt =1) used in DC subtraction"
line.long 0x25C "DC_Q2_SW,"
hexmask.long.tbyte 0x25C 0.--23. 1. "dc_q2_sw,SW programmed DC Q value(for bcnt =2 ) used in DC subtraction"
line.long 0x260 "DC_Q3_SW,"
hexmask.long.tbyte 0x260 0.--23. 1. "dc_q3_sw,SW programmed DC Q value(for bcnt =3) used in DC subtraction"
line.long 0x264 "DC_Q4_SW,"
hexmask.long.tbyte 0x264 0.--23. 1. "dc_q4_sw,SW programmed DC Q value(for bcnt =4 ) used in DC subtraction"
line.long 0x268 "DC_Q5_SW,"
hexmask.long.tbyte 0x268 0.--23. 1. "dc_q5_sw,SW programmed DC Q value(for bcnt =5 ) used in DC subtraction"
line.long 0x26C "DC_Q6_SW,"
hexmask.long.tbyte 0x26C 0.--23. 1. "dc_q6_sw,SW programmed DC Q value(for bcnt =6 ) used in DC subtraction"
line.long 0x270 "DC_Q7_SW,"
hexmask.long.tbyte 0x270 0.--23. 1. "dc_q7_sw,SW programmed DC Q value(for bcnt =7 ) used in DC subtraction"
line.long 0x274 "DC_Q8_SW,"
hexmask.long.tbyte 0x274 0.--23. 1. "dc_q8_sw,SW programmed DC Q value(for bcnt =8) used in DC subtraction"
line.long 0x278 "DC_Q9_SW,"
hexmask.long.tbyte 0x278 0.--23. 1. "dc_q9_sw,SW programmed DC Q value(for bcnt =9 ) used in DC subtraction"
line.long 0x27C "DC_Q10_SW,"
hexmask.long.tbyte 0x27C 0.--23. 1. "dc_q10_sw,SW programmed DC Q value(for bcnt =10 ) used in DC subtraction"
line.long 0x280 "DC_Q11_SW,"
hexmask.long.tbyte 0x280 0.--23. 1. "dc_q11_sw,SW programmed DC Q value(for bcnt =11) used in DC subtraction"
line.long 0x284 "DC_SUB_CLIP,"
bitfld.long 0x284 0. "DC_SUB_CLIP,Indicates the DC subtraction clip status" "0,1"
line.long 0x288 "DC_RESERVED_2,"
line.long 0x28C "DC_RESERVED_3,"
line.long 0x290 "DC_RESERVED_4,"
line.long 0x294 "DC_RESERVED_5,"
line.long 0x298 "INTF_STATS_RESET_SW,"
bitfld.long 0x298 0. "intf_stats_reset_sw,SW reset for Interference stats module" "0,1"
line.long 0x29C "INTF_STATS_CTRL,"
hexmask.long.byte 0x29C 24.--31. 1. "intf_stats_magdiff_scale,Unsigned scaler (5.3) applied to INTERFSUM_MAGDIFFn from interference statistics block"
newline
hexmask.long.byte 0x29C 16.--23. 1. "intf_stats_mag_scale,Unsigned scaler (5.3) applied to INTERFSUM_MAGn from interference statistics block"
newline
bitfld.long 0x29C 4.--6. "intf_stats_magdiff_shift,Right shift applied after scaling - 2^(6+INTERFSUM_MAGDIFF_SHIFT)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x29C 0.--2. "intf_stats_mag_shift,Right shift applied after scaling - 2^(6+INTERSUM_MAGS_SHIFT)" "0,1,2,3,4,5,6,7"
line.long 0x2A0 "INTF_LOC_THRESH_MAG0_VAL,"
hexmask.long.tbyte 0x2A0 0.--23. 1. "intf_loc_thresh_mag0_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =0"
line.long 0x2A4 "INTF_LOC_THRESH_MAG1_VAL,"
hexmask.long.tbyte 0x2A4 0.--23. 1. "intf_loc_thresh_mag1_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =1"
line.long 0x2A8 "INTF_LOC_THRESH_MAG2_VAL,"
hexmask.long.tbyte 0x2A8 0.--23. 1. "intf_loc_thresh_mag2_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =2"
line.long 0x2AC "INTF_LOC_THRESH_MAG3_VAL,"
hexmask.long.tbyte 0x2AC 0.--23. 1. "intf_loc_thresh_mag3_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =3"
line.long 0x2B0 "INTF_LOC_THRESH_MAG4_VAL,"
hexmask.long.tbyte 0x2B0 0.--23. 1. "intf_loc_thresh_mag4_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =4"
line.long 0x2B4 "INTF_LOC_THRESH_MAG5_VAL,"
hexmask.long.tbyte 0x2B4 0.--23. 1. "intf_loc_thresh_mag5_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =5"
line.long 0x2B8 "INTF_LOC_THRESH_MAG6_VAL,"
hexmask.long.tbyte 0x2B8 0.--23. 1. "intf_loc_thresh_mag6_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =6"
line.long 0x2BC "INTF_LOC_THRESH_MAG7_VAL,"
hexmask.long.tbyte 0x2BC 0.--23. 1. "intf_loc_thresh_mag7_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =7"
line.long 0x2C0 "INTF_LOC_THRESH_MAG8_VAL,"
hexmask.long.tbyte 0x2C0 0.--23. 1. "intf_loc_thresh_mag8_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =8"
line.long 0x2C4 "INTF_LOC_THRESH_MAG9_VAL,"
hexmask.long.tbyte 0x2C4 0.--23. 1. "intf_loc_thresh_mag9_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =9"
line.long 0x2C8 "INTF_LOC_THRESH_MAG10_VAL,"
hexmask.long.tbyte 0x2C8 0.--23. 1. "intf_loc_thresh_mag10_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =10"
line.long 0x2CC "INTF_LOC_THRESH_MAG11_VAL,"
hexmask.long.tbyte 0x2CC 0.--23. 1. "intf_loc_thresh_mag11_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =11"
line.long 0x2D0 "INTF_LOC_THRESH_MAGDIFF0_VAL,"
hexmask.long.tbyte 0x2D0 0.--23. 1. "intf_loc_thresh_magdiff0_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =0"
line.long 0x2D4 "INTF_LOC_THRESH_MAGDIFF1_VAL,"
hexmask.long.tbyte 0x2D4 0.--23. 1. "intf_loc_thresh_magdiff1_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =1"
line.long 0x2D8 "INTF_LOC_THRESH_MAGDIFF2_VAL,"
hexmask.long.tbyte 0x2D8 0.--23. 1. "intf_loc_thresh_magdiff2_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =2"
line.long 0x2DC "INTF_LOC_THRESH_MAGDIFF3_VAL,"
hexmask.long.tbyte 0x2DC 0.--23. 1. "intf_loc_thresh_magdiff3_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =3"
line.long 0x2E0 "INTF_LOC_THRESH_MAGDIFF4_VAL,"
hexmask.long.tbyte 0x2E0 0.--23. 1. "intf_loc_thresh_magdiff4_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =4"
line.long 0x2E4 "INTF_LOC_THRESH_MAGDIFF5_VAL,"
hexmask.long.tbyte 0x2E4 0.--23. 1. "intf_loc_thresh_magdiff5_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =5"
line.long 0x2E8 "INTF_LOC_THRESH_MAGDIFF6_VAL,"
hexmask.long.tbyte 0x2E8 0.--23. 1. "intf_loc_thresh_magdiff6_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =6"
line.long 0x2EC "INTF_LOC_THRESH_MAGDIFF7_VAL,"
hexmask.long.tbyte 0x2EC 0.--23. 1. "intf_loc_thresh_magdiff7_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =7"
line.long 0x2F0 "INTF_LOC_THRESH_MAGDIFF8_VAL,"
hexmask.long.tbyte 0x2F0 0.--23. 1. "intf_loc_thresh_magdiff8_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =8"
line.long 0x2F4 "INTF_LOC_THRESH_MAGDIFF9_VAL,"
hexmask.long.tbyte 0x2F4 0.--23. 1. "intf_loc_thresh_magdiff9_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =9"
line.long 0x2F8 "INTF_LOC_THRESH_MAGDIFF10_VAL,"
hexmask.long.tbyte 0x2F8 0.--23. 1. "intf_loc_thresh_magdiff10_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =10"
line.long 0x2FC "INTF_LOC_THRESH_MAGDIFF11_VAL,"
hexmask.long.tbyte 0x2FC 0.--23. 1. "intf_loc_thresh_magdiff11_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =11"
line.long 0x300 "INTF_LOC_COUNT_ALL_CHIRP,"
hexmask.long.word 0x300 0.--11. 1. "intf_loc_count_all_chirp,Number of samples that exceeded the threshold in a chirp"
line.long 0x304 "INTF_LOC_COUNT_ALL_FRAME,"
hexmask.long.tbyte 0x304 0.--19. 1. "intf_loc_count_all_frame,Number of samples that exceeded the threshold in a frame"
line.long 0x308 "INTF_STATS_MAG_ACC_0_LSB,"
line.long 0x30C "INTF_STATS_MAG_ACC_0_MSB,"
bitfld.long 0x30C 0.--3. "intf_stats_mag_acc_0_msb,This read only register contains the accumulator value of interference magnitude(MSB 4 bits) for bcnt = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x310 "INTF_STATS_MAG_ACC_1_LSB,"
line.long 0x314 "INTF_STATS_MAG_ACC_1_MSB,"
bitfld.long 0x314 0.--3. "intf_stats_mag_acc_1_msb,This read only contains the accumulator value of interference magnitude (MSB 4 bits) for bcnt = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x318 "INTF_STATS_MAG_ACC_2_LSB,"
line.long 0x31C "INTF_STATS_MAG_ACC_2_MSB,"
bitfld.long 0x31C 0.--3. "intf_stats_mag_acc_2_msb,This read only register contains the accumulator value of interference magnitude (MSB 4 bits) for bcnt = 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x320 "INTF_STATS_MAG_ACC_3_LSB,"
line.long 0x324 "INTF_STATS_MAG_ACC_3_MSB,"
bitfld.long 0x324 0.--3. "intf_stats_mag_acc_3_msb,This read only register contains the accumulator value of the interference magnitude(for MSB 4 bits) for bcnt = 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x328 "INTF_STATS_MAG_ACC_4_LSB,"
line.long 0x32C "INTF_STATS_MAG_ACC_4_MSB,"
bitfld.long 0x32C 0.--3. "intf_stats_mag_acc_4_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x330 "INTF_STATS_MAG_ACC_5_LSB,"
line.long 0x334 "INTF_STATS_MAG_ACC_5_MSB,"
bitfld.long 0x334 0.--3. "intf_stats_mag_acc_5_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x338 "INTF_STATS_MAG_ACC_6_LSB,"
line.long 0x33C "INTF_STATS_MAG_ACC_6_MSB,"
bitfld.long 0x33C 0.--3. "intf_stats_mag_acc_6_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x340 "INTF_STATS_MAG_ACC_7_LSB,"
line.long 0x344 "INTF_STATS_MAG_ACC_7_MSB,"
bitfld.long 0x344 0.--3. "intf_stats_mag_acc_7_msb,This read only register contains the accumulator value of the interference magnitude (MSB4 bits)for bcnt = 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x348 "INTF_STATS_MAG_ACC_8_LSB,"
line.long 0x34C "INTF_STATS_MAG_ACC_8_MSB,"
bitfld.long 0x34C 0.--3. "intf_stats_mag_acc_8_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x350 "INTF_STATS_MAG_ACC_9_LSB,"
line.long 0x354 "INTF_STATS_MAG_ACC_9_MSB,"
bitfld.long 0x354 0.--3. "intf_stats_mag_acc_9_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x358 "INTF_STATS_MAG_ACC_10_LSB,"
line.long 0x35C "INTF_STATS_MAG_ACC_10_MSB,"
bitfld.long 0x35C 0.--3. "intf_stats_mag_acc_10_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x360 "INTF_STATS_MAG_ACC_11_LSB,"
line.long 0x364 "INTF_STATS_MAG_ACC_11_MSB,"
bitfld.long 0x364 0.--3. "intf_stats_mag_acc_11_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x368 "INTF_STATS_MAGDIFF_ACC_0_LSB,"
line.long 0x36C "INTF_STATS_MAGDIFF_ACC_0_MSB,"
bitfld.long 0x36C 0.--3. "intf_stats_magdiff_acc_0_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x370 "INTF_STATS_MAGDIFF_ACC_1_LSB,"
line.long 0x374 "INTF_STATS_MAGDIFF_ACC_1_MSB,"
bitfld.long 0x374 0.--3. "intf_stats_magdiff_acc_1_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x378 "INTF_STATS_MAGDIFF_ACC_2_LSB,"
line.long 0x37C "INTF_STATS_MAGDIFF_ACC_2_MSB,"
bitfld.long 0x37C 0.--3. "intf_stats_magdiff_acc_2_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x380 "INTF_STATS_MAGDIFF_ACC_3_LSB,"
line.long 0x384 "INTF_STATS_MAGDIFF_ACC_3_MSB,"
bitfld.long 0x384 0.--3. "intf_stats_magdiff_acc_3_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x388 "INTF_STATS_MAGDIFF_ACC_4_LSB,"
line.long 0x38C "INTF_STATS_MAGDIFF_ACC_4_MSB,"
bitfld.long 0x38C 0.--3. "intf_stats_magdiff_acc_4_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x390 "INTF_STATS_MAGDIFF_ACC_5_LSB,"
line.long 0x394 "INTF_STATS_MAGDIFF_ACC_5_MSB,"
bitfld.long 0x394 0.--3. "intf_stats_magdiff_acc_5_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x398 "INTF_STATS_MAGDIFF_ACC_6_LSB,"
line.long 0x39C "INTF_STATS_MAGDIFF_ACC_6_MSB,"
bitfld.long 0x39C 0.--3. "intf_stats_magdiff_acc_6_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A0 "INTF_STATS_MAGDIFF_ACC_7_LSB,"
line.long 0x3A4 "INTF_STATS_MAGDIFF_ACC_7_MSB,"
bitfld.long 0x3A4 0.--3. "intf_stats_magdiff_acc_7_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A8 "INTF_STATS_MAGDIFF_ACC_8_LSB,"
line.long 0x3AC "INTF_STATS_MAGDIFF_ACC_8_MSB,"
bitfld.long 0x3AC 0.--3. "intf_stats_magdiff_acc_8_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B0 "INTF_STATS_MAGDIFF_ACC_9_LSB,"
line.long 0x3B4 "INTF_STATS_MAGDIFF_ACC_9_MSB,"
bitfld.long 0x3B4 0.--3. "intf_stats_magdiff_acc_9_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B8 "INTF_STATS_MAGDIFF_ACC_10_LSB,"
line.long 0x3BC "INTF_STATS_MAGDIFF_ACC_10_MSB,"
bitfld.long 0x3BC 0.--3. "intf_stats_magdiff_acc_10_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C0 "INTF_STATS_MAGDIFF_ACC_11_LSB,"
line.long 0x3C4 "INTF_STATS_MAGDIFF_ACC_11_MSB,"
bitfld.long 0x3C4 0.--3. "intf_stats_magdiff_acc_11_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C8 "INTF_LOC_THRESH_MAG0_SW,"
hexmask.long.tbyte 0x3C8 0.--23. 1. "intf_loc_thresh_mag0_sw,SW programmed interface threshold magnitude for bcnt=0"
line.long 0x3CC "INTF_LOC_THRESH_MAG1_SW,"
hexmask.long.tbyte 0x3CC 0.--23. 1. "intf_loc_thresh_mag1_sw,SW programmed interface threshold magnitude for bcnt=1"
line.long 0x3D0 "INTF_LOC_THRESH_MAG2_SW,"
hexmask.long.tbyte 0x3D0 0.--23. 1. "intf_loc_thresh_mag2_sw,SW programmed interface threshold magnitude for bcnt=2"
line.long 0x3D4 "INTF_LOC_THRESH_MAG3_SW,"
hexmask.long.tbyte 0x3D4 0.--23. 1. "intf_loc_thresh_mag3_sw,SW programmed interface threshold magnitude for bcnt=3"
line.long 0x3D8 "INTF_LOC_THRESH_MAG4_SW,"
hexmask.long.tbyte 0x3D8 0.--23. 1. "intf_loc_thresh_mag4_sw,SW programmed interface threshold magnitude for bcnt=4"
line.long 0x3DC "INTF_LOC_THRESH_MAG5_SW,"
hexmask.long.tbyte 0x3DC 0.--23. 1. "intf_loc_thresh_mag5_sw,SW programmed interface threshold magnitude for bcnt=5"
line.long 0x3E0 "INTF_LOC_THRESH_MAG6_SW,"
hexmask.long.tbyte 0x3E0 0.--23. 1. "intf_loc_thresh_mag6_sw,SW programmed interface threshold magnitude for bcnt=6"
line.long 0x3E4 "INTF_LOC_THRESH_MAG7_SW,"
hexmask.long.tbyte 0x3E4 0.--23. 1. "intf_loc_thresh_mag7_sw,SW programmed interface threshold magnitude for bcnt=7"
line.long 0x3E8 "INTF_LOC_THRESH_MAG8_SW,"
hexmask.long.tbyte 0x3E8 0.--23. 1. "intf_loc_thresh_mag8_sw,SW programmed interface threshold magnitude for bcnt=8"
line.long 0x3EC "INTF_LOC_THRESH_MAG9_SW,"
hexmask.long.tbyte 0x3EC 0.--23. 1. "intf_loc_thresh_mag9_sw,SW programmed interface threshold magnitude for bcnt=9"
line.long 0x3F0 "INTF_LOC_THRESH_MAG10_SW,"
hexmask.long.tbyte 0x3F0 0.--23. 1. "intf_loc_thresh_mag10_sw,SW programmed interface threshold magnitude for bcnt=10"
line.long 0x3F4 "INTF_LOC_THRESH_MAG11_SW,"
hexmask.long.tbyte 0x3F4 0.--23. 1. "intf_loc_thresh_mag11_sw,SW programmed interface threshold magnitude for bcnt=11"
line.long 0x3F8 "INTF_LOC_THRESH_MAGDIFF0_SW,"
hexmask.long.tbyte 0x3F8 0.--23. 1. "intf_loc_thresh_magdiff0_sw,SW programmed interface threshold magnitude difference for bcnt=0"
line.long 0x3FC "INTF_LOC_THRESH_MAGDIFF1_SW,"
hexmask.long.tbyte 0x3FC 0.--23. 1. "intf_loc_thresh_magdiff1_sw,SW programmed interface threshold magnitude difference for bcnt=1"
line.long 0x400 "INTF_LOC_THRESH_MAGDIFF2_SW,"
hexmask.long.tbyte 0x400 0.--23. 1. "intf_loc_thresh_magdiff2_sw,SW programmed interface threshold magnitude difference for bcnt=2"
line.long 0x404 "INTF_LOC_THRESH_MAGDIFF3_SW,"
hexmask.long.tbyte 0x404 0.--23. 1. "intf_loc_thresh_magdiff3_sw,SW programmed interface threshold magnitude difference for bcnt=3"
line.long 0x408 "INTF_LOC_THRESH_MAGDIFF4_SW,"
hexmask.long.tbyte 0x408 0.--23. 1. "intf_loc_thresh_magdiff4_sw,SW programmed interface threshold magnitude difference for bcnt=4"
line.long 0x40C "INTF_LOC_THRESH_MAGDIFF5_SW,"
hexmask.long.tbyte 0x40C 0.--23. 1. "intf_loc_thresh_magdiff5_sw,SW programmed interface threshold magnitude difference for bcnt=5"
line.long 0x410 "INTF_LOC_THRESH_MAGDIFF6_SW,"
hexmask.long.tbyte 0x410 0.--23. 1. "intf_loc_thresh_magdiff6_sw,SW programmed interface threshold magnitude difference for bcnt=6"
line.long 0x414 "INTF_LOC_THRESH_MAGDIFF7_SW,"
hexmask.long.tbyte 0x414 0.--23. 1. "intf_loc_thresh_magdiff7_sw,SW programmed interface threshold magnitude difference for bcnt=7"
line.long 0x418 "INTF_LOC_THRESH_MAGDIFF8_SW,"
hexmask.long.tbyte 0x418 0.--23. 1. "intf_loc_thresh_magdiff8_sw,SW programmed interface threshold magnitude difference for bcnt=8"
line.long 0x41C "INTF_LOC_THRESH_MAGDIFF9_SW,"
hexmask.long.tbyte 0x41C 0.--23. 1. "intf_loc_thresh_magdiff9_sw,SW programmed interface threshold magnitude difference for bcnt=9"
line.long 0x420 "INTF_LOC_THRESH_MAGDIFF10_SW,"
hexmask.long.tbyte 0x420 0.--23. 1. "intf_loc_thresh_magdiff10_sw,SW programmed interface threshold magnitude difference for bcnt=10"
line.long 0x424 "INTF_LOC_THRESH_MAGDIFF11_SW,"
hexmask.long.tbyte 0x424 0.--23. 1. "intf_loc_thresh_magdiff11_sw,SW programmed interface threshold magnitude difference for bcnt=11"
line.long 0x428 "INTF_STATS_ACC_CLIP_STATUS,"
hexmask.long.word 0x428 16.--27. 1. "intf_stats_magdiff_accumulator_clip_status,Interference magnitue difference accumulator Clip status"
newline
hexmask.long.word 0x428 0.--11. 1. "intf_stats_mag_accumulator_clip_status,Interference magnitue accumulator Clip status"
line.long 0x42C "INTF_STATS_THRESH_CLIP_STATUS,"
hexmask.long.word 0x42C 16.--27. 1. "intf_stats_thresh_magdiff_clip_status,Interference magnitude difference threshold Clip status"
newline
hexmask.long.word 0x42C 0.--11. 1. "intf_stats_thresh_mag_clip_status,Interference magnitude threshold Clip status"
line.long 0x430 "INTF_MITG_WINDOW_PARAM_0,"
bitfld.long 0x430 0.--4. "intf_mitg_window_param_0,This is a programmable array of window parameters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x434 "INTF_MITG_WINDOW_PARAM_1,"
bitfld.long 0x434 0.--4. "intf_mitg_window_param_1,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x438 "INTF_MITG_WINDOW_PARAM_2,"
bitfld.long 0x438 0.--4. "intf_mitg_window_param_2,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x43C "INTF_MITG_WINDOW_PARAM_3,"
bitfld.long 0x43C 0.--4. "intf_mitg_window_param_3,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x440 "INTF_MITG_WINDOW_PARAM_4,"
bitfld.long 0x440 0.--4. "intf_mitg_window_param_4,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x444 "INTF_STATS_SUM_MAG_VAL,"
hexmask.long.tbyte 0x444 0.--23. 1. "intf_stats_sum_mag_val,Indicates the sum of mag values ; Only Configured BCNT mag values are added"
line.long 0x448 "INTF_STATS_SUM_MAG_VAL_CLIP_STATUS,"
bitfld.long 0x448 0. "intf_stats_sum_mag_val_clip_status,Indicates the clip status of sum of mag values" "0,1"
line.long 0x44C "INTF_STATS_SUM_MAGDIFF_VAL,"
hexmask.long.tbyte 0x44C 0.--23. 1. "intf_stats_sum_magdiff_val,Indicates the sum of magdiff values ; Only Configured BCNT magdiff values are added"
line.long 0x450 "INTF_STATS_SUM_MAGDIFF_VAL_CLIP_STATUS,"
bitfld.long 0x450 0. "intf_stats_sum_magdiff_val_clip_status,indicates the clip status of sum of magdiff values" "0,1"
line.long 0x454 "INTERF_RESERVED_5,"
group.long 0x4B8++0x1BB
line.long 0x00 "TWID_INCR_DELTA_FRAC,"
hexmask.long.word 0x00 0.--9. 1. "twid_incr_delta_frac,Used in complex multiplier mode 10 Delta Fractional frequency increment per param-set looping Instantaneous frequency is (TWIDINCR << 10) +TWID_INCR_DELTA_ FRAC*c c is current execution count of the parameter set"
line.long 0x04 "RECWIN_RESET_SW,"
bitfld.long 0x04 0. "recwin_reset_sw,This resets the param set counter / execution counter used in Complex multiplier mode 8" "0,1"
line.long 0x08 "TWID_INCR_DELTA_FRAC_RESET_SW,"
bitfld.long 0x08 0. "twid_incr_delta_frac_reset_sw,This resets the param set counter used in Complex multiplier mode 10" "0,1"
line.long 0x0C "TWID_INCR_DELTA_FRAC_CLIP_STATUS,"
bitfld.long 0x0C 0. "twid_incr_delta_frac_clip_status,Indicates the clip status for TWID_INCR_DELTA_FRAC accumulator" "0,1"
line.long 0x10 "RECWIN_INIT_KVAL,"
hexmask.long.word 0x10 0.--11. 1. "recwin_init_kval,Indicates the initialization value of execution counter in recursive window mode"
line.long 0x14 "CMULT_RESERVED_2,"
line.long 0x18 "CHAN_COMB_SIZE,"
hexmask.long.byte 0x18 0.--7. 1. "chan_comb_size,Number of samples after combination"
line.long 0x1C "CHAN_COMB_VEC_0,"
line.long 0x20 "CHAN_COMB_VEC_1,"
line.long 0x24 "CHAN_COMB_VEC_2,"
line.long 0x28 "CHAN_COMB_VEC_3,"
line.long 0x2C "CHAN_COMB_VEC_4,"
line.long 0x30 "CHAN_COMB_VEC_5,"
line.long 0x34 "CHAN_COMB_VEC_6,"
line.long 0x38 "CHAN_COMB_VEC_7,"
line.long 0x3C "CHANNEL_COMB_CLIP_STATUS,"
bitfld.long 0x3C 0. "channel_comb_clip_status,Indicates the clip status of the channel combination" "0,1"
line.long 0x40 "ZERO_INSERT_NUM,"
hexmask.long.byte 0x40 0.--7. 1. "zero_insert_num,Number of zeros to be inserted in an iteration"
line.long 0x44 "ZERO_INSERT_MASK_0,"
line.long 0x48 "ZERO_INSERT_MASK_1,"
line.long 0x4C "ZERO_INSERT_MASK_2,"
line.long 0x50 "ZERO_INSERT_MASK_3,"
line.long 0x54 "ZERO_INSERT_MASK_4,"
line.long 0x58 "ZERO_INSERT_MASK_5,"
line.long 0x5C "ZERO_INSERT_MASK_6,"
line.long 0x60 "ZERO_INSERT_MASK_7,"
line.long 0x64 "ZERO_INSERT_RESERVED_1,"
line.long 0x68 "ZERO_INSERT_RESERVED_2,"
line.long 0x6C "ZERO_INSERT_RESERVED_3,"
line.long 0x70 "ZERO_INSERT_RESERVED_4,"
line.long 0x74 "LFSR_SEED,"
hexmask.long 0x74 0.--28. 1. "lfsr_seed,Seed for LFSR (random pattern): For twiddle factor dithering there is an LFSR that is used whose seed value is loaded by writing to this 29-bit LFSRSEED register"
line.long 0x78 "LFSR_LOAD,"
bitfld.long 0x78 0. "lfsr_load,Its self clearing bit" "0,1"
line.long 0x7C "DITHER_TWID_EN,"
bitfld.long 0x7C 0. "dither_twid_en,Twiddle factor dithering enable: This register-bit is used to enable and disable dithering of twiddle factors in the FFT" "0,1"
line.long 0x80 "FFT_CLIP,"
hexmask.long.word 0x80 0.--12. 1. "fft_clip,FFT Clip Status (read-only): This is a read-only status register which indicates any saturation/clipping events that have happened in the FFT butterfly stages"
line.long 0x84 "CLR_FFTCLIP,"
bitfld.long 0x84 0. "clr_fftclip,Clear FFT Clip Status register: This register bit when set clears the FFTCLIP register" "0,1"
line.long 0x88 "CLR_CLIP_MISC,"
bitfld.long 0x88 0. "clr_clip_status,This clears the following clip register channel_comb_clip_status dc_acc_clip_status dc_est_clip_status intf_stats_mag_accumulator_clip_status intf_stats_magdiff_accumulator_clip_status intf_stats_thresh_mag_clip_status.." "0,1"
line.long 0x8C "IP_OP_FORMATTER_CLIP_STATUS,"
bitfld.long 0x8C 16. "op_formatter_clip_status,Indicates the output formatter clip status" "0,1"
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bitfld.long 0x8C 0. "ip_formatter_clip_status,Indicates the input formatter clip status" "0,1"
line.long 0x90 "FFT_RESERVED_1,"
line.long 0x94 "FFT_RESERVED_2,"
line.long 0x98 "FFT_RESERVED_3,"
line.long 0x9C "MAX1_VALUE,"
hexmask.long.tbyte 0x9C 0.--23. 1. "max1_value,These registers contain the max value on a per-iteration basis"
line.long 0xA0 "MAX2_VALUE,"
hexmask.long.tbyte 0xA0 0.--23. 1. "max2_value,These registers contain the max value on a per-iteration basis"
line.long 0xA4 "MAX3_VALUE,"
hexmask.long.tbyte 0xA4 0.--23. 1. "max3_value,These registers contain the max value on a per-iteration basis"
line.long 0xA8 "MAX4_VALUE,"
hexmask.long.tbyte 0xA8 0.--23. 1. "max4_value,These registers contain the max value on a per-iteration basis"
line.long 0xAC "MAX1_INDEX,"
hexmask.long.word 0xAC 0.--11. 1. "max1_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xB0 "MAX2_INDEX,"
hexmask.long.word 0xB0 0.--11. 1. "max2_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xB4 "MAX3_INDEX,"
hexmask.long.word 0xB4 0.--11. 1. "max3_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xB8 "MAX4_INDEX,"
hexmask.long.word 0xB8 0.--11. 1. "max4_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xBC "I_SUM1_LSB,"
line.long 0xC0 "I_SUM1_MSB,"
bitfld.long 0xC0 0.--3. "i_sum1_msb,I Sum value 1 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "I_SUM2_LSB,"
line.long 0xC8 "I_SUM2_MSB,"
bitfld.long 0xC8 0.--3. "i_sum2_msb,I Sum value 2 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "I_SUM3_LSB,"
line.long 0xD0 "I_SUM3_MSB,"
bitfld.long 0xD0 0.--3. "i_sum3_msb,I Sum value 3 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "I_SUM4_LSB,"
line.long 0xD8 "I_SUM4_MSB,"
bitfld.long 0xD8 0.--3. "i_sum4_msb,I Sum value 4 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "Q_SUM1_LSB,"
line.long 0xE0 "Q_SUM1_MSB,"
bitfld.long 0xE0 0.--3. "q_sum1_msb,Q Sum value 1 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "Q_SUM2_LSB,"
line.long 0xE8 "Q_SUM2_MSB,"
bitfld.long 0xE8 0.--3. "q_sum2_msb,Q Sum value 2 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "Q_SUM3_LSB,"
line.long 0xF0 "Q_SUM3_MSB,"
bitfld.long 0xF0 0.--3. "q_sum3_msb,Q Sum value 3 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "Q_SUM4_LSB,"
line.long 0xF8 "Q_SUM4_MSB,"
bitfld.long 0xF8 0.--3. "q_sum4_msb,Q Sum value 4 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "FFTSUMDIV,"
bitfld.long 0xFC 0.--4. "fftsumdiv,Right-shifting for Sum statistic: This register specifies the number of bits to right-shift the sum statistic before it is written to destination memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x100 "MAX2D_OFFSET_DIM1,"
hexmask.long.tbyte 0x100 0.--23. 1. "max2d_offset_dim1,Offset to be added to dimension 1 Maxima results"
line.long 0x104 "MAX2D_OFFSET_DIM2,"
hexmask.long.tbyte 0x104 0.--23. 1. "max2d_offset_dim2,Offset to be added to dimension 2 Maxima results"
line.long 0x108 "CDF_CNT_THRESH,"
hexmask.long.word 0x108 0.--11. 1. "cdf_cnt_thresh,This register is applicable in CDF_CNT_THRESH mode of operation"
line.long 0x10C "STATS_RESERVED_1,"
line.long 0x110 "STATS_RESERVED_2,"
line.long 0x114 "STATS_RESERVED_3,"
line.long 0x118 "STATS_RESERVED_4,"
line.long 0x11C "STATS_RESERVED_5,"
line.long 0x120 "CFAR_PEAKCNT,"
hexmask.long.word 0x120 0.--11. 1. "cfar_peakcnt,CFAR detected peak count: This is a read-only register that contains the number of detected peaks that are logged in the destination memory when CFAR Engine is configured in Detected Peaks List mode"
line.long 0x124 "CFAR_DET_THR,"
hexmask.long.tbyte 0x124 0.--23. 1. "cfar_det_thr,To be added"
line.long 0x128 "CFAR_TEST_REG,"
hexmask.long.tbyte 0x128 0.--23. 1. "cfar_test_reg,To be added"
line.long 0x12C "CFAR_THRESH,"
hexmask.long.tbyte 0x12C 0.--17. 1. "cfar_thresh,Threshold scale factor: This register is used to specify the threshold scale factor"
line.long 0x130 "CFAR_RESERVED_1,"
line.long 0x134 "CFAR_RESERVED_2,"
line.long 0x138 "CFAR_RESERVED_3,"
line.long 0x13C "CFAR_RESERVED_4,"
line.long 0x140 "CMP_EGE_K0123,"
bitfld.long 0x140 24.--28. "cmp_ege_k3,3th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 16.--20. "cmp_ege_k2,2th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 8.--12. "cmp_ege_k1,1th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 0.--4. "cmp_ege_k0,0th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x144 "CMP_EGE_K4567,"
bitfld.long 0x144 24.--28. "cmp_ege_k7,7th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x144 16.--20. "cmp_ege_k6,6th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x144 8.--12. "cmp_ege_k5,5th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x144 0.--4. "cmp_ege_k4,4th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x148 "MEM_INIT_START,"
bitfld.long 0x148 14. "hist_odd_ram,writing 1'b1 would start the memory initialization for the Histogram memory 2 It s a self clearing bit" "0,1"
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bitfld.long 0x148 13. "hist_even_ram,writing 1'b1 would start the memory initialization for the Histogram memory 1 It s a self clearing bit" "0,1"
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bitfld.long 0x148 12. "per_iter_max_val_ram,writing 1'b1 would start the memory initialization for the 2D MAX per iteration RAM It s a self clearing bit" "0,1"
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bitfld.long 0x148 11. "per_sample_max_val_odd_ram,writing 1'b1 would start the memory initialization for the 2D MAX per sample RAM 2 It s a self clearing bit" "0,1"
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bitfld.long 0x148 10. "per_sample_max_val_even_ram,writing 1'b1 would start the memory initialization for the 2D MAX per sample RAM 1 It s a self clearing bit" "0,1"
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bitfld.long 0x148 9. "window_ram,writing 1'b1 would start the memory initialization for the window memory It s a self clearing bit" "0,1"
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bitfld.long 0x148 8. "param_ram,writing 1'b1 would start the memory initialization for the Param memory It s a self clearing bit" "0,1"
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bitfld.long 0x148 7. "dmem7,writing 1'b1 would start the memory initialization for the DMEM7 It s a self clearing bit" "0,1"
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bitfld.long 0x148 6. "dmem6,writing 1'b1 would start the memory initialization for the DMEM6 It s a self clearing bit" "0,1"
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bitfld.long 0x148 5. "dmem5,writing 1'b1 would start the memory initialization for the DMEM5 It s a self clearing bit" "0,1"
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bitfld.long 0x148 4. "dmem4,writing 1'b1 would start the memory initialization for the DMEM4 It s a self clearing bit" "0,1"
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bitfld.long 0x148 3. "dmem3,writing 1'b1 would start the memory initialization for the DMEM3 It s a self clearing bit" "0,1"
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bitfld.long 0x148 2. "dmem2,writing 1'b1 would start the memory initialization for the DMEM2 It s a self clearing bit" "0,1"
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bitfld.long 0x148 1. "dmem1,writing 1'b1 would start the memory initialization for the DMEM1" "0,1"
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bitfld.long 0x148 0. "dmem0,writing 1'b1 would start the memory initialization for the DMEM0 It s a self clearing bit" "0,1"
line.long 0x14C "MEM_INIT_DONE,"
bitfld.long 0x14C 14. "hist_odd_ram,Will be 1'b1 after cmpletion of memory initialization for hist_odd_ram" "0,1"
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bitfld.long 0x14C 13. "hist_even_ram,Will be 1'b1 after cmpletion of memory initialization for hist_even_ram" "0,1"
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bitfld.long 0x14C 12. "per_iteration_max_val_ram,Will be 1'b1 after cmpletion of memory initialization for per_iteration_max_val_ram" "0,1"
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bitfld.long 0x14C 11. "per_sample_max_val_odd_ram,Will be 1'b1 after cmpletion of memory initialization for per_sample_max_val_odd_ram" "0,1"
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bitfld.long 0x14C 10. "per_sample_max_val_even_ram,Will be 1'b1 after cmpletion of memory initialization for per_sample_max_val_even_ram" "0,1"
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bitfld.long 0x14C 9. "window_ram,Will be 1'b1 after cmpletion of memory initialization for window_ram" "0,1"
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bitfld.long 0x14C 8. "param_ram,Will be 1'b1 after cmpletion of memory initialization for param_ram" "0,1"
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bitfld.long 0x14C 7. "dmem7,Will be 1'b1 after cmpletion of memory initialization for dmem7" "0,1"
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bitfld.long 0x14C 6. "dmem6,Will be 1'b1 after cmpletion of memory initialization for dmem6" "0,1"
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bitfld.long 0x14C 5. "dmem5,Will be 1'b1 after cmpletion of memory initialization for dmem5" "0,1"
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bitfld.long 0x14C 4. "dmem4,Will be 1'b1 after cmpletion of memory initialization for dmem4" "0,1"
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bitfld.long 0x14C 3. "dmem3,Will be 1'b1 after cmpletion of memory initialization for dmem3" "0,1"
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bitfld.long 0x14C 2. "dmem2,Will be 1'b1 after cmpletion of memory initialization for dmem2" "0,1"
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bitfld.long 0x14C 1. "dmem1,Will be 1'b1 after cmpletion of memory initialization for dmem1" "0,1"
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bitfld.long 0x14C 0. "dmem0,Will be 1'b1 after cmpletion of memory initialization for dmem0" "0,1"
line.long 0x150 "MEM_INIT_STATUS,"
bitfld.long 0x150 14. "hist_odd_ram,Will be 1'b1 during memory initialization for hist_odd_ram" "0,1"
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bitfld.long 0x150 13. "hist_even_ram,Will be 1'b1 during memory initialization for hist_even_ram" "0,1"
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bitfld.long 0x150 12. "per_iteration_max_val_ram,Will be 1'b1 during memory initialization for per_iteration_max_val_ram" "0,1"
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bitfld.long 0x150 11. "per_sample_max_val_odd_ram,Will be 1'b1 during memory initialization for per_sample_max_val_odd_ram" "0,1"
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bitfld.long 0x150 10. "per_sample_max_val_even_ram,Will be 1'b1 during memory initialization for per_sample_max_val_even_ram" "0,1"
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bitfld.long 0x150 9. "window_ram,Will be 1'b1 during memory initialization for window_ram" "0,1"
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bitfld.long 0x150 8. "param_ram,Will be 1'b1 during memory initialization for param_ram" "0,1"
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bitfld.long 0x150 7. "dmem7,Will be 1'b1 during memory initialization for dmem7" "0,1"
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bitfld.long 0x150 6. "dmem6,Will be 1'b1 during memory initialization for dmem6" "0,1"
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bitfld.long 0x150 5. "dmem5,Will be 1'b1 during memory initialization for dmem5" "0,1"
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bitfld.long 0x150 4. "dmem4,Will be 1'b1 during memory initialization for dmem4" "0,1"
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bitfld.long 0x150 3. "dmem3,Will be 1'b1 during memory initialization for dmem3" "0,1"
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bitfld.long 0x150 2. "dmem2,Will be 1'b1 during memory initialization for dmem2" "0,1"
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bitfld.long 0x150 1. "dmem1,Will be 1'b1 during memory initialization for dmem1" "0,1"
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bitfld.long 0x150 0. "dmem0,Will be 1'b1 during memory initialization for dmem0" "0,1"
line.long 0x154 "LM_THRESH_VAL,"
hexmask.long.word 0x154 16.--31. 1. "dimc_thresh_val,Threshold value configured for Dimension C"
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hexmask.long.word 0x154 0.--15. 1. "dimb_thresh_val,Threshold value configured for Dimension B"
line.long 0x158 "LM_2DSTATS_BASE_ADDR,"
hexmask.long.word 0x158 16.--27. 1. "base_addr_dimc,Base Address in Stats RAM for the Threshold values corresponding to dimension C"
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hexmask.long.word 0x158 0.--11. 1. "base_addr_dimb,Base Address in Stats RAM for the Threshold values corresponding to dimension B"
line.long 0x15C "HWA_SAFETY_EN,"
bitfld.long 0x15C 3. "cfg_dmem_parity_en,Writing 1'b1 would enable the parity chekcer for the 8 DMEM memories" "0,1"
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bitfld.long 0x15C 2. "cfg_window_ram_parity_en,Writing 1'b1 enables parity for windowing RAM" "0,1"
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bitfld.long 0x15C 1. "cfg_fsm_lockstep_inv_en,Writing 1'b1 will invert the redundant FSM outputs" "0,1"
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bitfld.long 0x15C 0. "cfg_fsm_lockstep_en,Writing 1'b1 would enable the lockstep logic for FSM" "0,1"
line.long 0x160 "HWA_SAFETY_ERR_MASK,"
bitfld.long 0x160 9. "fsm_lockstep," "FSM lockstep error is not masked,FSM lockstep error is masked"
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bitfld.long 0x160 8. "window_ram," "window RAM parity error is not masked,window RAM parity error is masked"
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bitfld.long 0x160 7. "dmem7," "DMEM7 parity error is not masked,DMEM7 parity error is masked"
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bitfld.long 0x160 6. "dmem6," "DMEM6 parity error is not masked,DMEM6 parity error is masked"
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bitfld.long 0x160 5. "dmem5," "DMEM5 parity error is not masked,DMEM5 parity error is masked"
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bitfld.long 0x160 4. "dmem4," "DMEM4 parity error is not masked,DMEM4 parity error is masked"
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bitfld.long 0x160 3. "dmem3," "DMEM3 parity error is not masked,DMEM3 parity error is masked"
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bitfld.long 0x160 2. "dmem2," "DMEM2 parity error is not masked,DMEM2 parity error is masked"
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bitfld.long 0x160 1. "dmem1," "DMEM1 parity error is not masked,DMEM1 parity error is masked"
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bitfld.long 0x160 0. "dmem0," "DMEM0 parity error is not masked,DMEM0 parity error is masked"
line.long 0x164 "HWA_SAFETY_ERR_STATUS,"
bitfld.long 0x164 9. "fsm_lockstep,Indicates the FSM lockstep error (Masked status)" "0,1"
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bitfld.long 0x164 8. "window_ram,Indicates the parity error in window RAM (Masked status)" "0,1"
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bitfld.long 0x164 7. "dmem7,Indicates the parity error in dmem7 (Masked status)" "0,1"
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bitfld.long 0x164 6. "dmem6,Indicates the parity error in dmem6 (Masked status)" "0,1"
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bitfld.long 0x164 5. "dmem5,Indicates the parity error in dmem5 (Masked status)" "0,1"
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bitfld.long 0x164 4. "dmem4,Indicates the parity error in dmem4 (Masked status)" "0,1"
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bitfld.long 0x164 3. "dmem3,Indicates the parity error in dmem3 (Masked status)" "0,1"
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bitfld.long 0x164 2. "dmem2,Indicates the parity error in dmem2 (Masked status)" "0,1"
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bitfld.long 0x164 1. "dmem1,Indicates the parity error in dmem1 (Masked status)" "0,1"
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bitfld.long 0x164 0. "dmem0,Indicates the parity error in dmem0 (Masked status)" "0,1"
line.long 0x168 "HWA_SAFETY_ERR_STATUS_RAW,"
bitfld.long 0x168 9. "fsm_lockstep,Indicates the FSM lockstep error (raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 9" "0,1"
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bitfld.long 0x168 8. "window_ram,Indicates the parity error in window RAM(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 8" "0,1"
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bitfld.long 0x168 7. "dmem7,Indicates the parity error in dmem7(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 7" "0,1"
newline
bitfld.long 0x168 6. "dmem6,Indicates the parity error in dmem6(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 6" "0,1"
newline
bitfld.long 0x168 5. "dmem5,Indicates the parity error in dmem5(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 5" "0,1"
newline
bitfld.long 0x168 4. "dmem4,Indicates the parity error in dmem4(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 4" "0,1"
newline
bitfld.long 0x168 3. "dmem3,Indicates the parity error in dmem3(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 3" "0,1"
newline
bitfld.long 0x168 2. "dmem2,Indicates the parity error in dmem2(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 2" "0,1"
newline
bitfld.long 0x168 1. "dmem1,Indicates the parity error in dmem1(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 1" "0,1"
newline
bitfld.long 0x168 0. "dmem0,Indicates the parity error in dmem0(raw status)" "0,1"
line.long 0x16C "HWA_SAFETY_DMEM0_ERR_ADDR,"
hexmask.long.word 0x16C 0.--9. 1. "dmem0_err_addr,Captures the address where parity error occured for dmem0"
line.long 0x170 "HWA_SAFETY_DMEM1_ERR_ADDR,"
hexmask.long.word 0x170 0.--9. 1. "dmem1_err_addr,Captures the address where parity error occured for dmem1"
line.long 0x174 "HWA_SAFETY_DMEM2_ERR_ADDR,"
hexmask.long.word 0x174 0.--9. 1. "dmem2_err_addr,Captures the address where parity error occured for dmem2"
line.long 0x178 "HWA_SAFETY_DMEM3_ERR_ADDR,"
hexmask.long.word 0x178 0.--9. 1. "dmem3_err_addr,Captures the address where parity error occured for dmem3"
line.long 0x17C "HWA_SAFETY_DMEM4_ERR_ADDR,"
hexmask.long.word 0x17C 0.--9. 1. "dmem4_err_addr,Captures the address where parity error occured for dmem4"
line.long 0x180 "HWA_SAFETY_DMEM5_ERR_ADDR,"
hexmask.long.word 0x180 0.--9. 1. "dmem5_err_addr,Captures the address where parity error occured for dmem5"
line.long 0x184 "HWA_SAFETY_DMEM6_ERR_ADDR,"
hexmask.long.word 0x184 0.--9. 1. "dmem6_err_addr,Captures the address where parity error occured for dmem6"
line.long 0x188 "HWA_SAFETY_DMEM7_ERR_ADDR,"
hexmask.long.word 0x188 0.--9. 1. "dmem7_err_addr,Captures the address where parity error occured for dmem7"
line.long 0x18C "HWA_SAFETY_WINDOW_RAM_ERR_ADDR,"
hexmask.long.word 0x18C 0.--10. 1. "window_ram_err_addr,Captures the address where parity error occured for window RAM"
line.long 0x190 "MEM_ACCESS_ERR_STATUS,"
bitfld.long 0x190 7. "dmem7,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem7 at the same time" "0,1"
newline
bitfld.long 0x190 6. "dmem6,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem6 at the same time" "0,1"
newline
bitfld.long 0x190 5. "dmem5,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem5 at the same time" "0,1"
newline
bitfld.long 0x190 4. "dmem4,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem4 at the same time" "0,1"
newline
bitfld.long 0x190 3. "dmem3,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem3 at the same time" "0,1"
newline
bitfld.long 0x190 2. "dmem2,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem2 at the same time" "0,1"
newline
bitfld.long 0x190 1. "dmem1,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem1 at the same time" "0,1"
newline
bitfld.long 0x190 0. "dmem0,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem0 at the same time" "0,1"
line.long 0x194 "LOOP_CNT,"
hexmask.long.word 0x194 16.--27. 1. "loop_cnt_alt,Loop count for alternate thread"
newline
hexmask.long.word 0x194 0.--11. 1. "loop_cnt,Loop count"
line.long 0x198 "PARAMADDR,"
bitfld.long 0x198 0.--5. "paramaddr,Index of the current parameter set being executed from PARAM RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x19C "PARAMADDR_CPUINTR0,"
bitfld.long 0x19C 0.--5. "paramaddr,Index of the parameter set when PARAM_DONE_INTR0 is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1A0 "PARAMADDR_CPUINTR1,"
bitfld.long 0x1A0 0.--5. "paramaddr,Index of the parameter set when PARAM_DONE_INTR1 is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1A4 "FSM_STATE,"
bitfld.long 0x1A4 0.--2. "fsm_state,Current state of the state machine" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "SINGLE_STEP_EN,"
bitfld.long 0x1A8 0. "single_step_en,Single step enable" "0,1"
line.long 0x1AC "SINGLE_STEP_TRIG,"
bitfld.long 0x1AC 0. "single_step_trig,This is a self clearing sofware trigger bit" "0,1"
line.long 0x1B0 "HWA_DMEM_A_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "HWA_DMEM_A_BUS_SAFETY_FI,"
hexmask.long.byte 0x1B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1B8 "HWA_DMEM_A_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x678++0x0F
line.long 0x00 "HWA_DMEM_A_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x04 "HWA_DMEM_B_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x04 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x04 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x08 "HWA_DMEM_B_BUS_SAFETY_FI,"
hexmask.long.byte 0x08 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x08 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x0C "HWA_DMEM_B_BUS_SAFETY_ERR,"
hexmask.long.byte 0x0C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x68C++0x03
line.long 0x00 "HWA_DMEM_B_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "proxy_err,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "prot_err,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "enabled_proxy_err,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "enabled_kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "fault_ns,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "fault_type,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "fault_xid,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "fault_routeid,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "fault_privid,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "fault_clr,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x488)++0x03
line.long 0x00 "QCMULT_SCALE$1,"
hexmask.long.tbyte 0x00 0.--20. 1. "qcmult_scale0,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11 per-iteration based.."
repeat.end
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x458)++0x03
line.long 0x00 "ICMULT_SCALE$1,"
hexmask.long.tbyte 0x00 0.--20. 1. "icmult_scale0,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11 per-iteration based.."
repeat.end
width 0x0B
tree.end
tree "DSS_MCRC (DSS MCRC Module Registers)"
base ad:0x83300000
group.long 0x00++0x03
line.long 0x00 "CRC_CTRL0,Contains sw reset control bit to reset PSA"
rbitfld.long 0x00 31. "NU12,Reserved" "0,1"
rbitfld.long 0x00 30. "NU11,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "NU10,Reserved" "0,1"
rbitfld.long 0x00 27.--28. "NU9,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 25.--26. "NU8,Reserved" "0,1,2,3"
rbitfld.long 0x00 24. "NU7,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "NU6,Reserved" "0,1"
rbitfld.long 0x00 22. "NU5,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "NU4,Reserved" "0,1"
rbitfld.long 0x00 19.--20. "NU3,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 17.--18. "NU2,Reserved" "0,1,2,3"
rbitfld.long 0x00 16. "NU1,Reserved" "0,1"
newline
bitfld.long 0x00 15. "CH2_CRC_SEL2,Refer 'CH2_DW_SEL' field description" "0,1"
bitfld.long 0x00 14. "CH2_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 13. "CH2_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 11.--12. "CH2_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 9.--10. "CH2_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 8. "CH2_PSA_SWREST,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 7. "CH1_CRC_SEL2,Refer 'CH1_DW_SEL' field description" "0,1"
bitfld.long 0x00 6. "CH1_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 5. "CH1_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 3.--4. "CH1_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 1.--2. "CH1_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 0. "CH1_PSA_SWREST,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
group.long 0x08++0x03
line.long 0x00 "CRC_CTRL1,Contains power down control bit"
hexmask.long 0x00 1.--31. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode"
group.long 0x10++0x03
line.long 0x00 "CRC_CTRL2,Contains channel mode. data trace enable control bits"
rbitfld.long 0x00 26.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "NU14,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 18.--23. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 16.--17. "NU13,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 10.--15. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode: 0" "reserved 1,Full-CPU mode,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved2,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable" "Data Trace disable,Data Trace enable"
newline
rbitfld.long 0x00 2.--3. "Reserved1,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode: 0" "reserved 1,Full-CPU mode,?..."
group.long 0x18++0x03
line.long 0x00 "CRC_INTS,Write one to a bit to enable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU22,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU21,Reserved" "0,1"
rbitfld.long 0x00 26. "NU20,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU19,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU18,Reserved" "0,1"
rbitfld.long 0x00 19. "NU17,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU16,Reserved" "0,1"
rbitfld.long 0x00 17. "NU15,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENS,Channel 2 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENS,Channel 1 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
bitfld.long 0x00 1. "CH1_CRCFAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x20++0x03
line.long 0x00 "CRC_INTR,Write one to a bit to disable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU30,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU29,Reserved" "0,1"
rbitfld.long 0x00 26. "NU28,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU27,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU26,Reserved" "0,1"
rbitfld.long 0x00 19. "NU25,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU24,Reserved" "0,1"
rbitfld.long 0x00 17. "NU23,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENR,Channel 2 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
newline
bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENR,Channel 1 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
newline
bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
bitfld.long 0x00 1. "CH1_CRCFAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x28++0x03
line.long 0x00 "CRC_STATUS_REG,Contains interrupt flags for different types of interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU38,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU37,Reserved" "0,1"
rbitfld.long 0x00 26. "NU36,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU35,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU34,Reserved" "0,1"
rbitfld.long 0x00 19. "NU33,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU32,Reserved" "0,1"
rbitfld.long 0x00 17. "NU31,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUT,Channel 2 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 9. "CH2_CRCFAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUT,Channel 1 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
bitfld.long 0x00 1. "CH1_CRCFAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x30++0x03
line.long 0x00 "CRC_INT_OFFSET_REG,Contains the interrupt offset vector address"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "OFSTREG,CRC Interrupt Offset"
rgroup.long 0x38++0x03
line.long 0x00 "CRC_BUSY,Contains the busy flag for each channel"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "NU40,Reserved" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved3,Reserved"
bitfld.long 0x00 16. "NU39,Reserved" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved2,Reserved"
bitfld.long 0x00 8. "Ch2_BUSY,Ch2_BUSY" "0,1"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "CH1_BUSY,CH1_BUSY" "0,1"
group.long 0x40++0x13
line.long 0x00 "CRC_PCOUNT_REG1,Channel 1 preload register for the pattern count"
hexmask.long.word 0x00 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register"
line.long 0x04 "CRC_SCOUNT_REG1,Channel 1 preload register for the sector count"
hexmask.long.word 0x04 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register"
line.long 0x08 "CRC_CURSEC_REG1,Channel 1 current sector register contains the sector number which causes CRC failure"
hexmask.long.word 0x08 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register"
line.long 0x0C "CRC_WDTOPLD1,Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register"
line.long 0x10 "CRC_BCTOPLD1,Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x10 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Regis- ter"
group.long 0x60++0x33
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA signature low register"
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA signature high register"
line.long 0x08 "CRC_REGL1,Channel 1 CRC value low register"
line.long 0x0C "CRC_REGH1,Channel 1 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL1,Channel 1 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH1,Channel 1 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL1,Channel 1 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH1,Channel 1 un-compressed raw data high register"
line.long 0x20 "CRC_PCOUNT_REG2,Channel 2 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,Channel 2 Pattern Counter Preload Register"
line.long 0x24 "CRC_SCOUNT_REG2,Channel 2 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register"
line.long 0x28 "CRC_CURSEC_REG2,Channel 2 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register"
line.long 0x2C "CRC_WDTOPLD2,Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register"
line.long 0x30 "CRC_BCTOPLD2,Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Regis- ter"
group.long 0xA0++0x33
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA signature low register"
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA signature high register"
line.long 0x08 "CRC_REGL2,Channel 2 CRC value low register"
line.long 0x0C "CRC_REGH2,Channel 2 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL2,Channel 2 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH2,Channel 2 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL2,Channel 2 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH2,Channel 2 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG3,Channel 3 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU41,Reserved"
line.long 0x24 "CRC_SCOUNT_REG3,Channel 3 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU42,Reserved"
line.long 0x28 "CRC_CURSEC_REG3,Channel 3 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU43,Reserved"
line.long 0x2C "CRC_WDTOPLD3,Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU44,Reserved"
line.long 0x30 "CRC_BCTOPLD3,Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU45,Reserved"
rgroup.long 0xE0++0x33
line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA signature low register"
line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA signature high register"
line.long 0x08 "CRC_REGL3,Channel 3 CRC value low register"
line.long 0x0C "CRC_REGH3,Channel 3 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL3,Channel 3 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH3,Channel 3 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL3,Channel 3 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH3,Channel 3 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG4,Channel 4 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU54,Reserved"
line.long 0x24 "CRC_SCOUNT_REG4,Channel 4 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU55,Reserved"
line.long 0x28 "CRC_CURSEC_REG4,Channel 4 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU56,Reserved"
line.long 0x2C "CRC_WDTOPLD4,Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU57,Reserved"
line.long 0x30 "CRC_BCTOPLD4,Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU58,Reserved"
rgroup.long 0x120++0x27
line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA signature low register"
line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA signature high register"
line.long 0x08 "CRC_REGL4,Channel 4 CRC value low register"
line.long 0x0C "CRC_REGH4,Channel 4 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL4,Channel 4 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH4,Channel 4 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL4,Channel 4 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH4,Channel 4 un-compressed raw data high Register"
line.long 0x20 "MCRC_BUS_SEL,Disables either or all tracing of data buses"
hexmask.long 0x20 3.--31. 1. "NU67,Reserved"
bitfld.long 0x20 2. "MEn,MEn" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled"
newline
bitfld.long 0x20 1. "DTCMEn,DTCMEn" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.."
bitfld.long 0x20 0. "ITCMEn,ITCMEn" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled"
line.long 0x24 "MCRC_RESERVED,0x144 to 0x1FF is reserved area"
width 0x0B
tree.end
tree "DSS_PCR (DSS PCR Module Registers)"
base ad:0x6F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "DSS_RCM (DSS RCM Module Registers)"
base ad:0x6000000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x27
line.long 0x00 "DSP_PD_CTRL,"
bitfld.long 0x00 4. "proc_halt,Controls the unhalting on the processor during the power-up sequence" "The processor is unhalted at the end of the..,The DSP is kept in halt state at the end of the.."
newline
bitfld.long 0x00 0. "interrupt_mask,Masks interrupts to the DSP" "Send the interrupts to the DSP after power on,Mask interrupts to the DSP before powering off.."
line.long 0x04 "DSP_PD_TRIGGER_WAKUP,"
bitfld.long 0x04 0. "wakeup_trigger,Write pulse bit field: Trigger Power Up of the DSP" "0,1"
line.long 0x08 "DSP_PD_TRIGGER_SLEEP,"
bitfld.long 0x08 0. "sleep_trigger,Write pulse bit field: Trigger Power Down of the DSP" "0,1"
line.long 0x0C "DSP_PD_STATUS,"
bitfld.long 0x0C 8. "pwrsm_dbg_ovrd,Status bit indicating if there is an override for the DSP from Debug SubSystem" "No override from DebugSS,Override from DebugSS"
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bitfld.long 0x0C 4.--5. "pd_status,Power Mode status of DSP" "Powered OFF,Transitioning from OFF to ON..,Transitioning from ON to OFF..,Powered ON"
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bitfld.long 0x0C 0. "proc_halted,Processor is halted" "0,1"
line.long 0x10 "DSP_PD_CTRL_MISC0,"
bitfld.long 0x10 24.--29. "pwrsm_grst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of GRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 18.--23. "pwrsm_porrst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of POR during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 12.--17. "pwrsm_lrst_assertcnt,TI Internal Feature No of cycles to wait after assertion of LRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 6.--11. "pwrsm_grst_assertcnt,TI Internal Feature No of cycles to wait after assertion of GRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 0.--5. "pwrsm_porrst_assertcnt,TI Internal Feature No of cycles to wait after assertion of POR during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DSP_PD_CTRL_MISC1,"
bitfld.long 0x14 24.--26. "iso_sync_bypass,HW RnD reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20.--22. "rst_sync_bypass,HW RnD reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 18. "pwrsm_lresetout_mask,TI Internal Feature" "0,1"
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bitfld.long 0x14 12.--17. "pwrsm_isoen_assertcnt,TI Internal Feature No of cycles to wait after assertion of ISO_ENABLE during GEM power-down sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 6.--11. "pwrsm_clkstop_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of GEM_CLK_STOP_REQ during GEM Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 0.--5. "pwrsm_lrst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of LRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DSP_PD_STATUS_MISC0,"
bitfld.long 0x18 17. "pwrsm_lrstout,TI Internal Feature Lreset output indication from GEM" "0,1"
newline
bitfld.long 0x18 16. "pwrsm_c66_clkstop_ack,TI Internal Feature Clock stop request ack from GEM" "0,1"
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bitfld.long 0x18 15. "pwrsm_sdma_async2scr_clkstop_ack,TI Internal Feature SDMA slave disable Done from clock stop ack from the master port of the async bridge present in the SDMA port" "0,1"
newline
bitfld.long 0x18 14. "pwrsm_sdma_async2rcm_clkstop_req,TI Internal Feature SDMA Slave disable Ack from Interconnect" "0,1"
newline
bitfld.long 0x18 13. "pwrsm_sdma_scr2async_clkstop_req,TI Internal Feature Clock Stop request from SCR to SDMA Async Bridge" "0,1"
newline
bitfld.long 0x18 12. "pwrsm_mem_agoodout,TI Internal Feature Memory AGOOD Output from GEM (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 11. "pwrsm_mem_aonout,TI Internal Feature Memory AON Output from GEM (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 10. "pwrsm_mem_pgoodout,TI Internal Feature Memory PGOOD Output from DSP (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 9. "pwrsm_mem_ponout,TI Internal Feature Memory PON Output from DSP (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 8. "pwrsm_pgoodout,TI Internal Feature Logic PGOOD Output from DSP (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 7. "pwrsm_ponout,TI Internal Feature Logic PON Output from DSP (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 0.--5. "state,This is the internal state of the DSP power State machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DSP_PD_WAKEUP_MASK0,"
line.long 0x20 "DSP_PD_WAKEUP_MASK1,"
line.long 0x24 "DSP_PD_WAKEUP_MASK2,"
group.long 0x48++0x10B
line.long 0x00 "DSP_PD_WAKEUP_STATUS0_CLR,"
line.long 0x04 "DSP_PD_WAKEUP_STATUS1_CLR,"
line.long 0x08 "DSP_PD_WAKEUP_STATUS2_CLR,"
line.long 0x0C "DSP_PD_MISSED_EVENT_MASK0,"
line.long 0x10 "DSP_PD_MISSED_EVENT_MASK1,"
line.long 0x14 "DSP_PD_MISSED_EVENT_MASK2,"
line.long 0x18 "DSP_PD_MISSED_EVENT_STATUS0,"
line.long 0x1C "DSP_PD_MISSED_EVENT_STATUS1,"
line.long 0x20 "DSP_PD_MISSED_EVENT_STATUS2,"
line.long 0x24 "DSP_RST_CAUSE,"
abitfld.long 0x24 16.--23. "por_cause,DSP POR reset Bitwise Indication : Bit" "0x00=Por Reset Bit,0x01=Sub system Reset from TOPRCM Bit,0x02=Reset from DSS_RCM,0x03=Reset from Power FSM Bit,0x04=Reset from STC FSM"
newline
abitfld.long 0x24 8.--15. "grst_cause,DSP Greset Bitwise Indication : Bit" "0x00=Por Reset Bit,0x01=Sub system Reset from TOPRCM Bit,0x02=Reset from DSS_RCM,0x03=Reset from Power FSM Bit,0x04=Reset from STC FSM"
newline
abitfld.long 0x24 0.--7. "lrst_cause,DSP Lreset Bitwise Indication : Bit" "0x00=Por Reset Bit,0x01=Sub system Reset from TOPRCM Bit,0x02=Reset from DSS_RCM,0x03=Reset from Debugss Bit,0x04=Reset from Power FSM Bit,0x05=Reset from STC FSM"
line.long 0x28 "DSP_RST_CAUSE_CLR,"
bitfld.long 0x28 0. "clear,Write pulse bit field: Write 0x1 to clear the reset cause register for any previous resets : Its a wspecial access type write to this field will generate a pulse" "0,1"
line.long 0x2C "DSP_STC_PBIST_CTRL,"
bitfld.long 0x2C 16.--21. "pbist_tmode_vlct_assertcnt,No of clocks (in terms of 200 MHz DSPSS Bus clock) after asserting GEM TMODE VLCT signal before proceeding to the next state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x2C 10.--15. "pbist_tmode_vlct_deassertcnt,No of clocks (in terms of 200 MHz DSPSS Bus clock) after De-asserting GEM TMODE VLCT signal before proceeding to the next state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x2C 6.--9. "pbist_selftest_key,[4:1] DSP PBIST SELFTEST KEY = 4'b1010" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x2C 5. "stc_b2b_en,Enables back to Back STC.Needs to be set to 1 for self test" "0,1"
newline
bitfld.long 0x2C 4. "stc_clk_stp_ack_mask,Mask bit for ignoring the clock stop ack from GEM" "0,1"
newline
bitfld.long 0x2C 3. "proc_halt,Configuration to halt the state machine before the final de-assertion of LRST to enable program download" "0,1"
newline
bitfld.long 0x2C 2. "stc_boot_en,Enable GEM STC during GEM power UP" "0,1"
newline
bitfld.long 0x2C 0.--1. "mode_enable,Enable for PBIST and STC" "0,1,2,3"
line.long 0x30 "DSP_STC_PBIST_STATUS,"
bitfld.long 0x30 2.--7. "stc_pbist_sm_status,PBIST status from GEM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 0.--1. "pbist_status,Current state of STC PBIST state machine" "0,1,2,3"
line.long 0x34 "DSP_STC_PBIST_CTRL_MISC0,"
hexmask.long.word 0x34 16.--31. 1. "byp_value,DSP PBIST STC misc Control"
newline
hexmask.long.word 0x34 0.--15. 1. "byp_en,DSP PBIST STC misc Control"
line.long 0x38 "DSP_STC_PBIST_CTRL_MISC1,"
bitfld.long 0x38 4.--9. "sm_ovr_val,TI Internal Register.Reserved for HW RnD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x38 3. "sm_ovr_en,TI Internal Register.Reserved for HW RnD" "0,1"
line.long 0x3C "DSP_STC_PBIST_START,"
bitfld.long 0x3C 0. "sm_trig,Write pulse bit field: Trigger pulse for the STC PBIST state machine" "0,1"
line.long 0x40 "DSP_STC_PBIST_STATUS_CLR,"
bitfld.long 0x40 0. "clear,Write pulse bit field: Clear bit for PBIST Status : Its a wspecial access type write to this field will generate a pulse" "0,1"
line.long 0x44 "DSS_DSP_CLK_SRC_SEL,"
hexmask.long.word 0x44 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS DSP"
line.long 0x48 "DSS_HWA_CLK_SRC_SEL,"
bitfld.long 0x48 0.--2. "clksrcsel,Select line for selecting source clock for DSS HWA" "TOPRCM_CR5_CLK,?,?,?,?,?,?,TOPRCM_SYS_CLK"
line.long 0x4C "DSS_RTIA_CLK_SRC_SEL,"
hexmask.long.word 0x4C 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS_RTIA"
line.long 0x50 "DSS_RTIB_CLK_SRC_SEL,"
hexmask.long.word 0x50 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS RTIB"
line.long 0x54 "DSS_WDT_CLK_SRC_SEL,"
hexmask.long.word 0x54 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS Watchdog"
line.long 0x58 "DSS_SCIA_CLK_SRC_SEL,"
hexmask.long.word 0x58 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS SCIA"
line.long 0x5C "DSS_DSP_CLK_DIV_VAL,"
hexmask.long.word 0x5C 0.--11. 1. "clkdiv,Divider value for DSS DSP selected clock"
line.long 0x60 "DSS_RTIA_CLK_DIV_VAL,"
hexmask.long.word 0x60 0.--11. 1. "clkdiv,Divider value for DSS RTIA selected clock"
line.long 0x64 "DSS_RTIB_CLK_DIV_VAL,"
hexmask.long.word 0x64 0.--11. 1. "clkdiv,Divider value for DSS RTIB selected clock"
line.long 0x68 "DSS_WDT_CLK_DIV_VAL,"
hexmask.long.word 0x68 0.--11. 1. "clkdiv,Divider value for DSS Watchdog selected clock"
line.long 0x6C "DSS_SCIA_CLK_DIV_VAL,"
hexmask.long.word 0x6C 0.--11. 1. "clkdiv,Divider value for DSS SCIA selected clock"
line.long 0x70 "DSS_DSP_CLK_GATE,"
bitfld.long 0x70 0.--2. "gated,Clock gatring config for DSS DSP" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x74 "DSS_HWA_CLK_GATE,"
bitfld.long 0x74 0.--2. "gated,Clock gatring config for DSS HWA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x78 "DSS_RTIA_CLK_GATE,"
bitfld.long 0x78 0.--2. "gated,Clock gatring config for DSS RTA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x7C "DSS_RTIB_CLK_GATE,"
bitfld.long 0x7C 0.--2. "gated,Clock gatring config for DSS RTIB Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x80 "DSS_WDT_CLK_GATE,"
bitfld.long 0x80 0.--2. "gated,Clock gatring config for DSS Watchdog Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x84 "DSS_SCIA_CLK_GATE,"
bitfld.long 0x84 0.--2. "gated,Clock gatring config for DSS SCIA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x88 "DSS_CBUFF_CLK_GATE,"
bitfld.long 0x88 0.--2. "gated,Not Supported" "0,1,2,3,4,5,6,7"
line.long 0x8C "DSS_DSP_CLK_STATUS,"
hexmask.long.byte 0x8C 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS DSP Clock"
newline
hexmask.long.byte 0x8C 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS DSP Clock"
line.long 0x90 "DSS_HWA_CLK_STATUS,"
bitfld.long 0x90 0.--1. "clkinuse,Status shows the source clock slected for DSS HWA Clock" "0,1,2,3"
line.long 0x94 "DSS_RTIA_CLK_STATUS,"
hexmask.long.byte 0x94 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS RTIA Clock"
newline
hexmask.long.byte 0x94 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS RTIA Clock"
line.long 0x98 "DSS_RTIB_CLK_STATUS,"
hexmask.long.byte 0x98 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS RTIB Clock"
newline
hexmask.long.byte 0x98 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS RTIB Clock"
line.long 0x9C "DSS_WDT_CLK_STATUS,"
hexmask.long.byte 0x9C 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS Watchdog Clock"
newline
hexmask.long.byte 0x9C 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS Watchdog Clock"
line.long 0xA0 "DSS_SCIA_CLK_STATUS,"
hexmask.long.byte 0xA0 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS SCIA Clock"
newline
hexmask.long.byte 0xA0 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS SCIA Clock"
line.long 0xA4 "DSS_DSP_RST_CTRL,"
bitfld.long 0xA4 8.--10. "assert_local,Local Reset control for DSS DSP Data should be loaded as multibit" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0xA4 4.--6. "assert_global,Global Reset control forDSS DSP Data should be loaded as multibit" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0xA4 0.--2. "assert_por,Power on Reset control for DSS DSP Data should be loaded as multibit" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0xA8 "DSS_ESM_RST_CTRL,"
bitfld.long 0xA8 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xAC "DSS_SCIA_RST_CTRL,"
bitfld.long 0xAC 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xB0 "DSS_RTIA_RST_CTRL,"
bitfld.long 0xB0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xB4 "DSS_RTIB_RST_CTRL,"
bitfld.long 0xB4 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xB8 "DSS_WDT_RST_CTRL,"
bitfld.long 0xB8 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xBC "DSS_DCCA_RST_CTRL,"
bitfld.long 0xBC 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xC0 "DSS_DCCB_RST_CTRL,"
bitfld.long 0xC0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xC4 "DSS_MCRC_RST_CTRL,"
bitfld.long 0xC4 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xC8 "DSP_DFT_DIV_CTRL,"
bitfld.long 0xC8 4.--6. "clk_disable,DSP DFT Control for clock_disable" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC8 0.--3. "div_factor,DSP DFT Control for div factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "DSS_DSP_L2_PD_CTRL,"
bitfld.long 0xCC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xCC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xCC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xD0 "DSS_L3_BANKA0_PD_CTRL,"
bitfld.long 0xD0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xD4 "DSS_L3_BANKA1_PD_CTRL,"
bitfld.long 0xD4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xD8 "DSS_L3_BANKA2_PD_CTRL,"
bitfld.long 0xD8 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD8 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD8 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xDC "DSS_L3_BANKA3_PD_CTRL,"
bitfld.long 0xDC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xDC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xDC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xE0 "DSS_L3_BANKB0_PD_CTRL,"
bitfld.long 0xE0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xE4 "DSS_L3_BANKB1_PD_CTRL,"
bitfld.long 0xE4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xE8 "DSS_L3_BANKB2_PD_CTRL,"
bitfld.long 0xE8 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE8 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE8 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xEC "DSS_L3_BANKB3_PD_CTRL,"
bitfld.long 0xEC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xEC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xEC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xF0 "DSS_L3_BANKC0_PD_CTRL,"
bitfld.long 0xF0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xF4 "DSS_L3_BANKC1_PD_CTRL,"
bitfld.long 0xF4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xF8 "DSS_L3_BANKC2_PD_CTRL,"
bitfld.long 0xF8 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xFC "DSS_L3_BANKC3_PD_CTRL,"
bitfld.long 0xFC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xFC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xFC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x100 "DSS_L3_BANKD0_PD_CTRL,"
bitfld.long 0x100 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x104 "DSS_L3_BANKD1_PD_CTRL,"
bitfld.long 0x104 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x108 "DSS_L3_BANKD2_PD_CTRL,"
bitfld.long 0x108 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x108 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x108 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
group.long 0x158++0x43
line.long 0x00 "DSS_HWA_PD_CTRL,"
bitfld.long 0x00 16.--18. "pgoodin,SW Control for <IP>_PD_CTRL Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "ponin,SW Control for <IP>_PD_CTRL Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x04 "DSS_DSP_L2_PD_STATUS,"
bitfld.long 0x04 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x04 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x08 "DSS_L3_BANKA0_PD_STATUS,"
bitfld.long 0x08 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x08 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x08 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x08 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x0C "DSS_L3_BANKA1_PD_STATUS,"
bitfld.long 0x0C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x0C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x0C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x0C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x10 "DSS_L3_BANKA2_PD_STATUS,"
bitfld.long 0x10 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x10 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x10 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x10 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x14 "DSS_L3_BANKA3_PD_STATUS,"
bitfld.long 0x14 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x14 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x14 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x14 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x18 "DSS_L3_BANKB0_PD_STATUS,"
bitfld.long 0x18 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x18 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x18 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x18 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x1C "DSS_L3_BANKB1_PD_STATUS,"
bitfld.long 0x1C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x1C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x1C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x1C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x20 "DSS_L3_BANKB2_PD_STATUS,"
bitfld.long 0x20 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x20 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x20 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x20 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x24 "DSS_L3_BANKB3_PD_STATUS,"
bitfld.long 0x24 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x24 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x24 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x24 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x28 "DSS_L3_BANKC0_PD_STATUS,"
bitfld.long 0x28 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x28 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x28 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x28 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x2C "DSS_L3_BANKC1_PD_STATUS,"
bitfld.long 0x2C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x2C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x2C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x2C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x30 "DSS_L3_BANKC2_PD_STATUS,"
bitfld.long 0x30 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x30 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x30 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x30 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x34 "DSS_L3_BANKC3_PD_STATUS,"
bitfld.long 0x34 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x34 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x34 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x34 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x38 "DSS_L3_BANKD0_PD_STATUS,"
bitfld.long 0x38 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x38 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x38 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x38 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x3C "DSS_L3_BANKD1_PD_STATUS,"
bitfld.long 0x3C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x3C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x3C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x3C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x40 "DSS_L3_BANKD2_PD_STATUS,"
bitfld.long 0x40 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x40 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x40 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x40 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
rgroup.long 0x1A0++0x43
line.long 0x00 "DSS_HWA_PD_STATUS,"
bitfld.long 0x00 3. "pgoodout,Status for <IP>_PD_CTRL Power up CRTL1" "0,1"
newline
bitfld.long 0x00 2. "ponout,Status for <IP>_PD_CTRL Power up CRTL0" "0,1"
newline
bitfld.long 0x00 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x00 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x04 "DSS_DSP_TRCCLK_DIVRATIO,"
bitfld.long 0x04 0.--3. "divratio,DSP Trace Clock Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DSS_DSP_TCLK_DIVRATIO,"
bitfld.long 0x08 0.--3. "divratio,DSP TCLK Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DSS_DSP_DITHERED_CLK_CTRL,"
bitfld.long 0x0C 31. "load,Write pulse bit field: DSP Dithered Clock LFSR Load" "0,1"
newline
bitfld.long 0x0C 28.--30. "enable,DSP Dithered Clock Enable" "Disabled,?,?,?,?,?,?,Enabled"
newline
hexmask.long 0x0C 0.--27. 1. "seed,DSP Dithered Clock LFSR Seed"
line.long 0x10 "DSS_L3_PD_CTRL_STICKYBIT,"
bitfld.long 0x10 0.--2. "set,Sticky bit for DSS L3 PD CTRL" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSP_PD_CTRL_MISC2,"
hexmask.long.word 0x14 16.--31. 1. "pwrsm_agood_assertcnt,Value of agood asertion delay"
newline
hexmask.long.word 0x14 0.--15. 1. "pwrsm_pgood_assertcnt,Value of pgood asertion delay"
line.long 0x18 "DSP_PD_CTRL_MISC3,"
bitfld.long 0x18 16. "lreset_req_gate,Gate the lreset request from GEM" "0,1"
newline
hexmask.long.word 0x18 0.--15. 1. "pwrs_pd_waitcnt,Value of power down wait delay"
line.long 0x1C "DSP_PD_CTRL_OVERRIDE0,"
bitfld.long 0x1C 24.--29. "state_bypass_val,DSS DSP power FSM state bypass control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.tbyte 0x1C 0.--23. 1. "bypass_val,DSS DSP power FSM bypass control"
line.long 0x20 "DSP_PD_CTRL_OVERRIDE1,"
bitfld.long 0x20 24. "state_bypass_en,DSS DSP power FSM state bypass control enable.For debug pupose" "0,1"
newline
hexmask.long.tbyte 0x20 0.--23. 1. "bypass_en,DSS DSP power FSM bypass control enable.For debug pupose"
line.long 0x24 "DSP_PD_CTRL_OVERRIDE2,"
bitfld.long 0x24 0.--2. "override_enable,DSS DSP power FSM override enable .For debug pupose" "0,1,2,3,4,5,6,7"
line.long 0x28 "DSS_HWA_RST_CTRL,"
bitfld.long 0x28 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x2C "DSS_HWA_RST_CTRL,"
bitfld.long 0x2C 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x30 "DSS_EDMA_RST_CTRL,"
bitfld.long 0x30 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x34 "DSS_EDMA_RST_CTRL,"
bitfld.long 0x34 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x38 "DSS_EDMA_RST_CTRL,"
bitfld.long 0x38 4.--6. "assert_tc1,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x38 0.--2. "assert_tc0,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x3C "DSS_EDMA_RST_CTRL,"
bitfld.long 0x3C 4.--6. "assert_tc1,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x3C 0.--2. "assert_tc0,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x40 "DSS_TPTCC_RST_CTRL,"
bitfld.long 0x40 20.--22. "assert_tc5,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 16.--18. "assert_tc4,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 12.--14. "assert_tc3,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 8.--10. "assert_tc2,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 4.--6. "assert_tc1,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 0.--2. "assert_tc0,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x3C)++0x03
line.long 0x00 "DSP_PD_WAKEUP_STATUS$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_RTIA (DSS RTIA Module Registers)"
base ad:0x6F7A000
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "DSS_RTIB (DSS RTIB Module Registers)"
base ad:0x6F7A100
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "DSS_SCIA (DSS SCIA Module Registers)"
base ad:0x6F7B000
group.long 0x00++0x5F
line.long 0x00 "SCIGCR0,The SCIGCR0 register defines the module reset"
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
newline
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
line.long 0x04 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
rbitfld.long 0x04 26.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
newline
bitfld.long 0x04 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
newline
rbitfld.long 0x04 18.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
newline
bitfld.long 0x04 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
newline
rbitfld.long 0x04 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
newline
bitfld.long 0x04 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function" "0,1"
newline
bitfld.long 0x04 7. "SW_nRESET,Software reset (active low)" "0,1"
newline
rbitfld.long 0x04 6. "RESERVED1,Reserved" "0,1"
newline
bitfld.long 0x04 5. "CLOCK,SCI internal clock enable" "0,1"
newline
bitfld.long 0x04 4. "STOP,SCI number of stop bits" "0,1"
newline
bitfld.long 0x04 3. "PARITY,SCI parity odd/even selection" "0,1"
newline
bitfld.long 0x04 2. "PARITY_ENA,SCI parity enable" "0,1"
newline
bitfld.long 0x04 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0,1"
newline
bitfld.long 0x04 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0,1"
line.long 0x08 "RESERVED1,Reserved"
line.long 0x0C "SCISETINT,SCI Set Interrupt Register"
rbitfld.long 0x0C 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x0C 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request for address and data frames"
newline
bitfld.long 0x0C 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x0C 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x0C 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 8. "SET_TX_INT,Set Transmitter interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x0C 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 0. "SET_BRKDT_INT,Set Break-detect interrupt" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x10 "SCICLEARINT,SCI Clear Interrupt Register"
rbitfld.long 0x10 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 25. "CLR_OE_INT,Clear Overrun-Error Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 24. "CLR_PE_INT,Clear Parity Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x10 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 18. "CLR_RX_DMA_ALL,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request for address frames"
newline
bitfld.long 0x10 17. "CLR_RX_DMA,Clear RX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x10 16. "CLR_TX_DMA,Clear TX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
newline
rbitfld.long 0x10 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 9. "CLR_RX_INT,Clear Receiver interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 8. "CLR_TX_INT,Clear Transmitter interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
rbitfld.long 0x10 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 0. "CLR_BRKDT_INT,Clear Break-detect interrupt" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x14 "SCISETINTLVL,SCI Set Interrupt Level Register"
rbitfld.long 0x14 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
bitfld.long 0x14 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
bitfld.long 0x14 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
rbitfld.long 0x14 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read)" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x14 15. "SET_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x14 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
line.long 0x18 "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
rbitfld.long 0x18 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x18 15. "CLR_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x18 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x18 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
line.long 0x1C "SCIFLR,SCI Flags Register"
rbitfld.long 0x1C 27.--31. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 26. "FE,SCI framing error flag Read" "No effect,Clears this bit to 0"
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rbitfld.long 0x1C 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
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rbitfld.long 0x1C 24. "PE,SCI parity error flag" "0,1"
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hexmask.long.word 0x1C 13.--23. 1. "RESERVED2,Reserved"
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rbitfld.long 0x1C 12. "RXWAKE,Receiver wake-up detect flag" "0,1"
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rbitfld.long 0x1C 11. "TX_EMPTY,Transmitter empty flag" "0,1"
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bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wake-up method select" "0,1"
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rbitfld.long 0x1C 9. "RXRDY,SCI receiver ready flag" "0,1"
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rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag" "0,1"
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rbitfld.long 0x1C 4.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame" "0,1"
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rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state" "0,1"
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rbitfld.long 0x1C 1. "WAKEUP,Wake-up flag" "0,1"
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rbitfld.long 0x1C 0. "BRKDT,SCI break-detect flag" "0,1"
line.long 0x20 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x20 0.--3. "INTVECT0,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x24 0.--3. "INTVECT1,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "SCICHAR,SCI Character Control Register"
hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x28 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
line.long 0x2C "SCIBAUD,SCI Baud Rate Selection Register"
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED,Reserved"
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hexmask.long.tbyte 0x2C 0.--23. 1. "BAUD,SCI 24-bit baud selection"
line.long 0x30 "SCIED,Receiver Emulation Data Buffer"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x30 0.--7. 1. "ED,Receiver Emulation Data Buffer"
line.long 0x34 "SCIRD,Receiver Data Buffer"
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x34 0.--7. 1. "RD,Contains received data"
line.long 0x38 "SCITD,Transmit Data Buffer Register"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x38 0.--7. 1. "TD,Contains Data to be transmitted"
line.long 0x3C "SCIPIO0,SCI Pin I/O Control Register 0"
hexmask.long 0x3C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x3C 2. "TX_FUNC,Defines the function of pin SCITX" "SCIRX is a general-purpose digital I/O pin,SCIRX is the SCI receive pin"
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bitfld.long 0x3C 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x3C 0. "CLK_FUNC,Clock function" "SCICLK is a general-purpose digital I/O pin,SCICLK is the SCI serial clock pin"
line.long 0x40 "SCIPIO1,SCI Pin I/O Control Register 1"
hexmask.long 0x40 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x40 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0)" "SCITX is a general-purpose input pin,SCITX is a general-purpose output pin"
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bitfld.long 0x40 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x40 0. "CLK_DIR,Clock data direction" "0,1"
line.long 0x44 "SCIPIO2,SCI Pin I/O Control Register 2"
hexmask.long 0x44 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x44 2. "TX_DATA_IN,Contains current value on the SCITX pin" "SCITX value is logic low,SCITX value is logic high"
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bitfld.long 0x44 1. "RX_DATA_IN,Contains current value on the SCIRX pin" "SCIRX value is logic low,SCIRX value is logic high"
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bitfld.long 0x44 0. "CLK_DATA_IN,Contains the current value on pin SCICLK" "Pin SCICLK value is logic low,Pin SCICLK value is logic high"
line.long 0x48 "SCIPIO3,SCI Pin I/O Control Register 3"
hexmask.long 0x48 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x48 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "Output value on SCITX is a 0 (logic low),Output value on SCITX is a 1 (logic high)"
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bitfld.long 0x48 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "Output value on SCIRX is 0 (logic low),Output value on SCIRX is 1 (logic high)"
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bitfld.long 0x48 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "Output value on SCICLK is a 0 (logic low),Output value on SCICLK is a 1 (logic high)"
line.long 0x4C "SCIPIO4,SCI Pin I/O Control Register 4"
hexmask.long 0x4C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4C 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
line.long 0x50 "SCIPIO5,SCI Pin I/O Control Register 5"
hexmask.long 0x50 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x50 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
line.long 0x54 "SCIPIO6,SCI Pin I/O Control Register 6"
hexmask.long 0x54 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x54 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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bitfld.long 0x54 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x54 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
line.long 0x58 "SCIPIO7,SCI Pin I/O Control Register 7"
hexmask.long 0x58 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x58 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX" "Pull Control on SCITX pin is enabled,Pull Control on SCITX pin is disabled"
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bitfld.long 0x58 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX" "Pull Control on SCIRX pin is enabled,Pull Control on SCIRX pin is disabled"
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bitfld.long 0x58 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK" "Pull Control on SCICLK pin is enabled,Pull Control on SCICLK pin is disabled"
line.long 0x5C "SCIPIO8,SCI Pin I/O Control Register 8"
hexmask.long 0x5C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x5C 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX" "Pull-Down is on SCITX pin,Pull-Up is on SCITX pin"
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bitfld.long 0x5C 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX" "Pull-Down is on SCIRX pin,Pull-Up is on SCIRX pin"
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bitfld.long 0x5C 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK" "Pull-Down is on SCICLK pin,Pull-Up is on SCICLK pin"
group.long 0x80++0x03
line.long 0x00 "SCIPIO9,SCI Pin I/O Control Register 9"
hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 2. "TX_SL,This bit controls the slew rate for the SCITX pin" "The normal output buffer is used for SCITX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 1. "RX_SL,This bit controls the slew rate for the SCIRX pin" "The normal output buffer is used for SCIRX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin" "The normal output buffer is used for SCICLK pin,The output buffer with slew control is used for.."
group.long 0x90++0x03
line.long 0x00 "SCIIODCTRL,SCI IO DFT Control"
rbitfld.long 0x00 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 26. "FEN,Frame Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 25. "PEN,Parity Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 24. "BRKDT_ENA,Break Detect Error Enable" "No effect,This bit is used to.."
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rbitfld.long 0x00 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry" "0,1,2,3"
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bitfld.long 0x00 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 12.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "LBP_ENA,Module loopback enable" "Digital loopback is enabled,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x00 0. "RXP_ENA,Module Analog loopback through receive pin enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
repeat 8. (list 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "DSS_TPCC_A (DSS TPCCA Module Registers)"
base ad:0x6100000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
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bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
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bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
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bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
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bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
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bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
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bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
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bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
newline
hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
newline
hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
newline
bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
newline
bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
newline
bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
newline
bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
newline
bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
newline
bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
newline
bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
newline
bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
newline
bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
newline
bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
newline
bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
newline
bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
newline
bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
newline
bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
newline
bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
newline
bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
newline
bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
newline
bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
newline
bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
tree "DSS_TPCC_B (DSS TPCCB Module Registers)"
base ad:0x6120000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
newline
hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
newline
hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
newline
bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
newline
bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
newline
bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
newline
bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
newline
bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
newline
bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
newline
bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
newline
bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
newline
bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
newline
bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
newline
bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
newline
bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
newline
bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
newline
bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
newline
bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
newline
bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
newline
bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
tree "DSS_TPCC_C (DSS TPCCC Module Registers)"
base ad:0x6140000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
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bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
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bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
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bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
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bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
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bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
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bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
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bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
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bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
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bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
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bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
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bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
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bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
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bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
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bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
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bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
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bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
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bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
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bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
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bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
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bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
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bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
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bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
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bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
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bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
newline
hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
newline
hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
newline
bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
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bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
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bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
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bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
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bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
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bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
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bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
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bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
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bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
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bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
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bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
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bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
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bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
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bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
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bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
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bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
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bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
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bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
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bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
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bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
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bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
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bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
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bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
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bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
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bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
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bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
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bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
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bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
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bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
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bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
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bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
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bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
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bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
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bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
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bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
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bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
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bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
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bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
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bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
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bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
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bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
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bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
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bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
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bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
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bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
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bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
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bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
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bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
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bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
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bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
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bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
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bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
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bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
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bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
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bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
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bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
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bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
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bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
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bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
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bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
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bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
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bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
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bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
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bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
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bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
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bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
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bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
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bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
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bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
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bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
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bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
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bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
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bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
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bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
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bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
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bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
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bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
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bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
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bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
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bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
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bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
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bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x6160000 ad:0x6180000 )
tree "DSS_TPTC_A$1 (DSS TPTC A$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
repeat 2. (list 0. 1. )(list ad:0x61A0000 ad:0x61C0000 )
tree "DSS_TPTC_B$1 (DSS TPTC B$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
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bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
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bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
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bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
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bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list ad:0x61E0000 ad:0x6200000 ad:0x6220000 ad:0x6240000 ad:0x6260000 ad:0x6280000 )
tree "DSS_TPTC_C$1 (DSS TPTC C$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
tree "DSS_WDT (DSS WDT Module Registers)"
base ad:0x6F7A200
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x401A0000 ad:0x401C0000 )
tree "MPU_DSS_HWA_DMA$1 (DSS HWA DMA$1 MPU Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
repeat.end
tree "MPU_DSS_HWA_PROC (DSS HWA PROC MPU Module Registers)"
base ad:0x401E0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKA (DSS L3 BANKA MPU Module Registers)"
base ad:0x40120000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKB (DSS L3 BANKB MPU Module Registers)"
base ad:0x40140000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKC (DSS L3 BANKC MPU Module Registers)"
base ad:0x40160000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKD (MSS L3 BANKD MPU Module Registers)"
base ad:0x40180000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_MBOX (DSS MBOX MPU Module Registers)"
base ad:0x40200000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_CR5A_AXIS (MSS CR5A AXIS MPU Module Registers)"
base ad:0x400E0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_CR5B_AXIS (MSS CR5B AXIS MPU Module Registers)"
base ad:0x40100000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_L2_BANKA (MSS L2 BANKA MPU Module Registers)"
base ad:0x40020000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_L2_BANKB (MSS L2 BANKB MPU Module Registers)"
base ad:0x40040000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_MBOX (MPU MSS MBOX Module Registers)"
base ad:0x40080000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_PCRA (MSS PCRA MPU Module Registers)"
base ad:0x400A0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_QSPI (MSS QSPI MPU Module Registers)"
base ad:0x400C0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MSS_CCMR (MSS CCMR Module Registers)"
base ad:0x2F7AC00
group.long 0x00++0x1B
line.long 0x00 "CCMSR1,CPU Compare Status Register"
hexmask.long.word 0x00 17.--31. 1. "NU2,Reserved"
bitfld.long 0x00 16. "CMPE1,Compare Error" "CPU signals are identical,CPU signal compare mismatch Writes '1' to clear.."
newline
hexmask.long.byte 0x00 9.--15. 1. "NU1,Reserved"
bitfld.long 0x00 8. "STC1,Self Test Complete" "self test on-going if self test mode asserted,self test is complete Writes have no effect"
newline
bitfld.long 0x00 2.--7. "NU0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "STET1,Self Test Error Type" "self test failed during Compare Match test,self test failed during Compare mismatch test.."
newline
bitfld.long 0x00 0. "STE1,Self Test Error" "self test passed,self test failed Writes have no effect"
line.long 0x04 "CCMKEYR1,CPU Compare Key Register"
hexmask.long 0x04 4.--31. 1. "NU3,Reserved"
bitfld.long 0x04 0.--3. "MKEY1,Mode Key" "lock step mode,?,?,?,?,?,self test mode,?,?,error forcing mode,?,?,?,?,?,self test error forcing mode"
line.long 0x08 "CCMSR2,VIM Compare Status Register"
hexmask.long.word 0x08 17.--31. 1. "NU6,Reserved"
bitfld.long 0x08 16. "CMPE2,Compare Error" "VIM signals are identical,VIM signal compare mismatch Writes '1' to clear.."
newline
hexmask.long.byte 0x08 9.--15. 1. "NU5,Reserved"
bitfld.long 0x08 8. "STC2,Self Test Complete" "self test on-going if self test mode asserted,self test is complete Writes have no effect"
newline
bitfld.long 0x08 2.--7. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 1. "STET2,Self Test Error Type" "self test failed during Compare Match test,self test failed during Compare mismatch test.."
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bitfld.long 0x08 0. "STE2,Self Test Error" "self test passed,self test failed Writes have no effect"
line.long 0x0C "CCMKEYR2,VIM Compare Key Register"
hexmask.long 0x0C 4.--31. 1. "NU7,Reserved"
bitfld.long 0x0C 0.--3. "MKEY2,Mode Key" "lock step mode,?,?,?,?,?,self test mode,?,?,error forcing mode,?,?,?,?,?,self test error forcing mode"
line.long 0x10 "CCMSR3,Inactivity Monitor Status Register"
hexmask.long.word 0x10 17.--31. 1. "NU10,Reserved"
bitfld.long 0x10 16. "CMPE3,Compare Error" "Inactivity monitor signals are identical,Inactivity monitor signal compare mismatch.."
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hexmask.long.byte 0x10 9.--15. 1. "NU9,Reserved"
bitfld.long 0x10 8. "STC3,Self Test Complete" "self test on-going if self test mode asserted,self test is complete Writes have no effect"
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bitfld.long 0x10 2.--7. "NU8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 1. "STET3,Self Test Error Type" "self test failed during Compare Match test,self test failed during Compare mismatch test.."
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bitfld.long 0x10 0. "STE3,Self Test Error" "self test passed,self test failed Writes have no effect"
line.long 0x14 "CCMKEYR3,Inactivity Monitor Key Register"
hexmask.long 0x14 4.--31. 1. "NU11,Reserved"
bitfld.long 0x14 0.--3. "MKEY3,Mode Key" "lock step mode,?,?,?,?,?,self test mode,?,?,error forcing mode,?,?,?,?,?,self test error forcing mode"
line.long 0x18 "CCMPOLCNTRL,CPU Compare Polarity Control Register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU12,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "POL_INV,This value is used to invert the 8 XOR of the CPU1 to create compare fail in functional active compare mode"
width 0x0B
tree.end
tree "MSS_CPSW (MSS CPSW Module Registers)"
base ad:0x7000000
rgroup.long 0x00++0x0F
line.long 0x00 "SS_IDVER_REG,SS ID Version Register"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "SS_SYNCE_COUNT_REG,SS SYNCE Count Register"
line.long 0x08 "SS_SYNCE_MUX_REG,SS Synce Mux Register"
bitfld.long 0x08 0.--5. "SYNCE_SEL,Sync E Select Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "SS_CONTROL_REG,SS Control Register"
bitfld.long 0x0C 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode" "The low power indicate state includes gating off..,The low power indicate state does not gate the.."
newline
bitfld.long 0x0C 0. "EEE_EN,Energy Efficient Ethernet Enable" "EEE is disabled,EEE is enabled"
group.long 0x18++0x07
line.long 0x00 "SS_INT_CONTROL_REG,SS Interrupt Control Register"
bitfld.long 0x00 31. "INT_TEST,Interrupt Test" "0,1"
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bitfld.long 0x00 16.--21. "INT_BYPASS,Interrupt Bypass Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--11. 1. "INT_PRESCALE,Interrupt Prescale Value"
line.long 0x04 "SS_STATUS_REG,SS Status Register"
bitfld.long 0x04 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1"
rgroup.long 0x30++0x03
line.long 0x00 "SS_RGMII1_STATUS_REG,RGMII1 Status Register"
bitfld.long 0x00 3. "FULLDUPLEX,Rgmii full dulex" "Half-duplex,Full-duplex"
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bitfld.long 0x00 1.--2. "SPEED,Rgmii1 speed" "0,1,2,3"
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bitfld.long 0x00 0. "LINK,Rgmii1 link indicator" "Link is down,Link is up"
group.long 0x80++0x0F
line.long 0x00 "SS_TH_THRESH_PULSE_EN_REG,THost Threshold Pulse Interrupt Enable Register"
hexmask.long.byte 0x00 0.--7. 1. "TH_THRESH_PULSE_EN,THost Threshold Pulse Interrupt Enable Register"
line.long 0x04 "SS_TH_PULSE_EN_REG,THost Pulse Interrupt Enable Register"
hexmask.long.byte 0x04 0.--7. 1. "TH_PULSE_EN,THost Pulse Interrupt Enable Register"
line.long 0x08 "SS_FH_PULSE_EN_REG,FHost Pulse Interrupt Enable Register"
hexmask.long.byte 0x08 0.--7. 1. "FH_PULSE_EN,FHost Pulse Interrupt Enable Register"
line.long 0x0C "SS_MISC_EN_REG,Misc Interrupt Enable Register"
bitfld.long 0x0C 6. "DED_PEND_EN,MISC DED Memory Protect Error Interrupt Enable" "0,1"
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bitfld.long 0x0C 5. "SEC_PEND_EN,MISC SEC Memory Protect Error Interrupt Enable" "0,1"
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bitfld.long 0x0C 4. "EVNT_PEND_EN,MISC CPTS Event Interrupt Enable" "0,1"
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bitfld.long 0x0C 3. "STAT_PEND_EN,MISC Statistics Interrupt Enable - OR of bits n downto 0" "0,1"
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bitfld.long 0x0C 2. "HOST_PEND_EN,MISC Host Interrupt Enable" "0,1"
newline
bitfld.long 0x0C 1. "MDIO_LINKINT_EN,MISC MDIO linkint - OR of bits 1 and 0" "0,1"
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bitfld.long 0x0C 0. "MDIO_USERINT_EN,MISC_MDIO userint interrupt enable - OR of bits 1 and 0" "0,1"
rgroup.long 0xB0++0x0F
line.long 0x00 "SS_TH_THRESH_PULSE_STATUS_REG,THost Threshold Pulse Interrupt Status Register"
hexmask.long.byte 0x00 0.--7. 1. "TH_THRESH_PULSE_ST,THost Threshold Pulse Interrupt Status Register"
line.long 0x04 "SS_TH_PULSE_STATUS_REG,THost Pulse Interrupt Status Register"
hexmask.long.byte 0x04 0.--7. 1. "TH_PULSE_STATUS,THost Pulse Interrupt Status Register"
line.long 0x08 "SS_FH_PULSE_STATUS_REG,FHost Pulse Interrupt Status Register"
hexmask.long.byte 0x08 0.--7. 1. "FH_PULSE_STATUS,FHost Pulse Interrupt Status Register"
line.long 0x0C "SS_MISC_STATUS_REG,Misc Interrupt Status Register - Set bits in this register indicate that an enabled interrupt is asserted"
bitfld.long 0x0C 6. "DED_PEND,MISC DED Memory Protect Error Interrupt" "0,1"
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bitfld.long 0x0C 5. "SEC_PEND,MISC SEC Memory Protect Error Interrupt" "0,1"
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bitfld.long 0x0C 4. "EVNT_PEND,MISC CPTS Event Interrupt" "0,1"
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bitfld.long 0x0C 3. "STAT_PEND,MISC Statistics Interrupt - OR of bits n downto 0" "0,1"
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bitfld.long 0x0C 2. "HOST_PEND,MISC Host Interrupt Enable" "0,1"
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bitfld.long 0x0C 1. "MDIO_LINKINT,MISC MDIO linkint - OR of bits 1 and 0" "0,1"
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bitfld.long 0x0C 0. "MDIO_USERINT,MISC_MDIO userint interrupt - OR of bits 1 and 0" "0,1"
group.long 0xE0++0x07
line.long 0x00 "SS_TH_IMAX_REG,THost Interrupt Max Register Register"
bitfld.long 0x00 0.--5. "TH_IMAX,THost Interrupt Max Register Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SS_FH_IMAX_REG,FHost Interrupt Max Register Register"
bitfld.long 0x04 0.--5. "FH_IMAX,FHost Interrupt Max Register Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0xF00++0x47
line.long 0x00 "MDIO_VERSION_REG,MDIO Version Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CONTROL_REG,MDIO Control Register"
rbitfld.long 0x04 31. "IDLE,MDIO state machine idle" "0,1"
newline
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
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rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
newline
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
newline
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
newline
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
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hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider"
line.long 0x08 "ALIVE_REG,MDIO Alive Register"
line.long 0x0C "LINK_REG,MDIO Link Register"
line.long 0x10 "LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x14 "LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x18 "LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x18 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0x1C "LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
bitfld.long 0x1C 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x20 "USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
bitfld.long 0x20 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
line.long 0x24 "USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
bitfld.long 0x24 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
line.long 0x28 "USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x28 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
line.long 0x2C "USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
bitfld.long 0x2C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
line.long 0x30 "MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x30 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
newline
bitfld.long 0x30 1. "MDIO_OE,MDIO Output Enable" "0,1"
newline
bitfld.long 0x30 0. "MDIO_PIN,MDIO Pin" "0,1"
line.long 0x34 "POLL_REG,MDIO Poll Register"
bitfld.long 0x34 31. "MANUALMODE,MDIO Manual Mode" "0,1"
newline
bitfld.long 0x34 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
newline
hexmask.long.byte 0x34 0.--7. 1. "IPG,MDIO IPG"
line.long 0x38 "POLL_EN_REG,MDIO Poll Enable Register"
line.long 0x3C "CLAUS45_REG,MDIO Clause45 Register"
line.long 0x40 "USER_ADDR0_REG,MDIO Address 0 Register"
hexmask.long.word 0x40 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
line.long 0x44 "USER_ADDR1_REG,MDIO Address 1 Register"
hexmask.long.word 0x44 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
group.long 0xF80++0x07
line.long 0x00 "USER_ACCESS_REG,MDIO User Access Register"
bitfld.long 0x00 31. "GO,Go" "0,1"
newline
bitfld.long 0x00 30. "WRITE," "0,1"
newline
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
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bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
line.long 0x04 "USER_PHY_SEL_REG,MDIO User PHY Select Register"
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
newline
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
newline
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x20000++0x07
line.long 0x00 "CPSW_ID_VER_REG,CPSW ID Version"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification Value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM_VER,Custom Version Value" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR_VER,Minor Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CONTROL_REG,CPSW Switch Control"
bitfld.long 0x04 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1"
newline
bitfld.long 0x04 18. "EST_ENABLE,Intersperced Express Traffic enable" "0,1"
newline
bitfld.long 0x04 17. "UNUSED,Unused" "0,1"
newline
bitfld.long 0x04 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1"
newline
bitfld.long 0x04 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1"
newline
bitfld.long 0x04 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1"
newline
bitfld.long 0x04 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1"
newline
bitfld.long 0x04 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 2. "P0_ENABLE,Port 0 Enable" "0,1"
newline
bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "0,1"
newline
bitfld.long 0x04 0. "S_CN_SWITCH,VLAN Aware Mode" "0,1"
group.long 0x20010++0x37
line.long 0x00 "EM_CONTROL_REG,CPSW Emulation Control"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
newline
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "STAT_PORT_EN_REG,CPSW Statistics Port Enable"
bitfld.long 0x04 8. "P8_STAT_EN,Port 8 Statistics Enable" "0,1"
newline
bitfld.long 0x04 7. "P7_STAT_EN,Port 7 Statistics Enable" "0,1"
newline
bitfld.long 0x04 6. "P6_STAT_EN,Port 6 Statistics Enable" "0,1"
newline
bitfld.long 0x04 5. "P5_STAT_EN,Port 5 Statistics Enable" "0,1"
newline
bitfld.long 0x04 4. "P4_STAT_EN,Port 4 Statistics Enable" "0,1"
newline
bitfld.long 0x04 3. "P3_STAT_EN,Port 3 Statistics Enable" "0,1"
newline
bitfld.long 0x04 2. "P2_STAT_EN,Port 2 Statistics Enable" "0,1"
newline
bitfld.long 0x04 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1"
newline
bitfld.long 0x04 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1"
line.long 0x08 "PTYPE_REG,CPSW Transmit Priority Type"
bitfld.long 0x08 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 0.--4. "ESC_PRI_LD_VAL,Escalate Priority Load Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "SOFT_IDLE_REG,CPSW Software Idle"
bitfld.long 0x0C 0. "SOFT_IDLE,Software Idle" "0,1"
line.long 0x10 "THRU_RATE_REG,CPSW Thru Rate"
bitfld.long 0x10 12.--15. "SL_RX_THRU_RATE,Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 0.--3. "P0_RX_THRU_RATE,CPPI FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold"
bitfld.long 0x14 0.--4. "GAP_THRESH,Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "TX_START_WDS_REG,CPSW Transmit FIFO Start Words"
hexmask.long.word 0x18 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit Start Words"
line.long 0x1C "EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value"
hexmask.long.word 0x1C 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value"
line.long 0x20 "TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set"
bitfld.long 0x20 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear"
bitfld.long 0x24 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low"
hexmask.long.byte 0x28 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
newline
hexmask.long.byte 0x28 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
newline
hexmask.long.byte 0x28 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
newline
hexmask.long.byte 0x28 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x2C "TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High"
hexmask.long.byte 0x2C 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
newline
hexmask.long.byte 0x2C 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
newline
hexmask.long.byte 0x2C 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
newline
hexmask.long.byte 0x2C 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
line.long 0x30 "TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low"
hexmask.long.byte 0x30 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
newline
hexmask.long.byte 0x30 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
newline
hexmask.long.byte 0x30 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
newline
hexmask.long.byte 0x30 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x34 "TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High"
hexmask.long.byte 0x34 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
newline
hexmask.long.byte 0x34 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
newline
hexmask.long.byte 0x34 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
newline
hexmask.long.byte 0x34 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
group.long 0x20050++0x07
line.long 0x00 "VLAN_LTYPE_REG,VLAN Length/type"
hexmask.long.word 0x00 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType"
newline
hexmask.long.word 0x00 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType"
line.long 0x04 "EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain"
hexmask.long.byte 0x04 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain"
group.long 0x20100++0x1F
line.long 0x00 "TX_PRI0_MAXLEN_REG,Transmit Priority 0 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Length"
line.long 0x04 "TX_PRI1_MAXLEN_REG,Transmit Priority 1 Maximum Length"
hexmask.long.word 0x04 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Length"
line.long 0x08 "TX_PRI2_MAXLEN_REG,Transmit Priority 2 Maximum Length"
hexmask.long.word 0x08 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Length"
line.long 0x0C "TX_PRI3_MAXLEN_REG,Transmit Priority 3 Maximum Length"
hexmask.long.word 0x0C 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Length"
line.long 0x10 "TX_PRI4_MAXLEN_REG,Transmit Priority 4 Maximum Length"
hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Length"
line.long 0x14 "TX_PRI5_MAXLEN_REG,Transmit Priority 5 Maximum Length"
hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Length"
line.long 0x18 "TX_PRI6_MAXLEN_REG,Transmit Priority 6 Maximum Length"
hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Length"
line.long 0x1C "TX_PRI7_MAXLEN_REG,Transmit Priority 7 Maximum Length"
hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Length"
group.long 0x21004++0x07
line.long 0x00 "P0_CONTROL_REG,CPPI Port 0 Control"
bitfld.long 0x00 18. "RX_REMAP_DSCP_V6,Port 0 Remap DSCP_V6 Enable" "0,1"
newline
bitfld.long 0x00 17. "RX_REMAP_DSCP_V4,Port 0 Remap DSCP_V4 Enable" "0,1"
newline
bitfld.long 0x00 16. "RX_REMAP_VLAN,Port 0 Remap VLAN Enable" "0,1"
newline
bitfld.long 0x00 15. "RX_ECC_ERR_EN,Port 0 Receive ECC Error Enable" "0,1"
newline
bitfld.long 0x00 14. "TX_ECC_ERR_EN,Port 0 Transmit ECC Error Enable" "0,1"
newline
bitfld.long 0x00 2. "DSCP_IPV6_EN,Port 0 IPv6 DSCP enable" "0,1"
newline
bitfld.long 0x00 1. "DSCP_IPV4_EN,Port 0 IPv4 DSCP enable" "0,1"
newline
bitfld.long 0x00 0. "RX_CHECKSUM_EN,Port 0 Receive Checksum Enable" "0,1"
line.long 0x04 "P0_FLOW_ID_OFFSET_REG,CPPI Port 0 Flow ID Offset"
hexmask.long.word 0x04 0.--13. 1. "VALUE,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0"
rgroup.long 0x21010++0x1B
line.long 0x00 "P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count"
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Port 0 Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--5. "RX_BLK_CNT,Port 0 Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "P0_PORT_VLAN_REG,CPPI Port 0 VLAN"
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
newline
hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
line.long 0x08 "P0_TX_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x08 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x0C "P0_PRI_CTL_REG,CPPI Port 0 Priority Control"
hexmask.long.byte 0x0C 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
newline
bitfld.long 0x0C 8. "RX_PTYPE,Receive Priority Type" "0,1"
line.long 0x10 "P0_RX_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map"
bitfld.long 0x10 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "P0_RX_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length"
hexmask.long.word 0x14 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length"
line.long 0x18 "P0_TX_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority"
bitfld.long 0x18 28.--31. "PRI7,Priority 7 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 24.--27. "PRI6,Priority 6 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 20.--23. "PRI5,Priority 5 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 16.--19. "PRI4,Priority 4 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 12.--15. "PRI3,Priority 3 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 8.--11. "PRI2,Priority 2 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 4.--7. "PRI1,Priority 1 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "PRI0,Priority 0 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x21030++0x0F
line.long 0x00 "P0_IDLE2LPI_REG,Port 0 EEE Idle to LPI counter"
hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Port 0 EEE Idle to LPI counter load value"
line.long 0x04 "P0_LPI2WAKE_REG,Port 0 EEE LPI to wake counter"
hexmask.long.tbyte 0x04 0.--23. 1. "COUNT,Port 0 EEE LPI to wake counter load value"
line.long 0x08 "P0_EEE_STATUS_REG,Port 0 EEE status"
bitfld.long 0x08 6. "TX_FIFO_EMPTY,CPPI port 0 transmit FIFO (switch egress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x08 5. "RX_FIFO_EMPTY,CPPI port 0 receive FIFO (switch ingress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x08 4. "TX_FIFO_HOLD,CPPI port 0 transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
newline
bitfld.long 0x08 3. "TX_WAKE,CPPI port 0 transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
newline
bitfld.long 0x08 2. "TX_LPI,CPPI port 0 transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
newline
bitfld.long 0x08 1. "RX_LPI,CPPI port 0 receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
newline
bitfld.long 0x08 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
line.long 0x0C "P0_RX_PKTS_PRI_REG,CPPI Port Receive Packets per priority"
bitfld.long 0x0C 28.--31. "PRI7,Priority 7 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 24.--27. "PRI6,Priority 6 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 20.--23. "PRI5,Priority 5 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 16.--19. "PRI4,Priority 4 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 12.--15. "PRI3,Priority 3 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 8.--11. "PRI2,Priority 2 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 4.--7. "PRI1,Priority 1 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0.--3. "PRI0,Priority 0 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2104C++0x07
line.long 0x00 "P0_RX_GAP_REG,Port 0 Receive Gap Register"
hexmask.long.word 0x00 16.--25. 1. "RX_GAP_CNT,Port 0 Receive Gap Count"
newline
hexmask.long.byte 0x00 0.--7. 1. "RX_GAP_EN,Port 0 Receive Gap Enable"
line.long 0x04 "P0_FIFO_STATUS_REG,Port 0 FIFO Status"
hexmask.long.byte 0x04 0.--7. 1. "TX_PRI_ACTIVE,Port 0 FIFO Status"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x21120)++0x03
line.long 0x00 "P0_RX_DSCP_MAP_REG_$1,CPPI Port 0 Receive IPV4/IPV6 DSCP Map N"
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x21140)++0x03
line.long 0x00 "P0_PRI_CIR_REG_$1,CPPI Port 0 Rx Priority P Committed Information Rate"
hexmask.long 0x00 0.--27. 1. "PRI_CIR,Priority N CIR"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x21160)++0x03
line.long 0x00 "P0_PRI_EIR_REG_$1,CPPI Port 0 Rx Priority P Excess Information Rate"
hexmask.long 0x00 0.--27. 1. "PRI_EIR,Priority N EIR"
repeat.end
group.long 0x21180++0x1F
line.long 0x00 "P0_TX_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "P0_TX_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High"
bitfld.long 0x04 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "P0_TX_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low"
bitfld.long 0x08 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "P0_TX_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High"
bitfld.long 0x0C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "P0_TX_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x10 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "P0_TX_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x14 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "P0_TX_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x18 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "P0_TX_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x1C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21300++0x07
line.long 0x00 "P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A"
hexmask.long.byte 0x00 24.--31. 1. "PORT4,Port 4 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x00 16.--23. 1. "PORT3,Port 3 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x00 8.--15. 1. "PORT2,Port 2 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x00 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value"
line.long 0x04 "P0_SRC_ID_B_REG,CPPI Port 0 CPPI Source ID B"
hexmask.long.byte 0x04 24.--31. 1. "PORT8,Port 8 CPPI Info Word0 Source ID Value"
newline
hexmask.long.byte 0x04 16.--23. 1. "PORT7,Port 7 CPPI Info Word0 Source ID Value"
newline
hexmask.long.byte 0x04 8.--15. 1. "PORT6,Port 6 CPPI Info Word0 Source ID Value"
newline
hexmask.long.byte 0x04 0.--7. 1. "PORT5,Port 5 CPPI Info Word0 Source ID Value"
group.long 0x21320++0x03
line.long 0x00 "P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority"
bitfld.long 0x00 28.--31. "PRI7,Priority 7 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 24.--27. "PRI6,Priority 6 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PRI5,Priority 5 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "PRI4,Priority 4 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PRI3,Priority 3 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "PRI2,Priority 2 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PRI1,Priority 1 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PRI0,Priority 0 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x22000++0x0B
line.long 0x00 "PN_RESERVED_REG,Reserved"
line.long 0x04 "PN_CONTROL_REG,Enet Port N Control"
bitfld.long 0x04 17. "EST_PORT_EN,EST Port Enable" "0,1"
newline
bitfld.long 0x04 15. "RX_ECC_ERR_EN,Port 0 Receive ECC Error Enable" "0,1"
newline
bitfld.long 0x04 14. "TX_ECC_ERR_EN,Port 0 Transmit ECC Error Enable" "0,1"
newline
bitfld.long 0x04 12. "TX_LPI_CLKSTOP_EN,Transmit LPI clockstop enable" "0,1"
newline
bitfld.long 0x04 2. "DSCP_IPV6_EN,IPv6 DSCP enable" "0,1"
newline
bitfld.long 0x04 1. "DSCP_IPV4_EN,IPv4 DSCP enable" "0,1"
line.long 0x08 "PN_MAX_BLKS_REG,Enet Port N FIFO Max Blocks"
hexmask.long.byte 0x08 8.--15. 1. "TX_MAX_BLKS,Transmit FIFO maximum blocks"
newline
hexmask.long.byte 0x08 0.--7. 1. "RX_MAX_BLKS,Receive FIFO maximum blocks"
rgroup.long 0x22010++0x2B
line.long 0x00 "PN_BLK_CNT_REG,Enet Port N FIFO Block Usage Count"
bitfld.long 0x00 16.--21. "RX_BLK_CNT_P,Receive Prempt Queue Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--5. "RX_BLK_CNT_E,Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PN_PORT_VLAN_REG,Enet Port N VLAN"
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
newline
hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
line.long 0x08 "PN_TX_PRI_MAP_REG,Enet Port N Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x08 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x0C "PN_PRI_CTL_REG,Enet Port N Priority Control"
hexmask.long.byte 0x0C 24.--31. 1. "TX_FLOW_PRI,Transmit Priority Based Flow Control Enable (per priority)"
newline
hexmask.long.byte 0x0C 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
newline
bitfld.long 0x0C 12.--15. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "PN_RX_PRI_MAP_REG,Enet Port N RX Pkt Pri to Header Pri Map"
bitfld.long 0x10 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "PN_RX_MAXLEN_REG,Enet Port N Receive Frame Max Length"
hexmask.long.word 0x14 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length"
line.long 0x18 "PN_TX_BLKS_PRI_REG,Enet Port N Transmit Block Sub Per Priority"
bitfld.long 0x18 28.--31. "PRI7,Priority 7 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 24.--27. "PRI6,Priority 6 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 20.--23. "PRI5,Priority 5 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 16.--19. "PRI4,Priority 4 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 12.--15. "PRI3,Priority 3 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 8.--11. "PRI2,Priority 2 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 4.--7. "PRI1,Priority 1 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "PRI0,Priority 0 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "PN_RX_FLOW_THRESH_REG,Enet MAC Receive Flow Threshold in Receive Buffer Words"
hexmask.long.word 0x1C 0.--8. 1. "COUNT,Receive Flow Threshold in Words"
line.long 0x20 "PN_IDLE2LPI_REG,Enet Port N EEE Idle to LPI counter"
hexmask.long.tbyte 0x20 0.--23. 1. "COUNT,EEE Idle to LPI counter load value"
line.long 0x24 "PN_LPI2WAKE_REG,Enet Port N EEE LPI to wake counter"
hexmask.long.tbyte 0x24 0.--23. 1. "COUNT,EEE LPI to wake counter load value"
line.long 0x28 "PN_EEE_STATUS_REG,Enet Port N EEE status"
bitfld.long 0x28 6. "TX_FIFO_EMPTY,Transmit FIFO (switch egress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x28 5. "RX_FIFO_EMPTY,Receive FIFO (switch ingress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x28 4. "TX_FIFO_HOLD,Transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
newline
bitfld.long 0x28 3. "TX_WAKE,Transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
newline
bitfld.long 0x28 2. "TX_LPI,Transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
newline
bitfld.long 0x28 1. "RX_LPI,Receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
newline
bitfld.long 0x28 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
rgroup.long 0x22050++0x03
line.long 0x00 "PN_FIFO_STATUS_REG,Enet Port N FIFO STATUS"
bitfld.long 0x00 18. "EST_BUFACT,Transmit FIFO EST Buffer Active" "0,1"
newline
bitfld.long 0x00 17. "EST_ADD_ERR,Transmit FIFO EST Address Error" "0,1"
newline
bitfld.long 0x00 16. "EST_CNT_ERR,Transmit FIFO EST Count Error" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "TX_E_MAC_ALLOW,Transmit FIFO Express Queue Priority Allow"
newline
hexmask.long.byte 0x00 0.--7. 1. "TX_PRI_ACTIVE,Transmit FIFO Priority Active"
group.long 0x22060++0x03
line.long 0x00 "PN_EST_CONTROL_REG,Enet Port N EST CONTROL"
hexmask.long.word 0x00 16.--25. 1. "EST_FILL_MARGIN,Transmit FIFO EST Fill Margin"
newline
hexmask.long.byte 0x00 9.--15. 1. "EST_PREMPT_COMP,Transmit FIFO EST Prempt Comparision Value"
newline
bitfld.long 0x00 8. "EST_FILL_EN,Transmit FIFO EST Fill Enable" "0,1"
newline
bitfld.long 0x00 5.--7. "EST_TS_PRI,Transmit FIFO EST TimeStamp Priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "EST_TS_ONEPRI,Transmit FIFO EST TimeStamp One Priority" "0,1"
newline
bitfld.long 0x00 3. "EST_TS_FIRST,Transmit FIFO EST TimeStamp First Express Packet" "0,1"
newline
bitfld.long 0x00 2. "EST_TS_EN,Transmit FIFO EST TimeStamp Enable" "0,1"
newline
bitfld.long 0x00 1. "EST_BUFSEL,Transmit FIFO EST Buffer Select" "0,1"
newline
bitfld.long 0x00 0. "EST_ONEBUF,Transmit FIFO EST One Buffer" "0,1"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22120)++0x03
line.long 0x00 "PN_RX_DSCP_MAP_REG_$1,Enet Port N Receive IPV4/IPV6 DSCP Map M"
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22140)++0x03
line.long 0x00 "PN_PRI_CIR_REG_$1,Enet Port N Rx Priority P Committed Information Rate Value"
hexmask.long 0x00 0.--27. 1. "PRI_CIR,Priority N committed information rate"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22160)++0x03
line.long 0x00 "PN_PRI_EIR_REG_$1,Enet Port N Rx Priority P Excess Informatoin Rate Value"
hexmask.long 0x00 0.--27. 1. "PRI_EIR,Priority N Excess Information Rate count"
repeat.end
group.long 0x22180++0x1F
line.long 0x00 "PN_TX_D_THRESH_SET_L_REG,Enet Port N Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "PN_TX_D_THRESH_SET_H_REG,Enet Port N Tx PFC Destination Threshold Set High"
bitfld.long 0x04 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "PN_TX_D_THRESH_CLR_L_REG,Enet Port N Tx PFC Destination Threshold Clr Low"
bitfld.long 0x08 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "PN_TX_D_THRESH_CLR_H_REG,Enet Port N Tx PFC Destination Threshold Clr High"
bitfld.long 0x0C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "PN_TX_G_BUF_THRESH_SET_L_REG,Enet Port N Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x10 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "PN_TX_G_BUF_THRESH_SET_H_REG,Enet Port N Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x14 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "PN_TX_G_BUF_THRESH_CLR_L_REG,Enet Port N Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x18 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "PN_TX_G_BUF_THRESH_CLR_H_REG,Enet Port N Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x1C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22300++0x23
line.long 0x00 "PN_TX_D_OFLOW_ADDVAL_L_REG,Enet Port N Tx Destination Out Flow Add Values Low"
bitfld.long 0x00 24.--28. "PRI3,Port PFC Destination Based Out Flow Add Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PRI2,Port PFC Destination Based Out Flow Add Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "PRI1,Port PFC Destination Based Out Flow Add Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "PRI0,Port PFC Destination Based Out Flow Add Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "PN_TX_D_OFLOW_ADDVAL_H_REG,Enet Port N Tx Destination Out Flow Add Values High"
bitfld.long 0x04 24.--28. "PRI7,Port PFC Destination Based Out Flow Add Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 16.--20. "PRI6,Port PFC Destination Based Out Flow Add Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 8.--12. "PRI5,Port PFC Destination Based Out Flow Add Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--4. "PRI4,Port PFC Destination Based Out Flow Add Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "PN_SA_L_REG,Enet Port N Tx Pause Frame Source Address Low"
hexmask.long.byte 0x08 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits"
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hexmask.long.byte 0x08 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8"
line.long 0x0C "PN_SA_H_REG,Enet Port N Tx Pause Frame Source Address High"
hexmask.long.byte 0x0C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16"
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hexmask.long.byte 0x0C 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24"
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hexmask.long.byte 0x0C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32"
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hexmask.long.byte 0x0C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40"
line.long 0x10 "PN_TS_CTL_REG,Enet Port N Time Sync Control"
hexmask.long.word 0x10 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable"
newline
bitfld.long 0x10 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable" "0,1"
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bitfld.long 0x10 10. "TS_TX_ANNEX_E_EN,Time Synce Transmit Annex E Enable" "0,1"
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bitfld.long 0x10 9. "TS_RX_ANNEX_E_EN,Time Synce Receive Annex E Enable" "0,1"
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bitfld.long 0x10 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 enable transmit and receive" "0,1"
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bitfld.long 0x10 7. "TS_TX_ANNEX_D_EN,Time Synce Transmit Annex D Enable" "0,1"
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bitfld.long 0x10 6. "TS_TX_VLAN_LTYPE2_E,Time Sync Transmit VLAN LTYPE 2 enable" "0,1"
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bitfld.long 0x10 5. "TS_TX_VLAN_LTYPE1_E,Time Sync Transmit VLAN LTYPE 1 enable" "0,1"
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bitfld.long 0x10 4. "TS_TX_ANNEX_F_EN,Time Synce Transmit Annex F Enable" "0,1"
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bitfld.long 0x10 3. "TS_RX_ANNEX_D_EN,Time Synce Receive Annex D Enable" "0,1"
newline
bitfld.long 0x10 2. "TS_RX_VLAN_LTYPE2_E,Time Sync Receive VLAN LTYPE 2 enable" "0,1"
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bitfld.long 0x10 1. "TS_RX_VLAN_LTYPE1_E,Time Sync Receive VLAN LTYPE 1 enable" "0,1"
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bitfld.long 0x10 0. "TS_RX_ANNEX_F_EN,Time Synce Receive Annex F Enable" "0,1"
line.long 0x14 "PN_TS_SEQ_LTYPE_REG,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)"
bitfld.long 0x14 16.--21. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1"
line.long 0x18 "PN_TS_VLAN_LTYPE_REG,Enet Port N Time Sync VLAN2 and VLAN2"
hexmask.long.word 0x18 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2"
newline
hexmask.long.word 0x18 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1"
line.long 0x1C "PN_TS_CTL_LTYPE2_REG,Enet Port N Time Sync Control and LTYPE 2"
bitfld.long 0x1C 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1"
newline
bitfld.long 0x1C 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1"
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bitfld.long 0x1C 22. "TS_320,Time Sync Destination IP Address 320 Enable" "0,1"
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bitfld.long 0x1C 21. "TS_319,Time Sync Destination IP Address 319 Enable" "0,1"
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bitfld.long 0x1C 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1"
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bitfld.long 0x1C 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1"
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bitfld.long 0x1C 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1"
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bitfld.long 0x1C 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1"
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bitfld.long 0x1C 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1"
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hexmask.long.word 0x1C 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2"
line.long 0x20 "PN_TS_CTL2_REG,Enet Port N Time Sync Control 2"
bitfld.long 0x20 16.--21. "TS_DOMAIN_OFFSET,Time Sync Domain Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x20 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable"
group.long 0x22330++0x13
line.long 0x00 "PN_MAC_CONTROL_REG,Enet Port N Mac Control"
bitfld.long 0x00 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable" "0,1"
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bitfld.long 0x00 23. "RX_CSF_EN,RX Copy Short Frames Enable" "0,1"
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bitfld.long 0x00 22. "RX_CEF_EN,RX Copy Error Frames Enable" "0,1"
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bitfld.long 0x00 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable" "0,1"
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bitfld.long 0x00 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
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bitfld.long 0x00 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable" "0,1"
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bitfld.long 0x00 18. "EXT_EN,External Enable" "0,1"
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bitfld.long 0x00 17. "GIG_FORCE,Gigabit Mode Force" "0,1"
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bitfld.long 0x00 16. "IFCTL_B,Interface Control B" "0,1"
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bitfld.long 0x00 15. "IFCTL_A,Interface Control A" "0,1"
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bitfld.long 0x00 12. "CRC_TYPE,Port CRC Type" "0,1"
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bitfld.long 0x00 11. "CMD_IDLE,Command Idle" "0,1"
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bitfld.long 0x00 10. "TX_SHORT_GAP_ENABLE,Transmit Short Gap Enable" "0,1"
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bitfld.long 0x00 7. "GIG,Gigabit Mode" "0,1"
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bitfld.long 0x00 6. "TX_PACE,Transmit Pacing Enable" "0,1"
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bitfld.long 0x00 5. "GMII_EN,GMII Enable" "0,1"
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bitfld.long 0x00 4. "TX_FLOW_EN,Transmit Flow Control Enable" "0,1"
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bitfld.long 0x00 3. "RX_FLOW_EN,Receive Flow Control Enable" "0,1"
newline
bitfld.long 0x00 2. "MTEST,Manufacturing Test Mode" "0,1"
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bitfld.long 0x00 1. "LOOPBACK,Loop Back Mode" "0,1"
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bitfld.long 0x00 0. "FULLDUPLEX,Full Duplex mode" "0,1"
line.long 0x04 "PN_MAC_STATUS_REG,Enet Port N Mac Status"
bitfld.long 0x04 31. "IDLE,cpxmac_sl IDLE" "0,1"
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bitfld.long 0x04 30. "E_IDLE,Express cpxmac_sl IDLE" "0,1"
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bitfld.long 0x04 28. "MAC_TX_IDLE,Prempt and Express cpxmac_sl Transmit IDLE" "0,1"
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bitfld.long 0x04 27. "TORF,Top of receive FIFO flow control trigger occurred" "0,1"
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bitfld.long 0x04 24.--26. "TORF_PRI,The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x04 16.--23. 1. "TX_PFC_FLOW_ACT,Transmit Priority Based Flow Control Active (priority 7 down to 0)"
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hexmask.long.byte 0x04 8.--15. 1. "RX_PFC_FLOW_ACT,Receive Priority Based Flow Control Active (priority 7 down to 0)"
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bitfld.long 0x04 6. "EXT_RX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
newline
bitfld.long 0x04 5. "EXT_TX_FLOW_EN,External Receive Flow Control Enable" "0,1"
newline
bitfld.long 0x04 4. "EXT_GIG,External GIG mode" "0,1"
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bitfld.long 0x04 3. "EXT_FULLDUPLEX,External Fullduplex" "0,1"
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bitfld.long 0x04 1. "RX_FLOW_ACT,Receive Flow Control Active" "0,1"
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bitfld.long 0x04 0. "TX_FLOW_ACT,Transmit Flow Control Active" "0,1"
line.long 0x08 "PN_MAC_SOFT_RESET_REG,Enet Port N Mac Soft Reset"
bitfld.long 0x08 0. "SOFT_RESET,Software reset" "0,1"
line.long 0x0C "PN_MAC_BOFFTEST_REG,Enet Port N Mac Backoff Test"
bitfld.long 0x0C 26.--30. "PACEVAL,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x0C 16.--25. 1. "RNDNUM,Backoff Random Number Generator"
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rbitfld.long 0x0C 12.--15. "COLL_COUNT,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x0C 0.--9. 1. "TX_BACKOFF,Backoff Count"
line.long 0x10 "PN_MAC_RX_PAUSETIMER_REG,Enet Port N 802.3 Receive Pause Timer"
hexmask.long.word 0x10 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22350)++0x03
line.long 0x00 "PN_MAC_RXN_PAUSETIMER_REG_$1,Enet Port N PFC Priority P Rx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value"
repeat.end
group.long 0x22370++0x03
line.long 0x00 "PN_MAC_TX_PAUSETIMER_REG,Enet Port N 802.3 Tx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22380)++0x03
line.long 0x00 "PN_MAC_TXN_PAUSETIMER_REG_$1,Enet Port N PFC Priority P Tx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value"
repeat.end
group.long 0x223A0++0x07
line.long 0x00 "PN_MAC_EMCONTROL_REG,Enet Port N Emulation Control"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
newline
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "PN_MAC_TX_GAP_REG,Enet Port N Tx Inter Packet Gap"
hexmask.long.word 0x04 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap"
group.long 0x223AC++0x13
line.long 0x00 "PN_INTERVLAN_OPX_POINTER_REG,Enet Port N Tx Egress InterVLAN Operation Pointer"
bitfld.long 0x00 0.--2. "PN_INTERVLAN_OPX_POINTER_REG,Egress InterVLAN Operation Pointer" "0,1,2,3,4,5,6,7"
line.long 0x04 "PN_INTERVLAN_OPX_A_REG,Enet Port N Tx Egress InterVLAN A"
line.long 0x08 "PN_INTERVLAN_OPX_B_REG,Enet Port N Tx Egress InterVLAN B"
line.long 0x0C "PN_INTERVLAN_OPX_C_REG,Enet Port N Tx Egress InterVLAN C"
line.long 0x10 "PN_INTERVLAN_OPX_D_REG,Enet Port N Tx Egress InterVLAN D"
hexmask.long.word 0x10 0.--15. 1. "INTERVLAN_OPX_D,Egress InterVLAN D"
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
rgroup.long 0x34000++0x0B
line.long 0x00 "CPDMA_FH_IDVER_REG,CPDMA Transmit IDVER"
line.long 0x04 "CPDMA_FH_CONTROL_REG,CPDMA Transmit Control Register"
bitfld.long 0x04 0. "FH_EN,CPDMA Transmit DMA Enable" "0,1"
line.long 0x08 "CPDMA_FH_TEARDOWN_REG,CPDMA Transmit Teardown Register"
bitfld.long 0x08 31. "FH_TDN_RDY,CPDMA Transmit Teardown Ready" "0,1"
newline
bitfld.long 0x08 0.--2. "FH_TDN_CH,CPDMA Transmit Teardown Channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x34010++0x1F
line.long 0x00 "CPDMA_TH_IDVER_REG,CPDMA Receive IDVER"
line.long 0x04 "CPDMA_TH_CONTROL_REG,CPDMA Receive Control Register"
bitfld.long 0x04 0. "TH_EN,CPDMA Receive DMA Enable" "0,1"
line.long 0x08 "CPDMA_TH_TEARDOWN_REG,CPDMA Receive Teardown Register"
bitfld.long 0x08 31. "TH_TDN_RDY,CPDMA Receive Teardown Ready" "0,1"
newline
bitfld.long 0x08 0.--2. "TH_TDN_CH,CPDMA Receive Teardown Channel" "0,1,2,3,4,5,6,7"
line.long 0x0C "CPDMA_SOFT_RESET_REG,CPDMA Soft Reset Register"
bitfld.long 0x0C 0. "SOFT_RESET,CPDMA and CPSW Soft Reset Enable" "0,1"
line.long 0x10 "CPDMA_CONTROL_REG,CPDMA Control Register"
bitfld.long 0x10 6. "TH_TS_ENCAP,CPDMA Receive TimeStamp Encapsulated" "0,1"
newline
bitfld.long 0x10 5. "TH_VLAN_ENCAP,CPDMA Receive VLAN Encapsulated" "0,1"
newline
bitfld.long 0x10 4. "TH_CEF,CPDMA Receive Copy Error Frames" "0,1"
newline
bitfld.long 0x10 3. "CMD_IDLE,CPDMA Command Idle" "0,1"
newline
bitfld.long 0x10 2. "TH_OFFLEN_BLOCK,CPDMA Receive Offset/Length Word Write Block" "0,1"
newline
bitfld.long 0x10 1. "TH_OWNERSHIP,CPDMA Receive Ownership Write Bit Value" "0,1"
newline
bitfld.long 0x10 0. "FH_PTYPE,CPDMA Transmit Queue Priority Type" "0,1"
line.long 0x14 "CPDMA_STATUS_REG,CPDMA Status Register"
bitfld.long 0x14 31. "IDLE,CPDMA Transmit Host Error Code" "0,1"
newline
bitfld.long 0x14 20.--23. "FH_HOST_ERROR_CODE,CPDMA Transmit Host Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 16.--18. "FH_ERR_CH,CPDMA Transmit Error Channel Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 12.--15. "TH_HOST_ERROR_CODE,CPDMA Receive Host Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 8.--10. "TH_ERR_CH,CPDMA Receive Error Channel Number" "0,1,2,3,4,5,6,7"
line.long 0x18 "CPDMA_TH_BUFFER_OFFSET_REG,CPDMA Receive Buffer Offset Register"
hexmask.long.word 0x18 0.--10. 1. "TH_BUFFER_OFFSET,CPDMA Receive Buffer Offset Register"
line.long 0x1C "CPDMA_EMULATION_CONTROL_REG,CPDMA Receive Buffer Offset Register"
bitfld.long 0x1C 1. "FREE,CPDMA Receive Buffer Offset Register" "0,1"
newline
bitfld.long 0x1C 0. "SOFT,CPDMA Receive Buffer Offset Register" "0,1"
rgroup.long 0x34080++0x17
line.long 0x00 "CPDMA_FH_INTSTAT_RAW_REG,CPDMA FHost Interrupt Status RAW"
bitfld.long 0x00 7. "FH7_PEND_RAW,CPDMA FHost Channel 7 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 6. "FH6_PEND_RAW,CPDMA FHost Channel 6 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 5. "FH5_PEND_RAW,CPDMA FHost Channel 5 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 4. "FH4_PEND_RAW,CPDMA FHost Channel 4 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 3. "FH3_PEND_RAW,CPDMA FHost Channel 3 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 2. "FH2_PEND_RAW,CPDMA FHost Channel 2 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 1. "FH1_PEND_RAW,CPDMA FHost Channel 1 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 0. "FH0_PEND_RAW,CPDMA FHost Channel 0 Interrupt Pending RAW" "0,1"
line.long 0x04 "CPDMA_FH_INTSTAT_MASKED_REG,CPDMA FHost Interrupt Status MASKED"
bitfld.long 0x04 7. "FH7_PEND_MASKED,CPDMA FHost Channel 7 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 6. "FH6_PEND_MASKED,CPDMA FHost Channel 6 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 5. "FH5_PEND_MASKED,CPDMA FHost Channel 5 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 4. "FH4_PEND_MASKED,CPDMA FHost Channel 4 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 3. "FH3_PEND_MASKED,CPDMA FHost Channel 3 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 2. "FH2_PEND_MASKED,CPDMA FHost Channel 2 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 1. "FH1_PEND_MASKED,CPDMA FHost Channel 1 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 0. "FH0_PEND_MASKED,CPDMA FHost Channel 0 Interrupt Pending MASKED" "0,1"
line.long 0x08 "CPDMA_FH_INTSTAT_MASKED_SET_REG,CPDMA FHost Interrupt Masked SET"
bitfld.long 0x08 7. "FH7_PEND_MASKED_SET,CPDMA FHost Channel 7 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 6. "FH6_PEND_MASKED_SET,CPDMA FHost Channel 6 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 5. "FH5_PEND_MASKED_SET,CPDMA FHost Channel 5 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 4. "FH4_PEND_MASKED_SET,CPDMA FHost Channel 4 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 3. "FH3_PEND_MASKED_SET,CPDMA FHost Channel 3 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 2. "FH2_PEND_MASKED_SET,CPDMA FHost Channel 2 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 1. "FH1_PEND_MASKED_SET,CPDMA FHost Channel 1 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 0. "FH0_PEND_MASKED_SET,CPDMA FHost Channel 0 Interrupt Pending MASKED Set" "0,1"
line.long 0x0C "CPDMA_FH_INTSTAT_MASKED_CLR_REG,CPDMA FHost Interrupt Masked CLR"
bitfld.long 0x0C 7. "FH7_PEND_MASKED_CLR,CPDMA FHost Channel 7 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 6. "FH6_PEND_MASKED_CLR,CPDMA FHost Channel 6 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 5. "FH5_PEND_MASKED_CLR,CPDMA FHost Channel 5 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 4. "FH4_PEND_MASKED_CLR,CPDMA FHost Channel 4 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 3. "FH3_PEND_MASKED_CLR,CPDMA FHost Channel 3 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 2. "FH2_PEND_MASKED_CLR,CPDMA FHost Channel 2 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 1. "FH1_PEND_MASKED_CLR,CPDMA FHost Channel 1 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 0. "FH0_PEND_MASKED_CLR,CPDMA FHost Channel 0 Interrupt Pending MASKED Clr" "0,1"
line.long 0x10 "CPDMA_IN_VECTOR_REG,CPDMA DMA IN Vector"
line.long 0x14 "CPDMA_EOI_VECTOR_REG,CPDMA DMA EOI Vector"
bitfld.long 0x14 0.--4. "DMA_EOI_VECTOR,CPDMA DMA EOI Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x340A0++0x5F
line.long 0x00 "CPDMA_TH_INTSTAT_RAW_REG,CPDMA Receive Interrupt Status RAW"
bitfld.long 0x00 15. "TH7_THRESH_PEND_RAW,CPDMA Receive Channel 7 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 14. "TH6_THRESH_PEND_RAW,CPDMA Receive Channel 6 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 13. "TH5_THRESH_PEND_RAW,CPDMA Receive Channel 5 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 12. "TH4_THRESH_PEND_RAW,CPDMA Receive Channel 4 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 11. "TH3_THRESH_PEND_RAW,CPDMA Receive Channel 3 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 10. "TH2_THRESH_PEND_RAW,CPDMA Receive Channel 2 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 9. "TH1_THRESH_PEND_RAW,CPDMA Receive Channel 1 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 8. "TH0_THRESH_PEND_RAW,CPDMA Receive Channel 0 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 7. "TH7_PEND_RAW,CPDMA Receive Channel 7 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 6. "TH6_PEND_RAW,CPDMA Receive Channel 6 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 5. "TH5_PEND_RAW,CPDMA Receive Channel 5 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 4. "TH4_PEND_RAW,CPDMA Receive Channel 4 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 3. "TH3_PEND_RAW,CPDMA Receive Channel 3 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 2. "TH2_PEND_RAW,CPDMA Receive Channel 2 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 1. "TH1_PEND_RAW,CPDMA Receive Channel 1 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 0. "TH0_PEND_RAW,CPDMA Receive Channel 0 Interrupt Pending RAW" "0,1"
line.long 0x04 "CPDMA_TH_INTSTAT_MASKED_REG,CPDMA Receive Interrupt Status MASKED"
bitfld.long 0x04 15. "TH7_THRESH_PEND_MASKED,CPDMA Receive Channel 7 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 14. "TH6_THRESH_PEND_MASKED,CPDMA Receive Channel 6 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 13. "TH5_THRESH_PEND_MASKED,CPDMA Receive Channel 5 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 12. "TH4_THRESH_PEND_MASKED,CPDMA Receive Channel 4 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 11. "TH3_THRESH_PEND_MASKED,CPDMA Receive Channel 3 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 10. "TH2_THRESH_PEND_MASKED,CPDMA Receive Channel 2 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 9. "TH1_THRESH_PEND_MASKED,CPDMA Receive Channel 1 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 8. "TH0_THRESH_PEND_MASKED,CPDMA Receive Channel 0 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 7. "TH7_PEND_MASKED,CPDMA Receive Channel 7 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 6. "TH6_PEND_MASKED,CPDMA Receive Channel 6 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 5. "TH5_PEND_MASKED,CPDMA Receive Channel 5 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 4. "TH4_PEND_MASKED,CPDMA Receive Channel 4 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 3. "TH3_PEND_MASKED,CPDMA Receive Channel 3 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 2. "TH2_PEND_MASKED,CPDMA Receive Channel 2 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 1. "TH1_PEND_MASKED,CPDMA Receive Channel 1 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 0. "TH0_PEND_MASKED,CPDMA Receive Channel 0 Interrupt Pending MASKED" "0,1"
line.long 0x08 "CPDMA_TH_INTSTAT_SET_REG,CPDMA THost Interrupt Masked SET"
bitfld.long 0x08 15. "TH7_THRESH_PEND_MASKED_SET,CPDMA THost Channel 7 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 14. "TH6_THRESH_PEND_MASKED_SET,CPDMA THost Channel 6 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 13. "TH5_THRESH_PEND_MASKED_SET,CPDMA THost Channel 5 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 12. "TH4_THRESH_PEND_MASKED_SET,CPDMA THost Channel 4 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 11. "TH3_THRESH_PEND_MASKED_SET,CPDMA THost Channel 3 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 10. "TH2_THRESH_PEND_MASKED_SET,CPDMA THost Channel 2 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 9. "TH1_THRESH_PEND_MASKED_SET,CPDMA THost Channel 1 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 8. "TH0_THRESH_PEND_MASKED_SET,CPDMA THost Channel 0 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 7. "TH7_PEND_MASKED_SET,CPDMA THost Channel 7 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 6. "TH6_PEND_MASKED_SET,CPDMA THost Channel 6 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 5. "TH5_PEND_MASKED_SET,CPDMA THost Channel 5 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 4. "TH4_PEND_MASKED_SET,CPDMA THost Channel 4 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 3. "TH3_PEND_MASKED_SET,CPDMA THost Channel 3 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 2. "TH2_PEND_MASKED_SET,CPDMA THost Channel 2 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 1. "TH1_PEND_MASKED_SET,CPDMA THost Channel 1 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 0. "TH0_PEND_MASKED_SET,CPDMA THost Channel 0 Interrupt Pending SET" "0,1"
line.long 0x0C "CPDMA_TH_INTSTAT_CLR_REG,CPDMA THost Interrupt Masked CLR"
bitfld.long 0x0C 15. "TH7_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 7 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 14. "TH6_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 6 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 13. "TH5_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 5 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 12. "TH4_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 4 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 11. "TH3_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 3 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 10. "TH2_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 2 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 9. "TH1_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 1 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 8. "TH0_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 0 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 7. "TH7_PEND_MASKED_CLR,CPDMA THost Channel 7 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 6. "TH6_PEND_MASKED_CLR,CPDMA THost Channel 6 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 5. "TH5_PEND_MASKED_CLR,CPDMA THost Channel 5 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 4. "TH4_PEND_MASKED_CLR,CPDMA THost Channel 4 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 3. "TH3_PEND_MASKED_CLR,CPDMA THost Channel 3 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 2. "TH2_PEND_MASKED_CLR,CPDMA THost Channel 2 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 1. "TH1_PEND_MASKED_CLR,CPDMA THost Channel 1 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 0. "TH0_PEND_MASKED_CLR,CPDMA THost Channel 0 Interrupt Pending CLR" "0,1"
line.long 0x10 "CPDMA_INTSTAT_RAW_REG,CPDMA DMA Interrupt Status RAW"
bitfld.long 0x10 1. "HOST_PEND_RAW,CPDMA HOST Interrupt Pending RAW" "0,1"
line.long 0x14 "CPDMA_INTSTAT_MASKED_REG,CPDMA DMA Interrupt Status MASKED"
bitfld.long 0x14 1. "HOST_PEND,CPDMA HOST Interrupt Pending MASKED" "0,1"
line.long 0x18 "CPDMA_INTSTAT_SET_REG,CPDMA DMA Interrupt Status SET"
bitfld.long 0x18 1. "HOST_PEND_MASKED_SET,CPDMA HOST Interrupt Masked SET" "0,1"
line.long 0x1C "CPDMA_INTSTAT_CLR_REG,CPDMA DMA Interrupt Status CLR"
bitfld.long 0x1C 1. "HOST_PEND_MASKED_CLR,CPDMA HOST Interrupt Masked CLR" "0,1"
line.long 0x20 "CPDMA_TH0_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x20 0.--7. 1. "TH0_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x24 "CPDMA_TH1_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x24 0.--7. 1. "TH1_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x28 "CPDMA_TH2_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x28 0.--7. 1. "TH2_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x2C "CPDMA_TH3_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x2C 0.--7. 1. "TH3_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x30 "CPDMA_TH4_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x30 0.--7. 1. "TH4_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x34 "CPDMA_TH5_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x34 0.--7. 1. "TH5_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x38 "CPDMA_TH6_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x38 0.--7. 1. "TH6_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x3C "CPDMA_TH7_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x3C 0.--7. 1. "TH7_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x40 "CPDMA_TH0_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x40 0.--14. 1. "TH0_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x44 "CPDMA_TH1_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x44 0.--14. 1. "TH1_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x48 "CPDMA_TH2_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x48 0.--14. 1. "TH2_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x4C "CPDMA_TH3_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x4C 0.--14. 1. "TH3_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x50 "CPDMA_TH4_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x50 0.--14. 1. "TH4_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x54 "CPDMA_TH5_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x54 0.--14. 1. "TH5_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x58 "CPDMA_TH6_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x58 0.--14. 1. "TH6_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x5C "CPDMA_TH7_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x5C 0.--14. 1. "TH7_FREEBUFFER,CPDMA THost Free Buffer Count Register"
group.long 0x34200++0x7F
line.long 0x00 "CPDMA_FH0_HDP_REG,CPDMA FHost Channel 0 Head Descriptor Pointer"
line.long 0x04 "CPDMA_FH1_HDP_REG,CPDMA FHost Channel 1 Head Descriptor Pointer"
line.long 0x08 "CPDMA_FH2_HDP_REG,CPDMA FHost Channel 2 Head Descriptor Pointer"
line.long 0x0C "CPDMA_FH3_HDP_REG,CPDMA FHost Channel 3 Head Descriptor Pointer"
line.long 0x10 "CPDMA_FH4_HDP_REG,CPDMA FHost Channel 4 Head Descriptor Pointer"
line.long 0x14 "CPDMA_FH5_HDP_REG,CPDMA FHost Channel 5 Head Descriptor Pointer"
line.long 0x18 "CPDMA_FH6_HDP_REG,CPDMA FHost Channel 6 Head Descriptor Pointer"
line.long 0x1C "CPDMA_FH7_HDP_REG,CPDMA FHost Channel 7 Head Descriptor Pointer"
line.long 0x20 "CPDMA_TH0_HDP_REG,CPDMA THost Channel 0 Head Descriptor Pointer"
line.long 0x24 "CPDMA_TH1_HDP_REG,CPDMA THost Channel 1 Head Descriptor Pointer"
line.long 0x28 "CPDMA_TH2_HDP_REG,CPDMA THost Channel 2 Head Descriptor Pointer"
line.long 0x2C "CPDMA_TH3_HDP_REG,CPDMA THost Channel 3 Head Descriptor Pointer"
line.long 0x30 "CPDMA_TH4_HDP_REG,CPDMA THost Channel 4 Head Descriptor Pointer"
line.long 0x34 "CPDMA_TH5_HDP_REG,CPDMA THost Channel 5 Head Descriptor Pointer"
line.long 0x38 "CPDMA_TH6_HDP_REG,CPDMA THost Channel 6 Head Descriptor Pointer"
line.long 0x3C "CPDMA_TH7_HDP_REG,CPDMA THost Channel 7 Head Descriptor Pointer"
line.long 0x40 "CPDMA_FH0_CP_REG,CPDMA FHost Channel 0 Completion Pointer"
line.long 0x44 "CPDMA_FH1_CP_REG,CPDMA FHost Channel 1 Completion Pointer"
line.long 0x48 "CPDMA_FH2_CP_REG,CPDMA FHost Channel 2 Completion Pointer"
line.long 0x4C "CPDMA_FH3_CP_REG,CPDMA FHost Channel 3 Completion Pointer"
line.long 0x50 "CPDMA_FH4_CP_REG,CPDMA FHost Channel 4 Completion Pointer"
line.long 0x54 "CPDMA_FH5_CP_REG,CPDMA FHost Channel 5 Completion Pointer"
line.long 0x58 "CPDMA_FH6_CP_REG,CPDMA FHost Channel 6 Completion Pointer"
line.long 0x5C "CPDMA_FH7_CP_REG,CPDMA FHost Channel 7 Completion Pointer"
line.long 0x60 "CPDMA_TH0_CP_REG,CPDMA THost Channel 0 Completion Pointer"
line.long 0x64 "CPDMA_TH1_CP_REG,CPDMA THost Channel 1 Completion Pointer"
line.long 0x68 "CPDMA_TH2_CP_REG,CPDMA THost Channel 2 Completion Pointer"
line.long 0x6C "CPDMA_TH3_CP_REG,CPDMA THost Channel 3 Completion Pointer"
line.long 0x70 "CPDMA_TH4_CP_REG,CPDMA THost Channel 4 Completion Pointer"
line.long 0x74 "CPDMA_TH5_CP_REG,CPDMA THost Channel 5 Completion Pointer"
line.long 0x78 "CPDMA_TH6_CP_REG,CPDMA THost Channel 6 Completion Pointer"
line.long 0x7C "CPDMA_TH7_CP_REG,CPDMA THost Channel 7 Completion Pointer"
group.long 0x34300++0x7F
line.long 0x00 "TEST_CPDMA_FH0_HDP_REG,Test CPDMA FHost Channel 0 Head Descriptor Pointer"
line.long 0x04 "TEST_CPDMA_FH1_HDP_REG,Test CPDMA FHost Channel 1 Head Descriptor Pointer"
line.long 0x08 "TEST_CPDMA_FH2_HDP_REG,Test CPDMA FHost Channel 2 Head Descriptor Pointer"
line.long 0x0C "TEST_CPDMA_FH3_HDP_REG,Test CPDMA FHost Channel 3 Head Descriptor Pointer"
line.long 0x10 "TEST_CPDMA_FH4_HDP_REG,Test CPDMA FHost Channel 4 Head Descriptor Pointer"
line.long 0x14 "TEST_CPDMA_FH5_HDP_REG,Test CPDMA FHost Channel 5 Head Descriptor Pointer"
line.long 0x18 "TEST_CPDMA_FH6_HDP_REG,Test CPDMA FHost Channel 6 Head Descriptor Pointer"
line.long 0x1C "TEST_CPDMA_FH7_HDP_REG,Test CPDMA FHost Channel 7 Head Descriptor Pointer"
line.long 0x20 "TEST_CPDMA_TH0_HDP_REG,Test CPDMA THost Channel 0 Head Descriptor Pointer"
line.long 0x24 "TEST_CPDMA_TH1_HDP_REG,Test CPDMA THost Channel 1 Head Descriptor Pointer"
line.long 0x28 "TEST_CPDMA_TH2_HDP_REG,Test CPDMA THost Channel 2 Head Descriptor Pointer"
line.long 0x2C "TEST_CPDMA_TH3_HDP_REG,Test CPDMA THost Channel 3 Head Descriptor Pointer"
line.long 0x30 "TEST_CPDMA_TH4_HDP_REG,Test CPDMA THost Channel 4 Head Descriptor Pointer"
line.long 0x34 "TEST_CPDMA_TH5_HDP_REG,Test CPDMA THost Channel 5 Head Descriptor Pointer"
line.long 0x38 "TEST_CPDMA_TH6_HDP_REG,Test CPDMA THost Channel 6 Head Descriptor Pointer"
line.long 0x3C "TEST_CPDMA_TH7_HDP_REG,Test CPDMA THost Channel 7 Head Descriptor Pointer"
line.long 0x40 "TEST_CPDMA_FH0_CP_REG,Test CPDMA FHost Channel 0 Completion Pointer"
line.long 0x44 "TEST_CPDMA_FH1_CP_REG,Test CPDMA FHost Channel 1 Completion Pointer"
line.long 0x48 "TEST_CPDMA_FH2_CP_REG,Test CPDMA FHost Channel 2 Completion Pointer"
line.long 0x4C "TEST_CPDMA_FH3_CP_REG,Test CPDMA FHost Channel 3 Completion Pointer"
line.long 0x50 "TEST_CPDMA_FH4_CP_REG,Test CPDMA FHost Channel 4 Completion Pointer"
line.long 0x54 "TEST_CPDMA_FH5_CP_REG,Test CPDMA FHost Channel 5 Completion Pointer"
line.long 0x58 "TEST_CPDMA_FH6_CP_REG,Test CPDMA FHost Channel 6 Completion Pointer"
line.long 0x5C "TEST_CPDMA_FH7_CP_REG,Test CPDMA FHost Channel 7 Completion Pointer"
line.long 0x60 "TEST_CPDMA_TH0_CP_REG,Test CPDMA THost Channel 0 Completion Pointer"
line.long 0x64 "TEST_CPDMA_TH1_CP_REG,Test CPDMA THost Channel 1 Completion Pointer"
line.long 0x68 "TEST_CPDMA_TH2_CP_REG,Test CPDMA THost Channel 2 Completion Pointer"
line.long 0x6C "TEST_CPDMA_TH3_CP_REG,Test CPDMA THost Channel 3 Completion Pointer"
line.long 0x70 "TEST_CPDMA_TH4_CP_REG,Test CPDMA THost Channel 4 Completion Pointer"
line.long 0x74 "TEST_CPDMA_TH5_CP_REG,Test CPDMA THost Channel 5 Completion Pointer"
line.long 0x78 "TEST_CPDMA_TH6_CP_REG,Test CPDMA THost Channel 6 Completion Pointer"
line.long 0x7C "TEST_CPDMA_TH7_CP_REG,Test CPDMA THost Channel 7 Completion Pointer"
group.long 0x3A000++0x0B
line.long 0x00 "RXGOODFRAMES,Total number of good frames received"
line.long 0x04 "RXBROADCASTFRAMES,Total number of good broadcast frames received"
line.long 0x08 "RXMULTICASTFRAMES,Total number of good multicast frames received"
group.long 0x3A010++0x03
line.long 0x00 "RXCRCERRORS,Total number of CRC errors frames received"
group.long 0x3A018++0x03
line.long 0x00 "RXOVERSIZEDFRAMES,Total number of oversized frames received"
group.long 0x3A020++0x1F
line.long 0x00 "RXUNDERSIZEDFRAMES,Total number of undersized frames received"
line.long 0x04 "RXFRAGMENTS,Total number of fragmented frames received"
line.long 0x08 "ALE_DROP,Total number of frames dropped by the ALE"
line.long 0x0C "ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
line.long 0x10 "RXOCTETS,Total number of received bytes in good frames"
line.long 0x14 "TXGOODFRAMES,Total number of good frames transmitted"
line.long 0x18 "TXBROADCASTFRAMES,Total number of good broadcast frames transmitted"
line.long 0x1C "TXMULTICASTFRAMES,Total number of good multicast frames transmitted"
group.long 0x3A04C++0x07
line.long 0x00 "TXSINGLECOLLFRAMES,Total number of transmitted frames experiencing a single collision"
line.long 0x04 "TXMULTCOLLFRAMES,Total number of transmitted frames experiencing multiple collisions"
group.long 0x3A064++0x7B
line.long 0x00 "TXOCTETS,Total number of bytes in all good frames transmitted"
line.long 0x04 "OCTETFRAMES64,Total number of 64-byte frames received and transmitted"
line.long 0x08 "OCTETFRAMES65T127,Total number of frames of size 65 to 127 bytes received and transmitted"
line.long 0x0C "OCTETFRAMES128T255,Total number of frames of size 128 to 255 bytes received and transmitted"
line.long 0x10 "OCTETFRAMES256T511,Total number of frames of size 256 to 511 bytes received and transmitted"
line.long 0x14 "OCTETFRAMES512T1023,Total number of frames of size 512 to 1023 bytes received and transmitted"
line.long 0x18 "OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
line.long 0x1C "NETOCTETS,Total number of bytes received and transmitted"
line.long 0x20 "RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop"
line.long 0x24 "PORTMASK_DROP,Total number of dropped frames received due to portmask"
line.long 0x28 "RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop"
line.long 0x2C "ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting"
line.long 0x30 "ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress"
line.long 0x34 "ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA"
line.long 0x38 "ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode"
line.long 0x3C "ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode"
line.long 0x40 "ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication"
line.long 0x44 "ALE_UNKN_UNI,ALE Receive Unknown Unicast"
line.long 0x48 "ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount"
line.long 0x4C "ALE_UNKN_MLT,ALE Receive Unknown Multicast"
line.long 0x50 "ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount"
line.long 0x54 "ALE_UNKN_BRD,ALE Receive Unknown Broadcast"
line.long 0x58 "ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount"
line.long 0x5C "ALE_POL_MATCH,ALE Policer Matched"
line.long 0x60 "ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red"
line.long 0x64 "ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow"
line.long 0x68 "ALE_MULT_SA_DROP,ALE Multicast Source Address Drop"
line.long 0x6C "ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop"
line.long 0x70 "ALE_LEN_ERROR_DROP,ALE Length Error Drop"
line.long 0x74 "ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop"
line.long 0x78 "ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop"
group.long 0x3A17C++0x03
line.long 0x00 "TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error"
group.long 0x3A200++0xDF
line.long 0x00 "RXGOODFRAMES,Total number of good frames received"
line.long 0x04 "RXBROADCASTFRAMES,Total number of good broadcast frames received"
line.long 0x08 "RXMULTICASTFRAMES,Total number of good multicast frames received"
line.long 0x0C "RXPAUSEFRAMES,Total number of pause frames received"
line.long 0x10 "RXCRCERRORS,Total number of CRC errors frames received"
line.long 0x14 "RXALIGNCODEERRORS,Total number of alignment/code errors received"
line.long 0x18 "RXOVERSIZEDFRAMES,Total number of oversized frames received"
line.long 0x1C "RXJABBERFRAMES,Total number of jabber frames received"
line.long 0x20 "RXUNDERSIZEDFRAMES,Total number of undersized frames received"
line.long 0x24 "RXFRAGMENTS,Total number of fragmented frames received"
line.long 0x28 "ALE_DROP,Total number of frames dropped by the ALE"
line.long 0x2C "ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
line.long 0x30 "RXOCTETS,Total number of received bytes in good frames"
line.long 0x34 "TXGOODFRAMES,Total number of good frames transmitted"
line.long 0x38 "TXBROADCASTFRAMES,Total number of good broadcast frames transmitted"
line.long 0x3C "TXMULTICASTFRAMES,Total number of good multicast frames transmitted"
line.long 0x40 "TXPAUSEFRAMES,Total number of pause frames transmitted"
line.long 0x44 "TXDEFERREDFRAMES,Total number of deferred frames transmitted"
line.long 0x48 "TXCOLLISIONFRAMES,Total number of transmitted frames experiencing a collision"
line.long 0x4C "TXSINGLECOLLFRAMES,Total number of transmitted frames experiencing a single collision"
line.long 0x50 "TXMULTCOLLFRAMES,Total number of transmitted frames experiencing multiple collisions"
line.long 0x54 "TXEXCESSIVECOLLISIONS,Total number of transmitted frames abandoned due to excessive collisions"
line.long 0x58 "TXLATECOLLISIONS,Total number of transmitted frames abandoned due to a late collision"
line.long 0x5C "RXIPGERROR,Total number of receive inter-packet gap errors (10G only)"
line.long 0x60 "TXCARRIERSENSEERRORS,Total number of transmitted frames that experienced a carrier loss"
line.long 0x64 "TXOCTETS,Total number of bytes in all good frames transmitted"
line.long 0x68 "OCTETFRAMES64,Total number of 64-byte frames received and transmitted"
line.long 0x6C "OCTETFRAMES65T127,Total number of frames of size 65 to 127 bytes received and transmitted"
line.long 0x70 "OCTETFRAMES128T255,Total number of frames of size 128 to 255 bytes received and transmitted"
line.long 0x74 "OCTETFRAMES256T511,Total number of frames of size 256 to 511 bytes received and transmitted"
line.long 0x78 "OCTETFRAMES512T1023,Total number of frames of size 512 to 1023 bytes received and transmitted"
line.long 0x7C "OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
line.long 0x80 "NETOCTETS,Total number of bytes received and transmitted"
line.long 0x84 "RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop"
line.long 0x88 "PORTMASK_DROP,Total number of dropped frames received due to portmask"
line.long 0x8C "RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop"
line.long 0x90 "ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting"
line.long 0x94 "ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress"
line.long 0x98 "ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA"
line.long 0x9C "ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode"
line.long 0xA0 "ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode"
line.long 0xA4 "ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication"
line.long 0xA8 "ALE_UNKN_UNI,ALE Receive Unknown Unicast"
line.long 0xAC "ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount"
line.long 0xB0 "ALE_UNKN_MLT,ALE Receive Unknown Multicast"
line.long 0xB4 "ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount"
line.long 0xB8 "ALE_UNKN_BRD,ALE Receive Unknown Broadcast"
line.long 0xBC "ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount"
line.long 0xC0 "ALE_POL_MATCH,ALE Policer Matched"
line.long 0xC4 "ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red"
line.long 0xC8 "ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow"
line.long 0xCC "ALE_MULT_SA_DROP,ALE Multicast Source Address Drop"
line.long 0xD0 "ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop"
line.long 0xD4 "ALE_LEN_ERROR_DROP,ALE Length Error Drop"
line.long 0xD8 "ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop"
line.long 0xDC "ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop"
group.long 0x3A37C++0x83
line.long 0x00 "TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error"
line.long 0x04 "ENET_PN_TX_PRI_REG_0,ENET Port n PRIORITY N Packet Count"
line.long 0x08 "ENET_PN_TX_PRI_REG_1,ENET Port n PRIORITY N Packet Count"
line.long 0x0C "ENET_PN_TX_PRI_REG_2,ENET Port n PRIORITY N Packet Count"
line.long 0x10 "ENET_PN_TX_PRI_REG_3,ENET Port n PRIORITY N Packet Count"
line.long 0x14 "ENET_PN_TX_PRI_REG_4,ENET Port n PRIORITY N Packet Count"
line.long 0x18 "ENET_PN_TX_PRI_REG_5,ENET Port n PRIORITY N Packet Count"
line.long 0x1C "ENET_PN_TX_PRI_REG_6,ENET Port n PRIORITY N Packet Count"
line.long 0x20 "ENET_PN_TX_PRI_REG_7,ENET Port n PRIORITY N Packet Count"
line.long 0x24 "ENET_PN_TX_PRI_BCNT_REG_0,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x28 "ENET_PN_TX_PRI_BCNT_REG_1,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x2C "ENET_PN_TX_PRI_BCNT_REG_2,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x30 "ENET_PN_TX_PRI_BCNT_REG_3,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x34 "ENET_PN_TX_PRI_BCNT_REG_4,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x38 "ENET_PN_TX_PRI_BCNT_REG_5,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x3C "ENET_PN_TX_PRI_BCNT_REG_6,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x40 "ENET_PN_TX_PRI_BCNT_REG_7,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x44 "ENET_PN_TX_PRI_DROP_REG_0,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x48 "ENET_PN_TX_PRI_DROP_REG_1,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x4C "ENET_PN_TX_PRI_DROP_REG_2,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x50 "ENET_PN_TX_PRI_DROP_REG_3,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x54 "ENET_PN_TX_PRI_DROP_REG_4,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x58 "ENET_PN_TX_PRI_DROP_REG_5,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x5C "ENET_PN_TX_PRI_DROP_REG_6,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x60 "ENET_PN_TX_PRI_DROP_REG_7,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x64 "ENET_PN_TX_PRI_DROP_BCNT_REG_0,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x68 "ENET_PN_TX_PRI_DROP_BCNT_REG_1,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x6C "ENET_PN_TX_PRI_DROP_BCNT_REG_2,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x70 "ENET_PN_TX_PRI_DROP_BCNT_REG_3,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x74 "ENET_PN_TX_PRI_DROP_BCNT_REG_4,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x78 "ENET_PN_TX_PRI_DROP_BCNT_REG_5,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x7C "ENET_PN_TX_PRI_DROP_BCNT_REG_6,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x80 "ENET_PN_TX_PRI_DROP_BCNT_REG_7,ENET Port n PRIORITY N Packet Drop Byte Count"
rgroup.long 0x3D000++0x5B
line.long 0x00 "IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,Identification value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CONTROL_REG,Time Sync Control Register"
bitfld.long 0x04 28.--31. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1"
newline
bitfld.long 0x04 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1"
newline
bitfld.long 0x04 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
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bitfld.long 0x04 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
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bitfld.long 0x04 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
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bitfld.long 0x04 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
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bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
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bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
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bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
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bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
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bitfld.long 0x04 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1"
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bitfld.long 0x04 6. "TS_COMP_TOG,Timestamp Compare Toggle mode" "TS_COMP is in non-toggle mode,TS_COMP is in toggle mode"
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bitfld.long 0x04 5. "MODE,Timestamp mode" "0,1"
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bitfld.long 0x04 4. "SEQUENCE_EN,Sequence Enable" "0,1"
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bitfld.long 0x04 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1"
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bitfld.long 0x04 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1"
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bitfld.long 0x04 1. "INT_TEST,Interrupt test" "0,1"
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bitfld.long 0x04 0. "CPTS_EN,Time sync enable" "0,1"
line.long 0x08 "RFTCLK_SEL_REG,RFTCLK Select Register"
bitfld.long 0x08 0.--4. "RFTCLK_SEL,Reference clock select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x0C 0. "TS_PUSH,Time stamp event push" "0,1"
line.long 0x10 "TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
line.long 0x14 "TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x14 0. "TS_LOAD_EN,Time stamp load enable" "0,1"
line.long 0x18 "TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
line.long 0x1C "TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
line.long 0x20 "INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x20 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
line.long 0x24 "INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x24 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
line.long 0x28 "INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x28 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x2C "TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x2C 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
line.long 0x30 "EVENT_POP_REG,Event Pop Register"
bitfld.long 0x30 0. "EVENT_POP,Event pop" "0,1"
line.long 0x34 "EVENT_0_REG,Event 0 Register"
line.long 0x38 "EVENT_1_REG,Event 1 Register"
bitfld.long 0x38 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
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bitfld.long 0x38 24.--28. "PORT_NUMBER,Port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 20.--23. "EVENT_TYPE,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 16.--19. "MESSAGE_TYPE,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x38 0.--15. 1. "SEQUENCE_ID,Sequence ID"
line.long 0x3C "EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x3C 0.--7. 1. "DOMAIN,Domain"
line.long 0x40 "EVENT_3_REG,Event 3 Register"
line.long 0x44 "TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
line.long 0x48 "TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
line.long 0x4C "TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x4C 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7"
line.long 0x50 "TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
line.long 0x54 "TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x54 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value"
line.long 0x58 "TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x58 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value"
group.long 0x3D0E0++0x1B
line.long 0x00 "COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
line.long 0x04 "COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
line.long 0x08 "CONTROL_REG,Time Stamp Generate Function Control"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1"
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bitfld.long 0x08 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1"
line.long 0x0C "LENGTH_REG,Time Stamp Generate Function Length Value"
line.long 0x10 "PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
line.long 0x14 "PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
line.long 0x18 "NUDGE_REG,Time Stamp Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
group.long 0x3D200++0x1B
line.long 0x00 "COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value"
line.long 0x04 "COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value"
line.long 0x08 "CONTROL_REG,Time Stamp ESTF Generate Function Control"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1"
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bitfld.long 0x08 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1"
line.long 0x0C "LENGTH_REG,Time Stamp ESTF Generate Function Length Value"
line.long 0x10 "PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value"
line.long 0x14 "PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value"
line.long 0x18 "NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value"
rgroup.long 0x3E000++0x17
line.long 0x00 "MOD_VER,The Module and Version Register identifies the module identifier and revision of the ALE_2g32 module"
hexmask.long.word 0x00 16.--31. 1. "MODULE_ID,ALE_2g32 module ID"
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bitfld.long 0x00 11.--15. "RTL_VERSION,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR_REVISION,Major Revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM_REVISION,Custom Revision" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR_REVISION,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ALE_STATUS,The ALE status provides information on the ALE configuration and state"
bitfld.long 0x04 31. "UREGANDREGMSK12,When set the unregistered multicast field is a mask versus an index on 12 bit boundary in the ALE table" "0,1"
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bitfld.long 0x04 30. "UREGANDREGMSK08,When set the unregistered multicast field is a mask versus an index on 8 bit boundary in the ALE table" "0,1"
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hexmask.long.byte 0x04 8.--15. 1. "POLCNTDIV8,This is the number of policer engines the ALE implements divided by 8"
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bitfld.long 0x04 7. "RAMDEPTH128,The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both ramdepth128 and ramdepth32 are zero the depth is 64" "0,1"
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bitfld.long 0x04 6. "RAMDEPTH32,The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both ramdepth128 and ramdepth32 are zero the depth is 64" "0,1"
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bitfld.long 0x04 0.--4. "KLUENTRIES,This is the number of table entries total divided by 1024" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "ALE_CONTROL,The ALE Control Register is used to set the ALE modes used for all ports"
bitfld.long 0x08 31. "ENABLE_ALE,Enable ALE " "Drop all packets,Enable ALE packet processing"
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bitfld.long 0x08 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero" "0,1"
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bitfld.long 0x08 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit" "0,1"
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bitfld.long 0x08 24. "MIRROR_DP,Mirror Destination Port - This field defines the port to which destination traffic destined will be duplicated" "0,1"
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bitfld.long 0x08 21.--23. "UPD_BW_CTRL,The ~iupd_bw_ctrl field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16. "MIRROR_TOP,Mirror To Port - This field defines the destination port for the mirror traffic" "0,1"
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bitfld.long 0x08 15. "UPD_STATIC,Update Static Entries - A static Entry is an entry that is not agable" "0,1"
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bitfld.long 0x08 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn - This field when set will prevent source addresses of unknown VLAN IDs from being automatically added into the look up table if learning is enabled" "0,1"
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bitfld.long 0x08 12. "MIRROR_MEN,Mirror Match Entry Enable - This field enables the match mirror option" "0,1"
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bitfld.long 0x08 11. "MIRROR_DEN,Mirror Destination Port Enable - This field enables the destination port mirror option" "0,1"
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bitfld.long 0x08 10. "MIRROR_SEN,Mirror Source Port Enable - This field enables the source port mirror option" "0,1"
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bitfld.long 0x08 8. "EN_HOST_UNI_FLOOD,Unknown unicast packets flood to host " "unknown unicast packets are not sent to the host,unknown unicast packets flood to host port as.."
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bitfld.long 0x08 7. "LEARN_NO_VLANID,Learn No VID - " "VID is learned with the source address,VID is not learned with the source address.."
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bitfld.long 0x08 6. "ENABLE_VID0_MODE,Enable VLAN ID = 0 Mode " "Process the priority tagged packet with VID =..,Process the priority tagged packet with VID = 0"
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bitfld.long 0x08 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode - When set any packet with a non-matching OUI source address will be dropped to the host unless the packet destination address matches a supervisory destination address table entry" "0,1"
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bitfld.long 0x08 4. "ENABLE_BYPASS,ALE Bypass - When set packets received on non-host ports are sent to the host" "no bypass,bypass the ALE"
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bitfld.long 0x08 3. "BCAST_MCAST_CTL,Rate Limit Transmit mode " "Broadcast and multicast rate limit counters are..,Broadcast and multicast rate limit counters are.."
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bitfld.long 0x08 2. "ALE_VLAN_AWARE,ALE VLAN Aware - Determines how traffic is forwarded using VLAN rules. " "Simple switch rules packets forwarded to all..,VLAN Aware rules packets forwarded based on VLAN.."
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bitfld.long 0x08 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software" "The ALE is not in MAC authorization mode,The ALE is in MAC authorization mode"
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bitfld.long 0x08 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit " "Broadcast/Multicast rates not limited,Broadcast/Multicast packet reception limited to.."
line.long 0x0C "ALE_CTRL2,The ALE Control 2 Register is used to set the extended features used for all ports"
bitfld.long 0x0C 31. "TRK_EN_DST,Trunk Enable Destination Address - This field enables the destination MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 30. "TRK_EN_SRC,Trunk Enable Source Address - This field enables the source MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 29. "TRK_EN_PRI,Trunk Enable Priority - This field enables the VLAN Priority bits to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 27. "TRK_EN_IVLAN,Trunk Enable Inner VLAN - This field enables the inner VLAN ID value (C-VLANID) to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 25. "TRK_EN_SIP,Trunk Enable Source IP Address - This field enables the source IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged VLAN tagged.." "0,1"
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bitfld.long 0x0C 24. "TRK_EN_DIP,Trunk Enable Destination IP Address - This field enables the destination IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged.." "0,1"
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bitfld.long 0x0C 23. "DROP_BADLEN,Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet" "0,1"
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bitfld.long 0x0C 22. "NODROP_SRCMCST,No Drop Source Multicast will disable the dropping of any source address with the multicast bit set" "0,1"
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bitfld.long 0x0C 21. "DEFNOFRAG,Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found" "0,1"
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bitfld.long 0x0C 20. "DEFLMTNXTHDR,Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match the ~iALE_NXT_HDR register values" "0,1"
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bitfld.long 0x0C 16.--18. "TRK_BASE,Trunk Base - This field is the hash formula starting value" "?,~i00000000,~i01010101,~i02102102,~i03210321,?..."
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bitfld.long 0x0C 0.--4. "MIRROR_MIDX,Mirror Index - This field is the ALE lookup table entry index that when a match occurs will cause this traffic to be mirrored to the ~imirror_top port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "ALE_PRESCALE,The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value"
hexmask.long.tbyte 0x10 0.--19. 1. "ALE_PRESCALE,ALE Prescale - The input clock is divided by this value for use in the multicast/broadcast rate limiters"
line.long 0x14 "ALE_AGING_CTRL,The ALE Aging Control sets the aging interval which will cause periodic aging to occur"
bitfld.long 0x14 31. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable - When set will divide the aging interval by 1000" "0,1"
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bitfld.long 0x14 30. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable - When set will divide the aging interval by 1000" "0,1"
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hexmask.long.tbyte 0x14 0.--23. 1. "ALE_AGING_TIMER,ALE Aging Timer - This field specifies the number of clock cycles times 1 000 000 between aging operations"
group.long 0x3E01C++0x07
line.long 0x00 "ALE_NXT_HDR,The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header"
hexmask.long.byte 0x00 24.--31. 1. "IP_NXT_HDR3,The ~iip_nxt_hdr3 is the forth protocol or next header compared when enabled"
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hexmask.long.byte 0x00 16.--23. 1. "IP_NXT_HDR2,The ~iip_nxt_hdr2 is the third protocol or next header compared when enabled"
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hexmask.long.byte 0x00 8.--15. 1. "IP_NXT_HDR1,The ~iip_nxt_hdr1 is the second protocol or next header compared when enabled"
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hexmask.long.byte 0x00 0.--7. 1. "IP_NXT_HDR0,The ~iip_nxt_hdr0 is the first protocol or next header compared when enabled"
line.long 0x04 "ALE_TBLCTL,The ALE table control register is used to read or write that ALE table entries"
bitfld.long 0x04 31. "TABLEWR,Table Write - This bit is used to write the table words to the lookup table. " "Table Read Operation is performed,Table write operation is performed"
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bitfld.long 0x04 0.--4. "TABLEIDX,The table index is used to determine which lookup table entry is read or written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3E034++0x0B
line.long 0x00 "ALE_TBLW2,The ALE Table Word 2 is the most significant word of an ALE table entry"
hexmask.long.byte 0x00 0.--6. 1. "TABLEWRD2,Table Entry bits [71:64]"
line.long 0x04 "ALE_TBLW1,The ALE Table Word 1 is the middle word of an ALE table entry"
line.long 0x08 "ALE_TBLW0,The ALE Table Word 0 is the least significant word of an ALE table entry"
repeat 2. (list 0x0 0x1 )(list 0x0 0x4 )
group.long ($2+0x3E040)++0x03
line.long 0x00 "I0_ALE_PORTCTL0_$1,The ALE Port Control Register sets the port specific modes of operation"
hexmask.long.byte 0x00 24.--31. 1. "I0_REG_P0_BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter"
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hexmask.long.byte 0x00 16.--23. 1. "I0_REG_P0_MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter"
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bitfld.long 0x00 15. "I0_REG_P0_DROP_DOUBLE_VLAN,Drop Double VLAN - When set cause any received packet with double VLANs to be dropped" "0,1"
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bitfld.long 0x00 14. "I0_REG_P0_DROP_DUAL_VLAN,Drop Dual VLAN - When set will cause any received packet with dual VLAN stag followed by ctag to be dropped" "0,1"
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bitfld.long 0x00 13. "I0_REG_P0_MACONLY_CAF,Mac Only Copy All Frames - When set a Mac Only port will transfer all received good frames to the host" "0,1"
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bitfld.long 0x00 12. "I0_REG_P0_DIS_PAUTHMOD,Disable Port" "0,1"
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bitfld.long 0x00 11. "I0_REG_P0_MACONLY,MAC Only - When set enables this port be treated like a MAC port for the host" "0,1"
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bitfld.long 0x00 10. "I0_REG_P0_TRUNKEN,Trunk Enable - This field is used to enable a port into a trunk" "0,1"
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bitfld.long 0x00 8.--9. "I0_REG_P0_TRUNKNUM,Trunk Number - This field is used as the trunk number when the ~ip0_trunken is also set" "0,1,2,3"
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bitfld.long 0x00 7. "I0_REG_P0_MIRROR_SP,Mirror Source Port - This field enables the source port mirror option" "0,1"
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bitfld.long 0x00 5. "I0_REG_P0_NO_SA_UPDATE,No Source Address Update - When set will not update the source addresses for this port" "0,1"
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bitfld.long 0x00 4. "I0_REG_P0_NO_LEARN,No Learn - When set will not learn the source addresses for this port" "0,1"
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bitfld.long 0x00 3. "I0_REG_P0_VID_INGRESS_CHECK,VLAN Ingress" "0,1"
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bitfld.long 0x00 2. "I0_REG_P0_DROP_UN_TAGGED,If Drop Untagged - When set will drop packets without a VLAN tag" "0,1"
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bitfld.long 0x00 0.--1. "I0_REG_P0_PORTSTATE,Port State - Defins the current port state used for lookup operations. " "Disabled,Blocked,Learning,Forwarding"
repeat.end
group.long 0x3E090++0x0F
line.long 0x00 "ALE_UVLAN_MEMBER,The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID"
bitfld.long 0x00 0.--1. "UVLAN_MEMBER_LIST,Unknown VLAN Member List - Each bit represents the port member status for unknown VLANs" "0,1,2,3"
line.long 0x04 "ALE_UVLAN_URCAST,The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID"
bitfld.long 0x04 0.--1. "UVLAN_UNREG_MCAST,Unknown VLAN Unregister Multicast Flood Mask - Each bit represents the port to which unregistered multicast are sent for unregistered VLANs" "0,1,2,3"
line.long 0x08 "ALE_UVLAN_RMCAST,The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID"
bitfld.long 0x08 0.--1. "UVLAN_REG_MCAST_FLOOD_MASK,Unknown VLAN Register Multicast Flood Mask - Each bit represents the port to which registered multicast are sent for unregistered VLANs" "0,1,2,3"
line.long 0x0C "ALE_UVLAN_UNTAG,The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed"
bitfld.long 0x0C 0.--1. "UVLAN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress Mask - Each bit represents the port where the VLAN will be removed for unregistered VLANs" "0,1,2,3"
group.long 0x3E0B8++0x0B
line.long 0x00 "ALE_STAT_DIAG,The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters"
bitfld.long 0x00 15. "PBCAST_DIAG,When set and the ~iport_diag is set to zero will allow all ports to see the same stat diagnostic increment" "0,1"
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bitfld.long 0x00 8. "PORT_DIAG,The port selected that a received packet will cause the selected error to increment" "0,1"
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bitfld.long 0x00 0.--3. "STAT_DIAG,When non-zero will cause the selected statistic to increment on the next frame received" "Disabled,Destination Equal Source Drop Stat will count,VLAN Ingress Check Drop Stat will count,Source Multicast Drop Stat will count,Dual VLAN Drop Stat will count,Ether Type length error Drop Stat will count,Next Hop Limit Drop Stat will count,IPv4 Fragment Drop Stat will count,Classifier Hit Stat will count,Classifier Red Drop Stat will count,Classifier Yellow Drop Stat will count,ALE Overflow Drop Stat will count,Rate Limit Drop Stat will count,Blocked Address Drop Stat will count,Secure Address Drop Stat will count,Authorization Drop Stat will count"
line.long 0x04 "ALE_OAM_LB_CTRL,The ALE OAM Control allows ports to be put into OAM Loopback. only non-supervisor packet are looped back to the source port"
bitfld.long 0x04 0.--1. "OAM_LB_CTRL,The ~ioam_lb_ctrl allows any port to be put into OAM loopback that is any packet received will be returned to the same port with an egressop of 0xFF which swaps the source and destination address" "0,1,2,3"
line.long 0x08 "ALE_MSK_MUX0,VLAN Mask Mux x - The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for vlan registered and unregister mask respectively"
bitfld.long 0x08 0.--1. "VLAN_MASK_MUX_0,VLAN Mask Mux x - When selected by the VLAN lookup table entry FwdUnRegIdx or FwdAllRegIdx is used as the FwdUnRegMask or FwdUnRegMask values anded with the member list to determine the forwarding of packets" "0,1,2,3"
repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x4 0x8 )
group.long ($2+0x3E0C4)++0x03
line.long 0x00 "I1_ALE_MSK_MUX1_$1,VLAN Mask Mux x - The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for vlan registered and unregister mask respectively"
bitfld.long 0x00 0.--1. "I1_REG_VLAN_MASK_MUX_1,VLAN Mask Mux x - When selected by the VLAN lookup table entry FwdUnRegIdx or FwdAllRegIdx is used as the FwdUnRegMask or FwdUnRegMask values anded with the member list to determine the forwarding of packets" "0,1,2,3"
repeat.end
group.long 0x3E0FC++0x17
line.long 0x00 "EGRESSOP,The Egress Operation register allows enabled classifiers with IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions"
abitfld.long 0x00 24.--31. "EGRESS_OP,The Egress Operation defines the operation performed by the CPSW Egress Packet Operations " "0x00=NOP,0xFF=Swap SA and DA of packet this is intended.."
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bitfld.long 0x00 21.--23. "EGRESS_TRK,The Egress Trunk Index is the calculated trunk index from the SA DA or VLAN if modified to that InterVLAN routing will work on trunks as well" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "TTL_CHECK,The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions" "0,1"
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bitfld.long 0x00 0.--1. "DEST_PORTS,The Destination Ports is a list of the ports the classified packet will be set to" "0,1,2,3"
line.long 0x04 "POLICECFG0,The Policing Config 0 holds the port. frame priority and ONU address index as well as match enables for port. frame priority and ONU address matching"
bitfld.long 0x04 31. "PORT_MEN,Port Match Enable - Enabled port match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 30. "TRUNKID,Trunk ID - When set indicates the port number is a trunk group" "0,1"
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bitfld.long 0x04 25. "PORT_NUM,Port Number - Specifies the port address to match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 19. "PRI_MEN,Priority Match Enable - Enables frame priority match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 16.--18. "PRI_VAL,Priority Value - Specifies the frame priority to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 15. "ONU_MEN,OUI Match Enable - Enables frame ONU address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 0.--4. "ONU_INDEX,OUI Table Entry Index - Specifies the ALE ONU address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "POLICECFG1,The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses"
bitfld.long 0x08 31. "DST_MEN,Destination Address Match Enable - Enables frame L2 destination address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x08 16.--20. "DST_INDEX,Destination Address Table Entry Index - Specifies the ALE L2 destination address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 15. "SRC_MEN,Source Address Match Enable - Enables frame L2 source address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x08 0.--4. "SRC_INDEX,Source Address Table Entry Index - Specifies the ALE L2 source address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "POLICECFG2,The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses"
bitfld.long 0x0C 31. "OVLAN_MEN,Outer VLAN Match Enable - Enables frame Outer VLAN address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x0C 16.--20. "OVLAN_INDEX,Outer VLAN Table Entry Index - Specifies the ALE Outer VLAN address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 15. "IVLAN_MEN,Inner VLAN Match Enable - Enables frame Inner VLAN address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x0C 0.--4. "IVLAN_INDEX,Inner VLAN Table Entry Index - Specifies the ALE Inner VLAN address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "POLICECFG3,The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address"
bitfld.long 0x10 31. "ETHERTYPE_MEN,EtherType Match Enable - Enables frame Ether Type match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x10 16.--20. "ETHERTYPE_INDEX,EtherType Table Entry Index - Specifies the ALE Ether Type lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 15. "IPSRC_MEN,IP Source Address Match Enable - Enables frame IP Source address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x10 0.--4. "IPSRC_INDEX,IP Source Address Table Entry Index - Specifies the ALE IP Source address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "POLICECFG4,The Policing Config 4 holds the match enable/match index for the IP Destination address"
bitfld.long 0x14 31. "IPDST_MEN,IP Destination Address Match Enable - Enables frame IP Destination address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x14 16.--20. "IPDST_INDEX,IP Destination Address Table Entry Index - Specifies the ALE IP Destination address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3E118++0x17
line.long 0x00 "POLICECFG6,The PIR counter is a 37 bit internal counter where ~ipir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time"
line.long 0x04 "POLICECFG7,The CIR counter is a 37 bit internal counter where ~icir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time"
line.long 0x08 "POLICETBLCTL,The Policing Table Control is used to read or write the selected policing/classifier entry"
bitfld.long 0x08 31. "WRITE_ENABLE,Write Enable - Setting this bit will write the POLICECFG0-7 to the ~ipol_tbl_idx selected policing/classifier entry" "0,1"
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bitfld.long 0x08 0.--1. "POL_TBL_IDX,Policer Entry Index - This field specifies the policing/classifier entry to be read or written" "0,1,2,3"
line.long 0x0C "POLICECONTROL,The Control Enables color marking as well as internal ALE packet dropping rules"
bitfld.long 0x0C 31. "POLICING_EN,Policing Enable - Enables the policing to color the packets this also enables red or yellow drop capabilities" "0,1"
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bitfld.long 0x0C 29. "RED_DROP_EN,RED Drop Enable - Enables the ALE to drop the red colored packets" "0,1"
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bitfld.long 0x0C 28. "YELLOW_DROP_EN,WELLOW Drop Enable - Enables the ALE to drop yellow packets based on the ~iyellowthresh value" "0,1"
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bitfld.long 0x0C 24.--26. "YELLOWTHRESH,Yellow Threshold - When set enables a portion of the yellow packets to be dropped based on the ~iyellow_drop_en enable. 0-100% " "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 22.--23. "POLMCHMODE,Policing Match Mode - This field determines what happens to packets that fail to hit any policing/classifier entry. " "No Hit packets are marked GREEN,No Hit packets are marked YELLOW,No Hit packets are marked RED,No Hit packets are marked based on.."
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bitfld.long 0x0C 21. "PRIORITY_THREAD_EN,Priority Thread Enable - This field determines if priority is OR'd to the default thread when no classifiers hit and the default thread is enabled" "0,1"
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bitfld.long 0x0C 20. "MAC_ONLY_DEF_DIS,MAC Only Default Disable - This field when set disables the default thread on MAC Only Ports" "0,1"
line.long 0x10 "POLICETESTCTL,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition"
bitfld.long 0x10 31. "POL_CLRALL_HIT,Policer Clear - This bit clears all the policing/classifier hit bits" "0,1"
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bitfld.long 0x10 30. "POL_CLRALL_REDHIT,Policer Clear RED - This bit clears all the policing/classifier RED hit bits" "0,1"
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bitfld.long 0x10 29. "POL_CLRALL_YELLOWHIT,Policer Clear YELLOW - This bit clears all the policing/classifier YELLOW hit bits" "0,1"
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bitfld.long 0x10 28. "POL_CLRSEL_ALL,Police Clear Selected - This bit clears the selected policing/classifier hit redhit and yellowhit bits" "0,1"
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bitfld.long 0x10 0.--1. "POL_TEST_IDX,Policer Test Index - This field selects which policing/classifier hit bits will be read or written" "0,1,2,3"
line.long 0x14 "POLICEHSTAT,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier"
bitfld.long 0x14 31. "POL_HIT,Policer Hit - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit by a packet seen on any port that matches the policing/classifier entry match" "0,1"
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bitfld.long 0x14 30. "POL_REDHIT,Policer Hit RED - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit during a RED condition by a packet seen on any port that matches the policing/classifier entry match" "0,1"
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bitfld.long 0x14 29. "POL_YELLOWHIT,Policer Hit YELLOW - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit during a YELLOW condition by a packet seen on any port that matches the policing/classifier entry match" "0,1"
group.long 0x3E134++0x0B
line.long 0x00 "THREADMAPDEF,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched."
bitfld.long 0x00 15. "DEFTHREAD_EN,Default Tread Enable - When set the switch will use the ~idefthreadval for the host interface thread ID if no classifier is matched" "0,1"
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bitfld.long 0x00 0.--5. "DEFTHREADVAL,Default Thread Value - This field specifies the default thread ID value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "THREADMAPCTL,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host"
bitfld.long 0x04 0.--1. "CLASSINDEX,Classifier Index - This is the classifier index entry that the thread enable and thread value will be read or written by the ~bTHREADMAPVAL register" "0,1,2,3"
line.long 0x08 "THREADMAPVAL,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry"
bitfld.long 0x08 15. "THREAD_EN,Thread Enable - When set the switch will use the ~ithreadval for the selected classifier match" "0,1"
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bitfld.long 0x08 0.--5. "THREADVAL,Thread Value - This field is the thread ID value that is used to map a classifier hit to thread ID for host traffic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x3F000++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3F008++0x27
line.long 0x00 "vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
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bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "reserved_svbus_0,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x0C "reserved_svbus_1,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x10 "reserved_svbus_2,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x14 "reserved_svbus_3,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x18 "reserved_svbus_4,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x1C "reserved_svbus_5,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x20 "reserved_svbus_6,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x24 "reserved_svbus_7,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3F03C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
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bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
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bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
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bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
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bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
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bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
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bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
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bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
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bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
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bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
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bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
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bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
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bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
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bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
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bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
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bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
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bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
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bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
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bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
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bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x3F080++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
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bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
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bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
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bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
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bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
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bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
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bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
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bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
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bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
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bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
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bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
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bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
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bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
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bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
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bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
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bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
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bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
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bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
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bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
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bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x3F0C0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
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bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
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bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
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bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
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bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
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bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
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bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
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bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
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bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
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bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
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bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
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bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
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bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
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bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
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bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
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bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
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bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
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bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
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bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
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bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x3F13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
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bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
newline
bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
newline
bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
newline
bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
newline
bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
newline
bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
newline
bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
newline
bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
newline
bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
newline
bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
newline
bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
newline
bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
newline
bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
newline
bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
newline
bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
newline
bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
newline
bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
newline
bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
newline
bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x3F180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
newline
bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
newline
bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
newline
bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
newline
bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
newline
bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
newline
bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
newline
bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
newline
bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
newline
bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
newline
bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
newline
bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
newline
bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
newline
bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
newline
bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x3F1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
newline
bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
newline
bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
newline
bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
newline
bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
newline
bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
newline
bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
newline
bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
newline
bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
newline
bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
newline
bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
newline
bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
newline
bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
newline
bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
newline
bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x3F200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_CTRL (MSS CTRL Module Registers)"
base ad:0x2120000
rgroup.long 0x00++0x517
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MSS_SW_INT,"
bitfld.long 0x04 0.--4. "pulse,Write_pulse bit field: writing 1'b1 to each bit will trigger MSS_SW_INT<0-4> respectively to CR5A/B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "MSS_CAPEVNT_SEL,"
hexmask.long.byte 0x08 8.--15. 1. "src1,Writing a value 'N' will select Nth interrupt from CR5A/B interrupt mapping to trigger CAP-EVENT1 to all MSS_RTIs"
newline
hexmask.long.byte 0x08 0.--7. 1. "src0,Writing a value 'N' will select Nth interrupt from CR5A/B interrupt mapping to trigger CAP-EVENT0 to all MSS_RTIs"
line.long 0x0C "MSS_DMA_REQ_SEL,"
line.long 0x10 "MSS_DMA1_REQ_SEL,"
line.long 0x14 "MSS_IRQ_REQ_SEL,"
line.long 0x18 "MSS_SPI_TRIG_SRC,"
hexmask.long.word 0x18 16.--26. 1. "trig_spib,Writing 1'b1 to each bit will trigger MSS_SPIB Trigger<0-10> respectively"
newline
bitfld.long 0x18 0.--1. "trig_spia,Writing 1'b1 to each bit will trigger MSS_SPIA Trigger<0-1> respectively" "0,1,2,3"
line.long 0x1C "MSS_ATCM_MEM_INIT,"
bitfld.long 0x1C 0. "mem_init,Write_pulse bit field: Writing 1'b1 will start initializing the ATCM banks of CR5A/B" "0,1"
line.long 0x20 "MSS_ATCM_MEM_INIT_DONE,"
bitfld.long 0x20 0. "mem_init_done,This field will be high once initialization of ATCM banks is finished" "0,1"
line.long 0x24 "MSS_ATCM_MEM_INIT_STATUS,"
bitfld.long 0x24 0. "mem_status," "0,1"
line.long 0x28 "MSS_BTCM_MEM_INIT,"
bitfld.long 0x28 0. "mem_init,Write_pulse bit field: Writing 1'b1 will start initializing the B0/1TCM banks of CR5A/B" "0,1"
line.long 0x2C "MSS_BTCM_MEM_INIT_DONE,"
bitfld.long 0x2C 0. "mem_init_done,This field will be high once initialization of B0/1TCM banks is finished" "0,1"
line.long 0x30 "MSS_BTCM_MEM_INIT_STATUS,"
bitfld.long 0x30 0. "mem_status," "0,1"
line.long 0x34 "MSS_L2_MEM_INIT,"
bitfld.long 0x34 1. "partition1,Write_pulse bit field: Writing 1'b1 will start initializing the L2 Bank1" "0,1"
newline
bitfld.long 0x34 0. "partition0,Write_pulse bit field: Writing 1'b1 will start initializing the L2 Bank0" "0,1"
line.long 0x38 "MSS_L2_MEM_INIT_DONE,"
bitfld.long 0x38 1. "partition1,This field will be high once intialization of L2 bank1 is finished" "0,1"
newline
bitfld.long 0x38 0. "partition0,This field will be high once intialization of L2 bank0 is finished" "0,1"
line.long 0x3C "MSS_L2_MEM_INIT_STATUS,"
bitfld.long 0x3C 1. "partition1," "0,1"
newline
bitfld.long 0x3C 0. "partition0," "0,1"
line.long 0x40 "MSS_MAILBOX_MEM_INIT,"
bitfld.long 0x40 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_MBOX" "0,1"
line.long 0x44 "MSS_MAIlBOX_MEM_INIT_DONE,"
bitfld.long 0x44 0. "mem0_done,This field will be high once intialization of MSS_MBOX is finished" "0,1"
line.long 0x48 "MSS_MAILBOX_MEM_INIT_STATUS,"
bitfld.long 0x48 0. "mem0_status," "0,1"
line.long 0x4C "MSS_RETRAM_MEM_INIT,"
bitfld.long 0x4C 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_RETRAM" "0,1"
line.long 0x50 "MSS_RETRAM_MEM_INIT_DONE,"
bitfld.long 0x50 0. "mem0_done,This field will be high once intialization of MSS_RETRAM is finished" "0,1"
line.long 0x54 "MSS_RETRAM_MEM_INIT_STATUS,"
bitfld.long 0x54 0. "mem0_status," "0,1"
line.long 0x58 "MSS_SPIA_MEM_INIT,"
bitfld.long 0x58 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_SPIA" "0,1"
line.long 0x5C "MSS_SPIA_MEM_INIT_DONE,"
bitfld.long 0x5C 0. "mem0_done,This field will be high once intialization of MSS_SPIA is finished" "0,1"
line.long 0x60 "MSS_SPIA_MEM_INIT_STATUS,"
bitfld.long 0x60 0. "mem0_status," "0,1"
line.long 0x64 "MSS_SPIB_MEM_INIT,"
bitfld.long 0x64 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_SPIB" "0,1"
line.long 0x68 "MSS_SPIB_MEM_INIT_DONE,"
bitfld.long 0x68 0. "mem0_done,This field will be high once intialization of MSS_SPIB is finished" "0,1"
line.long 0x6C "MSS_SPIB_MEM_INIT_STATUS,"
bitfld.long 0x6C 0. "mem0_status," "0,1"
line.long 0x70 "MSS_TPCC_MEMINIT_START,"
bitfld.long 0x70 16. "tpcc_b_meminit_start,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_TPCCB" "0,1"
newline
bitfld.long 0x70 0. "tpcc_a_meminit_start,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_TPCCA" "0,1"
line.long 0x74 "MSS_TPCC_MEMINIT_DONE,"
bitfld.long 0x74 16. "tpcc_b_meminit_done,This field will be high once intialization of MSS_TPCCB is finished" "0,1"
newline
bitfld.long 0x74 0. "tpcc_a_meminit_done,This field will be high once intialization of MSS_TPCCA is finished" "0,1"
line.long 0x78 "MSS_TPCC_MEMINIT_STATUS,"
bitfld.long 0x78 16. "tpcc_b_meminit_status," "0,1"
newline
bitfld.long 0x78 0. "tpcc_a_meminit_status," "0,1"
line.long 0x7C "MSS_GPADC_MEM_INIT,"
bitfld.long 0x7C 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_GPADC_DATA_MEM" "0,1"
line.long 0x80 "MSS_GPADC_MEM_INIT_DONE,"
bitfld.long 0x80 0. "mem0_done,This field will be high once intialization of MSS_GPADC_DATA_MEM is finished" "0,1"
line.long 0x84 "MSS_GPADC_MEM_INIT_STATUS,"
bitfld.long 0x84 0. "mem0_status," "0,1"
line.long 0x88 "MSS_SPIA_CFG,"
bitfld.long 0x88 24. "spia_int_trig_polarity,SPIA trigger source polarity select" "0,1"
newline
bitfld.long 0x88 16. "spia_trig_gate_en,When set the TRIGGER s are un-gated only when chip-select is active" "0,1"
newline
bitfld.long 0x88 8. "spia_cs_trigsrc_en,MIBSPIB CS Trigger SRC enable" "0,1"
newline
bitfld.long 0x88 0.--2. "spiasync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x8C "MSS_SPIB_CFG,"
bitfld.long 0x8C 24. "spib_int_trig_polarity,SPIB trigger source polarity select" "0,1"
newline
bitfld.long 0x8C 16. "spib_trig_gate_en,When set the TRIGGER s are un-gated only when chip-select is active" "0,1"
newline
bitfld.long 0x8C 8. "spib_cs_trigsrc_en,MIBSPIB CS Trigger SRC enable" "0,1"
newline
bitfld.long 0x8C 0.--2. "spibsync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x90 "MSS_EPWM_CFG,"
line.long 0x94 "MSS_GIO_CFG,"
line.long 0x98 "MSS_MCAN_FE_SELECT,"
bitfld.long 0x98 16.--18. "mcanb_fe_select,writing a value'N' would select Nth filter interrupt combination for hwa_cm4 interrupt and also HW_SYNC_IN Example: writing 3'd<1-7> selects MSS_MCANB_FE_INT<1-7> respectively" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x98 0.--2. "mcana_fe_select,writing a value'N' would select Nth filter interrupt combination for hwa_cm4 interrupt and also HW_SYNC_IN Example: writing 3'd<1-7> would select MSS_MCANA_FE_INT<1-7> respectively" "0,1,2,3,4,5,6,7"
line.long 0x9C "HW_SPARE_REG1,"
line.long 0xA0 "MSS_MCANA_INT_CLR,"
line.long 0xA4 "MSS_MCANA_INT_MASK,"
line.long 0xA8 "MSS_MCANA_INT_STAT,"
line.long 0xAC "HW_SPARE_REG2,"
line.long 0xB0 "CCC_ERR_STATUS,"
hexmask.long.byte 0xB0 16.--23. 1. "cccb_errot_status,CCCB Error Status (for Debug) {3'd0 counter_error counter_done timeout_error counter_error counter_done}"
newline
hexmask.long.byte 0xB0 0.--7. 1. "ccca_errot_status,CCCA Error Status (for Debug) {3'd0 counter_error counter_done timeout_error counter_error counter_done}"
line.long 0xB4 "CCCA_CFG0,"
hexmask.long.word 0xB4 16.--31. 1. "ccca_margin_count,Margin value for clock comparison in terms of counter1 clock.CCC error will not be generated if counter1 counter value is within count1_expected_val +/- MARGIN_COUNT"
newline
hexmask.long.byte 0xB4 9.--15. 1. "Reserved,Not used"
newline
bitfld.long 0xB4 8. "ccca_single_shot_mode," "0,1"
newline
bitfld.long 0xB4 7. "ccca_enable_module," "0,1"
newline
bitfld.long 0xB4 6. "ccca_disable_clocks," "0,1"
newline
bitfld.long 0xB4 3.--5. "ccca_clk1_sel,Selection for Clock 1" "Select clock0_src0 as source for counter1,Select clock0_src1 as source for counter1,Select clock0_src2 as source for counter1,?,?,?,?,Select clock0_src7 as source for counter1"
newline
bitfld.long 0xB4 0.--2. "ccca_clk0_sel,Selection for Clock 0" "Select clock0_src0 as source for counter0,Select clock0_src1 as source for counter0,Select clock0_src2 as source for counter0,?,?,?,?,Select clock0_src7 as source for counter0"
line.long 0xB8 "CCCA_CFG1,"
line.long 0xBC "CCCA_CFG2,"
line.long 0xC0 "CCCA_CFG3,"
line.long 0xC4 "CCCA_CNTVAL,"
line.long 0xC8 "CCCB_CFG0,"
hexmask.long.word 0xC8 16.--31. 1. "cccb_margin_count,Margin value for clock comparison in terms of counter1 clock.CCC error will not be generated if counter1 counter value is within count1_expected_val +/- MARGIN_COUNT"
newline
hexmask.long.byte 0xC8 9.--15. 1. "Reserved,Not used"
newline
bitfld.long 0xC8 8. "cccb_single_shot_mode," "0,1"
newline
bitfld.long 0xC8 7. "cccb_enable_module," "0,1"
newline
bitfld.long 0xC8 6. "cccb_disable_clocks," "0,1"
newline
bitfld.long 0xC8 3.--5. "CCCB_clk1_sel,Selection for Clock 1" "Select clock0_src0 as source for counter1,Select clock0_src1 as source for counter1,Select clock0_src2 as source for counter1,?,?,?,?,Select clock0_src7 as source for counter1"
newline
bitfld.long 0xC8 0.--2. "CCCB_clk0_sel,Selection for Clock 0" "Select clock0_src0 as source for counter0,Select clock0_src1 as source for counter0,Select clock0_src2 as source for counter0,?,?,?,?,Select clock0_src7 as source for counter0"
line.long 0xCC "CCCB_CFG1,"
line.long 0xD0 "CCCB_CFG2,"
line.long 0xD4 "CCCB_CFG3,"
line.long 0xD8 "CCCB_CNTVAL,"
line.long 0xDC "CCC_DCC_COMMON,"
bitfld.long 0xDC 12. "enable_cccb_err_nmi," "0,1"
newline
bitfld.long 0xDC 8. "enable_cccb_err_rstn," "0,1"
line.long 0xE0 "R5_GLOBAL_CONFIG,"
bitfld.long 0xE0 0. "teinit,Exception handling state at reset" "0,1"
line.long 0xE4 "R5_AHB_EN,"
bitfld.long 0xE4 16.--18. "cpu1_ahb_init,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE4 0.--2. "cpu0_ahb_init,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0xE8 "R5A_AHB_BASE,"
hexmask.long.tbyte 0xE8 0.--19. 1. "ahb_base,Ti internal Register"
line.long 0xEC "R5A_AHB_SIZE,"
bitfld.long 0xEC 0.--4. "ahb_size,Ti internal Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xF0 "R5B_AHB_BASE,"
hexmask.long.tbyte 0xF0 0.--19. 1. "ahb_base,Ti internal Register"
line.long 0xF4 "R5B_AHB_SIZE,"
bitfld.long 0xF4 0.--4. "ahb_size,Ti internal Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xF8 "R5_TCM_EXT_ERR_EN,"
bitfld.long 0xF8 16.--18. "cpu1_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 0.--2. "cpu0_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0xFC "R5_TCM_ERR_EN,"
bitfld.long 0xFC 16.--18. "cpu1_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xFC 0.--2. "cpu0_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0x100 "R5_INIT_TCM,"
bitfld.long 0x100 20.--22. "lockzram_cpu1,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 16.--18. "tcmb_cpu1,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 12.--14. "tcma_cpu1,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 8.--10. "lockzram_cpu0,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 4.--6. "tcmb_cpu0,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 0.--2. "tcma_cpu0,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0x104 "R5_TCM_ECC_WRENZ_EN,"
bitfld.long 0x104 20.--22. "cpu1_tcmb1_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 16.--18. "cpu1_tcmb0_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 12.--14. "cpu1_tcma_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 8.--10. "cpu0_tcmb1_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 4.--6. "cpu0_tcmb0_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 0.--2. "cpu0_tcma_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x108 "ESM_GATING0,"
line.long 0x10C "ESM_GATING1,"
line.long 0x110 "ESM_GATING2,"
line.long 0x114 "ESM_GATING3,"
line.long 0x118 "ESM_GATING4,"
line.long 0x11C "ESM_GATING5,"
line.long 0x120 "ESM_GATING6,"
line.long 0x124 "ESM_GATING7,"
line.long 0x128 "ERR_PARITY_ATCM0,"
hexmask.long.tbyte 0x128 0.--19. 1. "addr,Address lathched when parity error is occurred for ATCM of CR5A"
line.long 0x12C "ERR_PARITY_ATCM1,"
hexmask.long.tbyte 0x12C 0.--19. 1. "addr,Address lathched when parity error is occurred for ATCM of CR5B"
line.long 0x130 "ERR_PARITY_B0TCM0,"
hexmask.long.tbyte 0x130 0.--19. 1. "addr,Address lathched when parity error is occurred for B0TCM of CR5A"
line.long 0x134 "ERR_PARITY_B0TCM1,"
hexmask.long.tbyte 0x134 0.--19. 1. "addr,Address lathched when parity error is occurred for B0TCM of CR5B"
line.long 0x138 "ERR_PARITY_B1TCM0,"
hexmask.long.tbyte 0x138 0.--19. 1. "addr,Address lathched when parity error is occurred for B1TCM of CR5A"
line.long 0x13C "ERR_PARITY_B1TCM1,"
hexmask.long.tbyte 0x13C 0.--19. 1. "addr,Address lathched when parity error is occurred for B1TCM of CR5B"
line.long 0x140 "TCM_PARITY_CTRL,"
bitfld.long 0x140 20.--22. "b1tcm1_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 16.--18. "b1tcm0_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 12.--14. "b0cm1_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 8.--10. "b0tcm0_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 4.--6. "atcm1_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 0.--2. "atcm0_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x144 "TCM_PARITY_ERRFRC,"
bitfld.long 0x144 20.--22. "b1tcm1,Pulse bit-field writing 3'b111 forces a parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 16.--18. "b1tcm0,Pulse bit-field writing 3'b111 forces a parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 12.--14. "b0tcm1,Pulse bit-field writing 3'b111 forces a parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 8.--10. "b0tcm0,Pulse bit-field writing 3'b111 forces a parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 4.--6. "atcm1,Pulse bit-field writing 3'b111 forces a parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 0.--2. "atcm0,Pulse bit-field writing 3'b111 forces a parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x148 "HW_SPARE_REG3,"
line.long 0x14C "SPIA_IO_CFG,"
bitfld.long 0x14C 16.--18. "miso_oen_by_cs,MIBSPIA MISO OE_N Control based on Chip selectCS-applicable in slave mode" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
newline
bitfld.long 0x14C 8.--10. "cs_pol,MIBSPIA CS polarity-slave mode" "Active low,Active high,?..."
newline
bitfld.long 0x14C 0.--2. "cs_deact," "0,1,2,3,4,5,6,7"
line.long 0x150 "SPIB_IO_CFG,"
bitfld.long 0x150 16.--18. "miso_oen_by_cs,MIBSPIB MISO OE_N Control based on Chip selectCS-applicable in slave mode" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
newline
bitfld.long 0x150 8.--10. "cs_pol,MIBSPIB CS polarity-slave mode" "Active low,Active high,?..."
newline
bitfld.long 0x150 0.--2. "cs_deact," "0,1,2,3,4,5,6,7"
line.long 0x154 "SPI_HOST_IRQ,"
bitfld.long 0x154 0.--2. "host_irq,HOST IRQ" "0,1,2,3,4,5,6,7"
line.long 0x158 "TPTC_DBS_CONFIG,"
bitfld.long 0x158 8.--9. "tptc_b0,Default burst size tieoff value for TPTC_B0" "0,1,2,3"
newline
bitfld.long 0x158 4.--5. "tptc_a1,Default burst size tieoff value for TPTC_A1" "0,1,2,3"
newline
bitfld.long 0x158 0.--1. "tptc_a0,Default burst size tieoff value for TPTC_A0" "0,1,2,3"
line.long 0x15C "TPCC_PARITY_CTRL,"
bitfld.long 0x15C 20. "tpcc_b_parity_err_clr,parity clear bit" "0,1"
newline
bitfld.long 0x15C 16. "tpcc_a_parity_err_clr,parity clear bit" "0,1"
newline
bitfld.long 0x15C 12. "tpcc_b_parity_testen,parity test enable for tpcc b" "0,1"
newline
bitfld.long 0x15C 8. "tpcc_b_parity_en,parity en for tpcc b" "0,1"
newline
bitfld.long 0x15C 4. "tpcc_a_parity_testen,parity test enable for tpcc a" "0,1"
newline
bitfld.long 0x15C 0. "tpcc_a_parity_en,writing 1'b1 enables parity for TPCC_A" "0,1"
line.long 0x160 "TPCC_PARITY_STATUS,"
hexmask.long.byte 0x160 16.--23. 1. "tpcc_b_parity_addr,address where parity error happened for tpccb"
newline
hexmask.long.byte 0x160 0.--7. 1. "tpcc_a_parity_addr,address where parity error happened for tpcca"
line.long 0x164 "MSS_DBG_ACK_CTL0,"
bitfld.long 0x164 24.--26. "cpsw,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 20.--22. "dccd,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 16.--18. "dccc,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 12.--14. "dccb,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 8.--10. "dcca,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 4.--6. "cccb,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 0.--2. "ccca,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x168 "MSS_DBG_ACK_CTL1,"
bitfld.long 0x168 24.--26. "scib,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 20.--22. "scia,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 16.--18. "i2c,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 12.--14. "mcrc,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 8.--10. "wdt,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 4.--6. "rti,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 0.--2. "dcan,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x16C "CPSW_CONTROL,"
bitfld.long 0x16C 16. "rgmii1_id_mode,writing 1'b1 would disable the internal clock delays" "0,1"
newline
bitfld.long 0x16C 8. "rmii_ref_clk_oe_n,To select the rmii_ref_clk from PAD or from MSS_RCM" "clock will be from mss_rcm through..,will be from"
newline
bitfld.long 0x16C 0.--2. "port1_mode_sel,Port 1 Interface" "GMII/MII,RMII,RGMII,Not Supported,?..."
line.long 0x170 "MSS_TPCC_A_ERRAGG_MASK,"
bitfld.long 0x170 26. "tptc_a1_read_access_error,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 25. "tptc_a0_read_access_error,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 24. "tpcc_a_read_access_error,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 18. "tptc_a1_write_access_error,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 17. "tptc_a0_write_access_error,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 16. "tpcc_a_write_access_error,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 4. "tpcc_a_par_err,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 3. "tptc_a1_err,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 2. "tptc_a0_err,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 1. "tpcc_a_mpint,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 0. "tpcc_a_errint,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x174 "MSS_TPCC_A_ERRAGG_STATUS,"
bitfld.long 0x174 26. "tptc_a1_read_access_error,Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x174 25. "tptc_a0_read_access_error,Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x174 24. "tpcc_a_read_access_error,Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x174 18. "tptc_a1_write_access_error,Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x174 17. "tptc_a0_write_access_error,Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x174 16. "tpcc_a_write_access_error,Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x174 4. "tpcc_a_par_err,Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x174 3. "tptc_a1_err,Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x174 2. "tptc_a0_err,Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x174 1. "tpcc_a_mpint,Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x174 0. "tpcc_a_errint,Status of Error from MSS_TPCC_A" "0,1"
line.long 0x178 "MSS_TPCC_A_ERRAGG_STATUS_RAW,"
bitfld.long 0x178 26. "tptc_a1_read_access_error,Raw Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x178 25. "tptc_a0_read_access_error,Raw Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x178 24. "tpcc_a_read_access_error,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 18. "tptc_a1_write_access_error,Raw Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x178 17. "tptc_a0_write_access_error,Raw Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x178 16. "tpcc_a_write_access_error,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 4. "tpcc_a_par_err,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 3. "tptc_a1_err,Raw Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x178 2. "tptc_a0_err,Raw Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x178 1. "tpcc_a_mpint,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 0. "tpcc_a_errint,Raw Status of Error from MSS_TPCC_A" "0,1"
line.long 0x17C "MSS_TPCC_A_INTAGG_MASK,"
bitfld.long 0x17C 17. "tptc_a1,Mask Interrupt from TPTC A1 to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 16. "tptc_a0,Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 8. "tpcc_a_int7,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 7. "tpcc_a_int6,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 6. "tpcc_a_int5,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 5. "tpcc_a_int4,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 4. "tpcc_a_int3,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 3. "tpcc_a_int2,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 2. "tpcc_a_int1,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 1. "tpcc_a_int0,Mask Interrupt from TPCC A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 0. "tpcc_a_intg,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x180 "MSS_TPCC_A_INTAGG_STATUS,"
bitfld.long 0x180 17. "tptc_a1,Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x180 16. "tptc_a0,Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x180 8. "tpcc_a_int7,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 7. "tpcc_a_int6,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 6. "tpcc_a_int5,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 5. "tpcc_a_int4,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 4. "tpcc_a_int3,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 3. "tpcc_a_int2,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 2. "tpcc_a_int1,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 1. "tpcc_a_int0,Status of Interrupt from TPCC A Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x180 0. "tpcc_a_intg,Status of Interrupt from MSS_TPCC_A" "0,1"
line.long 0x184 "MSS_TPCC_A_INTAGG_STATUS_RAW,"
bitfld.long 0x184 17. "tptc_a1,Raw Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x184 16. "tptc_a0,Raw Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x184 8. "tpcc_a_int7,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 7. "tpcc_a_int6,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 6. "tpcc_a_int5,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 5. "tpcc_a_int4,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 4. "tpcc_a_int3,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 3. "tpcc_a_int2,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 2. "tpcc_a_int1,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 1. "tpcc_a_int0,Raw Status of Interrupt from TPCC A" "0,1"
newline
bitfld.long 0x184 0. "tpcc_a_intg,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
line.long 0x188 "MSS_TPCC_B_ERRAGG_MASK,"
bitfld.long 0x188 25. "tptc_b0_read_access_error,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 24. "tpcc_b_read_access_error,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 17. "tptc_b0_write_access_error,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 16. "tpcc_b_write_access_error,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 4. "tpcc_b_par_err,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 2. "tptc_b0_err,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 1. "tpcc_b_mpint,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 0. "tpcc_b_errint,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x18C "MSS_TPCC_B_ERRAGG_STATUS,"
bitfld.long 0x18C 25. "tptc_b0_read_access_error,Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x18C 24. "tpcc_b_read_access_error,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 17. "tptc_b0_write_access_error,Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x18C 16. "tpcc_b_write_access_error,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 4. "tpcc_b_par_err,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 2. "tptc_b0_err,Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x18C 1. "tpcc_b_mpint,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 0. "tpcc_b_errint,Status of Error from MSS_TPCC_B" "0,1"
line.long 0x190 "MSS_TPCC_B_ERRAGG_STATUS_RAW,"
bitfld.long 0x190 25. "tptc_b0_read_access_error,Raw Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x190 24. "tpcc_b_read_access_error,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 17. "tptc_b0_write_access_error,Raw Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x190 16. "tpcc_b_write_access_error,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 4. "tpcc_b_par_err,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 2. "tptc_b0_err,Raw Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x190 1. "tpcc_b_mpint,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 0. "tpcc_b_errint,Raw Status of Error from MSS_TPCC_B" "0,1"
line.long 0x194 "MSS_TPCC_B_INTAGG_MASK,"
bitfld.long 0x194 16. "tptc_b0,Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 8. "tpcc_b_int7,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 7. "tpcc_b_int6,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 6. "tpcc_b_int5,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 5. "tpcc_b_int4,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 4. "tpcc_b_int3,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 3. "tpcc_b_int2,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 2. "tpcc_b_int1,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 1. "tpcc_b_int0,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 0. "tpcc_b_intg,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x198 "MSS_TPCC_B_INTAGG_STATUS,"
bitfld.long 0x198 16. "tptc_b0,Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x198 8. "tpcc_b_int7,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 7. "tpcc_b_int6,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 6. "tpcc_b_int5,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 5. "tpcc_b_int4,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 4. "tpcc_b_int3,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 3. "tpcc_b_int2,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 2. "tpcc_b_int1,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 1. "tpcc_b_int0,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 0. "tpcc_b_intg,Status of Interrupt from MSS_TPCC_B" "0,1"
line.long 0x19C "MSS_TPCC_B_INTAGG_STATUS_RAW,"
bitfld.long 0x19C 16. "tptc_b0,Raw Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x19C 8. "tpcc_b_int7,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 7. "tpcc_b_int6,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 6. "tpcc_b_int5,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 5. "tpcc_b_int4,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 4. "tpcc_b_int3,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 3. "tpcc_b_int2,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 2. "tpcc_b_int1,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 1. "tpcc_b_int0,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 0. "tpcc_b_intg,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
line.long 0x1A0 "MSS_BUS_SAFETY_CTRL,"
bitfld.long 0x1A0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1A4 "MSS_CR5A_AXI_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1A4 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A4 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "MSS_CR5A_AXI_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x1A8 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A8 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1AC "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1AC 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B0 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1B0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B4 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1B8 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1BC "MSS_CR5B_AXI_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1BC 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1BC 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1BC 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "MSS_CR5B_AXI_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x1C0 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C0 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C0 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C0 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1C4 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1C4 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1C8 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1C8 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1CC "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1D0 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1D4 "MSS_CR5A_AXI_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1D4 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1D4 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D4 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1D8 "MSS_CR5A_AXI_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1D8 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D8 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D8 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1D8 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1DC "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1DC 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1DC 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1DC 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1DC 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1E0 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1E0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1E4 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1E8 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1EC "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1F0 "MSS_CR5B_AXI_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1F0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1F0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1F4 "MSS_CR5B_AXI_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1F4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1F4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1F8 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1F8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1FC "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1FC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1FC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x200 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x204 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x208 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x20C "MSS_CR5A_AXI_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x20C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x20C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x20C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x210 "MSS_CR5A_AXI_S_BUS_SAFETY_FI,"
hexmask.long.byte 0x210 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x210 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x210 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x210 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x214 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0x214 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x214 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x214 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x214 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x218 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x218 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x218 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x21C "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x220 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x224 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x228 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x22C "MSS_CR5B_AXI_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x22C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x22C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x22C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x230 "MSS_CR5B_AXI_S_BUS_SAFETY_FI,"
hexmask.long.byte 0x230 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x230 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x230 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x230 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x234 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0x234 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x234 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x234 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x234 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x238 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x238 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x238 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x23C "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x240 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x244 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x248 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x24C "MSS_TPTC_A0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x24C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x24C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x250 "MSS_TPTC_A0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x250 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x250 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x250 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x250 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x254 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x254 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x254 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x254 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x254 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x258 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x258 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x258 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x25C "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x260 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x264 "MSS_TPTC_A1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x264 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x264 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x264 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x268 "MSS_TPTC_A1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x268 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x268 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x268 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x268 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x26C "MSS_TPTC_A1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x26C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x26C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x26C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x26C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x270 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x270 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x270 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x274 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x278 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x27C "MSS_TPTC_B0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x27C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x27C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x27C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x280 "MSS_TPTC_B0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x280 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x280 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x280 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x280 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x284 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x284 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x284 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x284 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x284 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x288 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x288 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x288 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x28C "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x290 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x294 "MSS_TPTC_A0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x294 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x294 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x294 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x298 "MSS_TPTC_A0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x298 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x298 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x298 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x298 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x29C "MSS_TPTC_A0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x29C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x29C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x29C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x29C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2A0 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2A0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2A0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2A4 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2A8 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x2AC "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x2B0 "MSS_TPTC_A1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x2B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x2B4 "MSS_TPTC_A1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x2B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x2B8 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x2B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2BC "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2BC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2BC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2C0 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2C4 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x2C8 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x2CC "MSS_TPTC_B0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x2CC 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2CC 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2CC 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x2D0 "MSS_TPTC_B0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x2D0 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D0 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D0 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2D0 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x2D4 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x2D4 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D4 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D4 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D4 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2D8 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2D8 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D8 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2DC "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2E0 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x2E4 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x2E8 "HSM_TPTC_A0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x2E8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2E8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2E8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x2EC "HSM_TPTC_A0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x2EC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2EC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2EC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2EC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x2F0 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x2F0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2F4 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2F4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2F8 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2FC "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x300 "HSM_TPTC_A1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x300 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x300 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x300 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x304 "HSM_TPTC_A1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x304 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x304 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x304 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x304 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x308 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x308 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x308 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x308 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x308 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x30C "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x30C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x30C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x310 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x314 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x318 "HSM_TPTC_A0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x318 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x318 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x318 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x31C "HSM_TPTC_A0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x31C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x31C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x31C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x31C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x320 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x320 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x320 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x320 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x320 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x324 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x324 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x324 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x328 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x32C "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x330 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x334 "HSM_TPTC_A1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x334 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x334 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x334 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x338 "HSM_TPTC_A1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x338 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x338 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x338 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x338 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x33C "HSM_TPTC_A1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x33C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x33C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x33C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x33C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x340 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x340 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x340 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x344 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x348 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x34C "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x350 "MSS_QSPI_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x350 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x350 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x350 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x354 "MSS_QSPI_BUS_SAFETY_FI,"
hexmask.long.byte 0x354 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x354 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x354 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x354 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x358 "MSS_QSPI_BUS_SAFETY_ERR,"
hexmask.long.byte 0x358 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x358 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x358 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x358 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x35C "MSS_QSPI_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x35C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x35C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x360 "MSS_QSPI_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x364 "MSS_QSPI_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x368 "MSS_QSPI_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x36C "MSS_QSPI_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x370 "HSM_DTHE_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x370 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x370 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x370 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x374 "HSM_DTHE_BUS_SAFETY_FI,"
hexmask.long.byte 0x374 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x374 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x374 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x374 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x378 "HSM_DTHE_BUS_SAFETY_ERR,"
hexmask.long.byte 0x378 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x378 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x378 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x378 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x37C "HSM_DTHE_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x37C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x37C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x380 "HSM_DTHE_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x384 "HSM_DTHE_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x388 "HSM_DTHE_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x38C "HSM_DTHE_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x390 "MSS_CPSW_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x390 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x390 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x390 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x394 "MSS_CPSW_BUS_SAFETY_FI,"
hexmask.long.byte 0x394 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x394 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x394 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x394 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x398 "MSS_CPSW_BUS_SAFETY_ERR,"
hexmask.long.byte 0x398 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x398 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x398 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x398 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x39C "MSS_CPSW_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x39C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x39C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3A0 "MSS_CPSW_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x3A4 "MSS_CPSW_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x3A8 "MSS_CPSW_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3AC "MSS_CPSW_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x3B0 "MSS_MCRC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x3B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x3B4 "MSS_MCRC_BUS_SAFETY_FI,"
hexmask.long.byte 0x3B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x3B8 "MSS_MCRC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x3B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3BC "MSS_MCRC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3BC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3BC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3C0 "MSS_MCRC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x3C4 "MSS_MCRC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x3C8 "MSS_MCRC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3CC "MSS_MCRC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x3D0 "MSS_PCR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x3D0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3D0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x3D4 "MSS_PCR_BUS_SAFETY_FI,"
hexmask.long.byte 0x3D4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3D4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x3D8 "MSS_PCR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x3D8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3DC "MSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3DC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3DC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3E0 "MSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x3E4 "MSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x3E8 "MSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3EC "MSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x3F0 "MSS_PCR2_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x3F0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3F0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x3F4 "MSS_PCR2_BUS_SAFETY_FI,"
hexmask.long.byte 0x3F4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3F4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x3F8 "MSS_PCR2_BUS_SAFETY_ERR,"
hexmask.long.byte 0x3F8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3FC "MSS_PCR2_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3FC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3FC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x400 "MSS_PCR2_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x404 "MSS_PCR2_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x408 "MSS_PCR2_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x40C "MSS_PCR2_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x410 "HSM_M_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x410 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x410 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x410 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x414 "HSM_M_BUS_SAFETY_FI,"
hexmask.long.byte 0x414 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x414 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x414 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x414 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x418 "HSM_M_BUS_SAFETY_ERR,"
hexmask.long.byte 0x418 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x418 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x418 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x418 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x41C "HSM_M_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x41C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x41C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x420 "HSM_M_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x424 "HSM_M_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x428 "HSM_M_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x42C "HSM_M_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x430 "HSM_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x430 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x430 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x430 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x434 "HSM_S_BUS_SAFETY_FI,"
hexmask.long.byte 0x434 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x434 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x434 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x434 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x438 "HSM_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0x438 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x438 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x438 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x438 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x43C "HSM_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x43C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x43C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x440 "HSM_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x444 "HSM_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x448 "HSM_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x44C "HSM_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x450 "DAP_R232_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x450 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x450 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x450 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x454 "DAP_R232_BUS_SAFETY_FI,"
hexmask.long.byte 0x454 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x454 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x454 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x454 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x458 "DAP_R232_BUS_SAFETY_ERR,"
hexmask.long.byte 0x458 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x458 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x458 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x458 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x45C "DAP_R232_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x45C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x45C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x460 "DAP_R232_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x464 "DAP_R232_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x468 "DAP_R232_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x46C "DAP_R232_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x470 "MSS_L2_A_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x470 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x470 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x470 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x474 "MSS_L2_A_BUS_SAFETY_FI,"
hexmask.long.byte 0x474 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x474 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x474 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x474 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x478 "MSS_L2_A_BUS_SAFETY_ERR,"
hexmask.long.byte 0x478 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x478 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x478 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x478 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x47C "MSS_L2_A_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x47C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x47C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x480 "MSS_L2_A_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x484 "MSS_L2_A_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x488 "MSS_L2_A_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x48C "MSS_L2_A_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x490 "MSS_L2_B_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x490 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x490 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x490 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x494 "MSS_L2_B_BUS_SAFETY_FI,"
hexmask.long.byte 0x494 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x494 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x494 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x494 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x498 "MSS_L2_B_BUS_SAFETY_ERR,"
hexmask.long.byte 0x498 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x498 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x498 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x498 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x49C "MSS_L2_B_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x49C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x49C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4A0 "MSS_L2_B_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x4A4 "MSS_L2_B_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x4A8 "MSS_L2_B_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x4AC "MSS_L2_B_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x4B0 "MSS_MBOX_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x4B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4B4 "MSS_MBOX_BUS_SAFETY_FI,"
hexmask.long.byte 0x4B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x4B8 "MSS_MBOX_BUS_SAFETY_ERR,"
hexmask.long.byte 0x4B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4BC "MSS_MBOX_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4BC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4BC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4C0 "MSS_MBOX_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x4C4 "MSS_MBOX_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x4C8 "MSS_MBOX_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x4CC "MSS_MBOX_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x4D0 "MSS_SWBUF_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x4D0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4D0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4D4 "MSS_SWBUF_BUS_SAFETY_FI,"
hexmask.long.byte 0x4D4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4D4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x4D8 "MSS_SWBUF_BUS_SAFETY_ERR,"
hexmask.long.byte 0x4D8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4DC "MSS_SWBUF_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4DC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4DC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4E0 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x4E4 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x4E8 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x4EC "MSS_SWBUF_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x4F0 "MSS_GPADC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x4F0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4F0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4F4 "MSS_GPADC_BUS_SAFETY_FI,"
hexmask.long.byte 0x4F4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4F4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x4F8 "MSS_GPADC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x4F8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4FC "MSS_GPADC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4FC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4FC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x500 "MSS_GPADC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x504 "MSS_GPADC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x508 "MSS_GPADC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x50C "MSS_GPADC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x510 "MSS_BUS_SAFETY_SEC_ERR_STAT0,"
bitfld.long 0x510 31. "mss_dmmslv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 30. "mss_dmm,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 29. "gpadc,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 28. "mss_swbuf,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 27. "mss_mbox,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 26. "l2ram1,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 25. "l2ram0,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 24. "dthe,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 23. "hsm_s,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 22. "per_pcr2,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 21. "per_pcr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 20. "mcrc,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 19. "qspi,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 18. "hsm_tptc_A1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 17. "hsm_tptc_A1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 16. "hsm_tptc_A0_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 15. "hsm_tptc_A0_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 14. "mss_tptc_B1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 13. "mss_tptc_A1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 12. "mss_tptc_A0_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 11. "mss_tptc_B1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 10. "mss_tptc_A1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 9. "mss_tptc_A0_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 8. "cpsw,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 7. "hsm,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 6. "dap_rs232,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 5. "cr5b_slv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 4. "cr5a_slv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 3. "cr5b_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 2. "cr5a_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 1. "cr5b_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 0. "cr5a_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
line.long 0x514 "MSS_BUS_SAFETY_SEC_ERR_STAT1,"
bitfld.long 0x514 24. "mss_to_mdo,Bus safety single-bit-error of Node mentioned in the field" "0,1"
group.long 0x520++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x538++0xDF
line.long 0x00 "MSS_DMM_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x00 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x00 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x00 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x04 "MSS_DMM_BUS_SAFETY_FI,"
hexmask.long.byte 0x04 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x04 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x08 "MSS_DMM_BUS_SAFETY_ERR,"
hexmask.long.byte 0x08 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x0C "MSS_DMM_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x0C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x10 "MSS_DMM_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x14 "MSS_DMM_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x18 "MSS_DMM_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1C "MSS_DMM_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x20 "MSS_DMM_SLV_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x20 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x20 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x20 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x24 "MSS_DMM_SLV_BUS_SAFETY_FI,"
hexmask.long.byte 0x24 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x24 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x28 "MSS_DMM_SLV_BUS_SAFETY_ERR,"
hexmask.long.byte 0x28 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2C "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x30 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x34 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x38 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3C "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x40 "MSS_TO_MDO_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x40 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x40 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x40 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x44 "MSS_TO_MDO_BUS_SAFETY_FI,"
hexmask.long.byte 0x44 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x44 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x48 "MSS_TO_MDO_BUS_SAFETY_ERR,"
hexmask.long.byte 0x48 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4C "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x50 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x54 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x58 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x5C "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x60 "MSS_SCRP_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x60 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x60 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x60 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x64 "MSS_SCRP_BUS_SAFETY_FI,"
hexmask.long.byte 0x64 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x64 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x68 "MSS_SCRP_BUS_SAFETY_ERR,"
hexmask.long.byte 0x68 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x6C "MSS_SCRP_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x6C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x70 "MSS_SCRP_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x74 "MSS_SCRP_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x78 "MSS_SCRP_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x7C "MSS_SCRP_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x80 "MSS_CR5A_AHB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x80 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x80 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x80 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x84 "MSS_CR5A_AHB_BUS_SAFETY_FI,"
hexmask.long.byte 0x84 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x84 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x88 "MSS_CR5A_AHB_BUS_SAFETY_ERR,"
hexmask.long.byte 0x88 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x8C "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x8C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x90 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x94 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x98 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x9C "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xA0 "MSS_CR5B_AHB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xA0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xA4 "MSS_CR5B_AHB_BUS_SAFETY_FI,"
hexmask.long.byte 0xA4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xA8 "MSS_CR5B_AHB_BUS_SAFETY_ERR,"
hexmask.long.byte 0xA8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xAC "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xAC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB0 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xB4 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0xB8 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xBC "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xC0 "DMM_CTRL_REG,"
bitfld.long 0xC0 0. "dmm_pad_select," "0,1"
line.long 0xC4 "MSS_CR5A_MBOX_WRITE_DONE,"
bitfld.long 0xC4 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
newline
bitfld.long 0xC4 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
newline
bitfld.long 0xC4 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
newline
bitfld.long 0xC4 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
newline
bitfld.long 0xC4 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
newline
bitfld.long 0xC4 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
newline
bitfld.long 0xC4 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
newline
bitfld.long 0xC4 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0xC8 "MSS_CR5A_MBOX_READ_REQ,"
bitfld.long 0xC8 28. "proc_7,This is request from processor 7 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 24. "proc_6,This is request from processor 6 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 20. "proc_5,This is request from processor 5 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 16. "proc_4,This is request from processor 4 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 12. "proc_3,This is request from processor 3 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 8. "proc_2,This is request from processor 2 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 4. "proc_1,This is request from processor 1 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 0. "proc_0,This is request from processor 0 to mss_cr5a" "0,1"
line.long 0xCC "MSS_CR5A_MBOX_READ_DONE,"
bitfld.long 0xCC 28. "proc_7,This register should be written once finishing reading from CR5A's mailbox written by proc 7" "0,1"
newline
bitfld.long 0xCC 24. "proc_6,This register should be written once finishing reading from CR5A's mailbox written by proc 6" "0,1"
newline
bitfld.long 0xCC 20. "proc_5,This register should be written once finishing reading from CR5A's mailbox written by proc 5" "0,1"
newline
bitfld.long 0xCC 16. "proc_4,This register should be written once finishing reading from CR5A's mailbox written by proc 4" "0,1"
newline
bitfld.long 0xCC 12. "proc_3,This register should be written once finishing reading from CR5A's mailbox written by proc 3" "0,1"
newline
bitfld.long 0xCC 8. "proc_2,This register should be written once finishing reading from CR5A's mailbox written by proc 2" "0,1"
newline
bitfld.long 0xCC 4. "proc_1,This register should be written once finishing reading from CR5A's mailbox written by proc 1" "0,1"
newline
bitfld.long 0xCC 0. "proc_0,This register should be written once finishing reading from CR5A's mailbox written by proc 0" "0,1"
line.long 0xD0 "MSS_CR5B_MBOX_WRITE_DONE,"
bitfld.long 0xD0 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
newline
bitfld.long 0xD0 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
newline
bitfld.long 0xD0 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
newline
bitfld.long 0xD0 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
newline
bitfld.long 0xD0 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
newline
bitfld.long 0xD0 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
newline
bitfld.long 0xD0 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
newline
bitfld.long 0xD0 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0xD4 "MSS_CR5B_MBOX_READ_REQ,"
bitfld.long 0xD4 28. "proc_7,This is request from processor 7 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 24. "proc_6,This is request from processor 6 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 20. "proc_5,This is request from processor 5 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 16. "proc_4,This is request from processor 4 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 12. "proc_3,This is request from processor 3 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 8. "proc_2,This is request from processor 2 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 4. "proc_1,This is request from processor 1 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 0. "proc_0,This is request from processor 0 to mss_CR5B" "0,1"
line.long 0xD8 "MSS_CR5B_MBOX_READ_DONE,"
bitfld.long 0xD8 28. "proc_7,This register should be written once finishing reading from CR5B's mailbox written by proc 7" "0,1"
newline
bitfld.long 0xD8 24. "proc_6,This register should be written once finishing reading from CR5B's mailbox written by proc 6" "0,1"
newline
bitfld.long 0xD8 20. "proc_5,This register should be written once finishing reading from CR5B's mailbox written by proc 5" "0,1"
newline
bitfld.long 0xD8 16. "proc_4,This register should be written once finishing reading from CR5B's mailbox written by proc 4" "0,1"
newline
bitfld.long 0xD8 12. "proc_3,This register should be written once finishing reading from CR5B's mailbox written by proc 3" "0,1"
newline
bitfld.long 0xD8 8. "proc_2,This register should be written once finishing reading from CR5B's mailbox written by proc 2" "0,1"
newline
bitfld.long 0xD8 4. "proc_1,This register should be written once finishing reading from CR5B's mailbox written by proc 1" "0,1"
newline
bitfld.long 0xD8 0. "proc_0,This register should be written once finishing reading from CR5B's mailbox written by proc 0" "0,1"
line.long 0xDC "MSS_PBIST_KEY_RST,"
bitfld.long 0xDC 4.--7. "pbist_st_rst,MSS PBIST controller will be brought out of reset when value is 0xA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0xDC 0.--3. "pbist_st_key,Top PBIST Selftest Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x624++0x0F
line.long 0x00 "MSS_QSPI_CONFIG,"
bitfld.long 0x00 8.--10. "clk_loopback,Write 3'b111 to take board level loop back clock for QSPI" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "ext_clk,Write 3'b111 to external clock as QSPI baud clock source needed for DFT IO char" "0,1,2,3,4,5,6,7"
line.long 0x04 "MSS_STC_CONTROL,"
bitfld.long 0x04 0.--2. "cr5_wfi_overide,writing 3'b111 will bypass the wfi signals from R5SS" "0,1,2,3,4,5,6,7"
line.long 0x08 "MSS_CTI_TRIG_SEL,"
hexmask.long.byte 0x08 0.--7. 1. "trig8_sel,Used for selecting the trigger source for 8th trigger of MSS_CTI"
line.long 0x0C "MSS_DBGSS_CTI_TRIG_SEL,"
hexmask.long.byte 0x0C 16.--23. 1. "trig3,Used for selecting the trigger source for 3rd trigger of ONE_MCU_CTI"
newline
hexmask.long.byte 0x0C 8.--15. 1. "trig2,Used for selecting the trigger source for 2nd trigger of ONE_MCU_CTI"
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hexmask.long.byte 0x0C 0.--7. 1. "trig1,Used for selecting the trigger source for 1st trigger of ONE_MCU_CTI"
group.long 0x654++0x8B
line.long 0x00 "MSS_TPTC_ECCAGGR_CLK_CNTRL,"
bitfld.long 0x00 2. "tptc_B0,Writing '0' will gate the clock to TPTC_B0-FIFO during ECC-AGGR interaction(fault injection)" "0,1"
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bitfld.long 0x00 1. "tptc_A1,Writing '0' will gate the clock to TPTC_A1-FIFO during ECC-AGGR interaction(fault injection)" "0,1"
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bitfld.long 0x00 0. "tptc_A0,Writing '0' will gate the clock to TPTC_A0-FIFO during ECC-AGGR interaction(fault injection)" "0,1"
line.long 0x04 "MSS_PERIPH_ERRAGG_MASK0,"
bitfld.long 0x04 27. "top_mdo_wr,Mask Interrupt from TOP_MDO to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 26. "top_mdo_rd,Mask Interrupt from TOP_MDO to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 25. "rcss_rcm_wr,Mask Interrupt from RCSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 24. "rcss_rcm_rd,Mask Interrupt from RCSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 23. "rcss_ctrl_wr,Mask Interrupt from RCSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 22. "rcss_ctrl_rd,Mask Interrupt from RCSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 21. "hwa_cfg_wr,Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 20. "hwa_cfg_rd,Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 19. "dss_cm4_ctrl_wr,Mask Interrupt from DSS_CM4_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 18. "dss_cm4_ctrl_rd,Mask Interrupt from DSS_CM4_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 17. "dss_rcm_wr,Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 16. "dss_rcm_rd,Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 15. "dss_ctrl_wr,Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 14. "dss_ctrl_rd,Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 13. "hsm_ctrl_wr,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 12. "hsm_ctrl_rd,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 11. "hsm_soc_ctrl_wr,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 10. "hsm_soc_ctrl_rd,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 9. "top_aurora_wr,Mask Interrupt from TOP_AURORA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 8. "top_aurora_rd,Mask Interrupt from TOP_AURORA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 7. "top_rcm_wr,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 6. "top_rcm_rd,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 5. "top_ctrl_wr,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 4. "top_ctrl_rd,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 3. "mss_rcm_wr,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 2. "mss_rcm_rd,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 1. "mss_ctrl_wr,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 0. "mss_ctrl_rd,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x08 "MSS_PERIPH_ERRAGG_STATUS0,"
bitfld.long 0x08 27. "top_mdo_wr,Status of Interrupt from TOP_MDO Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 26. "top_mdo_rd,Status of Interrupt from TOP_MDO Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 25. "rcss_rcm_wr,Status of Interrupt from RCSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 24. "rcss_rcm_rd,Status of Interrupt from RCSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 23. "rcss_ctrl_wr,Status of Interrupt from RCSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 22. "rcss_ctrl_rd,Status of Interrupt from RCSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 21. "hwa_cfg_wr,Status of Interrupt from HWA_CFG Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 20. "hwa_cfg_rd,Status of Interrupt from HWA_CFG Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 19. "dss_cm4_ctrl_wr,Status of Interrupt from DSS_CM4_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 18. "dss_cm4_ctrl_rd,Status of Interrupt from DSS_CM4_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 17. "dss_rcm_wr,Status of Interrupt from DSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 16. "dss_rcm_rd,Status of Interrupt from DSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 15. "dss_ctrl_wr,Status of Interrupt from DSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 14. "dss_ctrl_rd,Status of Interrupt from DSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 13. "hsm_ctrl_wr,Status of Interrupt from HSM_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 12. "hsm_ctrl_rd,Status of Interrupt from HSM_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 11. "hsm_soc_ctrl_wr,Status of Interrupt from HSM_SOC_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 10. "hsm_soc_ctrl_rd,Status of Interrupt from HSM_SOC_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 9. "top_aurora_wr,Status of Interrupt from TOP_AURORA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 8. "top_aurora_rd,Status of Interrupt from TOP_AURORA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 7. "top_rcm_wr,Status of Interrupt from TOP_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 6. "top_rcm_rd,Status of Interrupt from TOP_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 5. "top_ctrl_wr,Status of Interrupt from TOP_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 4. "top_ctrl_rd,Status of Interrupt from TOP_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 3. "mss_rcm_wr,Status of Interrupt from MSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 2. "mss_rcm_rd,Status of Interrupt from MSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 1. "mss_ctrl_wr,Status of Interrupt from MSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 0. "mss_ctrl_rd,Status of Interrupt from MSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
line.long 0x0C "MSS_PERIPH_ERRAGG_STATUS_RAW0,"
bitfld.long 0x0C 27. "top_mdo_wr,Raw Status of Interrupt from TOP_MDO" "0,1"
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bitfld.long 0x0C 26. "top_mdo_rd,Raw Status of Interrupt from TOP_MDO" "0,1"
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bitfld.long 0x0C 25. "rcss_rcm_wr,Raw Status of Interrupt from RCSS_RCM" "0,1"
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bitfld.long 0x0C 24. "rcss_rcm_rd,Raw Status of Interrupt from RCSS_RCM" "0,1"
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bitfld.long 0x0C 23. "rcss_ctrl_wr,Raw Status of Interrupt from RCSS_CTRL" "0,1"
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bitfld.long 0x0C 22. "rcss_ctrl_rd,Raw Status of Interrupt from RCSS_CTRL" "0,1"
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bitfld.long 0x0C 21. "hwa_cfg_wr,Raw Status of Interrupt from HWA_CFG" "0,1"
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bitfld.long 0x0C 20. "hwa_cfg_rd,Raw Status of Interrupt from HWA_CFG" "0,1"
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bitfld.long 0x0C 19. "dss_cm4_ctrl_wr,Raw Status of Interrupt from DSS_CM4_CTRL" "0,1"
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bitfld.long 0x0C 18. "dss_cm4_ctrl_rd,Raw Status of Interrupt from DSS_CM4_CTRL" "0,1"
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bitfld.long 0x0C 17. "dss_rcm_wr,Raw Status of Interrupt from DSS_RCM" "0,1"
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bitfld.long 0x0C 16. "dss_rcm_rd,Raw Status of Interrupt from DSS_RCM" "0,1"
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bitfld.long 0x0C 15. "dss_ctrl_wr,Raw Status of Interrupt from DSS_CTRL" "0,1"
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bitfld.long 0x0C 14. "dss_ctrl_rd,Raw Status of Interrupt from DSS_CTRL" "0,1"
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bitfld.long 0x0C 13. "hsm_ctrl_wr,Raw Status of Interrupt from HSM_CTRL" "0,1"
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bitfld.long 0x0C 12. "hsm_ctrl_rd,Raw Status of Interrupt from HSM_CTRL" "0,1"
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bitfld.long 0x0C 11. "hsm_soc_ctrl_wr,Raw Status of Interrupt from HSM_SOC_CTRL" "0,1"
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bitfld.long 0x0C 10. "hsm_soc_ctrl_rd,Raw Status of Interrupt from HSM_SOC_CTRL" "0,1"
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bitfld.long 0x0C 9. "top_aurora_wr,Raw Status of Interrupt from TOP_AURORA" "0,1"
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bitfld.long 0x0C 8. "top_aurora_rd,Raw Status of Interrupt from TOP_AURORA" "0,1"
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bitfld.long 0x0C 7. "top_rcm_wr,Raw Status of Interrupt from TOP_RCM" "0,1"
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bitfld.long 0x0C 6. "top_rcm_rd,Raw Status of Interrupt from TOP_RCM" "0,1"
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bitfld.long 0x0C 5. "top_ctrl_wr,Raw Status of Interrupt from TOP_CTRL" "0,1"
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bitfld.long 0x0C 4. "top_ctrl_rd,Raw Status of Interrupt from TOP_CTRL" "0,1"
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bitfld.long 0x0C 3. "mss_rcm_wr,Raw Status of Interrupt from MSS_RCM" "0,1"
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bitfld.long 0x0C 2. "mss_rcm_rd,Raw Status of Interrupt from MSS_RCM" "0,1"
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bitfld.long 0x0C 1. "mss_ctrl_wr,Raw Status of Interrupt from MSS_CTRL" "0,1"
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bitfld.long 0x0C 0. "mss_ctrl_rd,Raw Status of Interrupt from MSS_CTRL" "0,1"
line.long 0x10 "MSS_PERIPH_ERRAGG_MASK1,"
bitfld.long 0x10 16. "mpu_rd_hsm,Mask Interrupt from MPU_DSS_HSM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 15. "mpu_rd_dss_mbox,Mask Interrupt from MPU_DSS_MBOX to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 14. "mpu_rd_dss_hwa_proc,Mask Interrupt from MPU_DSS_HWA_PROC to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x10 13. "mpu_rd_dss_hwa_dma1,Mask Interrupt from MPU_DSS_HWA_DMA1 to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 12. "mpu_rd_dss_hwa_dma0,Mask Interrupt from MPU_DSS_HWA_DMA0 to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 11. "mpu_rd_dss_l3_bankd,Mask Interrupt from MPU_DSS_L3_BANKD to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 10. "mpu_rd_dss_l3_bankc,Mask Interrupt from MPU_DSS_L3_BANKC to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 9. "mpu_rd_dss_l3_bankb,Mask Interrupt from MPU_DSS_L3_BANKB to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 8. "mpu_rd_dss_l3_banka,Mask Interrupt from MPU_DSS_L3_BANKA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x10 7. "mpu_rd_mss_cr5b_axis,Mask Interrupt from MPU_MSS_CR5B_AXIS to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x10 6. "mpu_rd_mss_cr5a_axis,Mask Interrupt from MPU_MSS_CR5A_AXIS to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 5. "mpu_rd_mss_qspi,Mask Interrupt from MPU_MSS_QSPI to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 4. "mpu_rd_mss_pcra,Mask Interrupt from MPU_MSS_PCRA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 3. "mpu_rd_mss_mbox,Mask Interrupt from MPU_MSS_MBOX to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 2. "mpu_rd_hsm_dthe,Mask Interrupt from MPU_HSM_DTHE to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 1. "mpu_rd_mss_l2_bankb,Mask Interrupt from MPU_MSS_L2_BANKB to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 0. "mpu_rd_mss_l2_banka,Mask Interrupt from MPU_MSS_L2_BANKA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x14 "MSS_PERIPH_ERRAGG_STATUS1,"
bitfld.long 0x14 16. "mpu_rd_hsm,Status of Interrupt from MPU_HSM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 15. "mpu_rd_dss_mbox,Status of Interrupt from MPU_DSS_MBOX Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 14. "mpu_rd_dss_hwa_proc,Status of Interrupt from MPU_DSS_HWA_PROC Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 13. "mpu_rd_dss_hwa_dma1,Status of Interrupt from MPU_DSS_HWA_DMA1 Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 12. "mpu_rd_dss_hwa_dma0,Status of Interrupt from MPU_DSS_HWA_DMA0 Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 11. "mpu_rd_dss_l3_bankd,Status of Interrupt from MPU_DSS_L3_BANKD Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 10. "mpu_rd_dss_l3_bankc,Status of Interrupt from MPU_DSS_L3_BANKC Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 9. "mpu_rd_dss_l3_bankb,Status of Interrupt from MPU_DSS_L3_BANKB Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 8. "mpu_rd_dss_l3_banka,Status of Interrupt from MPU_DSS_L3_BANKA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 7. "mpu_rd_mss_cr5b_axis,Status of Interrupt from MPU_MSS_CR5B_AXIS Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x14 6. "mpu_rd_mss_cr5a_axis,Status of Interrupt from MPU_MSS_CR5A_AXIS Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 5. "mpu_rd_mss_qspi,Status of Interrupt from MPU_MSS_QSPI Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 4. "mpu_rd_mss_pcra,Status of Interrupt from MPU_MSS_PCRA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 3. "mpu_rd_mss_mbox,Status of Interrupt from MPU_MSS_MBOX Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 2. "mpu_rd_hsm_dthe,Status of Interrupt from MPU_HSM_DTHE Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 1. "mpu_rd_mss_l2_bankb,Status of Interrupt from MPU_MSS_L2_BANKB Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 0. "mpu_rd_mss_l2_banka,Status of Interrupt from MPU_MSS_L2_BANKA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
line.long 0x18 "MSS_PERIPH_ERRAGG_STATUS_RAW1,"
bitfld.long 0x18 16. "mpu_rd_hsm,Raw Status of Interrupt from MPU_HSM" "0,1"
newline
bitfld.long 0x18 15. "mpu_rd_dss_mbox,Raw Status of Interrupt from MPU_DSS_MBOX" "0,1"
newline
bitfld.long 0x18 14. "mpu_rd_dss_hwa_proc,Raw Status of Interrupt from MPU_DSS_HWA_PROC" "0,1"
newline
bitfld.long 0x18 13. "mpu_rd_dss_hwa_dma1,Raw Status of Interrupt from MPU_DSS_HWA_DMA1" "0,1"
newline
bitfld.long 0x18 12. "mpu_rd_dss_hwa_dma0,Raw Status of Interrupt from MPU_DSS_HWA_DMA0" "0,1"
newline
bitfld.long 0x18 11. "mpu_rd_dss_l3_bankd,Raw Status of Interrupt from MPU_DSS_L3_BANKD" "0,1"
newline
bitfld.long 0x18 10. "mpu_rd_dss_l3_bankc,Raw Status of Interrupt from MPU_DSS_L3_BANKC" "0,1"
newline
bitfld.long 0x18 9. "mpu_rd_dss_l3_bankb,Raw Status of Interrupt from MPU_DSS_L3_BANKB" "0,1"
newline
bitfld.long 0x18 8. "mpu_rd_dss_l3_banka,Raw Status of Interrupt from MPU_DSS_L3_BANKA" "0,1"
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bitfld.long 0x18 7. "mpu_rd_mss_cr5b_axis,Raw Status of Interrupt from MPU_MSS_CR5B_AXIS" "0,1"
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bitfld.long 0x18 6. "mpu_rd_mss_cr5a_axis,Raw Status of Interrupt from MPU_MSS_CR5A_AXIS" "0,1"
newline
bitfld.long 0x18 5. "mpu_rd_mss_qspi,Raw Status of Interrupt from MPU_MSS_QSPI" "0,1"
newline
bitfld.long 0x18 4. "mpu_rd_mss_pcra,Raw Status of Interrupt from MPU_MSS_PCRA" "0,1"
newline
bitfld.long 0x18 3. "mpu_rd_mss_mbox,Raw Status of Interrupt from MPU_MSS_MBOX" "0,1"
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bitfld.long 0x18 2. "mpu_rd_hsm_dthe,Raw Status of Interrupt from MPU_HSM_D" "0,1"
newline
bitfld.long 0x18 1. "mpu_rd_mss_l2_bankb,Raw Status of Interrupt from MPU_MSS_L2_BANKB" "0,1"
newline
bitfld.long 0x18 0. "mpu_rd_mss_l2_banka,Raw Status of Interrupt from MPU_MSS_L2_BANKA" "0,1"
line.long 0x1C "MSS_DMM_EVENT0_REG,"
bitfld.long 0x1C 28. "event_sel3,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x1C 24. "event_trig3,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
newline
bitfld.long 0x1C 20. "event_sel2,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x1C 16. "event_trig2,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
newline
bitfld.long 0x1C 12. "event_sel1,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x1C 8. "event_trig1,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
newline
bitfld.long 0x1C 4. "event_sel0,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
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bitfld.long 0x1C 0. "event_trig0,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
line.long 0x20 "MSS_DMM_EVENT1_REG,"
bitfld.long 0x20 28. "event_sel7,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x20 24. "event_trig7,DMM trigger for RCSS_CSI2A_SOF_INT1" "0,1"
newline
bitfld.long 0x20 20. "event_sel6,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x20 16. "event_trig6,DMM trigger for RCSS_CSI2A_SOF_INT1" "0,1"
newline
bitfld.long 0x20 12. "event_sel5,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x20 8. "event_trig5,DMM trigger for RCSS_CSI2A_SOF_INT1" "0,1"
newline
bitfld.long 0x20 4. "event_sel4,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
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bitfld.long 0x20 0. "event_trig4,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
line.long 0x24 "MSS_DMM_EVENT2_REG,"
bitfld.long 0x24 28. "event_sel11,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 24. "event_trig11,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x24 20. "event_sel10,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 16. "event_trig10,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x24 12. "event_sel9,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 8. "event_trig9,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x24 4. "event_sel8,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 0. "event_trig8,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
line.long 0x28 "MSS_DMM_EVENT3_REG,"
bitfld.long 0x28 28. "event_sel15,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 24. "event_trig15,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x28 20. "event_sel14,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 16. "event_trig14,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x28 12. "event_sel13,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 8. "event_trig13,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x28 4. "event_sel12,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 0. "event_trig12,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
line.long 0x2C "MSS_DMM_EVENT4_REG,"
bitfld.long 0x2C 28. "event_sel19,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 24. "event_trig19,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x2C 20. "event_sel18,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 16. "event_trig18,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x2C 12. "event_sel17,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 8. "event_trig17,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x2C 4. "event_sel16,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 0. "event_trig16,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
line.long 0x30 "MSS_DMM_EVENT5_REG,"
bitfld.long 0x30 28. "event_sel23,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 24. "event_trig23,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x30 20. "event_sel22,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 16. "event_trig22,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x30 12. "event_sel21,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 8. "event_trig21,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x30 4. "event_sel20,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 0. "event_trig20,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
line.long 0x34 "MSS_DMM_EVENT6_REG,"
bitfld.long 0x34 28. "event_sel27,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 24. "event_trig27,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
newline
bitfld.long 0x34 20. "event_sel26,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 16. "event_trig26,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
newline
bitfld.long 0x34 12. "event_sel25,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 8. "event_trig25,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
newline
bitfld.long 0x34 4. "event_sel24,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 0. "event_trig24,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
line.long 0x38 "MSS_DMM_EVENT7_REG,"
bitfld.long 0x38 28. "event_sel31,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 24. "event_trig31,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
newline
bitfld.long 0x38 20. "event_sel30,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 16. "event_trig30,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
newline
bitfld.long 0x38 12. "event_sel29,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 8. "event_trig29,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
newline
bitfld.long 0x38 4. "event_sel28,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 0. "event_trig28,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
line.long 0x3C "MSS_DMM_EVENT8_REG,"
bitfld.long 0x3C 28. "event_sel35,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 24. "event_trig35,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
newline
bitfld.long 0x3C 20. "event_sel34,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 16. "event_trig34,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
newline
bitfld.long 0x3C 12. "event_sel33,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 8. "event_trig33,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
newline
bitfld.long 0x3C 4. "event_sel32,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 0. "event_trig32,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
line.long 0x40 "MSS_DMM_EVENT9_REG,"
bitfld.long 0x40 28. "event_sel39,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 24. "event_trig39,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
newline
bitfld.long 0x40 20. "event_sel38,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 16. "event_trig38,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
newline
bitfld.long 0x40 12. "event_sel37,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 8. "event_trig37,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
newline
bitfld.long 0x40 4. "event_sel36,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 0. "event_trig36,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
line.long 0x44 "MSS_DMM_EVENT10_REG,"
bitfld.long 0x44 28. "event_sel43,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 24. "event_trig43,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
newline
bitfld.long 0x44 20. "event_sel42,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 16. "event_trig42,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
newline
bitfld.long 0x44 12. "event_sel41,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 8. "event_trig41,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
newline
bitfld.long 0x44 4. "event_sel40,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 0. "event_trig40,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
line.long 0x48 "MSS_DMM_EVENT11_REG,"
bitfld.long 0x48 28. "event_sel47,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 24. "event_trig47,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
newline
bitfld.long 0x48 20. "event_sel46,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 16. "event_trig46,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
newline
bitfld.long 0x48 12. "event_sel45,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 8. "event_trig45,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
newline
bitfld.long 0x48 4. "event_sel44,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 0. "event_trig44,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
line.long 0x4C "MSS_DMM_EVENT12_REG,"
bitfld.long 0x4C 28. "event_sel51,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 24. "event_trig51,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x4C 20. "event_sel50,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 16. "event_trig50,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x4C 12. "event_sel49,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 8. "event_trig49,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x4C 4. "event_sel48,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 0. "event_trig48,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
line.long 0x50 "MSS_DMM_EVENT13_REG,"
bitfld.long 0x50 28. "event_sel55,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 24. "event_trig55,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x50 20. "event_sel54,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 16. "event_trig54,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x50 12. "event_sel53,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 8. "event_trig53,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x50 4. "event_sel52,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 0. "event_trig52,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
line.long 0x54 "MSS_DMM_EVENT14_REG,"
bitfld.long 0x54 28. "event_sel59,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 24. "event_trig59,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x54 20. "event_sel58,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 16. "event_trig58,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x54 12. "event_sel57,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 8. "event_trig57,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x54 4. "event_sel56,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 0. "event_trig56,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
line.long 0x58 "MSS_DMM_EVENT15_REG,"
bitfld.long 0x58 28. "event_sel63,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 24. "event_trig63,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x58 20. "event_sel62,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 16. "event_trig62,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x58 12. "event_sel61,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 8. "event_trig61,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x58 4. "event_sel60,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 0. "event_trig60,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
line.long 0x5C "MSS_TPTC_BOUNDARY_CFG,"
bitfld.long 0x5C 16.--21. "tptc_b0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_B0 Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x5C 8.--13. "tptc_a1_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A1 Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x5C 0.--5. "tptc_a0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A0 Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x60 "MSS_TPTC_XID_REORDER_CFG,"
bitfld.long 0x60 16. "tptc_b0_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x60 8. "tptc_a1_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x60 0. "tptc_a0_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A0" "0,1"
line.long 0x64 "GPADC_CTRL,"
bitfld.long 0x64 8.--12. "gpadc_trigin_sel,Writing below decimal values to this regiter will select corresponding interrupt as GPADC trigger source" "GPIO_0,GPIO_1,GPIO_2,GPIO_3,RSS_CSI2A_EOL_INT,RSS_CSI2A_SOF_INT0,RSS_CSI2A_SOF_INT1,RSS_CSI2A_SOF_INT,RSS_CSI2B_SOF_INT,HW_Sync_FE1,HW_Sync_FE2,DSS_RTIA_1,DSS_RTIB_1,MSS_RTIA_INT1,MSS_RTIB_INT1,MMR based SW trigger,?..."
newline
bitfld.long 0x64 0. "gpadc_sw_trig,Writing 1'b1 will give MMR based SW trigger to GPADC" "0,1"
line.long 0x68 "HW_Sync_FE_CTRL,"
bitfld.long 0x68 8. "fe2_sel,Writing" "Selects MCANA filter event as HW_Sync_FE2,Selects MCANB filter event as HW_Sync_FE2"
newline
bitfld.long 0x68 0. "fe1_sel,Writing" "Selects MCANA filter event as HW_Sync_FE1,Selects MCANB filter event as HW_Sync_FE1"
line.long 0x6C "DEBUGSS_CSETB_FLUSH,"
rbitfld.long 0x6C 10. "CSETB_FULL,When HIGH indicates that the ETB RAM has overflowed or wrapped around to address zero" "0,1"
newline
rbitfld.long 0x6C 9. "CSETB_ACQ_COMPLETE,When HIGH indicates that trace acquisition is complete by ETB that is the trigger counter is at zero" "0,1"
newline
rbitfld.long 0x6C 8. "CSETB_FLUSHINACK,Return acknowledgement to CSETBFLUSHIN" "0,1"
newline
bitfld.long 0x6C 0. "CSETB_FLUSHIN,External control used to assert the ATB signal AFVALIDS and drain any historical FIFO information on the bus" "0,1"
line.long 0x70 "ANALOG_WU_STATUS_REG_POLARITY_INV,"
line.long 0x74 "ANALOG_CLK_STATUS_REG_POLARITY_INV,"
line.long 0x78 "ANALOG_WU_STATUS_REG_GRP1_MASK,"
line.long 0x7C "ANALOG_CLK_STATUS_REG_GRP1_MASK,"
line.long 0x80 "ANALOG_WU_STATUS_REG_GRP2_MASK,"
line.long 0x84 "ANALOG_CLK_STATUS_REG_GRP2_MASK,"
line.long 0x88 "NERROR_MASK,"
bitfld.long 0x88 0.--2. "mask,writing 3'b111 will mask the Nerror propagation to pad Writing 3'b000 will unmask the Nerror propagation to pad" "0,1,2,3,4,5,6,7"
group.long 0x800++0x13
line.long 0x00 "R5_CONTROL,"
bitfld.long 0x00 24.--26. "rom_wait_state,writing '111' enables a single cycle wait state with respect to CR5A_clk for rom access" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "reset_fsm_trigger,writing 3'b111 will trigger the reset FSM" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "lock_step_switch_wait,writing 3'b111 ensures switch happens only after R5SS reset" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "lock_step,writing 3'b000 ensures R5 to be in Dual-Core mode" "0,1,2,3,4,5,6,7"
line.long 0x04 "R5_ROM_ECLIPSE,"
bitfld.long 0x04 8.--10. "memswap_wait,writing 3'b111 ensures ROM-Eclipsing happens only after R5SS reset" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--2. "memswap,writing '111' ensures eclipsing of CR5A_ROM immediately if memswap_wait is not set" "0,1,2,3,4,5,6,7"
line.long 0x08 "R5_COREA_HALT,"
bitfld.long 0x08 0.--2. "halt,writing '000' will unhalt CR5A" "0,1,2,3,4,5,6,7"
line.long 0x0C "R5_COREB_HALT,"
bitfld.long 0x0C 0.--2. "halt,writing '000' will unhalt for CR5B" "0,1,2,3,4,5,6,7"
line.long 0x10 "R5_STATUS_REG,"
bitfld.long 0x10 8. "lock_step,Reading" "confirms R5SS is in Dual-core mode,confirms R5SS is in lockstep mode"
newline
bitfld.long 0x10 0. "memswap,reading" "0,1"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x634)++0x03
line.long 0x00 "MSS_BOOT_INFO_REG$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x618)++0x03
line.long 0x00 "MSS_PBIST_REG$1,"
repeat.end
repeat 7. (list 0. 1. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x518)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_DCCA (MSS DCCA Module Registers)"
base ad:0x2F79C00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DCCB (MSS DCCB Module Registers)"
base ad:0x2F79D00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DCCC (MSS DCCC Module Registers)"
base ad:0x2F79E00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DCCD (MSS DCCD Module Registers)"
base ad:0x2F79F00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DMM_A (MSS DMMA Module Registers)"
base ad:0x3F79C00
group.long 0x00++0x8F
line.long 0x00 "GLBCTRL,Sets the global configuration of the module"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "BUSY,BUSY User and privilege mode (read)" "the DMM does not currently receive data and has..,the module is currently receiving data or has.."
newline
rbitfld.long 0x00 19.--23. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18. "CONTCLK,CONTCLK" "suspend RTPCLK between packets,enable free running clock between packets"
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bitfld.long 0x00 17. "COS,COS" "disable data reception while in suspend mode,enable data reception while in suspend mode"
bitfld.long 0x00 16. "RESET,RESET This bit resets the statemachine and the registers to its reset value except the RESET bit itself" "no reset of DMM module,reset DMM module to its reset state"
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rbitfld.long 0x00 11.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9.--10. "DDM_WIDTH,DDM_WIDTH: Packet Width in Direct Data Mode User and privilege mode read and write operation: Bit Encoding Transfer Size 00 8 bit 01 16 bit 10 32 bit 11 Reserved" "0,1,2,3"
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bitfld.long 0x00 8. "TM_DMM,TM_DMM: Packet Format If this bit is set the DMM module assumes to receive packets by the Direct Data Mode" "enable Trace Mode,enable Direct Data Mode"
rbitfld.long 0x00 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "ONOFF,ON/OFF User and privilege mode (read)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTSET       ,Enables interrupts"
hexmask.long.word 0x04 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x04 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Set This enables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Set This enables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,enable interrupt when BMM HRESP = Error"
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bitfld.long 0x04 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Set This enables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Set This enables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,enable interrupt"
bitfld.long 0x04 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Set This enables the interrupt generation in case of an error condition" "no influence on bit,enable interrupt (sets corresponding bit in.."
line.long 0x08 "INTCLR,Disables interrupts"
hexmask.long.word 0x08 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x08 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Clear This disables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Clear This disables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,disable interrupt on BMM HRESP = Error"
newline
bitfld.long 0x08 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Clear This disables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Clear This disables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Clear This disables the interrupt generation in case of an error condition" "no influence on bit,disable interrupt (clears corresponding bit in.."
line.long 0x0C "INTLVL,Selects high or low priority interrupt level"
hexmask.long.word 0x0C 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x0C 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
line.long 0x10 "INTFLAG,Interrupt Flags"
hexmask.long.word 0x10 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x10 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 7. "BUSERROR,BUSERROR: BMM Bus Error Response This bit is set when the BMM HRESP = Error" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
line.long 0x14 "OFF1,Interrupt offset for high priority level"
hexmask.long 0x14 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x14 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "OFF2,Interrupt offset for low priority level"
hexmask.long 0x18 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x18 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "DDMDEST,Configuration of Buffer for Direct Data Mode"
line.long 0x20 "DDMBL,Defines the blocksize for the buffer in Direct Data Mode"
hexmask.long 0x20 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x20 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DDMPT,Pointer to the last written entry in the buffer"
hexmask.long.tbyte 0x24 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x24 0.--14. 1. "POINTER,POINTER These bits hold the pointer to the next entry to be written in the buffer"
line.long 0x28 "INTPT,Programmable Interrupt Pointer"
hexmask.long.tbyte 0x28 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x28 0.--14. 1. "INTPT,INTPT: Interrupt Pointer When the buffer pointer (DMMDDMPT) matches the programmed value in DMMINTPT and the PROG_BUF interrupt is set a interrupt is generated"
line.long 0x2C "DEST0REG1,Defines Region 1 for Destination 0"
hexmask.long.word 0x2C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x2C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x30 "DEST0BL1,Defines the blocksize for the buffer for Destination 0 Region 1"
hexmask.long 0x30 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x30 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DEST0REG2,Defines Region 2 for Destination 0"
hexmask.long.word 0x34 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x34 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x38 "DEST0BL2,Defines the blocksize for the buffer for Destination 0 Region 2"
hexmask.long 0x38 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x38 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "DEST1REG1,Defines Region 1 for Destination1"
hexmask.long.word 0x3C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x3C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x40 "DEST1BL1,Defines the blocksize for the buffer for Destination 1 Region 1"
hexmask.long 0x40 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x40 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "DEST1REG2,Defines Region 2 for Destination 1"
hexmask.long.word 0x44 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x44 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x48 "DEST1BL2,Defines the blocksize for the buffer for Destination 1 Region 2"
hexmask.long 0x48 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x48 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "DEST2REG1,Defines Region 1 for Destination 2"
hexmask.long.word 0x4C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x4C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x50 "DEST2BL1,Defines the blocksize for the buffer for Destination 2 Region 1"
hexmask.long 0x50 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x50 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "DEST2REG2,Defines Region 2 for Destination 2"
hexmask.long.word 0x54 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x54 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x58 "DEST2BL2,Defines the blocksize for the buffer for Destination 2 Region 2"
hexmask.long 0x58 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x58 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "DEST3REG1,Defines Region 1 for Destination 3"
hexmask.long.word 0x5C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x5C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x60 "DEST3BL1,Defines the blocksize for the buffer for Destination 3 Region 1"
hexmask.long 0x60 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x60 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "DEST3REG2,Defines Region 2 for Destination 3"
hexmask.long.word 0x64 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x64 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x68 "DEST3BL2,Defines the blocksize for the buffer for Destination 3 Region 2"
hexmask.long 0x68 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x68 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "DMMPC0,Defines functional or GIO mode of pins"
hexmask.long.word 0x6C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x6C 18. "ENAFUNC,ENAFUNC: Functional mode of DMMENA pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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abitfld.long 0x6C 2.--17. "DATAxFUNC,DATAxFUNC: Functional mode of DMMDATA[x] pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "0x0000=Pin is used in GIO mode,0x0001=Pin is used in Functional model mode"
bitfld.long 0x6C 1. "CLKFUNC,CLKFUNC: Functional mode of DMMCLK pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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bitfld.long 0x6C 0. "SYNCFUNC,SYNCFUNC: Functional mode of DMMSYNC pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
line.long 0x70 "DMMPC1,Defines direction of pins"
hexmask.long.word 0x70 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x70 18. "ENADIR,ENADIR: Direction of DMMENA pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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abitfld.long 0x70 2.--17. "DATAxDIR,DATAxDIR: Direction of DMMDATA[x] pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "0x0000=Pin is set to input,0x0001=Pin is set to output"
bitfld.long 0x70 1. "CLKDIR,CLKDIR: Direction of DMMCLK pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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bitfld.long 0x70 0. "SYNCDIR,SYNCDIR: Direction of DMMSYNC pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
line.long 0x74 "DMMPC2,Input level of pins"
hexmask.long.word 0x74 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x74 18. "ENAIN,ENAIN: DMMENA input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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abitfld.long 0x74 2.--17. "DATAxIN,DATAxIN: DMMDATA[x] input This bit reflects the state of the pin in all modes User and privilege mode (read)" "0x0000=Logic low (input voltage is VIL or lower),0x0001=Logic high (input voltage is VIH or.."
bitfld.long 0x74 1. "CLKIN,CLKIN: DMMCLK input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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bitfld.long 0x74 0. "SYNCIN,SYNCIN: DMMSYNC input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
line.long 0x78 "DMMPC3,Sets pins to high or low"
hexmask.long.word 0x78 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x78 18. "ENAOUT,ENAOUT: Output state of DMMENA pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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abitfld.long 0x78 2.--17. "DATAxOUT,DATAxOUT: Output state of DMMDATA[x] pin This bit sets the pin to logic low or high level User and privilege mode (read)" "0x0000=Logic low (output voltage is set to VOL..,0x0001=Logic high (output voltage is set to VOH.."
bitfld.long 0x78 1. "CLKOUT,CLKOUT: Output state of DMMCLK pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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bitfld.long 0x78 0. "SYNCOUT,SYNCOUT: Output state of DMMSYNC pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
line.long 0x7C "DMMPC4,Sets pins to high"
hexmask.long.word 0x7C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x7C 18. "ENASET,ENASET: Sets output state of DMMENA pin to logic high Value in the ENASET bit sets the data output control register bit to 1 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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abitfld.long 0x7C 2.--17. "DATAxSET,DATAxSET: Sets output state of DMMDATA[x] pin to logic high Value in the DATAxSET bit sets the data output control register bit to 1 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=Sets the pin to Logic high (output.."
bitfld.long 0x7C 1. "CLKSET,CLKSET: Sets output state of DMMCLK pin to logic high Value in the CLKSET bit sets the data output control register bit to 1 regardless of the current value in the CLKOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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bitfld.long 0x7C 0. "SYNCSET,SYNCSET: Sets output state of DMMSYNC pin logic high Value in the SYNCSET bit sets the data output control register bit to 1 regardless of the current value in the SYNCOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
line.long 0x80 "DMMPC5,Sets pins to low"
hexmask.long.word 0x80 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x80 18. "ENACLR,ENACLR: Sets output state of DMMENA pin to logic low Value in the ENACLR bit clears the data output control register bit to 0 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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abitfld.long 0x80 2.--17. "DATAxCLR,DATAxCLR: Sets output state of DMMDATA[x] pin to logic low Value in the DATAxCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=clears the pin to logic low (output.."
bitfld.long 0x80 1. "CLKCLR,CLKCLR: Sets output state of DMMCLK pin to logic low Value in the CLKCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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bitfld.long 0x80 0. "SYNCCLR,SYNCCLR: Sets output state of DMMSYNC pin to logic low Value in the SYNCCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
line.long 0x84 "DMMPC6,Configures open drain functionality of pin"
hexmask.long.word 0x84 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x84 18. "ENAPDR,ENAPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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abitfld.long 0x84 2.--17. "DATAxPDR,DATAxPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "0x0000=configures pin as push/pull,0x0001=configures pin as open drain"
bitfld.long 0x84 1. "CLKPDR,CLKPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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bitfld.long 0x84 0. "SYNCPDR,SYNCPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
line.long 0x88 "DMMPC7,Enables/Disables pullup/pulldown structure of pin"
hexmask.long.word 0x88 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x88 18. "ENAPDIS,ENAPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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abitfld.long 0x88 2.--17. "DATAxPDIS,DATAxPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "0x0000=enables pullup/pulldown functionality,0x0001=disables pullup/pulldown functionality"
bitfld.long 0x88 1. "CLKPDIS,CLKPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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bitfld.long 0x88 0. "SYNCPDIS,SYNCPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
line.long 0x8C "DMMPC8,Enables pullup or pulldown structure of pin"
hexmask.long.word 0x8C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x8C 18. "ENAPSEL,ENAPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
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abitfld.long 0x8C 2.--17. "DATAxPSEL,DATAxPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "0x0000=enables pulldown functionality,0x0001=enables pullup functionality"
bitfld.long 0x8C 1. "CLKPDSEL,CLKPDSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
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bitfld.long 0x8C 0. "SYNCPSEL,SYNCPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
width 0x0B
tree.end
tree "MSS_DMM_B (MSS DMMB Module Registers)"
base ad:0x3F79E00
group.long 0x00++0x8F
line.long 0x00 "GLBCTRL,Sets the global configuration of the module"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "BUSY,BUSY User and privilege mode (read)" "the DMM does not currently receive data and has..,the module is currently receiving data or has.."
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rbitfld.long 0x00 19.--23. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18. "CONTCLK,CONTCLK" "suspend RTPCLK between packets,enable free running clock between packets"
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bitfld.long 0x00 17. "COS,COS" "disable data reception while in suspend mode,enable data reception while in suspend mode"
bitfld.long 0x00 16. "RESET,RESET This bit resets the statemachine and the registers to its reset value except the RESET bit itself" "no reset of DMM module,reset DMM module to its reset state"
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rbitfld.long 0x00 11.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9.--10. "DDM_WIDTH,DDM_WIDTH: Packet Width in Direct Data Mode User and privilege mode read and write operation: Bit Encoding Transfer Size 00 8 bit 01 16 bit 10 32 bit 11 Reserved" "0,1,2,3"
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bitfld.long 0x00 8. "TM_DMM,TM_DMM: Packet Format If this bit is set the DMM module assumes to receive packets by the Direct Data Mode" "enable Trace Mode,enable Direct Data Mode"
rbitfld.long 0x00 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "ONOFF,ON/OFF User and privilege mode (read)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTSET       ,Enables interrupts"
hexmask.long.word 0x04 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x04 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Set This enables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Set This enables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,enable interrupt when BMM HRESP = Error"
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bitfld.long 0x04 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Set This enables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Set This enables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,enable interrupt"
bitfld.long 0x04 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Set This enables the interrupt generation in case of an error condition" "no influence on bit,enable interrupt (sets corresponding bit in.."
line.long 0x08 "INTCLR,Disables interrupts"
hexmask.long.word 0x08 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x08 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Clear This disables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Clear This disables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,disable interrupt on BMM HRESP = Error"
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bitfld.long 0x08 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Clear This disables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Clear This disables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Clear This disables the interrupt generation in case of an error condition" "no influence on bit,disable interrupt (clears corresponding bit in.."
line.long 0x0C "INTLVL,Selects high or low priority interrupt level"
hexmask.long.word 0x0C 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x0C 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
line.long 0x10 "INTFLAG,Interrupt Flags"
hexmask.long.word 0x10 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x10 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 7. "BUSERROR,BUSERROR: BMM Bus Error Response This bit is set when the BMM HRESP = Error" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
line.long 0x14 "OFF1,Interrupt offset for high priority level"
hexmask.long 0x14 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x14 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "OFF2,Interrupt offset for low priority level"
hexmask.long 0x18 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x18 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "DDMDEST,Configuration of Buffer for Direct Data Mode"
line.long 0x20 "DDMBL,Defines the blocksize for the buffer in Direct Data Mode"
hexmask.long 0x20 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x20 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DDMPT,Pointer to the last written entry in the buffer"
hexmask.long.tbyte 0x24 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x24 0.--14. 1. "POINTER,POINTER These bits hold the pointer to the next entry to be written in the buffer"
line.long 0x28 "INTPT,Programmable Interrupt Pointer"
hexmask.long.tbyte 0x28 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x28 0.--14. 1. "INTPT,INTPT: Interrupt Pointer When the buffer pointer (DMMDDMPT) matches the programmed value in DMMINTPT and the PROG_BUF interrupt is set a interrupt is generated"
line.long 0x2C "DEST0REG1,Defines Region 1 for Destination 0"
hexmask.long.word 0x2C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x2C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x30 "DEST0BL1,Defines the blocksize for the buffer for Destination 0 Region 1"
hexmask.long 0x30 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x30 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DEST0REG2,Defines Region 2 for Destination 0"
hexmask.long.word 0x34 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x34 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x38 "DEST0BL2,Defines the blocksize for the buffer for Destination 0 Region 2"
hexmask.long 0x38 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x38 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "DEST1REG1,Defines Region 1 for Destination1"
hexmask.long.word 0x3C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x3C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x40 "DEST1BL1,Defines the blocksize for the buffer for Destination 1 Region 1"
hexmask.long 0x40 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x40 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "DEST1REG2,Defines Region 2 for Destination 1"
hexmask.long.word 0x44 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x44 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x48 "DEST1BL2,Defines the blocksize for the buffer for Destination 1 Region 2"
hexmask.long 0x48 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x48 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "DEST2REG1,Defines Region 1 for Destination 2"
hexmask.long.word 0x4C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x4C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x50 "DEST2BL1,Defines the blocksize for the buffer for Destination 2 Region 1"
hexmask.long 0x50 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x50 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "DEST2REG2,Defines Region 2 for Destination 2"
hexmask.long.word 0x54 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x54 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x58 "DEST2BL2,Defines the blocksize for the buffer for Destination 2 Region 2"
hexmask.long 0x58 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x58 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "DEST3REG1,Defines Region 1 for Destination 3"
hexmask.long.word 0x5C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x5C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x60 "DEST3BL1,Defines the blocksize for the buffer for Destination 3 Region 1"
hexmask.long 0x60 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x60 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "DEST3REG2,Defines Region 2 for Destination 3"
hexmask.long.word 0x64 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x64 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x68 "DEST3BL2,Defines the blocksize for the buffer for Destination 3 Region 2"
hexmask.long 0x68 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x68 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "DMMPC0,Defines functional or GIO mode of pins"
hexmask.long.word 0x6C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x6C 18. "ENAFUNC,ENAFUNC: Functional mode of DMMENA pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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abitfld.long 0x6C 2.--17. "DATAxFUNC,DATAxFUNC: Functional mode of DMMDATA[x] pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "0x0000=Pin is used in GIO mode,0x0001=Pin is used in Functional model mode"
bitfld.long 0x6C 1. "CLKFUNC,CLKFUNC: Functional mode of DMMCLK pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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bitfld.long 0x6C 0. "SYNCFUNC,SYNCFUNC: Functional mode of DMMSYNC pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
line.long 0x70 "DMMPC1,Defines direction of pins"
hexmask.long.word 0x70 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x70 18. "ENADIR,ENADIR: Direction of DMMENA pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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abitfld.long 0x70 2.--17. "DATAxDIR,DATAxDIR: Direction of DMMDATA[x] pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "0x0000=Pin is set to input,0x0001=Pin is set to output"
bitfld.long 0x70 1. "CLKDIR,CLKDIR: Direction of DMMCLK pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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bitfld.long 0x70 0. "SYNCDIR,SYNCDIR: Direction of DMMSYNC pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
line.long 0x74 "DMMPC2,Input level of pins"
hexmask.long.word 0x74 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x74 18. "ENAIN,ENAIN: DMMENA input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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abitfld.long 0x74 2.--17. "DATAxIN,DATAxIN: DMMDATA[x] input This bit reflects the state of the pin in all modes User and privilege mode (read)" "0x0000=Logic low (input voltage is VIL or lower),0x0001=Logic high (input voltage is VIH or.."
bitfld.long 0x74 1. "CLKIN,CLKIN: DMMCLK input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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bitfld.long 0x74 0. "SYNCIN,SYNCIN: DMMSYNC input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
line.long 0x78 "DMMPC3,Sets pins to high or low"
hexmask.long.word 0x78 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x78 18. "ENAOUT,ENAOUT: Output state of DMMENA pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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abitfld.long 0x78 2.--17. "DATAxOUT,DATAxOUT: Output state of DMMDATA[x] pin This bit sets the pin to logic low or high level User and privilege mode (read)" "0x0000=Logic low (output voltage is set to VOL..,0x0001=Logic high (output voltage is set to VOH.."
bitfld.long 0x78 1. "CLKOUT,CLKOUT: Output state of DMMCLK pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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bitfld.long 0x78 0. "SYNCOUT,SYNCOUT: Output state of DMMSYNC pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
line.long 0x7C "DMMPC4,Sets pins to high"
hexmask.long.word 0x7C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x7C 18. "ENASET,ENASET: Sets output state of DMMENA pin to logic high Value in the ENASET bit sets the data output control register bit to 1 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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abitfld.long 0x7C 2.--17. "DATAxSET,DATAxSET: Sets output state of DMMDATA[x] pin to logic high Value in the DATAxSET bit sets the data output control register bit to 1 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=Sets the pin to Logic high (output.."
bitfld.long 0x7C 1. "CLKSET,CLKSET: Sets output state of DMMCLK pin to logic high Value in the CLKSET bit sets the data output control register bit to 1 regardless of the current value in the CLKOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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bitfld.long 0x7C 0. "SYNCSET,SYNCSET: Sets output state of DMMSYNC pin logic high Value in the SYNCSET bit sets the data output control register bit to 1 regardless of the current value in the SYNCOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
line.long 0x80 "DMMPC5,Sets pins to low"
hexmask.long.word 0x80 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x80 18. "ENACLR,ENACLR: Sets output state of DMMENA pin to logic low Value in the ENACLR bit clears the data output control register bit to 0 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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abitfld.long 0x80 2.--17. "DATAxCLR,DATAxCLR: Sets output state of DMMDATA[x] pin to logic low Value in the DATAxCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=clears the pin to logic low (output.."
bitfld.long 0x80 1. "CLKCLR,CLKCLR: Sets output state of DMMCLK pin to logic low Value in the CLKCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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bitfld.long 0x80 0. "SYNCCLR,SYNCCLR: Sets output state of DMMSYNC pin to logic low Value in the SYNCCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
line.long 0x84 "DMMPC6,Configures open drain functionality of pin"
hexmask.long.word 0x84 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x84 18. "ENAPDR,ENAPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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abitfld.long 0x84 2.--17. "DATAxPDR,DATAxPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "0x0000=configures pin as push/pull,0x0001=configures pin as open drain"
bitfld.long 0x84 1. "CLKPDR,CLKPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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bitfld.long 0x84 0. "SYNCPDR,SYNCPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
line.long 0x88 "DMMPC7,Enables/Disables pullup/pulldown structure of pin"
hexmask.long.word 0x88 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x88 18. "ENAPDIS,ENAPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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abitfld.long 0x88 2.--17. "DATAxPDIS,DATAxPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "0x0000=enables pullup/pulldown functionality,0x0001=disables pullup/pulldown functionality"
bitfld.long 0x88 1. "CLKPDIS,CLKPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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bitfld.long 0x88 0. "SYNCPDIS,SYNCPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
line.long 0x8C "DMMPC8,Enables pullup or pulldown structure of pin"
hexmask.long.word 0x8C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x8C 18. "ENAPSEL,ENAPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
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abitfld.long 0x8C 2.--17. "DATAxPSEL,DATAxPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "0x0000=enables pulldown functionality,0x0001=enables pullup functionality"
bitfld.long 0x8C 1. "CLKPDSEL,CLKPDSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
newline
bitfld.long 0x8C 0. "SYNCPSEL,SYNCPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
width 0x0B
tree.end
tree "MSS_ECC_AGG_MSS (MSS ECC Aggregator MSS Module Registers)"
base ad:0x2F7C000
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 7. "TPTC_B0_PEND,Interrupt Pending Status for tptc_b0_pend" "0,1"
bitfld.long 0x04 6. "TPTC_A1_PEND,Interrupt Pending Status for tptc_a1_pend" "0,1"
bitfld.long 0x04 5. "TPTC_A0_PEND,Interrupt Pending Status for tptc_a0_pend" "0,1"
bitfld.long 0x04 4. "GPADC_PEND,Interrupt Pending Status for gpadc_pend" "0,1"
bitfld.long 0x04 3. "MSS_RETRAM_PEND,Interrupt Pending Status for mss_retram_pend" "0,1"
bitfld.long 0x04 2. "MSS_MBOX_PEND,Interrupt Pending Status for mss_mbox_pend" "0,1"
newline
bitfld.long 0x04 1. "MSS_L2SLV1_PEND,Interrupt Pending Status for mss_l2slv1_pend" "0,1"
bitfld.long 0x04 0. "MSS_L2SLV0_PEND,Interrupt Pending Status for mss_l2slv0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_SET,Interrupt Enable Set Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_SET,Interrupt Enable Set Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_SET,Interrupt Enable Set Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_CLR,Interrupt Enable Clear Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_CLR,Interrupt Enable Clear Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_CLR,Interrupt Enable Clear Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 7. "TPTC_B0_PEND,Interrupt Pending Status for tptc_b0_pend" "0,1"
bitfld.long 0x04 6. "TPTC_A1_PEND,Interrupt Pending Status for tptc_a1_pend" "0,1"
bitfld.long 0x04 5. "TPTC_A0_PEND,Interrupt Pending Status for tptc_a0_pend" "0,1"
bitfld.long 0x04 4. "GPADC_PEND,Interrupt Pending Status for gpadc_pend" "0,1"
bitfld.long 0x04 3. "MSS_RETRAM_PEND,Interrupt Pending Status for mss_retram_pend" "0,1"
bitfld.long 0x04 2. "MSS_MBOX_PEND,Interrupt Pending Status for mss_mbox_pend" "0,1"
newline
bitfld.long 0x04 1. "MSS_L2SLV1_PEND,Interrupt Pending Status for mss_l2slv1_pend" "0,1"
bitfld.long 0x04 0. "MSS_L2SLV0_PEND,Interrupt Pending Status for mss_l2slv0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_SET,Interrupt Enable Set Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_SET,Interrupt Enable Set Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_SET,Interrupt Enable Set Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_CLR,Interrupt Enable Clear Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_CLR,Interrupt Enable Clear Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_CLR,Interrupt Enable Clear Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_ECC_AGG_R5A (MSS ECC Aggregator R5A Module Registers)"
base ad:0x2F7B800
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_ECC_AGG_R5B (MSS ECC Aggregator R5B Module Registers)"
base ad:0x2F7BC00
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_ESM (MSS ESM Module Registers)"
base ad:0x2F7A400
group.long 0x00++0x5B
line.long 0x00 "ESMIEPSR1,ESM Enable ERROR Pin Action/Response Register 1"
line.long 0x04 "ESMIEPCR1,ESM Disable ERROR Pin Action/Response Register 1"
line.long 0x08 "ESMIESR1,ESM Interrupt Enable Set/Status Register 1"
line.long 0x0C "ESMIECR1,ESM Interrupt Enable Clear/Status Register 1"
line.long 0x10 "ESMILSR1,Interrupt Level Set/Status Register 1"
line.long 0x14 "ESMILCR1,Interrupt Level Clear/Status Register 1"
line.long 0x18 "ESMSR1,ESM Status Register 1"
line.long 0x1C "ESMSR2,ESM Status Register 2"
line.long 0x20 "ESMSR3,ESM Status Register 3"
line.long 0x24 "ESMEPSR,ESM ERROR Pin Status Register"
hexmask.long 0x24 1.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EPSF,ERROR Pin Status Flag" "0,1"
line.long 0x28 "ESMIOFFHR,ESM Interrupt Offset High Register"
hexmask.long.tbyte 0x28 9.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x28 0.--8. 1. "INTOFFH,Offset High Level Interrupt"
line.long 0x2C "ESMIOFFLR,ESM Interrupt Offset Low Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x2C 0.--7. 1. "INTOFFL,Offset Low Level Interrupt"
line.long 0x30 "ESMLTCR,ESM Low-Time Counter Register"
hexmask.long.word 0x30 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x30 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin"
line.long 0x34 "ESMLTCPR,ESM Low-Time Counter Preload Register"
hexmask.long.word 0x34 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x34 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter"
line.long 0x38 "ESMEKR,ESM Error Key Register"
hexmask.long 0x38 4.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0.--3. "EKEY,Error Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "ESMSSR2,ESM Status Shadow Register 2"
line.long 0x40 "ESMIEPSR4,ESM Enable ERROR Pin Action/Response Register 4"
line.long 0x44 "ESMIEPCR4,ESM Disable ERROR Pin Action/Response Register 4"
line.long 0x48 "ESMIESR4,ESM Interrupt Enable Set/Status Register 4"
line.long 0x4C "ESMIECR4,ESM Interrupt Enable Clear/Status Register 4"
line.long 0x50 "ESMILSR4,Interrupt Level Set/Status Register 4"
line.long 0x54 "ESMILCR4,Interrupt Level Clear/Status Register 4"
line.long 0x58 "ESMSR4,ESM Status Register 4"
group.long 0x80++0x1B
line.long 0x00 "ESMIEPSR7,ESM Enable ERROR Pin Action/Response Register 7"
line.long 0x04 "ESMIEPCR7,ESM Disable ERROR Pin Action/Response Register 7"
line.long 0x08 "ESMIESR7,ESM Interrupt Enable Set/Status Register 7"
line.long 0x0C "ESMIECR7,ESM Interrupt Enable Clear/Status Register 7"
line.long 0x10 "ESMILSR7,Interrupt Level Set/Status Register 7"
line.long 0x14 "ESMILCR7,Interrupt Level Clear/Status Register 7"
line.long 0x18 "ESMSR7,ESM Status Register 7"
group.long 0xC0++0x1B
line.long 0x00 "ESMIEPSR10,ESM Enable ERROR Pin Action/Response Register 10"
line.long 0x04 "ESMIEPCR10,ESM Disable ERROR Pin Action/Response Register 10"
line.long 0x08 "ESMIESR10,ESM Interrupt Enable Set/Status Register 10"
line.long 0x0C "ESMIECR10,ESM Interrupt Enable Clear/Status Register 10"
line.long 0x10 "ESMILSR10,Interrupt Level Set/Status Register 10"
line.long 0x14 "ESMILCR10,Interrupt Level Clear/Status Register 10"
line.long 0x18 "ESMSR10,ESM Status Register 10"
width 0x0B
tree.end
tree "MSS_ETPWMA (MSS ETPWMA Module Registers)"
base ad:0x3F78C00
group.long 0x00++0x3F
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
hexmask.long.word 0x00 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x00 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value" "0,1"
bitfld.long 0x00 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred" "0,1"
bitfld.long 0x00 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit" "0,1"
newline
bitfld.long 0x00 14.--15. "TBCTL_FREE,_SOFT,Emulation Mode Bits" "0,1,2,3"
bitfld.long 0x00 13. "TBCTL_PHSDIR,Phase Direction Bit" "0,1"
bitfld.long 0x00 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0" "0,1"
bitfld.long 0x00 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select" "0,1,2,3"
bitfld.long 0x00 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero" "0,1"
bitfld.long 0x00 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
newline
bitfld.long 0x00 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation" "0,1,2,3"
line.long 0x04 "TBPHS,Time-Base Phase Register"
hexmask.long.word 0x04 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal"
hexmask.long.word 0x04 0.--15. 1. "Reserved,Reserved"
line.long 0x08 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
hexmask.long.word 0x08 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter"
hexmask.long.word 0x08 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value"
line.long 0x0C "CMPCTL,Counter-Compare Control Register"
rbitfld.long 0x0C 26.--31. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
bitfld.long 0x0C 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made" "0,1"
rbitfld.long 0x0C 23. "Reserved3,Reserved" "0,1"
newline
bitfld.long 0x0C 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode" "0,1"
rbitfld.long 0x0C 21. "Reserved2,Reserved" "0,1"
bitfld.long 0x0C 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode" "0,1"
bitfld.long 0x0C 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1)" "0,1,2,3"
newline
bitfld.long 0x0C 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "0,1,2,3"
hexmask.long.word 0x0C 0.--15. 1. "Reserved1,Reserved"
line.long 0x10 "CMPA,Counter-Compare A Register"
hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR)"
hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
rbitfld.long 0x14 28.--31. "Reserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
newline
bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period" "0,1,2,3"
bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero" "0,1,2,3"
hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR)"
line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is.." "0,1,2,3"
bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
newline
bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low High High Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
rbitfld.long 0x18 12.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period" "0,1,2,3"
newline
bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero" "0,1,2,3"
line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled" "0,1"
hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28" "0,1,2,3"
bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28" "0,1,2,3"
newline
bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28" "0,1,2,3"
hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
rbitfld.long 0x20 26.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count"
rbitfld.long 0x20 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count"
line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
rbitfld.long 0x24 28.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation" "0,1"
rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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rbitfld.long 0x28 12.--15. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3"
bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3"
line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect" "0,1"
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hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred" "0,1"
bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred" "0,1"
bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated" "0,1"
line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB" "0,1"
bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated" "0,1,2,3,4,5,6,7"
bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA" "0,1"
bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x30 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored" "0,1"
bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored" "0,1"
rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB" "0,1"
bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set" "0,1"
rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated" "0,1"
bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred" "0,1,2,3"
bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated" "0,1,2,3"
bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred" "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated" "0,1,2,3"
rbitfld.long 0x34 4.--7. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred" "0,1,2,3"
bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated" "0,1,2,3"
line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit" "0,1"
bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit" "0,1"
rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit" "0,1"
hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
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rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
line.long 0x3C "PCCTL,PWM-Chopper Control Register"
hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 1.--4. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
group.long 0x60++0x13
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
rbitfld.long 0x00 26.--31. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
rbitfld.long 0x00 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x00 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x00 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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bitfld.long 0x00 12.--15. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
hexmask.long.word 0x04 22.--31. 1. "Reserved3,Reserved"
bitfld.long 0x04 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
bitfld.long 0x04 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
bitfld.long 0x04 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
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bitfld.long 0x04 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
rbitfld.long 0x04 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x04 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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rbitfld.long 0x04 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x04 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x04 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x04 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
hexmask.long.word 0x08 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied"
hexmask.long.word 0x08 2.--15. 1. "Reserved,Reserved"
bitfld.long 0x08 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode" "0,1"
bitfld.long 0x08 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture" "0,1"
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated"
hexmask.long.word 0x0C 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter"
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1"
hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_ETPWMB (MSS ETPWMB Module Registers)"
base ad:0x3F78D00
group.long 0x00++0x3F
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
hexmask.long.word 0x00 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x00 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value" "0,1"
bitfld.long 0x00 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred" "0,1"
bitfld.long 0x00 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit" "0,1"
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bitfld.long 0x00 14.--15. "TBCTL_FREE,_SOFT,Emulation Mode Bits" "0,1,2,3"
bitfld.long 0x00 13. "TBCTL_PHSDIR,Phase Direction Bit" "0,1"
bitfld.long 0x00 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0" "0,1"
bitfld.long 0x00 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select" "0,1,2,3"
bitfld.long 0x00 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero" "0,1"
bitfld.long 0x00 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
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bitfld.long 0x00 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation" "0,1,2,3"
line.long 0x04 "TBPHS,Time-Base Phase Register"
hexmask.long.word 0x04 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal"
hexmask.long.word 0x04 0.--15. 1. "Reserved,Reserved"
line.long 0x08 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
hexmask.long.word 0x08 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter"
hexmask.long.word 0x08 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value"
line.long 0x0C "CMPCTL,Counter-Compare Control Register"
rbitfld.long 0x0C 26.--31. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
bitfld.long 0x0C 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made" "0,1"
rbitfld.long 0x0C 23. "Reserved3,Reserved" "0,1"
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bitfld.long 0x0C 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode" "0,1"
rbitfld.long 0x0C 21. "Reserved2,Reserved" "0,1"
bitfld.long 0x0C 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode" "0,1"
bitfld.long 0x0C 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1)" "0,1,2,3"
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bitfld.long 0x0C 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "0,1,2,3"
hexmask.long.word 0x0C 0.--15. 1. "Reserved1,Reserved"
line.long 0x10 "CMPA,Counter-Compare A Register"
hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR)"
hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
rbitfld.long 0x14 28.--31. "Reserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period" "0,1,2,3"
bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero" "0,1,2,3"
hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR)"
line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is.." "0,1,2,3"
bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low High High Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
rbitfld.long 0x18 12.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period" "0,1,2,3"
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bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero" "0,1,2,3"
line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled" "0,1"
hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28" "0,1,2,3"
bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28" "0,1,2,3"
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bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28" "0,1,2,3"
hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
rbitfld.long 0x20 26.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count"
rbitfld.long 0x20 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count"
line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
rbitfld.long 0x24 28.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation" "0,1"
rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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rbitfld.long 0x28 12.--15. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3"
bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3"
line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect" "0,1"
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hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred" "0,1"
bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred" "0,1"
bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated" "0,1"
line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB" "0,1"
bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated" "0,1,2,3,4,5,6,7"
bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA" "0,1"
bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x30 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored" "0,1"
bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored" "0,1"
rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB" "0,1"
bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set" "0,1"
rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated" "0,1"
bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred" "0,1,2,3"
bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated" "0,1,2,3"
bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred" "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated" "0,1,2,3"
rbitfld.long 0x34 4.--7. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred" "0,1,2,3"
bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated" "0,1,2,3"
line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit" "0,1"
bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit" "0,1"
rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit" "0,1"
hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
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rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
line.long 0x3C "PCCTL,PWM-Chopper Control Register"
hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 1.--4. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
group.long 0x60++0x13
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
rbitfld.long 0x00 26.--31. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
rbitfld.long 0x00 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x00 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x00 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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bitfld.long 0x00 12.--15. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
hexmask.long.word 0x04 22.--31. 1. "Reserved3,Reserved"
bitfld.long 0x04 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
bitfld.long 0x04 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
bitfld.long 0x04 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
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bitfld.long 0x04 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
rbitfld.long 0x04 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x04 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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rbitfld.long 0x04 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x04 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x04 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x04 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
hexmask.long.word 0x08 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied"
hexmask.long.word 0x08 2.--15. 1. "Reserved,Reserved"
bitfld.long 0x08 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode" "0,1"
bitfld.long 0x08 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture" "0,1"
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated"
hexmask.long.word 0x0C 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter"
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1"
hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_ETPWMC (MSS ETPWMC Module Registers)"
base ad:0x3F78E00
group.long 0x00++0x3F
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
hexmask.long.word 0x00 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x00 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value" "0,1"
bitfld.long 0x00 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred" "0,1"
bitfld.long 0x00 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit" "0,1"
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bitfld.long 0x00 14.--15. "TBCTL_FREE,_SOFT,Emulation Mode Bits" "0,1,2,3"
bitfld.long 0x00 13. "TBCTL_PHSDIR,Phase Direction Bit" "0,1"
bitfld.long 0x00 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0" "0,1"
bitfld.long 0x00 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select" "0,1,2,3"
bitfld.long 0x00 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero" "0,1"
bitfld.long 0x00 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
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bitfld.long 0x00 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation" "0,1,2,3"
line.long 0x04 "TBPHS,Time-Base Phase Register"
hexmask.long.word 0x04 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal"
hexmask.long.word 0x04 0.--15. 1. "Reserved,Reserved"
line.long 0x08 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
hexmask.long.word 0x08 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter"
hexmask.long.word 0x08 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value"
line.long 0x0C "CMPCTL,Counter-Compare Control Register"
rbitfld.long 0x0C 26.--31. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
bitfld.long 0x0C 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made" "0,1"
rbitfld.long 0x0C 23. "Reserved3,Reserved" "0,1"
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bitfld.long 0x0C 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode" "0,1"
rbitfld.long 0x0C 21. "Reserved2,Reserved" "0,1"
bitfld.long 0x0C 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode" "0,1"
bitfld.long 0x0C 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1)" "0,1,2,3"
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bitfld.long 0x0C 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "0,1,2,3"
hexmask.long.word 0x0C 0.--15. 1. "Reserved1,Reserved"
line.long 0x10 "CMPA,Counter-Compare A Register"
hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR)"
hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
rbitfld.long 0x14 28.--31. "Reserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period" "0,1,2,3"
bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero" "0,1,2,3"
hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR)"
line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is.." "0,1,2,3"
bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low High High Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
rbitfld.long 0x18 12.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period" "0,1,2,3"
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bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero" "0,1,2,3"
line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled" "0,1"
hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28" "0,1,2,3"
bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28" "0,1,2,3"
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bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28" "0,1,2,3"
hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
rbitfld.long 0x20 26.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count"
rbitfld.long 0x20 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count"
line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
rbitfld.long 0x24 28.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation" "0,1"
rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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rbitfld.long 0x28 12.--15. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3"
bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3"
line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect" "0,1"
newline
hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred" "0,1"
bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred" "0,1"
bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated" "0,1"
line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB" "0,1"
bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated" "0,1,2,3,4,5,6,7"
bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA" "0,1"
bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x30 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored" "0,1"
bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored" "0,1"
rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB" "0,1"
bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set" "0,1"
rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated" "0,1"
bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred" "0,1,2,3"
bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated" "0,1,2,3"
bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred" "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated" "0,1,2,3"
rbitfld.long 0x34 4.--7. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred" "0,1,2,3"
bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated" "0,1,2,3"
line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit" "0,1"
bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit" "0,1"
rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit" "0,1"
hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
newline
rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
line.long 0x3C "PCCTL,PWM-Chopper Control Register"
hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 1.--4. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
group.long 0x60++0x13
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
rbitfld.long 0x00 26.--31. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
rbitfld.long 0x00 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x00 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x00 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
newline
bitfld.long 0x00 12.--15. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
hexmask.long.word 0x04 22.--31. 1. "Reserved3,Reserved"
bitfld.long 0x04 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
bitfld.long 0x04 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
bitfld.long 0x04 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
newline
bitfld.long 0x04 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
rbitfld.long 0x04 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x04 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
newline
rbitfld.long 0x04 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x04 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x04 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
newline
bitfld.long 0x04 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
hexmask.long.word 0x08 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied"
hexmask.long.word 0x08 2.--15. 1. "Reserved,Reserved"
bitfld.long 0x08 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode" "0,1"
bitfld.long 0x08 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture" "0,1"
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated"
hexmask.long.word 0x0C 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter"
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1"
hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_GIO (MSS GIO Module Registers)"
base ad:0x2F7B400
group.long 0x00++0x03
line.long 0x00 "GIOGCR,GIO reset"
hexmask.long 0x00 1.--31. 1. "NU0,Reserved"
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "GIOPWDN,GIO power down mode register"
bitfld.long 0x00 0. "GIOPWDN,Writing to the GIOPWDN bit is only allowed in privilege mode" "Normal operation; clocks enabled to GIO..,Power-down mode"
group.long 0x08++0x14B
line.long 0x00 "GIOINTDET,Interrupt detection select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x00 24.--31. 1. "GIOINTDET_3,Interrupt detection select for pins GIOD[7:0]"
hexmask.long.byte 0x00 16.--23. 1. "GIOINTDET_2,Interrupt detection select for pins GIOC[7:0]"
hexmask.long.byte 0x00 8.--15. 1. "GIOINTDET_1,Interrupt detection select for pins GIOB[7:0]"
hexmask.long.byte 0x00 0.--7. 1. "GIOINTDET_0,Interrupt detection select for pins GIOA[7:0]"
line.long 0x04 "GIOPOL,Interrupt polarity select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x04 24.--31. 1. "GIOPOL_3,Interrupt polarity select for pins GIOD[7:0]"
hexmask.long.byte 0x04 16.--23. 1. "GIOPOL_2,Interrupt polarity select for pins GIOC[7:0]"
hexmask.long.byte 0x04 8.--15. 1. "GIOPOL_1,Interrupt polarity select for pins GIOB[7:0]"
hexmask.long.byte 0x04 0.--7. 1. "GIOPOL_0,Interrupt polarity select for pins GIOA[7:0]"
line.long 0x08 "GIOENASET,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x08 24.--31. 1. "GIOENASET_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x08 16.--23. 1. "GIOENASET_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x08 8.--15. 1. "GIOENASET_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x08 0.--7. 1. "GIOENASET_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x0C "GIOENACLR,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x0C 24.--31. 1. "GIOENACLR_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x0C 16.--23. 1. "GIOENACLR_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x0C 8.--15. 1. "GIOENACLR_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x0C 0.--7. 1. "GIOENACLR_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x10 "GIOLVLSET,GIO high priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x10 24.--31. 1. "GIOLVLSET_3,GIO high priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x10 16.--23. 1. "GIOLVLSET_2,GIO high priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x10 8.--15. 1. "GIOLVLSET_1,GIO high priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x10 0.--7. 1. "GIOLVLSET_0,GIO high priority interrupt for pins GIOA[7:0]"
line.long 0x14 "GIOLVLCLR,GIO low priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x14 24.--31. 1. "GIOLVLCLR_3,GIO low priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x14 16.--23. 1. "GIOLVLCLR_2,GIO low priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x14 8.--15. 1. "GIOLVLCLR_1,GIO low priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x14 0.--7. 1. "GIOLVLCLR_0,GIO low priority interrupt for pins GIOA[7:0]"
line.long 0x18 "GIOFLG,GIO flag for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x18 24.--31. 1. "GIOFLG_3,GIO flag for pins GIOD[7:0]"
hexmask.long.byte 0x18 16.--23. 1. "GIOFLG_2,GIO flag for pins GIOC[7:0]"
hexmask.long.byte 0x18 8.--15. 1. "GIOFLG_1,GIO flag for pins GIOB[7:0]"
hexmask.long.byte 0x18 0.--7. 1. "GIOFLG_0,GIO flag for pins GIOA[7:0]"
line.long 0x1C "GIOOFFA,Index bits for currently pending high-priority interrupt Register A"
hexmask.long 0x1C 6.--31. 1. "NU1,Reserved"
bitfld.long 0x1C 0.--5. "GIOOFFA,Index bits for currently pending high-priority interrupt Register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "GIOOFFB,Index bits for currently pending high-priority interrupt Register B"
hexmask.long 0x20 6.--31. 1. "NU2,Reserved"
bitfld.long 0x20 0.--5. "GIOOFFB,Index bits for currently pending high-priority interrupt Register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "GIOEMUA,GIO emulation register A"
hexmask.long 0x24 6.--31. 1. "NU3,Reserved"
bitfld.long 0x24 0.--5. "GIOEMUA,GIO emulation register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "GIOEMUB,GIO emulation register B"
hexmask.long 0x28 6.--31. 1. "NU4,Reserved"
bitfld.long 0x28 0.--5. "GIOEMUB,GIO emulation register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "GIODIRA,GIO data direction of pins in Port A"
hexmask.long.tbyte 0x2C 8.--31. 1. "NU5,Reserved"
hexmask.long.byte 0x2C 0.--7. 1. "GIODIRA,GIO data direction of pins in Port A"
line.long 0x30 "GIODINA,GIO data input for pins in port A"
hexmask.long.tbyte 0x30 8.--31. 1. "NU11,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "GIODINA,GIO data input for pins in port A"
line.long 0x34 "GIODOUTA,GIO data output for pins in port A"
hexmask.long.tbyte 0x34 8.--31. 1. "NU17,Reserved"
hexmask.long.byte 0x34 0.--7. 1. "GIODOUTA,GIO data output for pins in port A"
line.long 0x38 "GIOSETA,GIO data set for port A"
hexmask.long.tbyte 0x38 8.--31. 1. "NU23,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "GIODSETA,GIO data set for port A"
line.long 0x3C "GIOCLRA,GIO data clear for port A"
hexmask.long.tbyte 0x3C 8.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x3C 0.--7. 1. "GIODCLRA,GIO data clear for port A"
line.long 0x40 "GIOPDRA,GIO open drain for port A"
hexmask.long.tbyte 0x40 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x40 0.--7. 1. "GIOPDRA,GIO open drain for port A"
line.long 0x44 "GIOPULDISA,GIO pul disable for port A"
hexmask.long.tbyte 0x44 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x44 0.--7. 1. "GIOPULDISA,GIO pull disable for port A"
line.long 0x48 "GIOPSLA,GIO pul select for port A"
hexmask.long.tbyte 0x48 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x48 0.--7. 1. "GIOPSLA,GIO pull select for port A"
line.long 0x4C "GIODIRB,GIO data direction of pins in Port B"
hexmask.long.tbyte 0x4C 8.--31. 1. "NU6,Reserved"
hexmask.long.byte 0x4C 0.--7. 1. "GIODIRB,GIO data direction of pins in Port B"
line.long 0x50 "GIODINB,GIO data input for pins in port B"
hexmask.long.tbyte 0x50 8.--31. 1. "NU12,Reserved"
hexmask.long.byte 0x50 0.--7. 1. "GIODINB,GIO data input for pins in port B"
line.long 0x54 "GIODOUTB,GIO data output for pins in port B"
hexmask.long.tbyte 0x54 8.--31. 1. "NU18,Reserved"
hexmask.long.byte 0x54 0.--7. 1. "GIODOUTB,GIO data output for pins in port B"
line.long 0x58 "GIOSETB,GIO data set for port B"
hexmask.long.tbyte 0x58 8.--31. 1. "NU24,Reserved"
hexmask.long.byte 0x58 0.--7. 1. "GIODSETB,GIO data set for port B"
line.long 0x5C "GIOCLRB,GIO data clear for port B"
hexmask.long.tbyte 0x5C 8.--31. 1. "NU30,Reserved"
hexmask.long.byte 0x5C 0.--7. 1. "GIODCLRB,GIO data clear for port B"
line.long 0x60 "GIOPDRB,GIO open drain for port B"
hexmask.long.tbyte 0x60 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x60 0.--7. 1. "GIOPDRB,GIO open drain for port B"
line.long 0x64 "GIOPULDISB,GIO pul disable for port B"
hexmask.long.tbyte 0x64 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x64 0.--7. 1. "GIOPULDISB,GIO pull disable for port B"
line.long 0x68 "GIOPSLB,GIO pul select for port B"
hexmask.long.tbyte 0x68 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x68 0.--7. 1. "GIOPSLB,GIO pull select for port B"
line.long 0x6C "GIODIRC,GIO data direction of pins in Port C"
hexmask.long.tbyte 0x6C 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x6C 0.--7. 1. "GIODIRC,GIO data direction of pins in Port C"
line.long 0x70 "GIODINC,GIO data input for pins in port C"
hexmask.long.tbyte 0x70 8.--31. 1. "NU13,Reserved"
hexmask.long.byte 0x70 0.--7. 1. "GIODINC,GIO data input for pins in port C"
line.long 0x74 "GIODOUTC,GIO data output for pins in port C"
hexmask.long.tbyte 0x74 8.--31. 1. "NU19,Reserved"
hexmask.long.byte 0x74 0.--7. 1. "GIODOUTC,GIO data output for pins in port C"
line.long 0x78 "GIOSETC,GIO data set for port C"
hexmask.long.tbyte 0x78 8.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x78 0.--7. 1. "GIODSETC,GIO data set for port C"
line.long 0x7C "GIOCLRC,GIO data clear for port C"
hexmask.long.tbyte 0x7C 8.--31. 1. "NU31,Reserved"
hexmask.long.byte 0x7C 0.--7. 1. "GIODCLRC,GIO data clear for port C"
line.long 0x80 "GIOPDRC,GIO open drain for port C"
hexmask.long.tbyte 0x80 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x80 0.--7. 1. "GIOPDRC,GIO open drain for port C"
line.long 0x84 "GIOPULDISC,GIO pul disable for port C"
hexmask.long.tbyte 0x84 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x84 0.--7. 1. "GIOPULDISC,GIO pull disable for port C"
line.long 0x88 "GIOPSLC,GIO pul select for port C"
hexmask.long.tbyte 0x88 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x88 0.--7. 1. "GIOPSLC,GIO pull select for port C"
line.long 0x8C "GIODIRD,GIO data direction of pins in Port D"
hexmask.long.tbyte 0x8C 8.--31. 1. "NU8,Reserved"
hexmask.long.byte 0x8C 0.--7. 1. "GIODIRD,GIO data direction of pins in Port D"
line.long 0x90 "GIODIND,GIO data input for pins in port D"
hexmask.long.tbyte 0x90 8.--31. 1. "NU14,Reserved"
hexmask.long.byte 0x90 0.--7. 1. "GIODIND,GIO data input for pins in port D"
line.long 0x94 "GIODOUTD,GIO data output for pins in port D"
hexmask.long.tbyte 0x94 8.--31. 1. "NU20,Reserved"
hexmask.long.byte 0x94 0.--7. 1. "GIODOUTD,GIO data output for pins in port D"
line.long 0x98 "GIOSETD,GIO data set for port D"
hexmask.long.tbyte 0x98 8.--31. 1. "NU26,Reserved"
hexmask.long.byte 0x98 0.--7. 1. "GIODSETD,GIO data set for port D"
line.long 0x9C "GIOCLRD,GIO data clear for port D"
hexmask.long.tbyte 0x9C 8.--31. 1. "NU32,Reserved"
hexmask.long.byte 0x9C 0.--7. 1. "GIODCLRD,GIO data clear for port D"
line.long 0xA0 "GIOPDRD,GIO open drain for port D"
hexmask.long.tbyte 0xA0 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA0 0.--7. 1. "GIOPDRD,GIO open drain for port D"
line.long 0xA4 "GIOPULDISD,GIO pul disable for port D"
hexmask.long.tbyte 0xA4 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA4 0.--7. 1. "GIOPULDISD,GIO pull disable for port D"
line.long 0xA8 "GIOPSLD,GIO pul select for port D"
hexmask.long.tbyte 0xA8 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA8 0.--7. 1. "GIOPSLD,GIO pull select for port D"
line.long 0xAC "GIODIRE,GIO data direction of pins in Port E"
hexmask.long.tbyte 0xAC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xAC 0.--7. 1. "GIODIRE,GIO data direction of pins in Port E"
line.long 0xB0 "GIODINE,GIO data input for pins in port E"
hexmask.long.tbyte 0xB0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xB0 0.--7. 1. "GIODINE,GIO data input for pins in port E"
line.long 0xB4 "GIODOUTE,GIO data output for pins in port E"
hexmask.long.tbyte 0xB4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xB4 0.--7. 1. "GIODOUTE,GIO data output for pins in port E"
line.long 0xB8 "GIOSETE,GIO data set for port E"
hexmask.long.tbyte 0xB8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xB8 0.--7. 1. "GIODSETE,GIO data set for port E"
line.long 0xBC "GIOCLRE,GIO data clear for port E"
hexmask.long.tbyte 0xBC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xBC 0.--7. 1. "GIODCLRE,GIO data clear for port E"
line.long 0xC0 "GIOPDRE,GIO open drain for port E"
hexmask.long.tbyte 0xC0 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC0 0.--7. 1. "GIOPDRE,GIO open drain for port E"
line.long 0xC4 "GIOPULDISE,GIO pul disable for port E"
hexmask.long.tbyte 0xC4 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC4 0.--7. 1. "GIOPULDISE,GIO pull disable for port E"
line.long 0xC8 "GIOPSLE,GIO pul select for port E"
hexmask.long.tbyte 0xC8 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC8 0.--7. 1. "GIOPSLE,GIO pull select for port E"
line.long 0xCC "GIODIRF,GIO data direction of pins in Port F"
hexmask.long.tbyte 0xCC 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0xCC 0.--7. 1. "GIODIRF,GIO data direction of pins in Port F"
line.long 0xD0 "GIODINF,GIO data input for pins in Port F"
hexmask.long.tbyte 0xD0 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0xD0 0.--7. 1. "GIODINF,GIO data input for pins in port F"
line.long 0xD4 "GIODOUTF,GIO data output for pins in Port F"
hexmask.long.tbyte 0xD4 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0xD4 0.--7. 1. "GIODOUTF,GIO data output for pins in port F"
line.long 0xD8 "GIOSETF,GIO data set for Port F"
hexmask.long.tbyte 0xD8 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0xD8 0.--7. 1. "GIODSETF,GIO data set for port F"
line.long 0xDC "GIOCLRF,GIO data clear for Port F"
hexmask.long.tbyte 0xDC 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0xDC 0.--7. 1. "GIODCLRF,GIO data clear for port F"
line.long 0xE0 "GIOPDRF,GIO open drain for Port F"
hexmask.long.tbyte 0xE0 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE0 0.--7. 1. "GIOPDRF,GIO open drain for port F"
line.long 0xE4 "GIOPULDISF,GIO pul disable for port F"
hexmask.long.tbyte 0xE4 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE4 0.--7. 1. "GIOPULDISF,GIO pull disable for port F"
line.long 0xE8 "GIOPSLF,GIO pul select for port F"
hexmask.long.tbyte 0xE8 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE8 0.--7. 1. "GIOPSLF,GIO pull select for port F"
line.long 0xEC "GIODIRG,GIO data direction of pins in Port G"
hexmask.long.tbyte 0xEC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xEC 0.--7. 1. "GIODIRG,GIO data direction of pins in Port G"
line.long 0xF0 "GIODING,GIO data input for pins in port G"
hexmask.long.tbyte 0xF0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xF0 0.--7. 1. "GIODING,GIO data input for pins in port G"
line.long 0xF4 "GIODOUTG,GIO data output for pins in port G"
hexmask.long.tbyte 0xF4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xF4 0.--7. 1. "GIODOUTG,GIO data output for pins in port G"
line.long 0xF8 "GIOSETG,GIO data set for port G"
hexmask.long.tbyte 0xF8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xF8 0.--7. 1. "GIODSETG,GIO data set for port G"
line.long 0xFC "GIOCLRG,GIO data clear for port G"
hexmask.long.tbyte 0xFC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xFC 0.--7. 1. "GIODCLRG,GIO data clear for port G"
line.long 0x100 "GIOPDRG,GIO open drain for port G"
hexmask.long.tbyte 0x100 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x100 0.--7. 1. "GIOPDRG,GIO open drain for port G"
line.long 0x104 "GIOPULDISG,GIO pul disable for port G"
hexmask.long.tbyte 0x104 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x104 0.--7. 1. "GIOPULDISG,GIO pull disable for port G"
line.long 0x108 "GIOPSLG,GIO pul select for port G"
hexmask.long.tbyte 0x108 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x108 0.--7. 1. "GIOPSLG,GIO pull select for port G"
line.long 0x10C "GIODIRH,GIO data direction of pins in Port H"
hexmask.long.tbyte 0x10C 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0x10C 0.--7. 1. "GIODIRH,GIO data direction of pins in Port H"
line.long 0x110 "GIODINH,GIO data input for pins in Port H"
hexmask.long.tbyte 0x110 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x110 0.--7. 1. "GIODINH,GIO data input for pins in port H"
line.long 0x114 "GIODOUTH,GIO data output for pins in Port H"
hexmask.long.tbyte 0x114 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0x114 0.--7. 1. "GIODOUTH,GIO data output for pins in port H"
line.long 0x118 "GIOSETH,GIO data set for Port H"
hexmask.long.tbyte 0x118 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0x118 0.--7. 1. "GIODSETH,GIO data set for port H"
line.long 0x11C "GIOCLRH,GIO data clear for Port H"
hexmask.long.tbyte 0x11C 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0x11C 0.--7. 1. "GIODCLRH,GIO data clear for port H"
line.long 0x120 "GIOPDRH,GIO open drain for Port H"
hexmask.long.tbyte 0x120 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x120 0.--7. 1. "GIOPDRH,GIO open drain for port H"
line.long 0x124 "GIOPULDISH,GIO pul disable for port H"
hexmask.long.tbyte 0x124 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x124 0.--7. 1. "GIOPULDISH,GIO pull disable for port H"
line.long 0x128 "GIOPSLH,GIO pul select for port H"
hexmask.long.tbyte 0x128 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x128 0.--7. 1. "GIOPSLH,GIO pull select for port H"
line.long 0x12C "GIOSRCA,GIO slew rate select for port A"
hexmask.long.tbyte 0x12C 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x12C 0.--7. 1. "GIOSRCA,GIO slew rate control for port A"
line.long 0x130 "GIOSRCB,GIO slew rate select for port B"
hexmask.long.tbyte 0x130 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x130 0.--7. 1. "GIOSRCB,GIO slew rate control for port B"
line.long 0x134 "GIOSRCC,GIO slew rate select for port C"
hexmask.long.tbyte 0x134 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x134 0.--7. 1. "GIOSRCC,GIO slew rate control for port C"
line.long 0x138 "GIOSRCD,GIO slew rate select for port D"
hexmask.long.tbyte 0x138 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x138 0.--7. 1. "GIOSRCD,GIO slew rate control for port D"
line.long 0x13C "GIOSRCE,GIO slew rate select for port E"
hexmask.long.tbyte 0x13C 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x13C 0.--7. 1. "GIOSRCE,GIO slew rate control for port E"
line.long 0x140 "GIOSRCF,GIO slew rate select for port F"
hexmask.long.tbyte 0x140 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x140 0.--7. 1. "GIOSRCF,GIO slew rate control for port F"
line.long 0x144 "GIOSRCG,GIO slew rate select for port G"
hexmask.long.tbyte 0x144 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x144 0.--7. 1. "GIOSRCG,GIO slew rate control for port G"
line.long 0x148 "GIOSRCH,GIO slew rate select for port H"
hexmask.long.tbyte 0x148 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x148 0.--7. 1. "GIOSRCH,GIO slew rate control for port H"
width 0x0B
tree.end
tree "MSS_GPADC_DATA_RAM (MSS GPADC DATA RAM Module Registers)"
base ad:0xC5030000
group.long 0x00++0x03
line.long 0x00 "START,"
group.long 0x7FC++0x03
line.long 0x00 "END,"
width 0x0B
tree.end
tree "MSS_GPADC_PKT_RAM (MSS GPADC PKT RAM Module Registers)"
base ad:0x30C0000
group.long 0x00++0x7FF
line.long 0x00 "INST0_0,"
line.long 0x04 "INST0_1,"
hexmask.long.byte 0x04 25.--31. 1. "NU2,"
rbitfld.long 0x04 24. "NU1," "0,1"
bitfld.long 0x04 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x04 16.--22. 1. "SKIP_SAMPLES,Number of GPADC clock cycles to skip before collecting valid samples"
hexmask.long.byte 0x04 8.--15. 1. "COLLECT_SAMPLES,Number of GPADC samples to collect"
hexmask.long.byte 0x04 0.--7. 1. "PARAM,Parameter(input to one hot encoding) to be passed to analog"
line.long 0x08 "INST1_0,"
line.long 0x0C "INST1_1,"
hexmask.long.byte 0x0C 25.--31. 1. "NU2,"
rbitfld.long 0x0C 24. "NU1," "0,1"
bitfld.long 0x0C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x0C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x0C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x0C 0.--7. 1. "PARAM,"
line.long 0x10 "INST2_0,"
line.long 0x14 "INST2_1,"
hexmask.long.byte 0x14 25.--31. 1. "NU2,"
rbitfld.long 0x14 24. "NU1," "0,1"
bitfld.long 0x14 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x14 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x14 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x14 0.--7. 1. "PARAM,"
line.long 0x18 "INST3_0,"
line.long 0x1C "INST3_1,"
hexmask.long.byte 0x1C 25.--31. 1. "NU2,"
rbitfld.long 0x1C 24. "NU1," "0,1"
bitfld.long 0x1C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1C 0.--7. 1. "PARAM,"
line.long 0x20 "INST4_0,"
line.long 0x24 "INST4_1,"
hexmask.long.byte 0x24 25.--31. 1. "NU2,"
rbitfld.long 0x24 24. "NU1," "0,1"
bitfld.long 0x24 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x24 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x24 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x24 0.--7. 1. "PARAM,"
line.long 0x28 "INST5_0,"
line.long 0x2C "INST5_1,"
hexmask.long.byte 0x2C 25.--31. 1. "NU2,"
rbitfld.long 0x2C 24. "NU1," "0,1"
bitfld.long 0x2C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2C 0.--7. 1. "PARAM,"
line.long 0x30 "INST6_0,"
line.long 0x34 "INST6_1,"
hexmask.long.byte 0x34 25.--31. 1. "NU2,"
rbitfld.long 0x34 24. "NU1," "0,1"
bitfld.long 0x34 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x34 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x34 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x34 0.--7. 1. "PARAM,"
line.long 0x38 "INST7_0,"
line.long 0x3C "INST7_1,"
hexmask.long.byte 0x3C 25.--31. 1. "NU2,"
rbitfld.long 0x3C 24. "NU1," "0,1"
bitfld.long 0x3C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3C 0.--7. 1. "PARAM,"
line.long 0x40 "INST8_0,"
line.long 0x44 "INST8_1,"
hexmask.long.byte 0x44 25.--31. 1. "NU2,"
rbitfld.long 0x44 24. "NU1," "0,1"
bitfld.long 0x44 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x44 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x44 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x44 0.--7. 1. "PARAM,"
line.long 0x48 "INST9_0,"
line.long 0x4C "INST9_1,"
hexmask.long.byte 0x4C 25.--31. 1. "NU2,"
rbitfld.long 0x4C 24. "NU1," "0,1"
bitfld.long 0x4C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4C 0.--7. 1. "PARAM,"
line.long 0x50 "INST10_0,"
line.long 0x54 "INST10_1,"
hexmask.long.byte 0x54 25.--31. 1. "NU2,"
rbitfld.long 0x54 24. "NU1," "0,1"
bitfld.long 0x54 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x54 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x54 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x54 0.--7. 1. "PARAM,"
line.long 0x58 "INST11_0,"
line.long 0x5C "INST11_1,"
hexmask.long.byte 0x5C 25.--31. 1. "NU2,"
rbitfld.long 0x5C 24. "NU1," "0,1"
bitfld.long 0x5C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5C 0.--7. 1. "PARAM,"
line.long 0x60 "INST12_0,"
line.long 0x64 "INST12_1,"
hexmask.long.byte 0x64 25.--31. 1. "NU2,"
rbitfld.long 0x64 24. "NU1," "0,1"
bitfld.long 0x64 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x64 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x64 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x64 0.--7. 1. "PARAM,"
line.long 0x68 "INST13_0,"
line.long 0x6C "INST13_1,"
hexmask.long.byte 0x6C 25.--31. 1. "NU2,"
rbitfld.long 0x6C 24. "NU1," "0,1"
bitfld.long 0x6C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6C 0.--7. 1. "PARAM,"
line.long 0x70 "INST14_0,"
line.long 0x74 "INST14_1,"
hexmask.long.byte 0x74 25.--31. 1. "NU2,"
rbitfld.long 0x74 24. "NU1," "0,1"
bitfld.long 0x74 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x74 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x74 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x74 0.--7. 1. "PARAM,"
line.long 0x78 "INST15_0,"
line.long 0x7C "INST15_1,"
hexmask.long.byte 0x7C 25.--31. 1. "NU2,"
rbitfld.long 0x7C 24. "NU1," "0,1"
bitfld.long 0x7C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7C 0.--7. 1. "PARAM,"
line.long 0x80 "INST16_0,"
line.long 0x84 "INST16_1,"
hexmask.long.byte 0x84 25.--31. 1. "NU2,"
rbitfld.long 0x84 24. "NU1," "0,1"
bitfld.long 0x84 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x84 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x84 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x84 0.--7. 1. "PARAM,"
line.long 0x88 "INST17_0,"
line.long 0x8C "INST17_1,"
hexmask.long.byte 0x8C 25.--31. 1. "NU2,"
rbitfld.long 0x8C 24. "NU1," "0,1"
bitfld.long 0x8C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x8C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x8C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x8C 0.--7. 1. "PARAM,"
line.long 0x90 "INST18_0,"
line.long 0x94 "INST18_1,"
hexmask.long.byte 0x94 25.--31. 1. "NU2,"
rbitfld.long 0x94 24. "NU1," "0,1"
bitfld.long 0x94 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x94 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x94 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x94 0.--7. 1. "PARAM,"
line.long 0x98 "INST19_0,"
line.long 0x9C "INST19_1,"
hexmask.long.byte 0x9C 25.--31. 1. "NU2,"
rbitfld.long 0x9C 24. "NU1," "0,1"
bitfld.long 0x9C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x9C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x9C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x9C 0.--7. 1. "PARAM,"
line.long 0xA0 "INST20_0,"
line.long 0xA4 "INST20_1,"
hexmask.long.byte 0xA4 25.--31. 1. "NU2,"
rbitfld.long 0xA4 24. "NU1," "0,1"
bitfld.long 0xA4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xA4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xA4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xA4 0.--7. 1. "PARAM,"
line.long 0xA8 "INST21_0,"
line.long 0xAC "INST21_1,"
hexmask.long.byte 0xAC 25.--31. 1. "NU2,"
rbitfld.long 0xAC 24. "NU1," "0,1"
bitfld.long 0xAC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xAC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xAC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xAC 0.--7. 1. "PARAM,"
line.long 0xB0 "INST22_0,"
line.long 0xB4 "INST22_1,"
hexmask.long.byte 0xB4 25.--31. 1. "NU2,"
rbitfld.long 0xB4 24. "NU1," "0,1"
bitfld.long 0xB4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xB4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xB4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xB4 0.--7. 1. "PARAM,"
line.long 0xB8 "INST23_0,"
line.long 0xBC "INST23_1,"
hexmask.long.byte 0xBC 25.--31. 1. "NU2,"
rbitfld.long 0xBC 24. "NU1," "0,1"
bitfld.long 0xBC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xBC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xBC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xBC 0.--7. 1. "PARAM,"
line.long 0xC0 "INST24_0,"
line.long 0xC4 "INST24_1,"
hexmask.long.byte 0xC4 25.--31. 1. "NU2,"
rbitfld.long 0xC4 24. "NU1," "0,1"
bitfld.long 0xC4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xC4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xC4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xC4 0.--7. 1. "PARAM,"
line.long 0xC8 "INST25_0,"
line.long 0xCC "INST25_1,"
hexmask.long.byte 0xCC 25.--31. 1. "NU2,"
rbitfld.long 0xCC 24. "NU1," "0,1"
bitfld.long 0xCC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xCC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xCC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xCC 0.--7. 1. "PARAM,"
line.long 0xD0 "INST26_0,"
line.long 0xD4 "INST26_1,"
hexmask.long.byte 0xD4 25.--31. 1. "NU2,"
rbitfld.long 0xD4 24. "NU1," "0,1"
bitfld.long 0xD4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xD4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xD4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xD4 0.--7. 1. "PARAM,"
line.long 0xD8 "INST27_0,"
line.long 0xDC "INST27_1,"
hexmask.long.byte 0xDC 25.--31. 1. "NU2,"
rbitfld.long 0xDC 24. "NU1," "0,1"
bitfld.long 0xDC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xDC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xDC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xDC 0.--7. 1. "PARAM,"
line.long 0xE0 "INST28_0,"
line.long 0xE4 "INST28_1,"
hexmask.long.byte 0xE4 25.--31. 1. "NU2,"
rbitfld.long 0xE4 24. "NU1," "0,1"
bitfld.long 0xE4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xE4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xE4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xE4 0.--7. 1. "PARAM,"
line.long 0xE8 "INST29_0,"
line.long 0xEC "INST29_1,"
hexmask.long.byte 0xEC 25.--31. 1. "NU2,"
rbitfld.long 0xEC 24. "NU1," "0,1"
bitfld.long 0xEC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xEC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xEC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xEC 0.--7. 1. "PARAM,"
line.long 0xF0 "INST30_0,"
line.long 0xF4 "INST30_1,"
hexmask.long.byte 0xF4 25.--31. 1. "NU2,"
rbitfld.long 0xF4 24. "NU1," "0,1"
bitfld.long 0xF4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xF4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xF4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xF4 0.--7. 1. "PARAM,"
line.long 0xF8 "INST31_0,"
line.long 0xFC "INST31_1,"
hexmask.long.byte 0xFC 25.--31. 1. "NU2,"
rbitfld.long 0xFC 24. "NU1," "0,1"
bitfld.long 0xFC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xFC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xFC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xFC 0.--7. 1. "PARAM,"
line.long 0x100 "INST32_0,"
line.long 0x104 "INST32_1,"
hexmask.long.byte 0x104 25.--31. 1. "NU2,"
rbitfld.long 0x104 24. "NU1," "0,1"
bitfld.long 0x104 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x104 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x104 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x104 0.--7. 1. "PARAM,"
line.long 0x108 "INST33_0,"
line.long 0x10C "INST33_1,"
hexmask.long.byte 0x10C 25.--31. 1. "NU2,"
rbitfld.long 0x10C 24. "NU1," "0,1"
bitfld.long 0x10C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x10C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x10C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x10C 0.--7. 1. "PARAM,"
line.long 0x110 "INST34_0,"
line.long 0x114 "INST34_1,"
hexmask.long.byte 0x114 25.--31. 1. "NU2,"
rbitfld.long 0x114 24. "NU1," "0,1"
bitfld.long 0x114 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x114 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x114 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x114 0.--7. 1. "PARAM,"
line.long 0x118 "INST35_0,"
line.long 0x11C "INST35_1,"
hexmask.long.byte 0x11C 25.--31. 1. "NU2,"
rbitfld.long 0x11C 24. "NU1," "0,1"
bitfld.long 0x11C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x11C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x11C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x11C 0.--7. 1. "PARAM,"
line.long 0x120 "INST36_0,"
line.long 0x124 "INST36_1,"
hexmask.long.byte 0x124 25.--31. 1. "NU2,"
rbitfld.long 0x124 24. "NU1," "0,1"
bitfld.long 0x124 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x124 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x124 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x124 0.--7. 1. "PARAM,"
line.long 0x128 "INST37_0,"
line.long 0x12C "INST37_1,"
hexmask.long.byte 0x12C 25.--31. 1. "NU2,"
rbitfld.long 0x12C 24. "NU1," "0,1"
bitfld.long 0x12C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x12C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x12C 0.--7. 1. "PARAM,"
line.long 0x130 "INST38_0,"
line.long 0x134 "INST38_1,"
hexmask.long.byte 0x134 25.--31. 1. "NU2,"
rbitfld.long 0x134 24. "NU1," "0,1"
bitfld.long 0x134 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x134 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x134 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x134 0.--7. 1. "PARAM,"
line.long 0x138 "INST39_0,"
line.long 0x13C "INST39_1,"
hexmask.long.byte 0x13C 25.--31. 1. "NU2,"
rbitfld.long 0x13C 24. "NU1," "0,1"
bitfld.long 0x13C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x13C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x13C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x13C 0.--7. 1. "PARAM,"
line.long 0x140 "INST40_0,"
line.long 0x144 "INST40_1,"
hexmask.long.byte 0x144 25.--31. 1. "NU2,"
rbitfld.long 0x144 24. "NU1," "0,1"
bitfld.long 0x144 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x144 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x144 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x144 0.--7. 1. "PARAM,"
line.long 0x148 "INST41_0,"
line.long 0x14C "INST41_1,"
hexmask.long.byte 0x14C 25.--31. 1. "NU2,"
rbitfld.long 0x14C 24. "NU1," "0,1"
bitfld.long 0x14C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x14C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x14C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x14C 0.--7. 1. "PARAM,"
line.long 0x150 "INST42_0,"
line.long 0x154 "INST42_1,"
hexmask.long.byte 0x154 25.--31. 1. "NU2,"
rbitfld.long 0x154 24. "NU1," "0,1"
bitfld.long 0x154 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x154 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x154 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x154 0.--7. 1. "PARAM,"
line.long 0x158 "INST43_0,"
line.long 0x15C "INST43_1,"
hexmask.long.byte 0x15C 25.--31. 1. "NU2,"
rbitfld.long 0x15C 24. "NU1," "0,1"
bitfld.long 0x15C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x15C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x15C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x15C 0.--7. 1. "PARAM,"
line.long 0x160 "INST44_0,"
line.long 0x164 "INST44_1,"
hexmask.long.byte 0x164 25.--31. 1. "NU2,"
rbitfld.long 0x164 24. "NU1," "0,1"
bitfld.long 0x164 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x164 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x164 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x164 0.--7. 1. "PARAM,"
line.long 0x168 "INST45_0,"
line.long 0x16C "INST45_1,"
hexmask.long.byte 0x16C 25.--31. 1. "NU2,"
rbitfld.long 0x16C 24. "NU1," "0,1"
bitfld.long 0x16C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x16C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x16C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x16C 0.--7. 1. "PARAM,"
line.long 0x170 "INST46_0,"
line.long 0x174 "INST46_1,"
hexmask.long.byte 0x174 25.--31. 1. "NU2,"
rbitfld.long 0x174 24. "NU1," "0,1"
bitfld.long 0x174 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x174 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x174 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x174 0.--7. 1. "PARAM,"
line.long 0x178 "INST47_0,"
line.long 0x17C "INST47_1,"
hexmask.long.byte 0x17C 25.--31. 1. "NU2,"
rbitfld.long 0x17C 24. "NU1," "0,1"
bitfld.long 0x17C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x17C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x17C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x17C 0.--7. 1. "PARAM,"
line.long 0x180 "INST48_0,"
line.long 0x184 "INST48_1,"
hexmask.long.byte 0x184 25.--31. 1. "NU2,"
rbitfld.long 0x184 24. "NU1," "0,1"
bitfld.long 0x184 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x184 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x184 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x184 0.--7. 1. "PARAM,"
line.long 0x188 "INST49_0,"
line.long 0x18C "INST49_1,"
hexmask.long.byte 0x18C 25.--31. 1. "NU2,"
rbitfld.long 0x18C 24. "NU1," "0,1"
bitfld.long 0x18C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x18C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x18C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x18C 0.--7. 1. "PARAM,"
line.long 0x190 "INST50_0,"
line.long 0x194 "INST50_1,"
hexmask.long.byte 0x194 25.--31. 1. "NU2,"
rbitfld.long 0x194 24. "NU1," "0,1"
bitfld.long 0x194 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x194 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x194 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x194 0.--7. 1. "PARAM,"
line.long 0x198 "INST51_0,"
line.long 0x19C "INST51_1,"
hexmask.long.byte 0x19C 25.--31. 1. "NU2,"
rbitfld.long 0x19C 24. "NU1," "0,1"
bitfld.long 0x19C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x19C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x19C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x19C 0.--7. 1. "PARAM,"
line.long 0x1A0 "INST52_0,"
line.long 0x1A4 "INST52_1,"
hexmask.long.byte 0x1A4 25.--31. 1. "NU2,"
rbitfld.long 0x1A4 24. "NU1," "0,1"
bitfld.long 0x1A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1A4 0.--7. 1. "PARAM,"
line.long 0x1A8 "INST53_0,"
line.long 0x1AC "INST53_1,"
hexmask.long.byte 0x1AC 25.--31. 1. "NU2,"
rbitfld.long 0x1AC 24. "NU1," "0,1"
bitfld.long 0x1AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1AC 0.--7. 1. "PARAM,"
line.long 0x1B0 "INST54_0,"
line.long 0x1B4 "INST54_1,"
hexmask.long.byte 0x1B4 25.--31. 1. "NU2,"
rbitfld.long 0x1B4 24. "NU1," "0,1"
bitfld.long 0x1B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1B4 0.--7. 1. "PARAM,"
line.long 0x1B8 "INST55_0,"
line.long 0x1BC "INST55_1,"
hexmask.long.byte 0x1BC 25.--31. 1. "NU2,"
rbitfld.long 0x1BC 24. "NU1," "0,1"
bitfld.long 0x1BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1BC 0.--7. 1. "PARAM,"
line.long 0x1C0 "INST56_0,"
line.long 0x1C4 "INST56_1,"
hexmask.long.byte 0x1C4 25.--31. 1. "NU2,"
rbitfld.long 0x1C4 24. "NU1," "0,1"
bitfld.long 0x1C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1C4 0.--7. 1. "PARAM,"
line.long 0x1C8 "INST57_0,"
line.long 0x1CC "INST57_1,"
hexmask.long.byte 0x1CC 25.--31. 1. "NU2,"
rbitfld.long 0x1CC 24. "NU1," "0,1"
bitfld.long 0x1CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1CC 0.--7. 1. "PARAM,"
line.long 0x1D0 "INST58_0,"
line.long 0x1D4 "INST58_1,"
hexmask.long.byte 0x1D4 25.--31. 1. "NU2,"
rbitfld.long 0x1D4 24. "NU1," "0,1"
bitfld.long 0x1D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1D4 0.--7. 1. "PARAM,"
line.long 0x1D8 "INST59_0,"
line.long 0x1DC "INST59_1,"
hexmask.long.byte 0x1DC 25.--31. 1. "NU2,"
rbitfld.long 0x1DC 24. "NU1," "0,1"
bitfld.long 0x1DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1DC 0.--7. 1. "PARAM,"
line.long 0x1E0 "INST60_0,"
line.long 0x1E4 "INST60_1,"
hexmask.long.byte 0x1E4 25.--31. 1. "NU2,"
rbitfld.long 0x1E4 24. "NU1," "0,1"
bitfld.long 0x1E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1E4 0.--7. 1. "PARAM,"
line.long 0x1E8 "INST61_0,"
line.long 0x1EC "INST61_1,"
hexmask.long.byte 0x1EC 25.--31. 1. "NU2,"
rbitfld.long 0x1EC 24. "NU1," "0,1"
bitfld.long 0x1EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1EC 0.--7. 1. "PARAM,"
line.long 0x1F0 "INST62_0,"
line.long 0x1F4 "INST62_1,"
hexmask.long.byte 0x1F4 25.--31. 1. "NU2,"
rbitfld.long 0x1F4 24. "NU1," "0,1"
bitfld.long 0x1F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1F4 0.--7. 1. "PARAM,"
line.long 0x1F8 "INST63_0,"
line.long 0x1FC "INST63_1,"
hexmask.long.byte 0x1FC 25.--31. 1. "NU2,"
rbitfld.long 0x1FC 24. "NU1," "0,1"
bitfld.long 0x1FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1FC 0.--7. 1. "PARAM,"
line.long 0x200 "INST64_0,"
line.long 0x204 "INST64_1,"
hexmask.long.byte 0x204 25.--31. 1. "NU2,"
rbitfld.long 0x204 24. "NU1," "0,1"
bitfld.long 0x204 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x204 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x204 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x204 0.--7. 1. "PARAM,"
line.long 0x208 "INST65_0,"
line.long 0x20C "INST65_1,"
hexmask.long.byte 0x20C 25.--31. 1. "NU2,"
rbitfld.long 0x20C 24. "NU1," "0,1"
bitfld.long 0x20C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x20C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x20C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x20C 0.--7. 1. "PARAM,"
line.long 0x210 "INST66_0,"
line.long 0x214 "INST66_1,"
hexmask.long.byte 0x214 25.--31. 1. "NU2,"
rbitfld.long 0x214 24. "NU1," "0,1"
bitfld.long 0x214 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x214 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x214 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x214 0.--7. 1. "PARAM,"
line.long 0x218 "INST67_0,"
line.long 0x21C "INST67_1,"
hexmask.long.byte 0x21C 25.--31. 1. "NU2,"
rbitfld.long 0x21C 24. "NU1," "0,1"
bitfld.long 0x21C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x21C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x21C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x21C 0.--7. 1. "PARAM,"
line.long 0x220 "INST68_0,"
line.long 0x224 "INST68_1,"
hexmask.long.byte 0x224 25.--31. 1. "NU2,"
rbitfld.long 0x224 24. "NU1," "0,1"
bitfld.long 0x224 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x224 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x224 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x224 0.--7. 1. "PARAM,"
line.long 0x228 "INST69_0,"
line.long 0x22C "INST69_1,"
hexmask.long.byte 0x22C 25.--31. 1. "NU2,"
rbitfld.long 0x22C 24. "NU1," "0,1"
bitfld.long 0x22C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x22C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x22C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x22C 0.--7. 1. "PARAM,"
line.long 0x230 "INST70_0,"
line.long 0x234 "INST70_1,"
hexmask.long.byte 0x234 25.--31. 1. "NU2,"
rbitfld.long 0x234 24. "NU1," "0,1"
bitfld.long 0x234 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x234 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x234 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x234 0.--7. 1. "PARAM,"
line.long 0x238 "INST71_0,"
line.long 0x23C "INST71_1,"
hexmask.long.byte 0x23C 25.--31. 1. "NU2,"
rbitfld.long 0x23C 24. "NU1," "0,1"
bitfld.long 0x23C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x23C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x23C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x23C 0.--7. 1. "PARAM,"
line.long 0x240 "INST72_0,"
line.long 0x244 "INST72_1,"
hexmask.long.byte 0x244 25.--31. 1. "NU2,"
rbitfld.long 0x244 24. "NU1," "0,1"
bitfld.long 0x244 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x244 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x244 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x244 0.--7. 1. "PARAM,"
line.long 0x248 "INST73_0,"
line.long 0x24C "INST73_1,"
hexmask.long.byte 0x24C 25.--31. 1. "NU2,"
rbitfld.long 0x24C 24. "NU1," "0,1"
bitfld.long 0x24C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x24C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x24C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x24C 0.--7. 1. "PARAM,"
line.long 0x250 "INST74_0,"
line.long 0x254 "INST74_1,"
hexmask.long.byte 0x254 25.--31. 1. "NU2,"
rbitfld.long 0x254 24. "NU1," "0,1"
bitfld.long 0x254 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x254 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x254 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x254 0.--7. 1. "PARAM,"
line.long 0x258 "INST75_0,"
line.long 0x25C "INST75_1,"
hexmask.long.byte 0x25C 25.--31. 1. "NU2,"
rbitfld.long 0x25C 24. "NU1," "0,1"
bitfld.long 0x25C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x25C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x25C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x25C 0.--7. 1. "PARAM,"
line.long 0x260 "INST76_0,"
line.long 0x264 "INST76_1,"
hexmask.long.byte 0x264 25.--31. 1. "NU2,"
rbitfld.long 0x264 24. "NU1," "0,1"
bitfld.long 0x264 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x264 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x264 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x264 0.--7. 1. "PARAM,"
line.long 0x268 "INST77_0,"
line.long 0x26C "INST77_1,"
hexmask.long.byte 0x26C 25.--31. 1. "NU2,"
rbitfld.long 0x26C 24. "NU1," "0,1"
bitfld.long 0x26C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x26C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x26C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x26C 0.--7. 1. "PARAM,"
line.long 0x270 "INST78_0,"
line.long 0x274 "INST78_1,"
hexmask.long.byte 0x274 25.--31. 1. "NU2,"
rbitfld.long 0x274 24. "NU1," "0,1"
bitfld.long 0x274 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x274 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x274 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x274 0.--7. 1. "PARAM,"
line.long 0x278 "INST79_0,"
line.long 0x27C "INST79_1,"
hexmask.long.byte 0x27C 25.--31. 1. "NU2,"
rbitfld.long 0x27C 24. "NU1," "0,1"
bitfld.long 0x27C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x27C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x27C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x27C 0.--7. 1. "PARAM,"
line.long 0x280 "INST80_0,"
line.long 0x284 "INST80_1,"
hexmask.long.byte 0x284 25.--31. 1. "NU2,"
rbitfld.long 0x284 24. "NU1," "0,1"
bitfld.long 0x284 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x284 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x284 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x284 0.--7. 1. "PARAM,"
line.long 0x288 "INST81_0,"
line.long 0x28C "INST81_1,"
hexmask.long.byte 0x28C 25.--31. 1. "NU2,"
rbitfld.long 0x28C 24. "NU1," "0,1"
bitfld.long 0x28C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x28C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x28C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x28C 0.--7. 1. "PARAM,"
line.long 0x290 "INST82_0,"
line.long 0x294 "INST82_1,"
hexmask.long.byte 0x294 25.--31. 1. "NU2,"
rbitfld.long 0x294 24. "NU1," "0,1"
bitfld.long 0x294 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x294 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x294 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x294 0.--7. 1. "PARAM,"
line.long 0x298 "INST83_0,"
line.long 0x29C "INST83_1,"
hexmask.long.byte 0x29C 25.--31. 1. "NU2,"
rbitfld.long 0x29C 24. "NU1," "0,1"
bitfld.long 0x29C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x29C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x29C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x29C 0.--7. 1. "PARAM,"
line.long 0x2A0 "INST84_0,"
line.long 0x2A4 "INST84_1,"
hexmask.long.byte 0x2A4 25.--31. 1. "NU2,"
rbitfld.long 0x2A4 24. "NU1," "0,1"
bitfld.long 0x2A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2A4 0.--7. 1. "PARAM,"
line.long 0x2A8 "INST85_0,"
line.long 0x2AC "INST85_1,"
hexmask.long.byte 0x2AC 25.--31. 1. "NU2,"
rbitfld.long 0x2AC 24. "NU1," "0,1"
bitfld.long 0x2AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2AC 0.--7. 1. "PARAM,"
line.long 0x2B0 "INST86_0,"
line.long 0x2B4 "INST86_1,"
hexmask.long.byte 0x2B4 25.--31. 1. "NU2,"
rbitfld.long 0x2B4 24. "NU1," "0,1"
bitfld.long 0x2B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2B4 0.--7. 1. "PARAM,"
line.long 0x2B8 "INST87_0,"
line.long 0x2BC "INST87_1,"
hexmask.long.byte 0x2BC 25.--31. 1. "NU2,"
rbitfld.long 0x2BC 24. "NU1," "0,1"
bitfld.long 0x2BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2BC 0.--7. 1. "PARAM,"
line.long 0x2C0 "INST88_0,"
line.long 0x2C4 "INST88_1,"
hexmask.long.byte 0x2C4 25.--31. 1. "NU2,"
rbitfld.long 0x2C4 24. "NU1," "0,1"
bitfld.long 0x2C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2C4 0.--7. 1. "PARAM,"
line.long 0x2C8 "INST89_0,"
line.long 0x2CC "INST89_1,"
hexmask.long.byte 0x2CC 25.--31. 1. "NU2,"
rbitfld.long 0x2CC 24. "NU1," "0,1"
bitfld.long 0x2CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2CC 0.--7. 1. "PARAM,"
line.long 0x2D0 "INST90_0,"
line.long 0x2D4 "INST90_1,"
hexmask.long.byte 0x2D4 25.--31. 1. "NU2,"
rbitfld.long 0x2D4 24. "NU1," "0,1"
bitfld.long 0x2D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2D4 0.--7. 1. "PARAM,"
line.long 0x2D8 "INST91_0,"
line.long 0x2DC "INST91_1,"
hexmask.long.byte 0x2DC 25.--31. 1. "NU2,"
rbitfld.long 0x2DC 24. "NU1," "0,1"
bitfld.long 0x2DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2DC 0.--7. 1. "PARAM,"
line.long 0x2E0 "INST92_0,"
line.long 0x2E4 "INST92_1,"
hexmask.long.byte 0x2E4 25.--31. 1. "NU2,"
rbitfld.long 0x2E4 24. "NU1," "0,1"
bitfld.long 0x2E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2E4 0.--7. 1. "PARAM,"
line.long 0x2E8 "INST93_0,"
line.long 0x2EC "INST93_1,"
hexmask.long.byte 0x2EC 25.--31. 1. "NU2,"
rbitfld.long 0x2EC 24. "NU1," "0,1"
bitfld.long 0x2EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2EC 0.--7. 1. "PARAM,"
line.long 0x2F0 "INST94_0,"
line.long 0x2F4 "INST94_1,"
hexmask.long.byte 0x2F4 25.--31. 1. "NU2,"
rbitfld.long 0x2F4 24. "NU1," "0,1"
bitfld.long 0x2F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2F4 0.--7. 1. "PARAM,"
line.long 0x2F8 "INST95_0,"
line.long 0x2FC "INST95_1,"
hexmask.long.byte 0x2FC 25.--31. 1. "NU2,"
rbitfld.long 0x2FC 24. "NU1," "0,1"
bitfld.long 0x2FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2FC 0.--7. 1. "PARAM,"
line.long 0x300 "INST96_0,"
line.long 0x304 "INST96_1,"
hexmask.long.byte 0x304 25.--31. 1. "NU2,"
rbitfld.long 0x304 24. "NU1," "0,1"
bitfld.long 0x304 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x304 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x304 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x304 0.--7. 1. "PARAM,"
line.long 0x308 "INST97_0,"
line.long 0x30C "INST97_1,"
hexmask.long.byte 0x30C 25.--31. 1. "NU2,"
rbitfld.long 0x30C 24. "NU1," "0,1"
bitfld.long 0x30C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x30C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x30C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x30C 0.--7. 1. "PARAM,"
line.long 0x310 "INST98_0,"
line.long 0x314 "INST98_1,"
hexmask.long.byte 0x314 25.--31. 1. "NU2,"
rbitfld.long 0x314 24. "NU1," "0,1"
bitfld.long 0x314 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x314 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x314 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x314 0.--7. 1. "PARAM,"
line.long 0x318 "INST99_0,"
line.long 0x31C "INST99_1,"
hexmask.long.byte 0x31C 25.--31. 1. "NU2,"
rbitfld.long 0x31C 24. "NU1," "0,1"
bitfld.long 0x31C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x31C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x31C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x31C 0.--7. 1. "PARAM,"
line.long 0x320 "INST100_0,"
line.long 0x324 "INST100_1,"
hexmask.long.byte 0x324 25.--31. 1. "NU2,"
rbitfld.long 0x324 24. "NU1," "0,1"
bitfld.long 0x324 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x324 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x324 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x324 0.--7. 1. "PARAM,"
line.long 0x328 "INST101_0,"
line.long 0x32C "INST101_1,"
hexmask.long.byte 0x32C 25.--31. 1. "NU2,"
rbitfld.long 0x32C 24. "NU1," "0,1"
bitfld.long 0x32C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x32C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x32C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x32C 0.--7. 1. "PARAM,"
line.long 0x330 "INST102_0,"
line.long 0x334 "INST102_1,"
hexmask.long.byte 0x334 25.--31. 1. "NU2,"
rbitfld.long 0x334 24. "NU1," "0,1"
bitfld.long 0x334 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x334 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x334 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x334 0.--7. 1. "PARAM,"
line.long 0x338 "INST103_0,"
line.long 0x33C "INST103_1,"
hexmask.long.byte 0x33C 25.--31. 1. "NU2,"
rbitfld.long 0x33C 24. "NU1," "0,1"
bitfld.long 0x33C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x33C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x33C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x33C 0.--7. 1. "PARAM,"
line.long 0x340 "INST104_0,"
line.long 0x344 "INST104_1,"
hexmask.long.byte 0x344 25.--31. 1. "NU2,"
rbitfld.long 0x344 24. "NU1," "0,1"
bitfld.long 0x344 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x344 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x344 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x344 0.--7. 1. "PARAM,"
line.long 0x348 "INST105_0,"
line.long 0x34C "INST105_1,"
hexmask.long.byte 0x34C 25.--31. 1. "NU2,"
rbitfld.long 0x34C 24. "NU1," "0,1"
bitfld.long 0x34C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x34C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x34C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x34C 0.--7. 1. "PARAM,"
line.long 0x350 "INST106_0,"
line.long 0x354 "INST106_1,"
hexmask.long.byte 0x354 25.--31. 1. "NU2,"
rbitfld.long 0x354 24. "NU1," "0,1"
bitfld.long 0x354 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x354 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x354 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x354 0.--7. 1. "PARAM,"
line.long 0x358 "INST107_0,"
line.long 0x35C "INST107_1,"
hexmask.long.byte 0x35C 25.--31. 1. "NU2,"
rbitfld.long 0x35C 24. "NU1," "0,1"
bitfld.long 0x35C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x35C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x35C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x35C 0.--7. 1. "PARAM,"
line.long 0x360 "INST108_0,"
line.long 0x364 "INST108_1,"
hexmask.long.byte 0x364 25.--31. 1. "NU2,"
rbitfld.long 0x364 24. "NU1," "0,1"
bitfld.long 0x364 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x364 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x364 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x364 0.--7. 1. "PARAM,"
line.long 0x368 "INST109_0,"
line.long 0x36C "INST109_1,"
hexmask.long.byte 0x36C 25.--31. 1. "NU2,"
rbitfld.long 0x36C 24. "NU1," "0,1"
bitfld.long 0x36C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x36C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x36C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x36C 0.--7. 1. "PARAM,"
line.long 0x370 "INST110_0,"
line.long 0x374 "INST110_1,"
hexmask.long.byte 0x374 25.--31. 1. "NU2,"
rbitfld.long 0x374 24. "NU1," "0,1"
bitfld.long 0x374 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x374 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x374 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x374 0.--7. 1. "PARAM,"
line.long 0x378 "INST111_0,"
line.long 0x37C "INST111_1,"
hexmask.long.byte 0x37C 25.--31. 1. "NU2,"
rbitfld.long 0x37C 24. "NU1," "0,1"
bitfld.long 0x37C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x37C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x37C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x37C 0.--7. 1. "PARAM,"
line.long 0x380 "INST112_0,"
line.long 0x384 "INST112_1,"
hexmask.long.byte 0x384 25.--31. 1. "NU2,"
rbitfld.long 0x384 24. "NU1," "0,1"
bitfld.long 0x384 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x384 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x384 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x384 0.--7. 1. "PARAM,"
line.long 0x388 "INST113_0,"
line.long 0x38C "INST113_1,"
hexmask.long.byte 0x38C 25.--31. 1. "NU2,"
rbitfld.long 0x38C 24. "NU1," "0,1"
bitfld.long 0x38C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x38C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x38C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x38C 0.--7. 1. "PARAM,"
line.long 0x390 "INST114_0,"
line.long 0x394 "INST114_1,"
hexmask.long.byte 0x394 25.--31. 1. "NU2,"
rbitfld.long 0x394 24. "NU1," "0,1"
bitfld.long 0x394 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x394 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x394 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x394 0.--7. 1. "PARAM,"
line.long 0x398 "INST115_0,"
line.long 0x39C "INST115_1,"
hexmask.long.byte 0x39C 25.--31. 1. "NU2,"
rbitfld.long 0x39C 24. "NU1," "0,1"
bitfld.long 0x39C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x39C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x39C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x39C 0.--7. 1. "PARAM,"
line.long 0x3A0 "INST116_0,"
line.long 0x3A4 "INST116_1,"
hexmask.long.byte 0x3A4 25.--31. 1. "NU2,"
rbitfld.long 0x3A4 24. "NU1," "0,1"
bitfld.long 0x3A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3A4 0.--7. 1. "PARAM,"
line.long 0x3A8 "INST117_0,"
line.long 0x3AC "INST117_1,"
hexmask.long.byte 0x3AC 25.--31. 1. "NU2,"
rbitfld.long 0x3AC 24. "NU1," "0,1"
bitfld.long 0x3AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3AC 0.--7. 1. "PARAM,"
line.long 0x3B0 "INST118_0,"
line.long 0x3B4 "INST118_1,"
hexmask.long.byte 0x3B4 25.--31. 1. "NU2,"
rbitfld.long 0x3B4 24. "NU1," "0,1"
bitfld.long 0x3B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3B4 0.--7. 1. "PARAM,"
line.long 0x3B8 "INST119_0,"
line.long 0x3BC "INST119_1,"
hexmask.long.byte 0x3BC 25.--31. 1. "NU2,"
rbitfld.long 0x3BC 24. "NU1," "0,1"
bitfld.long 0x3BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3BC 0.--7. 1. "PARAM,"
line.long 0x3C0 "INST120_0,"
line.long 0x3C4 "INST120_1,"
hexmask.long.byte 0x3C4 25.--31. 1. "NU2,"
rbitfld.long 0x3C4 24. "NU1," "0,1"
bitfld.long 0x3C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3C4 0.--7. 1. "PARAM,"
line.long 0x3C8 "INST121_0,"
line.long 0x3CC "INST121_1,"
hexmask.long.byte 0x3CC 25.--31. 1. "NU2,"
rbitfld.long 0x3CC 24. "NU1," "0,1"
bitfld.long 0x3CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3CC 0.--7. 1. "PARAM,"
line.long 0x3D0 "INST122_0,"
line.long 0x3D4 "INST122_1,"
hexmask.long.byte 0x3D4 25.--31. 1. "NU2,"
rbitfld.long 0x3D4 24. "NU1," "0,1"
bitfld.long 0x3D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3D4 0.--7. 1. "PARAM,"
line.long 0x3D8 "INST123_0,"
line.long 0x3DC "INST123_1,"
hexmask.long.byte 0x3DC 25.--31. 1. "NU2,"
rbitfld.long 0x3DC 24. "NU1," "0,1"
bitfld.long 0x3DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3DC 0.--7. 1. "PARAM,"
line.long 0x3E0 "INST124_0,"
line.long 0x3E4 "INST124_1,"
hexmask.long.byte 0x3E4 25.--31. 1. "NU2,"
rbitfld.long 0x3E4 24. "NU1," "0,1"
bitfld.long 0x3E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3E4 0.--7. 1. "PARAM,"
line.long 0x3E8 "INST125_0,"
line.long 0x3EC "INST125_1,"
hexmask.long.byte 0x3EC 25.--31. 1. "NU2,"
rbitfld.long 0x3EC 24. "NU1," "0,1"
bitfld.long 0x3EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3EC 0.--7. 1. "PARAM,"
line.long 0x3F0 "INST126_0,"
line.long 0x3F4 "INST126_1,"
hexmask.long.byte 0x3F4 25.--31. 1. "NU2,"
rbitfld.long 0x3F4 24. "NU1," "0,1"
bitfld.long 0x3F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3F4 0.--7. 1. "PARAM,"
line.long 0x3F8 "INST127_0,"
line.long 0x3FC "INST127_1,"
hexmask.long.byte 0x3FC 25.--31. 1. "NU2,"
rbitfld.long 0x3FC 24. "NU1," "0,1"
bitfld.long 0x3FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3FC 0.--7. 1. "PARAM,"
line.long 0x400 "INST128_0,"
line.long 0x404 "INST128_1,"
hexmask.long.byte 0x404 25.--31. 1. "NU2,"
rbitfld.long 0x404 24. "NU1," "0,1"
bitfld.long 0x404 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x404 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x404 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x404 0.--7. 1. "PARAM,"
line.long 0x408 "INST129_0,"
line.long 0x40C "INST129_1,"
hexmask.long.byte 0x40C 25.--31. 1. "NU2,"
rbitfld.long 0x40C 24. "NU1," "0,1"
bitfld.long 0x40C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x40C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x40C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x40C 0.--7. 1. "PARAM,"
line.long 0x410 "INST130_0,"
line.long 0x414 "INST130_1,"
hexmask.long.byte 0x414 25.--31. 1. "NU2,"
rbitfld.long 0x414 24. "NU1," "0,1"
bitfld.long 0x414 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x414 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x414 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x414 0.--7. 1. "PARAM,"
line.long 0x418 "INST131_0,"
line.long 0x41C "INST131_1,"
hexmask.long.byte 0x41C 25.--31. 1. "NU2,"
rbitfld.long 0x41C 24. "NU1," "0,1"
bitfld.long 0x41C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x41C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x41C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x41C 0.--7. 1. "PARAM,"
line.long 0x420 "INST132_0,"
line.long 0x424 "INST132_1,"
hexmask.long.byte 0x424 25.--31. 1. "NU2,"
rbitfld.long 0x424 24. "NU1," "0,1"
bitfld.long 0x424 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x424 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x424 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x424 0.--7. 1. "PARAM,"
line.long 0x428 "INST133_0,"
line.long 0x42C "INST133_1,"
hexmask.long.byte 0x42C 25.--31. 1. "NU2,"
rbitfld.long 0x42C 24. "NU1," "0,1"
bitfld.long 0x42C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x42C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x42C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x42C 0.--7. 1. "PARAM,"
line.long 0x430 "INST134_0,"
line.long 0x434 "INST134_1,"
hexmask.long.byte 0x434 25.--31. 1. "NU2,"
rbitfld.long 0x434 24. "NU1," "0,1"
bitfld.long 0x434 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x434 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x434 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x434 0.--7. 1. "PARAM,"
line.long 0x438 "INST135_0,"
line.long 0x43C "INST135_1,"
hexmask.long.byte 0x43C 25.--31. 1. "NU2,"
rbitfld.long 0x43C 24. "NU1," "0,1"
bitfld.long 0x43C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x43C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x43C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x43C 0.--7. 1. "PARAM,"
line.long 0x440 "INST136_0,"
line.long 0x444 "INST136_1,"
hexmask.long.byte 0x444 25.--31. 1. "NU2,"
rbitfld.long 0x444 24. "NU1," "0,1"
bitfld.long 0x444 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x444 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x444 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x444 0.--7. 1. "PARAM,"
line.long 0x448 "INST137_0,"
line.long 0x44C "INST137_1,"
hexmask.long.byte 0x44C 25.--31. 1. "NU2,"
rbitfld.long 0x44C 24. "NU1," "0,1"
bitfld.long 0x44C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x44C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x44C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x44C 0.--7. 1. "PARAM,"
line.long 0x450 "INST138_0,"
line.long 0x454 "INST138_1,"
hexmask.long.byte 0x454 25.--31. 1. "NU2,"
rbitfld.long 0x454 24. "NU1," "0,1"
bitfld.long 0x454 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x454 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x454 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x454 0.--7. 1. "PARAM,"
line.long 0x458 "INST139_0,"
line.long 0x45C "INST139_1,"
hexmask.long.byte 0x45C 25.--31. 1. "NU2,"
rbitfld.long 0x45C 24. "NU1," "0,1"
bitfld.long 0x45C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x45C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x45C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x45C 0.--7. 1. "PARAM,"
line.long 0x460 "INST140_0,"
line.long 0x464 "INST140_1,"
hexmask.long.byte 0x464 25.--31. 1. "NU2,"
rbitfld.long 0x464 24. "NU1," "0,1"
bitfld.long 0x464 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x464 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x464 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x464 0.--7. 1. "PARAM,"
line.long 0x468 "INST141_0,"
line.long 0x46C "INST141_1,"
hexmask.long.byte 0x46C 25.--31. 1. "NU2,"
rbitfld.long 0x46C 24. "NU1," "0,1"
bitfld.long 0x46C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x46C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x46C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x46C 0.--7. 1. "PARAM,"
line.long 0x470 "INST142_0,"
line.long 0x474 "INST142_1,"
hexmask.long.byte 0x474 25.--31. 1. "NU2,"
rbitfld.long 0x474 24. "NU1," "0,1"
bitfld.long 0x474 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x474 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x474 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x474 0.--7. 1. "PARAM,"
line.long 0x478 "INST143_0,"
line.long 0x47C "INST143_1,"
hexmask.long.byte 0x47C 25.--31. 1. "NU2,"
rbitfld.long 0x47C 24. "NU1," "0,1"
bitfld.long 0x47C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x47C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x47C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x47C 0.--7. 1. "PARAM,"
line.long 0x480 "INST144_0,"
line.long 0x484 "INST144_1,"
hexmask.long.byte 0x484 25.--31. 1. "NU2,"
rbitfld.long 0x484 24. "NU1," "0,1"
bitfld.long 0x484 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x484 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x484 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x484 0.--7. 1. "PARAM,"
line.long 0x488 "INST145_0,"
line.long 0x48C "INST145_1,"
hexmask.long.byte 0x48C 25.--31. 1. "NU2,"
rbitfld.long 0x48C 24. "NU1," "0,1"
bitfld.long 0x48C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x48C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x48C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x48C 0.--7. 1. "PARAM,"
line.long 0x490 "INST146_0,"
line.long 0x494 "INST146_1,"
hexmask.long.byte 0x494 25.--31. 1. "NU2,"
rbitfld.long 0x494 24. "NU1," "0,1"
bitfld.long 0x494 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x494 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x494 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x494 0.--7. 1. "PARAM,"
line.long 0x498 "INST147_0,"
line.long 0x49C "INST147_1,"
hexmask.long.byte 0x49C 25.--31. 1. "NU2,"
rbitfld.long 0x49C 24. "NU1," "0,1"
bitfld.long 0x49C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x49C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x49C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x49C 0.--7. 1. "PARAM,"
line.long 0x4A0 "INST148_0,"
line.long 0x4A4 "INST148_1,"
hexmask.long.byte 0x4A4 25.--31. 1. "NU2,"
rbitfld.long 0x4A4 24. "NU1," "0,1"
bitfld.long 0x4A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4A4 0.--7. 1. "PARAM,"
line.long 0x4A8 "INST149_0,"
line.long 0x4AC "INST149_1,"
hexmask.long.byte 0x4AC 25.--31. 1. "NU2,"
rbitfld.long 0x4AC 24. "NU1," "0,1"
bitfld.long 0x4AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4AC 0.--7. 1. "PARAM,"
line.long 0x4B0 "INST150_0,"
line.long 0x4B4 "INST150_1,"
hexmask.long.byte 0x4B4 25.--31. 1. "NU2,"
rbitfld.long 0x4B4 24. "NU1," "0,1"
bitfld.long 0x4B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4B4 0.--7. 1. "PARAM,"
line.long 0x4B8 "INST151_0,"
line.long 0x4BC "INST151_1,"
hexmask.long.byte 0x4BC 25.--31. 1. "NU2,"
rbitfld.long 0x4BC 24. "NU1," "0,1"
bitfld.long 0x4BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4BC 0.--7. 1. "PARAM,"
line.long 0x4C0 "INST152_0,"
line.long 0x4C4 "INST152_1,"
hexmask.long.byte 0x4C4 25.--31. 1. "NU2,"
rbitfld.long 0x4C4 24. "NU1," "0,1"
bitfld.long 0x4C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4C4 0.--7. 1. "PARAM,"
line.long 0x4C8 "INST153_0,"
line.long 0x4CC "INST153_1,"
hexmask.long.byte 0x4CC 25.--31. 1. "NU2,"
rbitfld.long 0x4CC 24. "NU1," "0,1"
bitfld.long 0x4CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4CC 0.--7. 1. "PARAM,"
line.long 0x4D0 "INST154_0,"
line.long 0x4D4 "INST154_1,"
hexmask.long.byte 0x4D4 25.--31. 1. "NU2,"
rbitfld.long 0x4D4 24. "NU1," "0,1"
bitfld.long 0x4D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4D4 0.--7. 1. "PARAM,"
line.long 0x4D8 "INST155_0,"
line.long 0x4DC "INST155_1,"
hexmask.long.byte 0x4DC 25.--31. 1. "NU2,"
rbitfld.long 0x4DC 24. "NU1," "0,1"
bitfld.long 0x4DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4DC 0.--7. 1. "PARAM,"
line.long 0x4E0 "INST156_0,"
line.long 0x4E4 "INST156_1,"
hexmask.long.byte 0x4E4 25.--31. 1. "NU2,"
rbitfld.long 0x4E4 24. "NU1," "0,1"
bitfld.long 0x4E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4E4 0.--7. 1. "PARAM,"
line.long 0x4E8 "INST157_0,"
line.long 0x4EC "INST157_1,"
hexmask.long.byte 0x4EC 25.--31. 1. "NU2,"
rbitfld.long 0x4EC 24. "NU1," "0,1"
bitfld.long 0x4EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4EC 0.--7. 1. "PARAM,"
line.long 0x4F0 "INST158_0,"
line.long 0x4F4 "INST158_1,"
hexmask.long.byte 0x4F4 25.--31. 1. "NU2,"
rbitfld.long 0x4F4 24. "NU1," "0,1"
bitfld.long 0x4F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4F4 0.--7. 1. "PARAM,"
line.long 0x4F8 "INST159_0,"
line.long 0x4FC "INST159_1,"
hexmask.long.byte 0x4FC 25.--31. 1. "NU2,"
rbitfld.long 0x4FC 24. "NU1," "0,1"
bitfld.long 0x4FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4FC 0.--7. 1. "PARAM,"
line.long 0x500 "INST160_0,"
line.long 0x504 "INST160_1,"
hexmask.long.byte 0x504 25.--31. 1. "NU2,"
rbitfld.long 0x504 24. "NU1," "0,1"
bitfld.long 0x504 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x504 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x504 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x504 0.--7. 1. "PARAM,"
line.long 0x508 "INST161_0,"
line.long 0x50C "INST161_1,"
hexmask.long.byte 0x50C 25.--31. 1. "NU2,"
rbitfld.long 0x50C 24. "NU1," "0,1"
bitfld.long 0x50C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x50C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x50C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x50C 0.--7. 1. "PARAM,"
line.long 0x510 "INST162_0,"
line.long 0x514 "INST162_1,"
hexmask.long.byte 0x514 25.--31. 1. "NU2,"
rbitfld.long 0x514 24. "NU1," "0,1"
bitfld.long 0x514 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x514 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x514 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x514 0.--7. 1. "PARAM,"
line.long 0x518 "INST163_0,"
line.long 0x51C "INST163_1,"
hexmask.long.byte 0x51C 25.--31. 1. "NU2,"
rbitfld.long 0x51C 24. "NU1," "0,1"
bitfld.long 0x51C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x51C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x51C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x51C 0.--7. 1. "PARAM,"
line.long 0x520 "INST164_0,"
line.long 0x524 "INST164_1,"
hexmask.long.byte 0x524 25.--31. 1. "NU2,"
rbitfld.long 0x524 24. "NU1," "0,1"
bitfld.long 0x524 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x524 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x524 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x524 0.--7. 1. "PARAM,"
line.long 0x528 "INST165_0,"
line.long 0x52C "INST165_1,"
hexmask.long.byte 0x52C 25.--31. 1. "NU2,"
rbitfld.long 0x52C 24. "NU1," "0,1"
bitfld.long 0x52C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x52C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x52C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x52C 0.--7. 1. "PARAM,"
line.long 0x530 "INST166_0,"
line.long 0x534 "INST166_1,"
hexmask.long.byte 0x534 25.--31. 1. "NU2,"
rbitfld.long 0x534 24. "NU1," "0,1"
bitfld.long 0x534 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x534 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x534 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x534 0.--7. 1. "PARAM,"
line.long 0x538 "INST167_0,"
line.long 0x53C "INST167_1,"
hexmask.long.byte 0x53C 25.--31. 1. "NU2,"
rbitfld.long 0x53C 24. "NU1," "0,1"
bitfld.long 0x53C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x53C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x53C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x53C 0.--7. 1. "PARAM,"
line.long 0x540 "INST168_0,"
line.long 0x544 "INST168_1,"
hexmask.long.byte 0x544 25.--31. 1. "NU2,"
rbitfld.long 0x544 24. "NU1," "0,1"
bitfld.long 0x544 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x544 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x544 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x544 0.--7. 1. "PARAM,"
line.long 0x548 "INST169_0,"
line.long 0x54C "INST169_1,"
hexmask.long.byte 0x54C 25.--31. 1. "NU2,"
rbitfld.long 0x54C 24. "NU1," "0,1"
bitfld.long 0x54C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x54C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x54C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x54C 0.--7. 1. "PARAM,"
line.long 0x550 "INST170_0,"
line.long 0x554 "INST170_1,"
hexmask.long.byte 0x554 25.--31. 1. "NU2,"
rbitfld.long 0x554 24. "NU1," "0,1"
bitfld.long 0x554 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x554 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x554 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x554 0.--7. 1. "PARAM,"
line.long 0x558 "INST171_0,"
line.long 0x55C "INST171_1,"
hexmask.long.byte 0x55C 25.--31. 1. "NU2,"
rbitfld.long 0x55C 24. "NU1," "0,1"
bitfld.long 0x55C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x55C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x55C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x55C 0.--7. 1. "PARAM,"
line.long 0x560 "INST172_0,"
line.long 0x564 "INST172_1,"
hexmask.long.byte 0x564 25.--31. 1. "NU2,"
rbitfld.long 0x564 24. "NU1," "0,1"
bitfld.long 0x564 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x564 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x564 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x564 0.--7. 1. "PARAM,"
line.long 0x568 "INST173_0,"
line.long 0x56C "INST173_1,"
hexmask.long.byte 0x56C 25.--31. 1. "NU2,"
rbitfld.long 0x56C 24. "NU1," "0,1"
bitfld.long 0x56C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x56C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x56C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x56C 0.--7. 1. "PARAM,"
line.long 0x570 "INST174_0,"
line.long 0x574 "INST174_1,"
hexmask.long.byte 0x574 25.--31. 1. "NU2,"
rbitfld.long 0x574 24. "NU1," "0,1"
bitfld.long 0x574 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x574 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x574 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x574 0.--7. 1. "PARAM,"
line.long 0x578 "INST175_0,"
line.long 0x57C "INST175_1,"
hexmask.long.byte 0x57C 25.--31. 1. "NU2,"
rbitfld.long 0x57C 24. "NU1," "0,1"
bitfld.long 0x57C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x57C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x57C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x57C 0.--7. 1. "PARAM,"
line.long 0x580 "INST176_0,"
line.long 0x584 "INST176_1,"
hexmask.long.byte 0x584 25.--31. 1. "NU2,"
rbitfld.long 0x584 24. "NU1," "0,1"
bitfld.long 0x584 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x584 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x584 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x584 0.--7. 1. "PARAM,"
line.long 0x588 "INST177_0,"
line.long 0x58C "INST177_1,"
hexmask.long.byte 0x58C 25.--31. 1. "NU2,"
rbitfld.long 0x58C 24. "NU1," "0,1"
bitfld.long 0x58C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x58C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x58C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x58C 0.--7. 1. "PARAM,"
line.long 0x590 "INST178_0,"
line.long 0x594 "INST178_1,"
hexmask.long.byte 0x594 25.--31. 1. "NU2,"
rbitfld.long 0x594 24. "NU1," "0,1"
bitfld.long 0x594 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x594 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x594 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x594 0.--7. 1. "PARAM,"
line.long 0x598 "INST179_0,"
line.long 0x59C "INST179_1,"
hexmask.long.byte 0x59C 25.--31. 1. "NU2,"
rbitfld.long 0x59C 24. "NU1," "0,1"
bitfld.long 0x59C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x59C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x59C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x59C 0.--7. 1. "PARAM,"
line.long 0x5A0 "INST180_0,"
line.long 0x5A4 "INST180_1,"
hexmask.long.byte 0x5A4 25.--31. 1. "NU2,"
rbitfld.long 0x5A4 24. "NU1," "0,1"
bitfld.long 0x5A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5A4 0.--7. 1. "PARAM,"
line.long 0x5A8 "INST181_0,"
line.long 0x5AC "INST181_1,"
hexmask.long.byte 0x5AC 25.--31. 1. "NU2,"
rbitfld.long 0x5AC 24. "NU1," "0,1"
bitfld.long 0x5AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5AC 0.--7. 1. "PARAM,"
line.long 0x5B0 "INST182_0,"
line.long 0x5B4 "INST182_1,"
hexmask.long.byte 0x5B4 25.--31. 1. "NU2,"
rbitfld.long 0x5B4 24. "NU1," "0,1"
bitfld.long 0x5B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5B4 0.--7. 1. "PARAM,"
line.long 0x5B8 "INST183_0,"
line.long 0x5BC "INST183_1,"
hexmask.long.byte 0x5BC 25.--31. 1. "NU2,"
rbitfld.long 0x5BC 24. "NU1," "0,1"
bitfld.long 0x5BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5BC 0.--7. 1. "PARAM,"
line.long 0x5C0 "INST184_0,"
line.long 0x5C4 "INST184_1,"
hexmask.long.byte 0x5C4 25.--31. 1. "NU2,"
rbitfld.long 0x5C4 24. "NU1," "0,1"
bitfld.long 0x5C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5C4 0.--7. 1. "PARAM,"
line.long 0x5C8 "INST185_0,"
line.long 0x5CC "INST185_1,"
hexmask.long.byte 0x5CC 25.--31. 1. "NU2,"
rbitfld.long 0x5CC 24. "NU1," "0,1"
bitfld.long 0x5CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5CC 0.--7. 1. "PARAM,"
line.long 0x5D0 "INST186_0,"
line.long 0x5D4 "INST186_1,"
hexmask.long.byte 0x5D4 25.--31. 1. "NU2,"
rbitfld.long 0x5D4 24. "NU1," "0,1"
bitfld.long 0x5D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5D4 0.--7. 1. "PARAM,"
line.long 0x5D8 "INST187_0,"
line.long 0x5DC "INST187_1,"
hexmask.long.byte 0x5DC 25.--31. 1. "NU2,"
rbitfld.long 0x5DC 24. "NU1," "0,1"
bitfld.long 0x5DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5DC 0.--7. 1. "PARAM,"
line.long 0x5E0 "INST188_0,"
line.long 0x5E4 "INST188_1,"
hexmask.long.byte 0x5E4 25.--31. 1. "NU2,"
rbitfld.long 0x5E4 24. "NU1," "0,1"
bitfld.long 0x5E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5E4 0.--7. 1. "PARAM,"
line.long 0x5E8 "INST189_0,"
line.long 0x5EC "INST189_1,"
hexmask.long.byte 0x5EC 25.--31. 1. "NU2,"
rbitfld.long 0x5EC 24. "NU1," "0,1"
bitfld.long 0x5EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5EC 0.--7. 1. "PARAM,"
line.long 0x5F0 "INST190_0,"
line.long 0x5F4 "INST190_1,"
hexmask.long.byte 0x5F4 25.--31. 1. "NU2,"
rbitfld.long 0x5F4 24. "NU1," "0,1"
bitfld.long 0x5F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5F4 0.--7. 1. "PARAM,"
line.long 0x5F8 "INST191_0,"
line.long 0x5FC "INST191_1,"
hexmask.long.byte 0x5FC 25.--31. 1. "NU2,"
rbitfld.long 0x5FC 24. "NU1," "0,1"
bitfld.long 0x5FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5FC 0.--7. 1. "PARAM,"
line.long 0x600 "INST192_0,"
line.long 0x604 "INST192_1,"
hexmask.long.byte 0x604 25.--31. 1. "NU2,"
rbitfld.long 0x604 24. "NU1," "0,1"
bitfld.long 0x604 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x604 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x604 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x604 0.--7. 1. "PARAM,"
line.long 0x608 "INST193_0,"
line.long 0x60C "INST193_1,"
hexmask.long.byte 0x60C 25.--31. 1. "NU2,"
rbitfld.long 0x60C 24. "NU1," "0,1"
bitfld.long 0x60C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x60C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x60C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x60C 0.--7. 1. "PARAM,"
line.long 0x610 "INST194_0,"
line.long 0x614 "INST194_1,"
hexmask.long.byte 0x614 25.--31. 1. "NU2,"
rbitfld.long 0x614 24. "NU1," "0,1"
bitfld.long 0x614 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x614 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x614 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x614 0.--7. 1. "PARAM,"
line.long 0x618 "INST195_0,"
line.long 0x61C "INST195_1,"
hexmask.long.byte 0x61C 25.--31. 1. "NU2,"
rbitfld.long 0x61C 24. "NU1," "0,1"
bitfld.long 0x61C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x61C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x61C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x61C 0.--7. 1. "PARAM,"
line.long 0x620 "INST196_0,"
line.long 0x624 "INST196_1,"
hexmask.long.byte 0x624 25.--31. 1. "NU2,"
rbitfld.long 0x624 24. "NU1," "0,1"
bitfld.long 0x624 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x624 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x624 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x624 0.--7. 1. "PARAM,"
line.long 0x628 "INST197_0,"
line.long 0x62C "INST197_1,"
hexmask.long.byte 0x62C 25.--31. 1. "NU2,"
rbitfld.long 0x62C 24. "NU1," "0,1"
bitfld.long 0x62C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x62C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x62C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x62C 0.--7. 1. "PARAM,"
line.long 0x630 "INST198_0,"
line.long 0x634 "INST198_1,"
hexmask.long.byte 0x634 25.--31. 1. "NU2,"
rbitfld.long 0x634 24. "NU1," "0,1"
bitfld.long 0x634 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x634 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x634 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x634 0.--7. 1. "PARAM,"
line.long 0x638 "INST199_0,"
line.long 0x63C "INST199_1,"
hexmask.long.byte 0x63C 25.--31. 1. "NU2,"
rbitfld.long 0x63C 24. "NU1," "0,1"
bitfld.long 0x63C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x63C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x63C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x63C 0.--7. 1. "PARAM,"
line.long 0x640 "INST200_0,"
line.long 0x644 "INST200_1,"
hexmask.long.byte 0x644 25.--31. 1. "NU2,"
rbitfld.long 0x644 24. "NU1," "0,1"
bitfld.long 0x644 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x644 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x644 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x644 0.--7. 1. "PARAM,"
line.long 0x648 "INST201_0,"
line.long 0x64C "INST201_1,"
hexmask.long.byte 0x64C 25.--31. 1. "NU2,"
rbitfld.long 0x64C 24. "NU1," "0,1"
bitfld.long 0x64C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x64C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x64C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x64C 0.--7. 1. "PARAM,"
line.long 0x650 "INST202_0,"
line.long 0x654 "INST202_1,"
hexmask.long.byte 0x654 25.--31. 1. "NU2,"
rbitfld.long 0x654 24. "NU1," "0,1"
bitfld.long 0x654 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x654 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x654 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x654 0.--7. 1. "PARAM,"
line.long 0x658 "INST203_0,"
line.long 0x65C "INST203_1,"
hexmask.long.byte 0x65C 25.--31. 1. "NU2,"
rbitfld.long 0x65C 24. "NU1," "0,1"
bitfld.long 0x65C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x65C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x65C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x65C 0.--7. 1. "PARAM,"
line.long 0x660 "INST204_0,"
line.long 0x664 "INST204_1,"
hexmask.long.byte 0x664 25.--31. 1. "NU2,"
rbitfld.long 0x664 24. "NU1," "0,1"
bitfld.long 0x664 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x664 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x664 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x664 0.--7. 1. "PARAM,"
line.long 0x668 "INST205_0,"
line.long 0x66C "INST205_1,"
hexmask.long.byte 0x66C 25.--31. 1. "NU2,"
rbitfld.long 0x66C 24. "NU1," "0,1"
bitfld.long 0x66C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x66C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x66C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x66C 0.--7. 1. "PARAM,"
line.long 0x670 "INST206_0,"
line.long 0x674 "INST206_1,"
hexmask.long.byte 0x674 25.--31. 1. "NU2,"
rbitfld.long 0x674 24. "NU1," "0,1"
bitfld.long 0x674 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x674 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x674 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x674 0.--7. 1. "PARAM,"
line.long 0x678 "INST207_0,"
line.long 0x67C "INST207_1,"
hexmask.long.byte 0x67C 25.--31. 1. "NU2,"
rbitfld.long 0x67C 24. "NU1," "0,1"
bitfld.long 0x67C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x67C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x67C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x67C 0.--7. 1. "PARAM,"
line.long 0x680 "INST208_0,"
line.long 0x684 "INST208_1,"
hexmask.long.byte 0x684 25.--31. 1. "NU2,"
rbitfld.long 0x684 24. "NU1," "0,1"
bitfld.long 0x684 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x684 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x684 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x684 0.--7. 1. "PARAM,"
line.long 0x688 "INST209_0,"
line.long 0x68C "INST209_1,"
hexmask.long.byte 0x68C 25.--31. 1. "NU2,"
rbitfld.long 0x68C 24. "NU1," "0,1"
bitfld.long 0x68C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x68C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x68C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x68C 0.--7. 1. "PARAM,"
line.long 0x690 "INST210_0,"
line.long 0x694 "INST210_1,"
hexmask.long.byte 0x694 25.--31. 1. "NU2,"
rbitfld.long 0x694 24. "NU1," "0,1"
bitfld.long 0x694 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x694 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x694 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x694 0.--7. 1. "PARAM,"
line.long 0x698 "INST211_0,"
line.long 0x69C "INST211_1,"
hexmask.long.byte 0x69C 25.--31. 1. "NU2,"
rbitfld.long 0x69C 24. "NU1," "0,1"
bitfld.long 0x69C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x69C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x69C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x69C 0.--7. 1. "PARAM,"
line.long 0x6A0 "INST212_0,"
line.long 0x6A4 "INST212_1,"
hexmask.long.byte 0x6A4 25.--31. 1. "NU2,"
rbitfld.long 0x6A4 24. "NU1," "0,1"
bitfld.long 0x6A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6A4 0.--7. 1. "PARAM,"
line.long 0x6A8 "INST213_0,"
line.long 0x6AC "INST213_1,"
hexmask.long.byte 0x6AC 25.--31. 1. "NU2,"
rbitfld.long 0x6AC 24. "NU1," "0,1"
bitfld.long 0x6AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6AC 0.--7. 1. "PARAM,"
line.long 0x6B0 "INST214_0,"
line.long 0x6B4 "INST214_1,"
hexmask.long.byte 0x6B4 25.--31. 1. "NU2,"
rbitfld.long 0x6B4 24. "NU1," "0,1"
bitfld.long 0x6B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6B4 0.--7. 1. "PARAM,"
line.long 0x6B8 "INST215_0,"
line.long 0x6BC "INST215_1,"
hexmask.long.byte 0x6BC 25.--31. 1. "NU2,"
rbitfld.long 0x6BC 24. "NU1," "0,1"
bitfld.long 0x6BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6BC 0.--7. 1. "PARAM,"
line.long 0x6C0 "INST216_0,"
line.long 0x6C4 "INST216_1,"
hexmask.long.byte 0x6C4 25.--31. 1. "NU2,"
rbitfld.long 0x6C4 24. "NU1," "0,1"
bitfld.long 0x6C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6C4 0.--7. 1. "PARAM,"
line.long 0x6C8 "INST217_0,"
line.long 0x6CC "INST217_1,"
hexmask.long.byte 0x6CC 25.--31. 1. "NU2,"
rbitfld.long 0x6CC 24. "NU1," "0,1"
bitfld.long 0x6CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6CC 0.--7. 1. "PARAM,"
line.long 0x6D0 "INST218_0,"
line.long 0x6D4 "INST218_1,"
hexmask.long.byte 0x6D4 25.--31. 1. "NU2,"
rbitfld.long 0x6D4 24. "NU1," "0,1"
bitfld.long 0x6D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6D4 0.--7. 1. "PARAM,"
line.long 0x6D8 "INST219_0,"
line.long 0x6DC "INST219_1,"
hexmask.long.byte 0x6DC 25.--31. 1. "NU2,"
rbitfld.long 0x6DC 24. "NU1," "0,1"
bitfld.long 0x6DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6DC 0.--7. 1. "PARAM,"
line.long 0x6E0 "INST220_0,"
line.long 0x6E4 "INST220_1,"
hexmask.long.byte 0x6E4 25.--31. 1. "NU2,"
rbitfld.long 0x6E4 24. "NU1," "0,1"
bitfld.long 0x6E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6E4 0.--7. 1. "PARAM,"
line.long 0x6E8 "INST221_0,"
line.long 0x6EC "INST221_1,"
hexmask.long.byte 0x6EC 25.--31. 1. "NU2,"
rbitfld.long 0x6EC 24. "NU1," "0,1"
bitfld.long 0x6EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6EC 0.--7. 1. "PARAM,"
line.long 0x6F0 "INST222_0,"
line.long 0x6F4 "INST222_1,"
hexmask.long.byte 0x6F4 25.--31. 1. "NU2,"
rbitfld.long 0x6F4 24. "NU1," "0,1"
bitfld.long 0x6F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6F4 0.--7. 1. "PARAM,"
line.long 0x6F8 "INST223_0,"
line.long 0x6FC "INST223_1,"
hexmask.long.byte 0x6FC 25.--31. 1. "NU2,"
rbitfld.long 0x6FC 24. "NU1," "0,1"
bitfld.long 0x6FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6FC 0.--7. 1. "PARAM,"
line.long 0x700 "INST224_0,"
line.long 0x704 "INST224_1,"
hexmask.long.byte 0x704 25.--31. 1. "NU2,"
rbitfld.long 0x704 24. "NU1," "0,1"
bitfld.long 0x704 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x704 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x704 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x704 0.--7. 1. "PARAM,"
line.long 0x708 "INST225_0,"
line.long 0x70C "INST225_1,"
hexmask.long.byte 0x70C 25.--31. 1. "NU2,"
rbitfld.long 0x70C 24. "NU1," "0,1"
bitfld.long 0x70C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x70C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x70C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x70C 0.--7. 1. "PARAM,"
line.long 0x710 "INST226_0,"
line.long 0x714 "INST226_1,"
hexmask.long.byte 0x714 25.--31. 1. "NU2,"
rbitfld.long 0x714 24. "NU1," "0,1"
bitfld.long 0x714 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x714 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x714 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x714 0.--7. 1. "PARAM,"
line.long 0x718 "INST227_0,"
line.long 0x71C "INST227_1,"
hexmask.long.byte 0x71C 25.--31. 1. "NU2,"
rbitfld.long 0x71C 24. "NU1," "0,1"
bitfld.long 0x71C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x71C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x71C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x71C 0.--7. 1. "PARAM,"
line.long 0x720 "INST228_0,"
line.long 0x724 "INST228_1,"
hexmask.long.byte 0x724 25.--31. 1. "NU2,"
rbitfld.long 0x724 24. "NU1," "0,1"
bitfld.long 0x724 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x724 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x724 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x724 0.--7. 1. "PARAM,"
line.long 0x728 "INST229_0,"
line.long 0x72C "INST229_1,"
hexmask.long.byte 0x72C 25.--31. 1. "NU2,"
rbitfld.long 0x72C 24. "NU1," "0,1"
bitfld.long 0x72C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x72C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x72C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x72C 0.--7. 1. "PARAM,"
line.long 0x730 "INST230_0,"
line.long 0x734 "INST230_1,"
hexmask.long.byte 0x734 25.--31. 1. "NU2,"
rbitfld.long 0x734 24. "NU1," "0,1"
bitfld.long 0x734 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x734 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x734 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x734 0.--7. 1. "PARAM,"
line.long 0x738 "INST231_0,"
line.long 0x73C "INST231_1,"
hexmask.long.byte 0x73C 25.--31. 1. "NU2,"
rbitfld.long 0x73C 24. "NU1," "0,1"
bitfld.long 0x73C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x73C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x73C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x73C 0.--7. 1. "PARAM,"
line.long 0x740 "INST232_0,"
line.long 0x744 "INST232_1,"
hexmask.long.byte 0x744 25.--31. 1. "NU2,"
rbitfld.long 0x744 24. "NU1," "0,1"
bitfld.long 0x744 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x744 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x744 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x744 0.--7. 1. "PARAM,"
line.long 0x748 "INST233_0,"
line.long 0x74C "INST233_1,"
hexmask.long.byte 0x74C 25.--31. 1. "NU2,"
rbitfld.long 0x74C 24. "NU1," "0,1"
bitfld.long 0x74C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x74C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x74C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x74C 0.--7. 1. "PARAM,"
line.long 0x750 "INST234_0,"
line.long 0x754 "INST234_1,"
hexmask.long.byte 0x754 25.--31. 1. "NU2,"
rbitfld.long 0x754 24. "NU1," "0,1"
bitfld.long 0x754 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x754 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x754 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x754 0.--7. 1. "PARAM,"
line.long 0x758 "INST235_0,"
line.long 0x75C "INST235_1,"
hexmask.long.byte 0x75C 25.--31. 1. "NU2,"
rbitfld.long 0x75C 24. "NU1," "0,1"
bitfld.long 0x75C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x75C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x75C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x75C 0.--7. 1. "PARAM,"
line.long 0x760 "INST236_0,"
line.long 0x764 "INST236_1,"
hexmask.long.byte 0x764 25.--31. 1. "NU2,"
rbitfld.long 0x764 24. "NU1," "0,1"
bitfld.long 0x764 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x764 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x764 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x764 0.--7. 1. "PARAM,"
line.long 0x768 "INST237_0,"
line.long 0x76C "INST237_1,"
hexmask.long.byte 0x76C 25.--31. 1. "NU2,"
rbitfld.long 0x76C 24. "NU1," "0,1"
bitfld.long 0x76C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x76C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x76C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x76C 0.--7. 1. "PARAM,"
line.long 0x770 "INST238_0,"
line.long 0x774 "INST238_1,"
hexmask.long.byte 0x774 25.--31. 1. "NU2,"
rbitfld.long 0x774 24. "NU1," "0,1"
bitfld.long 0x774 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x774 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x774 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x774 0.--7. 1. "PARAM,"
line.long 0x778 "INST239_0,"
line.long 0x77C "INST239_1,"
hexmask.long.byte 0x77C 25.--31. 1. "NU2,"
rbitfld.long 0x77C 24. "NU1," "0,1"
bitfld.long 0x77C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x77C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x77C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x77C 0.--7. 1. "PARAM,"
line.long 0x780 "INST240_0,"
line.long 0x784 "INST240_1,"
hexmask.long.byte 0x784 25.--31. 1. "NU2,"
rbitfld.long 0x784 24. "NU1," "0,1"
bitfld.long 0x784 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x784 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x784 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x784 0.--7. 1. "PARAM,"
line.long 0x788 "INST241_0,"
line.long 0x78C "INST241_1,"
hexmask.long.byte 0x78C 25.--31. 1. "NU2,"
rbitfld.long 0x78C 24. "NU1," "0,1"
bitfld.long 0x78C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x78C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x78C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x78C 0.--7. 1. "PARAM,"
line.long 0x790 "INST242_0,"
line.long 0x794 "INST242_1,"
hexmask.long.byte 0x794 25.--31. 1. "NU2,"
rbitfld.long 0x794 24. "NU1," "0,1"
bitfld.long 0x794 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x794 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x794 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x794 0.--7. 1. "PARAM,"
line.long 0x798 "INST243_0,"
line.long 0x79C "INST243_1,"
hexmask.long.byte 0x79C 25.--31. 1. "NU2,"
rbitfld.long 0x79C 24. "NU1," "0,1"
bitfld.long 0x79C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x79C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x79C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x79C 0.--7. 1. "PARAM,"
line.long 0x7A0 "INST244_0,"
line.long 0x7A4 "INST244_1,"
hexmask.long.byte 0x7A4 25.--31. 1. "NU2,"
rbitfld.long 0x7A4 24. "NU1," "0,1"
bitfld.long 0x7A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7A4 0.--7. 1. "PARAM,"
line.long 0x7A8 "INST245_0,"
line.long 0x7AC "INST245_1,"
hexmask.long.byte 0x7AC 25.--31. 1. "NU2,"
rbitfld.long 0x7AC 24. "NU1," "0,1"
bitfld.long 0x7AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7AC 0.--7. 1. "PARAM,"
line.long 0x7B0 "INST246_0,"
line.long 0x7B4 "INST246_1,"
hexmask.long.byte 0x7B4 25.--31. 1. "NU2,"
rbitfld.long 0x7B4 24. "NU1," "0,1"
bitfld.long 0x7B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7B4 0.--7. 1. "PARAM,"
line.long 0x7B8 "INST247_0,"
line.long 0x7BC "INST247_1,"
hexmask.long.byte 0x7BC 25.--31. 1. "NU2,"
rbitfld.long 0x7BC 24. "NU1," "0,1"
bitfld.long 0x7BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7BC 0.--7. 1. "PARAM,"
line.long 0x7C0 "INST248_0,"
line.long 0x7C4 "INST248_1,"
hexmask.long.byte 0x7C4 25.--31. 1. "NU2,"
rbitfld.long 0x7C4 24. "NU1," "0,1"
bitfld.long 0x7C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7C4 0.--7. 1. "PARAM,"
line.long 0x7C8 "INST249_0,"
line.long 0x7CC "INST249_1,"
hexmask.long.byte 0x7CC 25.--31. 1. "NU2,"
rbitfld.long 0x7CC 24. "NU1," "0,1"
bitfld.long 0x7CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7CC 0.--7. 1. "PARAM,"
line.long 0x7D0 "INST250_0,"
line.long 0x7D4 "INST250_1,"
hexmask.long.byte 0x7D4 25.--31. 1. "NU2,"
rbitfld.long 0x7D4 24. "NU1," "0,1"
bitfld.long 0x7D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7D4 0.--7. 1. "PARAM,"
line.long 0x7D8 "INST251_0,"
line.long 0x7DC "INST251_1,"
hexmask.long.byte 0x7DC 25.--31. 1. "NU2,"
rbitfld.long 0x7DC 24. "NU1," "0,1"
bitfld.long 0x7DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7DC 0.--7. 1. "PARAM,"
line.long 0x7E0 "INST252_0,"
line.long 0x7E4 "INST252_1,"
hexmask.long.byte 0x7E4 25.--31. 1. "NU2,"
rbitfld.long 0x7E4 24. "NU1," "0,1"
bitfld.long 0x7E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7E4 0.--7. 1. "PARAM,"
line.long 0x7E8 "INST253_0,"
line.long 0x7EC "INST253_1,"
hexmask.long.byte 0x7EC 25.--31. 1. "NU2,"
rbitfld.long 0x7EC 24. "NU1," "0,1"
bitfld.long 0x7EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7EC 0.--7. 1. "PARAM,"
line.long 0x7F0 "INST254_0,"
line.long 0x7F4 "INST254_1,"
hexmask.long.byte 0x7F4 25.--31. 1. "NU2,"
rbitfld.long 0x7F4 24. "NU1," "0,1"
bitfld.long 0x7F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7F4 0.--7. 1. "PARAM,"
line.long 0x7F8 "INST255_0,"
line.long 0x7FC "INST255_1,"
hexmask.long.byte 0x7FC 25.--31. 1. "NU2,"
rbitfld.long 0x7FC 24. "NU1," "0,1"
bitfld.long 0x7FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7FC 0.--7. 1. "PARAM,"
width 0x0B
tree.end
tree "MSS_GPADC_REG (MSS GPADC REG Module Registers)"
base ad:0x3F79800
group.long 0x00++0x4F
line.long 0x00 "REG0,gpadc modes and enable"
hexmask.long.word 0x00 17.--31. 1. "NU3,TI reserved"
bitfld.long 0x00 16. "GPADC_DEBUG_MODE_ENABLE," "0,1"
rbitfld.long 0x00 12.--15. "NU2,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9.--11. "GPADC2ADCBUF_PATH_EN,TI reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "GPADC_FSM_CLK_ENABLE,Enable the clock to gpadc fsm" "0,1"
rbitfld.long 0x00 2.--7. "NU1,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "DCBIST_MODE," "0,1,2,3"
line.long 0x04 "REG1,gpadc start trigger for Inter frame mode"
hexmask.long.byte 0x04 25.--31. 1. "NU4,TI reserved"
bitfld.long 0x04 24. "GPADC_START_BYP_VAL," "0,1"
hexmask.long.byte 0x04 17.--23. 1. "NU3,TI reserved"
bitfld.long 0x04 16. "GPADC_FSM_BYPASS," "0,1"
newline
hexmask.long.byte 0x04 9.--15. 1. "NU2,TI reserved"
bitfld.long 0x04 8. "GPADC_INIT,Resets the FSM and clears the data RAM" "0,1"
hexmask.long.byte 0x04 1.--7. 1. "NU1,TI reserved"
bitfld.long 0x04 0. "GPADC_TRIGGER,Generates a single cycle pulse to trigger the IFM mode" "0,1"
line.long 0x08 "REG2,gpadc config for IFM"
line.long 0x0C "REG3,gpadc param. skip samples and collect samples for IFM"
hexmask.long.word 0x0C 23.--31. 1. "NU,"
hexmask.long.byte 0x0C 16.--22. 1. "SKIP_SAMPLES_IFM,number of GPADC clocks to skip after trigger"
hexmask.long.byte 0x0C 8.--15. 1. "COLLECT_SAMPLES_IFM,number of GPADC readings to collect"
hexmask.long.byte 0x0C 0.--7. 1. "PARAM_VAL_IFM,Param value to be passed to analog in IFM mode(after one hot encoding)"
line.long 0x10 "REG4,Base address for Chirp profile 0 in instruction packet RAM"
hexmask.long.byte 0x10 24.--31. 1. "PKT_RAM_BASE_ADDR_CP3,TI reserved"
hexmask.long.byte 0x10 16.--23. 1. "PKT_RAM_BASE_ADDR_CP2,TI reserved"
hexmask.long.byte 0x10 8.--15. 1. "PKT_RAM_BASE_ADDR_CP1,(End-Address + 1) of instruction-ram in CTM mode"
hexmask.long.byte 0x10 0.--7. 1. "PKT_RAM_BASE_ADDR_CP0,Start Address of instruction-ram in CTM mode"
line.long 0x14 "REG5,Base address for Chirp profile 1 in instruction packet RAM"
hexmask.long.byte 0x14 24.--31. 1. "PKT_RAM_BASE_ADDR_CP7,TI reserved"
hexmask.long.byte 0x14 16.--23. 1. "PKT_RAM_BASE_ADDR_CP6,TI reserved"
hexmask.long.byte 0x14 8.--15. 1. "PKT_RAM_BASE_ADDR_CP5,TI reserved"
hexmask.long.byte 0x14 0.--7. 1. "PKT_RAM_BASE_ADDR_CP4,TI reserved"
line.long 0x18 "REG6,Base address for Chirp profile 2 in instruction packet RAM"
hexmask.long.byte 0x18 24.--31. 1. "PKT_RAM_BASE_ADDR_CP11,TI reserved"
hexmask.long.byte 0x18 16.--23. 1. "PKT_RAM_BASE_ADDR_CP10,TI reserved"
hexmask.long.byte 0x18 8.--15. 1. "PKT_RAM_BASE_ADDR_CP9,TI reserved"
hexmask.long.byte 0x18 0.--7. 1. "PKT_RAM_BASE_ADDR_CP8,TI reserved"
line.long 0x1C "REG7,Base address for Chirp profile 3 in instruction packet RAM"
hexmask.long.byte 0x1C 24.--31. 1. "PKT_RAM_BASE_ADDR_CP15,TI reserved"
hexmask.long.byte 0x1C 16.--23. 1. "PKT_RAM_BASE_ADDR_CP14,TI reserved"
hexmask.long.byte 0x1C 8.--15. 1. "PKT_RAM_BASE_ADDR_CP13,TI reserved"
hexmask.long.byte 0x1C 0.--7. 1. "PKT_RAM_BASE_ADDR_CP12,TI reserved"
line.long 0x20 "REG8,"
hexmask.long.tbyte 0x20 9.--31. 1. "NU,"
bitfld.long 0x20 8. "GPADC_CLK_ENABLE,TI reserved" "0,1"
hexmask.long.byte 0x20 0.--7. 1. "GPADC_CLK_DIV,TI reserved"
line.long 0x24 "REG9,"
line.long 0x28 "REG10,"
line.long 0x2C "REG11,"
line.long 0x30 "REG12,"
hexmask.long.byte 0x30 24.--31. 1. "DRAM_REPAIRED_BIT,TI reserved"
hexmask.long.byte 0x30 16.--23. 1. "DRAM_ECC_ERR_ADDR,TI reserved"
hexmask.long.byte 0x30 9.--15. 1. "NU2,TI reserved"
bitfld.long 0x30 8. "DRAM_ECC_ERR_CLR,TI reserved" "0,1"
newline
hexmask.long.byte 0x30 1.--7. 1. "NU1,TI reserved"
bitfld.long 0x30 0. "DRAM_ECC_ENABLE," "0,1"
line.long 0x34 "REG13,"
line.long 0x38 "REG14,Sum of GP ADC readings"
hexmask.long.word 0x38 20.--31. 1. "NU,TI reserved"
hexmask.long.tbyte 0x38 0.--19. 1. "SUM_IFM,Sum of GP ADC readings"
line.long 0x3C "REG15,Min and Max of GP ADC readings"
bitfld.long 0x3C 26.--31. "NU2,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x3C 16.--25. 1. "MAX_GPADC,Max of GPADC readings"
bitfld.long 0x3C 10.--15. "NU1,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x3C 0.--9. 1. "MIN_GPADC,Min of GPADC readings"
line.long 0x40 "REG16,"
hexmask.long 0x40 1.--31. 1. "NU,TI reserved"
bitfld.long 0x40 0. "GPADC_MEM_INIT_DONE_STAT,Status for Data Mem init done.Used for FW polling .Will read '0' when init process is under progress" "0,1"
line.long 0x44 "REG17,"
hexmask.long 0x44 1.--31. 1. "NU,TI reserved"
bitfld.long 0x44 0. "GPADC_IFM_DONE_STATUS,Test completion status in IFM mode.Used for FW polling" "0,1"
line.long 0x48 "REG18,"
hexmask.long 0x48 1.--31. 1. "NU,TI reserved"
bitfld.long 0x48 0. "GPADC_IFM_DONE_CLR,Clear 'ifm_done_status'" "0,1"
line.long 0x4C "REG19,"
hexmask.long.word 0x4C 16.--31. 1. "NU,TI reserved"
hexmask.long.word 0x4C 0.--15. 1. "GPADC_SAMPLES_FRAME,Total number of GPADC samples collected in a frame"
group.long 0x58++0x03
line.long 0x00 "REG22,"
repeat 2. (list 20. 21. )(list 0x00 0x04 )
rgroup.long ($2+0x50)++0x03
line.long 0x00 "REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_I2C (MSS I2C Module Registers)"
base ad:0x2F7B000
group.long 0x00++0x3F
line.long 0x00 "ICOAR,I2C Own Address register"
hexmask.long.tbyte 0x00 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x00 0.--9. 1. "A9_A0,Own address"
line.long 0x04 "ICIMR,I2C Interrupt Mask/Status register"
hexmask.long 0x04 7.--31. 1. "NU,Reserved"
bitfld.long 0x04 6. "AAS,Address As Slave interrupt mask bit" "0,1"
newline
bitfld.long 0x04 5. "SCD,Stop Condition Detection mask bit" "0,1"
bitfld.long 0x04 4. "ICXRDY,Transmit Data Ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 3. "ICRRDY,Receive Data Ready interrupt mask bit" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 1. "NACK,No Acknowledgement interrupt mask bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration Lost interrupt mask bit" "0,1"
line.long 0x08 "ICSTR,I2C Interrupt Status register"
hexmask.long.tbyte 0x08 15.--31. 1. "NU2,Reserved"
bitfld.long 0x08 14. "SDIR,Slave Direction" "0,1"
newline
bitfld.long 0x08 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'" "0,1"
bitfld.long 0x08 12. "BB,Bus Busy" "0,1"
newline
bitfld.long 0x08 11. "RSFULL,Receive shift full" "0,1"
bitfld.long 0x08 10. "XSMT,Transmit shift empty not" "0,1"
newline
bitfld.long 0x08 9. "AAS,Address As Slave" "0,1"
bitfld.long 0x08 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call)" "0,1"
newline
bitfld.long 0x08 6.--7. "NU1,Reserved" "0,1,2,3"
bitfld.long 0x08 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition" "0,1"
newline
bitfld.long 0x08 4. "ICXRDY,Transmit Data Ready interrupt flag bit" "0,1"
bitfld.long 0x08 3. "ICRRDY,Receive Data Ready interrupt flag bit" "0,1"
newline
bitfld.long 0x08 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
bitfld.long 0x08 1. "NACK,No-Acknowledgement interrupt flag bit" "0,1"
newline
bitfld.long 0x08 0. "AL,Arbitration-Lost interrupt flag bit" "0,1"
line.long 0x0C "ICCLKL,I2C Clock Divider Low register"
hexmask.long.word 0x0C 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "ICCL15_ICCL0,Low time I2C SCL Clock Division Factor"
line.long 0x10 "ICCLKH,I2C Clock Divider High register"
hexmask.long.word 0x10 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I2C SCL Clock Division Factor"
line.long 0x14 "ICCNT,I2C Data Count register"
hexmask.long.word 0x14 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count"
line.long 0x18 "ICDRR,I2C Data Receive register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data"
line.long 0x1C "ICSAR,I2C Slave Address register"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address"
line.long 0x20 "ICDXR,I2C Data Transmit register"
hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data"
line.long 0x24 "ICMDR,I2C Mode register"
hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved"
bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode" "0,1"
newline
bitfld.long 0x24 14. "FREE,Free Running" "0,1"
bitfld.long 0x24 13. "STT,Start Condition (Master only mode)" "0,1"
newline
bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509)" "0,1"
bitfld.long 0x24 11. "STP,Stop Condition (Master mode only)" "0,1"
newline
bitfld.long 0x24 10. "MST,Master" "0,1"
bitfld.long 0x24 9. "TRX,Transmitter" "0,1"
newline
bitfld.long 0x24 8. "XA,Expanded Address" "0,1"
bitfld.long 0x24 7. "RM,Repeat Mode" "0,1"
newline
bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only)" "0,1"
bitfld.long 0x24 5. "IRS,I2C Reset Not" "0,1"
newline
bitfld.long 0x24 4. "STB,Start Byte (Master only mode)" "0,1"
bitfld.long 0x24 3. "FDF,Free Data Format" "0,1"
newline
bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted" "0,1,2,3,4,5,6,7"
line.long 0x28 "ICIVR,I2C Interrupt Vector register"
hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved"
bitfld.long 0x28 8.--11. "TESTMD,Reserved for internal testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 3.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--2. "INTCODE,Interrupt code" "0,1,2,3,4,5,6,7"
line.long 0x2C "ICEMDR,I2C Extended Mode register"
hexmask.long 0x2C 2.--31. 1. "NU,Reserved"
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave" "0,1"
newline
bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode" "0,1"
line.long 0x30 "ICPSC,I2C Prescaler register"
hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module"
line.long 0x34 "ICPID1,I2C Peripheral ID register 1"
hexmask.long.word 0x34 16.--31. 1. "NU,Reserved"
hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral"
newline
hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C"
line.long 0x38 "ICPID2,I2C Peripheral ID register 2"
hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral"
line.long 0x3C "ICDMAC,I2C DMA Control Register"
hexmask.long 0x3C 2.--31. 1. "NU,Reserved"
bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable" "0,1"
newline
bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable" "0,1"
group.long 0x48++0x1B
line.long 0x00 "ICPFUNC,I2C Pin Function register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved"
bitfld.long 0x00 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins" "Pins function as SCL and SDA,Pins functions as GPIO"
line.long 0x04 "ICPDIR,I2C Pin Direction register"
hexmask.long 0x04 2.--31. 1. "NU,Reserved"
bitfld.long 0x04 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO" "SDA pin functions as input,SDA pin functions as output"
newline
bitfld.long 0x04 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO" "SCL pin functions as input,SCL pin functions as output"
line.long 0x08 "ICPDIN,I2C Pin Data In register"
hexmask.long 0x08 2.--31. 1. "NU,Reserved"
bitfld.long 0x08 1. "PDIN1,Indicates the logic level present on the SDA pin" "Logic low present at SDA pin regardless of PFUNC..,Logic high present at SDA pin regardless of.."
newline
bitfld.long 0x08 0. "PDIN0,Indicates the logic level present on the SCL pin" "Logic low present at SCL pin regardless of PFUNC..,Logic high present at SCL pin regardless of.."
line.long 0x0C "ICPDOUT,I2C Pin Data Out register"
hexmask.long 0x0C 2.--31. 1. "NU,Reserved"
bitfld.long 0x0C 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output" "SDA pin driven low,SDA pin driven high"
newline
bitfld.long 0x0C 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output" "SCL pin driven low,SCL pin driven high"
line.long 0x10 "ICPDSET,I2C Pin Data Set register"
hexmask.long 0x10 2.--31. 1. "NU,Reserved"
bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin" "no effect,PDOUT[1] bit is set to.."
newline
bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin" "no effect,PDOUT[0] bit is set to.."
line.long 0x14 "ICPDCLR,I2C Pin Data Clear register"
hexmask.long 0x14 2.--31. 1. "NU,Reserved"
bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin" "no effect,PDOUT[1] bit is cleared.."
newline
bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin" "no effect,PDOUT[0] bit is cleared.."
line.long 0x18 "ICPDRV,I2C Pin Driver Mode Register"
hexmask.long 0x18 2.--31. 1. "NU,Reserved"
bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin" "I2C mode,GPIO mode"
newline
bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin" "I2C mode,GPIO mode"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "I2C_RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_IOMUX (MSS IOMUX Module Registers)"
base ad:0x20C0000
group.long 0x00++0x1DF
line.long 0x00 "PADAA_cfg_reg,"
hexmask.long.tbyte 0x00 11.--31. 1. "NU,Reserved"
bitfld.long 0x00 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x00 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x00 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x00 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x00 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x00 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x00 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x00 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PADAB_cfg_reg,"
hexmask.long.tbyte 0x04 11.--31. 1. "NU,Reserved"
bitfld.long 0x04 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x04 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x04 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x04 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x04 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x04 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x04 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x04 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "PADAC_cfg_reg,"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved"
bitfld.long 0x08 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x08 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x08 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x08 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x08 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x08 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x08 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x08 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "PADAD_cfg_reg,"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved"
bitfld.long 0x0C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x0C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x0C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x0C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x0C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x0C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x0C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x0C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "PADAE_cfg_reg,"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved"
bitfld.long 0x10 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x10 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x10 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x10 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x10 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x10 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x10 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x10 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "PADAF_cfg_reg,"
hexmask.long.tbyte 0x14 11.--31. 1. "NU,Reserved"
bitfld.long 0x14 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x14 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x14 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x14 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x14 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x14 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x14 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x14 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "PADAG_cfg_reg,"
hexmask.long.tbyte 0x18 11.--31. 1. "NU,Reserved"
bitfld.long 0x18 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x18 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x18 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x18 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x18 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x18 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x18 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x18 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "PADAH_cfg_reg,"
hexmask.long.tbyte 0x1C 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "PADAI_cfg_reg,"
hexmask.long.tbyte 0x20 11.--31. 1. "NU,Reserved"
bitfld.long 0x20 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x20 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x20 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x20 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x20 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x20 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x20 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x20 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "PADAJ_cfg_reg,"
hexmask.long.tbyte 0x24 11.--31. 1. "NU,Reserved"
bitfld.long 0x24 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x24 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x24 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x24 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x24 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x24 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x24 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x24 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "PADAK_cfg_reg,"
hexmask.long.tbyte 0x28 11.--31. 1. "NU,Reserved"
bitfld.long 0x28 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x28 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x28 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x28 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x28 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x28 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x28 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x28 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "PADAL_cfg_reg,"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU,Reserved"
bitfld.long 0x2C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x2C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x2C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x2C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x2C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x2C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x2C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x2C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "PADAM_cfg_reg,"
hexmask.long.tbyte 0x30 11.--31. 1. "NU,Reserved"
bitfld.long 0x30 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x30 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x30 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x30 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x30 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x30 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x30 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x30 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "PADAN_cfg_reg,"
hexmask.long.tbyte 0x34 11.--31. 1. "NU,Reserved"
bitfld.long 0x34 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x34 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x34 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x34 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x34 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x34 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x34 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x34 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "PADAO_cfg_reg,"
hexmask.long.tbyte 0x38 11.--31. 1. "NU,Reserved"
bitfld.long 0x38 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x38 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x38 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x38 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x38 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x38 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x38 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x38 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "PADAP_cfg_reg,"
hexmask.long.tbyte 0x3C 11.--31. 1. "NU,Reserved"
bitfld.long 0x3C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x3C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x3C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x3C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x3C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x3C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x3C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x3C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "PADAQ_cfg_reg,"
hexmask.long.tbyte 0x40 11.--31. 1. "NU,Reserved"
bitfld.long 0x40 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x40 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x40 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x40 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x40 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x40 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x40 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x40 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "PADAR_cfg_reg,"
hexmask.long.tbyte 0x44 11.--31. 1. "NU,Reserved"
bitfld.long 0x44 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x44 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x44 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x44 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x44 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x44 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x44 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x44 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "PADAS_cfg_reg,"
hexmask.long.tbyte 0x48 11.--31. 1. "NU,Reserved"
bitfld.long 0x48 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x48 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x48 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x48 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x48 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x48 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x48 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x48 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "PADAT_cfg_reg,"
hexmask.long.tbyte 0x4C 11.--31. 1. "NU,Reserved"
bitfld.long 0x4C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x4C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x4C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x4C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x4C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x4C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x4C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x4C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "PADAU_cfg_reg,"
hexmask.long.tbyte 0x50 11.--31. 1. "NU,Reserved"
bitfld.long 0x50 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x50 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x50 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x50 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x50 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x50 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x50 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x50 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "PADAV_cfg_reg,"
hexmask.long.tbyte 0x54 11.--31. 1. "NU,Reserved"
bitfld.long 0x54 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x54 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x54 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x54 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x54 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x54 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x54 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x54 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "PADAW_cfg_reg,"
hexmask.long.tbyte 0x58 11.--31. 1. "NU,Reserved"
bitfld.long 0x58 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x58 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x58 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x58 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x58 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x58 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x58 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x58 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "PADAX_cfg_reg,"
hexmask.long.tbyte 0x5C 11.--31. 1. "NU,Reserved"
bitfld.long 0x5C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x5C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x5C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x5C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x5C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x5C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x5C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x5C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x60 "PADAY_cfg_reg,"
hexmask.long.tbyte 0x60 11.--31. 1. "NU,Reserved"
bitfld.long 0x60 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x60 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x60 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x60 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x60 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x60 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x60 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x60 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "PADAZ_cfg_reg,"
hexmask.long.tbyte 0x64 11.--31. 1. "NU,Reserved"
bitfld.long 0x64 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x64 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x64 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x64 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x64 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x64 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x64 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x64 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "PADBA_cfg_reg,"
hexmask.long.tbyte 0x68 11.--31. 1. "NU,Reserved"
bitfld.long 0x68 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x68 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x68 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x68 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x68 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x68 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x68 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x68 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "PADBB_cfg_reg,"
hexmask.long.tbyte 0x6C 11.--31. 1. "NU,Reserved"
bitfld.long 0x6C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x6C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x6C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x6C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x6C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x6C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x6C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x6C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "PADBC_cfg_reg,"
hexmask.long.tbyte 0x70 11.--31. 1. "NU,Reserved"
bitfld.long 0x70 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x70 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x70 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x70 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x70 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x70 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x70 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x70 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x74 "PADBD_cfg_reg,"
hexmask.long.tbyte 0x74 11.--31. 1. "NU,Reserved"
bitfld.long 0x74 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x74 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x74 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x74 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x74 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x74 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x74 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x74 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x78 "PADBE_cfg_reg,"
hexmask.long.tbyte 0x78 11.--31. 1. "NU,Reserved"
bitfld.long 0x78 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x78 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x78 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x78 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x78 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x78 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x78 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x78 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x7C "PADBF_cfg_reg,"
hexmask.long.tbyte 0x7C 11.--31. 1. "NU,Reserved"
bitfld.long 0x7C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x7C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x7C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x7C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x7C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x7C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x7C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x7C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x80 "PADBG_cfg_reg,"
hexmask.long.tbyte 0x80 11.--31. 1. "NU,Reserved"
bitfld.long 0x80 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x80 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x80 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x80 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x80 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x80 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x80 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x80 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "PADBH_cfg_reg,"
hexmask.long.tbyte 0x84 11.--31. 1. "NU,Reserved"
bitfld.long 0x84 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x84 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x84 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x84 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x84 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x84 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x84 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x84 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "PADBI_cfg_reg,"
hexmask.long.tbyte 0x88 11.--31. 1. "NU,Reserved"
bitfld.long 0x88 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x88 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x88 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x88 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x88 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x88 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x88 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x88 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "PADBJ_cfg_reg,"
hexmask.long.tbyte 0x8C 11.--31. 1. "NU,Reserved"
bitfld.long 0x8C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x8C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x8C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x8C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x8C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x8C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x8C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x8C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "PADBK_cfg_reg,"
hexmask.long.tbyte 0x90 11.--31. 1. "NU,Reserved"
bitfld.long 0x90 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x90 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x90 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x90 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x90 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x90 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x90 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x90 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x94 "PADBL_cfg_reg,"
hexmask.long.tbyte 0x94 11.--31. 1. "NU,Reserved"
bitfld.long 0x94 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x94 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x94 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x94 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x94 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x94 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x94 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x94 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x98 "PADBM_cfg_reg,"
hexmask.long.tbyte 0x98 11.--31. 1. "NU,Reserved"
bitfld.long 0x98 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x98 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x98 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x98 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x98 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x98 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x98 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x98 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "PADBN_cfg_reg,"
hexmask.long.tbyte 0x9C 11.--31. 1. "NU,Reserved"
bitfld.long 0x9C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x9C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x9C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x9C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x9C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x9C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x9C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x9C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA0 "PADBO_cfg_reg,"
hexmask.long.tbyte 0xA0 11.--31. 1. "NU,Reserved"
bitfld.long 0xA0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xA0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xA0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xA0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xA0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xA0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xA0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xA0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "PADBP_cfg_reg,"
hexmask.long.tbyte 0xA4 11.--31. 1. "NU,Reserved"
bitfld.long 0xA4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xA4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xA4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xA4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xA4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xA4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xA4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xA4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA8 "PADBQ_cfg_reg,"
hexmask.long.tbyte 0xA8 11.--31. 1. "NU,Reserved"
bitfld.long 0xA8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xA8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xA8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xA8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xA8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xA8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xA8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xA8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xAC "PADBR_cfg_reg,"
hexmask.long.tbyte 0xAC 11.--31. 1. "NU,Reserved"
bitfld.long 0xAC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xAC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xAC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xAC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xAC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xAC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xAC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xAC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB0 "PADBS_cfg_reg,"
hexmask.long.tbyte 0xB0 11.--31. 1. "NU,Reserved"
bitfld.long 0xB0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xB0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xB0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xB0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xB0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xB0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xB0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xB0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB4 "PADBT_cfg_reg,"
hexmask.long.tbyte 0xB4 11.--31. 1. "NU,Reserved"
bitfld.long 0xB4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xB4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xB4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xB4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xB4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xB4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xB4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xB4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "PADBU_cfg_reg,"
hexmask.long.tbyte 0xB8 11.--31. 1. "NU,Reserved"
bitfld.long 0xB8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xB8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xB8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xB8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xB8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xB8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xB8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xB8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xBC "PADBV_cfg_reg,"
hexmask.long.tbyte 0xBC 11.--31. 1. "NU,Reserved"
bitfld.long 0xBC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xBC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xBC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xBC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xBC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xBC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xBC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xBC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC0 "PADBW_cfg_reg,"
hexmask.long.tbyte 0xC0 11.--31. 1. "NU,Reserved"
bitfld.long 0xC0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xC0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xC0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xC0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xC0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xC0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xC0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xC0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "PADBX_cfg_reg,"
hexmask.long.tbyte 0xC4 11.--31. 1. "NU,Reserved"
bitfld.long 0xC4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xC4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xC4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xC4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xC4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xC4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xC4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xC4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "PADBY_cfg_reg,"
hexmask.long.tbyte 0xC8 11.--31. 1. "NU,Reserved"
bitfld.long 0xC8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xC8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xC8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xC8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xC8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xC8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xC8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xC8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "PADBZ_cfg_reg,"
hexmask.long.tbyte 0xCC 11.--31. 1. "NU,Reserved"
bitfld.long 0xCC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xCC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xCC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xCC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xCC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xCC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xCC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xCC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD0 "PADCA_cfg_reg,"
hexmask.long.tbyte 0xD0 11.--31. 1. "NU,Reserved"
bitfld.long 0xD0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xD0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xD0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xD0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xD0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xD0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xD0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xD0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "PADCB_cfg_reg,"
hexmask.long.tbyte 0xD4 11.--31. 1. "NU,Reserved"
bitfld.long 0xD4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xD4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xD4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xD4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xD4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xD4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xD4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xD4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD8 "PADCC_cfg_reg,"
hexmask.long.tbyte 0xD8 11.--31. 1. "NU,Reserved"
bitfld.long 0xD8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xD8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xD8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xD8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xD8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xD8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xD8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xD8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "PADCD_cfg_reg,"
hexmask.long.tbyte 0xDC 11.--31. 1. "NU,Reserved"
bitfld.long 0xDC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xDC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xDC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xDC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xDC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xDC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xDC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xDC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE0 "PADCE_cfg_reg,"
hexmask.long.tbyte 0xE0 11.--31. 1. "NU,Reserved"
bitfld.long 0xE0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xE0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xE0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xE0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xE0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xE0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xE0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xE0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "PADCF_cfg_reg,"
hexmask.long.tbyte 0xE4 11.--31. 1. "NU,Reserved"
bitfld.long 0xE4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xE4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xE4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xE4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xE4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xE4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xE4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xE4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE8 "PADCG_cfg_reg,"
hexmask.long.tbyte 0xE8 11.--31. 1. "NU,Reserved"
bitfld.long 0xE8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xE8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xE8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xE8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xE8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xE8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xE8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xE8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "PADCH_cfg_reg,"
hexmask.long.tbyte 0xEC 11.--31. 1. "NU,Reserved"
bitfld.long 0xEC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xEC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xEC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xEC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xEC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xEC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xEC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xEC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF0 "PADCI_cfg_reg,"
hexmask.long.tbyte 0xF0 11.--31. 1. "NU,Reserved"
bitfld.long 0xF0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xF0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xF0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xF0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xF0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xF0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xF0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xF0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "PADCJ_cfg_reg,"
hexmask.long.tbyte 0xF4 11.--31. 1. "NU,Reserved"
bitfld.long 0xF4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xF4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xF4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xF4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xF4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xF4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xF4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xF4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF8 "PADCK_cfg_reg,"
hexmask.long.tbyte 0xF8 11.--31. 1. "NU,Reserved"
bitfld.long 0xF8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xF8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xF8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xF8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xF8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xF8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xF8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xF8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "PADCL_cfg_reg,"
hexmask.long.tbyte 0xFC 11.--31. 1. "NU,Reserved"
bitfld.long 0xFC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xFC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xFC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xFC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xFC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xFC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xFC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xFC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x100 "PADCM_cfg_reg,"
hexmask.long.tbyte 0x100 11.--31. 1. "NU,Reserved"
bitfld.long 0x100 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x100 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x100 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x100 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x100 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x100 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x100 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x100 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "PADCN_cfg_reg,"
hexmask.long.tbyte 0x104 11.--31. 1. "NU,Reserved"
bitfld.long 0x104 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x104 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x104 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x104 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x104 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x104 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x104 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x104 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x108 "PADCO_cfg_reg,"
hexmask.long.tbyte 0x108 11.--31. 1. "NU,Reserved"
bitfld.long 0x108 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x108 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x108 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x108 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x108 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x108 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x108 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x108 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10C "PADCP_cfg_reg,"
hexmask.long.tbyte 0x10C 11.--31. 1. "NU,Reserved"
bitfld.long 0x10C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x10C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x10C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x10C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x10C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x10C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x10C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x10C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x110 "PADCQ_cfg_reg,"
hexmask.long.tbyte 0x110 11.--31. 1. "NU,Reserved"
bitfld.long 0x110 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x110 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x110 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x110 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x110 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x110 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x110 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x110 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x114 "PADCR_cfg_reg,"
hexmask.long.tbyte 0x114 11.--31. 1. "NU,Reserved"
bitfld.long 0x114 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x114 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x114 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x114 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x114 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x114 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x114 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x114 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x118 "PADCS_cfg_reg,"
hexmask.long.tbyte 0x118 11.--31. 1. "NU,Reserved"
bitfld.long 0x118 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x118 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x118 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x118 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x118 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x118 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x118 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x118 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x11C "PADCT_cfg_reg,"
hexmask.long.tbyte 0x11C 11.--31. 1. "NU,Reserved"
bitfld.long 0x11C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x11C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x11C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x11C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x11C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x11C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x11C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x11C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x120 "PADCU_cfg_reg,"
hexmask.long.tbyte 0x120 11.--31. 1. "NU,Reserved"
bitfld.long 0x120 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x120 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x120 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x120 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x120 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x120 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x120 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x120 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "PADCV_cfg_reg,"
hexmask.long.tbyte 0x124 11.--31. 1. "NU,Reserved"
bitfld.long 0x124 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x124 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x124 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x124 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x124 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x124 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x124 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x124 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x128 "PADCW_cfg_reg,"
hexmask.long.tbyte 0x128 11.--31. 1. "NU,Reserved"
bitfld.long 0x128 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x128 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x128 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x128 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x128 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x128 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x128 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x128 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x12C "PADCX_cfg_reg,"
hexmask.long.tbyte 0x12C 11.--31. 1. "NU,Reserved"
bitfld.long 0x12C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x12C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x12C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x12C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x12C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x12C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x12C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x12C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x130 "PADCY_cfg_reg,"
hexmask.long.tbyte 0x130 11.--31. 1. "NU,Reserved"
bitfld.long 0x130 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x130 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x130 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x130 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x130 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x130 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x130 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x130 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x134 "PADCZ_cfg_reg,"
hexmask.long.tbyte 0x134 11.--31. 1. "NU,Reserved"
bitfld.long 0x134 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x134 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x134 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x134 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x134 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x134 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x134 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x134 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x138 "PADDA_cfg_reg,"
hexmask.long.tbyte 0x138 11.--31. 1. "NU,Reserved"
bitfld.long 0x138 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x138 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x138 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x138 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x138 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x138 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x138 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x138 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x13C "PADDB_cfg_reg,"
hexmask.long.tbyte 0x13C 11.--31. 1. "NU,Reserved"
bitfld.long 0x13C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x13C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x13C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x13C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x13C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x13C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x13C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x13C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x140 "PADDC_cfg_reg,"
hexmask.long.tbyte 0x140 11.--31. 1. "NU,Reserved"
bitfld.long 0x140 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x140 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x140 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x140 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x140 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x140 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x140 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x140 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "PADDD_cfg_reg,"
hexmask.long.tbyte 0x144 11.--31. 1. "NU,Reserved"
bitfld.long 0x144 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x144 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x144 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x144 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x144 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x144 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x144 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x144 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x148 "PADDE_cfg_reg,"
hexmask.long.tbyte 0x148 11.--31. 1. "NU,Reserved"
bitfld.long 0x148 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x148 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x148 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x148 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x148 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x148 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x148 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x148 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14C "PADDF_cfg_reg,"
hexmask.long.tbyte 0x14C 11.--31. 1. "NU,Reserved"
bitfld.long 0x14C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x14C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x14C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x14C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x14C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x14C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x14C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x14C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x150 "PADDG_cfg_reg,"
hexmask.long.tbyte 0x150 11.--31. 1. "NU,Reserved"
bitfld.long 0x150 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x150 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x150 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x150 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x150 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x150 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x150 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x150 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x154 "PADDH_cfg_reg,"
hexmask.long.tbyte 0x154 11.--31. 1. "NU,Reserved"
bitfld.long 0x154 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x154 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x154 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x154 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x154 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x154 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x154 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x154 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x158 "PADDI_cfg_reg,"
hexmask.long.tbyte 0x158 11.--31. 1. "NU,Reserved"
bitfld.long 0x158 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x158 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x158 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x158 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x158 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x158 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x158 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x158 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x15C "PADDJ_cfg_reg,"
hexmask.long.tbyte 0x15C 11.--31. 1. "NU,Reserved"
bitfld.long 0x15C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x15C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x15C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x15C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x15C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x15C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x15C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x15C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x160 "PADDK_cfg_reg,"
hexmask.long.tbyte 0x160 11.--31. 1. "NU,Reserved"
bitfld.long 0x160 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x160 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x160 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x160 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x160 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x160 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x160 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x160 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "PADDL_cfg_reg,"
hexmask.long.tbyte 0x164 11.--31. 1. "NU,Reserved"
bitfld.long 0x164 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x164 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x164 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x164 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x164 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x164 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x164 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x164 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x168 "PADDM_cfg_reg,"
hexmask.long.tbyte 0x168 11.--31. 1. "NU,Reserved"
bitfld.long 0x168 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x168 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x168 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x168 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x168 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x168 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x168 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x168 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "PADDN_cfg_reg,"
hexmask.long.tbyte 0x16C 11.--31. 1. "NU,Reserved"
bitfld.long 0x16C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x16C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x16C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x16C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x16C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x16C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x16C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x16C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x170 "PADDO_cfg_reg,"
hexmask.long.tbyte 0x170 11.--31. 1. "NU,Reserved"
bitfld.long 0x170 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x170 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x170 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x170 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x170 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x170 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x170 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x170 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "PADDP_cfg_reg,"
hexmask.long.tbyte 0x174 11.--31. 1. "NU,Reserved"
bitfld.long 0x174 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x174 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x174 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x174 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x174 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x174 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x174 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x174 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x178 "PADDQ_cfg_reg,"
hexmask.long.tbyte 0x178 11.--31. 1. "NU,Reserved"
bitfld.long 0x178 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x178 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x178 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x178 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x178 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x178 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x178 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x178 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "PADDR_cfg_reg,"
hexmask.long.tbyte 0x17C 11.--31. 1. "NU,Reserved"
bitfld.long 0x17C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x17C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x17C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x17C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x17C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x17C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x17C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x17C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x180 "PADDS_cfg_reg,"
hexmask.long.tbyte 0x180 11.--31. 1. "NU,Reserved"
bitfld.long 0x180 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x180 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x180 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x180 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x180 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x180 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x180 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x180 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "PADDT_cfg_reg,"
hexmask.long.tbyte 0x184 11.--31. 1. "NU,Reserved"
bitfld.long 0x184 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x184 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x184 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x184 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x184 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x184 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x184 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x184 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x188 "PADDU_cfg_reg,"
hexmask.long.tbyte 0x188 11.--31. 1. "NU,Reserved"
bitfld.long 0x188 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x188 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x188 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x188 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x188 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x188 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x188 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x188 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "PADDV_cfg_reg,"
hexmask.long.tbyte 0x18C 11.--31. 1. "NU,Reserved"
bitfld.long 0x18C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x18C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x18C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x18C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x18C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x18C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x18C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x18C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "PADDW_cfg_reg,"
hexmask.long.tbyte 0x190 11.--31. 1. "NU,Reserved"
bitfld.long 0x190 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x190 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x190 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x190 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x190 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x190 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x190 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x190 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "PADDX_cfg_reg,"
hexmask.long.tbyte 0x194 11.--31. 1. "NU,Reserved"
bitfld.long 0x194 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x194 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x194 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x194 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x194 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x194 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x194 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x194 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x198 "PADDY_cfg_reg,"
hexmask.long.tbyte 0x198 11.--31. 1. "NU,Reserved"
bitfld.long 0x198 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x198 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x198 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x198 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x198 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x198 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x198 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x198 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "PADDZ_cfg_reg,"
hexmask.long.tbyte 0x19C 11.--31. 1. "NU,Reserved"
bitfld.long 0x19C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x19C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x19C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x19C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x19C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x19C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x19C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x19C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "PADEA_cfg_reg,"
hexmask.long.tbyte 0x1A0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1A0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1A0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1A0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1A0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1A0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1A0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1A0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1A0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "PADEB_cfg_reg,"
hexmask.long.tbyte 0x1A4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1A4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1A4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1A4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1A4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1A4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1A4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1A4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1A4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "PADEC_cfg_reg,"
hexmask.long.tbyte 0x1A8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1A8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1A8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1A8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1A8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1A8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1A8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1A8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1A8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "PADED_cfg_reg,"
hexmask.long.tbyte 0x1AC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1AC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1AC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1AC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1AC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1AC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1AC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1AC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1AC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "PADEE_cfg_reg,"
hexmask.long.tbyte 0x1B0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1B0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1B0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1B0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1B0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1B0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1B0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1B0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1B0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "PADEF_cfg_reg,"
hexmask.long.tbyte 0x1B4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1B4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1B4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1B4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1B4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1B4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1B4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1B4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1B4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B8 "PADEG_cfg_reg,"
hexmask.long.tbyte 0x1B8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1B8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1B8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1B8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1B8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1B8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1B8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1B8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1B8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "PADEH_cfg_reg,"
hexmask.long.tbyte 0x1BC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1BC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1BC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1BC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1BC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1BC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1BC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1BC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1BC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C0 "PADEI_cfg_reg,"
hexmask.long.tbyte 0x1C0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "PADEJ_cfg_reg,"
hexmask.long.tbyte 0x1C4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C8 "PADEK_cfg_reg,"
hexmask.long.tbyte 0x1C8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "PADEL_cfg_reg,"
hexmask.long.tbyte 0x1CC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1CC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1CC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1CC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1CC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1CC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1CC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1CC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1CC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "PADEM_cfg_reg,"
hexmask.long.tbyte 0x1D0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1D0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1D0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1D0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1D0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1D0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1D0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1D0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1D0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "PADEN_cfg_reg,"
hexmask.long.tbyte 0x1D4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1D4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1D4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1D4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1D4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1D4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1D4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1D4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1D4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D8 "PADEO_cfg_reg,"
hexmask.long.tbyte 0x1D8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1D8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1D8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1D8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1D8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1D8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1D8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1D8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1D8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "PADEP_cfg_reg,"
hexmask.long.tbyte 0x1DC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1DC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1DC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1DC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1DC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1DC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1DC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1DC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1DC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1F0++0x0F
line.long 0x00 "USERMODEEN,"
line.long 0x04 "PADGLBLCFGREG,"
line.long 0x08 "IOCFGKICK0,"
line.long 0x0C "IOCFGKICK1,"
width 0x0B
tree.end
tree "MSS_MCANA_CFG (MSS MCANA Configuration Module Registers)"
base ad:0x2F7FC00
rgroup.long 0x00++0x2B
line.long 0x00 "SS_PID,SS_PID"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SS_CTRL,SS_CTRL"
hexmask.long 0x04 7.--31. 1. "NU0,Reserved"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
bitfld.long 0x04 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1"
newline
rbitfld.long 0x04 0.--2. "NU,Reserved" "0,1,2,3,4,5,6,7"
line.long 0x08 "SS_STAT,SS_STAT"
hexmask.long 0x08 3.--31. 1. "NU1,Reserved"
bitfld.long 0x08 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MMI_DONE," "0,1"
bitfld.long 0x08 0. "NU,Reserved" "0,1"
line.long 0x0C "SS_ICS,SS_ICS"
hexmask.long 0x0C 1.--31. 1. "NU2,Reserved"
bitfld.long 0x0C 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x10 "SS_IRS,SS_IRS"
hexmask.long 0x10 1.--31. 1. "NU3,Reserved"
bitfld.long 0x10 0. "IRS,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x14 "SS_IECS,SS_IECS"
hexmask.long 0x14 1.--31. 1. "NU4,Reserved"
bitfld.long 0x14 0. "IECS,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x18 "SS_IE,SS_IE"
hexmask.long 0x18 1.--31. 1. "NU5,Reserved"
bitfld.long 0x18 0. "IE,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x1C "SS_IES,SS_IES"
hexmask.long 0x1C 1.--31. 1. "NU6,Reserved"
bitfld.long 0x1C 0. "IES,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "SS_EOI,SS_EOI"
hexmask.long.tbyte 0x20 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targeted interrupt"
line.long 0x24 "SS_EXT_TS_PS,SS_EXT_TS_PS"
hexmask.long.byte 0x24 24.--31. 1. "NU8,Reserved"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value"
line.long 0x28 "SS_EXT_TS_USIC,SS_EXT_TS_USIC"
hexmask.long 0x28 5.--31. 1. "NU9,Reserved"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x200++0x2F
line.long 0x00 "CREL,CREL"
bitfld.long 0x00 28.--31. "REL,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month"
newline
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x04 "ENDN,ENDN"
line.long 0x08 "CUST,CUST"
line.long 0x0C "DBTP,DBTP"
hexmask.long.byte 0x0C 24.--31. 1. "NU13,Reserved"
bitfld.long 0x0C 23. "TDC,Transmitter Delay Compensation" "0,1"
rbitfld.long 0x0C 21.--22. "NU12,Reserved" "0,1,2,3"
bitfld.long 0x0C 16.--20. "DBRP,Data Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x0C 13.--15. "NU11,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8.--12. "DTSEG1,Data time segment before smaple point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "DSJW,Data resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "TEST,TEST"
hexmask.long.tbyte 0x10 8.--31. 1. "NU15,Reserved"
rbitfld.long 0x10 7. "RX,Receive Pin" "0,1"
bitfld.long 0x10 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x10 4. "LBCK,Loop Back Mode" "0,1"
rbitfld.long 0x10 0.--3. "NU14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "RWD,RWD"
hexmask.long.word 0x14 16.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x14 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x14 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x18 "CCCR,CCCR"
hexmask.long.tbyte 0x18 15.--31. 1. "NU18,Reserved"
bitfld.long 0x18 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x18 13. "EFBI,Edge Filtering durign Bus Integration" "0,1"
bitfld.long 0x18 12. "PXHD,Protocol Exception Handling Disable" "0,1"
rbitfld.long 0x18 10.--11. "NU17,Reserved" "0,1,2,3"
newline
bitfld.long 0x18 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x18 8. "FDOE,FD Operation Enable" "0,1"
bitfld.long 0x18 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x18 6. "DAR,Disable Automatic Regransmission" "0,1"
bitfld.long 0x18 5. "MON,Bus Monitoring Mode" "0,1"
newline
bitfld.long 0x18 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x18 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x18 2. "ASM,Restriced Operation Mode" "0,1"
bitfld.long 0x18 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x18 0. "INIT,Initialization" "0,1"
line.long 0x1C "NBTP,NBTP"
hexmask.long.byte 0x1C 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x1C 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x1C 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
rbitfld.long 0x1C 7. "NU19,Reserved" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x20 "TSCC,TSCC"
hexmask.long.word 0x20 20.--31. 1. "NU21,Reserved"
bitfld.long 0x20 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 2.--15. 1. "NU20,Reserved"
bitfld.long 0x20 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x24 "TSCV,TSCV"
hexmask.long.word 0x24 16.--31. 1. "NU22,Reserved"
hexmask.long.word 0x24 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x28 "TOCC,TOCC"
hexmask.long.word 0x28 16.--31. 1. "TOP,Timeout Period"
hexmask.long.word 0x28 3.--15. 1. "NU23,Reserved"
bitfld.long 0x28 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x28 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x2C "TOCV,TOCV"
hexmask.long.word 0x2C 16.--31. 1. "NU24,Reserved"
hexmask.long.word 0x2C 0.--15. 1. "TOC,Timeout Counter"
rgroup.long 0x240++0x0B
line.long 0x00 "ECR,ECR"
hexmask.long.byte 0x00 24.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x00 15. "RP,Recieve Error Passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Recieve Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x04 "PSR,PSR"
hexmask.long.word 0x04 23.--31. 1. "NU27,Reserved"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x04 15. "NU26,Reserved" "0,1"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x04 13. "RFDF,Recieved a CAN FD Message" "0,1"
newline
bitfld.long 0x04 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x04 6. "EW,Warning Status" "0,1"
newline
bitfld.long 0x04 5. "EP,Error Passive" "0,1"
bitfld.long 0x04 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
line.long 0x08 "TDCR,TDCR"
hexmask.long.tbyte 0x08 15.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
rbitfld.long 0x08 7. "NU28,Reserved" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x250++0x0F
line.long 0x00 "IR,IR"
rbitfld.long 0x00 30.--31. "NU30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0,1"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning Status" "0,1"
bitfld.long 0x00 23. "EP,Error Passive" "0,1"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0,1"
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0,1"
newline
bitfld.long 0x00 20. "BEC,Bit Error Corrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0,1"
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0,1"
newline
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0,1"
newline
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission Complete" "0,1"
bitfld.long 0x00 8. "HPM,High Priority Message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0,1"
newline
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0x04 "IE,IE"
rbitfld.long 0x04 30.--31. "NU31,Reserved" "0,1,2,3"
bitfld.long 0x04 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "0,1"
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
newline
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
newline
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
newline
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1"
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x04 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0x04 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
newline
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x08 "ILS,ILS"
rbitfld.long 0x08 30.--31. "NU32,Reserved" "0,1,2,3"
bitfld.long 0x08 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "0,1"
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
newline
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
newline
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
newline
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x08 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x08 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
newline
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x0C "ILE,ILE"
hexmask.long 0x0C 2.--31. 1. "NU33,Reserved"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "0,1"
group.long 0x280++0x0B
line.long 0x00 "GFC,GFC"
hexmask.long 0x00 6.--31. 1. "NU34,Reserved"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,reject Remote Frames Standard" "0,1"
bitfld.long 0x00 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x04 "SIDFC,SIDFC"
hexmask.long.byte 0x04 24.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "LSS_S,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA_S,Filter List Standard Start Address"
rbitfld.long 0x04 0.--1. "NU35,Reserved" "0,1,2,3"
line.long 0x08 "XIDFC,XIDFC"
hexmask.long.byte 0x08 24.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x08 16.--23. 1. "LSS_X,List Size Standard"
hexmask.long.word 0x08 2.--15. 1. "FLSSA_X,Filter List Standard Start Address"
rbitfld.long 0x08 0.--1. "NU37,Reserved" "0,1,2,3"
group.long 0x290++0x57
line.long 0x00 "XIDAM,XIDAM"
rbitfld.long 0x00 29.--31. "NU39,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
line.long 0x04 "HPMS,HPMS"
hexmask.long.word 0x04 16.--31. 1. "NU40,Reserved"
bitfld.long 0x04 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x04 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "NDAT1,NDAT1"
line.long 0x0C "NDAT2,NDAT2"
line.long 0x10 "RXF0C,RXF0C"
bitfld.long 0x10 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
rbitfld.long 0x10 23. "NU42_1,Reserved" "0,1"
hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size"
rbitfld.long 0x10 15. "NU42,Reserved" "0,1"
newline
hexmask.long.word 0x10 2.--14. 1. "F0SA,Rx FIFO 0 Start Address"
rbitfld.long 0x10 0.--1. "NU41,Reserved" "0,1,2,3"
line.long 0x14 "RXF0S,RXF0S"
bitfld.long 0x14 26.--31. "NU46,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x14 22.--23. "NU45,Reserved" "0,1,2,3"
bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 14.--15. "NU44,Reserved" "0,1,2,3"
bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 7. "NU43,Reserved" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
line.long 0x18 "RXF0A,RXF0A"
hexmask.long 0x18 6.--31. 1. "NU47,Reserved"
bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "RXBC,RXBC"
hexmask.long.word 0x1C 16.--31. 1. "NU49,Reserved"
hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address"
rbitfld.long 0x1C 0.--1. "NU48,Reserved" "0,1,2,3"
line.long 0x20 "RXF1C,RXF1C"
bitfld.long 0x20 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 0 Watermark"
rbitfld.long 0x20 23. "NU50_1,Reserved" "0,1"
hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 0 Size"
rbitfld.long 0x20 15. "NU50,Reserved" "0,1"
newline
hexmask.long.word 0x20 2.--14. 1. "F1SA,Rx FIFO 0 Start Address"
rbitfld.long 0x20 0.--1. "NU499,Reserved" "0,1,2,3"
line.long 0x24 "RXF1S,RXF1S"
bitfld.long 0x24 26.--31. "NU54,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 25. "RF1L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x24 24. "F1F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x24 22.--23. "NU53,Reserved" "0,1,2,3"
bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 14.--15. "NU52,Reserved" "0,1,2,3"
bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 7. "NU51,Reserved" "0,1"
hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level"
line.long 0x28 "RXF1A,RXF1A"
hexmask.long 0x28 6.--31. 1. "NU55,Reserved"
bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "RXESC,RXESC"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU58,Reserved"
bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 7. "NU57,Reserved" "0,1"
bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 3. "NU56,Reserved" "0,1"
newline
bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x30 "TXBC,TXBC"
bitfld.long 0x30 31. "NU61,Reserved" "0,1"
bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x30 22.--23. "NU60,Reserved" "0,1,2,3"
bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address"
bitfld.long 0x30 0.--1. "NU59,Reserved" "0,1,2,3"
line.long 0x34 "TXFQS,TXFQS"
hexmask.long.word 0x34 22.--31. 1. "NU64,Reserved"
bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "0,1"
bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 13.--15. "NU63,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x34 8.--12. "TFGI,Tx Queue Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 6.--7. "NU62,Reserved" "0,1,2,3"
bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "TXESC,TXESC"
hexmask.long 0x38 3.--31. 1. "NU65,Reserved"
bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x3C "TXBRP,TXBRP"
line.long 0x40 "TXBAR,TXBAR"
line.long 0x44 "TXBCR,TXBCR"
line.long 0x48 "TXBTO,TXBTO"
line.long 0x4C "TXBCF,TXBCF"
line.long 0x50 "TXBTIE,TXBTIE"
line.long 0x54 "TXBCIE,TXBCIE"
group.long 0x2F0++0x0F
line.long 0x00 "TXEFC,TXEFC"
bitfld.long 0x00 30.--31. "NU68,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 22.--23. "NU67,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
newline
bitfld.long 0x00 0.--1. "NU66,Reserved" "0,1,2,3"
line.long 0x04 "TXEFS,TXEFS"
bitfld.long 0x04 26.--31. "NU72,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x04 24. "EFF,Event FIFO Full" "0,1"
bitfld.long 0x04 21.--23. "NU71,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 13.--15. "NU70,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--7. "NU69,Reserved" "0,1,2,3"
bitfld.long 0x04 0.--5. "EFFL,Event FIFO FIll Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "TXEFA,TXEFA"
hexmask.long 0x08 5.--31. 1. "NU73,Reserved"
bitfld.long 0x08 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "RES16,RES16"
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C 0xB8 0xBC )
rgroup.long ($2+0x230)++0x03
line.long 0x00 "RES$1,RES00"
repeat.end
width 0x0B
tree.end
tree "MSS_MCANA_ECC (MSS MCANA ECC Module Registers)"
base ad:0x2F7F800
rgroup.long 0x00++0x03
line.long 0x00 "REV,Aggregator Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "VECTOR,ECC Vector Register"
hexmask.long.byte 0x00 25.--31. 1. "NU1,Reserved"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDR,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
rbitfld.long 0x00 11.--14. "NU0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "STAT,Misc Status"
hexmask.long.tbyte 0x04 11.--31. 1. "NU2,Reserved"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x14++0x17
line.long 0x00 "CTRL,CTRL"
hexmask.long.tbyte 0x00 9.--31. 1. "NU3,TI Internal : Reserved"
bitfld.long 0x00 8. "CHECK TIMEOUT,TI Internal : Check timeout" "0,1"
bitfld.long 0x00 7. "CHECK PARITY,TI Internal : Check Parity" "0,1"
bitfld.long 0x00 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1"
newline
bitfld.long 0x00 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM" "0,1"
bitfld.long 0x00 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1"
bitfld.long 0x00 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1"
bitfld.long 0x00 2. "EN_RMW,TI Internal : Enable rmw" "0,1"
newline
bitfld.long 0x00 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1"
bitfld.long 0x00 0. "ECC_EN,TI Internal : Enable ECC" "0,1"
line.long 0x04 "ERR_CTRL1,ERR_CTRL1"
line.long 0x08 "ERR_CTRL2,ERR_CTRL2"
hexmask.long.word 0x08 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x08 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set"
line.long 0x0C "ERR_STAT1,ERR_STAT1"
hexmask.long.word 0x0C 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error"
bitfld.long 0x0C 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status" "0,1"
bitfld.long 0x0C 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status" "0,1,2,3"
bitfld.long 0x0C 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status" "0,1"
newline
bitfld.long 0x0C 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt" "0,1"
bitfld.long 0x0C 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt" "0,1,2,3"
newline
bitfld.long 0x0C 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt" "0,1"
bitfld.long 0x0C 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt" "0,1,2,3"
bitfld.long 0x0C 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt" "0,1,2,3"
line.long 0x10 "ERR_STAT2,ERR_STAT2"
line.long 0x14 "ERR_STAT3,ERR_STAT3"
hexmask.long.tbyte 0x14 10.--31. 1. "NU6,TI Internal : Reserved"
bitfld.long 0x14 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1"
hexmask.long.byte 0x14 2.--8. 1. "NU5,TI Internal : Reserved"
bitfld.long 0x14 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1"
newline
rbitfld.long 0x14 0. "NU4,TI Internal : Reserved" "0,1"
group.long 0x3C++0x07
line.long 0x00 "SEC_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU7,Reserved"
bitfld.long 0x00 0. "SEC_EOI_WR,EOI Register" "0,1"
line.long 0x04 "SEC_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU8,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU9,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU10,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DED_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU11,Reserved"
bitfld.long 0x00 0. "DED_EOI_WR,EOI Register" "0,1"
line.long 0x04 "DED_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU12,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "DED_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU13,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU14,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "AGGR_ENABLE_SET,AGGR interrupt enable set Register"
hexmask.long 0x00 2.--31. 1. "NU15,Reserved"
bitfld.long 0x00 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt Enable Set Register for parity errors" "0,1"
line.long 0x04 "AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
hexmask.long 0x04 2.--31. 1. "NU16,Reserved"
bitfld.long 0x04 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt Enable Clear for parity errors" "0,1"
line.long 0x08 "AGGR_STATUS_SET,AGGR interrupt status set Register"
hexmask.long 0x08 4.--31. 1. "NU17,Reserved"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "AGGR_STATUS_CLR,AGGR interrupt status clear Register"
hexmask.long 0x0C 4.--31. 1. "NU18,Reserved"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_MCANB_CFG (MSS MCANB Configuration Module Registers)"
base ad:0x3F7FC00
rgroup.long 0x00++0x2B
line.long 0x00 "SS_PID,SS_PID"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SS_CTRL,SS_CTRL"
hexmask.long 0x04 7.--31. 1. "NU0,Reserved"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
bitfld.long 0x04 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1"
newline
rbitfld.long 0x04 0.--2. "NU,Reserved" "0,1,2,3,4,5,6,7"
line.long 0x08 "SS_STAT,SS_STAT"
hexmask.long 0x08 3.--31. 1. "NU1,Reserved"
bitfld.long 0x08 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MMI_DONE," "0,1"
bitfld.long 0x08 0. "NU,Reserved" "0,1"
line.long 0x0C "SS_ICS,SS_ICS"
hexmask.long 0x0C 1.--31. 1. "NU2,Reserved"
bitfld.long 0x0C 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x10 "SS_IRS,SS_IRS"
hexmask.long 0x10 1.--31. 1. "NU3,Reserved"
bitfld.long 0x10 0. "IRS,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x14 "SS_IECS,SS_IECS"
hexmask.long 0x14 1.--31. 1. "NU4,Reserved"
bitfld.long 0x14 0. "IECS,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x18 "SS_IE,SS_IE"
hexmask.long 0x18 1.--31. 1. "NU5,Reserved"
bitfld.long 0x18 0. "IE,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x1C "SS_IES,SS_IES"
hexmask.long 0x1C 1.--31. 1. "NU6,Reserved"
bitfld.long 0x1C 0. "IES,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "SS_EOI,SS_EOI"
hexmask.long.tbyte 0x20 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targeted interrupt"
line.long 0x24 "SS_EXT_TS_PS,SS_EXT_TS_PS"
hexmask.long.byte 0x24 24.--31. 1. "NU8,Reserved"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value"
line.long 0x28 "SS_EXT_TS_USIC,SS_EXT_TS_USIC"
hexmask.long 0x28 5.--31. 1. "NU9,Reserved"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x200++0x2F
line.long 0x00 "CREL,CREL"
bitfld.long 0x00 28.--31. "REL,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month"
newline
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x04 "ENDN,ENDN"
line.long 0x08 "CUST,CUST"
line.long 0x0C "DBTP,DBTP"
hexmask.long.byte 0x0C 24.--31. 1. "NU13,Reserved"
bitfld.long 0x0C 23. "TDC,Transmitter Delay Compensation" "0,1"
rbitfld.long 0x0C 21.--22. "NU12,Reserved" "0,1,2,3"
bitfld.long 0x0C 16.--20. "DBRP,Data Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x0C 13.--15. "NU11,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8.--12. "DTSEG1,Data time segment before smaple point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "DSJW,Data resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "TEST,TEST"
hexmask.long.tbyte 0x10 8.--31. 1. "NU15,Reserved"
rbitfld.long 0x10 7. "RX,Receive Pin" "0,1"
bitfld.long 0x10 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x10 4. "LBCK,Loop Back Mode" "0,1"
rbitfld.long 0x10 0.--3. "NU14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "RWD,RWD"
hexmask.long.word 0x14 16.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x14 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x14 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x18 "CCCR,CCCR"
hexmask.long.tbyte 0x18 15.--31. 1. "NU18,Reserved"
bitfld.long 0x18 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x18 13. "EFBI,Edge Filtering durign Bus Integration" "0,1"
bitfld.long 0x18 12. "PXHD,Protocol Exception Handling Disable" "0,1"
rbitfld.long 0x18 10.--11. "NU17,Reserved" "0,1,2,3"
newline
bitfld.long 0x18 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x18 8. "FDOE,FD Operation Enable" "0,1"
bitfld.long 0x18 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x18 6. "DAR,Disable Automatic Regransmission" "0,1"
bitfld.long 0x18 5. "MON,Bus Monitoring Mode" "0,1"
newline
bitfld.long 0x18 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x18 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x18 2. "ASM,Restriced Operation Mode" "0,1"
bitfld.long 0x18 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x18 0. "INIT,Initialization" "0,1"
line.long 0x1C "NBTP,NBTP"
hexmask.long.byte 0x1C 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x1C 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x1C 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
rbitfld.long 0x1C 7. "NU19,Reserved" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x20 "TSCC,TSCC"
hexmask.long.word 0x20 20.--31. 1. "NU21,Reserved"
bitfld.long 0x20 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 2.--15. 1. "NU20,Reserved"
bitfld.long 0x20 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x24 "TSCV,TSCV"
hexmask.long.word 0x24 16.--31. 1. "NU22,Reserved"
hexmask.long.word 0x24 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x28 "TOCC,TOCC"
hexmask.long.word 0x28 16.--31. 1. "TOP,Timeout Period"
hexmask.long.word 0x28 3.--15. 1. "NU23,Reserved"
bitfld.long 0x28 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x28 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x2C "TOCV,TOCV"
hexmask.long.word 0x2C 16.--31. 1. "NU24,Reserved"
hexmask.long.word 0x2C 0.--15. 1. "TOC,Timeout Counter"
rgroup.long 0x240++0x0B
line.long 0x00 "ECR,ECR"
hexmask.long.byte 0x00 24.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x00 15. "RP,Recieve Error Passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Recieve Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x04 "PSR,PSR"
hexmask.long.word 0x04 23.--31. 1. "NU27,Reserved"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x04 15. "NU26,Reserved" "0,1"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x04 13. "RFDF,Recieved a CAN FD Message" "0,1"
newline
bitfld.long 0x04 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x04 6. "EW,Warning Status" "0,1"
newline
bitfld.long 0x04 5. "EP,Error Passive" "0,1"
bitfld.long 0x04 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
line.long 0x08 "TDCR,TDCR"
hexmask.long.tbyte 0x08 15.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
rbitfld.long 0x08 7. "NU28,Reserved" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x250++0x0F
line.long 0x00 "IR,IR"
rbitfld.long 0x00 30.--31. "NU30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0,1"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning Status" "0,1"
bitfld.long 0x00 23. "EP,Error Passive" "0,1"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0,1"
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0,1"
newline
bitfld.long 0x00 20. "BEC,Bit Error Corrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0,1"
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0,1"
newline
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0,1"
newline
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission Complete" "0,1"
bitfld.long 0x00 8. "HPM,High Priority Message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0,1"
newline
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0x04 "IE,IE"
rbitfld.long 0x04 30.--31. "NU31,Reserved" "0,1,2,3"
bitfld.long 0x04 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "0,1"
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
newline
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
newline
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
newline
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1"
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x04 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0x04 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
newline
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x08 "ILS,ILS"
rbitfld.long 0x08 30.--31. "NU32,Reserved" "0,1,2,3"
bitfld.long 0x08 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "0,1"
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
newline
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
newline
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
newline
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x08 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x08 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
newline
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x0C "ILE,ILE"
hexmask.long 0x0C 2.--31. 1. "NU33,Reserved"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "0,1"
group.long 0x280++0x0B
line.long 0x00 "GFC,GFC"
hexmask.long 0x00 6.--31. 1. "NU34,Reserved"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,reject Remote Frames Standard" "0,1"
bitfld.long 0x00 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x04 "SIDFC,SIDFC"
hexmask.long.byte 0x04 24.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "LSS_S,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA_S,Filter List Standard Start Address"
rbitfld.long 0x04 0.--1. "NU35,Reserved" "0,1,2,3"
line.long 0x08 "XIDFC,XIDFC"
hexmask.long.byte 0x08 24.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x08 16.--23. 1. "LSS_X,List Size Standard"
hexmask.long.word 0x08 2.--15. 1. "FLSSA_X,Filter List Standard Start Address"
rbitfld.long 0x08 0.--1. "NU37,Reserved" "0,1,2,3"
group.long 0x290++0x57
line.long 0x00 "XIDAM,XIDAM"
rbitfld.long 0x00 29.--31. "NU39,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
line.long 0x04 "HPMS,HPMS"
hexmask.long.word 0x04 16.--31. 1. "NU40,Reserved"
bitfld.long 0x04 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x04 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "NDAT1,NDAT1"
line.long 0x0C "NDAT2,NDAT2"
line.long 0x10 "RXF0C,RXF0C"
bitfld.long 0x10 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
rbitfld.long 0x10 23. "NU42_1,Reserved" "0,1"
hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size"
rbitfld.long 0x10 15. "NU42,Reserved" "0,1"
newline
hexmask.long.word 0x10 2.--14. 1. "F0SA,Rx FIFO 0 Start Address"
rbitfld.long 0x10 0.--1. "NU41,Reserved" "0,1,2,3"
line.long 0x14 "RXF0S,RXF0S"
bitfld.long 0x14 26.--31. "NU46,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x14 22.--23. "NU45,Reserved" "0,1,2,3"
bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 14.--15. "NU44,Reserved" "0,1,2,3"
bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 7. "NU43,Reserved" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
line.long 0x18 "RXF0A,RXF0A"
hexmask.long 0x18 6.--31. 1. "NU47,Reserved"
bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "RXBC,RXBC"
hexmask.long.word 0x1C 16.--31. 1. "NU49,Reserved"
hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address"
rbitfld.long 0x1C 0.--1. "NU48,Reserved" "0,1,2,3"
line.long 0x20 "RXF1C,RXF1C"
bitfld.long 0x20 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 0 Watermark"
rbitfld.long 0x20 23. "NU50_1,Reserved" "0,1"
hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 0 Size"
rbitfld.long 0x20 15. "NU50,Reserved" "0,1"
newline
hexmask.long.word 0x20 2.--14. 1. "F1SA,Rx FIFO 0 Start Address"
rbitfld.long 0x20 0.--1. "NU499,Reserved" "0,1,2,3"
line.long 0x24 "RXF1S,RXF1S"
bitfld.long 0x24 26.--31. "NU54,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 25. "RF1L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x24 24. "F1F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x24 22.--23. "NU53,Reserved" "0,1,2,3"
bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 14.--15. "NU52,Reserved" "0,1,2,3"
bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 7. "NU51,Reserved" "0,1"
hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level"
line.long 0x28 "RXF1A,RXF1A"
hexmask.long 0x28 6.--31. 1. "NU55,Reserved"
bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "RXESC,RXESC"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU58,Reserved"
bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 7. "NU57,Reserved" "0,1"
bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 3. "NU56,Reserved" "0,1"
newline
bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x30 "TXBC,TXBC"
bitfld.long 0x30 31. "NU61,Reserved" "0,1"
bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x30 22.--23. "NU60,Reserved" "0,1,2,3"
bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address"
bitfld.long 0x30 0.--1. "NU59,Reserved" "0,1,2,3"
line.long 0x34 "TXFQS,TXFQS"
hexmask.long.word 0x34 22.--31. 1. "NU64,Reserved"
bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "0,1"
bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 13.--15. "NU63,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x34 8.--12. "TFGI,Tx Queue Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 6.--7. "NU62,Reserved" "0,1,2,3"
bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "TXESC,TXESC"
hexmask.long 0x38 3.--31. 1. "NU65,Reserved"
bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x3C "TXBRP,TXBRP"
line.long 0x40 "TXBAR,TXBAR"
line.long 0x44 "TXBCR,TXBCR"
line.long 0x48 "TXBTO,TXBTO"
line.long 0x4C "TXBCF,TXBCF"
line.long 0x50 "TXBTIE,TXBTIE"
line.long 0x54 "TXBCIE,TXBCIE"
group.long 0x2F0++0x0F
line.long 0x00 "TXEFC,TXEFC"
bitfld.long 0x00 30.--31. "NU68,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 22.--23. "NU67,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
newline
bitfld.long 0x00 0.--1. "NU66,Reserved" "0,1,2,3"
line.long 0x04 "TXEFS,TXEFS"
bitfld.long 0x04 26.--31. "NU72,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x04 24. "EFF,Event FIFO Full" "0,1"
bitfld.long 0x04 21.--23. "NU71,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 13.--15. "NU70,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--7. "NU69,Reserved" "0,1,2,3"
bitfld.long 0x04 0.--5. "EFFL,Event FIFO FIll Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "TXEFA,TXEFA"
hexmask.long 0x08 5.--31. 1. "NU73,Reserved"
bitfld.long 0x08 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "RES16,RES16"
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C 0xB8 0xBC )
rgroup.long ($2+0x230)++0x03
line.long 0x00 "RES$1,RES00"
repeat.end
width 0x0B
tree.end
tree "MSS_MCANB_ECC (MSS MCANB ECC Module Registers)"
base ad:0x3F7F800
rgroup.long 0x00++0x03
line.long 0x00 "REV,Aggregator Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "VECTOR,ECC Vector Register"
hexmask.long.byte 0x00 25.--31. 1. "NU1,Reserved"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDR,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
rbitfld.long 0x00 11.--14. "NU0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "STAT,Misc Status"
hexmask.long.tbyte 0x04 11.--31. 1. "NU2,Reserved"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x14++0x17
line.long 0x00 "CTRL,CTRL"
hexmask.long.tbyte 0x00 9.--31. 1. "NU3,TI Internal : Reserved"
bitfld.long 0x00 8. "CHECK TIMEOUT,TI Internal : Check timeout" "0,1"
bitfld.long 0x00 7. "CHECK PARITY,TI Internal : Check Parity" "0,1"
bitfld.long 0x00 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1"
newline
bitfld.long 0x00 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM" "0,1"
bitfld.long 0x00 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1"
bitfld.long 0x00 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1"
bitfld.long 0x00 2. "EN_RMW,TI Internal : Enable rmw" "0,1"
newline
bitfld.long 0x00 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1"
bitfld.long 0x00 0. "ECC_EN,TI Internal : Enable ECC" "0,1"
line.long 0x04 "ERR_CTRL1,ERR_CTRL1"
line.long 0x08 "ERR_CTRL2,ERR_CTRL2"
hexmask.long.word 0x08 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x08 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set"
line.long 0x0C "ERR_STAT1,ERR_STAT1"
hexmask.long.word 0x0C 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error"
bitfld.long 0x0C 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status" "0,1"
bitfld.long 0x0C 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status" "0,1,2,3"
bitfld.long 0x0C 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status" "0,1"
newline
bitfld.long 0x0C 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt" "0,1"
bitfld.long 0x0C 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt" "0,1,2,3"
newline
bitfld.long 0x0C 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt" "0,1"
bitfld.long 0x0C 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt" "0,1,2,3"
bitfld.long 0x0C 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt" "0,1,2,3"
line.long 0x10 "ERR_STAT2,ERR_STAT2"
line.long 0x14 "ERR_STAT3,ERR_STAT3"
hexmask.long.tbyte 0x14 10.--31. 1. "NU6,TI Internal : Reserved"
bitfld.long 0x14 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1"
hexmask.long.byte 0x14 2.--8. 1. "NU5,TI Internal : Reserved"
bitfld.long 0x14 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1"
newline
rbitfld.long 0x14 0. "NU4,TI Internal : Reserved" "0,1"
group.long 0x3C++0x07
line.long 0x00 "SEC_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU7,Reserved"
bitfld.long 0x00 0. "SEC_EOI_WR,EOI Register" "0,1"
line.long 0x04 "SEC_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU8,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU9,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU10,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DED_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU11,Reserved"
bitfld.long 0x00 0. "DED_EOI_WR,EOI Register" "0,1"
line.long 0x04 "DED_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU12,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "DED_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU13,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU14,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "AGGR_ENABLE_SET,AGGR interrupt enable set Register"
hexmask.long 0x00 2.--31. 1. "NU15,Reserved"
bitfld.long 0x00 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt Enable Set Register for parity errors" "0,1"
line.long 0x04 "AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
hexmask.long 0x04 2.--31. 1. "NU16,Reserved"
bitfld.long 0x04 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt Enable Clear for parity errors" "0,1"
line.long 0x08 "AGGR_STATUS_SET,AGGR interrupt status set Register"
hexmask.long 0x08 4.--31. 1. "NU17,Reserved"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "AGGR_STATUS_CLR,AGGR interrupt status clear Register"
hexmask.long 0x0C 4.--31. 1. "NU18,Reserved"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_MCRC (MSS MCRC Module Registers)"
base ad:0xC5020000
group.long 0x00++0x03
line.long 0x00 "CRC_CTRL0,Contains sw reset control bit to reset PSA"
rbitfld.long 0x00 31. "NU12,Reserved" "0,1"
rbitfld.long 0x00 30. "NU11,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "NU10,Reserved" "0,1"
rbitfld.long 0x00 27.--28. "NU9,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 25.--26. "NU8,Reserved" "0,1,2,3"
rbitfld.long 0x00 24. "NU7,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "NU6,Reserved" "0,1"
rbitfld.long 0x00 22. "NU5,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "NU4,Reserved" "0,1"
rbitfld.long 0x00 19.--20. "NU3,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 17.--18. "NU2,Reserved" "0,1,2,3"
rbitfld.long 0x00 16. "NU1,Reserved" "0,1"
newline
bitfld.long 0x00 15. "CH2_CRC_SEL2,Refer 'CH2_DW_SEL' field description" "0,1"
bitfld.long 0x00 14. "CH2_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 13. "CH2_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 11.--12. "CH2_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 9.--10. "CH2_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 8. "CH2_PSA_SWREST,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 7. "CH1_CRC_SEL2,Refer 'CH1_DW_SEL' field description" "0,1"
bitfld.long 0x00 6. "CH1_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 5. "CH1_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 3.--4. "CH1_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 1.--2. "CH1_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 0. "CH1_PSA_SWREST,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
group.long 0x08++0x03
line.long 0x00 "CRC_CTRL1,Contains power down control bit"
hexmask.long 0x00 1.--31. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode"
group.long 0x10++0x03
line.long 0x00 "CRC_CTRL2,Contains channel mode. data trace enable control bits"
rbitfld.long 0x00 26.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "NU14,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 18.--23. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 16.--17. "NU13,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 10.--15. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode: 0" "reserved 1,Full-CPU mode,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved2,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable" "Data Trace disable,Data Trace enable"
newline
rbitfld.long 0x00 2.--3. "Reserved1,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode: 0" "reserved 1,Full-CPU mode,?..."
group.long 0x18++0x03
line.long 0x00 "CRC_INTS,Write one to a bit to enable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU22,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU21,Reserved" "0,1"
rbitfld.long 0x00 26. "NU20,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU19,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU18,Reserved" "0,1"
rbitfld.long 0x00 19. "NU17,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU16,Reserved" "0,1"
rbitfld.long 0x00 17. "NU15,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENS,Channel 2 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENS,Channel 1 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
bitfld.long 0x00 1. "CH1_CRCFAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x20++0x03
line.long 0x00 "CRC_INTR,Write one to a bit to disable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU30,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU29,Reserved" "0,1"
rbitfld.long 0x00 26. "NU28,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU27,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU26,Reserved" "0,1"
rbitfld.long 0x00 19. "NU25,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU24,Reserved" "0,1"
rbitfld.long 0x00 17. "NU23,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENR,Channel 2 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
newline
bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENR,Channel 1 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
newline
bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
bitfld.long 0x00 1. "CH1_CRCFAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x28++0x03
line.long 0x00 "CRC_STATUS_REG,Contains interrupt flags for different types of interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU38,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU37,Reserved" "0,1"
rbitfld.long 0x00 26. "NU36,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU35,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU34,Reserved" "0,1"
rbitfld.long 0x00 19. "NU33,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU32,Reserved" "0,1"
rbitfld.long 0x00 17. "NU31,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUT,Channel 2 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 9. "CH2_CRCFAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUT,Channel 1 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
bitfld.long 0x00 1. "CH1_CRCFAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x30++0x03
line.long 0x00 "CRC_INT_OFFSET_REG,Contains the interrupt offset vector address"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "OFSTREG,CRC Interrupt Offset"
rgroup.long 0x38++0x03
line.long 0x00 "CRC_BUSY,Contains the busy flag for each channel"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "NU40,Reserved" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved3,Reserved"
bitfld.long 0x00 16. "NU39,Reserved" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved2,Reserved"
bitfld.long 0x00 8. "Ch2_BUSY,Ch2_BUSY" "0,1"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "CH1_BUSY,CH1_BUSY" "0,1"
group.long 0x40++0x13
line.long 0x00 "CRC_PCOUNT_REG1,Channel 1 preload register for the pattern count"
hexmask.long.word 0x00 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register"
line.long 0x04 "CRC_SCOUNT_REG1,Channel 1 preload register for the sector count"
hexmask.long.word 0x04 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register"
line.long 0x08 "CRC_CURSEC_REG1,Channel 1 current sector register contains the sector number which causes CRC failure"
hexmask.long.word 0x08 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register"
line.long 0x0C "CRC_WDTOPLD1,Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register"
line.long 0x10 "CRC_BCTOPLD1,Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x10 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Regis- ter"
group.long 0x60++0x33
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA signature low register"
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA signature high register"
line.long 0x08 "CRC_REGL1,Channel 1 CRC value low register"
line.long 0x0C "CRC_REGH1,Channel 1 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL1,Channel 1 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH1,Channel 1 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL1,Channel 1 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH1,Channel 1 un-compressed raw data high register"
line.long 0x20 "CRC_PCOUNT_REG2,Channel 2 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,Channel 2 Pattern Counter Preload Register"
line.long 0x24 "CRC_SCOUNT_REG2,Channel 2 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register"
line.long 0x28 "CRC_CURSEC_REG2,Channel 2 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register"
line.long 0x2C "CRC_WDTOPLD2,Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register"
line.long 0x30 "CRC_BCTOPLD2,Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Regis- ter"
group.long 0xA0++0x33
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA signature low register"
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA signature high register"
line.long 0x08 "CRC_REGL2,Channel 2 CRC value low register"
line.long 0x0C "CRC_REGH2,Channel 2 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL2,Channel 2 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH2,Channel 2 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL2,Channel 2 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH2,Channel 2 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG3,Channel 3 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU41,Reserved"
line.long 0x24 "CRC_SCOUNT_REG3,Channel 3 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU42,Reserved"
line.long 0x28 "CRC_CURSEC_REG3,Channel 3 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU43,Reserved"
line.long 0x2C "CRC_WDTOPLD3,Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU44,Reserved"
line.long 0x30 "CRC_BCTOPLD3,Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU45,Reserved"
rgroup.long 0xE0++0x33
line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA signature low register"
line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA signature high register"
line.long 0x08 "CRC_REGL3,Channel 3 CRC value low register"
line.long 0x0C "CRC_REGH3,Channel 3 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL3,Channel 3 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH3,Channel 3 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL3,Channel 3 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH3,Channel 3 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG4,Channel 4 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU54,Reserved"
line.long 0x24 "CRC_SCOUNT_REG4,Channel 4 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU55,Reserved"
line.long 0x28 "CRC_CURSEC_REG4,Channel 4 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU56,Reserved"
line.long 0x2C "CRC_WDTOPLD4,Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU57,Reserved"
line.long 0x30 "CRC_BCTOPLD4,Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU58,Reserved"
rgroup.long 0x120++0x27
line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA signature low register"
line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA signature high register"
line.long 0x08 "CRC_REGL4,Channel 4 CRC value low register"
line.long 0x0C "CRC_REGH4,Channel 4 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL4,Channel 4 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH4,Channel 4 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL4,Channel 4 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH4,Channel 4 un-compressed raw data high Register"
line.long 0x20 "MCRC_BUS_SEL,Disables either or all tracing of data buses"
hexmask.long 0x20 3.--31. 1. "NU67,Reserved"
bitfld.long 0x20 2. "MEn,MEn" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled"
newline
bitfld.long 0x20 1. "DTCMEn,DTCMEn" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.."
bitfld.long 0x20 0. "ITCMEn,ITCMEn" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled"
line.long 0x24 "MCRC_RESERVED,0x144 to 0x1FF is reserved area"
width 0x0B
tree.end
tree "MSS_PCR1 (MSS PCR1 Module Registers)"
base ad:0x2F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "MSS_PCR2 (MSS PCR2 Module Registers)"
base ad:0x3F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
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abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "MSS_QSPI (MSS QSPI Module Registers)"
base ad:0xC8000000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID"
bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3"
bitfld.long 0x00 28.--29. "Reserved,Always read as 0" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,The function of the module being used"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Release Number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom IP" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "SYSCONFIG,SYSCONFIG"
hexmask.long 0x00 6.--31. 1. "Reserved3,Always read as 0"
rbitfld.long 0x00 4.--5. "Reserved2,Always read as 0" "0,1,2,3"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode"
newline
rbitfld.long 0x00 0.--1. "Reserved1,Always read as 0" "0,1,2,3"
group.long 0x20++0x13
line.long 0x00 "INTR_STATUS_RAW_SET,INTR Interrupt Status Raw/Set Register"
hexmask.long 0x00 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x00 1. "WIRQ_RAW,Word Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.."
bitfld.long 0x00 0. "FIRQ_RAW,Frame Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.."
line.long 0x04 "INTR_STATUS_ENABLED_CLEAR,INTR Interrupt Status Enabled/Clear Register"
hexmask.long 0x04 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x04 1. "WIRQ_ENA,Word Interrupt Enabled Status Read indicates enabled status" "inactive,active Writing 1 will.."
bitfld.long 0x04 0. "FIRQ_ENA,Frame Interrupt Enabled Status Read indicates enabled status" "inactive,active Writing 1 will.."
line.long 0x08 "INTR_ENABLE_SET,INTR Interrupt Enable/Set Register"
hexmask.long 0x08 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x08 1. "WIRQ_ENA_SET,Word Interrupt Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
bitfld.long 0x08 0. "FIRQ_ENA_SET,Frame Interrupt Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
line.long 0x0C "INTR_ENABLE_CLEAR,INTR Interrupt Enable/Clear Register"
hexmask.long 0x0C 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x0C 1. "WIRQ_ENA_CLR,Word Interrupt Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
bitfld.long 0x0C 0. "FIRQ_ENA_CLR,Frame Interrupt Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
line.long 0x10 "INTC_EOI,EOI Register"
group.long 0x40++0x27
line.long 0x00 "SPI_CLOCK_CNTRL,SPI Clock Control Register (SPICC)"
bitfld.long 0x00 31. "CLKEN,Clock Enable" "0,1"
hexmask.long.word 0x00 16.--30. 1. "Reserved,Always read as 0"
hexmask.long.word 0x00 0.--15. 1. "DCLK_DIV,Serial data clock divide by ratio"
line.long 0x04 "SPI_DC,SPI Data Control Register (SPIDC)"
rbitfld.long 0x04 29.--31. "Reserved4,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 27.--28. "DD3,Data delay for chip select 3 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
bitfld.long 0x04 26. "CKPH3,Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out.." "0,1"
newline
bitfld.long 0x04 25. "CSP3,Chip select polarity for chip select 3 0- Active low 1- Active high" "0,1"
bitfld.long 0x04 24. "CKP3,Clock polarity for chip select 3 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
rbitfld.long 0x04 21.--23. "Reserved3,Always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 19.--20. "DD2,Data delay for chip select 2 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
bitfld.long 0x04 18. "CKPH2,Clock phase for chip select 2" "0,1"
bitfld.long 0x04 17. "CSP2,Chip select polarity for chip select 2 0- Active low 1- Active high" "0,1"
newline
bitfld.long 0x04 16. "CKP2,Clock polarity for chip select 2 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
rbitfld.long 0x04 13.--15. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11.--12. "DD1,Data delay for chip select 1 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
newline
bitfld.long 0x04 10. "CKPH1,Clock phase for chip select 1" "0,1"
bitfld.long 0x04 9. "CSP1,Chip select polarity for chip select 1 0- Active low 1- Active high" "0,1"
bitfld.long 0x04 8. "CKP1,Clock polarity for chip select 1 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
newline
rbitfld.long 0x04 5.--7. "Reserved1,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3.--4. "DD0,Data delay for chip select 0 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
bitfld.long 0x04 2. "CKPH0,Clock phase for chip select 0" "0,1"
newline
bitfld.long 0x04 1. "CSP0,Chip select polarity for chip select 0 0- Active low 1- Active high" "0,1"
bitfld.long 0x04 0. "CKP0,Clock polarity for chip select 0 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
line.long 0x08 "SPI_CMD,SPI Command Register (SPICR)"
rbitfld.long 0x08 30.--31. "Reserved3,Always read as 0" "0,1,2,3"
bitfld.long 0x08 28.--29. "CSNUM,Device select" "0,1,2,3"
rbitfld.long 0x08 26.--27. "Reserved2,Always read as 0" "0,1,2,3"
newline
hexmask.long.byte 0x08 19.--25. 1. "WLEN,Word length"
bitfld.long 0x08 16.--18. "CMD,Transfer command 000- Reserved 001- 4 pin Read Single 010- 4 pin Write Single 011- 4 pin Read Dual 100 - Reserved 101 - 3 pin Read Single 110 - 3 pin Write Single 111 - 6 pin Read Quad" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 15. "FIRQ,Frame count interrupt enable" "0,1"
newline
bitfld.long 0x08 14. "WIRQ,Word count interrupt enable" "0,1"
rbitfld.long 0x08 12.--13. "Reserved1,Always read as 0" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "FLEN,Frame Length 0- 1 word 1- 2 words ... 4095 - 4096 words"
line.long 0x0C "SPI_STATUS,SPI Status Register (SPISR)"
bitfld.long 0x0C 28.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 16.--27. 1. "WDCNT,Word count"
hexmask.long.word 0x0C 3.--15. 1. "Reserved1,Always read as 0"
newline
bitfld.long 0x0C 2. "FC,Frame complete" "0,1"
bitfld.long 0x0C 1. "WC,Word complete" "0,1"
bitfld.long 0x0C 0. "BUSY,Busy bit" "0,1"
line.long 0x10 "SPI_DATA,SPI Data Register (SPIDR)"
line.long 0x14 "SPI_SETUP0,Memory Mapped SPI Setup0 Register"
rbitfld.long 0x14 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x14 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x14 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x14 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x14 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x14 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x14 0.--7. 1. "RCMD,Read Command"
line.long 0x18 "SPI_SETUP1,Memory Mapped SPI Setup1 Register"
rbitfld.long 0x18 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x18 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x18 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x18 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x18 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x18 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x18 0.--7. 1. "RCMD,Read Command"
line.long 0x1C "SPI_SETUP2,Memory Mapped SPI Setup2 Register"
rbitfld.long 0x1C 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x1C 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x1C 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x1C 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x1C 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x1C 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x1C 0.--7. 1. "RCMD,Read Command"
line.long 0x20 "SPI_SETUP3,Memory Mapped SPI Setup3 Register"
rbitfld.long 0x20 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x20 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x20 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x20 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x20 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x20 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x20 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x20 0.--7. 1. "RCMD,Read Command"
line.long 0x24 "SPI_SWITCH,Memory Mapped SPI Switch Register"
hexmask.long 0x24 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x24 1. "MM_INT_EN,Memory Mapped mode interrupt enable" "0,1"
bitfld.long 0x24 0. "MMPT_S,MMPT select" "0,1"
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
group.long ($2+0x68)++0x03
line.long 0x00 "SPI_DATA$1,SPI Data Register (SPIDR1)"
repeat.end
repeat 9. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x10 0x14 0x18 0x30 0x34 0x38 )
rgroup.long ($2+0x04)++0x03
line.long 0x00 "MSS_QSPI_Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_R5SS_STC (MSS R5SS STC Module Registers)"
base ad:0x2F79800
group.long 0x00++0x11B
line.long 0x00 "STCGCR0,Self test Global control Reg0"
hexmask.long.word 0x00 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run"
newline
rbitfld.long 0x00 11.--15. "NU0,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval" "Continue NSTC run from previous interval,Restart NSTC run from ROM address 0 1X = Start..,?..."
line.long 0x04 "STCGCR1,Self test Global control Reg1"
hexmask.long.tbyte 0x04 12.--31. 1. "NU2,Reserved bits"
newline
bitfld.long 0x04 8.--11. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x04 7. "NU3,Reserved bits" "0,1"
newline
bitfld.long 0x04 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode" "XOR mode,Spread mode"
newline
bitfld.long 0x04 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration" "Operates in Normal Scan Mode,Operates in Low Power Scan Mode"
newline
bitfld.long 0x04 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
newline
bitfld.long 0x04 0.--3. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "STCTPR,Time out counter preload register"
line.long 0x0C "STC_CADDR,Current Address register for CORE1"
line.long 0x10 "STCCICR,Current Interval count register"
hexmask.long.word 0x10 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well"
newline
hexmask.long.word 0x10 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run"
line.long 0x14 "STCGSTAT,Global Status Register"
hexmask.long.tbyte 0x14 12.--31. 1. "NU4,Reserved bits"
newline
bitfld.long 0x14 8.--11. "ST_ACTIVE,Tells whether self test is currently active or not" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 2.--7. "NU5,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)" "Self test run has not failed,SelfTest run has failed"
newline
bitfld.long 0x14 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)" "Not completed,SelfTest run Completed"
line.long 0x18 "STCFSTAT,Fail Status Register"
hexmask.long 0x18 5.--31. 1. "NU6,Reserved bits"
newline
bitfld.long 0x18 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur" "Failure on Segment 0,Failure on Segment 1,Failure on Segment 2,Failure on Segment 3"
newline
bitfld.long 0x18 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)" "No time out error occurred,SelfTest run failed due to a timeout error"
newline
bitfld.long 0x18 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)" "No MISR mismatch for CORE2,Self test run failed due to MISR mismatch for.."
newline
bitfld.long 0x18 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments" "No MISR mismatch for CORE1,Self test run failed due to MISR mismatch for.."
line.long 0x1C "STCSCSCR,Signature compare Self Check Register"
hexmask.long 0x1C 5.--31. 1. "NU7,Reserved bits"
newline
bitfld.long 0x1C 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)" "No fault insertion,Inserts fault in the logic unedr test which will.."
newline
bitfld.long 0x1C 0.--3. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "STC_CADDR2,Current Address register for CORE2"
line.long 0x24 "STC_CLKDIV,Clock Divider Register"
rbitfld.long 0x24 27.--31. "NU8,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 19.--23. "NU9,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 11.--15. "NU10,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 3.--7. "NU11,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
line.long 0x28 "STC_SEGPLR,Segment 1st interval Preload Register"
hexmask.long 0x28 2.--31. 1. "NU12,Reserved bits"
newline
bitfld.long 0x28 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter" "Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of.."
line.long 0x2C "SEG0_START_ADDR,ROM Start address for Segment0"
hexmask.long.word 0x2C 20.--31. 1. "NU13,Reserved bits"
newline
hexmask.long.tbyte 0x2C 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x30 "SEG1_START_ADDR,ROM Start address for Segment1"
hexmask.long.word 0x30 20.--31. 1. "NU14,Reserved bits"
newline
hexmask.long.tbyte 0x30 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x34 "SEG2_START_ADDR,ROM Start address for Segment2"
hexmask.long.word 0x34 20.--31. 1. "NU15,Reserved bits"
newline
hexmask.long.tbyte 0x34 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x38 "SEG3_START_ADDR,ROM Start address for Segment3"
hexmask.long.word 0x38 20.--31. 1. "NU16,Reserved bits"
newline
hexmask.long.tbyte 0x38 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x3C "CORE1_CURMISR_0,Holds the MISR signature for CORE1"
line.long 0x40 "CORE1_CURMISR_1,Holds the MISR signature for CORE1"
line.long 0x44 "CORE1_CURMISR_2,Holds the MISR signature for CORE1"
line.long 0x48 "CORE1_CURMISR_3,Holds the MISR signature for CORE1"
line.long 0x4C "CORE1_CURMISR_4,Holds the MISR signature for CORE1"
line.long 0x50 "CORE1_CURMISR_5,Holds the MISR signature for CORE1"
line.long 0x54 "CORE1_CURMISR_6,Holds the MISR signature for CORE1"
line.long 0x58 "CORE1_CURMISR_7,Holds the MISR signature for CORE1"
line.long 0x5C "CORE1_CURMISR_8,Holds the MISR signature for CORE1"
line.long 0x60 "CORE1_CURMISR_9,Holds the MISR signature for CORE1"
line.long 0x64 "CORE1_CURMISR_10,Holds the MISR signature for CORE1"
line.long 0x68 "CORE1_CURMISR_11,Holds the MISR signature for CORE1"
line.long 0x6C "CORE1_CURMISR_12,Holds the MISR signature for CORE1"
line.long 0x70 "CORE1_CURMISR_13,Holds the MISR signature for CORE1"
line.long 0x74 "CORE1_CURMISR_14,Holds the MISR signature for CORE1"
line.long 0x78 "CORE1_CURMISR_15,Holds the MISR signature for CORE1"
line.long 0x7C "CORE1_CURMISR_16,Holds the MISR signature for CORE1"
line.long 0x80 "CORE1_CURMISR_17,Holds the MISR signature for CORE1"
line.long 0x84 "CORE1_CURMISR_18,Holds the MISR signature for CORE1"
line.long 0x88 "CORE1_CURMISR_19,Holds the MISR signature for CORE1"
line.long 0x8C "CORE1_CURMISR_20,Holds the MISR signature for CORE1"
line.long 0x90 "CORE1_CURMISR_21,Holds the MISR signature for CORE1"
line.long 0x94 "CORE1_CURMISR_22,Holds the MISR signature for CORE1"
line.long 0x98 "CORE1_CURMISR_23,Holds the MISR signature for CORE1"
line.long 0x9C "CORE1_CURMISR_24,Holds the MISR signature for CORE1"
line.long 0xA0 "CORE1_CURMISR_25,Holds the MISR signature for CORE1"
line.long 0xA4 "CORE1_CURMISR_26,Holds the MISR signature for CORE1"
line.long 0xA8 "CORE1_CURMISR_27,Holds the MISR signature for CORE1"
line.long 0xAC "CORE2_CURMISR_0,Holds the MISR signature for CORE2"
line.long 0xB0 "CORE2_CURMISR_1,Holds the MISR signature for CORE2"
line.long 0xB4 "CORE2_CURMISR_2,Holds the MISR signature for CORE2"
line.long 0xB8 "CORE2_CURMISR_3,Holds the MISR signature for CORE2"
line.long 0xBC "CORE2_CURMISR_4,Holds the MISR signature for CORE2"
line.long 0xC0 "CORE2_CURMISR_5,Holds the MISR signature for CORE2"
line.long 0xC4 "CORE2_CURMISR_6,Holds the MISR signature for CORE2"
line.long 0xC8 "CORE2_CURMISR_7,Holds the MISR signature for CORE2"
line.long 0xCC "CORE2_CURMISR_8,Holds the MISR signature for CORE2"
line.long 0xD0 "CORE2_CURMISR_9,Holds the MISR signature for CORE2"
line.long 0xD4 "CORE2_CURMISR_10,Holds the MISR signature for CORE2"
line.long 0xD8 "CORE2_CURMISR_11,Holds the MISR signature for CORE2"
line.long 0xDC "CORE2_CURMISR_12,Holds the MISR signature for CORE2"
line.long 0xE0 "CORE2_CURMISR_13,Holds the MISR signature for CORE2"
line.long 0xE4 "CORE2_CURMISR_14,Holds the MISR signature for CORE2"
line.long 0xE8 "CORE2_CURMISR_15,Holds the MISR signature for CORE2"
line.long 0xEC "CORE2_CURMISR_16,Holds the MISR signature for CORE2"
line.long 0xF0 "CORE2_CURMISR_17,Holds the MISR signature for CORE2"
line.long 0xF4 "CORE2_CURMISR_18,Holds the MISR signature for CORE2"
line.long 0xF8 "CORE2_CURMISR_19,Holds the MISR signature for CORE2"
line.long 0xFC "CORE2_CURMISR_20,Holds the MISR signature for CORE2"
line.long 0x100 "CORE2_CURMISR_21,Holds the MISR signature for CORE2"
line.long 0x104 "CORE2_CURMISR_22,Holds the MISR signature for CORE2"
line.long 0x108 "CORE2_CURMISR_23,Holds the MISR signature for CORE2"
line.long 0x10C "CORE2_CURMISR_24,Holds the MISR signature for CORE2"
line.long 0x110 "CORE2_CURMISR_25,Holds the MISR signature for CORE2"
line.long 0x114 "CORE2_CURMISR_26,Holds the MISR signature for CORE2"
line.long 0x118 "CORE2_CURMISR_27,Holds the MISR signature for CORE2"
width 0x0B
tree.end
tree "MSS_RCM (MSS RCM Module Registers)"
base ad:0x2100000
rgroup.long 0x00++0x1CB
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MSS_RST_CAUSE_CLR,"
bitfld.long 0x04 0.--2. "clr,Write pulse bit field: Clear bit for rst cause register (writing '111' will clear the rst cause register)" "0,1,2,3,4,5,6,7"
line.long 0x08 "MSS_RST_STATUS,"
hexmask.long.word 0x08 0.--15. 1. "cause,Has the status because of which reset has happened"
line.long 0x0C "SYSRST_BY_DBG_RST,"
bitfld.long 0x0C 16.--18. "r5b,writing '000' will block debug reset request from CR5B toggling globally reset for CR5B" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0.--2. "r5a,writing '000' will block debug reset request from CR5A toggling globally reset for CR5A" "0,1,2,3,4,5,6,7"
line.long 0x10 "RST_ASSERDLY,"
hexmask.long.byte 0x10 0.--7. 1. "common,Value decides number of cycles reset should be asserted for CR5SS related resets"
line.long 0x14 "RST2ASSERTDLY,"
hexmask.long.byte 0x14 24.--31. 1. "r5b,Value decides number of cycles should be held before asserting reset for r5ss local reset for CR5B"
hexmask.long.byte 0x14 16.--23. 1. "r5a,Value decides number of cycles should be held before asserting reset for r5ss local reset for CR5A"
hexmask.long.byte 0x14 8.--15. 1. "r5ssb,Value decides number of cycles should be held before asserting reset for r5ss global reset for CR5B"
newline
hexmask.long.byte 0x14 0.--7. 1. "r5ssa,Value decides number of cycles should be held before asserting reset for r5ss global reset for CR5A"
line.long 0x18 "RST_WFICHECK,"
bitfld.long 0x18 24.--26. "r5b,writing '000' will disable check for WFI before local reset assertion of CR5A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 16.--18. "r5a,writing '000' will disable check for WFI before local reset assertion of CR5A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 8.--10. "r5ssb,writing '000' will disable check for WFI before global reset assertion of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 0.--2. "r5ssa,writing '000' will disable check for WFI before global reset assertion of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x1C "MSS_MCANA_CLK_SRC_SEL,"
hexmask.long.word 0x1C 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCANA.Data should be loaded as multibit"
line.long 0x20 "MSS_MCANB_CLK_SRC_SEL,"
hexmask.long.word 0x20 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCANB.Data should be loaded as multibit"
line.long 0x24 "MSS_QSPI_CLK_SRC_SEL,"
hexmask.long.word 0x24 0.--11. 1. "clksrcsel,Select line for selecting source clock for QSPI.Data should be loaded as multibit"
line.long 0x28 "MSS_RTIA_CLK_SRC_SEL,"
hexmask.long.word 0x28 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIA.Data should be loaded as multibit"
line.long 0x2C "MSS_RTIB_CLK_SRC_SEL,"
hexmask.long.word 0x2C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIB.Data should be loaded as multibit"
line.long 0x30 "MSS_RTIC_CLK_SRC_SEL,"
hexmask.long.word 0x30 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIC.Data should be loaded as multibit"
line.long 0x34 "MSS_WDT_CLK_SRC_SEL,"
hexmask.long.word 0x34 0.--11. 1. "clksrcsel,Select line for selecting source clock for WDT.Data should be loaded as multibit"
line.long 0x38 "MSS_SPIA_CLK_SRC_SEL,"
hexmask.long.word 0x38 0.--11. 1. "clksrcsel,Select line for selecting source clock for SPIA.Data should be loaded as multibit"
line.long 0x3C "MSS_SPIB_CLK_SRC_SEL,"
hexmask.long.word 0x3C 0.--11. 1. "clksrcsel,Select line for selecting source clock for SPIB.Data should be loaded as multibit"
line.long 0x40 "MSS_I2C_CLK_SRC_SEL,"
hexmask.long.word 0x40 0.--11. 1. "clksrcsel,Select line for selecting source clock for I2C.Data should be loaded as multibit"
line.long 0x44 "MSS_SCIA_CLK_SRC_SEL,"
hexmask.long.word 0x44 0.--11. 1. "clksrcsel,Select line for selecting source clock for SCIA.Data should be loaded as multibit"
line.long 0x48 "MSS_SCIB_CLK_SRC_SEL,"
hexmask.long.word 0x48 0.--11. 1. "clksrcsel,Select line for selecting source clock for SCIB.Data should be loaded as multibit"
line.long 0x4C "MSS_CPTS_CLK_SRC_SEL,"
hexmask.long.word 0x4C 0.--11. 1. "clksrcsel,Select line for selecting source clock for CPTS.Data should be loaded as multibit"
line.long 0x50 "MSS_CPSW_CLK_SRC_SEL,"
hexmask.long.word 0x50 0.--11. 1. "clksrcsel,Select line for selecting source clock for CPSW.Data should be loaded as multibit"
line.long 0x54 "MSS_MCANA_CLK_DIV_VAL,"
hexmask.long.word 0x54 0.--11. 1. "clkdivr,Divider value MCANA selected clock.Data should be loaded as multibit"
line.long 0x58 "MSS_MCANB_CLK_DIV_VAL,"
hexmask.long.word 0x58 0.--11. 1. "clkdivr,Divider value MCANB selected clock.Data should be loaded as multibit"
line.long 0x5C "MSS_QSPI_CLK_DIV_VAL,"
hexmask.long.word 0x5C 0.--11. 1. "clkdivr,Divider value QSPI selected clock.Data should be loaded as multibit"
line.long 0x60 "MSS_RTIA_CLK_DIV_VAL,"
hexmask.long.word 0x60 0.--11. 1. "clkdivr,Divider value RTIA selected clock.Data should be loaded as multibit"
line.long 0x64 "MSS_RTIB_CLK_DIV_VAL,"
hexmask.long.word 0x64 0.--11. 1. "clkdivr,Divider value RTIB selected clock.Data should be loaded as multibit"
line.long 0x68 "MSS_RTIC_CLK_DIV_VAL,"
hexmask.long.word 0x68 0.--11. 1. "clkdivr,Divider value RTIC selected clock.Data should be loaded as multibit"
line.long 0x6C "MSS_WDT_CLK_DIV_VAL,"
hexmask.long.word 0x6C 0.--11. 1. "clkdivr,Divider value WDT selected clock.Data should be loaded as multibit"
line.long 0x70 "MSS_SPIA_CLK_DIV_VAL,"
hexmask.long.word 0x70 0.--11. 1. "clkdivr,Divider value SPIA selected clock.Data should be loaded as multibit"
line.long 0x74 "MSS_SPIB_CLK_DIV_VAL,"
hexmask.long.word 0x74 0.--11. 1. "clkdivr,Divider value SPIB selected clock.Data should be loaded as multibit"
line.long 0x78 "MSS_I2C_CLK_DIV_VAL,"
hexmask.long.word 0x78 0.--11. 1. "clkdivr,Divider value I2C selected clock.Data should be loaded as multibit"
line.long 0x7C "MSS_SCIA_CLK_DIV_VAL,"
hexmask.long.word 0x7C 0.--11. 1. "clkdivr,Divider value SCIA selected clock.Data should be loaded as multibit"
line.long 0x80 "MSS_SCIB_CLK_DIV_VAL,"
hexmask.long.word 0x80 0.--11. 1. "clkdivr,Divider value SCIB selected clock.Data should be loaded as multibit"
line.long 0x84 "MSS_CPTS_CLK_DIV_VAL,"
hexmask.long.word 0x84 0.--11. 1. "clkdivr,Divider value CPTS selected clock.Data should be loaded as multibit"
line.long 0x88 "MSS_CPSW_CLK_DIV_VAL,"
hexmask.long.word 0x88 0.--11. 1. "clkdivr,Divider value CPSW selected clock.Data should be loaded as multibit"
line.long 0x8C "MSS_RGMII_CLK_DIV_VAL,"
hexmask.long.word 0x8C 0.--11. 1. "clkdivr,Divider value RGMII selected clock.Data should be loaded as multibit"
line.long 0x90 "MSS_MII100_CLK_DIV_VAL,"
hexmask.long.word 0x90 0.--11. 1. "clkdivr,Divider value MII100 selected clock.Data should be loaded as multibit"
line.long 0x94 "MSS_MII10_CLK_DIV_VAL,"
hexmask.long.tbyte 0x94 0.--23. 1. "clkdivr,Divider value MII10 selected clock.Data should be loaded as multibit"
line.long 0x98 "MSS_GPADC_CLK_DIV_VAL,"
hexmask.long.tbyte 0x98 0.--23. 1. "clkdivr,Divider value GPADC selected clock.Data should be loaded as multibit"
line.long 0x9C "MSS_MCANA_CLK_GATE,"
bitfld.long 0x9C 0.--2. "gated,writing '111' will gate clock for MCANA" "0,1,2,3,4,5,6,7"
line.long 0xA0 "MSS_MCANB_CLK_GATE,"
bitfld.long 0xA0 0.--2. "gated,writing '111' will gate clock for MCANB" "0,1,2,3,4,5,6,7"
line.long 0xA4 "MSS_QSPI_CLK_GATE,"
bitfld.long 0xA4 0.--2. "gated,writing '111' will gate clock for QSPI" "0,1,2,3,4,5,6,7"
line.long 0xA8 "MSS_RTIA_CLK_GATE,"
bitfld.long 0xA8 0.--2. "gated,writing '111' will gate clock for RTIA" "0,1,2,3,4,5,6,7"
line.long 0xAC "MSS_RTIB_CLK_GATE,"
bitfld.long 0xAC 0.--2. "gated,writing '111' will gate clock for RTIB" "0,1,2,3,4,5,6,7"
line.long 0xB0 "MSS_RTIC_CLK_GATE,"
bitfld.long 0xB0 0.--2. "gated,writing '111' will gate clock for RTIC" "0,1,2,3,4,5,6,7"
line.long 0xB4 "MSS_WDT_CLK_GATE,"
bitfld.long 0xB4 0.--2. "gated,writing '111' will gate clock for WDT" "0,1,2,3,4,5,6,7"
line.long 0xB8 "MSS_SPIA_CLK_GATE,"
bitfld.long 0xB8 0.--2. "gated,writing '111' will gate clock for SPIA" "0,1,2,3,4,5,6,7"
line.long 0xBC "MSS_SPIB_CLK_GATE,"
bitfld.long 0xBC 0.--2. "gated,writing '111' will gate clock for SPIB" "0,1,2,3,4,5,6,7"
line.long 0xC0 "MSS_I2C_CLK_GATE,"
bitfld.long 0xC0 0.--2. "gated,writing '111' will gate clock for I2C" "0,1,2,3,4,5,6,7"
line.long 0xC4 "MSS_SCIA_CLK_GATE,"
bitfld.long 0xC4 0.--2. "gated,writing '111' will gate clock for SCIA" "0,1,2,3,4,5,6,7"
line.long 0xC8 "MSS_SCIB_CLK_GATE,"
bitfld.long 0xC8 0.--2. "gated,writing '111' will gate clock for SCIB" "0,1,2,3,4,5,6,7"
line.long 0xCC "MSS_CPTS_CLK_GATE,"
bitfld.long 0xCC 0.--2. "gated,writing '111' will gate clock for CPTS" "0,1,2,3,4,5,6,7"
line.long 0xD0 "MSS_CPSW_CLK_GATE,"
bitfld.long 0xD0 0.--2. "gated,writing '111' will gate clock for CPSW" "0,1,2,3,4,5,6,7"
line.long 0xD4 "MSS_RGMII_CLK_GATE,"
bitfld.long 0xD4 0.--2. "gated,writing '111' will gate clock for RGMII" "0,1,2,3,4,5,6,7"
line.long 0xD8 "MSS_MII100_CLK_GATE,"
bitfld.long 0xD8 0.--2. "gated,writing '111' will gate clock for MII100" "0,1,2,3,4,5,6,7"
line.long 0xDC "MSS_MII10_CLK_GATE,"
bitfld.long 0xDC 0.--2. "gated,writing '111' will gate clock for MII10" "0,1,2,3,4,5,6,7"
line.long 0xE0 "MSS_GPADC_CLK_GATE,"
bitfld.long 0xE0 0.--2. "gated,writing '111' will gate clock for MSS GPADC" "0,1,2,3,4,5,6,7"
line.long 0xE4 "MSS_MCANA_CLK_STATUS,"
hexmask.long.byte 0xE4 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCANA"
hexmask.long.byte 0xE4 0.--7. 1. "clkinuse,Status shows the source clock slected for MCANA"
line.long 0xE8 "MSS_MCANB_CLK_STATUS,"
hexmask.long.byte 0xE8 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCANB"
hexmask.long.byte 0xE8 0.--7. 1. "clkinuse,Status shows the source clock slected for MCANB"
line.long 0xEC "MSS_QSPI_CLK_STATUS,"
hexmask.long.byte 0xEC 8.--15. 1. "currdivider,Status shows the current divider value choosen for QSPI"
hexmask.long.byte 0xEC 0.--7. 1. "clkinuse,Status shows the source clock slected for QSPI"
line.long 0xF0 "MSS_RTIA_CLK_STATUS,"
hexmask.long.byte 0xF0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIA"
hexmask.long.byte 0xF0 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIA"
line.long 0xF4 "MSS_RTIB_CLK_STATUS,"
hexmask.long.byte 0xF4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIB"
hexmask.long.byte 0xF4 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIB"
line.long 0xF8 "MSS_RTIC_CLK_STATUS,"
hexmask.long.byte 0xF8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIC"
hexmask.long.byte 0xF8 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIC"
line.long 0xFC "MSS_WDT_CLK_STATUS,"
hexmask.long.byte 0xFC 8.--15. 1. "currdivider,Status shows the current divider value choosen for WDT"
hexmask.long.byte 0xFC 0.--7. 1. "clkinuse,Status shows the source clock slected for WDT"
line.long 0x100 "MSS_SPIA_CLK_STATUS,"
hexmask.long.byte 0x100 8.--15. 1. "currdivider,Status shows the current divider value choosen for SPIA"
hexmask.long.byte 0x100 0.--7. 1. "clkinuse,Status shows the source clock slected for SPIA"
line.long 0x104 "MSS_SPIB_CLK_STATUS,"
hexmask.long.byte 0x104 8.--15. 1. "currdivider,Status shows the current divider value choosen for SPIB"
hexmask.long.byte 0x104 0.--7. 1. "clkinuse,Status shows the source clock slected for SPIB"
line.long 0x108 "MSS_I2C_CLK_STATUS,"
hexmask.long.byte 0x108 8.--15. 1. "currdivider,Status shows the current divider value choosen for I2C"
hexmask.long.byte 0x108 0.--7. 1. "clkinuse,Status shows the source clock slected for I2C"
line.long 0x10C "MSS_SCIA_CLK_STATUS,"
hexmask.long.byte 0x10C 8.--15. 1. "currdivider,Status shows the current divider value choosen for SCIA"
hexmask.long.byte 0x10C 0.--7. 1. "clkinuse,Status shows the source clock slected for SCIA"
line.long 0x110 "MSS_SCIB_CLK_STATUS,"
hexmask.long.byte 0x110 8.--15. 1. "currdivider,Status shows the current divider value choosen for SCIB"
hexmask.long.byte 0x110 0.--7. 1. "clkinuse,Status shows the source clock slected for SCIB"
line.long 0x114 "MSS_CPTS_CLK_STATUS,"
hexmask.long.byte 0x114 8.--15. 1. "currdivider,Status shows the current divider value choosen for CPTS"
hexmask.long.byte 0x114 0.--7. 1. "clkinuse,Status shows the source clock slected for CPTS"
line.long 0x118 "MSS_CPSW_CLK_STATUS,"
hexmask.long.byte 0x118 8.--15. 1. "currdivider,Status shows the current divider value choosen for CPSW"
hexmask.long.byte 0x118 0.--7. 1. "clkinuse,Status shows the source clock slected for CPSW"
line.long 0x11C "MSS_RGMII_CLK_STATUS,"
hexmask.long.byte 0x11C 8.--15. 1. "currdivider,Status shows the current divider value choosen for RGMII"
line.long 0x120 "MSS_MII100_CLK_STATUS,"
hexmask.long.byte 0x120 8.--15. 1. "currdivider,Status shows the current divider value choosen for MII100"
line.long 0x124 "MSS_MII10_CLK_STATUS,"
hexmask.long.byte 0x124 8.--15. 1. "currdivider,Status shows the current divider value choosen for MII10"
line.long 0x128 "MSS_GPADC_CLK_STATUS,"
hexmask.long.byte 0x128 8.--15. 1. "currdivider,Status shows the current divider value choosen for GPADC"
line.long 0x12C "MSS_CR5SS_POR_RST_CTRL,"
bitfld.long 0x12C 0.--2. "assert,write pulse bit field: writing '111' will assert por reset to R5SS" "0,1,2,3,4,5,6,7"
line.long 0x130 "MSS_CR5SSA_RST_CTRL,"
bitfld.long 0x130 0.--2. "assert,write pulse bit field: writing '111' will reset CR5A and MSS_CR5A_VIM" "0,1,2,3,4,5,6,7"
line.long 0x134 "MSS_CR5SSB_RST_CTRL,"
bitfld.long 0x134 0.--2. "assert,write pulse bit field: writing '111' will reset CR5B and MSS_CR5B_VIM" "0,1,2,3,4,5,6,7"
line.long 0x138 "MSS_CR5A_RST_CTRL,"
bitfld.long 0x138 0.--2. "assert,write pulse bit field: writing '111' will reset CR5A only" "0,1,2,3,4,5,6,7"
line.long 0x13C "MSS_CR5B_RST_CTRL,"
bitfld.long 0x13C 0.--2. "assert,write pulse bit field: writing '111' will reset CR5B only" "0,1,2,3,4,5,6,7"
line.long 0x140 "MSS_VIMA_RST_CTRL,"
bitfld.long 0x140 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x144 "MSS_VIMB_RST_CTRL,"
bitfld.long 0x144 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x148 "MSS_CRC_RST_CTRL,"
bitfld.long 0x148 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x14C "MSS_RTIA_RST_CTRL,"
bitfld.long 0x14C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x150 "MSS_RTIB_RST_CTRL,"
bitfld.long 0x150 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x154 "MSS_RTIC_RST_CTRL,"
bitfld.long 0x154 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x158 "MSS_WDT_RST_CTRL,"
bitfld.long 0x158 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x15C "MSS_ESM_RST_CTRL,"
bitfld.long 0x15C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x160 "MSS_DCCA_RST_CTRL,"
bitfld.long 0x160 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x164 "MSS_DCCB_RST_CTRL,"
bitfld.long 0x164 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x168 "MSS_DCCC_RST_CTRL,"
bitfld.long 0x168 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x16C "MSS_DCCD_RST_CTRL,"
bitfld.long 0x16C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x170 "MSS_GIO_RST_CTRL,"
bitfld.long 0x170 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x174 "MSS_SPIA_RST_CTRL,"
bitfld.long 0x174 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x178 "MSS_SPIB_RST_CTRL,"
bitfld.long 0x178 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x17C "MSS_QSPI_RST_CTRL,"
bitfld.long 0x17C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x180 "MSS_PWM1_RST_CTRL,"
bitfld.long 0x180 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x184 "MSS_PWM2_RST_CTRL,"
bitfld.long 0x184 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x188 "MSS_PWM3_RST_CTRL,"
bitfld.long 0x188 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x18C "MSS_MCANA_RST_CTRL,"
bitfld.long 0x18C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x190 "MSS_MCANB_RST_CTRL,"
bitfld.long 0x190 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x194 "MSS_I2C_RST_CTRL,"
bitfld.long 0x194 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x198 "MSS_SCIA_RST_CTRL,"
bitfld.long 0x198 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x19C "MSS_SCIB_RST_CTRL,"
bitfld.long 0x19C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1A0 "MSS_EDMA_RST_CTRL,"
bitfld.long 0x1A0 24.--26. "tptcb0_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 16.--18. "tpccb_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 12.--14. "tptca1_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A0 8.--10. "tptca0_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 4.--6. "tpcca_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1A4 "MSS_INFRA_RST_CTRL,"
bitfld.long 0x1A4 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "MSS_CPSW_RST_CTRL,"
bitfld.long 0x1A8 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1AC "MSS_GPADC_RST_CTRL,"
bitfld.long 0x1AC 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "MSS_DMM_RST_CTRL,"
bitfld.long 0x1B0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "R5_COREA_GATE,"
bitfld.long 0x1B4 0.--2. "clkgate,writing '111' will gate clock to CR5A related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7"
line.long 0x1B8 "R5_COREB_GATE,"
bitfld.long 0x1B8 0.--2. "clkgate,writing '111' will gate clock to CR5B related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7"
line.long 0x1BC "MSS_L2_BANKA_PD_CTRL,"
bitfld.long 0x1BC 8.--10. "agoodin,SW control for power signal 'AGOODIN' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
bitfld.long 0x1BC 4.--6. "aonin,SW control for power signal 'AONIN' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
bitfld.long 0x1BC 0.--2. "iso,SW control for power signal 'ISO' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "MSS_L2_BANKB_PD_CTRL,"
bitfld.long 0x1C0 8.--10. "agoodin,SW control for power signal 'AGOODIN' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C0 4.--6. "aonin,SW control for power signal 'AONIN' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C0 0.--2. "iso,SW control for power signal 'ISO' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "MSS_L2_BANKA_PD_STATUS,"
bitfld.long 0x1C4 1. "agoodout,SW status indicating the 'pgoodin' of MSS_L2_BANKA" "0,1"
bitfld.long 0x1C4 0. "aonout,SW status indicating the 'ponin' of MSS_L2_BANKA" "0,1"
line.long 0x1C8 "MSS_L2_BANKB_PD_STATUS,"
bitfld.long 0x1C8 1. "agoodout,SW status indicating the 'pgoodin' of MSS_L2_BANKB" "0,1"
bitfld.long 0x1C8 0. "aonout,SW status indicating the 'ponin' of MSS_L2_BANKB" "0,1"
group.long 0x1D4++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x400++0x4F
line.long 0x00 "HSM_RTIA_CLK_SRC_SEL,"
hexmask.long.word 0x00 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_RTIA.Data should be loaded as multibit"
line.long 0x04 "HSM_WDT_CLK_SRC_SEL,"
hexmask.long.word 0x04 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_WDT.Data should be loaded as multibit"
line.long 0x08 "HSM_RTC_CLK_SRC_SEL,"
hexmask.long.word 0x08 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_RTC.Data should be loaded as multibit"
line.long 0x0C "HSM_DMTA_CLK_SRC_SEL,"
hexmask.long.word 0x0C 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_DMTA.Data should be loaded as multibit"
line.long 0x10 "HSM_DMTB_CLK_SRC_SEL,"
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_DMTB.Data should be loaded as multibit"
line.long 0x14 "HSM_RTI_CLK_DIV_VAL,"
hexmask.long.word 0x14 0.--11. 1. "clkdivr,Divider value HSM RTI selected clock.Data should be loaded as multibit"
line.long 0x18 "HSM_WDT_CLK_DIV_VAL,"
hexmask.long.word 0x18 0.--11. 1. "clkdivr,Divider value HSM WDT selected clock.Data should be loaded as multibit"
line.long 0x1C "HSM_RTC_CLK_DIV_VAL,"
hexmask.long.word 0x1C 0.--11. 1. "clkdivr,Divider value HSM RTC selected clock.Data should be loaded as multibit"
line.long 0x20 "HSM_DMTA_CLK_DIV_VAL,"
hexmask.long.word 0x20 0.--11. 1. "clkdivr,Divider value HSM DMTA selected clock.Data should be loaded as multibit"
line.long 0x24 "HSM_DMTB_CLK_DIV_VAL,"
hexmask.long.word 0x24 0.--11. 1. "clkdivr,Divider value HSM DMTB selected clock.Data should be loaded as multibit"
line.long 0x28 "HSM_RTI_CLK_GATE,"
bitfld.long 0x28 0.--2. "gated,writing '111' will gate clock for HSM RTI" "0,1,2,3,4,5,6,7"
line.long 0x2C "HSM_WDT_CLK_GATE,"
bitfld.long 0x2C 0.--2. "gated,writing '111' will gate clock for HSM WDT" "0,1,2,3,4,5,6,7"
line.long 0x30 "HSM_RTC_CLK_GATE,"
bitfld.long 0x30 0.--2. "gated,writing '111' will gate clock for HSM RTC" "0,1,2,3,4,5,6,7"
line.long 0x34 "HSM_DMTA_CLK_GATE,"
bitfld.long 0x34 0.--2. "gated,writing '111' will gate clock for HSM DMTA" "0,1,2,3,4,5,6,7"
line.long 0x38 "HSM_DMTB_CLK_GATE,"
bitfld.long 0x38 0.--2. "gated,writing '111' will gate clock for HSM DMTB" "0,1,2,3,4,5,6,7"
line.long 0x3C "HSM_RTI_CLK_STATUS,"
hexmask.long.byte 0x3C 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_RTI"
hexmask.long.byte 0x3C 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_RTI"
line.long 0x40 "HSM_WDT_CLK_STATUS,"
hexmask.long.byte 0x40 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_WDT"
hexmask.long.byte 0x40 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_WDT"
line.long 0x44 "HSM_RTC_CLK_STATUS,"
hexmask.long.byte 0x44 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_RTC"
hexmask.long.byte 0x44 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_RTC"
line.long 0x48 "HSM_DMTA_CLK_STATUS,"
hexmask.long.byte 0x48 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_DMTA"
hexmask.long.byte 0x48 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_DMTA"
line.long 0x4C "HSM_DMTB_CLK_STATUS,"
hexmask.long.byte 0x4C 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_DMTB"
hexmask.long.byte 0x4C 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_DMTB"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x1CC)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_RTIA (MSS RTIA Module Registers)"
base ad:0x2F7A000
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "MSS_RTIB (MSS RTIB Module Registers)"
base ad:0x2F7A100
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "MSS_RTIC (MSS RTIC Module Registers)"
base ad:0x2F7A200
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "MSS_SCIA (MSS SCIA Module Registers)"
base ad:0x2F7EC00
group.long 0x00++0x5F
line.long 0x00 "SCIGCR0,The SCIGCR0 register defines the module reset"
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
newline
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
line.long 0x04 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
rbitfld.long 0x04 26.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
newline
bitfld.long 0x04 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
newline
rbitfld.long 0x04 18.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
newline
bitfld.long 0x04 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
newline
rbitfld.long 0x04 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
newline
bitfld.long 0x04 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function" "0,1"
newline
bitfld.long 0x04 7. "SW_nRESET,Software reset (active low)" "0,1"
newline
rbitfld.long 0x04 6. "RESERVED1,Reserved" "0,1"
newline
bitfld.long 0x04 5. "CLOCK,SCI internal clock enable" "0,1"
newline
bitfld.long 0x04 4. "STOP,SCI number of stop bits" "0,1"
newline
bitfld.long 0x04 3. "PARITY,SCI parity odd/even selection" "0,1"
newline
bitfld.long 0x04 2. "PARITY_ENA,SCI parity enable" "0,1"
newline
bitfld.long 0x04 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0,1"
newline
bitfld.long 0x04 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0,1"
line.long 0x08 "RESERVED1,Reserved"
line.long 0x0C "SCISETINT,SCI Set Interrupt Register"
rbitfld.long 0x0C 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request for address and data frames"
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bitfld.long 0x0C 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set" "leaves the corresponding bit unchanged,enable DMA request"
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bitfld.long 0x0C 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 8. "SET_TX_INT,Set Transmitter interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 0. "SET_BRKDT_INT,Set Break-detect interrupt" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x10 "SCICLEARINT,SCI Clear Interrupt Register"
rbitfld.long 0x10 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 25. "CLR_OE_INT,Clear Overrun-Error Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 24. "CLR_PE_INT,Clear Parity Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x10 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 18. "CLR_RX_DMA_ALL,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request for address frames"
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bitfld.long 0x10 17. "CLR_RX_DMA,Clear RX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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bitfld.long 0x10 16. "CLR_TX_DMA,Clear TX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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rbitfld.long 0x10 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 9. "CLR_RX_INT,Clear Receiver interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 8. "CLR_TX_INT,Clear Transmitter interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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rbitfld.long 0x10 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 0. "CLR_BRKDT_INT,Clear Break-detect interrupt" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x14 "SCISETINTLVL,SCI Set Interrupt Level Register"
rbitfld.long 0x14 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read)" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x14 15. "SET_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x14 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
line.long 0x18 "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
rbitfld.long 0x18 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x18 15. "CLR_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x18 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x18 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
line.long 0x1C "SCIFLR,SCI Flags Register"
rbitfld.long 0x1C 27.--31. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 26. "FE,SCI framing error flag Read" "No effect,Clears this bit to 0"
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rbitfld.long 0x1C 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
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rbitfld.long 0x1C 24. "PE,SCI parity error flag" "0,1"
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hexmask.long.word 0x1C 13.--23. 1. "RESERVED2,Reserved"
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rbitfld.long 0x1C 12. "RXWAKE,Receiver wake-up detect flag" "0,1"
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rbitfld.long 0x1C 11. "TX_EMPTY,Transmitter empty flag" "0,1"
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bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wake-up method select" "0,1"
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rbitfld.long 0x1C 9. "RXRDY,SCI receiver ready flag" "0,1"
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rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag" "0,1"
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rbitfld.long 0x1C 4.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame" "0,1"
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rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state" "0,1"
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rbitfld.long 0x1C 1. "WAKEUP,Wake-up flag" "0,1"
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rbitfld.long 0x1C 0. "BRKDT,SCI break-detect flag" "0,1"
line.long 0x20 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x20 0.--3. "INTVECT0,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x24 0.--3. "INTVECT1,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "SCICHAR,SCI Character Control Register"
hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x28 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
line.long 0x2C "SCIBAUD,SCI Baud Rate Selection Register"
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED,Reserved"
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hexmask.long.tbyte 0x2C 0.--23. 1. "BAUD,SCI 24-bit baud selection"
line.long 0x30 "SCIED,Receiver Emulation Data Buffer"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x30 0.--7. 1. "ED,Receiver Emulation Data Buffer"
line.long 0x34 "SCIRD,Receiver Data Buffer"
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x34 0.--7. 1. "RD,Contains received data"
line.long 0x38 "SCITD,Transmit Data Buffer Register"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x38 0.--7. 1. "TD,Contains Data to be transmitted"
line.long 0x3C "SCIPIO0,SCI Pin I/O Control Register 0"
hexmask.long 0x3C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x3C 2. "TX_FUNC,Defines the function of pin SCITX" "SCIRX is a general-purpose digital I/O pin,SCIRX is the SCI receive pin"
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bitfld.long 0x3C 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x3C 0. "CLK_FUNC,Clock function" "SCICLK is a general-purpose digital I/O pin,SCICLK is the SCI serial clock pin"
line.long 0x40 "SCIPIO1,SCI Pin I/O Control Register 1"
hexmask.long 0x40 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x40 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0)" "SCITX is a general-purpose input pin,SCITX is a general-purpose output pin"
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bitfld.long 0x40 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x40 0. "CLK_DIR,Clock data direction" "0,1"
line.long 0x44 "SCIPIO2,SCI Pin I/O Control Register 2"
hexmask.long 0x44 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x44 2. "TX_DATA_IN,Contains current value on the SCITX pin" "SCITX value is logic low,SCITX value is logic high"
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bitfld.long 0x44 1. "RX_DATA_IN,Contains current value on the SCIRX pin" "SCIRX value is logic low,SCIRX value is logic high"
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bitfld.long 0x44 0. "CLK_DATA_IN,Contains the current value on pin SCICLK" "Pin SCICLK value is logic low,Pin SCICLK value is logic high"
line.long 0x48 "SCIPIO3,SCI Pin I/O Control Register 3"
hexmask.long 0x48 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x48 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "Output value on SCITX is a 0 (logic low),Output value on SCITX is a 1 (logic high)"
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bitfld.long 0x48 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "Output value on SCIRX is 0 (logic low),Output value on SCIRX is 1 (logic high)"
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bitfld.long 0x48 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "Output value on SCICLK is a 0 (logic low),Output value on SCICLK is a 1 (logic high)"
line.long 0x4C "SCIPIO4,SCI Pin I/O Control Register 4"
hexmask.long 0x4C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4C 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
line.long 0x50 "SCIPIO5,SCI Pin I/O Control Register 5"
hexmask.long 0x50 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x50 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
line.long 0x54 "SCIPIO6,SCI Pin I/O Control Register 6"
hexmask.long 0x54 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x54 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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bitfld.long 0x54 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x54 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
line.long 0x58 "SCIPIO7,SCI Pin I/O Control Register 7"
hexmask.long 0x58 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x58 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX" "Pull Control on SCITX pin is enabled,Pull Control on SCITX pin is disabled"
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bitfld.long 0x58 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX" "Pull Control on SCIRX pin is enabled,Pull Control on SCIRX pin is disabled"
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bitfld.long 0x58 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK" "Pull Control on SCICLK pin is enabled,Pull Control on SCICLK pin is disabled"
line.long 0x5C "SCIPIO8,SCI Pin I/O Control Register 8"
hexmask.long 0x5C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x5C 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX" "Pull-Down is on SCITX pin,Pull-Up is on SCITX pin"
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bitfld.long 0x5C 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX" "Pull-Down is on SCIRX pin,Pull-Up is on SCIRX pin"
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bitfld.long 0x5C 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK" "Pull-Down is on SCICLK pin,Pull-Up is on SCICLK pin"
group.long 0x80++0x03
line.long 0x00 "SCIPIO9,SCI Pin I/O Control Register 9"
hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 2. "TX_SL,This bit controls the slew rate for the SCITX pin" "The normal output buffer is used for SCITX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 1. "RX_SL,This bit controls the slew rate for the SCIRX pin" "The normal output buffer is used for SCIRX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin" "The normal output buffer is used for SCICLK pin,The output buffer with slew control is used for.."
group.long 0x90++0x03
line.long 0x00 "SCIIODCTRL,SCI IO DFT Control"
rbitfld.long 0x00 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 26. "FEN,Frame Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 25. "PEN,Parity Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 24. "BRKDT_ENA,Break Detect Error Enable" "No effect,This bit is used to.."
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rbitfld.long 0x00 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry" "0,1,2,3"
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bitfld.long 0x00 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 12.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "LBP_ENA,Module loopback enable" "Digital loopback is enabled,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x00 0. "RXP_ENA,Module Analog loopback through receive pin enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
repeat 8. (list 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_SCIB (MSS SCIB Module Registers)"
base ad:0x2F7ED00
group.long 0x00++0x5F
line.long 0x00 "SCIGCR0,The SCIGCR0 register defines the module reset"
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
line.long 0x04 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
rbitfld.long 0x04 26.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
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bitfld.long 0x04 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
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rbitfld.long 0x04 18.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
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bitfld.long 0x04 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
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rbitfld.long 0x04 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
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bitfld.long 0x04 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function" "0,1"
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bitfld.long 0x04 7. "SW_nRESET,Software reset (active low)" "0,1"
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rbitfld.long 0x04 6. "RESERVED1,Reserved" "0,1"
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bitfld.long 0x04 5. "CLOCK,SCI internal clock enable" "0,1"
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bitfld.long 0x04 4. "STOP,SCI number of stop bits" "0,1"
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bitfld.long 0x04 3. "PARITY,SCI parity odd/even selection" "0,1"
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bitfld.long 0x04 2. "PARITY_ENA,SCI parity enable" "0,1"
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bitfld.long 0x04 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0,1"
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bitfld.long 0x04 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0,1"
line.long 0x08 "RESERVED1,Reserved"
line.long 0x0C "SCISETINT,SCI Set Interrupt Register"
rbitfld.long 0x0C 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request for address and data frames"
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bitfld.long 0x0C 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set" "leaves the corresponding bit unchanged,enable DMA request"
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bitfld.long 0x0C 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 8. "SET_TX_INT,Set Transmitter interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 0. "SET_BRKDT_INT,Set Break-detect interrupt" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x10 "SCICLEARINT,SCI Clear Interrupt Register"
rbitfld.long 0x10 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 25. "CLR_OE_INT,Clear Overrun-Error Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 24. "CLR_PE_INT,Clear Parity Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x10 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 18. "CLR_RX_DMA_ALL,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request for address frames"
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bitfld.long 0x10 17. "CLR_RX_DMA,Clear RX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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bitfld.long 0x10 16. "CLR_TX_DMA,Clear TX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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rbitfld.long 0x10 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 9. "CLR_RX_INT,Clear Receiver interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 8. "CLR_TX_INT,Clear Transmitter interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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rbitfld.long 0x10 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 0. "CLR_BRKDT_INT,Clear Break-detect interrupt" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x14 "SCISETINTLVL,SCI Set Interrupt Level Register"
rbitfld.long 0x14 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read)" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x14 15. "SET_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x14 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
line.long 0x18 "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
rbitfld.long 0x18 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x18 15. "CLR_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x18 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x18 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
line.long 0x1C "SCIFLR,SCI Flags Register"
rbitfld.long 0x1C 27.--31. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 26. "FE,SCI framing error flag Read" "No effect,Clears this bit to 0"
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rbitfld.long 0x1C 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
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rbitfld.long 0x1C 24. "PE,SCI parity error flag" "0,1"
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hexmask.long.word 0x1C 13.--23. 1. "RESERVED2,Reserved"
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rbitfld.long 0x1C 12. "RXWAKE,Receiver wake-up detect flag" "0,1"
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rbitfld.long 0x1C 11. "TX_EMPTY,Transmitter empty flag" "0,1"
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bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wake-up method select" "0,1"
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rbitfld.long 0x1C 9. "RXRDY,SCI receiver ready flag" "0,1"
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rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag" "0,1"
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rbitfld.long 0x1C 4.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame" "0,1"
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rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state" "0,1"
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rbitfld.long 0x1C 1. "WAKEUP,Wake-up flag" "0,1"
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rbitfld.long 0x1C 0. "BRKDT,SCI break-detect flag" "0,1"
line.long 0x20 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x20 0.--3. "INTVECT0,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x24 0.--3. "INTVECT1,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "SCICHAR,SCI Character Control Register"
hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x28 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
line.long 0x2C "SCIBAUD,SCI Baud Rate Selection Register"
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED,Reserved"
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hexmask.long.tbyte 0x2C 0.--23. 1. "BAUD,SCI 24-bit baud selection"
line.long 0x30 "SCIED,Receiver Emulation Data Buffer"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x30 0.--7. 1. "ED,Receiver Emulation Data Buffer"
line.long 0x34 "SCIRD,Receiver Data Buffer"
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x34 0.--7. 1. "RD,Contains received data"
line.long 0x38 "SCITD,Transmit Data Buffer Register"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x38 0.--7. 1. "TD,Contains Data to be transmitted"
line.long 0x3C "SCIPIO0,SCI Pin I/O Control Register 0"
hexmask.long 0x3C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x3C 2. "TX_FUNC,Defines the function of pin SCITX" "SCIRX is a general-purpose digital I/O pin,SCIRX is the SCI receive pin"
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bitfld.long 0x3C 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x3C 0. "CLK_FUNC,Clock function" "SCICLK is a general-purpose digital I/O pin,SCICLK is the SCI serial clock pin"
line.long 0x40 "SCIPIO1,SCI Pin I/O Control Register 1"
hexmask.long 0x40 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x40 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0)" "SCITX is a general-purpose input pin,SCITX is a general-purpose output pin"
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bitfld.long 0x40 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x40 0. "CLK_DIR,Clock data direction" "0,1"
line.long 0x44 "SCIPIO2,SCI Pin I/O Control Register 2"
hexmask.long 0x44 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x44 2. "TX_DATA_IN,Contains current value on the SCITX pin" "SCITX value is logic low,SCITX value is logic high"
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bitfld.long 0x44 1. "RX_DATA_IN,Contains current value on the SCIRX pin" "SCIRX value is logic low,SCIRX value is logic high"
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bitfld.long 0x44 0. "CLK_DATA_IN,Contains the current value on pin SCICLK" "Pin SCICLK value is logic low,Pin SCICLK value is logic high"
line.long 0x48 "SCIPIO3,SCI Pin I/O Control Register 3"
hexmask.long 0x48 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x48 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "Output value on SCITX is a 0 (logic low),Output value on SCITX is a 1 (logic high)"
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bitfld.long 0x48 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "Output value on SCIRX is 0 (logic low),Output value on SCIRX is 1 (logic high)"
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bitfld.long 0x48 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "Output value on SCICLK is a 0 (logic low),Output value on SCICLK is a 1 (logic high)"
line.long 0x4C "SCIPIO4,SCI Pin I/O Control Register 4"
hexmask.long 0x4C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4C 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
line.long 0x50 "SCIPIO5,SCI Pin I/O Control Register 5"
hexmask.long 0x50 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x50 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
line.long 0x54 "SCIPIO6,SCI Pin I/O Control Register 6"
hexmask.long 0x54 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x54 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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bitfld.long 0x54 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x54 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
line.long 0x58 "SCIPIO7,SCI Pin I/O Control Register 7"
hexmask.long 0x58 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x58 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX" "Pull Control on SCITX pin is enabled,Pull Control on SCITX pin is disabled"
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bitfld.long 0x58 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX" "Pull Control on SCIRX pin is enabled,Pull Control on SCIRX pin is disabled"
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bitfld.long 0x58 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK" "Pull Control on SCICLK pin is enabled,Pull Control on SCICLK pin is disabled"
line.long 0x5C "SCIPIO8,SCI Pin I/O Control Register 8"
hexmask.long 0x5C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x5C 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX" "Pull-Down is on SCITX pin,Pull-Up is on SCITX pin"
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bitfld.long 0x5C 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX" "Pull-Down is on SCIRX pin,Pull-Up is on SCIRX pin"
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bitfld.long 0x5C 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK" "Pull-Down is on SCICLK pin,Pull-Up is on SCICLK pin"
group.long 0x80++0x03
line.long 0x00 "SCIPIO9,SCI Pin I/O Control Register 9"
hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 2. "TX_SL,This bit controls the slew rate for the SCITX pin" "The normal output buffer is used for SCITX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 1. "RX_SL,This bit controls the slew rate for the SCIRX pin" "The normal output buffer is used for SCIRX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin" "The normal output buffer is used for SCICLK pin,The output buffer with slew control is used for.."
group.long 0x90++0x03
line.long 0x00 "SCIIODCTRL,SCI IO DFT Control"
rbitfld.long 0x00 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 26. "FEN,Frame Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 25. "PEN,Parity Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 24. "BRKDT_ENA,Break Detect Error Enable" "No effect,This bit is used to.."
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rbitfld.long 0x00 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry" "0,1,2,3"
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bitfld.long 0x00 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 12.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "LBP_ENA,Module loopback enable" "Digital loopback is enabled,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x00 0. "RXP_ENA,Module Analog loopback through receive pin enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
repeat 8. (list 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_SPIA (MSS SPIA Module Registers)"
base ad:0x2F7E800
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
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rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
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bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
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bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
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bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
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rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
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abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
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rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
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abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
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abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
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abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
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bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
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abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
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rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
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bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
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bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
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rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
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rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
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bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
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bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
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hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
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bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
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rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "MSS_SPIB (MSS SPIB Module Registers)"
base ad:0x2F7EA00
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
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rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
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bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
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bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
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bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
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rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
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abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
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rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
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abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
newline
rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
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bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
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abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
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rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
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bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
newline
bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
newline
rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
newline
rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
newline
bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
newline
bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
newline
bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
newline
hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
newline
bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
newline
rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "MSS_TOPRCM (MSS TOPRCM Module Registers)"
base ad:0x2140000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x17
line.long 0x00 "HSI_CLK_SRC_SEL,"
hexmask.long.word 0x00 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSI"
line.long 0x04 "CSIRX_CLK_SRC_SEL,"
hexmask.long.word 0x04 0.--11. 1. "clksrcsel,Select line for selecting source clock for CSI Rx Data should be loaded as multibit"
line.long 0x08 "MCUCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x08 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCU Clkout Data should be loaded as multibit"
line.long 0x0C "PMICCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x0C 0.--11. 1. "clksrcsel,Select line for selecting source clock for PMIC Clkout Data should be loaded as multibit"
line.long 0x10 "OBSCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for OBS Clkout Data should be loaded as multibit"
line.long 0x14 "TRCCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for TRC Clkout Data should be loaded as multibit"
group.long 0x40++0x17
line.long 0x00 "HSI_DIV_VAL,"
hexmask.long.word 0x00 0.--11. 1. "clkdiv,Divider value for HSI selected clock"
line.long 0x04 "CSIRX_DIV_VAL,"
hexmask.long.word 0x04 0.--11. 1. "clkdiv,Divider value for CSI Rx selected clock"
line.long 0x08 "MCUCLKOUT_DIV_VAL,"
hexmask.long.word 0x08 0.--11. 1. "clkdiv,Divider value for MCU Clkout selected clock"
line.long 0x0C "PMICCLKOUT_DIV_VAL,"
hexmask.long.word 0x0C 0.--11. 1. "clkdiv,Divider value for PMIC Clkout selected clock"
line.long 0x10 "OBSCLKOUT_DIV_VAL,"
hexmask.long.word 0x10 0.--11. 1. "clkdiv,Divider value for OBS Clkout selected clock"
line.long 0x14 "TRCCLKOUT_DIV_VAL,"
hexmask.long.word 0x14 0.--11. 1. "clkdiv,Divider value for TRC Clkout selected clock"
group.long 0x80++0x1B
line.long 0x00 "HSI_CLK_GATE,"
bitfld.long 0x00 0.--2. "gated,Clock gatring config for HSI" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x04 "CSIRX_CLK_GATE,"
bitfld.long 0x04 0.--2. "gated,Clock gatring config for CSI Rx" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x08 "MCUCLKOUT_CLK_GATE,"
bitfld.long 0x08 0.--2. "gated,Clock gatring config for MCU Clkout" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x0C "PMICCLKOUT_CLK_GATE,"
bitfld.long 0x0C 0.--2. "gated,Clock gatring config for PMIC Clkout Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x10 "OBSCLKOUT_CLK_GATE,"
bitfld.long 0x10 0.--2. "gated,Clock gatring config for OBS Clkout Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x14 "TRCCLKOUT_CLK_GATE,"
bitfld.long 0x14 0.--2. "gated,Clock gatring config for TRC Clkout Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x18 "DSS_CLK_GATE,"
bitfld.long 0x18 0.--2. "gated,Clock gatring config for DSP Subsystem System Clock Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
rgroup.long 0xC0++0x17
line.long 0x00 "HSI_CLK_STATUS,"
hexmask.long.byte 0x00 8.--15. 1. "currdivider,Status shows the current divider value choosen for CortexR5 Clock"
newline
hexmask.long.byte 0x00 0.--7. 1. "clkinuse,Status shows the source clock slected for CortexR5 Clock"
line.long 0x04 "CSIRX_CLK_STATUS,"
hexmask.long.byte 0x04 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSI Clock"
newline
hexmask.long.byte 0x04 0.--7. 1. "clkinuse,Status shows the source clock slected for HSI Clock"
line.long 0x08 "MCUCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x08 8.--15. 1. "currdivider,Status shows the current divider value choosen for CSI Rx Clock"
newline
hexmask.long.byte 0x08 0.--7. 1. "clkinuse,Status shows the source clock slected for CSI Rx Clock"
line.long 0x0C "PMICCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x0C 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCU Clkout Clock"
newline
hexmask.long.byte 0x0C 0.--7. 1. "clkinuse,Status shows the source clock slected for MCU Clkout Clock"
line.long 0x10 "OBSCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x10 8.--15. 1. "currdivider,Status shows the current divider value choosen for PMIC Clkout Clock"
newline
hexmask.long.byte 0x10 0.--7. 1. "clkinuse,Status shows the source clock slected for PMIC Clkout Clock"
line.long 0x14 "TRCCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x14 8.--15. 1. "currdivider,Status shows the current divider value choosen for PMIC Clkout Clock"
newline
hexmask.long.byte 0x14 0.--7. 1. "clkinuse,Status shows the source clock slected for PMIC Clkout Clock"
group.long 0x100++0x0F
line.long 0x00 "WARM_RESET_CONFIG,"
bitfld.long 0x00 16.--18. "wdog_rst_en,Data should be loaded as multibit" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "sw_rst,Data should be loaded as multibit" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "pad_bypass,Bypass the Warm reset from Pad Input Data should be loaded as multibit" "Reset is not asserted by SW (multibit 000),?,?,?,?,?,?,Reset is asserted by SW (multibit 111)"
line.long 0x04 "SYS_RST_CAUSE,"
bitfld.long 0x04 0.--4. "cause,System Reset Cause register" "?,?,?,?,?,?,?,?,External Pad reset,POR reset,Warm reset due to MSS_WDT,?,Warm reset due to TOP_RMC,?,?,?,?,?,?,?,?,?,?,?,Warm reset due to HSM_WDT,?..."
line.long 0x08 "SYS_RST_CAUSE_CLR,"
bitfld.long 0x08 0. "clear,Write pulse bit field: System Reset Cause register Clear" "0,1"
line.long 0x0C "DSS_RST_CTRL,"
bitfld.long 0x0C 0.--2. "assert,Reset control for DSP Subsystem Data should be loaded as multibit" "Reset is not asserted by SW (multibit 000),?,?,?,?,?,?,Reset is asserted by SW (multibit 111)"
group.long 0x204++0x23
line.long 0x00 "RS232_BITINTERVAL,"
line.long 0x04 "LVDS_PAD_CTRL0,"
line.long 0x08 "LVDS_PAD_CTRL1,"
line.long 0x0C "DFT_DMLED_EXEC,"
line.long 0x10 "DFT_DMLED_STATUS,"
line.long 0x14 "LIMP_MODE_EN,"
bitfld.long 0x14 8.--10. "force_rcclk_en,Force the RCCLK on when limp mode is detected" "The RCCLK will not be forced on when limp mode..,?,?,?,?,?,?,The RCCLK will be forced on when limp mode is.."
newline
bitfld.long 0x14 4.--6. "ccca_en,Enable MSS_CCCA Error to generate Limp mode" "MSS_CCCA Error will not generate Limp mode..,?,?,?,?,?,?,MSS_CCCA Error will generate Limp mode (multibit.."
newline
bitfld.long 0x14 0.--2. "dcca_en,Enable MSS_DCCA Error to generate Limp mode" "MSS_DCCA Error will not generate Limp mode..,?,?,?,?,?,?,MSS_DCCA Error will generate Limp mode (multibit.."
line.long 0x18 "PMICCLKOUT_DCDC_CTRL,"
hexmask.long.byte 0x18 16.--23. 1. "max_freq_thr,PMIC Clockout DCDC Maximum Frequency Threshold"
newline
hexmask.long.byte 0x18 8.--15. 1. "min_freq_thr,PMIC Clockout DCDC Minimum Frequency Threshold"
newline
bitfld.long 0x18 4.--6. "reset_assert,Reset control for PMIC DCDC Data should be loaded as multibit" "Reset is not asserted by SW (multibit 000),?,?,?,?,?,?,Reset is asserted by SW (multibit 111)"
newline
bitfld.long 0x18 2. "freq_acc_mode,PMIC Clockout DCDC Freq Acc Enable" "0,1"
newline
bitfld.long 0x18 1. "dither_en,PMIC Clockout DCDC Clock Dither Enable" "0,1"
newline
bitfld.long 0x18 0. "dcdc_clk_en,PMIC Clockout DCDC Clock Enable" "0,1"
line.long 0x1C "PMICCLKOUT_DCDC_SLOPE,"
hexmask.long 0x1C 0.--26. 1. "slope_val,PMIC Clockout DCDC Slope Config Value"
line.long 0x20 "RCOSC32K_CTRL,"
bitfld.long 0x20 0.--2. "stoposc,Stop 32KHz RCOSC" "0,1,2,3,4,5,6,7"
group.long 0x400++0x5F
line.long 0x00 "PLL_CORE_PWRCTRL,"
bitfld.long 0x00 5. "PONIN,ON/OFF control of the weak power switch digital" "0,1"
newline
bitfld.long 0x00 4. "PGOODIN,ON/OFF control of the strong power switch digital" "0,1"
newline
bitfld.long 0x00 3. "RET,Save/Restore control for Retention mode" "0,1"
newline
bitfld.long 0x00 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
newline
bitfld.long 0x00 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins" "0,1"
newline
bitfld.long 0x00 0. "OFFMODE,Used to switch OFF the logic on VDDA" "0,1"
line.long 0x04 "PLL_CORE_CLKCTRL,"
bitfld.long 0x04 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK" "0,1"
newline
bitfld.long 0x04 30. "ENSSC,Controls Clock Spreading" "0,1"
newline
bitfld.long 0x04 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO" "synchronously disables CLKDCOLDO,synchronously enables CLKDCOLDO"
newline
bitfld.long 0x04 24.--28. "NWELLTRIM,Trim value for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 23. "IDLE,Sets PLL to Idle mode" "When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL.."
newline
bitfld.long 0x04 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module" "0,1"
newline
bitfld.long 0x04 21. "STBYRET,Standby retention control" "prepares ADPLLLJ for relock when out of..,prepares ADPLLLJ for retention by gating all the.."
newline
bitfld.long 0x04 20. "CLKOUTEN,CLKOUT enable or disable" "synchronously disables CLKOUT,synchronously enables CLKOUT"
newline
bitfld.long 0x04 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO" "synchronously disables CLKOUTLDO,synchronously enables CLKOUTLDO"
newline
bitfld.long 0x04 18. "ULOWCLKEN,Select CLKOUT source in bypass" "When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1),When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW"
newline
bitfld.long 0x04 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p" "0,1"
newline
bitfld.long 0x04 16. "M2PWDNZ,M2 divider power down mode" "Asynchronous power down for M2 divider,M2 divider is functional"
newline
bitfld.long 0x04 14. "STOPMODE,When in Lossclk/Stbyret" "Limp mode,Stopmode"
newline
bitfld.long 0x04 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector" "Reserved,?,HS2,Reserved,HS1,Reserved,?..."
newline
bitfld.long 0x04 8. "RELAXED_LOCK,Decides when FREQLOCK asserted" "FREQLOCK asserted when DC frequency error less..,FREQLOCK asserted when DC frequency error less.."
newline
bitfld.long 0x04 1. "SSCTYPE,SSC Type" "0,1"
newline
bitfld.long 0x04 0. "TINTZ,PLL core soft reset" "0,1"
line.long 0x08 "PLL_CORE_TENABLE,"
bitfld.long 0x08 0. "TENABLE,M N" "0,1"
line.long 0x0C "PLL_CORE_TENABLEDIV,"
bitfld.long 0x0C 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
line.long 0x10 "PLL_CORE_M2NDIV,"
hexmask.long.byte 0x10 16.--22. 1. "M2,Post-divider is REGM2"
newline
hexmask.long.byte 0x10 0.--7. 1. "N,Pre-divider is REGN+1"
line.long 0x14 "PLL_CORE_MN2DIV,"
bitfld.long 0x14 16.--19. "N2,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 0.--11. 1. "M,Feedback Multiplier is REGM"
line.long 0x18 "PLL_CORE_FRACDIV,"
hexmask.long.byte 0x18 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance"
newline
hexmask.long.tbyte 0x18 0.--17. 1. "FRACTIONALM,Fractional part of the M divider"
line.long 0x1C "PLL_CORE_BWCTRL,"
bitfld.long 0x1C 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
newline
bitfld.long 0x1C 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth" "decrease BW,increase BW"
line.long 0x20 "PLL_CORE_FRACCTRL,"
bitfld.long 0x20 31. "DOWNSPREAD,Controls frequency spread" "enables both side frequency spread about the..,enables low frequency spread only"
newline
bitfld.long 0x20 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
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bitfld.long 0x20 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
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hexmask.long.tbyte 0x20 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
line.long 0x24 "PLL_CORE_STATUS,"
bitfld.long 0x24 31. "PONOUT,Status of the weak power-switch" "indicates the/OFF status of the weak..,ndicates the ON status of the weak power-switch.."
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bitfld.long 0x24 30. "PGOODOUT,Status of the strong power-switch" "indicates the/OFF status of the strong..,ndicates the ON status of the strong.."
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bitfld.long 0x24 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down" "0,1"
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bitfld.long 0x24 28. "RECAL_BSTATUS3,Recalibration status flag" "0,1"
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bitfld.long 0x24 27. "RECAL_OPPIN,Recalibration status flag" "0,1"
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bitfld.long 0x24 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x24 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
newline
bitfld.long 0x24 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
newline
bitfld.long 0x24 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
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bitfld.long 0x24 7. "STBYRETACK,Standby and retention status" "indicates to SOC that all internal clocks in..,indicates to SOC that all internal clocks in.."
newline
bitfld.long 0x24 6. "LOSSREF,Reference input loss" "0,1"
newline
bitfld.long 0x24 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN" "CLKOUT gating completed,CLKOUT enabling completed"
newline
bitfld.long 0x24 4. "LOCK2,ADPLL internal loop lock status" "0,1"
newline
bitfld.long 0x24 3. "M2CHANGEACK,Acknowledge for change to M2 divider" "0,1"
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bitfld.long 0x24 2. "SSCACK,Spread Spectrum status" "Spread-spectrum Clocking is disabled on output..,Spread-spectrum Clocking is enabled on output.."
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bitfld.long 0x24 1. "HIGHJITTER,1 indicates jitter" "0,1"
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bitfld.long 0x24 0. "BYPASS,Bypass status signal" "0,1"
line.long 0x28 "PLL_CORE_HSDIVIDER,"
rbitfld.long 0x28 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
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rbitfld.long 0x28 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
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bitfld.long 0x28 2. "TENABLEDIV,Tenable Div" "0,1"
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bitfld.long 0x28 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x28 0. "BYPASS,HSDIVIDER Bypass" "0,1"
line.long 0x2C "PLL_CORE_HSDIVIDER_CLKOUT0,"
bitfld.long 0x2C 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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rbitfld.long 0x2C 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x2C 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x2C 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x2C 0.--4. "DIV,DPLL post-divider factor M4 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x30 "PLL_CORE_HSDIVIDER_CLKOUT1,"
bitfld.long 0x30 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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rbitfld.long 0x30 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x30 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x30 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x30 0.--4. "DIV,DPLL post-divider factor M5 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "PLL_CORE_HSDIVIDER_CLKOUT2,"
bitfld.long 0x34 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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rbitfld.long 0x34 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x34 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x34 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x34 0.--4. "DIV,DPLL post-divider factor M6 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "PLL_CORE_HSDIVIDER_CLKOUT3,"
bitfld.long 0x38 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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rbitfld.long 0x38 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x38 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x38 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x38 0.--4. "DIV,DPLL post-divider factor M7 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "MSS_CR5_CLK_SRC_SEL,"
hexmask.long.word 0x3C 0.--11. 1. "clksrcsel,Select line for selecting source clock for MSS Coretex R5 and System bus Clock"
line.long 0x40 "MSS_CR5_DIV_VAL,"
hexmask.long.word 0x40 0.--11. 1. "clkdiv,Divider value for Cortex R5 selected clock"
line.long 0x44 "SYS_CLK_DIV_VAL,"
hexmask.long.word 0x44 0.--11. 1. "clkdiv,Divider value for System Clock selected clock"
line.long 0x48 "MSS_CR5_CLK_GATE,"
bitfld.long 0x48 0.--2. "gated,Only for debug- Functionality not guaranteed Clock gating config for MSS Coretex R5" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x4C "SYS_CLK_GATE,"
bitfld.long 0x4C 0.--2. "gated,Only for debug- Functionality not guaranteed Clock gating config for System Clock Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x50 "SYS_CLK_STATUS,"
hexmask.long.byte 0x50 8.--15. 1. "currdivider,Status shows the current divider value choosen for Sys Clock"
line.long 0x54 "MSS_CR5_CLK_STATUS,"
hexmask.long.byte 0x54 8.--15. 1. "currdivider,Status shows the current divider value choosen for CortexR5 Clock"
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hexmask.long.byte 0x54 0.--7. 1. "clkinuse,Status shows the source clock slected for CortexR5 Clock"
line.long 0x58 "PLL_CORE_RSTCTRL,"
bitfld.long 0x58 0.--2. "assert,SW Reset override for the PLL" "0,1,2,3,4,5,6,7"
line.long 0x5C "PLL_CORE_HSDIVIDER_RSTCTRL,"
bitfld.long 0x5C 0.--2. "assert,SW Reset override for the HSDIVIDER" "0,1,2,3,4,5,6,7"
group.long 0x800++0x87
line.long 0x00 "PLL_DSP_PWRCTRL,"
bitfld.long 0x00 5. "PONIN,ON/OFF control of the weak power switch digital" "0,1"
newline
bitfld.long 0x00 4. "PGOODIN,ON/OFF control of the strong power switch digital" "0,1"
newline
bitfld.long 0x00 3. "RET,Save/Restore control for Retention mode" "0,1"
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bitfld.long 0x00 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
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bitfld.long 0x00 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins" "0,1"
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bitfld.long 0x00 0. "OFFMODE,Used to switch OFF the logic on VDDA" "0,1"
line.long 0x04 "PLL_DSP_CLKCTRL,"
bitfld.long 0x04 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK" "0,1"
newline
bitfld.long 0x04 30. "ENSSC,Controls Clock Spreading" "0,1"
newline
bitfld.long 0x04 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO" "synchronously disables CLKDCOLDO,synchronously enables CLKDCOLDO"
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bitfld.long 0x04 24.--28. "NWELLTRIM,Trim value for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 23. "IDLE,Sets PLL to Idle mode" "When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL.."
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bitfld.long 0x04 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module" "0,1"
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bitfld.long 0x04 21. "STBYRET,Standby retention control" "prepares ADPLLLJ for relock when out of..,prepares ADPLLLJ for retention by gating all the.."
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bitfld.long 0x04 20. "CLKOUTEN,CLKOUT enable or disable" "synchronously disables CLKOUT,synchronously enables CLKOUT"
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bitfld.long 0x04 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO" "synchronously disables CLKOUTLDO,synchronously enables CLKOUTLDO"
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bitfld.long 0x04 18. "ULOWCLKEN,Select CLKOUT source in bypass" "When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1),When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW"
newline
bitfld.long 0x04 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p" "0,1"
newline
bitfld.long 0x04 16. "M2PWDNZ,M2 divider power down mode" "Asynchronous power down for M2 divider,M2 divider is functional"
newline
bitfld.long 0x04 14. "STOPMODE,When in Lossclk/Stbyret" "Limp mode,Stopmode"
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bitfld.long 0x04 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector" "Reserved,?,HS2,Reserved,HS1,Reserved,?..."
newline
bitfld.long 0x04 8. "RELAXED_LOCK,Decides when FREQLOCK asserted" "FREQLOCK asserted when DC frequency error less..,FREQLOCK asserted when DC frequency error less.."
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bitfld.long 0x04 1. "SSCTYPE,SSC Type" "0,1"
newline
bitfld.long 0x04 0. "TINTZ,PLL core soft reset" "0,1"
line.long 0x08 "PLL_DSP_TENABLE,"
bitfld.long 0x08 0. "TENABLE,M N" "0,1"
line.long 0x0C "PLL_DSP_TENABLEDIV,"
bitfld.long 0x0C 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
line.long 0x10 "PLL_DSP_M2NDIV,"
hexmask.long.byte 0x10 16.--22. 1. "M2,Post-divider is REGM2"
newline
hexmask.long.byte 0x10 0.--7. 1. "N,Pre-divider is REGN+1"
line.long 0x14 "PLL_DSP_MN2DIV,"
bitfld.long 0x14 16.--19. "N2,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 0.--11. 1. "M,Feedback Multiplier is REGM"
line.long 0x18 "PLL_DSP_FRACDIV,"
hexmask.long.byte 0x18 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance"
newline
hexmask.long.tbyte 0x18 0.--17. 1. "FRACTIONALM,Fractional part of the M divider"
line.long 0x1C "PLL_DSP_BWCTRL,"
bitfld.long 0x1C 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
newline
bitfld.long 0x1C 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth" "decrease BW,increase BW"
line.long 0x20 "PLL_DSP_FRACCTRL,"
bitfld.long 0x20 31. "DOWNSPREAD,Controls frequency spread" "enables both side frequency spread about the..,enables low frequency spread only"
newline
bitfld.long 0x20 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x20 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
newline
bitfld.long 0x20 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
newline
hexmask.long.tbyte 0x20 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
line.long 0x24 "PLL_DSP_STATUS,"
bitfld.long 0x24 31. "PONOUT,Status of the weak power-switch" "indicates the/OFF status of the weak..,ndicates the ON status of the weak power-switch.."
newline
bitfld.long 0x24 30. "PGOODOUT,Status of the strong power-switch" "indicates the/OFF status of the strong..,ndicates the ON status of the strong.."
newline
bitfld.long 0x24 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down" "0,1"
newline
bitfld.long 0x24 28. "RECAL_BSTATUS3,Recalibration status flag" "0,1"
newline
bitfld.long 0x24 27. "RECAL_OPPIN,Recalibration status flag" "0,1"
newline
bitfld.long 0x24 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
newline
bitfld.long 0x24 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
newline
bitfld.long 0x24 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
newline
bitfld.long 0x24 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
newline
bitfld.long 0x24 7. "STBYRETACK,Standby and retention status" "indicates to SOC that all internal clocks in..,indicates to SOC that all internal clocks in.."
newline
bitfld.long 0x24 6. "LOSSREF,Reference input loss" "0,1"
newline
bitfld.long 0x24 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN" "CLKOUT gating completed,CLKOUT enabling completed"
newline
bitfld.long 0x24 4. "LOCK2,ADPLL internal loop lock status" "0,1"
newline
bitfld.long 0x24 3. "M2CHANGEACK,Acknowledge for change to M2 divider" "0,1"
newline
bitfld.long 0x24 2. "SSCACK,Spread Spectrum status" "Spread-spectrum Clocking is disabled on output..,Spread-spectrum Clocking is enabled on output.."
newline
bitfld.long 0x24 1. "HIGHJITTER,1 indicates jitter" "0,1"
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bitfld.long 0x24 0. "BYPASS,Bypass status signal" "0,1"
line.long 0x28 "PLL_DSP_HSDIVIDER,"
rbitfld.long 0x28 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
newline
rbitfld.long 0x28 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
newline
bitfld.long 0x28 2. "TENABLEDIV,Tenable Div" "0,1"
newline
bitfld.long 0x28 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x28 0. "BYPASS,HSDIVIDER Bypass" "0,1"
line.long 0x2C "PLL_DSP_HSDIVIDER_CLKOUT0,"
bitfld.long 0x2C 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
newline
rbitfld.long 0x2C 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x2C 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x2C 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x2C 0.--4. "DIV,DPLL post-divider factor M4 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x30 "PLL_DSP_HSDIVIDER_CLKOUT1,"
bitfld.long 0x30 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
newline
rbitfld.long 0x30 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
newline
bitfld.long 0x30 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x30 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
newline
bitfld.long 0x30 0.--4. "DIV,DPLL post-divider factor M5 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "PLL_DSP_HSDIVIDER_CLKOUT2,"
bitfld.long 0x34 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
newline
rbitfld.long 0x34 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
newline
bitfld.long 0x34 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x34 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
newline
bitfld.long 0x34 0.--4. "DIV,DPLL post-divider factor M6 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "PLL_DSP_HSDIVIDER_CLKOUT3,"
bitfld.long 0x38 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
newline
rbitfld.long 0x38 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
newline
bitfld.long 0x38 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x38 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
newline
bitfld.long 0x38 0.--4. "DIV,DPLL post-divider factor M7 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "PLL_PER_PWRCTRL,"
bitfld.long 0x3C 5. "PONIN,ON/OFF control of the weak power switch digital" "0,1"
newline
bitfld.long 0x3C 4. "PGOODIN,ON/OFF control of the strong power switch digital" "0,1"
newline
bitfld.long 0x3C 3. "RET,Save/Restore control for Retention mode" "0,1"
newline
bitfld.long 0x3C 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
newline
bitfld.long 0x3C 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins" "0,1"
newline
bitfld.long 0x3C 0. "OFFMODE,Used to switch OFF the logic on VDDA" "0,1"
line.long 0x40 "PLL_PER_CLKCTRL,"
bitfld.long 0x40 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK" "0,1"
newline
bitfld.long 0x40 30. "ENSSC,Controls Clock Spreading" "0,1"
newline
bitfld.long 0x40 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO" "synchronously disables CLKDCOLDO,synchronously enables CLKDCOLDO"
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bitfld.long 0x40 24.--28. "NWELLTRIM,Trim value for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 23. "IDLE,Sets PLL to Idle mode" "When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL.."
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bitfld.long 0x40 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module" "0,1"
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bitfld.long 0x40 21. "STBYRET,Standby retention control" "prepares ADPLLLJ for relock when out of..,prepares ADPLLLJ for retention by gating all the.."
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bitfld.long 0x40 20. "CLKOUTEN,CLKOUT enable or disable" "synchronously disables CLKOUT,synchronously enables CLKOUT"
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bitfld.long 0x40 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO" "synchronously disables CLKOUTLDO,synchronously enables CLKOUTLDO"
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bitfld.long 0x40 18. "ULOWCLKEN,Select CLKOUT source in bypass" "When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1),When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW"
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bitfld.long 0x40 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p" "0,1"
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bitfld.long 0x40 16. "M2PWDNZ,M2 divider power down mode" "Asynchronous power down for M2 divider,M2 divider is functional"
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bitfld.long 0x40 14. "STOPMODE,When in Lossclk/Stbyret" "Limp mode,Stopmode"
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bitfld.long 0x40 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector" "Reserved,?,HS2,Reserved,HS1,Reserved,?..."
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bitfld.long 0x40 8. "RELAXED_LOCK,Decides when FREQLOCK asserted" "FREQLOCK asserted when DC frequency error less..,FREQLOCK asserted when DC frequency error less.."
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bitfld.long 0x40 1. "SSCTYPE,SSC Type" "0,1"
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bitfld.long 0x40 0. "TINTZ,PLL core soft reset" "0,1"
line.long 0x44 "PLL_PER_TENABLE,"
bitfld.long 0x44 0. "TENABLE,M N" "0,1"
line.long 0x48 "PLL_PER_TENABLEDIV,"
bitfld.long 0x48 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
line.long 0x4C "PLL_PER_M2NDIV,"
hexmask.long.byte 0x4C 16.--22. 1. "M2,Post-divider is REGM2"
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hexmask.long.byte 0x4C 0.--7. 1. "N,Pre-divider is REGN+1"
line.long 0x50 "PLL_PER_MN2DIV,"
bitfld.long 0x50 16.--19. "N2,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x50 0.--11. 1. "M,Feedback Multiplier is REGM"
line.long 0x54 "PLL_PER_FRACDIV,"
hexmask.long.byte 0x54 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance"
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hexmask.long.tbyte 0x54 0.--17. 1. "FRACTIONALM,Fractional part of the M divider"
line.long 0x58 "PLL_PER_BWCTRL,"
bitfld.long 0x58 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
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bitfld.long 0x58 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth" "decrease BW,increase BW"
line.long 0x5C "PLL_PER_FRACCTRL,"
bitfld.long 0x5C 31. "DOWNSPREAD,Controls frequency spread" "enables both side frequency spread about the..,enables low frequency spread only"
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bitfld.long 0x5C 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x5C 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
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bitfld.long 0x5C 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
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hexmask.long.tbyte 0x5C 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
line.long 0x60 "PLL_PER_STATUS,"
bitfld.long 0x60 31. "PONOUT,Status of the weak power-switch" "indicates the/OFF status of the weak..,ndicates the ON status of the weak power-switch.."
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bitfld.long 0x60 30. "PGOODOUT,Status of the strong power-switch" "indicates the/OFF status of the strong..,ndicates the ON status of the strong.."
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bitfld.long 0x60 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down" "0,1"
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bitfld.long 0x60 28. "RECAL_BSTATUS3,Recalibration status flag" "0,1"
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bitfld.long 0x60 27. "RECAL_OPPIN,Recalibration status flag" "0,1"
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bitfld.long 0x60 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x60 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x60 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
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bitfld.long 0x60 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
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bitfld.long 0x60 7. "STBYRETACK,Standby and retention status" "indicates to SOC that all internal clocks in..,indicates to SOC that all internal clocks in.."
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bitfld.long 0x60 6. "LOSSREF,Reference input loss" "0,1"
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bitfld.long 0x60 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN" "CLKOUT gating completed,CLKOUT enabling completed"
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bitfld.long 0x60 4. "LOCK2,ADPLL internal loop lock status" "0,1"
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bitfld.long 0x60 3. "M2CHANGEACK,Acknowledge for change to M2 divider" "0,1"
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bitfld.long 0x60 2. "SSCACK,Spread Spectrum status" "Spread-spectrum Clocking is disabled on output..,Spread-spectrum Clocking is enabled on output.."
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bitfld.long 0x60 1. "HIGHJITTER,1 indicates jitter" "0,1"
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bitfld.long 0x60 0. "BYPASS,Bypass status signal" "0,1"
line.long 0x64 "PLL_PER_HSDIVIDER,"
rbitfld.long 0x64 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
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rbitfld.long 0x64 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
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bitfld.long 0x64 2. "TENABLEDIV,Tenable Div" "0,1"
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bitfld.long 0x64 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x64 0. "BYPASS,HSDIVIDER Bypass" "0,1"
line.long 0x68 "PLL_PER_HSDIVIDER_CLKOUT0,"
bitfld.long 0x68 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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rbitfld.long 0x68 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x68 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x68 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x68 0.--4. "DIV,DPLL post-divider factor M4 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x6C "PLL_PER_HSDIVIDER_CLKOUT1,"
bitfld.long 0x6C 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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rbitfld.long 0x6C 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x6C 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x6C 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x6C 0.--4. "DIV,DPLL post-divider factor M5 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x70 "PLL_PER_HSDIVIDER_CLKOUT2,"
bitfld.long 0x70 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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rbitfld.long 0x70 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x70 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x70 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x70 0.--4. "DIV,DPLL post-divider factor M6 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x74 "PLL_PER_HSDIVIDER_CLKOUT3,"
bitfld.long 0x74 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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rbitfld.long 0x74 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x74 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x74 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x74 0.--4. "DIV,DPLL post-divider factor M7 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x78 "PLL_DSP_RSTCTRL,"
bitfld.long 0x78 0.--2. "assert,SW Reset override for the PLL" "0,1,2,3,4,5,6,7"
line.long 0x7C "PLL_DSP_HSDIVIDER_RSTCTRL,"
bitfld.long 0x7C 0.--2. "assert,SW Reset override for the HSDIVIDER" "0,1,2,3,4,5,6,7"
line.long 0x80 "PLL_PER_RSTCTRL,"
bitfld.long 0x80 0.--2. "assert,SW Reset override for the PLL" "0,1,2,3,4,5,6,7"
line.long 0x84 "PLL_PER_HSDIVIDER_RSTCTRL,"
bitfld.long 0x84 0.--2. "assert,SW Reset override for the HSDIVIDER" "0,1,2,3,4,5,6,7"
group.long 0xC00++0x13
line.long 0x00 "ANA_REG_CLK_CTRL_REG1_XO_SLICER,"
bitfld.long 0x00 31. "OSC_CLKOUT_EN,OSC_CLKOUT Enable Enables the Slicer clock to drive the OSC_CLKOUT output buffer" "Functional Reset,Clock Enabled"
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bitfld.long 0x00 29.--30. "OSC_CLKOUT_FREQ_SEL,OSC_CLKOUT Frequency Selection Selects the output frequency as a division of the XTAL (or externally driven CLKP) frequency" "Functional Reset,?,XTAL/1,XTAL/4"
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bitfld.long 0x00 28. "OSC_CLKOUT_CLRZ_DIV,OSC_CLKOUT Divider ClearZ This active low signal permits the output frequency dividers to be properly cleared before enabling" "All dividers cleared,Functional Reset"
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bitfld.long 0x00 24.--27. "OSC_CLKOUT_DRV,OSC_CLKOUT Drive This bit controls the drive strength of the OSC_CLKOUT buffer" "No Test Output Hi-Z Output Drive Ctrl =..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Functional Reset"
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hexmask.long.word 0x00 13.--23. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x00 12. "XTAL_DETECT_XO_SLICER,XTAL Detect Enable This bit connects a pullup and sense circuitry to CLKM to detect the presence or absence of a crystal" "Functional Reset,XTAL sense function enabled (pullup and sense.."
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bitfld.long 0x00 11. "SLICER_DCCPL_XO_SLICER,Slicer DC-Coupled Mode" "Functional Reset,DC-couple CLKP to internal slicer to CLKP"
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bitfld.long 0x00 10. "SLICER_HIPWR_XO_SLICER,Slicer High-power Mode This bit bypasses the input clock slicer current-starving/filtering circuitry to increase gain and reduce device phase-noise at the expense of power and reduced supply noise rejection" "Functional Reset,High-power/high-speed test mode"
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bitfld.long 0x00 9. "FASTCHARGEZ_BIAS_XO_SLICER,Bias Fast-charge Enable (Active Low) This bit bypasses the RC filtering on the XOSC/SLICER Bias to permit more rapid power-up" "Bias fast-charge,Functional Reset"
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bitfld.long 0x00 4.--8. "XOSC_DRIVE_XO_SLICER,Crystal Oscillator Output Drive Binary-weighted oscillator drive control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--3. "RTRIM_BIAS_XO_SLICER,Crystal Oscillator and Slicer Bias RTrim Binary-weighted bias control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ANA_REG_CLK_CTRL_REG1_CLKTOP,"
hexmask.long 0x04 3.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x04 2. "ENABLE_XOSC,Enable Crystal Oscillator" "Disabled,Functional Reset"
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bitfld.long 0x04 1. "ENABLE_SLICER_CLKP,Enable CLKP Input Slicer" "Disabled,Functional Reset"
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bitfld.long 0x04 0. "ENABLE_BIAS_XO_SLICER,Enable Bias for Crystal Oscillator and Slicer" "Disabled,Functional Reset"
line.long 0x08 "ANA_REG_CLK_CTRL_REG2_CLKTOP,"
bitfld.long 0x08 31. "CTRL_DC_BIST_BUFEN,Disable for CLK_TOP DC BIST BUFFER" "Functional Reset,CLK TOP DC BIST BUFFER DISABLED"
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hexmask.long 0x08 0.--30. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
line.long 0x0C "ANA_REG_CLK_CTRL_REG1_LDO_CLKTOP,"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED1,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x0C 7. "CLK_BIST_DISABLE_LDO,DC BIST Disable for LDO" "Functional Reset,DC BIST Disabled"
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bitfld.long 0x0C 1.--6. "RESERVED0,Reserved Reads return 0x0 and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 0. "EN_SLICER_LDO,Slicer LDO Enable" "Slicer LDO Disabled,Functional Reset"
line.long 0x10 "ANA_REG_CLK_CTRL_REG2_LDO_CLKTOP,"
hexmask.long.byte 0x10 24.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x10 20.--23. "BISTMUX_CTRL,SLICER LDO BIST MUX CONTROL (ONE HOT) Analog MUX enables to BIST output port" "HI-Z Output,VBG_0P9*10/9 =1.0 V,VDD18*0.5 = 0.9V,?,Functional Reset,?,?,?,Floating WARNING: Enabling more than one bit..,?..."
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bitfld.long 0x10 16.--19. "TESTMUX_CTRL,SLICER LDO TEST MUX CONTROL (ONE HOT) Analog MUX enables to test output port" "Functional Reset,0.6 * VLDO_OUT,VDD18*0.5 = 0.9V,?,VSSA,?,?,?,LDO Test Current (12.5uA) WARNING:..,?..."
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bitfld.long 0x10 13.--15. "TLOAD_CTRL,SLICER LDO TLOAD CONTROL updated description needed" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 12. "ENABLE_PMOS_PULLDOWN,SLICER LDO PMOS PULL DOWN ENABLE" "Functional Reset,Slicer LDO PMOS Pull Down enabled"
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bitfld.long 0x10 11. "SCPRT_IBIAS_CTRL,SLICER LDO SHORT CKT PROTECTION IBIAS CONTROL" "Functional Reset,2X Nominal short circuit bias with higher.."
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bitfld.long 0x10 8.--10. "LDO_BW_CTRL,SLICER LDO BANDWIDTH CONTROL need updated description" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 7. "EN_BYPASS,SLICER LDO BYPASS ENABLE" "Functional Reset,Slicer LDO Bypassed with external voltage"
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bitfld.long 0x10 6. "EN_SHRT_CKT,SLICER LDO SHORT CKT PROTECTION ENABLE" "Functional Reset,Slicer LDO Short Ckt Protection Enabled"
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bitfld.long 0x10 5. "EN_TEST_MODE,SLICER LDO TEST MODE ENABLE" "Functional Reset,Slicer LDO TEST MODE Enabled"
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bitfld.long 0x10 4. "ENZ_LOW_BW_CAP,SLICER LDO LOW BW MODE DISABLE" "Slicer LDO Low BW mode Disabled,Functional Reset"
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bitfld.long 0x10 0.--3. "LDO_VOUT_CTRL,SLICER LDO VOUT TRIM NEEDS updated description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xC18++0x2F
line.long 0x00 "ANA_REG_CLK_STATUS_REG,"
hexmask.long 0x00 1.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x00 0. "SLICER_LDO_SC_OUT,SLICER LDO SHORT CIRCUIT INDICATOR" "Normal operation,LDO Output Short Circuit Detected"
line.long 0x04 "ANA_REG_REFSYS_CTRL_REG_LOWV,"
bitfld.long 0x04 31. "RESERVED2,Reserved" "0,1"
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bitfld.long 0x04 27.--30. "FTRIM_3_0,Filter TRIM Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 26. "RESERVED1,<7> Unused" "0,1"
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bitfld.long 0x04 25. "IDIODE_EN,<6> Idiode Active Low Control --> Unused in TPR Reserved for AWR <0> - Enable <1> - Disable" "0,1"
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bitfld.long 0x04 24. "REFSYS_V2I_BYPASS_EN,<5> REFSYS V2I By-Pass Enable" "0,1"
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bitfld.long 0x04 23. "TX_TOP_IBIAS_EN,<4> TX TOP IBIAS EN--> Unused in TPR Reserved for AWR" "0,1"
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bitfld.long 0x04 22. "LODIST_IBIAS_EN,<3> LO DIST BIAS EN --> Unused in TPR Reserved for AWR" "0,1"
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bitfld.long 0x04 21. "CLKTOP_IBIAS_EN,<2> CLK TOP IBIAS EN" "0,1"
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bitfld.long 0x04 20. "V2I_STARTUP,<1> V2I Startup" "0,1"
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bitfld.long 0x04 19. "BGAP_ISW,<0> BGAP ISW STARTUP" "0,1"
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bitfld.long 0x04 14.--18. "IREF_TRIM_4_0,Default Resistor Trim for NOM LOT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 9.--13. "MAG_TRIM_4_0,Default Magnitude Trim for NOM LOT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 4.--8. "SLOPE_TRIM_4_0,Default Slope Trim for NOM LOT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 3. "REFSYS_PRE_CHARGE,REFSYS Pre Charge Control" "Functional Reset,Enable Pre Charge Block"
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bitfld.long 0x04 2. "REFSYS_CAP_SW_CTRLZ,REFSYS Cap Switch Control" "Functional Reset,Disconnect External Cap to Reference output"
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bitfld.long 0x04 1. "REFSYS_V2I_EN_CTRL,REFSYS Enable Control" "Disable V2I REFSYS,Functional Reset"
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bitfld.long 0x04 0. "REFSYS_BGAP_EN_CTRL,REFSYS Enable Control" "Disable REFSYS,Functional Reset"
line.long 0x08 "ANA_REG_REFSYS_TMUX_CTRL_LOWV,"
bitfld.long 0x08 31. "REFSYS_CTRL_8,REFSYS Test Mux Enable" "Functional Reset,TMUX Enabled"
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hexmask.long.word 0x08 16.--30. 1. "RESERVED1,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x08 15. "LO_IBIASP_20u,<15> LO IBG BIASP 20uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 14. "TX_IBIASP_20u,<14> TX IBG BIASP 20uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 13. "BYPASS_MIRR_VPBIAS,VPBIAS Control for IREF Gen Test Mode V2I By-Pass Feature" "0,1"
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bitfld.long 0x08 12. "I2V_SENSE,Sense Voltage from the BIST I2V cinversion of 20u and 6u bias current paths Sense voltage of 1V for BIST select<6> Sense voltage of 0.3V for BIST select<7>" "0,1"
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bitfld.long 0x08 11. "VSSA_REF,<11> VSSA REF (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 10. "IREFP_10UA,<10> IREFP 10uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 9. "IDIODEP_100U,<9> Idiode BIASP 100uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 8. "RESERVED4,Unused" "0,1"
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bitfld.long 0x08 7. "IBIASP_TS_6U,<7> IBG BIASP TS 6uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 6. "IBIASP_20U,<6> CLK IBG BIASP 20uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 5. "RESERVED3,Unused" "0,1"
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bitfld.long 0x08 4. "VBE_WEAK,<4> - VBE Weak (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 3. "RESERVED2,Unused" "0,1"
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bitfld.long 0x08 2. "VBG_1P22V,<2> - VBG 1.22V (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 1. "VREF_0P9V,<1> - VREF 0P9V (Cap Node) (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 0. "VREF_0P45V,<0> - VREF 0P45 (TMUX One-Hot)" "0,1"
line.long 0x0C "ANA_REG_REFSYS_SPARE_REG_LOWV,"
bitfld.long 0x0C 31. "ANALOGTEST_TMUX_ESD_CTRL,ANALOGTEST TMUX ESD CTRL in Pad-Frame (formerly RX_REFSYS_TMUX_SPARE_CTRL_LOWV<31> in AWR/IWR devices but RX does not exist in TPR)" "0,1"
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hexmask.long.word 0x0C 22.--30. 1. "REFSYS_SPARE_30_22,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x0C 21. "VDD_OV_RSET_EN,If asserted VDD_OV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 20. "VDD_UV_RSET_EN,If asserted VDD_UV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 19. "VDDA_OSC_UV_RSET_EN,If asserted VDDA_OSC_UV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 18. "VIOIN_UV_RSET_EN,If asserted VIOIN_UV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 16.--17. "VDD_OV_SR_SEL,Final level of VDD 1.2V VMON OV Reference Selection See definition in REFSYS_SPARE_REG<15:14>" "0,1,2,3"
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bitfld.long 0x0C 14.--15. "VDD_OV_IR_DROP_COMP_SEL,VDD 1.2V VMON OV Reference Selection Reference selection is dependent on REFSYS_SPARE_REG<17:16> programming If REFSYS_SPARE_REG<17:16> = 0x0" "Functional..,0.58V,0.57V,0.56V"
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bitfld.long 0x0C 13. "RESERVED1,Reserved Reserved in case VIOIN OV VMON and self test is ever implemented" "0,1"
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bitfld.long 0x0C 12. "VDDS_3P3V_UV_SELF_TEST_SEL,Enable VIOIN Strict UV VMON Self Test If Self-test mode is enabled VIOIN UV VMON reference is programmed as follows for REFSYS_SPARE_REG<3:2>" "Functional..,0.64V"
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bitfld.long 0x0C 11. "RESERVED0,Reserved Reserved in case VDDA_OSC OV VMON and self test is ever implemented" "0,1"
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bitfld.long 0x0C 10. "VDDA_OSC_UV_SELF_TEST_SEL,Enable VDDA_OSC Strict UV VMON Self Test If Self-test mode is enabled VDDA_OSC UV VMON reference is programmed as follows for REFSYS_SPARE_REG<5:4>" "Functional..,0.64V"
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bitfld.long 0x0C 9. "VDD_OV_SELF_TEST_SEL,Enable 1.2V VDD Strict OV VMON Self Test If Self-test mode is enabled VDD 1.2V VMON OV reference is programmed based on REFSYS_SPARE_REG<1:0> as follows: If REFSYS_SPARE_REG<7:6> = 0x0 REFSYS_SPARE_REG<1:0>" "Functional..,0.5V"
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bitfld.long 0x0C 8. "VDD_UV_SELF_TEST_SEL,Enable 1.2V VDD Strict UV VMON Self Test If Self-test mode is enabled VDD 1.2V VMON UV reference is programmed based on REFSYS_SPARE_REG<15:14> as follows: If REFSYS_SPARE_REG<17:16> = 0x0 REFSYS_SPARE_REG<15:14>" "Functional..,0.58V"
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bitfld.long 0x0C 6.--7. "VDD_SR_SEL,Final level of VDD 1.2V VMON UV Reference Selection See definition in REFSYS_SPARE_REG<1:0>" "0,1,2,3"
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bitfld.long 0x0C 4.--5. "VDDA_OSC_IR_DROP_COMP_SEL,VDDA_OSC UV VMON Reference Selection" "Functional..,0.54V,0.52V,0.5V"
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bitfld.long 0x0C 2.--3. "VDDS_3P3V_IR_DROP_COMP_SEL,VIOIN VMON UV Reference Selection" "Functional..,0.54V,0.52V,0.5V"
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bitfld.long 0x0C 0.--1. "VDD_IR_DROP_COMP_SEL,VDD 1.2V VMON UV Reference Selection Reference selection is dependent on REFSYS_SPARE_REG<7:6> programming If REFSYS_SPARE_REG<7:6> = 0x0" "Functional..,0.5V,0.49V,0.48V"
line.long 0x10 "ANA_REG_WU_CTRL_REG_LOWV,"
bitfld.long 0x10 31. "RESERVED0,Reserved Reads return 0x0 and writes have no effect" "0,1"
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bitfld.long 0x10 29.--30. "WU_SPARE_IN_2,WU Spare Control" "0,1,2,3"
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bitfld.long 0x10 28. "WU_VDD_OV_VMON_EN,WU VDD OV VMON Enable Control" "Functional Reset,VDD OV Detect Enabled"
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bitfld.long 0x10 27. "WU_VDD_UV_VMON_EN,WU VDD UV VMON Enable Control" "Functional Reset,VDD UV Detect Enabled"
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bitfld.long 0x10 26. "WU_VDDA_OSC_UV_VMON_EN,WU VDDA OSC UV VMON Enable Control" "Functional Reset,VDDA OSC UV Detect Enabled"
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bitfld.long 0x10 25. "WU_VDDS_3P3V_UV_VMON_EN,WU VDDS 3.3V UV VMON Enable Control" "Functional Reset,VDDS 3.3V UV Detect Enabled"
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bitfld.long 0x10 23.--24. "WU_SPARE_IN,WU Spare Control Change for 1642 ES2P0 Change Name : Newly added OR gates to provide options to bypass crude VDD DET (also refer to <11>) Bit <0> of this field when HIGH over rides the crude VDD_DET this control is using firmware Bit<0> of.." "0,1,2,3"
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bitfld.long 0x10 22. "WU_SUPP_DET_CTRL,WU VMON Detect Status Override Disable in Functional Test SOP" "VMON Det Status Override Disabled,Functional Reset"
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bitfld.long 0x10 21. "WU_VRAM_VMON_EN,WU VRAM VMON Enable Control" "SRAM UV Detect Disabled,Functional Reset"
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bitfld.long 0x10 20. "WU_SUPP_VMON_EN,WU VMON Enable Control" "VMON Control Disabled,Functional Reset"
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bitfld.long 0x10 19. "WU_XTAL_DLY_CTRL,Introduce additional delay for XTAL settling" "Functional Reset,Introduce additional delay as per WU-SEQ"
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bitfld.long 0x10 18. "WU_OV_DET_CTRL,WU Over Voltage Detect Control Changed for 1243 ES3P0 (Metal only change from 1642 ES2P0) Change Name : FW control of VDD OV DET EN" "OV Detect is Enabled,Functional Reset"
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bitfld.long 0x10 17. "WU_UV_DET_CTRL,WU Under Voltage Detect Control" "UV Detect is disabled,Functional Reset"
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bitfld.long 0x10 16. "XTAL_EN_OVERRIDE,XTAL EN Override (WU-SEQ) Control" "Functional Reset,Override XTAL Enable if disabled by default"
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bitfld.long 0x10 15. "WU_CPU_CLK_CTRL,WU CLK Control" "CLK Monitor Function in Dig Sequencer is..,Functional Reset"
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bitfld.long 0x10 11.--14. "INT_CLK_FREQ_SEL_3_0,WU Internal Clock (RCOSC) Frequency Select Bit<3> is used as override for VMON on Untrimmed devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 3.--10. 1. "INT_CLK_TRIM_7_0,WU lnternal Clock (RCOSC) Trim"
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bitfld.long 0x10 2. "INT_CLK_SW_SEL,WU Internal Clock (RCOSC) SW_SEL" "TBD,.."
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bitfld.long 0x10 1. "INT_CLK_STOP,WU Internal Clock (RCOSC) STOP" "Functional Reset,Internal CLK is OFF"
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bitfld.long 0x10 0. "INT_CLK_EN,WU Internal Clock (RCOSC) ENABLE" "Internal CLK Disabled,Functional Reset"
line.long 0x14 "ANA_REG_WU_TMUX_CTRL_LOWV,"
bitfld.long 0x14 31. "WU_TMUX_EN,WU TMUX Enable" "Functional Reset,TMUX Enabled"
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hexmask.long.word 0x14 21.--30. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x14 20. "VDDSINT18,VIOIN scaled supply for VIOIN Detect Scaling Factor: VIOIN*(52/90)" "0,1"
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bitfld.long 0x14 19. "SCALED_VDDA_OSC,Scaled VDDA_OSC supply for crude supply detect Scaling Factor: VDDA_OSC*(22/39)" "0,1"
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bitfld.long 0x14 18. "VFB_0P85V,Scaled VDD 1.2V used as reference for VDDA_OSC crude supply detect" "0,1"
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bitfld.long 0x14 17. "VDDA_OSC_UV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 16. "VDD_SR_UV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 15. "VT_DIG_SIG_OV,Test Mux Control" "0,1"
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bitfld.long 0x14 14. "VT_DIG_SIG_UV,Test Mux Control" "0,1"
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bitfld.long 0x14 13. "VT_ANA_SIG,Test Mux Control" "0,1"
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bitfld.long 0x14 12. "VDDA14_2_INT,Test Mux Control" "0,1"
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bitfld.long 0x14 11. "SCALED_VDDA_LVDS_1P8V_1P2,Test Mux Control" "0,1"
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bitfld.long 0x14 10. "VDDA14_INT,Test Mux Control" "0,1"
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bitfld.long 0x14 9. "VIOIN_UV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 8. "SCALED_VDDA18,Test Mux Control" "0,1"
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bitfld.long 0x14 7. "VREF_0P9V,Test Mux Control" "0,1"
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bitfld.long 0x14 6. "VDD_SR_OV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 5. "SCALED_VDDA_LVDS_1P8V,Test Mux Control" "0,1"
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bitfld.long 0x14 4. "SCALED_VIOIN,Test Mux Control" "0,1"
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bitfld.long 0x14 3. "VFB_0P6V,Test Mux Control" "0,1"
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bitfld.long 0x14 2. "SCALED_VDDS18,Test Mux Control" "0,1"
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bitfld.long 0x14 1. "SCALED_VIO3318,Test Mux Control" "0,1"
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bitfld.long 0x14 0. "SCALED_VDDA_OSC_UV,Test Mux Control" "0,1"
line.long 0x18 "ANA_REG_TW_CTRL_REG_LOWV,"
hexmask.long.word 0x18 20.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x18 15.--19. "RTRIM_TW_4_0,RTRIM value to TW routed to BIST MUX IN REFSYS for I2V" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 14. "ANA_TMUX_BUF_EN,TW ANA TMUX Buffer Enabled" "Functional Reset,ANA TMUX Buffer Enabled"
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bitfld.long 0x18 13. "ANA_TMUX_BUF_BYPASS,TW ANA TMUX Buffer Bypass" "Functional Reset,ANA TMUX Buffer By-pass Enabled"
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bitfld.long 0x18 12. "VIN_EXT_CTRL,TW VIN Control from External Source" "Functional Reset,External VIN Control Enabled"
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bitfld.long 0x18 11. "VREF_EXT_CTRL,TW VREF Control from External SOurce" "Functional Reset,External VREF Control Enabled"
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bitfld.long 0x18 10. "IFORCE_EXT_CTRL,TW Iforce Control from External Source" "Functional Reset,IFORCE Control Enabled"
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bitfld.long 0x18 9. "TS_SE_INP_BUF_EN,TW ADC TS SE Inp Buffer Enable" "Functional Reset,Input Buffer Enabled"
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bitfld.long 0x18 8. "TS_DIFF_INP_BUF_EN,TW ADC TS DIFF Inp Buffer Enable" "Input Buffer disabled,Functional Reset"
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bitfld.long 0x18 5.--7. "ADC_REF_SEL_2_0,TW ADC Reference Select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 4. "ADC_REF_BUF_EN,TW ADC Reference Buffer Enable" "Input Buffer disabled,Functional Reset"
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bitfld.long 0x18 3. "ADC_INP_BUF_EN,TW ADC Input Buffer Enable" "Input Buffer disabled,Functional Reset"
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bitfld.long 0x18 2. "ADC_RESET,TW ADC Reset (Active High)" "ADC Out of Reset,Functional Reset"
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bitfld.long 0x18 1. "ADC_START_CONV,TW ADC Start Conversion" "0,1"
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bitfld.long 0x18 0. "ADC_EN,TW ADC Control" "Functional Reset,ADC Enable"
line.long 0x1C "ANA_REG_TW_ANA_TMUX_CTRL_LOWV,"
bitfld.long 0x1C 31. "ANA_TEST_EN,TW ANA Test MUX Enabled" "Functional Reset,ANA TMUX Control Enabled"
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bitfld.long 0x1C 30. "CLK_TMUX_ESD_CTRL,CLK TMUX ESD CTRL in Pad-Frame" "0,1"
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hexmask.long.word 0x1C 19.--29. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x1C 18. "ATESTV_VSLDO,Enable Output of ATESTV of VSLDO" "0,1"
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bitfld.long 0x1C 17. "TMUX_BUF_OUT_EN,Enable Output of TMUX buffer" "0,1"
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bitfld.long 0x1C 16. "I2V_SENSE,I2V Sense Voltage of External IREF Forced" "0,1"
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bitfld.long 0x1C 15. "BIST_MUX_OUT_1P8V,BIST Mux output pre ADC input Buffer" "0,1"
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bitfld.long 0x1C 14. "ODP,Ibias current from Top Refsys for measurement on Test Pin" "0,1"
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bitfld.long 0x1C 13. "VBE_TS_WEAK,Single PNP Sense voltage for TSENSE selected" "0,1"
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bitfld.long 0x1C 12. "VBE_TS_STRONG,Multi PNP Sense voltage for TSENSE selected" "0,1"
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bitfld.long 0x1C 11. "DELVBE_BUFF_OUT,Difference TSENSE signal delVbe scaled and buffered for chosen TSENSE element" "0,1"
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bitfld.long 0x1C 10. "ADC_REF_BUF_OUT,ADC reference buffer out to Test Pin" "0,1"
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bitfld.long 0x1C 9. "ADC_BUF_OUT_1P8V,Buffered output of ADC inputs to GPADC" "0,1"
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bitfld.long 0x1C 8. "DC_BIST_BUF_INP_1P8V,DC BIST Buffered output of RX TX CLK LO (shorted on to this net)" "0,1"
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bitfld.long 0x1C 7. "VBE_W_BUFF,Buffered value of Weak PNP" "0,1"
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bitfld.long 0x1C 6. "VBE_S_BUFF,Buffered value of Strong PNP" "0,1"
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bitfld.long 0x1C 5. "PM_ANA_INP_5,CLK ANA Test Pin Mapped" "0,1"
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bitfld.long 0x1C 4. "PM_ANA_INP_4,RX ANA Test Mux Control" "0,1"
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bitfld.long 0x1C 3. "PM_ANA_INP_3,LODIST ANA Test Mux Control" "0,1"
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bitfld.long 0x1C 2. "PM_ANA_INP_2,TX PM ANA Test Mux Control" "0,1"
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bitfld.long 0x1C 1. "REFSYS_TEST_OUT_1P8V,Mux Output of Refsys Test Mux" "0,1"
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bitfld.long 0x1C 0. "WU_ANA_TEST_OUT_1P8V,Mux Output of WU Test Mux" "0,1"
line.long 0x20 "ANA_REG_TW_SPARE_LOWV,"
line.long 0x24 "ANA_REG_WU_MODE_REG_LOWV,"
hexmask.long 0x24 7.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x24 2.--6. "SOP_MODE_LAT_4_0,SOP Mode Latched Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 1. "TEST_MODE_DET_SYNC,Latched Output of Test Mode Detect SOP" "0,1"
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bitfld.long 0x24 0. "FUNC_TEST_DET_SYNC,Latched Output of Functional Test Mode SOP" "0,1"
line.long 0x28 "ANA_REG_WU_STATUS_REG_LOWV,"
hexmask.long.word 0x28 19.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x28 18. "VDDS_3P3V_UVDET_LAT,New in TPR: Latched Value of 3.3V IO UV Detect" "UV Detect Not Triggered,UV Detect has Triggered"
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bitfld.long 0x28 17. "VDDA_OSC_UVDET_LAT,Latched value of UV detect of LOMULT 1.8V supply (AWR devices) For TPR Latched Value of UV Detect of VDDA_OSC" "UV Detect Not Triggered,UV Detect has Triggered"
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bitfld.long 0x28 16. "SUPP_OK_APLLVCO18,Supp Detect output of APLL VCO 1.8V" "Supply Not detected,Supply Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 15. "HVMODE,HVMODE Status from VMON" "1.8V VIO,3.3V VIO"
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bitfld.long 0x28 14. "LIMP_MODE_STATUS,Ref CLK status at Wake-up" "REF CLK is present,REF CLK is absent and CPU CLK Switched to RCOSC"
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bitfld.long 0x28 13. "XTAL_DET_STATUS,XTAL Detect status at Wake-up" "XTAL absent,XTAL Present"
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bitfld.long 0x28 12. "RCOSC_CLK_STATUS,RCOSC status at Wake-up" "RCOSC CLK absent,RCOSC CLK Present"
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bitfld.long 0x28 11. "REF_CLK_STATUS,Ref CLK status at Wake-up" "REF CLK absent,REF CLK Present"
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bitfld.long 0x28 10. "SUPP_OK_VDDD18,Supp Detect output of LVDS 1.8V" "Supply Not detected,Supply Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 9. "SUPP_OK_SRAM12,UV Detect Status of SRAM" "UV Not Detected,UV Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 8. "SUPP_OK_RF2_14,Supp Detect output of RF2 1.4V Pin" "Supply Not detected,Supply Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 7. "SUPP_OK_RF14,Updated for 1642 ES2P0 Change name : Mux for VIN_13 OK in LDO bypass mode This output bit is always tied low Tied LO in TPR and AWR/IWR devices" "0,1"
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bitfld.long 0x28 6. "SUPP_OK_RF10,Updated for 1642 ES2P0 Change name : Mux for VIN_13 OK in LDO bypass mode When RF_LDO_BYPASS_EN = 1 this bit will be high when the supply is > 0.75 When RF_LDO_BYPASS_EN = 0 this bit will be high when the supply is > 1.05 Tied LO in TPR.." "0,1"
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bitfld.long 0x28 5. "SUPP_OK_IO33,Supp Detect output of IO 3.3V" "Supply Not detected,Supply Detected"
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bitfld.long 0x28 4. "SUPP_OK_IO18,Supp Detect output of IO 1.8V" "Supply Not detected,Supply Detected"
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bitfld.long 0x28 3. "SUPP_OK_CLK18,Supp Detect output of CLK 1.8V" "Supply Not detected,Supply Detected For TPR Crude detection of.."
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bitfld.long 0x28 2. "SUPP_OK_ANA18,Supp Detect output of Ana 1.8V Tied LO in TPR (unused VMON)" "Supply Not detected,Supply Detected"
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bitfld.long 0x28 1. "CORE_UVDET_LAT,Latched Value of UV Detect" "UV Detect Not Triggered,UV Detect has Triggered"
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bitfld.long 0x28 0. "CORE_OVDET_LAT,Latched Value of OV Detect" "OV Detect Not Triggered,OV Detect has Triggered"
line.long 0x2C "ANA_REG_WU_SPARE_OUT_LOWV,"
hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x2C 7. "CORE_UVDET_LOWV,UV Detect of Core Supply-Unlatched" "0,1"
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bitfld.long 0x2C 6. "CORE_OVDET_LOWV,OV Detect of Core Supply-Unlatched" "0,1"
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bitfld.long 0x2C 5. "INT_OSC_CTRL,Internal Oscillator Control" "0,1"
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bitfld.long 0x2C 4. "SUPPDET_OV_CTRL,Supply Detect Override Bit" "0,1"
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bitfld.long 0x2C 3. "HVMODE,Status of VIO supply" "0,1"
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bitfld.long 0x2C 2. "VDDS18DET,Status of 1.8V IO Bias Supply" "0,1"
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bitfld.long 0x2C 1. "VDDARF_DET,Status of 1.3V RF Supply" "0,1"
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bitfld.long 0x2C 0. "VDDCLK18DET,Status of 1.8V CLK Supply" "0,1"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_TPCC_A (MSS TPCCA Module Registers)"
base ad:0x3100000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
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bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
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bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
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bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
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bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
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bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
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bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
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bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
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hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
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hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
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bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
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bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
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bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
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bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
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bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
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bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
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bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
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bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
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bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
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bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
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bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
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bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
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bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
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bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
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bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
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bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
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bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
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bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
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bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
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bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
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bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
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bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
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bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
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bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
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bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
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bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
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bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
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bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
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bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
tree "MSS_TPCC_B (MSS TPCCB Module Registers)"
base ad:0x3120000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
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bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
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bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
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bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
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bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
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bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
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bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
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hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
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hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
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bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
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bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
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bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
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bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
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bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
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bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
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bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
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bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
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bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
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bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
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bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
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bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
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bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
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bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
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bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
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bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
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bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
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bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
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bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
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bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
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bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
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bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
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bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
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bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
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bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
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bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
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bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
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bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
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bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
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bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
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bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
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bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
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bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
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bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
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bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
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bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
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bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
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bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
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bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
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bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x3140000 ad:0x3160000 )
tree "MSS_TPTC_A$1 (MSS TPTC A$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
tree "MSS_TPTC_B0 (MSS TPTC B0 Module Registers)"
base ad:0x3180000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
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bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
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bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
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bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
tree "MSS_VIM_R5A (MSS VIM CR5 CORE A)"
base ad:0x2080000
rgroup.long 0x00++0x27
line.long 0x00 "PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INFO,The Info Register gives the configuration Inforrmation of this VIM"
hexmask.long.tbyte 0x04 11.--31. 1. "RES1,RESERVE FIELD"
hexmask.long.word 0x04 0.--10. 1. "INTERRUPTS,Total number of Interrupts"
line.long 0x08 "PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ"
bitfld.long 0x08 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x08 20.--30. 1. "RES2,RESERVE FIELD"
bitfld.long 0x08 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 10.--15. "RES3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 0.--9. 1. "NUM,Number of the highest priority pending IRQ"
line.long 0x0C "PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ"
bitfld.long 0x0C 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x0C 20.--30. 1. "RES4,RESERVE FIELD"
bitfld.long 0x0C 16.--19. "PRI,Priority of the highest priority pending FIQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 10.--15. "RES5,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x0C 0.--9. 1. "NUM,Number of the highest priority pending FIQ"
line.long 0x10 "IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts"
line.long 0x14 "FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts"
line.long 0x18 "IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ"
hexmask.long 0x18 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x18 0.--1. "RES21,RESERVE FIELD" "0,1,2,3"
line.long 0x1C "FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ"
hexmask.long 0x1C 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x1C 0.--1. "RES22,RESERVE FIELD" "0,1,2,3"
line.long 0x20 "ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ"
bitfld.long 0x20 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x20 20.--30. 1. "RES6,RESERVE FIELD"
bitfld.long 0x20 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 10.--15. "RES7,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "NUM,Number of the currently active IRQ"
line.long 0x24 "ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ"
bitfld.long 0x24 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x24 20.--30. 1. "RES8,RESERVE FIELD"
bitfld.long 0x24 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 10.--15. "RES9,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x24 0.--9. 1. "NUM,Number of the currently active FIQ"
group.long 0x30++0x03
line.long 0x00 "DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ"
hexmask.long 0x00 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x00 0.--1. "RES23,RESERVE FIELD" "0,1,2,3"
group.long 0x400++0xFF
line.long 0x00 "RAW,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x04 "STS,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x08 "INTR_EN_SET,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x0C "INTER_EN_CLR,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x10 "IRQSTS,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x14 "FIQSTS,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x18 "INTMAP,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x1C "INTTYPE,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x20 "RAW_1,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x24 "STS_1,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x28 "INTR_EN_SET_1,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x2C "INTER_EN_CLR_1,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x30 "IRQSTS_1,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x34 "FIQSTS_1,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x38 "INTMAP_1,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x3C "INTTYPE_1,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x40 "RAW_2,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x44 "STS_2,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x48 "INTR_EN_SET_2,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x4C "INTER_EN_CLR_2,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x50 "IRQSTS_2,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x54 "FIQSTS_2,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x58 "INTMAP_2,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x5C "INTTYPE_2,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x60 "RAW_3,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x64 "STS_3,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x68 "INTR_EN_SET_3,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x6C "INTER_EN_CLR_3,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x70 "IRQSTS_3,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x74 "FIQSTS_3,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x78 "INTMAP_3,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x7C "INTTYPE_3,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x80 "RAW_4,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x84 "STS_4,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x88 "INTR_EN_SET_4,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x8C "INTER_EN_CLR_4,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x90 "IRQSTS_4,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x94 "FIQSTS_4,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x98 "INTMAP_4,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x9C "INTTYPE_4,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xA0 "RAW_5,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xA4 "STS_5,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xA8 "INTR_EN_SET_5,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xAC "INTER_EN_CLR_5,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xB0 "IRQSTS_5,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xB4 "FIQSTS_5,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xB8 "INTMAP_5,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xBC "INTTYPE_5,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xC0 "RAW_6,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xC4 "STS_6,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xC8 "INTR_EN_SET_6,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xCC "INTER_EN_CLR_6,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xD0 "IRQSTS_6,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xD4 "FIQSTS_6,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xD8 "INTMAP_6,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xDC "INTTYPE_6,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xE0 "RAW_7,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xE4 "STS_7,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xE8 "INTR_EN_SET_7,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xEC "INTER_EN_CLR_7,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xF0 "IRQSTS_7,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xF4 "FIQSTS_7,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xF8 "INTMAP_7,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xFC "INTTYPE_7,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
group.long 0x1000++0x3FF
line.long 0x00 "INTPRIORITY,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h4"
hexmask.long 0x00 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x00 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTPRIORITY_1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
hexmask.long 0x04 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x04 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "INTPRIORITY_2,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h6"
hexmask.long 0x08 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x08 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "INTPRIORITY_3,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h7"
hexmask.long 0x0C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x0C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "INTPRIORITY_4,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h8"
hexmask.long 0x10 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "INTPRIORITY_5,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h9"
hexmask.long 0x14 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "INTPRIORITY_6,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h10"
hexmask.long 0x18 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "INTPRIORITY_7,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h11"
hexmask.long 0x1C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "INTPRIORITY_8,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h12"
hexmask.long 0x20 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "INTPRIORITY_9,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h13"
hexmask.long 0x24 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "INTPRIORITY_10,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h14"
hexmask.long 0x28 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "INTPRIORITY_11,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h15"
hexmask.long 0x2C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "INTPRIORITY_12,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h16"
hexmask.long 0x30 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "INTPRIORITY_13,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h17"
hexmask.long 0x34 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "INTPRIORITY_14,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h18"
hexmask.long 0x38 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "INTPRIORITY_15,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h19"
hexmask.long 0x3C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "INTPRIORITY_16,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h20"
hexmask.long 0x40 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x40 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "INTPRIORITY_17,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h21"
hexmask.long 0x44 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x44 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "INTPRIORITY_18,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h22"
hexmask.long 0x48 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x48 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "INTPRIORITY_19,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h23"
hexmask.long 0x4C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x4C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "INTPRIORITY_20,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h24"
hexmask.long 0x50 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x50 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "INTPRIORITY_21,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h25"
hexmask.long 0x54 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x54 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "INTPRIORITY_22,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h26"
hexmask.long 0x58 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x58 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "INTPRIORITY_23,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h27"
hexmask.long 0x5C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x5C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x60 "INTPRIORITY_24,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h28"
hexmask.long 0x60 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x60 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "INTPRIORITY_25,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h29"
hexmask.long 0x64 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x64 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "INTPRIORITY_26,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h30"
hexmask.long 0x68 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x68 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "INTPRIORITY_27,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h31"
hexmask.long 0x6C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x6C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "INTPRIORITY_28,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h32"
hexmask.long 0x70 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x70 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x74 "INTPRIORITY_29,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h33"
hexmask.long 0x74 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x74 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x78 "INTPRIORITY_30,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h34"
hexmask.long 0x78 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x78 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x7C "INTPRIORITY_31,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h35"
hexmask.long 0x7C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x7C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x80 "INTPRIORITY_32,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h36"
hexmask.long 0x80 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x80 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "INTPRIORITY_33,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h37"
hexmask.long 0x84 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x84 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "INTPRIORITY_34,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h38"
hexmask.long 0x88 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x88 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "INTPRIORITY_35,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h39"
hexmask.long 0x8C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x8C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "INTPRIORITY_36,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h40"
hexmask.long 0x90 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x90 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x94 "INTPRIORITY_37,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h41"
hexmask.long 0x94 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x94 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x98 "INTPRIORITY_38,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h42"
hexmask.long 0x98 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x98 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "INTPRIORITY_39,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h43"
hexmask.long 0x9C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x9C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA0 "INTPRIORITY_40,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h44"
hexmask.long 0xA0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "INTPRIORITY_41,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h45"
hexmask.long 0xA4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA8 "INTPRIORITY_42,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h46"
hexmask.long 0xA8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xAC "INTPRIORITY_43,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h47"
hexmask.long 0xAC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xAC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB0 "INTPRIORITY_44,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h48"
hexmask.long 0xB0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB4 "INTPRIORITY_45,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h49"
hexmask.long 0xB4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "INTPRIORITY_46,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h50"
hexmask.long 0xB8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xBC "INTPRIORITY_47,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h51"
hexmask.long 0xBC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xBC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC0 "INTPRIORITY_48,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h52"
hexmask.long 0xC0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "INTPRIORITY_49,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h53"
hexmask.long 0xC4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "INTPRIORITY_50,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h54"
hexmask.long 0xC8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "INTPRIORITY_51,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h55"
hexmask.long 0xCC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xCC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD0 "INTPRIORITY_52,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h56"
hexmask.long 0xD0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "INTPRIORITY_53,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h57"
hexmask.long 0xD4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD8 "INTPRIORITY_54,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h58"
hexmask.long 0xD8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "INTPRIORITY_55,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h59"
hexmask.long 0xDC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xDC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE0 "INTPRIORITY_56,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h60"
hexmask.long 0xE0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "INTPRIORITY_57,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h61"
hexmask.long 0xE4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE8 "INTPRIORITY_58,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h62"
hexmask.long 0xE8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "INTPRIORITY_59,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h63"
hexmask.long 0xEC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xEC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF0 "INTPRIORITY_60,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h64"
hexmask.long 0xF0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "INTPRIORITY_61,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h65"
hexmask.long 0xF4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF8 "INTPRIORITY_62,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h66"
hexmask.long 0xF8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "INTPRIORITY_63,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h67"
hexmask.long 0xFC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xFC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x100 "INTPRIORITY_64,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h68"
hexmask.long 0x100 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x100 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "INTPRIORITY_65,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h69"
hexmask.long 0x104 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x104 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x108 "INTPRIORITY_66,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h70"
hexmask.long 0x108 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x108 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10C "INTPRIORITY_67,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h71"
hexmask.long 0x10C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x110 "INTPRIORITY_68,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h72"
hexmask.long 0x110 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x110 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x114 "INTPRIORITY_69,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h73"
hexmask.long 0x114 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x114 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x118 "INTPRIORITY_70,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h74"
hexmask.long 0x118 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x118 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x11C "INTPRIORITY_71,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h75"
hexmask.long 0x11C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x11C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x120 "INTPRIORITY_72,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h76"
hexmask.long 0x120 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x120 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "INTPRIORITY_73,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h77"
hexmask.long 0x124 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x124 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x128 "INTPRIORITY_74,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h78"
hexmask.long 0x128 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x128 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x12C "INTPRIORITY_75,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h79"
hexmask.long 0x12C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x12C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x130 "INTPRIORITY_76,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h80"
hexmask.long 0x130 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x130 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x134 "INTPRIORITY_77,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h81"
hexmask.long 0x134 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x134 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x138 "INTPRIORITY_78,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h82"
hexmask.long 0x138 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x138 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x13C "INTPRIORITY_79,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h83"
hexmask.long 0x13C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x13C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x140 "INTPRIORITY_80,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h84"
hexmask.long 0x140 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x140 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "INTPRIORITY_81,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h85"
hexmask.long 0x144 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x144 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x148 "INTPRIORITY_82,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h86"
hexmask.long 0x148 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x148 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14C "INTPRIORITY_83,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h87"
hexmask.long 0x14C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x150 "INTPRIORITY_84,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h88"
hexmask.long 0x150 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x150 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x154 "INTPRIORITY_85,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h89"
hexmask.long 0x154 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x154 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x158 "INTPRIORITY_86,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h90"
hexmask.long 0x158 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x158 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x15C "INTPRIORITY_87,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h91"
hexmask.long 0x15C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x15C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x160 "INTPRIORITY_88,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h92"
hexmask.long 0x160 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x160 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "INTPRIORITY_89,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h93"
hexmask.long 0x164 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x164 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x168 "INTPRIORITY_90,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h94"
hexmask.long 0x168 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x168 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "INTPRIORITY_91,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h95"
hexmask.long 0x16C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x16C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x170 "INTPRIORITY_92,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h96"
hexmask.long 0x170 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x170 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "INTPRIORITY_93,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h97"
hexmask.long 0x174 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x174 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x178 "INTPRIORITY_94,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h98"
hexmask.long 0x178 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x178 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "INTPRIORITY_95,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h99"
hexmask.long 0x17C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x17C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x180 "INTPRIORITY_96,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h100"
hexmask.long 0x180 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x180 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "INTPRIORITY_97,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h101"
hexmask.long 0x184 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x184 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x188 "INTPRIORITY_98,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h102"
hexmask.long 0x188 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x188 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "INTPRIORITY_99,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h103"
hexmask.long 0x18C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "INTPRIORITY_100,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h104"
hexmask.long 0x190 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x190 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "INTPRIORITY_101,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h105"
hexmask.long 0x194 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x194 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x198 "INTPRIORITY_102,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h106"
hexmask.long 0x198 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x198 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "INTPRIORITY_103,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h107"
hexmask.long 0x19C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x19C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "INTPRIORITY_104,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h108"
hexmask.long 0x1A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "INTPRIORITY_105,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h109"
hexmask.long 0x1A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "INTPRIORITY_106,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h110"
hexmask.long 0x1A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "INTPRIORITY_107,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h111"
hexmask.long 0x1AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "INTPRIORITY_108,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h112"
hexmask.long 0x1B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "INTPRIORITY_109,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h113"
hexmask.long 0x1B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B8 "INTPRIORITY_110,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h114"
hexmask.long 0x1B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "INTPRIORITY_111,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h115"
hexmask.long 0x1BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C0 "INTPRIORITY_112,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h116"
hexmask.long 0x1C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "INTPRIORITY_113,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h117"
hexmask.long 0x1C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C8 "INTPRIORITY_114,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h118"
hexmask.long 0x1C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "INTPRIORITY_115,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h119"
hexmask.long 0x1CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "INTPRIORITY_116,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h120"
hexmask.long 0x1D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "INTPRIORITY_117,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h121"
hexmask.long 0x1D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D8 "INTPRIORITY_118,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h122"
hexmask.long 0x1D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "INTPRIORITY_119,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h123"
hexmask.long 0x1DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E0 "INTPRIORITY_120,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h124"
hexmask.long 0x1E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "INTPRIORITY_121,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h125"
hexmask.long 0x1E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E8 "INTPRIORITY_122,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h126"
hexmask.long 0x1E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1EC "INTPRIORITY_123,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h127"
hexmask.long 0x1EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F0 "INTPRIORITY_124,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h128"
hexmask.long 0x1F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F4 "INTPRIORITY_125,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h129"
hexmask.long 0x1F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F8 "INTPRIORITY_126,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h130"
hexmask.long 0x1F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1FC "INTPRIORITY_127,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h131"
hexmask.long 0x1FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x200 "INTPRIORITY_128,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h132"
hexmask.long 0x200 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x200 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x204 "INTPRIORITY_129,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h133"
hexmask.long 0x204 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x204 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x208 "INTPRIORITY_130,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h134"
hexmask.long 0x208 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x208 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20C "INTPRIORITY_131,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h135"
hexmask.long 0x20C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "INTPRIORITY_132,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h136"
hexmask.long 0x210 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x210 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x214 "INTPRIORITY_133,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h137"
hexmask.long 0x214 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x214 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x218 "INTPRIORITY_134,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h138"
hexmask.long 0x218 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x218 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x21C "INTPRIORITY_135,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h139"
hexmask.long 0x21C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x21C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x220 "INTPRIORITY_136,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h140"
hexmask.long 0x220 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x220 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x224 "INTPRIORITY_137,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h141"
hexmask.long 0x224 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x224 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x228 "INTPRIORITY_138,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h142"
hexmask.long 0x228 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x228 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x22C "INTPRIORITY_139,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h143"
hexmask.long 0x22C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x22C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x230 "INTPRIORITY_140,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h144"
hexmask.long 0x230 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x230 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x234 "INTPRIORITY_141,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h145"
hexmask.long 0x234 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x234 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x238 "INTPRIORITY_142,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h146"
hexmask.long 0x238 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x238 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x23C "INTPRIORITY_143,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h147"
hexmask.long 0x23C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x23C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x240 "INTPRIORITY_144,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h148"
hexmask.long 0x240 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x240 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x244 "INTPRIORITY_145,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h149"
hexmask.long 0x244 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x244 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x248 "INTPRIORITY_146,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h150"
hexmask.long 0x248 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x248 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24C "INTPRIORITY_147,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h151"
hexmask.long 0x24C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x250 "INTPRIORITY_148,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h152"
hexmask.long 0x250 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x250 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x254 "INTPRIORITY_149,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h153"
hexmask.long 0x254 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x254 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x258 "INTPRIORITY_150,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h154"
hexmask.long 0x258 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x258 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x25C "INTPRIORITY_151,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h155"
hexmask.long 0x25C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x25C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x260 "INTPRIORITY_152,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h156"
hexmask.long 0x260 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x260 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x264 "INTPRIORITY_153,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h157"
hexmask.long 0x264 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x264 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x268 "INTPRIORITY_154,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h158"
hexmask.long 0x268 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x268 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x26C "INTPRIORITY_155,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h159"
hexmask.long 0x26C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x26C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x270 "INTPRIORITY_156,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h160"
hexmask.long 0x270 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x270 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x274 "INTPRIORITY_157,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h161"
hexmask.long 0x274 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x274 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x278 "INTPRIORITY_158,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h162"
hexmask.long 0x278 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x278 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x27C "INTPRIORITY_159,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h163"
hexmask.long 0x27C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x27C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x280 "INTPRIORITY_160,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h164"
hexmask.long 0x280 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x280 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x284 "INTPRIORITY_161,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h165"
hexmask.long 0x284 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x284 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x288 "INTPRIORITY_162,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h166"
hexmask.long 0x288 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x288 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28C "INTPRIORITY_163,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h167"
hexmask.long 0x28C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x290 "INTPRIORITY_164,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h168"
hexmask.long 0x290 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x290 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x294 "INTPRIORITY_165,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h169"
hexmask.long 0x294 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x294 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x298 "INTPRIORITY_166,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h170"
hexmask.long 0x298 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x298 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x29C "INTPRIORITY_167,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h171"
hexmask.long 0x29C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x29C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A0 "INTPRIORITY_168,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h172"
hexmask.long 0x2A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A4 "INTPRIORITY_169,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h173"
hexmask.long 0x2A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A8 "INTPRIORITY_170,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h174"
hexmask.long 0x2A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2AC "INTPRIORITY_171,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h175"
hexmask.long 0x2AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B0 "INTPRIORITY_172,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h176"
hexmask.long 0x2B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B4 "INTPRIORITY_173,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h177"
hexmask.long 0x2B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B8 "INTPRIORITY_174,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h178"
hexmask.long 0x2B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2BC "INTPRIORITY_175,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h179"
hexmask.long 0x2BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C0 "INTPRIORITY_176,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h180"
hexmask.long 0x2C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C4 "INTPRIORITY_177,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h181"
hexmask.long 0x2C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C8 "INTPRIORITY_178,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h182"
hexmask.long 0x2C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2CC "INTPRIORITY_179,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h183"
hexmask.long 0x2CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D0 "INTPRIORITY_180,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h184"
hexmask.long 0x2D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D4 "INTPRIORITY_181,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h185"
hexmask.long 0x2D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D8 "INTPRIORITY_182,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h186"
hexmask.long 0x2D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2DC "INTPRIORITY_183,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h187"
hexmask.long 0x2DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E0 "INTPRIORITY_184,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h188"
hexmask.long 0x2E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E4 "INTPRIORITY_185,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h189"
hexmask.long 0x2E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E8 "INTPRIORITY_186,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h190"
hexmask.long 0x2E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2EC "INTPRIORITY_187,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h191"
hexmask.long 0x2EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F0 "INTPRIORITY_188,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h192"
hexmask.long 0x2F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F4 "INTPRIORITY_189,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h193"
hexmask.long 0x2F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F8 "INTPRIORITY_190,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h194"
hexmask.long 0x2F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2FC "INTPRIORITY_191,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h195"
hexmask.long 0x2FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x300 "INTPRIORITY_192,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h196"
hexmask.long 0x300 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x300 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x304 "INTPRIORITY_193,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h197"
hexmask.long 0x304 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x304 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x308 "INTPRIORITY_194,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h198"
hexmask.long 0x308 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x308 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30C "INTPRIORITY_195,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h199"
hexmask.long 0x30C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x310 "INTPRIORITY_196,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h200"
hexmask.long 0x310 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x310 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x314 "INTPRIORITY_197,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h201"
hexmask.long 0x314 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x314 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x318 "INTPRIORITY_198,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h202"
hexmask.long 0x318 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x318 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x31C "INTPRIORITY_199,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h203"
hexmask.long 0x31C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x31C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x320 "INTPRIORITY_200,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h204"
hexmask.long 0x320 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x320 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x324 "INTPRIORITY_201,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h205"
hexmask.long 0x324 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x324 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x328 "INTPRIORITY_202,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h206"
hexmask.long 0x328 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x328 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x32C "INTPRIORITY_203,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h207"
hexmask.long 0x32C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x32C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x330 "INTPRIORITY_204,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h208"
hexmask.long 0x330 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x330 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x334 "INTPRIORITY_205,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h209"
hexmask.long 0x334 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x334 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x338 "INTPRIORITY_206,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h210"
hexmask.long 0x338 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x338 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x33C "INTPRIORITY_207,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h211"
hexmask.long 0x33C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x33C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x340 "INTPRIORITY_208,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h212"
hexmask.long 0x340 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x340 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x344 "INTPRIORITY_209,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h213"
hexmask.long 0x344 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x344 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x348 "INTPRIORITY_210,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h214"
hexmask.long 0x348 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x348 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34C "INTPRIORITY_211,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h215"
hexmask.long 0x34C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x350 "INTPRIORITY_212,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h216"
hexmask.long 0x350 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x350 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x354 "INTPRIORITY_213,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h217"
hexmask.long 0x354 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x354 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x358 "INTPRIORITY_214,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h218"
hexmask.long 0x358 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x358 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x35C "INTPRIORITY_215,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h219"
hexmask.long 0x35C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x35C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x360 "INTPRIORITY_216,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h220"
hexmask.long 0x360 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x360 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x364 "INTPRIORITY_217,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h221"
hexmask.long 0x364 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x364 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x368 "INTPRIORITY_218,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h222"
hexmask.long 0x368 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x368 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x36C "INTPRIORITY_219,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h223"
hexmask.long 0x36C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x36C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x370 "INTPRIORITY_220,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h224"
hexmask.long 0x370 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x370 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x374 "INTPRIORITY_221,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h225"
hexmask.long 0x374 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x374 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x378 "INTPRIORITY_222,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h226"
hexmask.long 0x378 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x378 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x37C "INTPRIORITY_223,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h227"
hexmask.long 0x37C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x37C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x380 "INTPRIORITY_224,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h228"
hexmask.long 0x380 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x380 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x384 "INTPRIORITY_225,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h229"
hexmask.long 0x384 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x384 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x388 "INTPRIORITY_226,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h230"
hexmask.long 0x388 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x388 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38C "INTPRIORITY_227,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h231"
hexmask.long 0x38C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x390 "INTPRIORITY_228,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h232"
hexmask.long 0x390 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x390 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x394 "INTPRIORITY_229,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h233"
hexmask.long 0x394 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x394 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x398 "INTPRIORITY_230,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h234"
hexmask.long 0x398 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x398 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x39C "INTPRIORITY_231,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h235"
hexmask.long 0x39C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x39C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A0 "INTPRIORITY_232,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h236"
hexmask.long 0x3A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A4 "INTPRIORITY_233,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h237"
hexmask.long 0x3A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A8 "INTPRIORITY_234,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h238"
hexmask.long 0x3A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3AC "INTPRIORITY_235,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h239"
hexmask.long 0x3AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B0 "INTPRIORITY_236,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h240"
hexmask.long 0x3B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B4 "INTPRIORITY_237,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h241"
hexmask.long 0x3B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B8 "INTPRIORITY_238,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h242"
hexmask.long 0x3B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3BC "INTPRIORITY_239,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h243"
hexmask.long 0x3BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C0 "INTPRIORITY_240,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h244"
hexmask.long 0x3C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C4 "INTPRIORITY_241,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h245"
hexmask.long 0x3C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C8 "INTPRIORITY_242,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h246"
hexmask.long 0x3C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3CC "INTPRIORITY_243,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h247"
hexmask.long 0x3CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D0 "INTPRIORITY_244,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h248"
hexmask.long 0x3D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D4 "INTPRIORITY_245,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h249"
hexmask.long 0x3D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D8 "INTPRIORITY_246,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h250"
hexmask.long 0x3D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3DC "INTPRIORITY_247,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h251"
hexmask.long 0x3DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E0 "INTPRIORITY_248,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h252"
hexmask.long 0x3E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E4 "INTPRIORITY_249,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h253"
hexmask.long 0x3E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E8 "INTPRIORITY_250,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h254"
hexmask.long 0x3E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3EC "INTPRIORITY_251,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h255"
hexmask.long 0x3EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F0 "INTPRIORITY_252,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h256"
hexmask.long 0x3F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F4 "INTPRIORITY_253,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h257"
hexmask.long 0x3F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F8 "INTPRIORITY_254,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h258"
hexmask.long 0x3F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3FC "INTPRIORITY_255,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h259"
hexmask.long 0x3FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x3FF
line.long 0x00 "INTVECTOR,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h4"
hexmask.long 0x00 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x00 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x04 "INTVECTOR_1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
hexmask.long 0x04 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x04 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x08 "INTVECTOR_2,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h6"
hexmask.long 0x08 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x08 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x0C "INTVECTOR_3,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h7"
hexmask.long 0x0C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x0C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10 "INTVECTOR_4,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h8"
hexmask.long 0x10 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14 "INTVECTOR_5,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h9"
hexmask.long 0x14 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18 "INTVECTOR_6,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h10"
hexmask.long 0x18 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C "INTVECTOR_7,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h11"
hexmask.long 0x1C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20 "INTVECTOR_8,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h12"
hexmask.long 0x20 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24 "INTVECTOR_9,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h13"
hexmask.long 0x24 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28 "INTVECTOR_10,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h14"
hexmask.long 0x28 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C "INTVECTOR_11,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h15"
hexmask.long 0x2C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30 "INTVECTOR_12,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h16"
hexmask.long 0x30 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34 "INTVECTOR_13,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h17"
hexmask.long 0x34 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38 "INTVECTOR_14,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h18"
hexmask.long 0x38 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C "INTVECTOR_15,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h19"
hexmask.long 0x3C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x40 "INTVECTOR_16,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h20"
hexmask.long 0x40 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x40 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x44 "INTVECTOR_17,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h21"
hexmask.long 0x44 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x44 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x48 "INTVECTOR_18,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h22"
hexmask.long 0x48 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x48 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x4C "INTVECTOR_19,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h23"
hexmask.long 0x4C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x4C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x50 "INTVECTOR_20,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h24"
hexmask.long 0x50 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x50 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x54 "INTVECTOR_21,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h25"
hexmask.long 0x54 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x54 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x58 "INTVECTOR_22,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h26"
hexmask.long 0x58 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x58 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x5C "INTVECTOR_23,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h27"
hexmask.long 0x5C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x5C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x60 "INTVECTOR_24,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h28"
hexmask.long 0x60 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x60 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x64 "INTVECTOR_25,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h29"
hexmask.long 0x64 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x64 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x68 "INTVECTOR_26,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h30"
hexmask.long 0x68 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x68 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x6C "INTVECTOR_27,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h31"
hexmask.long 0x6C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x6C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x70 "INTVECTOR_28,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h32"
hexmask.long 0x70 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x70 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x74 "INTVECTOR_29,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h33"
hexmask.long 0x74 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x74 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x78 "INTVECTOR_30,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h34"
hexmask.long 0x78 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x78 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x7C "INTVECTOR_31,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h35"
hexmask.long 0x7C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x7C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x80 "INTVECTOR_32,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h36"
hexmask.long 0x80 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x80 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x84 "INTVECTOR_33,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h37"
hexmask.long 0x84 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x84 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x88 "INTVECTOR_34,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h38"
hexmask.long 0x88 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x88 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x8C "INTVECTOR_35,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h39"
hexmask.long 0x8C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x8C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x90 "INTVECTOR_36,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h40"
hexmask.long 0x90 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x90 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x94 "INTVECTOR_37,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h41"
hexmask.long 0x94 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x94 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x98 "INTVECTOR_38,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h42"
hexmask.long 0x98 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x98 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x9C "INTVECTOR_39,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h43"
hexmask.long 0x9C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x9C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA0 "INTVECTOR_40,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h44"
hexmask.long 0xA0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA4 "INTVECTOR_41,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h45"
hexmask.long 0xA4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA8 "INTVECTOR_42,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h46"
hexmask.long 0xA8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xAC "INTVECTOR_43,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h47"
hexmask.long 0xAC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xAC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB0 "INTVECTOR_44,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h48"
hexmask.long 0xB0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB4 "INTVECTOR_45,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h49"
hexmask.long 0xB4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB8 "INTVECTOR_46,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h50"
hexmask.long 0xB8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xBC "INTVECTOR_47,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h51"
hexmask.long 0xBC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xBC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC0 "INTVECTOR_48,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h52"
hexmask.long 0xC0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC4 "INTVECTOR_49,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h53"
hexmask.long 0xC4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC8 "INTVECTOR_50,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h54"
hexmask.long 0xC8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xCC "INTVECTOR_51,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h55"
hexmask.long 0xCC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xCC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD0 "INTVECTOR_52,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h56"
hexmask.long 0xD0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD4 "INTVECTOR_53,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h57"
hexmask.long 0xD4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD8 "INTVECTOR_54,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h58"
hexmask.long 0xD8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xDC "INTVECTOR_55,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h59"
hexmask.long 0xDC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xDC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE0 "INTVECTOR_56,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h60"
hexmask.long 0xE0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE4 "INTVECTOR_57,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h61"
hexmask.long 0xE4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE8 "INTVECTOR_58,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h62"
hexmask.long 0xE8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xEC "INTVECTOR_59,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h63"
hexmask.long 0xEC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xEC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF0 "INTVECTOR_60,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h64"
hexmask.long 0xF0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF4 "INTVECTOR_61,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h65"
hexmask.long 0xF4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF8 "INTVECTOR_62,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h66"
hexmask.long 0xF8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xFC "INTVECTOR_63,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h67"
hexmask.long 0xFC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xFC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x100 "INTVECTOR_64,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h68"
hexmask.long 0x100 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x100 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x104 "INTVECTOR_65,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h69"
hexmask.long 0x104 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x104 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x108 "INTVECTOR_66,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h70"
hexmask.long 0x108 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x108 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10C "INTVECTOR_67,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h71"
hexmask.long 0x10C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x110 "INTVECTOR_68,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h72"
hexmask.long 0x110 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x110 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x114 "INTVECTOR_69,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h73"
hexmask.long 0x114 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x114 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x118 "INTVECTOR_70,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h74"
hexmask.long 0x118 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x118 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x11C "INTVECTOR_71,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h75"
hexmask.long 0x11C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x11C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x120 "INTVECTOR_72,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h76"
hexmask.long 0x120 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x120 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x124 "INTVECTOR_73,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h77"
hexmask.long 0x124 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x124 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x128 "INTVECTOR_74,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h78"
hexmask.long 0x128 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x128 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x12C "INTVECTOR_75,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h79"
hexmask.long 0x12C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x12C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x130 "INTVECTOR_76,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h80"
hexmask.long 0x130 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x130 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x134 "INTVECTOR_77,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h81"
hexmask.long 0x134 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x134 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x138 "INTVECTOR_78,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h82"
hexmask.long 0x138 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x138 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x13C "INTVECTOR_79,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h83"
hexmask.long 0x13C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x13C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x140 "INTVECTOR_80,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h84"
hexmask.long 0x140 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x140 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x144 "INTVECTOR_81,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h85"
hexmask.long 0x144 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x144 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x148 "INTVECTOR_82,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h86"
hexmask.long 0x148 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x148 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14C "INTVECTOR_83,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h87"
hexmask.long 0x14C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x150 "INTVECTOR_84,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h88"
hexmask.long 0x150 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x150 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x154 "INTVECTOR_85,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h89"
hexmask.long 0x154 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x154 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x158 "INTVECTOR_86,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h90"
hexmask.long 0x158 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x158 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x15C "INTVECTOR_87,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h91"
hexmask.long 0x15C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x15C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x160 "INTVECTOR_88,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h92"
hexmask.long 0x160 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x160 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x164 "INTVECTOR_89,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h93"
hexmask.long 0x164 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x164 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x168 "INTVECTOR_90,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h94"
hexmask.long 0x168 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x168 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x16C "INTVECTOR_91,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h95"
hexmask.long 0x16C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x16C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x170 "INTVECTOR_92,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h96"
hexmask.long 0x170 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x170 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x174 "INTVECTOR_93,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h97"
hexmask.long 0x174 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x174 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x178 "INTVECTOR_94,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h98"
hexmask.long 0x178 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x178 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x17C "INTVECTOR_95,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h99"
hexmask.long 0x17C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x17C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x180 "INTVECTOR_96,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h100"
hexmask.long 0x180 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x180 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x184 "INTVECTOR_97,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h101"
hexmask.long 0x184 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x184 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x188 "INTVECTOR_98,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h102"
hexmask.long 0x188 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x188 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18C "INTVECTOR_99,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h103"
hexmask.long 0x18C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x190 "INTVECTOR_100,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h104"
hexmask.long 0x190 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x190 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x194 "INTVECTOR_101,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h105"
hexmask.long 0x194 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x194 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x198 "INTVECTOR_102,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h106"
hexmask.long 0x198 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x198 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x19C "INTVECTOR_103,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h107"
hexmask.long 0x19C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x19C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A0 "INTVECTOR_104,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h108"
hexmask.long 0x1A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A4 "INTVECTOR_105,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h109"
hexmask.long 0x1A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A8 "INTVECTOR_106,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h110"
hexmask.long 0x1A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1AC "INTVECTOR_107,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h111"
hexmask.long 0x1AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B0 "INTVECTOR_108,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h112"
hexmask.long 0x1B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B4 "INTVECTOR_109,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h113"
hexmask.long 0x1B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B8 "INTVECTOR_110,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h114"
hexmask.long 0x1B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1BC "INTVECTOR_111,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h115"
hexmask.long 0x1BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C0 "INTVECTOR_112,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h116"
hexmask.long 0x1C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C4 "INTVECTOR_113,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h117"
hexmask.long 0x1C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C8 "INTVECTOR_114,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h118"
hexmask.long 0x1C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1CC "INTVECTOR_115,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h119"
hexmask.long 0x1CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D0 "INTVECTOR_116,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h120"
hexmask.long 0x1D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D4 "INTVECTOR_117,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h121"
hexmask.long 0x1D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D8 "INTVECTOR_118,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h122"
hexmask.long 0x1D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1DC "INTVECTOR_119,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h123"
hexmask.long 0x1DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E0 "INTVECTOR_120,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h124"
hexmask.long 0x1E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E4 "INTVECTOR_121,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h125"
hexmask.long 0x1E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E8 "INTVECTOR_122,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h126"
hexmask.long 0x1E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1EC "INTVECTOR_123,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h127"
hexmask.long 0x1EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F0 "INTVECTOR_124,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h128"
hexmask.long 0x1F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F4 "INTVECTOR_125,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h129"
hexmask.long 0x1F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F8 "INTVECTOR_126,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h130"
hexmask.long 0x1F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1FC "INTVECTOR_127,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h131"
hexmask.long 0x1FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x200 "INTVECTOR_128,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h132"
hexmask.long 0x200 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x200 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x204 "INTVECTOR_129,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h133"
hexmask.long 0x204 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x204 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x208 "INTVECTOR_130,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h134"
hexmask.long 0x208 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x208 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20C "INTVECTOR_131,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h135"
hexmask.long 0x20C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x210 "INTVECTOR_132,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h136"
hexmask.long 0x210 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x210 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x214 "INTVECTOR_133,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h137"
hexmask.long 0x214 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x214 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x218 "INTVECTOR_134,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h138"
hexmask.long 0x218 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x218 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x21C "INTVECTOR_135,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h139"
hexmask.long 0x21C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x21C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x220 "INTVECTOR_136,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h140"
hexmask.long 0x220 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x220 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x224 "INTVECTOR_137,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h141"
hexmask.long 0x224 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x224 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x228 "INTVECTOR_138,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h142"
hexmask.long 0x228 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x228 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x22C "INTVECTOR_139,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h143"
hexmask.long 0x22C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x22C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x230 "INTVECTOR_140,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h144"
hexmask.long 0x230 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x230 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x234 "INTVECTOR_141,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h145"
hexmask.long 0x234 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x234 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x238 "INTVECTOR_142,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h146"
hexmask.long 0x238 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x238 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x23C "INTVECTOR_143,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h147"
hexmask.long 0x23C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x23C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x240 "INTVECTOR_144,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h148"
hexmask.long 0x240 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x240 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x244 "INTVECTOR_145,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h149"
hexmask.long 0x244 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x244 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x248 "INTVECTOR_146,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h150"
hexmask.long 0x248 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x248 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24C "INTVECTOR_147,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h151"
hexmask.long 0x24C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x250 "INTVECTOR_148,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h152"
hexmask.long 0x250 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x250 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x254 "INTVECTOR_149,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h153"
hexmask.long 0x254 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x254 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x258 "INTVECTOR_150,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h154"
hexmask.long 0x258 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x258 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x25C "INTVECTOR_151,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h155"
hexmask.long 0x25C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x25C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x260 "INTVECTOR_152,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h156"
hexmask.long 0x260 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x260 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x264 "INTVECTOR_153,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h157"
hexmask.long 0x264 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x264 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x268 "INTVECTOR_154,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h158"
hexmask.long 0x268 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x268 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x26C "INTVECTOR_155,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h159"
hexmask.long 0x26C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x26C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x270 "INTVECTOR_156,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h160"
hexmask.long 0x270 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x270 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x274 "INTVECTOR_157,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h161"
hexmask.long 0x274 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x274 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x278 "INTVECTOR_158,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h162"
hexmask.long 0x278 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x278 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x27C "INTVECTOR_159,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h163"
hexmask.long 0x27C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x27C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x280 "INTVECTOR_160,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h164"
hexmask.long 0x280 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x280 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x284 "INTVECTOR_161,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h165"
hexmask.long 0x284 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x284 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x288 "INTVECTOR_162,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h166"
hexmask.long 0x288 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x288 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28C "INTVECTOR_163,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h167"
hexmask.long 0x28C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x290 "INTVECTOR_164,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h168"
hexmask.long 0x290 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x290 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x294 "INTVECTOR_165,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h169"
hexmask.long 0x294 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x294 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x298 "INTVECTOR_166,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h170"
hexmask.long 0x298 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x298 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x29C "INTVECTOR_167,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h171"
hexmask.long 0x29C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x29C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A0 "INTVECTOR_168,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h172"
hexmask.long 0x2A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A4 "INTVECTOR_169,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h173"
hexmask.long 0x2A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A8 "INTVECTOR_170,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h174"
hexmask.long 0x2A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2AC "INTVECTOR_171,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h175"
hexmask.long 0x2AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B0 "INTVECTOR_172,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h176"
hexmask.long 0x2B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B4 "INTVECTOR_173,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h177"
hexmask.long 0x2B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B8 "INTVECTOR_174,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h178"
hexmask.long 0x2B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2BC "INTVECTOR_175,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h179"
hexmask.long 0x2BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C0 "INTVECTOR_176,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h180"
hexmask.long 0x2C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C4 "INTVECTOR_177,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h181"
hexmask.long 0x2C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C8 "INTVECTOR_178,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h182"
hexmask.long 0x2C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2CC "INTVECTOR_179,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h183"
hexmask.long 0x2CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D0 "INTVECTOR_180,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h184"
hexmask.long 0x2D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D4 "INTVECTOR_181,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h185"
hexmask.long 0x2D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D8 "INTVECTOR_182,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h186"
hexmask.long 0x2D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2DC "INTVECTOR_183,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h187"
hexmask.long 0x2DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E0 "INTVECTOR_184,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h188"
hexmask.long 0x2E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E4 "INTVECTOR_185,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h189"
hexmask.long 0x2E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E8 "INTVECTOR_186,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h190"
hexmask.long 0x2E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2EC "INTVECTOR_187,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h191"
hexmask.long 0x2EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F0 "INTVECTOR_188,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h192"
hexmask.long 0x2F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F4 "INTVECTOR_189,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h193"
hexmask.long 0x2F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F8 "INTVECTOR_190,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h194"
hexmask.long 0x2F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2FC "INTVECTOR_191,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h195"
hexmask.long 0x2FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x300 "INTVECTOR_192,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h196"
hexmask.long 0x300 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x300 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x304 "INTVECTOR_193,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h197"
hexmask.long 0x304 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x304 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x308 "INTVECTOR_194,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h198"
hexmask.long 0x308 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x308 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30C "INTVECTOR_195,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h199"
hexmask.long 0x30C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x310 "INTVECTOR_196,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h200"
hexmask.long 0x310 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x310 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x314 "INTVECTOR_197,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h201"
hexmask.long 0x314 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x314 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x318 "INTVECTOR_198,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h202"
hexmask.long 0x318 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x318 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x31C "INTVECTOR_199,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h203"
hexmask.long 0x31C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x31C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x320 "INTVECTOR_200,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h204"
hexmask.long 0x320 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x320 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x324 "INTVECTOR_201,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h205"
hexmask.long 0x324 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x324 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x328 "INTVECTOR_202,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h206"
hexmask.long 0x328 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x328 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x32C "INTVECTOR_203,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h207"
hexmask.long 0x32C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x32C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x330 "INTVECTOR_204,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h208"
hexmask.long 0x330 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x330 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x334 "INTVECTOR_205,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h209"
hexmask.long 0x334 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x334 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x338 "INTVECTOR_206,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h210"
hexmask.long 0x338 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x338 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x33C "INTVECTOR_207,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h211"
hexmask.long 0x33C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x33C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x340 "INTVECTOR_208,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h212"
hexmask.long 0x340 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x340 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x344 "INTVECTOR_209,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h213"
hexmask.long 0x344 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x344 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x348 "INTVECTOR_210,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h214"
hexmask.long 0x348 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x348 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34C "INTVECTOR_211,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h215"
hexmask.long 0x34C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x350 "INTVECTOR_212,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h216"
hexmask.long 0x350 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x350 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x354 "INTVECTOR_213,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h217"
hexmask.long 0x354 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x354 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x358 "INTVECTOR_214,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h218"
hexmask.long 0x358 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x358 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x35C "INTVECTOR_215,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h219"
hexmask.long 0x35C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x35C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x360 "INTVECTOR_216,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h220"
hexmask.long 0x360 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x360 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x364 "INTVECTOR_217,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h221"
hexmask.long 0x364 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x364 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x368 "INTVECTOR_218,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h222"
hexmask.long 0x368 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x368 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x36C "INTVECTOR_219,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h223"
hexmask.long 0x36C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x36C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x370 "INTVECTOR_220,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h224"
hexmask.long 0x370 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x370 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x374 "INTVECTOR_221,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h225"
hexmask.long 0x374 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x374 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x378 "INTVECTOR_222,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h226"
hexmask.long 0x378 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x378 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x37C "INTVECTOR_223,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h227"
hexmask.long 0x37C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x37C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x380 "INTVECTOR_224,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h228"
hexmask.long 0x380 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x380 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x384 "INTVECTOR_225,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h229"
hexmask.long 0x384 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x384 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x388 "INTVECTOR_226,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h230"
hexmask.long 0x388 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x388 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38C "INTVECTOR_227,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h231"
hexmask.long 0x38C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x390 "INTVECTOR_228,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h232"
hexmask.long 0x390 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x390 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x394 "INTVECTOR_229,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h233"
hexmask.long 0x394 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x394 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x398 "INTVECTOR_230,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h234"
hexmask.long 0x398 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x398 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x39C "INTVECTOR_231,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h235"
hexmask.long 0x39C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x39C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A0 "INTVECTOR_232,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h236"
hexmask.long 0x3A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A4 "INTVECTOR_233,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h237"
hexmask.long 0x3A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A8 "INTVECTOR_234,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h238"
hexmask.long 0x3A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3AC "INTVECTOR_235,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h239"
hexmask.long 0x3AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B0 "INTVECTOR_236,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h240"
hexmask.long 0x3B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B4 "INTVECTOR_237,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h241"
hexmask.long 0x3B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B8 "INTVECTOR_238,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h242"
hexmask.long 0x3B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3BC "INTVECTOR_239,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h243"
hexmask.long 0x3BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C0 "INTVECTOR_240,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h244"
hexmask.long 0x3C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C4 "INTVECTOR_241,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h245"
hexmask.long 0x3C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C8 "INTVECTOR_242,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h246"
hexmask.long 0x3C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3CC "INTVECTOR_243,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h247"
hexmask.long 0x3CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D0 "INTVECTOR_244,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h248"
hexmask.long 0x3D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D4 "INTVECTOR_245,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h249"
hexmask.long 0x3D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D8 "INTVECTOR_246,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h250"
hexmask.long 0x3D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3DC "INTVECTOR_247,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h251"
hexmask.long 0x3DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E0 "INTVECTOR_248,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h252"
hexmask.long 0x3E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E4 "INTVECTOR_249,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h253"
hexmask.long 0x3E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E8 "INTVECTOR_250,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h254"
hexmask.long 0x3E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3EC "INTVECTOR_251,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h255"
hexmask.long 0x3EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F0 "INTVECTOR_252,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h256"
hexmask.long 0x3F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F4 "INTVECTOR_253,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h257"
hexmask.long 0x3F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F8 "INTVECTOR_254,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h258"
hexmask.long 0x3F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3FC "INTVECTOR_255,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h259"
hexmask.long 0x3FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3FC 0.--1. "RES20,Reserved" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_VIM_R5B (MSS VIM CR5 CORE B)"
base ad:0x20A0000
rgroup.long 0x00++0x27
line.long 0x00 "PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INFO,The Info Register gives the configuration Inforrmation of this VIM"
hexmask.long.tbyte 0x04 11.--31. 1. "RES1,RESERVE FIELD"
hexmask.long.word 0x04 0.--10. 1. "INTERRUPTS,Total number of Interrupts"
line.long 0x08 "PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ"
bitfld.long 0x08 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x08 20.--30. 1. "RES2,RESERVE FIELD"
bitfld.long 0x08 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 10.--15. "RES3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 0.--9. 1. "NUM,Number of the highest priority pending IRQ"
line.long 0x0C "PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ"
bitfld.long 0x0C 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x0C 20.--30. 1. "RES4,RESERVE FIELD"
bitfld.long 0x0C 16.--19. "PRI,Priority of the highest priority pending FIQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 10.--15. "RES5,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x0C 0.--9. 1. "NUM,Number of the highest priority pending FIQ"
line.long 0x10 "IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts"
line.long 0x14 "FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts"
line.long 0x18 "IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ"
hexmask.long 0x18 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x18 0.--1. "RES21,RESERVE FIELD" "0,1,2,3"
line.long 0x1C "FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ"
hexmask.long 0x1C 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x1C 0.--1. "RES22,RESERVE FIELD" "0,1,2,3"
line.long 0x20 "ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ"
bitfld.long 0x20 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x20 20.--30. 1. "RES6,RESERVE FIELD"
bitfld.long 0x20 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 10.--15. "RES7,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "NUM,Number of the currently active IRQ"
line.long 0x24 "ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ"
bitfld.long 0x24 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x24 20.--30. 1. "RES8,RESERVE FIELD"
bitfld.long 0x24 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 10.--15. "RES9,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x24 0.--9. 1. "NUM,Number of the currently active FIQ"
group.long 0x30++0x03
line.long 0x00 "DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ"
hexmask.long 0x00 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x00 0.--1. "RES23,RESERVE FIELD" "0,1,2,3"
group.long 0x400++0xFF
line.long 0x00 "RAW,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x04 "STS,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x08 "INTR_EN_SET,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x0C "INTER_EN_CLR,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x10 "IRQSTS,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x14 "FIQSTS,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x18 "INTMAP,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x1C "INTTYPE,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x20 "RAW_1,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x24 "STS_1,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x28 "INTR_EN_SET_1,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x2C "INTER_EN_CLR_1,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x30 "IRQSTS_1,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x34 "FIQSTS_1,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x38 "INTMAP_1,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x3C "INTTYPE_1,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x40 "RAW_2,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x44 "STS_2,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x48 "INTR_EN_SET_2,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x4C "INTER_EN_CLR_2,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x50 "IRQSTS_2,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x54 "FIQSTS_2,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x58 "INTMAP_2,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x5C "INTTYPE_2,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x60 "RAW_3,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x64 "STS_3,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x68 "INTR_EN_SET_3,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x6C "INTER_EN_CLR_3,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x70 "IRQSTS_3,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x74 "FIQSTS_3,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x78 "INTMAP_3,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x7C "INTTYPE_3,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x80 "RAW_4,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x84 "STS_4,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x88 "INTR_EN_SET_4,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x8C "INTER_EN_CLR_4,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x90 "IRQSTS_4,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x94 "FIQSTS_4,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x98 "INTMAP_4,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x9C "INTTYPE_4,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xA0 "RAW_5,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xA4 "STS_5,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xA8 "INTR_EN_SET_5,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xAC "INTER_EN_CLR_5,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xB0 "IRQSTS_5,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xB4 "FIQSTS_5,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xB8 "INTMAP_5,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xBC "INTTYPE_5,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xC0 "RAW_6,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xC4 "STS_6,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xC8 "INTR_EN_SET_6,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xCC "INTER_EN_CLR_6,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xD0 "IRQSTS_6,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xD4 "FIQSTS_6,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xD8 "INTMAP_6,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xDC "INTTYPE_6,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xE0 "RAW_7,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xE4 "STS_7,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xE8 "INTR_EN_SET_7,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xEC "INTER_EN_CLR_7,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xF0 "IRQSTS_7,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xF4 "FIQSTS_7,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xF8 "INTMAP_7,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xFC "INTTYPE_7,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
group.long 0x1000++0x3FF
line.long 0x00 "INTPRIORITY,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h4"
hexmask.long 0x00 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x00 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTPRIORITY_1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
hexmask.long 0x04 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x04 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "INTPRIORITY_2,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h6"
hexmask.long 0x08 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x08 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "INTPRIORITY_3,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h7"
hexmask.long 0x0C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x0C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "INTPRIORITY_4,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h8"
hexmask.long 0x10 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "INTPRIORITY_5,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h9"
hexmask.long 0x14 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "INTPRIORITY_6,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h10"
hexmask.long 0x18 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "INTPRIORITY_7,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h11"
hexmask.long 0x1C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "INTPRIORITY_8,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h12"
hexmask.long 0x20 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "INTPRIORITY_9,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h13"
hexmask.long 0x24 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "INTPRIORITY_10,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h14"
hexmask.long 0x28 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "INTPRIORITY_11,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h15"
hexmask.long 0x2C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "INTPRIORITY_12,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h16"
hexmask.long 0x30 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "INTPRIORITY_13,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h17"
hexmask.long 0x34 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "INTPRIORITY_14,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h18"
hexmask.long 0x38 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "INTPRIORITY_15,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h19"
hexmask.long 0x3C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "INTPRIORITY_16,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h20"
hexmask.long 0x40 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x40 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "INTPRIORITY_17,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h21"
hexmask.long 0x44 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x44 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "INTPRIORITY_18,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h22"
hexmask.long 0x48 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x48 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "INTPRIORITY_19,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h23"
hexmask.long 0x4C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x4C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "INTPRIORITY_20,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h24"
hexmask.long 0x50 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x50 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "INTPRIORITY_21,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h25"
hexmask.long 0x54 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x54 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "INTPRIORITY_22,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h26"
hexmask.long 0x58 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x58 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "INTPRIORITY_23,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h27"
hexmask.long 0x5C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x5C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x60 "INTPRIORITY_24,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h28"
hexmask.long 0x60 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x60 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "INTPRIORITY_25,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h29"
hexmask.long 0x64 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x64 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "INTPRIORITY_26,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h30"
hexmask.long 0x68 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x68 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "INTPRIORITY_27,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h31"
hexmask.long 0x6C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x6C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "INTPRIORITY_28,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h32"
hexmask.long 0x70 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x70 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x74 "INTPRIORITY_29,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h33"
hexmask.long 0x74 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x74 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x78 "INTPRIORITY_30,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h34"
hexmask.long 0x78 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x78 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x7C "INTPRIORITY_31,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h35"
hexmask.long 0x7C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x7C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x80 "INTPRIORITY_32,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h36"
hexmask.long 0x80 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x80 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "INTPRIORITY_33,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h37"
hexmask.long 0x84 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x84 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "INTPRIORITY_34,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h38"
hexmask.long 0x88 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x88 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "INTPRIORITY_35,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h39"
hexmask.long 0x8C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x8C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "INTPRIORITY_36,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h40"
hexmask.long 0x90 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x90 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x94 "INTPRIORITY_37,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h41"
hexmask.long 0x94 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x94 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x98 "INTPRIORITY_38,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h42"
hexmask.long 0x98 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x98 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "INTPRIORITY_39,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h43"
hexmask.long 0x9C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x9C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA0 "INTPRIORITY_40,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h44"
hexmask.long 0xA0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "INTPRIORITY_41,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h45"
hexmask.long 0xA4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA8 "INTPRIORITY_42,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h46"
hexmask.long 0xA8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xAC "INTPRIORITY_43,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h47"
hexmask.long 0xAC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xAC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB0 "INTPRIORITY_44,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h48"
hexmask.long 0xB0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB4 "INTPRIORITY_45,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h49"
hexmask.long 0xB4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "INTPRIORITY_46,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h50"
hexmask.long 0xB8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xBC "INTPRIORITY_47,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h51"
hexmask.long 0xBC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xBC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC0 "INTPRIORITY_48,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h52"
hexmask.long 0xC0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "INTPRIORITY_49,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h53"
hexmask.long 0xC4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "INTPRIORITY_50,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h54"
hexmask.long 0xC8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "INTPRIORITY_51,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h55"
hexmask.long 0xCC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xCC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD0 "INTPRIORITY_52,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h56"
hexmask.long 0xD0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "INTPRIORITY_53,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h57"
hexmask.long 0xD4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD8 "INTPRIORITY_54,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h58"
hexmask.long 0xD8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "INTPRIORITY_55,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h59"
hexmask.long 0xDC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xDC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE0 "INTPRIORITY_56,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h60"
hexmask.long 0xE0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "INTPRIORITY_57,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h61"
hexmask.long 0xE4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE8 "INTPRIORITY_58,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h62"
hexmask.long 0xE8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "INTPRIORITY_59,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h63"
hexmask.long 0xEC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xEC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF0 "INTPRIORITY_60,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h64"
hexmask.long 0xF0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "INTPRIORITY_61,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h65"
hexmask.long 0xF4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF8 "INTPRIORITY_62,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h66"
hexmask.long 0xF8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "INTPRIORITY_63,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h67"
hexmask.long 0xFC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xFC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x100 "INTPRIORITY_64,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h68"
hexmask.long 0x100 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x100 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "INTPRIORITY_65,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h69"
hexmask.long 0x104 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x104 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x108 "INTPRIORITY_66,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h70"
hexmask.long 0x108 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x108 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10C "INTPRIORITY_67,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h71"
hexmask.long 0x10C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x110 "INTPRIORITY_68,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h72"
hexmask.long 0x110 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x110 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x114 "INTPRIORITY_69,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h73"
hexmask.long 0x114 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x114 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x118 "INTPRIORITY_70,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h74"
hexmask.long 0x118 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x118 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x11C "INTPRIORITY_71,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h75"
hexmask.long 0x11C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x11C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x120 "INTPRIORITY_72,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h76"
hexmask.long 0x120 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x120 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "INTPRIORITY_73,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h77"
hexmask.long 0x124 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x124 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x128 "INTPRIORITY_74,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h78"
hexmask.long 0x128 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x128 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x12C "INTPRIORITY_75,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h79"
hexmask.long 0x12C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x12C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x130 "INTPRIORITY_76,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h80"
hexmask.long 0x130 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x130 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x134 "INTPRIORITY_77,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h81"
hexmask.long 0x134 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x134 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x138 "INTPRIORITY_78,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h82"
hexmask.long 0x138 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x138 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x13C "INTPRIORITY_79,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h83"
hexmask.long 0x13C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x13C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x140 "INTPRIORITY_80,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h84"
hexmask.long 0x140 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x140 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "INTPRIORITY_81,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h85"
hexmask.long 0x144 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x144 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x148 "INTPRIORITY_82,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h86"
hexmask.long 0x148 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x148 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14C "INTPRIORITY_83,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h87"
hexmask.long 0x14C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x150 "INTPRIORITY_84,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h88"
hexmask.long 0x150 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x150 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x154 "INTPRIORITY_85,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h89"
hexmask.long 0x154 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x154 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x158 "INTPRIORITY_86,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h90"
hexmask.long 0x158 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x158 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x15C "INTPRIORITY_87,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h91"
hexmask.long 0x15C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x15C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x160 "INTPRIORITY_88,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h92"
hexmask.long 0x160 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x160 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "INTPRIORITY_89,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h93"
hexmask.long 0x164 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x164 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x168 "INTPRIORITY_90,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h94"
hexmask.long 0x168 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x168 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "INTPRIORITY_91,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h95"
hexmask.long 0x16C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x16C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x170 "INTPRIORITY_92,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h96"
hexmask.long 0x170 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x170 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "INTPRIORITY_93,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h97"
hexmask.long 0x174 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x174 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x178 "INTPRIORITY_94,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h98"
hexmask.long 0x178 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x178 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "INTPRIORITY_95,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h99"
hexmask.long 0x17C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x17C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x180 "INTPRIORITY_96,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h100"
hexmask.long 0x180 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x180 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "INTPRIORITY_97,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h101"
hexmask.long 0x184 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x184 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x188 "INTPRIORITY_98,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h102"
hexmask.long 0x188 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x188 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "INTPRIORITY_99,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h103"
hexmask.long 0x18C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "INTPRIORITY_100,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h104"
hexmask.long 0x190 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x190 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "INTPRIORITY_101,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h105"
hexmask.long 0x194 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x194 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x198 "INTPRIORITY_102,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h106"
hexmask.long 0x198 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x198 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "INTPRIORITY_103,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h107"
hexmask.long 0x19C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x19C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "INTPRIORITY_104,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h108"
hexmask.long 0x1A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "INTPRIORITY_105,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h109"
hexmask.long 0x1A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "INTPRIORITY_106,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h110"
hexmask.long 0x1A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "INTPRIORITY_107,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h111"
hexmask.long 0x1AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "INTPRIORITY_108,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h112"
hexmask.long 0x1B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "INTPRIORITY_109,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h113"
hexmask.long 0x1B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B8 "INTPRIORITY_110,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h114"
hexmask.long 0x1B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "INTPRIORITY_111,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h115"
hexmask.long 0x1BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C0 "INTPRIORITY_112,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h116"
hexmask.long 0x1C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "INTPRIORITY_113,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h117"
hexmask.long 0x1C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C8 "INTPRIORITY_114,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h118"
hexmask.long 0x1C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "INTPRIORITY_115,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h119"
hexmask.long 0x1CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "INTPRIORITY_116,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h120"
hexmask.long 0x1D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "INTPRIORITY_117,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h121"
hexmask.long 0x1D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D8 "INTPRIORITY_118,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h122"
hexmask.long 0x1D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "INTPRIORITY_119,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h123"
hexmask.long 0x1DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E0 "INTPRIORITY_120,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h124"
hexmask.long 0x1E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "INTPRIORITY_121,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h125"
hexmask.long 0x1E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E8 "INTPRIORITY_122,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h126"
hexmask.long 0x1E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1EC "INTPRIORITY_123,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h127"
hexmask.long 0x1EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F0 "INTPRIORITY_124,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h128"
hexmask.long 0x1F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F4 "INTPRIORITY_125,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h129"
hexmask.long 0x1F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F8 "INTPRIORITY_126,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h130"
hexmask.long 0x1F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1FC "INTPRIORITY_127,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h131"
hexmask.long 0x1FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x200 "INTPRIORITY_128,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h132"
hexmask.long 0x200 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x200 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x204 "INTPRIORITY_129,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h133"
hexmask.long 0x204 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x204 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x208 "INTPRIORITY_130,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h134"
hexmask.long 0x208 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x208 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20C "INTPRIORITY_131,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h135"
hexmask.long 0x20C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "INTPRIORITY_132,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h136"
hexmask.long 0x210 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x210 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x214 "INTPRIORITY_133,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h137"
hexmask.long 0x214 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x214 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x218 "INTPRIORITY_134,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h138"
hexmask.long 0x218 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x218 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x21C "INTPRIORITY_135,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h139"
hexmask.long 0x21C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x21C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x220 "INTPRIORITY_136,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h140"
hexmask.long 0x220 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x220 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x224 "INTPRIORITY_137,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h141"
hexmask.long 0x224 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x224 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x228 "INTPRIORITY_138,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h142"
hexmask.long 0x228 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x228 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x22C "INTPRIORITY_139,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h143"
hexmask.long 0x22C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x22C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x230 "INTPRIORITY_140,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h144"
hexmask.long 0x230 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x230 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x234 "INTPRIORITY_141,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h145"
hexmask.long 0x234 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x234 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x238 "INTPRIORITY_142,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h146"
hexmask.long 0x238 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x238 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x23C "INTPRIORITY_143,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h147"
hexmask.long 0x23C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x23C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x240 "INTPRIORITY_144,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h148"
hexmask.long 0x240 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x240 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x244 "INTPRIORITY_145,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h149"
hexmask.long 0x244 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x244 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x248 "INTPRIORITY_146,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h150"
hexmask.long 0x248 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x248 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24C "INTPRIORITY_147,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h151"
hexmask.long 0x24C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x250 "INTPRIORITY_148,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h152"
hexmask.long 0x250 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x250 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x254 "INTPRIORITY_149,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h153"
hexmask.long 0x254 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x254 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x258 "INTPRIORITY_150,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h154"
hexmask.long 0x258 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x258 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x25C "INTPRIORITY_151,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h155"
hexmask.long 0x25C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x25C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x260 "INTPRIORITY_152,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h156"
hexmask.long 0x260 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x260 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x264 "INTPRIORITY_153,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h157"
hexmask.long 0x264 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x264 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x268 "INTPRIORITY_154,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h158"
hexmask.long 0x268 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x268 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x26C "INTPRIORITY_155,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h159"
hexmask.long 0x26C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x26C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x270 "INTPRIORITY_156,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h160"
hexmask.long 0x270 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x270 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x274 "INTPRIORITY_157,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h161"
hexmask.long 0x274 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x274 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x278 "INTPRIORITY_158,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h162"
hexmask.long 0x278 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x278 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x27C "INTPRIORITY_159,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h163"
hexmask.long 0x27C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x27C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x280 "INTPRIORITY_160,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h164"
hexmask.long 0x280 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x280 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x284 "INTPRIORITY_161,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h165"
hexmask.long 0x284 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x284 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x288 "INTPRIORITY_162,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h166"
hexmask.long 0x288 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x288 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28C "INTPRIORITY_163,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h167"
hexmask.long 0x28C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x290 "INTPRIORITY_164,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h168"
hexmask.long 0x290 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x290 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x294 "INTPRIORITY_165,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h169"
hexmask.long 0x294 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x294 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x298 "INTPRIORITY_166,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h170"
hexmask.long 0x298 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x298 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x29C "INTPRIORITY_167,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h171"
hexmask.long 0x29C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x29C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A0 "INTPRIORITY_168,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h172"
hexmask.long 0x2A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A4 "INTPRIORITY_169,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h173"
hexmask.long 0x2A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A8 "INTPRIORITY_170,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h174"
hexmask.long 0x2A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2AC "INTPRIORITY_171,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h175"
hexmask.long 0x2AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B0 "INTPRIORITY_172,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h176"
hexmask.long 0x2B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B4 "INTPRIORITY_173,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h177"
hexmask.long 0x2B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B8 "INTPRIORITY_174,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h178"
hexmask.long 0x2B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2BC "INTPRIORITY_175,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h179"
hexmask.long 0x2BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C0 "INTPRIORITY_176,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h180"
hexmask.long 0x2C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C4 "INTPRIORITY_177,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h181"
hexmask.long 0x2C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C8 "INTPRIORITY_178,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h182"
hexmask.long 0x2C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2CC "INTPRIORITY_179,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h183"
hexmask.long 0x2CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D0 "INTPRIORITY_180,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h184"
hexmask.long 0x2D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D4 "INTPRIORITY_181,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h185"
hexmask.long 0x2D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D8 "INTPRIORITY_182,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h186"
hexmask.long 0x2D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2DC "INTPRIORITY_183,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h187"
hexmask.long 0x2DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E0 "INTPRIORITY_184,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h188"
hexmask.long 0x2E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E4 "INTPRIORITY_185,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h189"
hexmask.long 0x2E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E8 "INTPRIORITY_186,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h190"
hexmask.long 0x2E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2EC "INTPRIORITY_187,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h191"
hexmask.long 0x2EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F0 "INTPRIORITY_188,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h192"
hexmask.long 0x2F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F4 "INTPRIORITY_189,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h193"
hexmask.long 0x2F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F8 "INTPRIORITY_190,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h194"
hexmask.long 0x2F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2FC "INTPRIORITY_191,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h195"
hexmask.long 0x2FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x300 "INTPRIORITY_192,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h196"
hexmask.long 0x300 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x300 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x304 "INTPRIORITY_193,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h197"
hexmask.long 0x304 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x304 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x308 "INTPRIORITY_194,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h198"
hexmask.long 0x308 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x308 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30C "INTPRIORITY_195,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h199"
hexmask.long 0x30C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x310 "INTPRIORITY_196,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h200"
hexmask.long 0x310 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x310 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x314 "INTPRIORITY_197,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h201"
hexmask.long 0x314 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x314 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x318 "INTPRIORITY_198,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h202"
hexmask.long 0x318 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x318 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x31C "INTPRIORITY_199,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h203"
hexmask.long 0x31C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x31C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x320 "INTPRIORITY_200,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h204"
hexmask.long 0x320 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x320 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x324 "INTPRIORITY_201,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h205"
hexmask.long 0x324 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x324 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x328 "INTPRIORITY_202,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h206"
hexmask.long 0x328 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x328 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x32C "INTPRIORITY_203,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h207"
hexmask.long 0x32C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x32C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x330 "INTPRIORITY_204,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h208"
hexmask.long 0x330 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x330 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x334 "INTPRIORITY_205,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h209"
hexmask.long 0x334 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x334 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x338 "INTPRIORITY_206,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h210"
hexmask.long 0x338 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x338 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x33C "INTPRIORITY_207,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h211"
hexmask.long 0x33C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x33C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x340 "INTPRIORITY_208,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h212"
hexmask.long 0x340 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x340 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x344 "INTPRIORITY_209,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h213"
hexmask.long 0x344 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x344 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x348 "INTPRIORITY_210,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h214"
hexmask.long 0x348 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x348 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34C "INTPRIORITY_211,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h215"
hexmask.long 0x34C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x350 "INTPRIORITY_212,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h216"
hexmask.long 0x350 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x350 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x354 "INTPRIORITY_213,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h217"
hexmask.long 0x354 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x354 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x358 "INTPRIORITY_214,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h218"
hexmask.long 0x358 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x358 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x35C "INTPRIORITY_215,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h219"
hexmask.long 0x35C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x35C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x360 "INTPRIORITY_216,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h220"
hexmask.long 0x360 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x360 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x364 "INTPRIORITY_217,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h221"
hexmask.long 0x364 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x364 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x368 "INTPRIORITY_218,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h222"
hexmask.long 0x368 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x368 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x36C "INTPRIORITY_219,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h223"
hexmask.long 0x36C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x36C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x370 "INTPRIORITY_220,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h224"
hexmask.long 0x370 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x370 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x374 "INTPRIORITY_221,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h225"
hexmask.long 0x374 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x374 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x378 "INTPRIORITY_222,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h226"
hexmask.long 0x378 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x378 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x37C "INTPRIORITY_223,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h227"
hexmask.long 0x37C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x37C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x380 "INTPRIORITY_224,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h228"
hexmask.long 0x380 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x380 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x384 "INTPRIORITY_225,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h229"
hexmask.long 0x384 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x384 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x388 "INTPRIORITY_226,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h230"
hexmask.long 0x388 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x388 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38C "INTPRIORITY_227,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h231"
hexmask.long 0x38C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x390 "INTPRIORITY_228,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h232"
hexmask.long 0x390 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x390 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x394 "INTPRIORITY_229,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h233"
hexmask.long 0x394 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x394 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x398 "INTPRIORITY_230,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h234"
hexmask.long 0x398 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x398 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x39C "INTPRIORITY_231,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h235"
hexmask.long 0x39C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x39C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A0 "INTPRIORITY_232,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h236"
hexmask.long 0x3A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A4 "INTPRIORITY_233,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h237"
hexmask.long 0x3A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A8 "INTPRIORITY_234,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h238"
hexmask.long 0x3A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3AC "INTPRIORITY_235,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h239"
hexmask.long 0x3AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B0 "INTPRIORITY_236,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h240"
hexmask.long 0x3B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B4 "INTPRIORITY_237,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h241"
hexmask.long 0x3B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B8 "INTPRIORITY_238,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h242"
hexmask.long 0x3B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3BC "INTPRIORITY_239,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h243"
hexmask.long 0x3BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C0 "INTPRIORITY_240,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h244"
hexmask.long 0x3C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C4 "INTPRIORITY_241,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h245"
hexmask.long 0x3C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C8 "INTPRIORITY_242,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h246"
hexmask.long 0x3C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3CC "INTPRIORITY_243,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h247"
hexmask.long 0x3CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D0 "INTPRIORITY_244,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h248"
hexmask.long 0x3D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D4 "INTPRIORITY_245,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h249"
hexmask.long 0x3D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D8 "INTPRIORITY_246,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h250"
hexmask.long 0x3D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3DC "INTPRIORITY_247,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h251"
hexmask.long 0x3DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E0 "INTPRIORITY_248,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h252"
hexmask.long 0x3E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E4 "INTPRIORITY_249,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h253"
hexmask.long 0x3E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E8 "INTPRIORITY_250,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h254"
hexmask.long 0x3E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3EC "INTPRIORITY_251,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h255"
hexmask.long 0x3EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F0 "INTPRIORITY_252,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h256"
hexmask.long 0x3F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F4 "INTPRIORITY_253,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h257"
hexmask.long 0x3F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F8 "INTPRIORITY_254,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h258"
hexmask.long 0x3F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3FC "INTPRIORITY_255,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h259"
hexmask.long 0x3FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x3FF
line.long 0x00 "INTVECTOR,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h4"
hexmask.long 0x00 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x00 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x04 "INTVECTOR_1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
hexmask.long 0x04 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x04 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x08 "INTVECTOR_2,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h6"
hexmask.long 0x08 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x08 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x0C "INTVECTOR_3,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h7"
hexmask.long 0x0C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x0C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10 "INTVECTOR_4,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h8"
hexmask.long 0x10 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14 "INTVECTOR_5,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h9"
hexmask.long 0x14 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18 "INTVECTOR_6,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h10"
hexmask.long 0x18 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C "INTVECTOR_7,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h11"
hexmask.long 0x1C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20 "INTVECTOR_8,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h12"
hexmask.long 0x20 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24 "INTVECTOR_9,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h13"
hexmask.long 0x24 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28 "INTVECTOR_10,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h14"
hexmask.long 0x28 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C "INTVECTOR_11,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h15"
hexmask.long 0x2C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30 "INTVECTOR_12,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h16"
hexmask.long 0x30 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34 "INTVECTOR_13,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h17"
hexmask.long 0x34 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38 "INTVECTOR_14,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h18"
hexmask.long 0x38 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C "INTVECTOR_15,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h19"
hexmask.long 0x3C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x40 "INTVECTOR_16,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h20"
hexmask.long 0x40 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x40 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x44 "INTVECTOR_17,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h21"
hexmask.long 0x44 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x44 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x48 "INTVECTOR_18,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h22"
hexmask.long 0x48 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x48 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x4C "INTVECTOR_19,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h23"
hexmask.long 0x4C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x4C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x50 "INTVECTOR_20,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h24"
hexmask.long 0x50 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x50 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x54 "INTVECTOR_21,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h25"
hexmask.long 0x54 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x54 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x58 "INTVECTOR_22,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h26"
hexmask.long 0x58 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x58 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x5C "INTVECTOR_23,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h27"
hexmask.long 0x5C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x5C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x60 "INTVECTOR_24,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h28"
hexmask.long 0x60 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x60 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x64 "INTVECTOR_25,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h29"
hexmask.long 0x64 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x64 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x68 "INTVECTOR_26,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h30"
hexmask.long 0x68 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x68 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x6C "INTVECTOR_27,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h31"
hexmask.long 0x6C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x6C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x70 "INTVECTOR_28,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h32"
hexmask.long 0x70 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x70 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x74 "INTVECTOR_29,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h33"
hexmask.long 0x74 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x74 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x78 "INTVECTOR_30,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h34"
hexmask.long 0x78 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x78 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x7C "INTVECTOR_31,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h35"
hexmask.long 0x7C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x7C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x80 "INTVECTOR_32,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h36"
hexmask.long 0x80 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x80 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x84 "INTVECTOR_33,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h37"
hexmask.long 0x84 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x84 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x88 "INTVECTOR_34,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h38"
hexmask.long 0x88 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x88 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x8C "INTVECTOR_35,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h39"
hexmask.long 0x8C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x8C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x90 "INTVECTOR_36,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h40"
hexmask.long 0x90 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x90 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x94 "INTVECTOR_37,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h41"
hexmask.long 0x94 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x94 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x98 "INTVECTOR_38,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h42"
hexmask.long 0x98 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x98 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x9C "INTVECTOR_39,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h43"
hexmask.long 0x9C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x9C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA0 "INTVECTOR_40,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h44"
hexmask.long 0xA0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA4 "INTVECTOR_41,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h45"
hexmask.long 0xA4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA8 "INTVECTOR_42,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h46"
hexmask.long 0xA8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xAC "INTVECTOR_43,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h47"
hexmask.long 0xAC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xAC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB0 "INTVECTOR_44,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h48"
hexmask.long 0xB0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB4 "INTVECTOR_45,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h49"
hexmask.long 0xB4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB8 "INTVECTOR_46,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h50"
hexmask.long 0xB8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xBC "INTVECTOR_47,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h51"
hexmask.long 0xBC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xBC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC0 "INTVECTOR_48,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h52"
hexmask.long 0xC0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC4 "INTVECTOR_49,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h53"
hexmask.long 0xC4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC8 "INTVECTOR_50,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h54"
hexmask.long 0xC8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xCC "INTVECTOR_51,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h55"
hexmask.long 0xCC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xCC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD0 "INTVECTOR_52,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h56"
hexmask.long 0xD0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD4 "INTVECTOR_53,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h57"
hexmask.long 0xD4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD8 "INTVECTOR_54,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h58"
hexmask.long 0xD8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xDC "INTVECTOR_55,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h59"
hexmask.long 0xDC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xDC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE0 "INTVECTOR_56,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h60"
hexmask.long 0xE0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE4 "INTVECTOR_57,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h61"
hexmask.long 0xE4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE8 "INTVECTOR_58,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h62"
hexmask.long 0xE8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xEC "INTVECTOR_59,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h63"
hexmask.long 0xEC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xEC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF0 "INTVECTOR_60,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h64"
hexmask.long 0xF0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF4 "INTVECTOR_61,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h65"
hexmask.long 0xF4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF8 "INTVECTOR_62,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h66"
hexmask.long 0xF8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xFC "INTVECTOR_63,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h67"
hexmask.long 0xFC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xFC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x100 "INTVECTOR_64,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h68"
hexmask.long 0x100 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x100 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x104 "INTVECTOR_65,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h69"
hexmask.long 0x104 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x104 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x108 "INTVECTOR_66,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h70"
hexmask.long 0x108 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x108 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10C "INTVECTOR_67,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h71"
hexmask.long 0x10C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x110 "INTVECTOR_68,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h72"
hexmask.long 0x110 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x110 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x114 "INTVECTOR_69,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h73"
hexmask.long 0x114 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x114 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x118 "INTVECTOR_70,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h74"
hexmask.long 0x118 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x118 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x11C "INTVECTOR_71,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h75"
hexmask.long 0x11C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x11C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x120 "INTVECTOR_72,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h76"
hexmask.long 0x120 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x120 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x124 "INTVECTOR_73,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h77"
hexmask.long 0x124 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x124 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x128 "INTVECTOR_74,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h78"
hexmask.long 0x128 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x128 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x12C "INTVECTOR_75,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h79"
hexmask.long 0x12C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x12C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x130 "INTVECTOR_76,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h80"
hexmask.long 0x130 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x130 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x134 "INTVECTOR_77,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h81"
hexmask.long 0x134 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x134 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x138 "INTVECTOR_78,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h82"
hexmask.long 0x138 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x138 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x13C "INTVECTOR_79,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h83"
hexmask.long 0x13C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x13C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x140 "INTVECTOR_80,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h84"
hexmask.long 0x140 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x140 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x144 "INTVECTOR_81,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h85"
hexmask.long 0x144 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x144 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x148 "INTVECTOR_82,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h86"
hexmask.long 0x148 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x148 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14C "INTVECTOR_83,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h87"
hexmask.long 0x14C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x150 "INTVECTOR_84,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h88"
hexmask.long 0x150 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x150 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x154 "INTVECTOR_85,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h89"
hexmask.long 0x154 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x154 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x158 "INTVECTOR_86,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h90"
hexmask.long 0x158 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x158 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x15C "INTVECTOR_87,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h91"
hexmask.long 0x15C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x15C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x160 "INTVECTOR_88,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h92"
hexmask.long 0x160 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x160 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x164 "INTVECTOR_89,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h93"
hexmask.long 0x164 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x164 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x168 "INTVECTOR_90,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h94"
hexmask.long 0x168 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x168 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x16C "INTVECTOR_91,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h95"
hexmask.long 0x16C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x16C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x170 "INTVECTOR_92,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h96"
hexmask.long 0x170 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x170 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x174 "INTVECTOR_93,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h97"
hexmask.long 0x174 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x174 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x178 "INTVECTOR_94,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h98"
hexmask.long 0x178 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x178 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x17C "INTVECTOR_95,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h99"
hexmask.long 0x17C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x17C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x180 "INTVECTOR_96,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h100"
hexmask.long 0x180 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x180 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x184 "INTVECTOR_97,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h101"
hexmask.long 0x184 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x184 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x188 "INTVECTOR_98,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h102"
hexmask.long 0x188 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x188 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18C "INTVECTOR_99,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h103"
hexmask.long 0x18C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x190 "INTVECTOR_100,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h104"
hexmask.long 0x190 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x190 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x194 "INTVECTOR_101,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h105"
hexmask.long 0x194 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x194 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x198 "INTVECTOR_102,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h106"
hexmask.long 0x198 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x198 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x19C "INTVECTOR_103,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h107"
hexmask.long 0x19C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x19C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A0 "INTVECTOR_104,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h108"
hexmask.long 0x1A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A4 "INTVECTOR_105,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h109"
hexmask.long 0x1A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A8 "INTVECTOR_106,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h110"
hexmask.long 0x1A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1AC "INTVECTOR_107,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h111"
hexmask.long 0x1AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B0 "INTVECTOR_108,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h112"
hexmask.long 0x1B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B4 "INTVECTOR_109,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h113"
hexmask.long 0x1B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B8 "INTVECTOR_110,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h114"
hexmask.long 0x1B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1BC "INTVECTOR_111,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h115"
hexmask.long 0x1BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C0 "INTVECTOR_112,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h116"
hexmask.long 0x1C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C4 "INTVECTOR_113,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h117"
hexmask.long 0x1C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C8 "INTVECTOR_114,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h118"
hexmask.long 0x1C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1CC "INTVECTOR_115,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h119"
hexmask.long 0x1CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D0 "INTVECTOR_116,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h120"
hexmask.long 0x1D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D4 "INTVECTOR_117,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h121"
hexmask.long 0x1D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D8 "INTVECTOR_118,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h122"
hexmask.long 0x1D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1DC "INTVECTOR_119,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h123"
hexmask.long 0x1DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E0 "INTVECTOR_120,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h124"
hexmask.long 0x1E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E4 "INTVECTOR_121,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h125"
hexmask.long 0x1E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E8 "INTVECTOR_122,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h126"
hexmask.long 0x1E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1EC "INTVECTOR_123,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h127"
hexmask.long 0x1EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F0 "INTVECTOR_124,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h128"
hexmask.long 0x1F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F4 "INTVECTOR_125,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h129"
hexmask.long 0x1F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F8 "INTVECTOR_126,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h130"
hexmask.long 0x1F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1FC "INTVECTOR_127,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h131"
hexmask.long 0x1FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x200 "INTVECTOR_128,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h132"
hexmask.long 0x200 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x200 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x204 "INTVECTOR_129,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h133"
hexmask.long 0x204 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x204 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x208 "INTVECTOR_130,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h134"
hexmask.long 0x208 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x208 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20C "INTVECTOR_131,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h135"
hexmask.long 0x20C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x210 "INTVECTOR_132,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h136"
hexmask.long 0x210 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x210 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x214 "INTVECTOR_133,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h137"
hexmask.long 0x214 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x214 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x218 "INTVECTOR_134,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h138"
hexmask.long 0x218 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x218 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x21C "INTVECTOR_135,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h139"
hexmask.long 0x21C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x21C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x220 "INTVECTOR_136,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h140"
hexmask.long 0x220 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x220 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x224 "INTVECTOR_137,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h141"
hexmask.long 0x224 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x224 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x228 "INTVECTOR_138,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h142"
hexmask.long 0x228 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x228 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x22C "INTVECTOR_139,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h143"
hexmask.long 0x22C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x22C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x230 "INTVECTOR_140,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h144"
hexmask.long 0x230 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x230 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x234 "INTVECTOR_141,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h145"
hexmask.long 0x234 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x234 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x238 "INTVECTOR_142,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h146"
hexmask.long 0x238 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x238 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x23C "INTVECTOR_143,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h147"
hexmask.long 0x23C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x23C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x240 "INTVECTOR_144,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h148"
hexmask.long 0x240 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x240 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x244 "INTVECTOR_145,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h149"
hexmask.long 0x244 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x244 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x248 "INTVECTOR_146,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h150"
hexmask.long 0x248 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x248 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24C "INTVECTOR_147,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h151"
hexmask.long 0x24C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x250 "INTVECTOR_148,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h152"
hexmask.long 0x250 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x250 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x254 "INTVECTOR_149,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h153"
hexmask.long 0x254 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x254 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x258 "INTVECTOR_150,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h154"
hexmask.long 0x258 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x258 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x25C "INTVECTOR_151,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h155"
hexmask.long 0x25C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x25C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x260 "INTVECTOR_152,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h156"
hexmask.long 0x260 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x260 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x264 "INTVECTOR_153,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h157"
hexmask.long 0x264 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x264 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x268 "INTVECTOR_154,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h158"
hexmask.long 0x268 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x268 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x26C "INTVECTOR_155,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h159"
hexmask.long 0x26C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x26C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x270 "INTVECTOR_156,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h160"
hexmask.long 0x270 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x270 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x274 "INTVECTOR_157,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h161"
hexmask.long 0x274 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x274 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x278 "INTVECTOR_158,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h162"
hexmask.long 0x278 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x278 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x27C "INTVECTOR_159,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h163"
hexmask.long 0x27C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x27C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x280 "INTVECTOR_160,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h164"
hexmask.long 0x280 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x280 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x284 "INTVECTOR_161,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h165"
hexmask.long 0x284 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x284 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x288 "INTVECTOR_162,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h166"
hexmask.long 0x288 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x288 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28C "INTVECTOR_163,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h167"
hexmask.long 0x28C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x290 "INTVECTOR_164,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h168"
hexmask.long 0x290 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x290 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x294 "INTVECTOR_165,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h169"
hexmask.long 0x294 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x294 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x298 "INTVECTOR_166,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h170"
hexmask.long 0x298 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x298 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x29C "INTVECTOR_167,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h171"
hexmask.long 0x29C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x29C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A0 "INTVECTOR_168,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h172"
hexmask.long 0x2A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A4 "INTVECTOR_169,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h173"
hexmask.long 0x2A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A8 "INTVECTOR_170,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h174"
hexmask.long 0x2A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2AC "INTVECTOR_171,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h175"
hexmask.long 0x2AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B0 "INTVECTOR_172,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h176"
hexmask.long 0x2B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B4 "INTVECTOR_173,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h177"
hexmask.long 0x2B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B8 "INTVECTOR_174,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h178"
hexmask.long 0x2B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2BC "INTVECTOR_175,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h179"
hexmask.long 0x2BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C0 "INTVECTOR_176,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h180"
hexmask.long 0x2C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C4 "INTVECTOR_177,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h181"
hexmask.long 0x2C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C8 "INTVECTOR_178,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h182"
hexmask.long 0x2C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2CC "INTVECTOR_179,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h183"
hexmask.long 0x2CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D0 "INTVECTOR_180,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h184"
hexmask.long 0x2D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D4 "INTVECTOR_181,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h185"
hexmask.long 0x2D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D8 "INTVECTOR_182,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h186"
hexmask.long 0x2D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2DC "INTVECTOR_183,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h187"
hexmask.long 0x2DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E0 "INTVECTOR_184,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h188"
hexmask.long 0x2E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E4 "INTVECTOR_185,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h189"
hexmask.long 0x2E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E8 "INTVECTOR_186,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h190"
hexmask.long 0x2E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2EC "INTVECTOR_187,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h191"
hexmask.long 0x2EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F0 "INTVECTOR_188,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h192"
hexmask.long 0x2F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F4 "INTVECTOR_189,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h193"
hexmask.long 0x2F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F8 "INTVECTOR_190,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h194"
hexmask.long 0x2F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2FC "INTVECTOR_191,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h195"
hexmask.long 0x2FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x300 "INTVECTOR_192,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h196"
hexmask.long 0x300 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x300 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x304 "INTVECTOR_193,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h197"
hexmask.long 0x304 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x304 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x308 "INTVECTOR_194,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h198"
hexmask.long 0x308 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x308 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30C "INTVECTOR_195,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h199"
hexmask.long 0x30C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x310 "INTVECTOR_196,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h200"
hexmask.long 0x310 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x310 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x314 "INTVECTOR_197,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h201"
hexmask.long 0x314 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x314 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x318 "INTVECTOR_198,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h202"
hexmask.long 0x318 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x318 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x31C "INTVECTOR_199,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h203"
hexmask.long 0x31C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x31C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x320 "INTVECTOR_200,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h204"
hexmask.long 0x320 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x320 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x324 "INTVECTOR_201,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h205"
hexmask.long 0x324 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x324 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x328 "INTVECTOR_202,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h206"
hexmask.long 0x328 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x328 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x32C "INTVECTOR_203,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h207"
hexmask.long 0x32C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x32C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x330 "INTVECTOR_204,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h208"
hexmask.long 0x330 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x330 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x334 "INTVECTOR_205,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h209"
hexmask.long 0x334 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x334 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x338 "INTVECTOR_206,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h210"
hexmask.long 0x338 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x338 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x33C "INTVECTOR_207,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h211"
hexmask.long 0x33C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x33C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x340 "INTVECTOR_208,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h212"
hexmask.long 0x340 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x340 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x344 "INTVECTOR_209,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h213"
hexmask.long 0x344 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x344 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x348 "INTVECTOR_210,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h214"
hexmask.long 0x348 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x348 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34C "INTVECTOR_211,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h215"
hexmask.long 0x34C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x350 "INTVECTOR_212,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h216"
hexmask.long 0x350 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x350 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x354 "INTVECTOR_213,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h217"
hexmask.long 0x354 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x354 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x358 "INTVECTOR_214,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h218"
hexmask.long 0x358 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x358 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x35C "INTVECTOR_215,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h219"
hexmask.long 0x35C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x35C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x360 "INTVECTOR_216,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h220"
hexmask.long 0x360 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x360 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x364 "INTVECTOR_217,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h221"
hexmask.long 0x364 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x364 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x368 "INTVECTOR_218,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h222"
hexmask.long 0x368 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x368 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x36C "INTVECTOR_219,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h223"
hexmask.long 0x36C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x36C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x370 "INTVECTOR_220,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h224"
hexmask.long 0x370 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x370 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x374 "INTVECTOR_221,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h225"
hexmask.long 0x374 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x374 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x378 "INTVECTOR_222,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h226"
hexmask.long 0x378 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x378 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x37C "INTVECTOR_223,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h227"
hexmask.long 0x37C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x37C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x380 "INTVECTOR_224,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h228"
hexmask.long 0x380 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x380 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x384 "INTVECTOR_225,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h229"
hexmask.long 0x384 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x384 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x388 "INTVECTOR_226,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h230"
hexmask.long 0x388 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x388 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38C "INTVECTOR_227,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h231"
hexmask.long 0x38C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x390 "INTVECTOR_228,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h232"
hexmask.long 0x390 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x390 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x394 "INTVECTOR_229,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h233"
hexmask.long 0x394 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x394 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x398 "INTVECTOR_230,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h234"
hexmask.long 0x398 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x398 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x39C "INTVECTOR_231,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h235"
hexmask.long 0x39C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x39C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A0 "INTVECTOR_232,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h236"
hexmask.long 0x3A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A4 "INTVECTOR_233,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h237"
hexmask.long 0x3A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A8 "INTVECTOR_234,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h238"
hexmask.long 0x3A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3AC "INTVECTOR_235,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h239"
hexmask.long 0x3AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B0 "INTVECTOR_236,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h240"
hexmask.long 0x3B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B4 "INTVECTOR_237,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h241"
hexmask.long 0x3B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B8 "INTVECTOR_238,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h242"
hexmask.long 0x3B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3BC "INTVECTOR_239,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h243"
hexmask.long 0x3BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C0 "INTVECTOR_240,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h244"
hexmask.long 0x3C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C4 "INTVECTOR_241,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h245"
hexmask.long 0x3C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C8 "INTVECTOR_242,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h246"
hexmask.long 0x3C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3CC "INTVECTOR_243,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h247"
hexmask.long 0x3CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D0 "INTVECTOR_244,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h248"
hexmask.long 0x3D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D4 "INTVECTOR_245,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h249"
hexmask.long 0x3D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D8 "INTVECTOR_246,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h250"
hexmask.long 0x3D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3DC "INTVECTOR_247,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h251"
hexmask.long 0x3DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E0 "INTVECTOR_248,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h252"
hexmask.long 0x3E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E4 "INTVECTOR_249,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h253"
hexmask.long 0x3E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E8 "INTVECTOR_250,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h254"
hexmask.long 0x3E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3EC "INTVECTOR_251,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h255"
hexmask.long 0x3EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F0 "INTVECTOR_252,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h256"
hexmask.long 0x3F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F4 "INTVECTOR_253,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h257"
hexmask.long 0x3F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F8 "INTVECTOR_254,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h258"
hexmask.long 0x3F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3FC "INTVECTOR_255,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h259"
hexmask.long 0x3FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3FC 0.--1. "RES20,Reserved" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_WDT (MSS WDT Module Registers)"
base ad:0x2F7A300
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "RCSS_ATL (RCSS ATL Module Registers)"
base ad:0x5240000
rgroup.long 0x00++0x03
line.long 0x00 "REVISION,Peripheral Revision Register"
bitfld.long 0x00 30.--31. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x00 28.--29. "UNDEFINED_NAME," "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 11.--15. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "UNDEFINED_NAME," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x200++0x0B
line.long 0x00 "ATL0_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL0_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL0_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x210++0x0F
line.long 0x00 "ATL0_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL0_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL0_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL0_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
group.long 0x280++0x0B
line.long 0x00 "ATL1_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL1_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL1_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x290++0x0F
line.long 0x00 "ATL1_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL1_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL1_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL1_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
group.long 0x300++0x0B
line.long 0x00 "ATL2_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL2_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL2_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x310++0x0F
line.long 0x00 "ATL2_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL2_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL2_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL2_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
group.long 0x380++0x0B
line.long 0x00 "ATL3_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL3_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL3_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x390++0x0F
line.long 0x00 "ATL3_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL3_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL3_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL3_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
width 0x0B
tree.end
tree "RCSS_CSI2A (RCSS CSI2A Module Registers)"
base ad:0x5080000
rgroup.long 0x00++0x03
line.long 0x00 "CSI2_REVISION,MODULE REVISION This register contains the IP revision code in binary coded digital"
hexmask.long.tbyte 0x00 8.--31. 1. "RES1,RESERVE FIELD"
newline
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision"
group.long 0x10++0x0F
line.long 0x00 "CSI2_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES2,RESERVE FIELD"
newline
bitfld.long 0x00 12.--13. "MSTANDBY_MODE,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--11. 1. "RES3,RESERVE FIELD"
newline
bitfld.long 0x00 1. "SOFT_RESET,Software reset" "Normal mode,The module is reset"
newline
bitfld.long 0x00 0. "AUTO_IDLE,Internal OCP gating strategy" "OCP clock is free-running,Automatic OCP clock gating strategy is applied.."
line.long 0x04 "CSI2_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module excluding the interrupt status register"
hexmask.long 0x04 1.--31. 1. "RES4,RESERVE FIELD"
newline
bitfld.long 0x04 0. "RESET_DONE,Internal reset monitoring" "Internal module reset is on going,Reset completed"
line.long 0x08 "CSI2_IRQSTATUS,INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt"
hexmask.long.tbyte 0x08 15.--31. 1. "RES5,RESERVE FIELD"
newline
bitfld.long 0x08 14. "OCP_ERR_IRQ,OCP Error Interrupt" "READS,READS"
newline
bitfld.long 0x08 13. "SHORT_PACKET_IRQ,Short packet reception status (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "READS,READS"
newline
bitfld.long 0x08 12. "ECC_CORRECTION_IRQ,ECC has been used to do the correction of the only 1-bit error status (short packet only)" "READS,READS"
newline
bitfld.long 0x08 11. "ECC_NO_CORRECTION_IRQ,ECC error status (short and long packets)" "READS,READS"
newline
rbitfld.long 0x08 10. "COMPLEXIO2_ERR_IRQ,RESERVE FIELD" "0,1"
newline
bitfld.long 0x08 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: status of the PHY errors received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "READS,READS"
newline
bitfld.long 0x08 8. "FIFO_OVF_IRQ,FIFO overflow error status" "READS,READS"
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bitfld.long 0x08 7. "CONTEXT7,Context 7" "READS,READS"
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bitfld.long 0x08 6. "CONTEXT6,Context 6" "READS,READS"
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bitfld.long 0x08 5. "CONTEXT5,Context 5" "READS,READS"
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bitfld.long 0x08 4. "CONTEXT4,Context 4" "READS,READS"
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bitfld.long 0x08 3. "CONTEXT3,Context 3" "READS,READS"
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bitfld.long 0x08 2. "CONTEXT2,Context 2" "READS,READS"
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bitfld.long 0x08 1. "CONTEXT1,Context 1" "READS,READS"
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bitfld.long 0x08 0. "CONTEXT0,Context 0" "READS,READS"
line.long 0x0C "CSI2_IRQENABLE,INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually"
hexmask.long.tbyte 0x0C 15.--31. 1. "RES6,RESERVE FIELD"
newline
bitfld.long 0x0C 14. "OCP_ERR_IRQ,OCP Error Interrupt" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 13. "SHORT_PACKET_IRQ,Short packet reception (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 12. "ECC_CORRECTION_IRQ,ECC has been used to correct the only 1-bit error (short packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 11. "ECC_NO_CORRECTION_IRQ,ECC error (short and long packets)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 10. "COMPLEXIO2_ERR_IRQ,RESERVED" "0,1"
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bitfld.long 0x0C 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: the interrupt is triggered when any error is received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 8. "FIFO_OVF_IRQ,FIFO overflow enable" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 7. "CONTEXT7,Context 7" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 6. "CONTEXT6,Context 6" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 5. "CONTEXT5,Context 5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 4. "CONTEXT4,Context 4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 3. "CONTEXT3,Context 3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 2. "CONTEXT2,Context 2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 1. "CONTEXT1,Context 1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 0. "CONTEXT0,Context 0" "Event is masked,Event generates an interrupt when it occurs"
group.long 0x40++0x14B
line.long 0x00 "CSI2_CTRL,GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module"
hexmask.long.word 0x00 23.--31. 1. "RES7,RESERVE FIELD"
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bitfld.long 0x00 20.--22. "MFLAG_LEVH,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "MFLAG_LEVL,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "BURST_SIZE_EXPAND,Sets the DMA burst size on the L3 interconnect" "Use the burst size defined in the BURST_SIZE..,Allow generation of 16x64-bit bursts"
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bitfld.long 0x00 15. "VP_CLK_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 14. "STREAMING,Streaming mode" "Disable,Enable"
newline
bitfld.long 0x00 13. "NON_POSTED_WRITE,Not Posted Writes" "Disable,Enable"
newline
rbitfld.long 0x00 12. "RES8,RESERVE FIELD" "0,1"
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bitfld.long 0x00 11. "VP_ONLY_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 10. "STREAMING_32_BIT,Indicates if 64-bit or 32-bit streaming burst is used" "0,1"
newline
bitfld.long 0x00 8.--9. "VP_OUT_CTRL,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x00 7. "DBG_EN,Enables the debug mode" "Disable,Enable"
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bitfld.long 0x00 5.--6. "BURST_SIZE,Sets the DMA burst size on the L3 interconnect" "1x64 OCP writes,2x64 OCP writes,4x64 OCP writes,8x64 OCP writes"
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bitfld.long 0x00 4. "ENDIANNESS,Select endianness for YUV422 8 bit and YUV420 legacy formats" "Use native MIPI CSI2 endianness,Store all pixel formats little endian"
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bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "If IF_EN = 0 the interface is disabled immediately,If IF_EN = 1 the interface is disabled after all.."
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bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SECURE,RESERVE FIELD" "0,1"
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bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "The interface is disabled,The interface is enabled immediately the data.."
line.long 0x04 "CSI2_DBG_H,DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x08 "CSI2_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design"
hexmask.long 0x08 6.--31. 1. "RES9,RESERVE FIELD"
newline
bitfld.long 0x08 2.--5. "FIFODEPTH,Output FIFO size in multiple of 68 bits" "?,?,8x 68 bits,16x 68 bits,32x 68 bits,64x 68 bits,128 x 68 bits,256 x 68 bits,?..."
newline
bitfld.long 0x08 0.--1. "NBCONTEXTS,Number of contexts supported by the module" "1 Context,2 Contexts,4 Contexts,8 Contexts"
line.long 0x0C "CSI2_COMPLEXIO_CFG2,COMPLEX IO CONFIGURATION REGISTER for the complex IO #2 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x0C 31. "RES10,RESERVE FIELD" "0,1"
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bitfld.long 0x0C 30. "RESET_CTRL,RESERVE FIELD" "0,1"
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rbitfld.long 0x0C 29. "RESET_DONE,RESERVE FIELD" "0,1"
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bitfld.long 0x0C 27.--28. "PWR_CMD,RESERVE FIELD" "0,1,2,3"
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rbitfld.long 0x0C 25.--26. "PWR_STATUS,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x0C 24. "PWR_AUTO,RESERVE FIELD" "0,1"
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rbitfld.long 0x0C 20.--23. "RES11,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 19. "DATA4_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 16.--18. "DATA4_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 15. "DATA3_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 12.--14. "DATA3_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 11. "DATA2_POL,RESERVE FIELD" "0,1"
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bitfld.long 0x0C 8.--10. "DATA2_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 7. "DATA1_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 4.--6. "DATA1_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 3. "CLOCK_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 0.--2. "CLOCK_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
line.long 0x10 "CSI2_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex IO #1 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x10 31. "RES12,RESERVE FIELD" "0,1"
newline
bitfld.long 0x10 30. "RESET_CTRL,Controls the reset of the complex IO" "Complex IO reset active,Complex IO reset de-asserted"
newline
bitfld.long 0x10 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io" "Internal module reset is on going,Reset completed"
newline
bitfld.long 0x10 27.--28. "PWR_CMD,Command for power control of the complex io" "Command to change to OFF state,Command to change to ON state,Command to change to Ultra Low Power state,?..."
newline
bitfld.long 0x10 25.--26. "PWR_STATUS,Status of the power control of the complex io" "Complex IO in OFF state,Complex IO in ON state,Complex IO in Ultra Low Power state,?..."
newline
bitfld.long 0x10 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "Disable,Enable"
newline
rbitfld.long 0x10 20.--23. "RES13,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "Not used/connected,Data lane 4 is at the position 1,Data lane 4 is at the position 2,Data lane 4 is at the position 3,Data lane 4 is at the position 4,Data lane 4 is at the position 5,?..."
newline
bitfld.long 0x10 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "Not used/connected,Data lane 3 is at the position 1,Data lane 3 is at the position 2,Data lane 3 is at the position 3,Data lane 3 is at the position 4,Data lane 3 is at the position 5,?..."
newline
bitfld.long 0x10 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "Not used/connected,Data lane 2 is at the position 1,Data lane 2 is at the position 2,Data lane 2 is at the position 3,Data lane 2 is at the position 4,Data lane 2 is at the position 5,?..."
newline
bitfld.long 0x10 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,Data lane 1 is at the position 1,Data lane 1 is at the position 2,Data lane 1 is at the position 3,Data lane 1 is at the position 4,Data lane 1 is at the position 5,?..."
newline
bitfld.long 0x10 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,Clock lane is at the position 1,Clock lane is at the position 2,Clock lane is at the position 3,Clock lane is at the position 4,Clock lane is at the position 5,?..."
line.long 0x14 "CSI2_COMPLEXIO1_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #1"
rbitfld.long 0x14 27.--31. "RES14,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "READS,READS"
newline
bitfld.long 0x14 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "READS,READS"
newline
bitfld.long 0x14 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 19. "ERRCONTROL5,Control error for lane #5" "READS,READS"
newline
bitfld.long 0x14 18. "ERRCONTROL4,Control error for lane #4" "READS,READS"
newline
bitfld.long 0x14 17. "ERRCONTROL3,Control error for lane #3" "READS,READS"
newline
bitfld.long 0x14 16. "ERRCONTROL2,Control error for lane #2" "READS,READS"
newline
bitfld.long 0x14 15. "ERRCONTROL1,Control error for lane #1" "READS,READS"
newline
bitfld.long 0x14 14. "ERRESC5,Escape entry error for lane #5" "READS,READS"
newline
bitfld.long 0x14 13. "ERRESC4,Escape entry error for lane #4" "READS,READS"
newline
bitfld.long 0x14 12. "ERRESC3,Escape entry error for lane #3" "READS,READS"
newline
bitfld.long 0x14 11. "ERRESC2,Escape entry error for lane #2" "READS,READS"
newline
bitfld.long 0x14 10. "ERRESC1,Escape entry error for lane #1" "READS,READS"
newline
bitfld.long 0x14 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "READS,READS"
newline
bitfld.long 0x14 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "READS,READS"
newline
bitfld.long 0x14 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "READS,READS"
newline
bitfld.long 0x14 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "READS,READS"
newline
bitfld.long 0x14 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "READS,READS"
newline
bitfld.long 0x14 4. "ERRSOTHS5,Start of transmission error for lane #5" "READS,READS"
newline
bitfld.long 0x14 3. "ERRSOTHS4,Start of transmission error for lane #4" "READS,READS"
newline
bitfld.long 0x14 2. "ERRSOTHS3,Start of transmission error for lane #3" "READS,READS"
newline
bitfld.long 0x14 1. "ERRSOTHS2,Start of transmission error for lane #2" "READS,READS"
newline
bitfld.long 0x14 0. "ERRSOTHS1,Start of transmission error for lane #1" "READS,READS"
line.long 0x18 "CSI2_COMPLEXIO2_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #2"
rbitfld.long 0x18 27.--31. "RES15,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 24. "STATEULPM5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 23. "STATEULPM4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 21. "STATEULPM2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 20. "STATEULPM1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 14. "ERRESC5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 13. "ERRESC4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 12. "ERRESC3,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 11. "ERRESC2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 10. "ERRESC1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x1C "CSI2_SHORT_PACKET,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F"
hexmask.long.byte 0x1C 24.--31. 1. "RES16,RESERVE FIELD"
newline
hexmask.long.tbyte 0x1C 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD"
line.long 0x20 "CSI2_COMPLEXIO1_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #1"
rbitfld.long 0x20 27.--31. "RES17,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x20 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 19. "ERRCONTROL5,Control error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 18. "ERRCONTROL4,Control error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 17. "ERRCONTROL3,Control error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 16. "ERRCONTROL2,Control error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 15. "ERRCONTROL1,Control error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 14. "ERRESC5,Escape entry error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 13. "ERRESC4,Escape entry error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 12. "ERRESC3,Escape entry error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 11. "ERRESC2,Escape entry error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 10. "ERRESC1,Escape entry error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 4. "ERRSOTHS5,Start of transmission error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 3. "ERRSOTHS4,Start of transmission error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 2. "ERRSOTHS3,Start of transmission error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 1. "ERRSOTHS2,Start of transmission error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 0. "ERRSOTHS1,Start of transmission error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x24 "CSI2_COMPLEXIO2_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #2"
rbitfld.long 0x24 27.--31. "RES18,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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bitfld.long 0x24 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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bitfld.long 0x24 24. "STATEULPM5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 23. "STATEULPM4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 21. "STATEULPM2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 20. "STATEULPM1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 14. "ERRESC5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 13. "ERRESC4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 12. "ERRESC3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 11. "ERRESC2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 10. "ERRESC1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x28 "CSI2_DBG_P,DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x2C "CSI2_TIMING,TIMING REGISTER This register controls the CSI2 RECEIVER module"
bitfld.long 0x2C 31. "FORCE_RX_MODE_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 30. "STOP_STATE_X16_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 29. "STOP_STATE_X4_IO2,RESERVE FIELD" "0,1"
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hexmask.long.word 0x2C 16.--28. 1. "STOP_STATE_COUNTER_IO2,RESERVE FIELD"
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bitfld.long 0x2C 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal" "De-assertion of ForceRxMode,Assertion of ForceRxMode"
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bitfld.long 0x2C 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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bitfld.long 0x2C 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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hexmask.long.word 0x2C 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring"
line.long 0x30 "CSI2_CTX0_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x30 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x30 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x30 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x30 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x30 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x30 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x30 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x30 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x30 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x30 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x30 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x30 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x30 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x30 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x30 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x34 "CSI2_CTX0_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x34 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x34 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x34 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
newline
bitfld.long 0x34 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
newline
bitfld.long 0x34 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x34 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x38 "CSI2_CTX0_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x38 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x38 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
newline
rbitfld.long 0x38 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "CSI2_CTX0_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x3C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x3C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x40 "CSI2_CTX0_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x40 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x40 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "CSI2_CTX0_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x44 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x44 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x44 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x44 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x48 "CSI2_CTX0_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x48 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x48 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x48 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x48 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x48 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x48 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x48 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x48 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x48 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x48 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x4C "CSI2_CTX0_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x4C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x4C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x4C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x50 "CSI2_CTX1_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x50 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x50 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0x50 29. "RES19,RESERVE FIELD" "0,1"
newline
bitfld.long 0x50 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
newline
bitfld.long 0x50 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x50 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x50 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0x50 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0x50 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0x50 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0x50 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
newline
bitfld.long 0x50 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
newline
bitfld.long 0x50 2. "VP_FORCE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x50 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
newline
bitfld.long 0x50 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x54 "CSI2_CTX1_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x54 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x54 15. "RES20,RESERVE FIELD" "0,1"
newline
bitfld.long 0x54 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
newline
bitfld.long 0x54 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
newline
bitfld.long 0x54 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
newline
abitfld.long 0x54 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x58 "CSI2_CTX1_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x58 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x58 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x5C "CSI2_CTX1_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x5C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x5C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x60 "CSI2_CTX1_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x60 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x60 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "CSI2_CTX1_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x64 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x64 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x64 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x64 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x68 "CSI2_CTX1_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x68 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x68 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x68 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x68 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x68 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x68 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x68 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x68 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x68 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x68 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x6C "CSI2_CTX1_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x6C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x6C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x6C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x70 "CSI2_CTX2_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x70 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x70 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x70 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x70 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x70 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x70 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x70 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x70 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x70 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x70 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x70 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x70 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x70 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x70 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x70 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x74 "CSI2_CTX2_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x74 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x74 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x74 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x74 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x74 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x74 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x78 "CSI2_CTX2_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x78 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x78 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x7C "CSI2_CTX2_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x7C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x7C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x80 "CSI2_CTX2_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x80 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x80 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x84 "CSI2_CTX2_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x84 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x84 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x84 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x84 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x88 "CSI2_CTX2_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x88 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x88 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x88 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x88 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x88 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x88 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x88 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x88 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x88 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x88 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x8C "CSI2_CTX2_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x8C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x8C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x8C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x90 "CSI2_CTX3_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x90 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x90 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0x90 29. "RES19,RESERVE FIELD" "0,1"
newline
bitfld.long 0x90 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
newline
bitfld.long 0x90 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x90 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x90 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0x90 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0x90 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0x90 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0x90 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x90 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x90 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x90 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x90 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x94 "CSI2_CTX3_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x94 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x94 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x94 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x94 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x94 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x94 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x98 "CSI2_CTX3_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x98 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x98 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x9C "CSI2_CTX3_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x9C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x9C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA0 "CSI2_CTX3_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xA0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xA0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA4 "CSI2_CTX3_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xA4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0xA4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xA4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xA8 "CSI2_CTX3_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA8 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xA8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0xA8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0xA8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0xA8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0xA8 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xA8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0xA8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0xA8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0xA8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xAC "CSI2_CTX3_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xAC 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xAC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xAC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xB0 "CSI2_CTX4_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xB0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0xB0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xB0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xB0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xB0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xB0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xB0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xB0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xB0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xB0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xB0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xB0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xB0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xB4 "CSI2_CTX4_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xB4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xB4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xB4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xB4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xB4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xB4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xB8 "CSI2_CTX4_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xB8 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0xB8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xBC "CSI2_CTX4_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xBC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xBC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC0 "CSI2_CTX4_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xC0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xC0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC4 "CSI2_CTX4_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xC4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0xC4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xC4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xC8 "CSI2_CTX4_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC8 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0xC8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0xC8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0xC8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0xC8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0xC8 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0xC8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0xC8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0xC8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0xC8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xCC "CSI2_CTX4_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xCC 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0xCC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0xCC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xD0 "CSI2_CTX5_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xD0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0xD0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xD0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xD0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xD0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xD0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xD0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xD0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xD0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xD0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xD0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xD0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xD0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xD4 "CSI2_CTX5_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xD4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xD4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xD4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xD4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xD4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xD4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xD8 "CSI2_CTX5_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xD8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xD8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xDC "CSI2_CTX5_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xDC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xDC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE0 "CSI2_CTX5_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xE0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xE0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE4 "CSI2_CTX5_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xE4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0xE4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xE4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xE8 "CSI2_CTX5_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE8 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xE8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0xE8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0xE8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0xE8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0xE8 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xE8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0xE8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0xE8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0xE8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xEC "CSI2_CTX5_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xEC 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xEC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xEC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xF0 "CSI2_CTX6_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xF0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0xF0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xF0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xF0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xF0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xF0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xF0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xF0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xF0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xF0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xF0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xF0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xF0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xF0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xF0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xF4 "CSI2_CTX6_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xF4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xF4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xF4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xF4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xF4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xF4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xF8 "CSI2_CTX6_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xF8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xF8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xFC "CSI2_CTX6_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xFC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xFC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x100 "CSI2_CTX6_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x100 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x100 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x104 "CSI2_CTX6_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x104 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x104 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x104 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x104 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x108 "CSI2_CTX6_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x108 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x108 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x108 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x108 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x108 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x108 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x108 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x108 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x108 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x108 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x10C "CSI2_CTX6_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x10C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x10C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x10C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x110 "CSI2_CTX7_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x110 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x110 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x110 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x110 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x110 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x110 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x110 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x110 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x110 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x110 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x110 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x110 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x110 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x110 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x110 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x114 "CSI2_CTX7_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x114 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x114 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x114 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x114 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x114 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x114 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x118 "CSI2_CTX7_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x118 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x118 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x11C "CSI2_CTX7_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x11C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x11C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x120 "CSI2_CTX7_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x120 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x120 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x124 "CSI2_CTX7_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x124 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x124 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x124 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x124 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x128 "CSI2_CTX7_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x128 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x128 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x128 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x128 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x128 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x128 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x128 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x128 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x128 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x128 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x12C "CSI2_CTX7_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x12C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x12C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x12C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x130 "CSI2_PHY_CFG_REG0,"
hexmask.long.byte 0x130 24.--31. 1. "HS_CLK_CONFIG,Disable clock missing detector"
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hexmask.long.byte 0x130 16.--23. 1. "RESERVED,RESERVED"
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hexmask.long.byte 0x130 8.--15. 1. "THS_TERM,Ths-term timing parameter in multiples of DDR clock"
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hexmask.long.byte 0x130 0.--7. 1. "THS_SETTLE,THS-SETTLE timing parameter in multiples on DDR clock frequency"
line.long 0x134 "CSI2_PHY_CFG_REG1,"
bitfld.long 0x134 30.--31. "RSVD2,Reserved" "0,1,2,3"
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rbitfld.long 0x134 29. "RESETDONECTRLCLK,RESETDONECTRLCLK" "0,1"
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rbitfld.long 0x134 28. "RESETDONERXBYTECLK,RESETDONERXBYTECLK" "0,1"
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bitfld.long 0x134 26.--27. "RSVD1,Reserved" "0,1,2,3"
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rbitfld.long 0x134 25. "CLK_MISS_DET," "0,1"
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hexmask.long.byte 0x134 18.--24. 1. "TCLK_TERM,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + TCLK_TERM + ~ (1-15) ns Programmed value = ceil(9.5.."
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hexmask.long.byte 0x134 10.--17. 1. "D_PHY_HS_SYNC_PAT,DPHY mode HS sync pattern in byte order (reverse of RW 0xB8 received order) D-PHY mode sync pattern"
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bitfld.long 0x134 8.--9. "CTRLCLK_DIV_FACT,Divide factor for CTRLCLK for CLKMISS detector" "0,1,2,3"
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hexmask.long.byte 0x134 0.--7. 1. "TCLK_SETTLE,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~(1-2)* CTRLCLK + Tclk-settle + ~ (1 -15) ns Programmed value = max[3 ceil(155.."
line.long 0x138 "CSI2_PHY_CFG_REG2,"
bitfld.long 0x138 30.--31. "RXTRIGGERESC0,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "0,1,2,3"
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bitfld.long 0x138 28.--29. "RXTRIGGERESC1,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "0,1,2,3"
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bitfld.long 0x138 26.--27. "RXTRIGGERESC2,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2" "0,1,2,3"
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bitfld.long 0x138 24.--25. "RXTRIGGERESC3,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "0,1,2,3"
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hexmask.long.tbyte 0x138 0.--23. 1. "CCP2_SYNC_PAT,CCP2 mode sync pattern in byte order (reverse of received order)"
line.long 0x13C "CSI2_PHY_CFG_REG3,"
bitfld.long 0x13C 31. "OVR_ENHSRX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 26.--30. "ENHSRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 25. "OVR_ENRXTERM,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 20.--24. "ENRXTERM,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 19. "OVR_ENLPRX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 14.--18. "ENLPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 9.--13. "ENULPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 8. "OVR_ENLDO,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 7. "ENLDO,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 6. "OVR_ENBIAS,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 5. "ENBIAS,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 4. "OVR_ENCCP_TO_ANAT,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 3. "OVR_ENCCP_TO_HSRX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 2. "RSVD1,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 1. "RECAL_HS_RX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 0. "RECAL_BIAS,RESERVE FIELD" "0,1"
line.long 0x140 "CSI2_PHY_CFG_REG4,"
bitfld.long 0x140 27.--31. "TRIM_BIAS_GEN,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 22.--26. "TRIM_TERM_LANE4,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 17.--21. "TRIM_TERM_LANE3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 12.--16. "TRIM_TERM_LANE2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 7.--11. "TRIM_TERM_LANE1,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 2.--6. "TRIM_TERM_LANE0,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 1. "BYPASS_EFUSE,RESERVE FIELD" "0,1"
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bitfld.long 0x140 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x144 "CSI2_PHY_CFG_REG5,"
bitfld.long 0x144 26.--31. "TRIM_OFFSET_LANE4_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 20.--25. "TRIM_OFFSET_LANE3_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 14.--19. "TRIM_OFFSET_LANE2_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 8.--13. "TRIM_OFFSET_LANE1_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 2.--7. "TRIM_OFFSET_LANE0_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 1. "BYPASS_CALIB_OFFSET,RESERVE FIELD" "0,1"
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bitfld.long 0x144 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x148 "CSI2_PHY_CFG_REG6,"
hexmask.long.word 0x148 21.--31. 1. "RSVD2,RESERVE FIELD"
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bitfld.long 0x148 20. "OVR_AFE_LANE_ADR_POL,RESERVE FIELD" "0,1"
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hexmask.long.byte 0x148 12.--19. 1. "AFE_LANE_SEL,RESERVE FIELD"
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bitfld.long 0x148 11. "AFE_LANE_POL,RESERVE FIELD" "0,1"
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bitfld.long 0x148 10. "HSCOMOOUT,RESERVE FIELD" "0,1"
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bitfld.long 0x148 9. "BYPASS_LDO_REG,RESERVE FIELD" "0,1"
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bitfld.long 0x148 8. "OBSV_LDO_VOLT_DYA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 7. "OBSV_BIAS_CURR_DXA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 6. "RSVD1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 5. "BIASGEN_CAL_OVR,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 0.--4. "BIASGEN_CAL_OVR_VAL,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C0++0x3F
line.long 0x00 "CSI2_CTX0_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x00 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x00 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x04 "CSI2_CTX0_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x04 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x04 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x08 "CSI2_CTX1_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x08 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x08 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x0C "CSI2_CTX1_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x0C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x0C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x10 "CSI2_CTX2_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x10 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x10 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x14 "CSI2_CTX2_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x14 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x14 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x18 "CSI2_CTX3_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x18 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x18 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x1C "CSI2_CTX3_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x1C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x1C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x20 "CSI2_CTX4_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x20 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x20 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x24 "CSI2_CTX4_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x24 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x24 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x28 "CSI2_CTX5_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x28 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x28 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x2C "CSI2_CTX5_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x2C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x2C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x30 "CSI2_CTX6_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x30 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x30 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x34 "CSI2_CTX6_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x34 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x34 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x38 "CSI2_CTX7_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x38 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x38 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x3C "CSI2_CTX7_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x3C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x3C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
width 0x0B
tree.end
tree "RCSS_CSI2B (RCSS CSI2B Module Registers)"
base ad:0x50A0000
rgroup.long 0x00++0x03
line.long 0x00 "CSI2_REVISION,MODULE REVISION This register contains the IP revision code in binary coded digital"
hexmask.long.tbyte 0x00 8.--31. 1. "RES1,RESERVE FIELD"
newline
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision"
group.long 0x10++0x0F
line.long 0x00 "CSI2_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES2,RESERVE FIELD"
newline
bitfld.long 0x00 12.--13. "MSTANDBY_MODE,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--11. 1. "RES3,RESERVE FIELD"
newline
bitfld.long 0x00 1. "SOFT_RESET,Software reset" "Normal mode,The module is reset"
newline
bitfld.long 0x00 0. "AUTO_IDLE,Internal OCP gating strategy" "OCP clock is free-running,Automatic OCP clock gating strategy is applied.."
line.long 0x04 "CSI2_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module excluding the interrupt status register"
hexmask.long 0x04 1.--31. 1. "RES4,RESERVE FIELD"
newline
bitfld.long 0x04 0. "RESET_DONE,Internal reset monitoring" "Internal module reset is on going,Reset completed"
line.long 0x08 "CSI2_IRQSTATUS,INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt"
hexmask.long.tbyte 0x08 15.--31. 1. "RES5,RESERVE FIELD"
newline
bitfld.long 0x08 14. "OCP_ERR_IRQ,OCP Error Interrupt" "READS,READS"
newline
bitfld.long 0x08 13. "SHORT_PACKET_IRQ,Short packet reception status (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "READS,READS"
newline
bitfld.long 0x08 12. "ECC_CORRECTION_IRQ,ECC has been used to do the correction of the only 1-bit error status (short packet only)" "READS,READS"
newline
bitfld.long 0x08 11. "ECC_NO_CORRECTION_IRQ,ECC error status (short and long packets)" "READS,READS"
newline
rbitfld.long 0x08 10. "COMPLEXIO2_ERR_IRQ,RESERVE FIELD" "0,1"
newline
bitfld.long 0x08 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: status of the PHY errors received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "READS,READS"
newline
bitfld.long 0x08 8. "FIFO_OVF_IRQ,FIFO overflow error status" "READS,READS"
newline
bitfld.long 0x08 7. "CONTEXT7,Context 7" "READS,READS"
newline
bitfld.long 0x08 6. "CONTEXT6,Context 6" "READS,READS"
newline
bitfld.long 0x08 5. "CONTEXT5,Context 5" "READS,READS"
newline
bitfld.long 0x08 4. "CONTEXT4,Context 4" "READS,READS"
newline
bitfld.long 0x08 3. "CONTEXT3,Context 3" "READS,READS"
newline
bitfld.long 0x08 2. "CONTEXT2,Context 2" "READS,READS"
newline
bitfld.long 0x08 1. "CONTEXT1,Context 1" "READS,READS"
newline
bitfld.long 0x08 0. "CONTEXT0,Context 0" "READS,READS"
line.long 0x0C "CSI2_IRQENABLE,INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually"
hexmask.long.tbyte 0x0C 15.--31. 1. "RES6,RESERVE FIELD"
newline
bitfld.long 0x0C 14. "OCP_ERR_IRQ,OCP Error Interrupt" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 13. "SHORT_PACKET_IRQ,Short packet reception (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 12. "ECC_CORRECTION_IRQ,ECC has been used to correct the only 1-bit error (short packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 11. "ECC_NO_CORRECTION_IRQ,ECC error (short and long packets)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 10. "COMPLEXIO2_ERR_IRQ,RESERVED" "0,1"
newline
bitfld.long 0x0C 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: the interrupt is triggered when any error is received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 8. "FIFO_OVF_IRQ,FIFO overflow enable" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 7. "CONTEXT7,Context 7" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 6. "CONTEXT6,Context 6" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 5. "CONTEXT5,Context 5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 4. "CONTEXT4,Context 4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 3. "CONTEXT3,Context 3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 2. "CONTEXT2,Context 2" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 1. "CONTEXT1,Context 1" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 0. "CONTEXT0,Context 0" "Event is masked,Event generates an interrupt when it occurs"
group.long 0x40++0x14B
line.long 0x00 "CSI2_CTRL,GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module"
hexmask.long.word 0x00 23.--31. 1. "RES7,RESERVE FIELD"
newline
bitfld.long 0x00 20.--22. "MFLAG_LEVH,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--19. "MFLAG_LEVL,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16. "BURST_SIZE_EXPAND,Sets the DMA burst size on the L3 interconnect" "Use the burst size defined in the BURST_SIZE..,Allow generation of 16x64-bit bursts"
newline
bitfld.long 0x00 15. "VP_CLK_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 14. "STREAMING,Streaming mode" "Disable,Enable"
newline
bitfld.long 0x00 13. "NON_POSTED_WRITE,Not Posted Writes" "Disable,Enable"
newline
rbitfld.long 0x00 12. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 11. "VP_ONLY_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 10. "STREAMING_32_BIT,Indicates if 64-bit or 32-bit streaming burst is used" "0,1"
newline
bitfld.long 0x00 8.--9. "VP_OUT_CTRL,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x00 7. "DBG_EN,Enables the debug mode" "Disable,Enable"
newline
bitfld.long 0x00 5.--6. "BURST_SIZE,Sets the DMA burst size on the L3 interconnect" "1x64 OCP writes,2x64 OCP writes,4x64 OCP writes,8x64 OCP writes"
newline
bitfld.long 0x00 4. "ENDIANNESS,Select endianness for YUV422 8 bit and YUV420 legacy formats" "Use native MIPI CSI2 endianness,Store all pixel formats little endian"
newline
bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "If IF_EN = 0 the interface is disabled immediately,If IF_EN = 1 the interface is disabled after all.."
newline
bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SECURE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "The interface is disabled,The interface is enabled immediately the data.."
line.long 0x04 "CSI2_DBG_H,DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x08 "CSI2_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design"
hexmask.long 0x08 6.--31. 1. "RES9,RESERVE FIELD"
newline
bitfld.long 0x08 2.--5. "FIFODEPTH,Output FIFO size in multiple of 68 bits" "?,?,8x 68 bits,16x 68 bits,32x 68 bits,64x 68 bits,128 x 68 bits,256 x 68 bits,?..."
newline
bitfld.long 0x08 0.--1. "NBCONTEXTS,Number of contexts supported by the module" "1 Context,2 Contexts,4 Contexts,8 Contexts"
line.long 0x0C "CSI2_COMPLEXIO_CFG2,COMPLEX IO CONFIGURATION REGISTER for the complex IO #2 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x0C 31. "RES10,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 30. "RESET_CTRL,RESERVE FIELD" "0,1"
newline
rbitfld.long 0x0C 29. "RESET_DONE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 27.--28. "PWR_CMD,RESERVE FIELD" "0,1,2,3"
newline
rbitfld.long 0x0C 25.--26. "PWR_STATUS,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x0C 24. "PWR_AUTO,RESERVE FIELD" "0,1"
newline
rbitfld.long 0x0C 20.--23. "RES11,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 19. "DATA4_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 16.--18. "DATA4_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 15. "DATA3_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 12.--14. "DATA3_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 11. "DATA2_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 8.--10. "DATA2_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 7. "DATA1_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 4.--6. "DATA1_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 3. "CLOCK_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 0.--2. "CLOCK_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
line.long 0x10 "CSI2_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex IO #1 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x10 31. "RES12,RESERVE FIELD" "0,1"
newline
bitfld.long 0x10 30. "RESET_CTRL,Controls the reset of the complex IO" "Complex IO reset active,Complex IO reset de-asserted"
newline
bitfld.long 0x10 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io" "Internal module reset is on going,Reset completed"
newline
bitfld.long 0x10 27.--28. "PWR_CMD,Command for power control of the complex io" "Command to change to OFF state,Command to change to ON state,Command to change to Ultra Low Power state,?..."
newline
bitfld.long 0x10 25.--26. "PWR_STATUS,Status of the power control of the complex io" "Complex IO in OFF state,Complex IO in ON state,Complex IO in Ultra Low Power state,?..."
newline
bitfld.long 0x10 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "Disable,Enable"
newline
rbitfld.long 0x10 20.--23. "RES13,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "Not used/connected,Data lane 4 is at the position 1,Data lane 4 is at the position 2,Data lane 4 is at the position 3,Data lane 4 is at the position 4,Data lane 4 is at the position 5,?..."
newline
bitfld.long 0x10 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "Not used/connected,Data lane 3 is at the position 1,Data lane 3 is at the position 2,Data lane 3 is at the position 3,Data lane 3 is at the position 4,Data lane 3 is at the position 5,?..."
newline
bitfld.long 0x10 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "Not used/connected,Data lane 2 is at the position 1,Data lane 2 is at the position 2,Data lane 2 is at the position 3,Data lane 2 is at the position 4,Data lane 2 is at the position 5,?..."
newline
bitfld.long 0x10 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,Data lane 1 is at the position 1,Data lane 1 is at the position 2,Data lane 1 is at the position 3,Data lane 1 is at the position 4,Data lane 1 is at the position 5,?..."
newline
bitfld.long 0x10 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,Clock lane is at the position 1,Clock lane is at the position 2,Clock lane is at the position 3,Clock lane is at the position 4,Clock lane is at the position 5,?..."
line.long 0x14 "CSI2_COMPLEXIO1_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #1"
rbitfld.long 0x14 27.--31. "RES14,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "READS,READS"
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bitfld.long 0x14 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "READS,READS"
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bitfld.long 0x14 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 19. "ERRCONTROL5,Control error for lane #5" "READS,READS"
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bitfld.long 0x14 18. "ERRCONTROL4,Control error for lane #4" "READS,READS"
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bitfld.long 0x14 17. "ERRCONTROL3,Control error for lane #3" "READS,READS"
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bitfld.long 0x14 16. "ERRCONTROL2,Control error for lane #2" "READS,READS"
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bitfld.long 0x14 15. "ERRCONTROL1,Control error for lane #1" "READS,READS"
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bitfld.long 0x14 14. "ERRESC5,Escape entry error for lane #5" "READS,READS"
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bitfld.long 0x14 13. "ERRESC4,Escape entry error for lane #4" "READS,READS"
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bitfld.long 0x14 12. "ERRESC3,Escape entry error for lane #3" "READS,READS"
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bitfld.long 0x14 11. "ERRESC2,Escape entry error for lane #2" "READS,READS"
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bitfld.long 0x14 10. "ERRESC1,Escape entry error for lane #1" "READS,READS"
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bitfld.long 0x14 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "READS,READS"
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bitfld.long 0x14 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "READS,READS"
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bitfld.long 0x14 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "READS,READS"
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bitfld.long 0x14 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "READS,READS"
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bitfld.long 0x14 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "READS,READS"
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bitfld.long 0x14 4. "ERRSOTHS5,Start of transmission error for lane #5" "READS,READS"
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bitfld.long 0x14 3. "ERRSOTHS4,Start of transmission error for lane #4" "READS,READS"
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bitfld.long 0x14 2. "ERRSOTHS3,Start of transmission error for lane #3" "READS,READS"
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bitfld.long 0x14 1. "ERRSOTHS2,Start of transmission error for lane #2" "READS,READS"
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bitfld.long 0x14 0. "ERRSOTHS1,Start of transmission error for lane #1" "READS,READS"
line.long 0x18 "CSI2_COMPLEXIO2_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #2"
rbitfld.long 0x18 27.--31. "RES15,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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bitfld.long 0x18 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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bitfld.long 0x18 24. "STATEULPM5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 23. "STATEULPM4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 21. "STATEULPM2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 20. "STATEULPM1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 14. "ERRESC5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 13. "ERRESC4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 12. "ERRESC3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 11. "ERRESC2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 10. "ERRESC1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x1C "CSI2_SHORT_PACKET,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F"
hexmask.long.byte 0x1C 24.--31. 1. "RES16,RESERVE FIELD"
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hexmask.long.tbyte 0x1C 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD"
line.long 0x20 "CSI2_COMPLEXIO1_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #1"
rbitfld.long 0x20 27.--31. "RES17,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 19. "ERRCONTROL5,Control error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 18. "ERRCONTROL4,Control error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 17. "ERRCONTROL3,Control error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 16. "ERRCONTROL2,Control error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 15. "ERRCONTROL1,Control error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 14. "ERRESC5,Escape entry error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 13. "ERRESC4,Escape entry error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 12. "ERRESC3,Escape entry error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 11. "ERRESC2,Escape entry error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 10. "ERRESC1,Escape entry error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 4. "ERRSOTHS5,Start of transmission error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 3. "ERRSOTHS4,Start of transmission error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 2. "ERRSOTHS3,Start of transmission error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 1. "ERRSOTHS2,Start of transmission error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 0. "ERRSOTHS1,Start of transmission error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x24 "CSI2_COMPLEXIO2_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #2"
rbitfld.long 0x24 27.--31. "RES18,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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bitfld.long 0x24 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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bitfld.long 0x24 24. "STATEULPM5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 23. "STATEULPM4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 21. "STATEULPM2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 20. "STATEULPM1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 14. "ERRESC5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 13. "ERRESC4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 12. "ERRESC3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 11. "ERRESC2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 10. "ERRESC1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x28 "CSI2_DBG_P,DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x2C "CSI2_TIMING,TIMING REGISTER This register controls the CSI2 RECEIVER module"
bitfld.long 0x2C 31. "FORCE_RX_MODE_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 30. "STOP_STATE_X16_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 29. "STOP_STATE_X4_IO2,RESERVE FIELD" "0,1"
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hexmask.long.word 0x2C 16.--28. 1. "STOP_STATE_COUNTER_IO2,RESERVE FIELD"
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bitfld.long 0x2C 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal" "De-assertion of ForceRxMode,Assertion of ForceRxMode"
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bitfld.long 0x2C 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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bitfld.long 0x2C 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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hexmask.long.word 0x2C 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring"
line.long 0x30 "CSI2_CTX0_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x30 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x30 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x30 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x30 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x30 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x30 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x30 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x30 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x30 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x30 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x30 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x30 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x30 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x30 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x30 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x34 "CSI2_CTX0_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x34 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x34 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x34 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x34 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x34 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x34 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x38 "CSI2_CTX0_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x38 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x38 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
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rbitfld.long 0x38 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "CSI2_CTX0_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x3C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x3C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x40 "CSI2_CTX0_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x40 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x40 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "CSI2_CTX0_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x44 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x44 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x44 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x44 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x48 "CSI2_CTX0_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x48 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x48 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x48 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x48 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x48 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x48 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x48 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x48 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x48 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x48 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x4C "CSI2_CTX0_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x4C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x4C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x4C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x50 "CSI2_CTX1_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x50 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x50 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x50 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x50 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x50 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x50 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x50 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x50 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x50 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x50 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x50 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x50 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x50 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x50 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x50 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x54 "CSI2_CTX1_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x54 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x54 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x54 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x54 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x54 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x54 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x58 "CSI2_CTX1_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x58 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x58 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x5C "CSI2_CTX1_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x5C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x5C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x60 "CSI2_CTX1_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x60 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x60 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "CSI2_CTX1_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x64 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x64 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x64 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x64 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x68 "CSI2_CTX1_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x68 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x68 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x68 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x68 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x68 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x68 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x68 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x68 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x68 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x68 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x6C "CSI2_CTX1_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x6C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x6C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x6C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x70 "CSI2_CTX2_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x70 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x70 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0x70 29. "RES19,RESERVE FIELD" "0,1"
newline
bitfld.long 0x70 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
newline
bitfld.long 0x70 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x70 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x70 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0x70 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0x70 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0x70 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0x70 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
newline
bitfld.long 0x70 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
newline
bitfld.long 0x70 2. "VP_FORCE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x70 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
newline
bitfld.long 0x70 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x74 "CSI2_CTX2_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x74 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x74 15. "RES20,RESERVE FIELD" "0,1"
newline
bitfld.long 0x74 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
newline
bitfld.long 0x74 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
newline
bitfld.long 0x74 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
newline
abitfld.long 0x74 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x78 "CSI2_CTX2_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x78 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x78 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x7C "CSI2_CTX2_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x7C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x7C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x80 "CSI2_CTX2_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x80 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x80 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x84 "CSI2_CTX2_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x84 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x84 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x84 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x84 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x88 "CSI2_CTX2_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x88 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x88 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x88 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x88 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x88 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x88 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x88 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x88 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x88 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x88 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x8C "CSI2_CTX2_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x8C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x8C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x8C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x90 "CSI2_CTX3_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x90 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x90 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x90 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x90 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x90 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x90 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x90 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x90 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x90 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x90 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x90 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x90 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x90 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x90 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x90 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x94 "CSI2_CTX3_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x94 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x94 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x94 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x94 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x94 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x94 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x98 "CSI2_CTX3_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x98 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x98 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x9C "CSI2_CTX3_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x9C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x9C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA0 "CSI2_CTX3_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xA0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xA0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA4 "CSI2_CTX3_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xA4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0xA4 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0xA4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xA8 "CSI2_CTX3_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA8 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0xA8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0xA8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0xA8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0xA8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0xA8 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0xA8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0xA8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0xA8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0xA8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xAC "CSI2_CTX3_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xAC 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0xAC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xAC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xB0 "CSI2_CTX4_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xB0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0xB0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0xB0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xB0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0xB0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0xB0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0xB0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0xB0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0xB0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0xB0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xB0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xB0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xB0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xB4 "CSI2_CTX4_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xB4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xB4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xB4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xB4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xB4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xB4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xB8 "CSI2_CTX4_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xB8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xB8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xBC "CSI2_CTX4_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xBC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xBC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC0 "CSI2_CTX4_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xC0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xC0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC4 "CSI2_CTX4_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xC4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0xC4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xC4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xC8 "CSI2_CTX4_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC8 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xC8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0xC8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0xC8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0xC8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0xC8 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xC8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0xC8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0xC8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0xC8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xCC "CSI2_CTX4_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xCC 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xCC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xCC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xD0 "CSI2_CTX5_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xD0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0xD0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xD0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xD0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xD0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xD0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xD0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xD0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xD0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xD0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xD0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xD0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xD0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xD4 "CSI2_CTX5_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xD4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xD4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xD4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xD4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xD4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xD4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xD8 "CSI2_CTX5_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xD8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xD8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xDC "CSI2_CTX5_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xDC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xDC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE0 "CSI2_CTX5_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xE0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xE0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE4 "CSI2_CTX5_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xE4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0xE4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xE4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xE8 "CSI2_CTX5_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE8 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0xE8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0xE8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0xE8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0xE8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0xE8 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0xE8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0xE8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0xE8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0xE8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xEC "CSI2_CTX5_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xEC 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0xEC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0xEC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xF0 "CSI2_CTX6_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xF0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0xF0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xF0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xF0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xF0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0xF0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xF0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xF0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xF0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xF0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0xF0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xF0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xF0 2. "VP_FORCE,RESERVE FIELD" "0,1"
newline
bitfld.long 0xF0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xF0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xF4 "CSI2_CTX6_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xF4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xF4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xF4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xF4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xF4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xF4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xF8 "CSI2_CTX6_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xF8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xF8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xFC "CSI2_CTX6_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xFC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xFC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x100 "CSI2_CTX6_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x100 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x100 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x104 "CSI2_CTX6_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x104 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x104 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x104 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x104 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x104 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x104 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x108 "CSI2_CTX6_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x108 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x108 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x108 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x108 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x108 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x108 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x108 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x108 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x108 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x108 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x10C "CSI2_CTX6_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x10C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x10C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x10C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x110 "CSI2_CTX7_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x110 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x110 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x110 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x110 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x110 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x110 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x110 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x110 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x110 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x110 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x110 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x110 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x110 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x110 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x110 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x114 "CSI2_CTX7_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x114 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x114 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x114 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x114 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x114 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
newline
abitfld.long 0x114 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x118 "CSI2_CTX7_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x118 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x118 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x11C "CSI2_CTX7_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x11C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x11C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x120 "CSI2_CTX7_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x120 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x120 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x124 "CSI2_CTX7_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x124 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x124 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x124 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x124 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x128 "CSI2_CTX7_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x128 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x128 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x128 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x128 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x128 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x128 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x128 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x128 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x128 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x128 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x12C "CSI2_CTX7_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x12C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x12C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x12C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x130 "CSI2_PHY_CFG_REG0,"
hexmask.long.byte 0x130 24.--31. 1. "HS_CLK_CONFIG,Disable clock missing detector"
newline
hexmask.long.byte 0x130 16.--23. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x130 8.--15. 1. "THS_TERM,Ths-term timing parameter in multiples of DDR clock"
newline
hexmask.long.byte 0x130 0.--7. 1. "THS_SETTLE,THS-SETTLE timing parameter in multiples on DDR clock frequency"
line.long 0x134 "CSI2_PHY_CFG_REG1,"
bitfld.long 0x134 30.--31. "RSVD2,Reserved" "0,1,2,3"
newline
rbitfld.long 0x134 29. "RESETDONECTRLCLK,RESETDONECTRLCLK" "0,1"
newline
rbitfld.long 0x134 28. "RESETDONERXBYTECLK,RESETDONERXBYTECLK" "0,1"
newline
bitfld.long 0x134 26.--27. "RSVD1,Reserved" "0,1,2,3"
newline
rbitfld.long 0x134 25. "CLK_MISS_DET," "0,1"
newline
hexmask.long.byte 0x134 18.--24. 1. "TCLK_TERM,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + TCLK_TERM + ~ (1-15) ns Programmed value = ceil(9.5.."
newline
hexmask.long.byte 0x134 10.--17. 1. "D_PHY_HS_SYNC_PAT,DPHY mode HS sync pattern in byte order (reverse of RW 0xB8 received order) D-PHY mode sync pattern"
newline
bitfld.long 0x134 8.--9. "CTRLCLK_DIV_FACT,Divide factor for CTRLCLK for CLKMISS detector" "0,1,2,3"
newline
hexmask.long.byte 0x134 0.--7. 1. "TCLK_SETTLE,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~(1-2)* CTRLCLK + Tclk-settle + ~ (1 -15) ns Programmed value = max[3 ceil(155.."
line.long 0x138 "CSI2_PHY_CFG_REG2,"
bitfld.long 0x138 30.--31. "RXTRIGGERESC0,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "0,1,2,3"
newline
bitfld.long 0x138 28.--29. "RXTRIGGERESC1,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "0,1,2,3"
newline
bitfld.long 0x138 26.--27. "RXTRIGGERESC2,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2" "0,1,2,3"
newline
bitfld.long 0x138 24.--25. "RXTRIGGERESC3,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "0,1,2,3"
newline
hexmask.long.tbyte 0x138 0.--23. 1. "CCP2_SYNC_PAT,CCP2 mode sync pattern in byte order (reverse of received order)"
line.long 0x13C "CSI2_PHY_CFG_REG3,"
bitfld.long 0x13C 31. "OVR_ENHSRX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 26.--30. "ENHSRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 25. "OVR_ENRXTERM,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 20.--24. "ENRXTERM,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 19. "OVR_ENLPRX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 14.--18. "ENLPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 9.--13. "ENULPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 8. "OVR_ENLDO,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 7. "ENLDO,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 6. "OVR_ENBIAS,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 5. "ENBIAS,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 4. "OVR_ENCCP_TO_ANAT,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 3. "OVR_ENCCP_TO_HSRX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 2. "RSVD1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 1. "RECAL_HS_RX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 0. "RECAL_BIAS,RESERVE FIELD" "0,1"
line.long 0x140 "CSI2_PHY_CFG_REG4,"
bitfld.long 0x140 27.--31. "TRIM_BIAS_GEN,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 22.--26. "TRIM_TERM_LANE4,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 17.--21. "TRIM_TERM_LANE3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 12.--16. "TRIM_TERM_LANE2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 7.--11. "TRIM_TERM_LANE1,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 2.--6. "TRIM_TERM_LANE0,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 1. "BYPASS_EFUSE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x140 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x144 "CSI2_PHY_CFG_REG5,"
bitfld.long 0x144 26.--31. "TRIM_OFFSET_LANE4_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 20.--25. "TRIM_OFFSET_LANE3_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 14.--19. "TRIM_OFFSET_LANE2_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 8.--13. "TRIM_OFFSET_LANE1_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 2.--7. "TRIM_OFFSET_LANE0_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 1. "BYPASS_CALIB_OFFSET,RESERVE FIELD" "0,1"
newline
bitfld.long 0x144 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x148 "CSI2_PHY_CFG_REG6,"
hexmask.long.word 0x148 21.--31. 1. "RSVD2,RESERVE FIELD"
newline
bitfld.long 0x148 20. "OVR_AFE_LANE_ADR_POL,RESERVE FIELD" "0,1"
newline
hexmask.long.byte 0x148 12.--19. 1. "AFE_LANE_SEL,RESERVE FIELD"
newline
bitfld.long 0x148 11. "AFE_LANE_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 10. "HSCOMOOUT,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 9. "BYPASS_LDO_REG,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 8. "OBSV_LDO_VOLT_DYA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 7. "OBSV_BIAS_CURR_DXA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 6. "RSVD1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 5. "BIASGEN_CAL_OVR,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 0.--4. "BIASGEN_CAL_OVR_VAL,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C0++0x3F
line.long 0x00 "CSI2_CTX0_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x00 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x00 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x04 "CSI2_CTX0_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x04 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x04 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x08 "CSI2_CTX1_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x08 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x08 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x0C "CSI2_CTX1_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x0C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x0C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x10 "CSI2_CTX2_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x10 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x10 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x14 "CSI2_CTX2_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x14 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x14 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x18 "CSI2_CTX3_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x18 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x18 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x1C "CSI2_CTX3_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x1C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x1C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x20 "CSI2_CTX4_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x20 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x20 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x24 "CSI2_CTX4_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x24 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x24 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x28 "CSI2_CTX5_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x28 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x28 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x2C "CSI2_CTX5_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x2C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x2C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x30 "CSI2_CTX6_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x30 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x30 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x34 "CSI2_CTX6_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x34 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x34 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x38 "CSI2_CTX7_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x38 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x38 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x3C "CSI2_CTX7_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x3C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x3C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
width 0x0B
tree.end
tree "RCSS_CTRL (RCSS Control Module Registers)"
base ad:0x5020000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x257
line.long 0x00 "RCSS_TPCC_A_ERRAGG_MASK,"
bitfld.long 0x00 26. "tptc_a1_read_access_error,Mask Error from RCSS_TPTC_A1 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 25. "tptc_a0_read_access_error,Mask Error from RCSS_TPTC_A0 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 24. "tpcc_a_read_access_error,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 18. "tptc_a1_write_access_error,Mask Error from RCSS_TPTC_A1 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 17. "tptc_a0_write_access_error,Mask Error from RCSS_TPTC_A0 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 16. "tpcc_a_write_access_error,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 8. "tpcc_a_parity_err,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 3. "tptc_a1_err,Mask Error from RCSS_TPTC_A1 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 2. "tptc_a0_err,Mask Error from RCSS_TPTC_A0 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 1. "tpcc_a_mpint,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 0. "tpcc_a_errint,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x04 "RCSS_TPCC_A_ERRAGG_STATUS,"
bitfld.long 0x04 26. "tptc_a1_read_access_error,Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x04 25. "tptc_a0_read_access_error,Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x04 24. "tpcc_a_read_access_error,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 18. "tptc_a1_write_access_error,Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x04 17. "tptc_a0_write_access_error,Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x04 16. "tpcc_a_write_access_error,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 8. "tpcc_a_parity_err,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 3. "tptc_a1_err,Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x04 2. "tptc_a0_err,Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x04 1. "tpcc_a_mpint,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 0. "tpcc_a_errint,Status of Error from RCSS_TPCC_A" "0,1"
line.long 0x08 "RCSS_TPCC_A_ERRAGG_STATUS_RAW,"
bitfld.long 0x08 26. "tptc_a1_read_access_error,Raw Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 25. "tptc_a0_read_access_error,Raw Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 24. "tpcc_a_read_access_error,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 18. "tptc_a1_write_access_error,Raw Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 17. "tptc_a0_write_access_error,Raw Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 16. "tpcc_a_write_access_error,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 8. "tpcc_a_parity_err,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 3. "tptc_a1_err,Raw Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 2. "tptc_a0_err,Raw Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 1. "tpcc_a_mpint,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 0. "tpcc_a_errint,Raw Status of Error from RCSS_TPCC_A" "0,1"
line.long 0x0C "RCSS_TPCC_A_INTAGG_MASK,"
bitfld.long 0x0C 17. "tptc_a1,Mask Interrupt from TPTC A1 to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 16. "tptc_a0,Mask Interrupt from TPTC A0 to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 8. "tpcc_a_int7,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 7. "tpcc_a_int6,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 6. "tpcc_a_int5,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 5. "tpcc_a_int4,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 4. "tpcc_a_int3,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 3. "tpcc_a_int2,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 2. "tpcc_a_int1,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 1. "tpcc_a_int0,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 0. "tpcc_a_intg,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x10 "RCSS_TPCC_A_INTAGG_STATUS,"
bitfld.long 0x10 17. "tptc_a1,Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x10 16. "tptc_a0,Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x10 8. "tpcc_a_int7,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 7. "tpcc_a_int6,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 6. "tpcc_a_int5,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 5. "tpcc_a_int4,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 4. "tpcc_a_int3,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 3. "tpcc_a_int2,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 2. "tpcc_a_int1,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 1. "tpcc_a_int0,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 0. "tpcc_a_intg,Status of Interrupt from RCSS_TPCC_A" "0,1"
line.long 0x14 "RCSS_TPCC_A_INTAGG_STATUS_RAW,"
bitfld.long 0x14 17. "tptc_a1,Raw Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x14 16. "tptc_a0,Raw Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x14 8. "tpcc_a_int7,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 7. "tpcc_a_int6,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 6. "tpcc_a_int5,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 5. "tpcc_a_int4,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 4. "tpcc_a_int3,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 3. "tpcc_a_int2,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 2. "tpcc_a_int1,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 1. "tpcc_a_int0,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 0. "tpcc_a_intg,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
line.long 0x18 "RCSS_SPI_TRIG_SRC,"
hexmask.long.word 0x18 16.--27. 1. "trig_spib,Trigger sources for RCSS SPIB"
newline
hexmask.long.word 0x18 0.--11. 1. "trig_spia,Trigger sources for RCSS SPIA"
line.long 0x1C "RCSS_SPIA_MEMINIT,"
bitfld.long 0x1C 0. "mem0_init,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x20 "RCSS_SPIA_MEMINIT_DONE,"
bitfld.long 0x20 0. "mem0_done,Status field" "0,1"
line.long 0x24 "RCSS_SPIA_MEMINIT_STATUS,"
bitfld.long 0x24 0. "mem0_status,Status field" "0,1"
line.long 0x28 "RCSS_SPIB_MEMINIT,"
bitfld.long 0x28 0. "mem0_init,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x2C "RCSS_SPIB_MEMINIT_DONE,"
bitfld.long 0x2C 0. "mem0_done,Status field" "0,1"
line.long 0x30 "RCSS_SPIB_MEMINIT_STATUS,"
bitfld.long 0x30 0. "mem0_status,Status field" "0,1"
line.long 0x34 "RCSS_TPCC_MEMINIT_START,"
bitfld.long 0x34 0. "tpcc_a_meminit_start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x38 "RCSS_TPCC_MEMINIT_DONE,"
bitfld.long 0x38 0. "tpcc_a_meminit_done,Status field" "0,1"
line.long 0x3C "RCSS_TPCC_MEMINIT_STATUS,"
bitfld.long 0x3C 0. "tpcc_a_meminit_status,Status field" "0,1"
line.long 0x40 "RCSS_SPIA_CFG,"
bitfld.long 0x40 24. "spia_int_trig_polarity,Trigger source polarity select" "Polarity 0,Polarity 1"
newline
bitfld.long 0x40 16. "spia_trig_gate_en,Trigger Gate Enable" "0,1"
newline
bitfld.long 0x40 8. "spia_cs_trigsrc_en,Chip Select Trigger SRC enable Wrie 0x1 to Use CS as trigger source" "0,1"
newline
bitfld.long 0x40 0.--2. "spiasync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x44 "RCSS_SPIB_CFG,"
bitfld.long 0x44 24. "spib_int_trig_polarity,Trigger source polarity select" "Polarity 0,Polarity 1"
newline
bitfld.long 0x44 16. "spib_trig_gate_en,Trigger Gate Enable" "0,1"
newline
bitfld.long 0x44 8. "spib_cs_trigsrc_en,Chip Select Trigger SRC enable Wrie 0x1 to Use CS as trigger source" "0,1"
newline
bitfld.long 0x44 0.--2. "spibsync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x48 "RCSS_SPIA_IOCFG,"
bitfld.long 0x48 16.--18. "miso_oen_by_cs,SPI MISO Output Enable Control based on Chip select CS" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
newline
bitfld.long 0x48 8.--10. "cs_pol,SPI CS polarity-slave mode" "Active low,Active high,?..."
newline
bitfld.long 0x48 0.--2. "cs_deact,Chip Select Deactivate" "0,1,2,3,4,5,6,7"
line.long 0x4C "RCSS_SPIB_IOCFG,"
bitfld.long 0x4C 16.--18. "miso_oen_by_cs,SPI MISO Output Enable Control based on Chip select CS" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
newline
bitfld.long 0x4C 8.--10. "cs_pol,SPI CS polarity-slave mode" "Active low,Active high,?..."
newline
bitfld.long 0x4C 0.--2. "cs_deact,Chip Select Deactivate" "0,1,2,3,4,5,6,7"
line.long 0x50 "RCSS_SPI_HOST_IRQ,"
bitfld.long 0x50 0.--2. "host_irq,TI internal reserved for R&D" "0,1,2,3,4,5,6,7"
line.long 0x54 "TPTC_DBS_CFG,"
bitfld.long 0x54 2.--3. "tptc_a1,Max Burst size tieoff value for TPTC A1" "0,1,2,3"
newline
bitfld.long 0x54 0.--1. "tptc_a0,Max Burst size tieoff value for TPTC A0" "0,1,2,3"
line.long 0x58 "RCSS_TPCC_A_PARITY_CTRL,"
bitfld.long 0x58 2. "parity_err_clr,Write pulse bit field: Write 0x1 to clear the Parit Error status for TPCC" "0,1"
newline
bitfld.long 0x58 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
newline
bitfld.long 0x58 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x5C "RCSS_TPCC_A_PARITY_STATUS,"
hexmask.long.byte 0x5C 8.--15. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x60 "RCSS_CSI2A_CFG,"
bitfld.long 0x60 28.--30. "sof_intr1_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2A_SOF_INT1" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x60 24.--26. "sof_intr0_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2A_SOF_INT0" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x60 20.--22. "eof_intr1_sel,Select the End of Frame Contx to be sent as RCSS_CSI2A_EOF_INT1" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x60 17.--19. "eof_intr0_sel,Select the End of Frame Contx to be sent as RCSS_CSI2A_EOF_INT0" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x60 16. "sign_ext_en,Sign Extention Enable for CSI2 A" "0,1"
newline
bitfld.long 0x60 8. "mwait,Power Idle Protocol related Mwait Port" "0,1"
newline
bitfld.long 0x60 0.--4. "lane_enable,Lane enable for CSI2 A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "RCSS_CSI2B_CFG,"
bitfld.long 0x64 28.--30. "sof_intr1_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2B_SOF_INT1" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x64 24.--26. "sof_intr0_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2B_SOF_INT0" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x64 20.--22. "eof_intr1_sel,Select the End of Frame Contx to be sent as RCSS_CSI2B_EOF_INT1" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x64 17.--19. "eof_intr0_sel,Select the End of Frame Contx to be sent as RCSS_CSI2B_EOF_INT0" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x64 16. "sign_ext_en,Sign Extention Enable for CSI2 B" "0,1"
newline
bitfld.long 0x64 8. "mwait,Power Idle Protocol related Mwait Port" "0,1"
newline
bitfld.long 0x64 0.--4. "lane_enable,Lane enable for CSI2 B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x68 "RCSS_CSI2A_CTX0_LINE_PING_PONG,"
bitfld.long 0x68 16. "enable,Enable line based ping pong toggle for Context 0" "Diabled,Enabled"
newline
hexmask.long.word 0x68 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 0"
line.long 0x6C "RCSS_CSI2A_CTX1_LINE_PING_PONG,"
bitfld.long 0x6C 16. "enable,Enable line based ping pong toggle for Context 1" "Diabled,Enabled"
newline
hexmask.long.word 0x6C 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 1"
line.long 0x70 "RCSS_CSI2A_CTX2_LINE_PING_PONG,"
bitfld.long 0x70 16. "enable,Enable line based ping pong toggle for Context 2" "Diabled,Enabled"
newline
hexmask.long.word 0x70 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 2"
line.long 0x74 "RCSS_CSI2A_CTX3_LINE_PING_PONG,"
bitfld.long 0x74 16. "enable,Enable line based ping pong toggle for Context 3" "Diabled,Enabled"
newline
hexmask.long.word 0x74 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 3"
line.long 0x78 "RCSS_CSI2A_CTX4_LINE_PING_PONG,"
bitfld.long 0x78 16. "enable,Enable line based ping pong toggle for Context 4" "Diabled,Enabled"
newline
hexmask.long.word 0x78 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 4"
line.long 0x7C "RCSS_CSI2A_CTX5_LINE_PING_PONG,"
bitfld.long 0x7C 16. "enable,Enable line based ping pong toggle for Context 5" "Diabled,Enabled"
newline
hexmask.long.word 0x7C 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 5"
line.long 0x80 "RCSS_CSI2A_CTX6_LINE_PING_PONG,"
bitfld.long 0x80 16. "enable,Enable line based ping pong toggle for Context 6" "Diabled,Enabled"
newline
hexmask.long.word 0x80 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 6"
line.long 0x84 "RCSS_CSI2A_CTX7_LINE_PING_PONG,"
bitfld.long 0x84 16. "enable,Enable line based ping pong toggle for Context 7" "Diabled,Enabled"
newline
hexmask.long.word 0x84 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 7"
line.long 0x88 "RCSS_CSI2A_PARITY_CTRL,"
bitfld.long 0x88 16. "fifo_parity_en,Enable Parity for CSI2 FIFO Memory" "0,1"
newline
bitfld.long 0x88 0. "ctx_parity_en,Enable Parity for CSI2 CTX Memory" "0,1"
line.long 0x8C "RCSS_CSI2A_PARITY_STATUS,"
hexmask.long.byte 0x8C 16.--22. 1. "fifo_parity_addr,CSI2 FIFO Memory Error Address at which Parity Error occurred"
newline
bitfld.long 0x8C 0.--3. "ctx_parity_addr,CSI2 CTX Memory Error Address at which Parity Error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "RCSS_CSI2B_CTX0_LINE_PING_PONG,"
bitfld.long 0x90 16. "enable,Enable line based ping pong toggle for Context 0" "Diabled,Enabled"
newline
hexmask.long.word 0x90 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 0"
line.long 0x94 "RCSS_CSI2B_CTX1_LINE_PING_PONG,"
bitfld.long 0x94 16. "enable,Enable line based ping pong toggle for Context 1" "Diabled,Enabled"
newline
hexmask.long.word 0x94 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 1"
line.long 0x98 "RCSS_CSI2B_CTX2_LINE_PING_PONG,"
bitfld.long 0x98 16. "enable,Enable line based ping pong toggle for Context 2" "Diabled,Enabled"
newline
hexmask.long.word 0x98 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 2"
line.long 0x9C "RCSS_CSI2B_CTX3_LINE_PING_PONG,"
bitfld.long 0x9C 16. "enable,Enable line based ping pong toggle for Context 3" "Diabled,Enabled"
newline
hexmask.long.word 0x9C 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 3"
line.long 0xA0 "RCSS_CSI2B_CTX4_LINE_PING_PONG,"
bitfld.long 0xA0 16. "enable,Enable line based ping pong toggle for Context 4" "Diabled,Enabled"
newline
hexmask.long.word 0xA0 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 4"
line.long 0xA4 "RCSS_CSI2B_CTX5_LINE_PING_PONG,"
bitfld.long 0xA4 16. "enable,Enable line based ping pong toggle for Context 5" "Diabled,Enabled"
newline
hexmask.long.word 0xA4 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 5"
line.long 0xA8 "RCSS_CSI2B_CTX6_LINE_PING_PONG,"
bitfld.long 0xA8 16. "enable,Enable line based ping pong toggle for Context 6" "Diabled,Enabled"
newline
hexmask.long.word 0xA8 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 6"
line.long 0xAC "RCSS_CSI2B_CTX7_LINE_PING_PONG,"
bitfld.long 0xAC 16. "enable,Enable line based ping pong toggle for Context 7" "Diabled,Enabled"
newline
hexmask.long.word 0xAC 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 7"
line.long 0xB0 "RCSS_CSI2B_PARITY_CTRL,"
bitfld.long 0xB0 16. "fifo_parity_en,Enable Parity for CSI2 FIFO Memory" "0,1"
newline
bitfld.long 0xB0 0. "ctx_parity_en,Enable Parity for CSI2 CTX Memory" "0,1"
line.long 0xB4 "RCSS_CSI2B_PARITY_STATUS,"
hexmask.long.byte 0xB4 16.--22. 1. "fifo_parity_addr,CSI2 FIFO Memory Error Address at which Parity Error occurred"
newline
bitfld.long 0xB4 0.--3. "ctx_parity_addr,CSI2 CTX Memory Error Address at which Parity Error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "RCSS_CSI2A_LANE0_CFG,"
rbitfld.long 0xB8 19. "dy0_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xB8 18. "dy0_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xB8 17. "dy0_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xB8 16. "dy0_in,Pad DY Input" "0,1"
newline
bitfld.long 0xB8 15. "dy0_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xB8 14. "dy0_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xB8 13. "dx0_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xB8 12. "dx0_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xB8 11. "dx0_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xB8 10. "dx0_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xB8 9. "dx0_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xB8 8. "dx0_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xB8 7. "dx0_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xB8 6. "dx0_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xB8 5. "dx0_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xB8 4. "dx0_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xB8 3. "dx0_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xB8 2. "dx0_in,Pad DX Input" "0,1"
newline
bitfld.long 0xB8 1. "dx0_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xB8 0. "dx0_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xBC "RCSS_CSI2A_LANE1_CFG,"
rbitfld.long 0xBC 19. "dy1_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xBC 18. "dy1_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xBC 17. "dy1_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xBC 16. "dy1_in,Pad DY Input" "0,1"
newline
bitfld.long 0xBC 15. "dy1_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xBC 14. "dy1_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xBC 13. "dx1_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xBC 12. "dx1_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xBC 11. "dx1_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xBC 10. "dx1_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xBC 9. "dx1_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xBC 8. "dx1_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xBC 7. "dx1_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xBC 6. "dx1_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xBC 5. "dx1_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xBC 4. "dx1_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xBC 3. "dx1_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xBC 2. "dx1_in,Pad DX Input" "0,1"
newline
bitfld.long 0xBC 1. "dx1_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xBC 0. "dx1_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xC0 "RCSS_CSI2A_LANE2_CFG,"
rbitfld.long 0xC0 19. "dy2_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xC0 18. "dy2_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xC0 17. "dy2_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC0 16. "dy2_in,Pad DY Input" "0,1"
newline
bitfld.long 0xC0 15. "dy2_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xC0 14. "dy2_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xC0 9. "dx2_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xC0 8. "dx2_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xC0 7. "dx2_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xC0 6. "dx2_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xC0 5. "dx2_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xC0 4. "dx2_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xC0 3. "dx2_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC0 2. "dx2_in,Pad DX Input" "0,1"
newline
bitfld.long 0xC0 1. "dx2_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xC0 0. "dx2_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xC4 "RCSS_CSI2A_LANE3_CFG,"
rbitfld.long 0xC4 19. "dy3_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xC4 18. "dy3_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xC4 17. "dy3_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC4 16. "dy3_in,Pad DY Input" "0,1"
newline
bitfld.long 0xC4 15. "dy3_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xC4 14. "dy3_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xC4 13. "dx3_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xC4 12. "dx3_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xC4 11. "dx3_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xC4 10. "dx3_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xC4 9. "dx3_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xC4 8. "dx3_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xC4 7. "dx3_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xC4 6. "dx3_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xC4 5. "dx3_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xC4 4. "dx3_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xC4 3. "dx3_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC4 2. "dx3_in,Pad DX Input" "0,1"
newline
bitfld.long 0xC4 1. "dx3_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xC4 0. "dx3_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xC8 "RCSS_CSI2A_LANE4_CFG,"
rbitfld.long 0xC8 19. "dy4_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xC8 18. "dy4_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xC8 17. "dy4_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC8 16. "dy4_in,Pad DY Input" "0,1"
newline
bitfld.long 0xC8 15. "dy4_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xC8 14. "dy4_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xC8 13. "dx4_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xC8 12. "dx4_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xC8 11. "dx4_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xC8 10. "dx4_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xC8 9. "dx4_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xC8 8. "dx4_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xC8 7. "dx4_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xC8 6. "dx4_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xC8 5. "dx4_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xC8 4. "dx4_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xC8 3. "dx4_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC8 2. "dx4_in,Pad DX Input" "0,1"
newline
bitfld.long 0xC8 1. "dx4_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xC8 0. "dx4_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xCC "RCSS_CSI2B_LANE0_CFG,"
rbitfld.long 0xCC 19. "dy0_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xCC 18. "dy0_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xCC 17. "dy0_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xCC 16. "dy0_in,Pad DY Input" "0,1"
newline
bitfld.long 0xCC 15. "dy0_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xCC 14. "dy0_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xCC 13. "dx0_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xCC 12. "dx0_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xCC 11. "dx0_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xCC 10. "dx0_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xCC 9. "dx0_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xCC 8. "dx0_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xCC 7. "dx0_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xCC 6. "dx0_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xCC 5. "dx0_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xCC 4. "dx0_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xCC 3. "dx0_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xCC 2. "dx0_in,Pad DX Input" "0,1"
newline
bitfld.long 0xCC 1. "dx0_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xCC 0. "dx0_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xD0 "RCSS_CSI2B_LANE1_CFG,"
rbitfld.long 0xD0 19. "dy1_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xD0 18. "dy1_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xD0 17. "dy1_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD0 16. "dy1_in,Pad DY Input" "0,1"
newline
bitfld.long 0xD0 15. "dy1_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xD0 14. "dy1_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xD0 13. "dx1_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xD0 12. "dx1_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xD0 11. "dx1_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xD0 10. "dx1_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xD0 9. "dx1_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xD0 8. "dx1_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xD0 7. "dx1_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xD0 6. "dx1_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xD0 5. "dx1_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xD0 4. "dx1_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xD0 3. "dx1_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD0 2. "dx1_in,Pad DX Input" "0,1"
newline
bitfld.long 0xD0 1. "dx1_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xD0 0. "dx1_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xD4 "RCSS_CSI2B_LANE2_CFG,"
rbitfld.long 0xD4 19. "dy2_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xD4 18. "dy2_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xD4 17. "dy2_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD4 16. "dy2_in,Pad DY Input" "0,1"
newline
bitfld.long 0xD4 15. "dy2_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xD4 14. "dy2_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xD4 9. "dx2_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xD4 8. "dx2_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xD4 7. "dx2_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xD4 6. "dx2_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xD4 5. "dx2_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xD4 4. "dx2_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xD4 3. "dx2_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD4 2. "dx2_in,Pad DX Input" "0,1"
newline
bitfld.long 0xD4 1. "dx2_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xD4 0. "dx2_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xD8 "RCSS_CSI2B_LANE3_CFG,"
rbitfld.long 0xD8 19. "dy3_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xD8 18. "dy3_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xD8 17. "dy3_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD8 16. "dy3_in,Pad DY Input" "0,1"
newline
bitfld.long 0xD8 15. "dy3_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xD8 14. "dy3_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xD8 13. "dx3_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xD8 12. "dx3_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xD8 11. "dx3_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xD8 10. "dx3_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xD8 9. "dx3_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xD8 8. "dx3_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xD8 7. "dx3_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xD8 6. "dx3_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xD8 5. "dx3_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xD8 4. "dx3_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xD8 3. "dx3_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD8 2. "dx3_in,Pad DX Input" "0,1"
newline
bitfld.long 0xD8 1. "dx3_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xD8 0. "dx3_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xDC "RCSS_CSI2B_LANE4_CFG,"
rbitfld.long 0xDC 19. "dy4_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xDC 18. "dy4_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xDC 17. "dy4_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xDC 16. "dy4_in,Pad DY Input" "0,1"
newline
bitfld.long 0xDC 15. "dy4_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xDC 14. "dy4_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xDC 13. "dx4_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xDC 12. "dx4_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xDC 11. "dx4_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xDC 10. "dx4_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xDC 9. "dx4_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xDC 8. "dx4_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xDC 7. "dx4_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xDC 6. "dx4_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xDC 5. "dx4_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xDC 4. "dx4_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xDC 3. "dx4_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xDC 2. "dx4_in,Pad DX Input" "0,1"
newline
bitfld.long 0xDC 1. "dx4_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xDC 0. "dx4_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xE0 "RCSS_CSI2A_FIFO_MEMINIT,"
bitfld.long 0xE0 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0xE4 "RCSS_CSI2A_FIFO_MEMINIT_DONE,"
bitfld.long 0xE4 0. "done,Status field" "0,1"
line.long 0xE8 "RCSS_CSI2A_FIFO_MEMINIT_STATUS,"
bitfld.long 0xE8 0. "status,Status field" "0,1"
line.long 0xEC "RCSS_CSI2A_CTX_MEMINIT,"
bitfld.long 0xEC 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0xF0 "RCSS_CSI2A_CTX_MEMINIT_DONE,"
bitfld.long 0xF0 0. "done,Status field" "0,1"
line.long 0xF4 "RCSS_CSI2A_CTX_MEMINIT_STATUS,"
bitfld.long 0xF4 0. "status,Status field" "0,1"
line.long 0xF8 "RCSS_CSI2B_FIFO_MEMINIT,"
bitfld.long 0xF8 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0xFC "RCSS_CSI2B_FIFO_MEMINIT_DONE,"
bitfld.long 0xFC 0. "done,Status field" "0,1"
line.long 0x100 "RCSS_CSI2B_FIFO_MEMINIT_STATUS,"
bitfld.long 0x100 0. "status,Status field" "0,1"
line.long 0x104 "RCSS_CSI2B_CTX_MEMINIT,"
bitfld.long 0x104 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x108 "RCSS_CSI2B_CTX_MEMINIT_DONE,"
bitfld.long 0x108 0. "done,Status field" "0,1"
line.long 0x10C "RCSS_CSI2B_CTX_MEMINIT_STATUS,"
bitfld.long 0x10C 0. "status,Status field" "0,1"
line.long 0x110 "RCSS_BUS_SAFETY_CTRL,"
bitfld.long 0x110 4.--6. "clk_disable,Option to clock gate the safety infrastructure is Safety is disabled" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x110 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x114 "RCSS_BUS_SAFETY_SEC_ERR_STAT0,"
bitfld.long 0x114 9. "RCSS_TPTC_A1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 8. "RCSS_TPTC_A0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 7. "RCSS_TPTC_A1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 6. "RCSS_TPTC_A0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 5. "RCSS_MCASPC,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 4. "RCSS_MCASPB,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 3. "RCSS_MCASPA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 2. "RCSS_PCR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 1. "RCSS_CSI2B_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 0. "RCSS_CSI2A_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x118 "RCSS_TPTCA0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x118 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x118 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x118 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x11C "RCSS_TPTCA0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x11C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x11C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x11C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x11C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x120 "RCSS_TPTCA0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x120 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x120 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x120 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x120 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x124 "RCSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x124 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x124 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x128 "RCSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x12C "RCSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x130 "RCSS_TPTCA1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x130 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x130 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x130 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x134 "RCSS_TPTCA1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x134 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x134 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x134 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x134 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x138 "RCSS_TPTCA1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x138 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x138 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x138 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x138 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x13C "RCSS_TPTCA1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x13C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x13C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x140 "RCSS_TPTCA1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x144 "RCSS_TPTCA1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x148 "RCSS_TPTCA0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x148 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x148 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x148 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14C "RCSS_TPTCA0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x14C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x150 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x150 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x150 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x150 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x150 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x154 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x154 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x154 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x158 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x15C "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x160 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x164 "RCSS_TPTCA1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x164 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x164 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x164 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x168 "RCSS_TPTCA1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x168 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x168 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x168 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x168 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x16C "RCSS_TPTCA1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x16C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x16C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x16C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x16C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x170 "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x170 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x170 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x174 "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x178 "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x17C "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x180 "RCSS_CSI2A_MDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x180 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x180 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x180 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x184 "RCSS_CSI2A_MDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x184 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x184 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x184 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x184 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x188 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x188 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x188 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x188 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x188 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x18C "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x18C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x190 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x194 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x198 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x19C "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1A0 "RCSS_CSI2B_MDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1A0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1A4 "RCSS_CSI2B_MDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x1A4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1A8 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1A8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1AC "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1AC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B0 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1B4 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1B8 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1BC "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1C0 "RCSS_PCR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1C0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "RCSS_PCR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1C4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1C8 "RCSS_PCR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1C8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1CC "RCSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1CC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1CC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1D0 "RCSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1D4 "RCSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1D8 "RCSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1DC "RCSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1E0 "RCSS_MCASPA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1E0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1E4 "RCSS_MCASPA_BUS_SAFETY_FI,"
hexmask.long.byte 0x1E4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1E8 "RCSS_MCASPA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1E8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1EC "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1EC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1F0 "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1F4 "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1F8 "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1FC "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x200 "RCSS_MCASPB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x200 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x200 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x200 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x204 "RCSS_MCASPB_BUS_SAFETY_FI,"
hexmask.long.byte 0x204 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x204 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x208 "RCSS_MCASPB_BUS_SAFETY_ERR,"
hexmask.long.byte 0x208 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x20C "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x20C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x210 "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x214 "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x218 "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x21C "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x220 "RCSS_MCASPC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x220 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x220 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x224 "RCSS_MCASPC_BUS_SAFETY_FI,"
hexmask.long.byte 0x224 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x224 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x228 "RCSS_MCASPC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x228 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x22C "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x22C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x22C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x230 "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x234 "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x238 "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x23C "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x240 "RCSS_SCIA_CTRL,"
bitfld.long 0x240 4. "DMA_RX_CLR,RCSS_SCIA RX DMA Clear" "0,1"
newline
bitfld.long 0x240 0. "DMA_TX_CLR,RCSS_SCIA TX DMA Clear" "0,1"
line.long 0x244 "RCSS_GIO_CFG,"
line.long 0x248 "RCSS_TPTC_BOUNDARY_CFG,"
bitfld.long 0x248 8.--13. "tptc_a1_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x248 0.--5. "tptc_a0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24C "RCSS_TPTC_XID_REORDER_CFG,"
bitfld.long 0x24C 8. "tptc_a1_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
newline
bitfld.long 0x24C 0. "tptc_a0_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
line.long 0x250 "DBG_ACK_CPU_CTRL,"
bitfld.long 0x250 0. "sel,Select the Processor Suspend that is used to Suspend the DSS Peripehrals" "DSP,MSS CR5"
line.long 0x254 "DBG_ACK_CTL0,"
bitfld.long 0x254 8.--10. "RCSS_ECAP,Enable Suspend of the peripheral" "Peripheral not suspended,Peripehal Suspended,?..."
newline
bitfld.long 0x254 4.--6. "RCSS_I2CB,Enable Suspend of the peripheral" "Peripheral not suspended,Peripehal Suspended,?..."
newline
bitfld.long 0x254 0.--2. "RCSS_I2CA,Enable Suspend of the peripheral" "Peripheral not suspended,Peripehal Suspended,?..."
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
width 0x0B
tree.end
tree "RCSS_ECAP (RCSS ECAP Module Registers)"
base ad:0x5F79C00
group.long 0x00++0x17
line.long 0x00 "TSCTR,Time-Stamp Counter"
line.long 0x04 "CTRPHS,Counter Phase Offset Value Register"
line.long 0x08 "CAP1,Capture 1 Register"
line.long 0x0C "CAP2,Capture 2 Register"
line.long 0x10 "CAP3,Capture 3 Register"
line.long 0x14 "CAP4,Capture 4 Register"
group.long 0x24++0x0F
line.long 0x00 "ECCTL0,Capture Control Register 0"
hexmask.long 0x00 7.--31. 1. "NU_1,Reserved"
hexmask.long.byte 0x00 0.--6. 1. "INPUTSEL,Capture input source select bits[[br]]0000000 capture input is ECAPxINPUT[0] [[br]]0000001 capture input is ECAPxINPUT[1] [[br]]0000010 capture input is ECAPxINPUT[2][[br]]"
line.long 0x04 "ECCTL1_ECCTL2,Capture Control Register 1 & Capture Control Register 2"
rbitfld.long 0x04 30.--31. "MODCNTRSTS,This bit field reads current status on modulo counter[[br]]00b (R) = CAP1 register gets loaded on next capture event.[[br]]01b (R) = CAP2 register gets loaded on next capture event.[[br]]10b (R) = CAP3 register gets loaded on next capture.." "0,1,2,3"
bitfld.long 0x04 28.--29. "DMAEVTSEL,DMA event select[[br]]00b (R/W) = DMA interrupt source is CEVT1[[br]]01b (R/W) = DMA interrupt source is CEVT2[[br]]10b (R/W) = DMA interrupt source is CEVT3[[br]]11b (R/W) = DMA interrupt source is CEVT4" "0,1,2,3"
bitfld.long 0x04 27. "CTRFILTRESET,Reset Bit[[br]]0h (R) = No effect[[br]]1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags[[br]] [[br]]Note: This provides an ability start capture module from known state in case spurious inputs.." "0,1"
bitfld.long 0x04 26. "APWMPOL,APWM output polarity select" "0,1"
newline
bitfld.long 0x04 25. "CAP_APWM,CAP/APWM operating mode select 0 ECAP_MODULE ECAP module operates in capture mode" "0,1"
bitfld.long 0x04 24. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer" "0,1"
bitfld.long 0x04 22.--23. "SYNCO_SEL,Sync-Out Select 0x0 SWSYNC sync out signal is SWSYNC 0x1 ECAP_CTR_PRD_TO_SYNCOUT Select CTR = PRD event to be the sync-out signal 0x2 ECAP_DISABLE_SYNC_OUT Disable sync out signal 0x3 ECAP_DISABLE_SYNC_OUT Disable sync out signal" "0,1,2,3"
bitfld.long 0x04 21. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 ECAP_DISABLE_SYNC_IN Disable sync-in option 1 ECAP_ENABLE_COUNTER_REGISTER Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event" "0,1"
newline
bitfld.long 0x04 20. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 ECAP_TSCTR_STOPPED TSCTR stopped 1 ECAP_TSCTR_FREE_RUNNING TSCTR free-running" "0,1"
bitfld.long 0x04 19. "REARM,Re-Arming Control" "0,1"
bitfld.long 0x04 17.--18. "STOP_WRAP,Stop value for one-shot mode" "0,1,2,3"
bitfld.long 0x04 16. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 ECAP_OPP_CONT Operate in continuous mode 1 ECAP_OPP_ONE Operate in one-Shot mode" "0,1"
newline
bitfld.long 0x04 14.--15. "FREE_SOFT,Emulation Control" "ECAP_STOP_EMU TSCTR counter stops immediately on..,ECAP_RUNS_UNTIL TSCTR counter runs until = 0,ECAP_UNAF_EMU_SUS TSCTR counter is unaffected by..,ECAP_UNAF_EMU_SUS2 TSCTR counter is unaffected.."
bitfld.long 0x04 9.--13. "PRESCALE,Event Filter prescale select 0x00 ECAP_DIV1 Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 ECAP_DIV2 Divide by 2 0x02 ECAP_DIV4 Divide by 4 0x03 ECAP_DIV6 Divide by 6 0x04 ECAP_DIV8 Divide by 8 0x05 ECAP_DIV10 Divide by 10 0x1E.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event" "0,1"
bitfld.long 0x04 7. "CTRRST4,Counter Reset on Capture Event 4 0 ECAP_DO_NOT_RESET_EVENT4 Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 ECAP_RESET_EVENT4 Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode.." "0,1"
newline
bitfld.long 0x04 6. "CAP4POL,Capture Event 4 Polarity select 0 ECAP_CAP_EVENT4_RISE Capture Event 4 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT4_FALL Capture Event 4 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x04 5. "CTRRST3,Counter Reset on Capture Event 3 0 ECAP_DO_NOT_RESET_EVENT3 Do not reset counter on Capture Event 3 (absolute time stamp) 1 ECAP_RESET_EVENT3 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x04 4. "CAP3POL,Capture Event 3 Polarity select 0 ECAP_CAP_EVENT3_RISE Capture Event 3 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT3_FALL Capture Event 3 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x04 3. "CTRRST2,Counter Reset on Capture Event 2 0 ECAP_DO_NOT_RESET_EVENT2 Do not reset counter on Capture Event 2 (absolute time stamp) 1 ECAP_RESET_EVENT2 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1"
newline
bitfld.long 0x04 2. "CAP2POL,Capture Event 2 Polarity select 0 ECAP_CAP_EVENT2_RISE Capture Event 2 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT2_FALL Capture Event 2 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x04 1. "CTRRST1,Counter Reset on Capture Event 1 0 ECAP_DO_NOT_RESET_EVENT1 Do not reset counter on Capture Event 1 (absolute time stamp) 1 ECAP_RESET_EVENT1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x04 0. "CAP1POL,Capture Event 1 Polarity select 0 ECAP_CAP_EVENT1_RISE Capture Event 1 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT1_FALL Capture Event 1 triggered on a falling edge (FE)" "0,1"
line.long 0x08 "ECEINT_ECFLG,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt"
hexmask.long.byte 0x08 25.--31. 1. "NU_4,Reserved"
rbitfld.long 0x08 24. "HRERROR_FLG,High resolution error status flag Read 0 ECAP_INDICATE_NO_EVENT Indicates no event occurred Read 1 ECAP_INDICATE_HIGH_RESOLUTION_ERROR Indicates the High resolution Error occurred" "0,1"
rbitfld.long 0x08 23. "CTR_CMP_FLG,Compare Equal Compare Status Flag" "0,1"
rbitfld.long 0x08 22. "CTR_PRD_FLG,Counter Equal Period Status Flag" "0,1"
newline
rbitfld.long 0x08 21. "CTROVF_FLG,Counter Overflow Status Flag" "0,1"
rbitfld.long 0x08 20. "CEVT4_FLG,Capture Event 4 Status Flag This flag is only active in CAP mode" "0,1"
rbitfld.long 0x08 19. "CEVT3_FLG,Capture Event 3 Status Flag" "0,1"
rbitfld.long 0x08 18. "CEVT2_FLG,Capture Event 2 Status Flag" "0,1"
newline
rbitfld.long 0x08 17. "CEVT1_FLG,Capture Event 1 Status Flag" "0,1"
rbitfld.long 0x08 16. "INT_FLG,Global Interrupt Status Flag Read 0 ECAP_INDICATE_NO_EVENT Indicates no event occurred Read 1 ECAP_INDICATE_INTERRUPT Indicates that an interrupt was generated" "0,1"
hexmask.long.byte 0x08 9.--15. 1. "NU_3,Reserved"
bitfld.long 0x08 8. "HRERROR,High resolution error interrupt enable 0 ECAP_DISAB_HRERROR_INTERRUPT Disable High Resolution Error as an Interrupt source 1 ECAP_ENAB_HRERROR_INTERRUPT Enable High Resolution Error as an Interrupt source" "0,1"
newline
bitfld.long 0x08 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 ECAP_DISAB_CE_INTERRUPT Disable Compare Equal as an Interrupt source 1 ECAP_ENAB_CE_INTERRUPT Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x08 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 ECAP_DISAB_PE_INTERRUPT Disable Period Equal as an Interrupt source 1 ECAP_ENAB_PE_INTERRUPT Enable Period Equal as an Interrupt source" "0,1"
bitfld.long 0x08 5. "CTROVF,Counter Overflow Interrupt Enable 0 ECAP_DISAB_CO_INTERRUPT Disabled counter Overflow as an Interrupt source 1 ECAP_ENAB_CO_INTERRUPT Enable counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x08 4. "CEVT4,Capture Event 4 Interrupt Enable 0 ECAP_DISAB_CAP4_INTERRUPT Disable Capture Event 4 as an Interrupt source 1 ECAP_ENAB_CAP4_INTERRUPT Capture Event 4 Interrupt Enable" "0,1"
newline
bitfld.long 0x08 3. "CEVT3,Capture Event 3 Interrupt Enable 0 ECAP_DISAB_CAP3_INTERRUPT Disable Capture Event 3 as an Interrupt source 1 ECAP_ENAB_CAP3_INTERRUPT Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x08 2. "CEVT2,Capture Event 2 Interrupt Enable 0 ECAP_DISAB_CAP2_INTERRUPT Disable Capture Event 2 as an Interrupt source 1 ECAP_ENAB_CAP2_INTERRUPT Enable Capture Event 2 as an Interrupt source" "0,1"
bitfld.long 0x08 1. "CEVT1,Capture Event 1 Interrupt Enable 0 ECAP_DISAB_CAP1_INTERRUPT Disable Capture Event 1 as an Interrupt source 1 ECAP_ENAB_CAP1_INTERRUPT Enable Capture Event 1 as an Interrupt source" "0,1"
rbitfld.long 0x08 0. "NU_2,Reserved" "0,1"
line.long 0x0C "ECCLR_ECFRC,Capture Interrupt Clear Register & Capture Interrupt Force Register"
hexmask.long.byte 0x0C 25.--31. 1. "NU_6,Reserved"
bitfld.long 0x0C 24. "HRERROR_FRC,High resolution error Force interrupt 0 ECAP_NO_EFFECT_0 No effect" "0,1"
bitfld.long 0x0C 23. "CTR_CMP_FRC,Force Counter Equal Compare Interrupt" "0,1"
bitfld.long 0x0C 22. "CTR_PRD_FRC,Force Counter Equal Period Interrupt" "0,1"
newline
bitfld.long 0x0C 21. "CTROVF_FRC,Force Counter Overflow 0 ECAP_NO_EFFECT_0 No effect" "0,1"
bitfld.long 0x0C 20. "CEVT4_FRC,Force Capture Event 4" "0,1"
bitfld.long 0x0C 19. "CEVT3_FRC,Force Capture Event 3" "0,1"
bitfld.long 0x0C 18. "CEVT2_FRC,Force Capture Event 2" "0,1"
newline
bitfld.long 0x0C 17. "CEVT1_FRC,Force Capture Event 1" "0,1"
hexmask.long.byte 0x0C 9.--16. 1. "NU_5,Reserved"
bitfld.long 0x0C 8. "HRERROR,High resolution error status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 7. "CTR_CMP,Counter Equal Compare Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
newline
bitfld.long 0x0C 6. "CTR_PRD,Counter Equal Period Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 5. "CTROVF,Counter Overflow Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 4. "CEVT4,Capture Event 4 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 3. "CEVT3,Capture Event 3 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
newline
bitfld.long 0x0C 2. "CEVT2,Capture Event 2 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 1. "CEVT1,Capture Event 1 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 0. "INT,ECAP Global Interrupt Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
group.long 0x3C++0x03
line.long 0x00 "ECAPSYNCINSEL,SYNC source select register"
hexmask.long 0x00 5.--31. 1. "NU_7,Reserved"
bitfld.long 0x00 0.--4. "SEL,These bits determines the source of SYNCIN signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "RCSS_GIO (RCSS GIO Module Registers)"
base ad:0x5F7B400
group.long 0x00++0x03
line.long 0x00 "GIOGCR,GIO reset"
hexmask.long 0x00 1.--31. 1. "NU0,Reserved"
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "GIOPWDN,GIO power down mode register"
bitfld.long 0x00 0. "GIOPWDN,Writing to the GIOPWDN bit is only allowed in privilege mode" "Normal operation; clocks enabled to GIO..,Power-down mode"
group.long 0x08++0x14B
line.long 0x00 "GIOINTDET,Interrupt detection select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x00 24.--31. 1. "GIOINTDET_3,Interrupt detection select for pins GIOD[7:0]"
hexmask.long.byte 0x00 16.--23. 1. "GIOINTDET_2,Interrupt detection select for pins GIOC[7:0]"
hexmask.long.byte 0x00 8.--15. 1. "GIOINTDET_1,Interrupt detection select for pins GIOB[7:0]"
hexmask.long.byte 0x00 0.--7. 1. "GIOINTDET_0,Interrupt detection select for pins GIOA[7:0]"
line.long 0x04 "GIOPOL,Interrupt polarity select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x04 24.--31. 1. "GIOPOL_3,Interrupt polarity select for pins GIOD[7:0]"
hexmask.long.byte 0x04 16.--23. 1. "GIOPOL_2,Interrupt polarity select for pins GIOC[7:0]"
hexmask.long.byte 0x04 8.--15. 1. "GIOPOL_1,Interrupt polarity select for pins GIOB[7:0]"
hexmask.long.byte 0x04 0.--7. 1. "GIOPOL_0,Interrupt polarity select for pins GIOA[7:0]"
line.long 0x08 "GIOENASET,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x08 24.--31. 1. "GIOENASET_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x08 16.--23. 1. "GIOENASET_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x08 8.--15. 1. "GIOENASET_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x08 0.--7. 1. "GIOENASET_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x0C "GIOENACLR,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x0C 24.--31. 1. "GIOENACLR_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x0C 16.--23. 1. "GIOENACLR_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x0C 8.--15. 1. "GIOENACLR_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x0C 0.--7. 1. "GIOENACLR_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x10 "GIOLVLSET,GIO high priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x10 24.--31. 1. "GIOLVLSET_3,GIO high priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x10 16.--23. 1. "GIOLVLSET_2,GIO high priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x10 8.--15. 1. "GIOLVLSET_1,GIO high priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x10 0.--7. 1. "GIOLVLSET_0,GIO high priority interrupt for pins GIOA[7:0]"
line.long 0x14 "GIOLVLCLR,GIO low priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x14 24.--31. 1. "GIOLVLCLR_3,GIO low priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x14 16.--23. 1. "GIOLVLCLR_2,GIO low priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x14 8.--15. 1. "GIOLVLCLR_1,GIO low priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x14 0.--7. 1. "GIOLVLCLR_0,GIO low priority interrupt for pins GIOA[7:0]"
line.long 0x18 "GIOFLG,GIO flag for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x18 24.--31. 1. "GIOFLG_3,GIO flag for pins GIOD[7:0]"
hexmask.long.byte 0x18 16.--23. 1. "GIOFLG_2,GIO flag for pins GIOC[7:0]"
hexmask.long.byte 0x18 8.--15. 1. "GIOFLG_1,GIO flag for pins GIOB[7:0]"
hexmask.long.byte 0x18 0.--7. 1. "GIOFLG_0,GIO flag for pins GIOA[7:0]"
line.long 0x1C "GIOOFFA,Index bits for currently pending high-priority interrupt Register A"
hexmask.long 0x1C 6.--31. 1. "NU1,Reserved"
bitfld.long 0x1C 0.--5. "GIOOFFA,Index bits for currently pending high-priority interrupt Register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "GIOOFFB,Index bits for currently pending high-priority interrupt Register B"
hexmask.long 0x20 6.--31. 1. "NU2,Reserved"
bitfld.long 0x20 0.--5. "GIOOFFB,Index bits for currently pending high-priority interrupt Register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "GIOEMUA,GIO emulation register A"
hexmask.long 0x24 6.--31. 1. "NU3,Reserved"
bitfld.long 0x24 0.--5. "GIOEMUA,GIO emulation register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "GIOEMUB,GIO emulation register B"
hexmask.long 0x28 6.--31. 1. "NU4,Reserved"
bitfld.long 0x28 0.--5. "GIOEMUB,GIO emulation register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "GIODIRA,GIO data direction of pins in Port A"
hexmask.long.tbyte 0x2C 8.--31. 1. "NU5,Reserved"
hexmask.long.byte 0x2C 0.--7. 1. "GIODIRA,GIO data direction of pins in Port A"
line.long 0x30 "GIODINA,GIO data input for pins in port A"
hexmask.long.tbyte 0x30 8.--31. 1. "NU11,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "GIODINA,GIO data input for pins in port A"
line.long 0x34 "GIODOUTA,GIO data output for pins in port A"
hexmask.long.tbyte 0x34 8.--31. 1. "NU17,Reserved"
hexmask.long.byte 0x34 0.--7. 1. "GIODOUTA,GIO data output for pins in port A"
line.long 0x38 "GIOSETA,GIO data set for port A"
hexmask.long.tbyte 0x38 8.--31. 1. "NU23,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "GIODSETA,GIO data set for port A"
line.long 0x3C "GIOCLRA,GIO data clear for port A"
hexmask.long.tbyte 0x3C 8.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x3C 0.--7. 1. "GIODCLRA,GIO data clear for port A"
line.long 0x40 "GIOPDRA,GIO open drain for port A"
hexmask.long.tbyte 0x40 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x40 0.--7. 1. "GIOPDRA,GIO open drain for port A"
line.long 0x44 "GIOPULDISA,GIO pul disable for port A"
hexmask.long.tbyte 0x44 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x44 0.--7. 1. "GIOPULDISA,GIO pull disable for port A"
line.long 0x48 "GIOPSLA,GIO pul select for port A"
hexmask.long.tbyte 0x48 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x48 0.--7. 1. "GIOPSLA,GIO pull select for port A"
line.long 0x4C "GIODIRB,GIO data direction of pins in Port B"
hexmask.long.tbyte 0x4C 8.--31. 1. "NU6,Reserved"
hexmask.long.byte 0x4C 0.--7. 1. "GIODIRB,GIO data direction of pins in Port B"
line.long 0x50 "GIODINB,GIO data input for pins in port B"
hexmask.long.tbyte 0x50 8.--31. 1. "NU12,Reserved"
hexmask.long.byte 0x50 0.--7. 1. "GIODINB,GIO data input for pins in port B"
line.long 0x54 "GIODOUTB,GIO data output for pins in port B"
hexmask.long.tbyte 0x54 8.--31. 1. "NU18,Reserved"
hexmask.long.byte 0x54 0.--7. 1. "GIODOUTB,GIO data output for pins in port B"
line.long 0x58 "GIOSETB,GIO data set for port B"
hexmask.long.tbyte 0x58 8.--31. 1. "NU24,Reserved"
hexmask.long.byte 0x58 0.--7. 1. "GIODSETB,GIO data set for port B"
line.long 0x5C "GIOCLRB,GIO data clear for port B"
hexmask.long.tbyte 0x5C 8.--31. 1. "NU30,Reserved"
hexmask.long.byte 0x5C 0.--7. 1. "GIODCLRB,GIO data clear for port B"
line.long 0x60 "GIOPDRB,GIO open drain for port B"
hexmask.long.tbyte 0x60 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x60 0.--7. 1. "GIOPDRB,GIO open drain for port B"
line.long 0x64 "GIOPULDISB,GIO pul disable for port B"
hexmask.long.tbyte 0x64 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x64 0.--7. 1. "GIOPULDISB,GIO pull disable for port B"
line.long 0x68 "GIOPSLB,GIO pul select for port B"
hexmask.long.tbyte 0x68 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x68 0.--7. 1. "GIOPSLB,GIO pull select for port B"
line.long 0x6C "GIODIRC,GIO data direction of pins in Port C"
hexmask.long.tbyte 0x6C 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x6C 0.--7. 1. "GIODIRC,GIO data direction of pins in Port C"
line.long 0x70 "GIODINC,GIO data input for pins in port C"
hexmask.long.tbyte 0x70 8.--31. 1. "NU13,Reserved"
hexmask.long.byte 0x70 0.--7. 1. "GIODINC,GIO data input for pins in port C"
line.long 0x74 "GIODOUTC,GIO data output for pins in port C"
hexmask.long.tbyte 0x74 8.--31. 1. "NU19,Reserved"
hexmask.long.byte 0x74 0.--7. 1. "GIODOUTC,GIO data output for pins in port C"
line.long 0x78 "GIOSETC,GIO data set for port C"
hexmask.long.tbyte 0x78 8.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x78 0.--7. 1. "GIODSETC,GIO data set for port C"
line.long 0x7C "GIOCLRC,GIO data clear for port C"
hexmask.long.tbyte 0x7C 8.--31. 1. "NU31,Reserved"
hexmask.long.byte 0x7C 0.--7. 1. "GIODCLRC,GIO data clear for port C"
line.long 0x80 "GIOPDRC,GIO open drain for port C"
hexmask.long.tbyte 0x80 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x80 0.--7. 1. "GIOPDRC,GIO open drain for port C"
line.long 0x84 "GIOPULDISC,GIO pul disable for port C"
hexmask.long.tbyte 0x84 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x84 0.--7. 1. "GIOPULDISC,GIO pull disable for port C"
line.long 0x88 "GIOPSLC,GIO pul select for port C"
hexmask.long.tbyte 0x88 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x88 0.--7. 1. "GIOPSLC,GIO pull select for port C"
line.long 0x8C "GIODIRD,GIO data direction of pins in Port D"
hexmask.long.tbyte 0x8C 8.--31. 1. "NU8,Reserved"
hexmask.long.byte 0x8C 0.--7. 1. "GIODIRD,GIO data direction of pins in Port D"
line.long 0x90 "GIODIND,GIO data input for pins in port D"
hexmask.long.tbyte 0x90 8.--31. 1. "NU14,Reserved"
hexmask.long.byte 0x90 0.--7. 1. "GIODIND,GIO data input for pins in port D"
line.long 0x94 "GIODOUTD,GIO data output for pins in port D"
hexmask.long.tbyte 0x94 8.--31. 1. "NU20,Reserved"
hexmask.long.byte 0x94 0.--7. 1. "GIODOUTD,GIO data output for pins in port D"
line.long 0x98 "GIOSETD,GIO data set for port D"
hexmask.long.tbyte 0x98 8.--31. 1. "NU26,Reserved"
hexmask.long.byte 0x98 0.--7. 1. "GIODSETD,GIO data set for port D"
line.long 0x9C "GIOCLRD,GIO data clear for port D"
hexmask.long.tbyte 0x9C 8.--31. 1. "NU32,Reserved"
hexmask.long.byte 0x9C 0.--7. 1. "GIODCLRD,GIO data clear for port D"
line.long 0xA0 "GIOPDRD,GIO open drain for port D"
hexmask.long.tbyte 0xA0 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA0 0.--7. 1. "GIOPDRD,GIO open drain for port D"
line.long 0xA4 "GIOPULDISD,GIO pul disable for port D"
hexmask.long.tbyte 0xA4 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA4 0.--7. 1. "GIOPULDISD,GIO pull disable for port D"
line.long 0xA8 "GIOPSLD,GIO pul select for port D"
hexmask.long.tbyte 0xA8 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA8 0.--7. 1. "GIOPSLD,GIO pull select for port D"
line.long 0xAC "GIODIRE,GIO data direction of pins in Port E"
hexmask.long.tbyte 0xAC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xAC 0.--7. 1. "GIODIRE,GIO data direction of pins in Port E"
line.long 0xB0 "GIODINE,GIO data input for pins in port E"
hexmask.long.tbyte 0xB0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xB0 0.--7. 1. "GIODINE,GIO data input for pins in port E"
line.long 0xB4 "GIODOUTE,GIO data output for pins in port E"
hexmask.long.tbyte 0xB4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xB4 0.--7. 1. "GIODOUTE,GIO data output for pins in port E"
line.long 0xB8 "GIOSETE,GIO data set for port E"
hexmask.long.tbyte 0xB8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xB8 0.--7. 1. "GIODSETE,GIO data set for port E"
line.long 0xBC "GIOCLRE,GIO data clear for port E"
hexmask.long.tbyte 0xBC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xBC 0.--7. 1. "GIODCLRE,GIO data clear for port E"
line.long 0xC0 "GIOPDRE,GIO open drain for port E"
hexmask.long.tbyte 0xC0 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC0 0.--7. 1. "GIOPDRE,GIO open drain for port E"
line.long 0xC4 "GIOPULDISE,GIO pul disable for port E"
hexmask.long.tbyte 0xC4 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC4 0.--7. 1. "GIOPULDISE,GIO pull disable for port E"
line.long 0xC8 "GIOPSLE,GIO pul select for port E"
hexmask.long.tbyte 0xC8 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC8 0.--7. 1. "GIOPSLE,GIO pull select for port E"
line.long 0xCC "GIODIRF,GIO data direction of pins in Port F"
hexmask.long.tbyte 0xCC 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0xCC 0.--7. 1. "GIODIRF,GIO data direction of pins in Port F"
line.long 0xD0 "GIODINF,GIO data input for pins in Port F"
hexmask.long.tbyte 0xD0 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0xD0 0.--7. 1. "GIODINF,GIO data input for pins in port F"
line.long 0xD4 "GIODOUTF,GIO data output for pins in Port F"
hexmask.long.tbyte 0xD4 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0xD4 0.--7. 1. "GIODOUTF,GIO data output for pins in port F"
line.long 0xD8 "GIOSETF,GIO data set for Port F"
hexmask.long.tbyte 0xD8 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0xD8 0.--7. 1. "GIODSETF,GIO data set for port F"
line.long 0xDC "GIOCLRF,GIO data clear for Port F"
hexmask.long.tbyte 0xDC 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0xDC 0.--7. 1. "GIODCLRF,GIO data clear for port F"
line.long 0xE0 "GIOPDRF,GIO open drain for Port F"
hexmask.long.tbyte 0xE0 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE0 0.--7. 1. "GIOPDRF,GIO open drain for port F"
line.long 0xE4 "GIOPULDISF,GIO pul disable for port F"
hexmask.long.tbyte 0xE4 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE4 0.--7. 1. "GIOPULDISF,GIO pull disable for port F"
line.long 0xE8 "GIOPSLF,GIO pul select for port F"
hexmask.long.tbyte 0xE8 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE8 0.--7. 1. "GIOPSLF,GIO pull select for port F"
line.long 0xEC "GIODIRG,GIO data direction of pins in Port G"
hexmask.long.tbyte 0xEC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xEC 0.--7. 1. "GIODIRG,GIO data direction of pins in Port G"
line.long 0xF0 "GIODING,GIO data input for pins in port G"
hexmask.long.tbyte 0xF0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xF0 0.--7. 1. "GIODING,GIO data input for pins in port G"
line.long 0xF4 "GIODOUTG,GIO data output for pins in port G"
hexmask.long.tbyte 0xF4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xF4 0.--7. 1. "GIODOUTG,GIO data output for pins in port G"
line.long 0xF8 "GIOSETG,GIO data set for port G"
hexmask.long.tbyte 0xF8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xF8 0.--7. 1. "GIODSETG,GIO data set for port G"
line.long 0xFC "GIOCLRG,GIO data clear for port G"
hexmask.long.tbyte 0xFC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xFC 0.--7. 1. "GIODCLRG,GIO data clear for port G"
line.long 0x100 "GIOPDRG,GIO open drain for port G"
hexmask.long.tbyte 0x100 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x100 0.--7. 1. "GIOPDRG,GIO open drain for port G"
line.long 0x104 "GIOPULDISG,GIO pul disable for port G"
hexmask.long.tbyte 0x104 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x104 0.--7. 1. "GIOPULDISG,GIO pull disable for port G"
line.long 0x108 "GIOPSLG,GIO pul select for port G"
hexmask.long.tbyte 0x108 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x108 0.--7. 1. "GIOPSLG,GIO pull select for port G"
line.long 0x10C "GIODIRH,GIO data direction of pins in Port H"
hexmask.long.tbyte 0x10C 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0x10C 0.--7. 1. "GIODIRH,GIO data direction of pins in Port H"
line.long 0x110 "GIODINH,GIO data input for pins in Port H"
hexmask.long.tbyte 0x110 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x110 0.--7. 1. "GIODINH,GIO data input for pins in port H"
line.long 0x114 "GIODOUTH,GIO data output for pins in Port H"
hexmask.long.tbyte 0x114 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0x114 0.--7. 1. "GIODOUTH,GIO data output for pins in port H"
line.long 0x118 "GIOSETH,GIO data set for Port H"
hexmask.long.tbyte 0x118 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0x118 0.--7. 1. "GIODSETH,GIO data set for port H"
line.long 0x11C "GIOCLRH,GIO data clear for Port H"
hexmask.long.tbyte 0x11C 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0x11C 0.--7. 1. "GIODCLRH,GIO data clear for port H"
line.long 0x120 "GIOPDRH,GIO open drain for Port H"
hexmask.long.tbyte 0x120 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x120 0.--7. 1. "GIOPDRH,GIO open drain for port H"
line.long 0x124 "GIOPULDISH,GIO pul disable for port H"
hexmask.long.tbyte 0x124 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x124 0.--7. 1. "GIOPULDISH,GIO pull disable for port H"
line.long 0x128 "GIOPSLH,GIO pul select for port H"
hexmask.long.tbyte 0x128 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x128 0.--7. 1. "GIOPSLH,GIO pull select for port H"
line.long 0x12C "GIOSRCA,GIO slew rate select for port A"
hexmask.long.tbyte 0x12C 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x12C 0.--7. 1. "GIOSRCA,GIO slew rate control for port A"
line.long 0x130 "GIOSRCB,GIO slew rate select for port B"
hexmask.long.tbyte 0x130 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x130 0.--7. 1. "GIOSRCB,GIO slew rate control for port B"
line.long 0x134 "GIOSRCC,GIO slew rate select for port C"
hexmask.long.tbyte 0x134 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x134 0.--7. 1. "GIOSRCC,GIO slew rate control for port C"
line.long 0x138 "GIOSRCD,GIO slew rate select for port D"
hexmask.long.tbyte 0x138 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x138 0.--7. 1. "GIOSRCD,GIO slew rate control for port D"
line.long 0x13C "GIOSRCE,GIO slew rate select for port E"
hexmask.long.tbyte 0x13C 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x13C 0.--7. 1. "GIOSRCE,GIO slew rate control for port E"
line.long 0x140 "GIOSRCF,GIO slew rate select for port F"
hexmask.long.tbyte 0x140 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x140 0.--7. 1. "GIOSRCF,GIO slew rate control for port F"
line.long 0x144 "GIOSRCG,GIO slew rate select for port G"
hexmask.long.tbyte 0x144 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x144 0.--7. 1. "GIOSRCG,GIO slew rate control for port G"
line.long 0x148 "GIOSRCH,GIO slew rate select for port H"
hexmask.long.tbyte 0x148 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x148 0.--7. 1. "GIOSRCH,GIO slew rate control for port H"
width 0x0B
tree.end
tree "RCSS_I2CA (RCSS I2CA Module Registers)"
base ad:0x5F7EC00
group.long 0x00++0x3F
line.long 0x00 "ICOAR,I2C Own Address register"
hexmask.long.tbyte 0x00 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x00 0.--9. 1. "A9_A0,Own address"
line.long 0x04 "ICIMR,I2C Interrupt Mask/Status register"
hexmask.long 0x04 7.--31. 1. "NU,Reserved"
bitfld.long 0x04 6. "AAS,Address As Slave interrupt mask bit" "0,1"
newline
bitfld.long 0x04 5. "SCD,Stop Condition Detection mask bit" "0,1"
bitfld.long 0x04 4. "ICXRDY,Transmit Data Ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 3. "ICRRDY,Receive Data Ready interrupt mask bit" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 1. "NACK,No Acknowledgement interrupt mask bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration Lost interrupt mask bit" "0,1"
line.long 0x08 "ICSTR,I2C Interrupt Status register"
hexmask.long.tbyte 0x08 15.--31. 1. "NU2,Reserved"
bitfld.long 0x08 14. "SDIR,Slave Direction" "0,1"
newline
bitfld.long 0x08 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'" "0,1"
bitfld.long 0x08 12. "BB,Bus Busy" "0,1"
newline
bitfld.long 0x08 11. "RSFULL,Receive shift full" "0,1"
bitfld.long 0x08 10. "XSMT,Transmit shift empty not" "0,1"
newline
bitfld.long 0x08 9. "AAS,Address As Slave" "0,1"
bitfld.long 0x08 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call)" "0,1"
newline
bitfld.long 0x08 6.--7. "NU1,Reserved" "0,1,2,3"
bitfld.long 0x08 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition" "0,1"
newline
bitfld.long 0x08 4. "ICXRDY,Transmit Data Ready interrupt flag bit" "0,1"
bitfld.long 0x08 3. "ICRRDY,Receive Data Ready interrupt flag bit" "0,1"
newline
bitfld.long 0x08 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
bitfld.long 0x08 1. "NACK,No-Acknowledgement interrupt flag bit" "0,1"
newline
bitfld.long 0x08 0. "AL,Arbitration-Lost interrupt flag bit" "0,1"
line.long 0x0C "ICCLKL,I2C Clock Divider Low register"
hexmask.long.word 0x0C 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "ICCL15_ICCL0,Low time I2C SCL Clock Division Factor"
line.long 0x10 "ICCLKH,I2C Clock Divider High register"
hexmask.long.word 0x10 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I2C SCL Clock Division Factor"
line.long 0x14 "ICCNT,I2C Data Count register"
hexmask.long.word 0x14 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count"
line.long 0x18 "ICDRR,I2C Data Receive register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data"
line.long 0x1C "ICSAR,I2C Slave Address register"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address"
line.long 0x20 "ICDXR,I2C Data Transmit register"
hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data"
line.long 0x24 "ICMDR,I2C Mode register"
hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved"
bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode" "0,1"
newline
bitfld.long 0x24 14. "FREE,Free Running" "0,1"
bitfld.long 0x24 13. "STT,Start Condition (Master only mode)" "0,1"
newline
bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509)" "0,1"
bitfld.long 0x24 11. "STP,Stop Condition (Master mode only)" "0,1"
newline
bitfld.long 0x24 10. "MST,Master" "0,1"
bitfld.long 0x24 9. "TRX,Transmitter" "0,1"
newline
bitfld.long 0x24 8. "XA,Expanded Address" "0,1"
bitfld.long 0x24 7. "RM,Repeat Mode" "0,1"
newline
bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only)" "0,1"
bitfld.long 0x24 5. "IRS,I2C Reset Not" "0,1"
newline
bitfld.long 0x24 4. "STB,Start Byte (Master only mode)" "0,1"
bitfld.long 0x24 3. "FDF,Free Data Format" "0,1"
newline
bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted" "0,1,2,3,4,5,6,7"
line.long 0x28 "ICIVR,I2C Interrupt Vector register"
hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved"
bitfld.long 0x28 8.--11. "TESTMD,Reserved for internal testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 3.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--2. "INTCODE,Interrupt code" "0,1,2,3,4,5,6,7"
line.long 0x2C "ICEMDR,I2C Extended Mode register"
hexmask.long 0x2C 2.--31. 1. "NU,Reserved"
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave" "0,1"
newline
bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode" "0,1"
line.long 0x30 "ICPSC,I2C Prescaler register"
hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module"
line.long 0x34 "ICPID1,I2C Peripheral ID register 1"
hexmask.long.word 0x34 16.--31. 1. "NU,Reserved"
hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral"
newline
hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C"
line.long 0x38 "ICPID2,I2C Peripheral ID register 2"
hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral"
line.long 0x3C "ICDMAC,I2C DMA Control Register"
hexmask.long 0x3C 2.--31. 1. "NU,Reserved"
bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable" "0,1"
newline
bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable" "0,1"
group.long 0x48++0x1B
line.long 0x00 "ICPFUNC,I2C Pin Function register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved"
bitfld.long 0x00 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins" "Pins function as SCL and SDA,Pins functions as GPIO"
line.long 0x04 "ICPDIR,I2C Pin Direction register"
hexmask.long 0x04 2.--31. 1. "NU,Reserved"
bitfld.long 0x04 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO" "SDA pin functions as input,SDA pin functions as output"
newline
bitfld.long 0x04 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO" "SCL pin functions as input,SCL pin functions as output"
line.long 0x08 "ICPDIN,I2C Pin Data In register"
hexmask.long 0x08 2.--31. 1. "NU,Reserved"
bitfld.long 0x08 1. "PDIN1,Indicates the logic level present on the SDA pin" "Logic low present at SDA pin regardless of PFUNC..,Logic high present at SDA pin regardless of.."
newline
bitfld.long 0x08 0. "PDIN0,Indicates the logic level present on the SCL pin" "Logic low present at SCL pin regardless of PFUNC..,Logic high present at SCL pin regardless of.."
line.long 0x0C "ICPDOUT,I2C Pin Data Out register"
hexmask.long 0x0C 2.--31. 1. "NU,Reserved"
bitfld.long 0x0C 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output" "SDA pin driven low,SDA pin driven high"
newline
bitfld.long 0x0C 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output" "SCL pin driven low,SCL pin driven high"
line.long 0x10 "ICPDSET,I2C Pin Data Set register"
hexmask.long 0x10 2.--31. 1. "NU,Reserved"
bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin" "no effect,PDOUT[1] bit is set to.."
newline
bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin" "no effect,PDOUT[0] bit is set to.."
line.long 0x14 "ICPDCLR,I2C Pin Data Clear register"
hexmask.long 0x14 2.--31. 1. "NU,Reserved"
bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin" "no effect,PDOUT[1] bit is cleared.."
newline
bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin" "no effect,PDOUT[0] bit is cleared.."
line.long 0x18 "ICPDRV,I2C Pin Driver Mode Register"
hexmask.long 0x18 2.--31. 1. "NU,Reserved"
bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin" "I2C mode,GPIO mode"
newline
bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin" "I2C mode,GPIO mode"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "I2C_RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "RCSS_I2CB (RCSS I2CB Module Registers)"
base ad:0x5F7F000
group.long 0x00++0x3F
line.long 0x00 "ICOAR,I2C Own Address register"
hexmask.long.tbyte 0x00 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x00 0.--9. 1. "A9_A0,Own address"
line.long 0x04 "ICIMR,I2C Interrupt Mask/Status register"
hexmask.long 0x04 7.--31. 1. "NU,Reserved"
bitfld.long 0x04 6. "AAS,Address As Slave interrupt mask bit" "0,1"
newline
bitfld.long 0x04 5. "SCD,Stop Condition Detection mask bit" "0,1"
bitfld.long 0x04 4. "ICXRDY,Transmit Data Ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 3. "ICRRDY,Receive Data Ready interrupt mask bit" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 1. "NACK,No Acknowledgement interrupt mask bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration Lost interrupt mask bit" "0,1"
line.long 0x08 "ICSTR,I2C Interrupt Status register"
hexmask.long.tbyte 0x08 15.--31. 1. "NU2,Reserved"
bitfld.long 0x08 14. "SDIR,Slave Direction" "0,1"
newline
bitfld.long 0x08 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'" "0,1"
bitfld.long 0x08 12. "BB,Bus Busy" "0,1"
newline
bitfld.long 0x08 11. "RSFULL,Receive shift full" "0,1"
bitfld.long 0x08 10. "XSMT,Transmit shift empty not" "0,1"
newline
bitfld.long 0x08 9. "AAS,Address As Slave" "0,1"
bitfld.long 0x08 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call)" "0,1"
newline
bitfld.long 0x08 6.--7. "NU1,Reserved" "0,1,2,3"
bitfld.long 0x08 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition" "0,1"
newline
bitfld.long 0x08 4. "ICXRDY,Transmit Data Ready interrupt flag bit" "0,1"
bitfld.long 0x08 3. "ICRRDY,Receive Data Ready interrupt flag bit" "0,1"
newline
bitfld.long 0x08 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
bitfld.long 0x08 1. "NACK,No-Acknowledgement interrupt flag bit" "0,1"
newline
bitfld.long 0x08 0. "AL,Arbitration-Lost interrupt flag bit" "0,1"
line.long 0x0C "ICCLKL,I2C Clock Divider Low register"
hexmask.long.word 0x0C 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "ICCL15_ICCL0,Low time I2C SCL Clock Division Factor"
line.long 0x10 "ICCLKH,I2C Clock Divider High register"
hexmask.long.word 0x10 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I2C SCL Clock Division Factor"
line.long 0x14 "ICCNT,I2C Data Count register"
hexmask.long.word 0x14 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count"
line.long 0x18 "ICDRR,I2C Data Receive register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data"
line.long 0x1C "ICSAR,I2C Slave Address register"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address"
line.long 0x20 "ICDXR,I2C Data Transmit register"
hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data"
line.long 0x24 "ICMDR,I2C Mode register"
hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved"
bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode" "0,1"
newline
bitfld.long 0x24 14. "FREE,Free Running" "0,1"
bitfld.long 0x24 13. "STT,Start Condition (Master only mode)" "0,1"
newline
bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509)" "0,1"
bitfld.long 0x24 11. "STP,Stop Condition (Master mode only)" "0,1"
newline
bitfld.long 0x24 10. "MST,Master" "0,1"
bitfld.long 0x24 9. "TRX,Transmitter" "0,1"
newline
bitfld.long 0x24 8. "XA,Expanded Address" "0,1"
bitfld.long 0x24 7. "RM,Repeat Mode" "0,1"
newline
bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only)" "0,1"
bitfld.long 0x24 5. "IRS,I2C Reset Not" "0,1"
newline
bitfld.long 0x24 4. "STB,Start Byte (Master only mode)" "0,1"
bitfld.long 0x24 3. "FDF,Free Data Format" "0,1"
newline
bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted" "0,1,2,3,4,5,6,7"
line.long 0x28 "ICIVR,I2C Interrupt Vector register"
hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved"
bitfld.long 0x28 8.--11. "TESTMD,Reserved for internal testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 3.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--2. "INTCODE,Interrupt code" "0,1,2,3,4,5,6,7"
line.long 0x2C "ICEMDR,I2C Extended Mode register"
hexmask.long 0x2C 2.--31. 1. "NU,Reserved"
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave" "0,1"
newline
bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode" "0,1"
line.long 0x30 "ICPSC,I2C Prescaler register"
hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module"
line.long 0x34 "ICPID1,I2C Peripheral ID register 1"
hexmask.long.word 0x34 16.--31. 1. "NU,Reserved"
hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral"
newline
hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C"
line.long 0x38 "ICPID2,I2C Peripheral ID register 2"
hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral"
line.long 0x3C "ICDMAC,I2C DMA Control Register"
hexmask.long 0x3C 2.--31. 1. "NU,Reserved"
bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable" "0,1"
newline
bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable" "0,1"
group.long 0x48++0x1B
line.long 0x00 "ICPFUNC,I2C Pin Function register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved"
bitfld.long 0x00 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins" "Pins function as SCL and SDA,Pins functions as GPIO"
line.long 0x04 "ICPDIR,I2C Pin Direction register"
hexmask.long 0x04 2.--31. 1. "NU,Reserved"
bitfld.long 0x04 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO" "SDA pin functions as input,SDA pin functions as output"
newline
bitfld.long 0x04 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO" "SCL pin functions as input,SCL pin functions as output"
line.long 0x08 "ICPDIN,I2C Pin Data In register"
hexmask.long 0x08 2.--31. 1. "NU,Reserved"
bitfld.long 0x08 1. "PDIN1,Indicates the logic level present on the SDA pin" "Logic low present at SDA pin regardless of PFUNC..,Logic high present at SDA pin regardless of.."
newline
bitfld.long 0x08 0. "PDIN0,Indicates the logic level present on the SCL pin" "Logic low present at SCL pin regardless of PFUNC..,Logic high present at SCL pin regardless of.."
line.long 0x0C "ICPDOUT,I2C Pin Data Out register"
hexmask.long 0x0C 2.--31. 1. "NU,Reserved"
bitfld.long 0x0C 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output" "SDA pin driven low,SDA pin driven high"
newline
bitfld.long 0x0C 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output" "SCL pin driven low,SCL pin driven high"
line.long 0x10 "ICPDSET,I2C Pin Data Set register"
hexmask.long 0x10 2.--31. 1. "NU,Reserved"
bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin" "no effect,PDOUT[1] bit is set to.."
newline
bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin" "no effect,PDOUT[0] bit is set to.."
line.long 0x14 "ICPDCLR,I2C Pin Data Clear register"
hexmask.long 0x14 2.--31. 1. "NU,Reserved"
bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin" "no effect,PDOUT[1] bit is cleared.."
newline
bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin" "no effect,PDOUT[0] bit is cleared.."
line.long 0x18 "ICPDRV,I2C Pin Driver Mode Register"
hexmask.long 0x18 2.--31. 1. "NU,Reserved"
bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin" "I2C mode,GPIO mode"
newline
bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin" "I2C mode,GPIO mode"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "I2C_RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "RCSS_MCASP_A (RCSS McASP A Module Registers)"
base ad:0x51E0000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 2.--5. "UNDEFINED_NAME,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Power management Configuration of the local target state management mode" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x10++0x13
line.long 0x00 "PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "UNDEFINED_NAME,Determines if AFSR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 28. "UNDEFINED_NAME,Determines if AFSX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x00 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x00 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x04 "PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "UNDEFINED_NAME,Determines if AFSR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 28. "UNDEFINED_NAME,Determines if AFSX pin functions as an input or output" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as an input or output" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x04 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x04 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as an input or output" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x08 "PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "UNDEFINED_NAME,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 30. "UNDEFINED_NAME,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x08 29. "UNDEFINED_NAME,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 28. "UNDEFINED_NAME,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x08 27. "UNDEFINED_NAME,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 26. "UNDEFINED_NAME,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x08 25. "UNDEFINED_NAME,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x08 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x08 0.--3. "UNDEFINED_NAME,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x0C "PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "UNDEFINED_NAME,Logic level on AFSR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 30. "UNDEFINED_NAME,Logic level on AHCLKR pin" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 29. "UNDEFINED_NAME,Logic level on ACLKR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 28. "UNDEFINED_NAME,Logic level on AFSX pin" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 27. "UNDEFINED_NAME,Logic level on AHCLKX pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 26. "UNDEFINED_NAME,Logic level on ACLKX pin" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 25. "UNDEFINED_NAME,Logic level on AMUTE pin" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x0C 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x0C 0.--3. "UNDEFINED_NAME,Logic level on AXR[n] pin" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x10 "PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "UNDEFINED_NAME,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 30. "UNDEFINED_NAME,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 29. "UNDEFINED_NAME,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 28. "UNDEFINED_NAME,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 27. "UNDEFINED_NAME,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 26. "UNDEFINED_NAME,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 25. "UNDEFINED_NAME,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x10 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x10 0.--3. "UNDEFINED_NAME,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
group.long 0x44++0x0F
line.long 0x00 "GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 12. "UNDEFINED_NAME,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 11. "UNDEFINED_NAME,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 10. "UNDEFINED_NAME,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 9. "UNDEFINED_NAME,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 8. "UNDEFINED_NAME,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 7. "UNDEFINED_NAME,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 6. "UNDEFINED_NAME,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 5. "UNDEFINED_NAME,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x04 4. "UNDEFINED_NAME,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 3. "UNDEFINED_NAME,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2. "UNDEFINED_NAME,Audio mute in [AMUTEIN] polarity select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 0.--1. "UNDEFINED_NAME,AMUTE pin enable bit [unless overridden by GPIO registers]" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Loopback generator mode bits" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 1. "UNDEFINED_NAME,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Loopback mode enable bit" "en_1_0x0,en_2_0x1"
line.long 0x0C "DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Valid bit for odd time slots [DIT right subframe]" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 2. "UNDEFINED_NAME,Valid bit for even time slots [DIT left subframe]" "en_1_0x0,en_2_0x1"
rbitfld.long 0x0C 1. "UNDEFINED_NAME," "0,1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,DIT mode enable bit" "en_1_0x0,en_2_0x1"
group.long 0x60++0x2F
line.long 0x00 "RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "0,1"
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rbitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "0,1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Receive bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 15. "UNDEFINED_NAME,Receive serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to the word" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 8.--12. "UNDEFINED_NAME,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Receive slot size" "en_7_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_5_0xA,en_1_0xB,en_4_0xC,en_2_0xD,en_6_0xE,en_3_0xF"
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bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for receive rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Receive frame sync mode select bits"
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rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Receive frame sync generation select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,Receive frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Receive bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Receive bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Receive high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Receive bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Receive start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Receive data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Receive last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Receive DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Receive clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected receive frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Receiver overrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Receive DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Receive start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Receive data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Receive last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of RSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Receive clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected receive frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Receiver overrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--8. 1. "UNDEFINED_NAME,"
line.long 0x28 "RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Receive clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Receive clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Receive data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0xA0++0x2F
line.long 0x00 "XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "0,1"
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rbitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Transmit sync bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 15. "UNDEFINED_NAME,Transmit serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to word defined by XMASK" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 8.--12. "UNDEFINED_NAME,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Transmit slot size" "en_2_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_7_0xA,en_5_0xB,en_6_0xC,en_3_0xD,en_1_0xE,en_4_0xF"
newline
bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for transmit rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Transmit frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Transmit frame sync generation select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,Transmit frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Transmit bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 6. "UNDEFINED_NAME,Transmit/receive operation asynchronous enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Transmit bit clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Transmit high-frequency clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x14 14. "UNDEFINED_NAME,Transmit bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Transmit start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Transmit data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Transmit DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 2. "UNDEFINED_NAME,Transmit clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected transmit frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 0. "UNDEFINED_NAME,Transmitter underrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 7. "UNDEFINED_NAME,Transmit DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Transmit start of frame flag" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 5. "UNDEFINED_NAME,Transmit data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Transmit last slot flag" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of XSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Transmit clock failure flag" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected transmit frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Transmitter underrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--9. 1. "UNDEFINED_NAME,Current transmit time slot count"
line.long 0x28 "XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Transmit clock maximum boundary"
newline
hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Transmit clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Transmit data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
group.long 0x180++0x3F
line.long 0x00 "SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x00 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x00 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x04 "SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x04 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x04 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x08 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x08 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x08 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x0C "SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x0C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x0C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x0C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x10 "SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x10 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x10 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x10 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x10 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x14 "SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x14 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x14 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x14 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x14 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x14 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x18 "SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x18 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x18 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x18 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x18 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x18 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x1C "SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x1C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x1C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x1C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x20 "SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x20 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x20 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x20 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x20 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x24 "SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x24 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x24 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x24 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x24 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x24 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x28 "SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x28 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x28 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x28 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x28 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x28 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x2C "SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x2C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x2C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x2C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x2C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x2C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x30 "SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x30 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x30 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x30 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x30 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x30 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x34 "SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x34 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x34 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x34 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x34 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x34 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x38 "SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x38 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x38 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x38 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x38 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x38 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x3C "SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x3C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x3C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x3C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x3C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x3C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x1000++0x0F
line.long 0x00 "WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 16. "UNDEFINED_NAME,Write FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
hexmask.long.byte 0x00 8.--15. 1. "UNDEFINED_NAME,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "UNDEFINED_NAME,Write word count per transfer [32 bit words]"
line.long 0x04 "WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x04 0.--7. "UNDEFINED_NAME,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16. "UNDEFINED_NAME,Read FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
abitfld.long 0x08 8.--15. "UNDEFINED_NAME,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "UNDEFINED_NAME,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x0C 0.--7. "UNDEFINED_NAME,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
width 0x0B
tree.end
tree "RCSS_MCASP_B (RCSS McASP B Module Registers)"
base ad:0x5200000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 2.--5. "UNDEFINED_NAME,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Power management Configuration of the local target state management mode" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x10++0x13
line.long 0x00 "PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "UNDEFINED_NAME,Determines if AFSR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 28. "UNDEFINED_NAME,Determines if AFSX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x00 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x00 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x04 "PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "UNDEFINED_NAME,Determines if AFSR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 28. "UNDEFINED_NAME,Determines if AFSX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as an input or output" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x04 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as an input or output" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x08 "PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "UNDEFINED_NAME,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 30. "UNDEFINED_NAME,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 29. "UNDEFINED_NAME,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 28. "UNDEFINED_NAME,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 27. "UNDEFINED_NAME,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 26. "UNDEFINED_NAME,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 25. "UNDEFINED_NAME,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x08 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x0C "PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "UNDEFINED_NAME,Logic level on AFSR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 30. "UNDEFINED_NAME,Logic level on AHCLKR pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 29. "UNDEFINED_NAME,Logic level on ACLKR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 28. "UNDEFINED_NAME,Logic level on AFSX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 27. "UNDEFINED_NAME,Logic level on AHCLKX pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 26. "UNDEFINED_NAME,Logic level on ACLKX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 25. "UNDEFINED_NAME,Logic level on AMUTE pin" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x0C 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x0C 0.--3. "UNDEFINED_NAME,Logic level on AXR[n] pin" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x10 "PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "UNDEFINED_NAME,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 30. "UNDEFINED_NAME,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 29. "UNDEFINED_NAME,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 28. "UNDEFINED_NAME,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 27. "UNDEFINED_NAME,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 26. "UNDEFINED_NAME,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 25. "UNDEFINED_NAME,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x10 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x10 0.--3. "UNDEFINED_NAME,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
group.long 0x44++0x0F
line.long 0x00 "GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 12. "UNDEFINED_NAME,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 11. "UNDEFINED_NAME,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 10. "UNDEFINED_NAME,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 9. "UNDEFINED_NAME,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 8. "UNDEFINED_NAME,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 7. "UNDEFINED_NAME,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 6. "UNDEFINED_NAME,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 5. "UNDEFINED_NAME,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x04 4. "UNDEFINED_NAME,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 3. "UNDEFINED_NAME,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2. "UNDEFINED_NAME,Audio mute in [AMUTEIN] polarity select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,AMUTE pin enable bit [unless overridden by GPIO registers]" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Loopback generator mode bits" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 1. "UNDEFINED_NAME,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Loopback mode enable bit" "en_1_0x0,en_2_0x1"
line.long 0x0C "DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Valid bit for odd time slots [DIT right subframe]" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 2. "UNDEFINED_NAME,Valid bit for even time slots [DIT left subframe]" "en_1_0x0,en_2_0x1"
rbitfld.long 0x0C 1. "UNDEFINED_NAME," "0,1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,DIT mode enable bit" "en_1_0x0,en_2_0x1"
group.long 0x60++0x2F
line.long 0x00 "RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Receive bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 15. "UNDEFINED_NAME,Receive serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to the word" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 8.--12. "UNDEFINED_NAME,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Receive slot size" "en_7_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_5_0xA,en_1_0xB,en_4_0xC,en_2_0xD,en_6_0xE,en_3_0xF"
newline
bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for receive rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Receive frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Receive frame sync generation select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,Receive frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Receive bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x10 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Receive bit clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Receive high-frequency clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x14 14. "UNDEFINED_NAME,Receive bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Receive start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Receive data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 4. "UNDEFINED_NAME,Receive last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Receive DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 2. "UNDEFINED_NAME,Receive clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected receive frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 0. "UNDEFINED_NAME,Receiver overrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 7. "UNDEFINED_NAME,Receive DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Receive start of frame flag" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 5. "UNDEFINED_NAME,Receive data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Receive last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of RSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Receive clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected receive frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Receiver overrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--8. 1. "UNDEFINED_NAME,"
line.long 0x28 "RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Receive clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Receive clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Receive data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0xA0++0x2F
line.long 0x00 "XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "0,1"
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rbitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Transmit sync bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 15. "UNDEFINED_NAME,Transmit serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to word defined by XMASK" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 8.--12. "UNDEFINED_NAME,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Transmit slot size" "en_2_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_7_0xA,en_5_0xB,en_6_0xC,en_3_0xD,en_1_0xE,en_4_0xF"
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bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for transmit rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Transmit frame sync mode select bits"
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rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Transmit frame sync generation select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,Transmit frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Transmit bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 6. "UNDEFINED_NAME,Transmit/receive operation asynchronous enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Transmit bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Transmit high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Transmit bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Transmit start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Transmit data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Transmit DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Transmit clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected transmit frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Transmitter underrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Transmit DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Transmit start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Transmit data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Transmit last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of XSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Transmit clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected transmit frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Transmitter underrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--9. 1. "UNDEFINED_NAME,Current transmit time slot count"
line.long 0x28 "XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Transmit clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Transmit clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Transmit data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
group.long 0x180++0x3F
line.long 0x00 "SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x00 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x04 "SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x04 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x04 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x08 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x08 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x08 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x0C "SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x0C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x0C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x0C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x10 "SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x10 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x10 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x10 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x14 "SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x14 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x14 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x14 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x14 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x14 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x18 "SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x18 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x18 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x18 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x18 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x18 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x1C "SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x1C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x1C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x1C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x20 "SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x20 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x20 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x20 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x20 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x24 "SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x24 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x24 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x24 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x24 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x24 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x28 "SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x28 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x28 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x28 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x28 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x28 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x2C "SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x2C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x2C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x2C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x2C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x2C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x30 "SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x30 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x30 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x30 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x30 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x30 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x34 "SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x34 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x34 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x34 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x34 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x34 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x38 "SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x38 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x38 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x38 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x38 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x38 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x3C "SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x3C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x3C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x3C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x3C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x3C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x1000++0x0F
line.long 0x00 "WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 16. "UNDEFINED_NAME,Write FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
hexmask.long.byte 0x00 8.--15. 1. "UNDEFINED_NAME,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "UNDEFINED_NAME,Write word count per transfer [32 bit words]"
line.long 0x04 "WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x04 0.--7. "UNDEFINED_NAME,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16. "UNDEFINED_NAME,Read FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
abitfld.long 0x08 8.--15. "UNDEFINED_NAME,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "UNDEFINED_NAME,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x0C 0.--7. "UNDEFINED_NAME,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
width 0x0B
tree.end
tree "RCSS_MCASP_C (RCSS McASP C Module Registers)"
base ad:0x5220000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 2.--5. "UNDEFINED_NAME,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Power management Configuration of the local target state management mode" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x10++0x13
line.long 0x00 "PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "UNDEFINED_NAME,Determines if AFSR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 28. "UNDEFINED_NAME,Determines if AFSX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x00 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x00 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x04 "PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "UNDEFINED_NAME,Determines if AFSR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 28. "UNDEFINED_NAME,Determines if AFSX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as an input or output" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x04 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as an input or output" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x08 "PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "UNDEFINED_NAME,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 30. "UNDEFINED_NAME,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 29. "UNDEFINED_NAME,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 28. "UNDEFINED_NAME,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 27. "UNDEFINED_NAME,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 26. "UNDEFINED_NAME,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 25. "UNDEFINED_NAME,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x08 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x0C "PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "UNDEFINED_NAME,Logic level on AFSR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 30. "UNDEFINED_NAME,Logic level on AHCLKR pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 29. "UNDEFINED_NAME,Logic level on ACLKR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 28. "UNDEFINED_NAME,Logic level on AFSX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 27. "UNDEFINED_NAME,Logic level on AHCLKX pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 26. "UNDEFINED_NAME,Logic level on ACLKX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 25. "UNDEFINED_NAME,Logic level on AMUTE pin" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x0C 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x0C 0.--3. "UNDEFINED_NAME,Logic level on AXR[n] pin" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x10 "PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "UNDEFINED_NAME,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 30. "UNDEFINED_NAME,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 29. "UNDEFINED_NAME,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 28. "UNDEFINED_NAME,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 27. "UNDEFINED_NAME,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 26. "UNDEFINED_NAME,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 25. "UNDEFINED_NAME,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x10 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x10 0.--3. "UNDEFINED_NAME,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
group.long 0x44++0x0F
line.long 0x00 "GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 12. "UNDEFINED_NAME,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 11. "UNDEFINED_NAME,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 10. "UNDEFINED_NAME,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 9. "UNDEFINED_NAME,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 8. "UNDEFINED_NAME,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 7. "UNDEFINED_NAME,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 6. "UNDEFINED_NAME,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 5. "UNDEFINED_NAME,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x04 4. "UNDEFINED_NAME,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 3. "UNDEFINED_NAME,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2. "UNDEFINED_NAME,Audio mute in [AMUTEIN] polarity select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,AMUTE pin enable bit [unless overridden by GPIO registers]" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Loopback generator mode bits" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 1. "UNDEFINED_NAME,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Loopback mode enable bit" "en_1_0x0,en_2_0x1"
line.long 0x0C "DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Valid bit for odd time slots [DIT right subframe]" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 2. "UNDEFINED_NAME,Valid bit for even time slots [DIT left subframe]" "en_1_0x0,en_2_0x1"
rbitfld.long 0x0C 1. "UNDEFINED_NAME," "0,1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,DIT mode enable bit" "en_1_0x0,en_2_0x1"
group.long 0x60++0x2F
line.long 0x00 "RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Receive bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 15. "UNDEFINED_NAME,Receive serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to the word" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 8.--12. "UNDEFINED_NAME,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Receive slot size" "en_7_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_5_0xA,en_1_0xB,en_4_0xC,en_2_0xD,en_6_0xE,en_3_0xF"
newline
bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for receive rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Receive frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Receive frame sync generation select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,Receive frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Receive bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Receive bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Receive high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Receive bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Receive start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Receive data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Receive last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Receive DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Receive clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected receive frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Receiver overrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Receive DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Receive start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Receive data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Receive last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of RSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Receive clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected receive frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Receiver overrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--8. 1. "UNDEFINED_NAME,"
line.long 0x28 "RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Receive clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Receive clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Receive data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0xA0++0x2F
line.long 0x00 "XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "0,1"
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rbitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Transmit sync bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 15. "UNDEFINED_NAME,Transmit serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to word defined by XMASK" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 8.--12. "UNDEFINED_NAME,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Transmit slot size" "en_2_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_7_0xA,en_5_0xB,en_6_0xC,en_3_0xD,en_1_0xE,en_4_0xF"
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bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for transmit rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Transmit frame sync mode select bits"
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rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Transmit frame sync generation select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,Transmit frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Transmit bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 6. "UNDEFINED_NAME,Transmit/receive operation asynchronous enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Transmit bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Transmit high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Transmit bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Transmit start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Transmit data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Transmit DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Transmit clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected transmit frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Transmitter underrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Transmit DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Transmit start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Transmit data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Transmit last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of XSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Transmit clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected transmit frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Transmitter underrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--9. 1. "UNDEFINED_NAME,Current transmit time slot count"
line.long 0x28 "XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Transmit clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Transmit clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Transmit data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
group.long 0x180++0x3F
line.long 0x00 "SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x00 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x04 "SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x04 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x04 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x08 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x08 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x08 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x0C "SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x0C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x0C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x0C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x10 "SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x10 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x10 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x10 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x14 "SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x14 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x14 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x14 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x14 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x14 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x18 "SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x18 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x18 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x18 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x18 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x18 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x1C "SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x1C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x1C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x1C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x20 "SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x20 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x20 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x20 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x24 "SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x24 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x24 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x24 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x24 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x24 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x28 "SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x28 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x28 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x28 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x28 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x28 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x2C "SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x2C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x2C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x2C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x2C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x2C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x30 "SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x30 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x30 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x30 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x30 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x30 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x34 "SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x34 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x34 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x34 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x34 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x34 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x38 "SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x38 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x38 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x38 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x38 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x38 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x3C "SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x3C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x3C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x3C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x3C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x3C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x1000++0x0F
line.long 0x00 "WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 16. "UNDEFINED_NAME,Write FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
hexmask.long.byte 0x00 8.--15. 1. "UNDEFINED_NAME,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "UNDEFINED_NAME,Write word count per transfer [32 bit words]"
line.long 0x04 "WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x04 0.--7. "UNDEFINED_NAME,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16. "UNDEFINED_NAME,Read FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
abitfld.long 0x08 8.--15. "UNDEFINED_NAME,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "UNDEFINED_NAME,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x0C 0.--7. "UNDEFINED_NAME,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
width 0x0B
tree.end
tree "RCSS_PCR (RCSS PCR Module Registers)"
base ad:0x5F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "RCSS_RCM (RCSS RCM Module Registers)"
base ad:0x5000000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x12F
line.long 0x00 "RCSS_I2CA_CLK_SRC_SEL,"
hexmask.long.word 0x00 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS_I2CA"
line.long 0x04 "RCSS_I2CB_CLK_SRC_SEL,"
hexmask.long.word 0x04 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS I2CB"
line.long 0x08 "RCSS_SCIA_CLK_SRC_SEL,"
hexmask.long.word 0x08 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS SCIA"
line.long 0x0C "RCSS_SPIA_CLK_SRC_SEL,"
hexmask.long.word 0x0C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS_SPIA"
line.long 0x10 "RCSS_SPIB_CLK_SRC_SEL,"
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS SPIB"
line.long 0x14 "RCSS_ATL_CLK_SRC_SEL,"
hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS ATL CLK Data should be loaded as multibit"
line.long 0x18 "RCSS_MCASPA_REF0_CLK_SRC_SEL,"
hexmask.long.word 0x18 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPA REF0 CLK Data should be loaded as multibit"
line.long 0x1C "RCSS_MCASPA_REF1_CLK_SRC_SEL,"
hexmask.long.word 0x1C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPA REF1 CLK"
line.long 0x20 "RCSS_MCASPA_AUX_CLK_SRC_SEL,"
hexmask.long.word 0x20 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPA AUX CLK Data should be loaded as multibit"
line.long 0x24 "RCSS_MCASPB_REF0_CLK_SRC_SEL,"
hexmask.long.word 0x24 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPB REF0 CLK Data should be loaded as multibit"
line.long 0x28 "RCSS_MCASPB_REF1_CLK_SRC_SEL,"
hexmask.long.word 0x28 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPB REF1 CLK"
line.long 0x2C "RCSS_MCASPB_AUX_CLK_SRC_SEL,"
hexmask.long.word 0x2C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPB AUX CLK Data should be loaded as multibit"
line.long 0x30 "RCSS_MCASPC_REF0_CLK_SRC_SEL,"
hexmask.long.word 0x30 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPC REF0 CLK Data should be loaded as multibit"
line.long 0x34 "RCSS_MCASPC_REF1_CLK_SRC_SEL,"
hexmask.long.word 0x34 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPC REF1 CLK"
line.long 0x38 "RCSS_MCASPC_AUX_CLK_SRC_SEL,"
hexmask.long.word 0x38 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPC AUX CLK Data should be loaded as multibit"
line.long 0x3C "RCSS_I2CA_CLK_DIV_VAL,"
hexmask.long.word 0x3C 0.--11. 1. "clkdiv,Divider value for RCSS I2CA selected clock"
line.long 0x40 "RCSS_I2CB_CLK_DIV_VAL,"
hexmask.long.word 0x40 0.--11. 1. "clkdiv,Divider value for RCSS I2CB selected clock"
line.long 0x44 "RCSS_SCIA_CLK_DIV_VAL,"
hexmask.long.word 0x44 0.--11. 1. "clkdiv,Divider value for RCSS SCIA selected clock"
line.long 0x48 "RCSS_SPIA_CLK_DIV_VAL,"
hexmask.long.word 0x48 0.--11. 1. "clkdiv,Divider value for RCSS SPIA selected clock"
line.long 0x4C "RCSS_SPIB_CLK_DIV_VAL,"
hexmask.long.word 0x4C 0.--11. 1. "clkdiv,Divider value for RCSS SPIB selected clock"
line.long 0x50 "RCSS_ATL_CLK_DIV_VAL,"
hexmask.long.word 0x50 0.--11. 1. "clkdiv,Divider value for RCSS ATL CLK selected clock"
line.long 0x54 "RCSS_MCASPA_REF0_CLK_DIV_VAL,"
hexmask.long.word 0x54 0.--11. 1. "clkdiv,Divider value for RCSS MCASPA REF0 CLK selected clock"
line.long 0x58 "RCSS_MCASPA_REF1_CLK_DIV_VAL,"
hexmask.long.word 0x58 0.--11. 1. "clkdiv,Divider value for RCSS MCASPA REF1 CLK selected clock"
line.long 0x5C "RCSS_MCASPA_AUX_CLK_DIV_VAL,"
hexmask.long.word 0x5C 0.--11. 1. "clkdiv,Divider value for RCSS MCASPA AUX CLK selected clock"
line.long 0x60 "RCSS_MCASPB_REF0_CLK_DIV_VAL,"
hexmask.long.word 0x60 0.--11. 1. "clkdiv,Divider value for RCSS MCASPB REF0 CLK selected clock"
line.long 0x64 "RCSS_MCASPB_REF1_CLK_DIV_VAL,"
hexmask.long.word 0x64 0.--11. 1. "clkdiv,Divider value for RCSS MCASPB REF1 CLK selected clock"
line.long 0x68 "RCSS_MCASPB_AUX_CLK_DIV_VAL,"
hexmask.long.word 0x68 0.--11. 1. "clkdiv,Divider value for RCSS MCASPB AUX CLK selected clock"
line.long 0x6C "RCSS_MCASPC_REF0_CLK_DIV_VAL,"
hexmask.long.word 0x6C 0.--11. 1. "clkdiv,Divider value for RCSS MCASPC REF0 CLK selected clock"
line.long 0x70 "RCSS_MCASPC_REF1_CLK_DIV_VAL,"
hexmask.long.word 0x70 0.--11. 1. "clkdiv,Divider value for RCSS MCASPC REF1 CLK selected clock"
line.long 0x74 "RCSS_MCASPC_AUX_CLK_DIV_VAL,"
hexmask.long.word 0x74 0.--11. 1. "clkdiv,Divider value for RCSS MCASPC AUX CLK selected clock"
line.long 0x78 "RCSS_I2CA_CLK_GATE,"
bitfld.long 0x78 0.--2. "gated,Clock gatring config for RCSS I2CA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x7C "RCSS_I2CB_CLK_GATE,"
bitfld.long 0x7C 0.--2. "gated,Clock gatring config for RCSS I2CB Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x80 "RCSS_SCIA_CLK_GATE,"
bitfld.long 0x80 0.--2. "gated,Clock gatring config for RCSS SCIA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x84 "RCSS_SPIA_CLK_GATE,"
bitfld.long 0x84 0.--2. "gated,Clock gatring config for RCSS SPIA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x88 "RCSS_SPIB_CLK_GATE,"
bitfld.long 0x88 0.--2. "gated,Clock gatring config for RCSS SPIB Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x8C "RCSS_ATL_CLK_GATE,"
bitfld.long 0x8C 0.--2. "gated,Clock gatring config for RCSS ATL CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x90 "RCSS_MCASPA_REF0_CLK_GATE,"
bitfld.long 0x90 0.--2. "gated,Clock gatring config for RCSS MCASPA REF0 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x94 "RCSS_MCASPA_REF1_CLK_GATE,"
bitfld.long 0x94 0.--2. "gated,Clock gatring config for RCSS MCASPA REF1 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x98 "RCSS_MCASPA_AUX_CLK_GATE,"
bitfld.long 0x98 0.--2. "gated,Clock gatring config for RCSS MCASPA AUX CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x9C "RCSS_MCASPB_REF0_CLK_GATE,"
bitfld.long 0x9C 0.--2. "gated,Clock gatring config for RCSS MCASPB REF0 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xA0 "RCSS_MCASPB_REF1_CLK_GATE,"
bitfld.long 0xA0 0.--2. "gated,Clock gatring config for RCSS MCASPB REF1 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xA4 "RCSS_MCASPB_AUX_CLK_GATE,"
bitfld.long 0xA4 0.--2. "gated,Clock gatring config for RCSS MCASPB AUX CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xA8 "RCSS_MCASPC_REF0_CLK_GATE,"
bitfld.long 0xA8 0.--2. "gated,Clock gatring config for RCSS MCASPC REF0 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xAC "RCSS_MCASPC_REF1_CLK_GATE,"
bitfld.long 0xAC 0.--2. "gated,Clock gatring config for RCSS MCASPC REF1 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xB0 "RCSS_MCASPC_AUX_CLK_GATE,"
bitfld.long 0xB0 0.--2. "gated,Clock gatring config for RCSS MCASPC AUX CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xB4 "RCSS_ECAP_SYS_CLK_GATE,"
bitfld.long 0xB4 0.--2. "gated,Clock gatring config for RCSS ECAP Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xB8 "RCSS_CSI2A_SYS_CLK_GATE,"
bitfld.long 0xB8 0.--2. "gated,Clock gatring config for RCSS CSI2A Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xBC "RCSS_CSI2B_SYS_CLK_GATE,"
bitfld.long 0xBC 0.--2. "gated,Clock gatring config for RCSS CSI2B Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xC0 "RCSS_I2CA_CLK_STATUS,"
hexmask.long.byte 0xC0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS I2CA Clock"
hexmask.long.byte 0xC0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS I2CA Clock"
line.long 0xC4 "RCSS_I2CB_CLK_STATUS,"
hexmask.long.byte 0xC4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS I2CB Clock"
hexmask.long.byte 0xC4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS I2CB Clock"
line.long 0xC8 "RCSS_SCIA_CLK_STATUS,"
hexmask.long.byte 0xC8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS SCIA Clock"
hexmask.long.byte 0xC8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS SCIA Clock"
line.long 0xCC "RCSS_SPIA_CLK_STATUS,"
hexmask.long.byte 0xCC 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS SPIA Clock"
hexmask.long.byte 0xCC 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS SPIA Clock"
line.long 0xD0 "RCSS_SPIB_CLK_STATUS,"
hexmask.long.byte 0xD0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS SPIB Clock"
hexmask.long.byte 0xD0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS SPIB Clock"
line.long 0xD4 "RCSS_ATL_CLK_STATUS,"
hexmask.long.byte 0xD4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS ATL_CLK Clock"
hexmask.long.byte 0xD4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS ATL_CLK Clock"
line.long 0xD8 "RCSS_MCASPA_REF0_CLK_STATUS,"
hexmask.long.byte 0xD8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPA_REF0_CLK Clock"
hexmask.long.byte 0xD8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPA_REF0_CLK Clock"
line.long 0xDC "RCSS_MCASPA_REF1_CLK_STATUS,"
hexmask.long.byte 0xDC 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPA_REF1_CLK Clock"
hexmask.long.byte 0xDC 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPA_REF1_CLK Clock"
line.long 0xE0 "RCSS_MCASPA_AUX_CLK_STATUS,"
hexmask.long.byte 0xE0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPA_AUX_CLK Clock"
hexmask.long.byte 0xE0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPA_AUX_CLK Clock"
line.long 0xE4 "RCSS_MCASPB_REF0_CLK_STATUS,"
hexmask.long.byte 0xE4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPB_REF0_CLK Clock"
hexmask.long.byte 0xE4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPB_REF0_CLK Clock"
line.long 0xE8 "RCSS_MCASPB_REF1_CLK_STATUS,"
hexmask.long.byte 0xE8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPB_REF1_CLK Clock"
hexmask.long.byte 0xE8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPB_REF1_CLK Clock"
line.long 0xEC "RCSS_MCASPB_AUX_CLK_STATUS,"
hexmask.long.byte 0xEC 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPB_AUX_CLK Clock"
hexmask.long.byte 0xEC 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPB_AUX_CLK Clock"
line.long 0xF0 "RCSS_MCASPC_REF0_CLK_STATUS,"
hexmask.long.byte 0xF0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPC_REF0_CLK Clock"
hexmask.long.byte 0xF0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPC_REF0_CLK Clock"
line.long 0xF4 "RCSS_MCASPC_REF1_CLK_STATUS,"
hexmask.long.byte 0xF4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPC_REF1_CLK Clock"
hexmask.long.byte 0xF4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPC_REF1_CLK Clock"
line.long 0xF8 "RCSS_MCASPC_AUX_CLK_STATUS,"
hexmask.long.byte 0xF8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPC_AUX_CLK Clock"
hexmask.long.byte 0xF8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPC_AUX_CLK Clock"
line.long 0xFC "RCSS_ECAP_RST_CTRL,"
bitfld.long 0xFC 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x100 "RCSS_CSI2A_RST_CTRL,"
bitfld.long 0x100 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x104 "RCSS_CSI2B_RST_CTRL,"
bitfld.long 0x104 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x108 "RCSS_I2CA_RST_CTRL,"
bitfld.long 0x108 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x10C "RCSS_I2CB_RST_CTRL,"
bitfld.long 0x10C 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x110 "RCSS_SCIA_RST_CTRL,"
bitfld.long 0x110 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x114 "RCSS_SPIA_RST_CTRL,"
bitfld.long 0x114 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x118 "RCSS_SPIB_RST_CTRL,"
bitfld.long 0x118 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x11C "RCSS_MCASPA_RST_CTRL,"
bitfld.long 0x11C 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x120 "RCSS_MCASPB_RST_CTRL,"
bitfld.long 0x120 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x124 "RCSS_MCASPC_RST_CTRL,"
bitfld.long 0x124 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x128 "RCSS_GIO_RST_CTRL,"
bitfld.long 0x128 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x12C "RCSS_EDMA_RST_CTRL,"
bitfld.long 0x12C 12.--14. "tptca1_assert,writing '111' will reset MSS_TPTCA0" "0,1,2,3,4,5,6,7"
bitfld.long 0x12C 8.--10. "tptca0_assert,writing '111' will reset MSS_TPCCA" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x12C 4.--6. "tpcca_assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
bitfld.long 0x12C 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "RCSS_SCI_A (RCSS SCIA Module Registers)"
base ad:0x50C0000
group.long 0x00++0x07
line.long 0x00 "UARTDR,Data Register. UARTDR"
hexmask.long.tbyte 0x00 12.--31. 1. "NU0,Reserved"
bitfld.long 0x00 11. "OE,Overrun error" "0,1"
newline
bitfld.long 0x00 10. "BE,Break error" "0,1"
bitfld.long 0x00 9. "PE,Parity error" "0,1"
newline
bitfld.long 0x00 8. "FE,Framing error" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive data character & Transmit data character"
line.long 0x04 "UARTRSR_ECR,Receive Status Register/Error Clear Register."
hexmask.long 0x04 4.--31. 1. "NU1,Reserved unpredictable when"
bitfld.long 0x04 3. "OE,Overrun error" "0,1"
newline
bitfld.long 0x04 2. "BE,Break error" "0,1"
bitfld.long 0x04 1. "PE,Parity error" "0,1"
newline
bitfld.long 0x04 0. "FE,Framing error" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "UARTFR,Flag Register. UARTFR"
hexmask.long.tbyte 0x00 9.--31. 1. "NU2,Reserved do not modify read as zero"
bitfld.long 0x00 8. "RI,Ring indicator" "0,1"
newline
bitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1"
bitfld.long 0x00 6. "RXFF,Receive FIFO full" "0,1"
newline
bitfld.long 0x00 5. "TXFF,Transmit FIFO full" "0,1"
bitfld.long 0x00 4. "RXFE,Receive FIFO empty" "0,1"
newline
bitfld.long 0x00 3. "BUSY,UART busy" "0,1"
bitfld.long 0x00 2. "DCD,Data carrier detect" "0,1"
newline
bitfld.long 0x00 1. "DSR,Data set ready" "0,1"
bitfld.long 0x00 0. "CTS,Clear to send" "0,1"
group.long 0x20++0x2B
line.long 0x00 "UARTILPR,IrDA Low-Power Counter Register. UARTILPR"
hexmask.long.tbyte 0x00 8.--31. 1. "NU3,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "ILPDVSR,8-bit low-power divisor value"
line.long 0x04 "UARTIBRD,Integer Baud Rate Register. UARTIBRD"
hexmask.long.tbyte 0x04 8.--31. 1. "NU4,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "BAUD_DIVINT,The fractional baud rate divisor"
line.long 0x08 "UARTFBRD,Fractional Baud Rate Register. UARTFBRD"
hexmask.long 0x08 6.--31. 1. "NU5,Reserved"
bitfld.long 0x08 0.--5. "BAUD_DIVFRAC,The fractional baud rate divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "UARTLCR_H,Line Control Register. UARTLCR_H"
hexmask.long.tbyte 0x0C 8.--31. 1. "NU6,Reserved do not modify read as zero"
bitfld.long 0x0C 7. "SPS,Stick parity select" "stick parity is disabled,if the EPS bit is 0 then the parity bit is.."
newline
bitfld.long 0x0C 5.--6. "WLEN,Word length" "5 bits,6 bits,7 bits,8 bits"
bitfld.long 0x0C 4. "FEN,Enable FIFOs" "FIFOs are disabled (character mode) that is the..,transmit and receive FIFO buffers are enabled.."
newline
bitfld.long 0x0C 3. "STP2,Two stop bits select" "0,1"
bitfld.long 0x0C 2. "EPS,Even parity select" "odd parity,even parity"
newline
bitfld.long 0x0C 1. "PEN,Parity enable" "parity is disabled and no parity bit added to..,parity checking and generation is enabled"
bitfld.long 0x0C 0. "BRK,Send break" "0,1"
line.long 0x10 "UARTCR,Control Register. UARTCR"
hexmask.long.word 0x10 16.--31. 1. "NU7,Reserved do not modify read as zero"
bitfld.long 0x10 15. "CTSEn,CTS hardware flow control enable" "0,1"
newline
bitfld.long 0x10 14. "RTSEn,RTS hardware flow control enable" "0,1"
bitfld.long 0x10 13. "Out2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output" "0,1"
newline
bitfld.long 0x10 12. "Out1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output" "0,1"
bitfld.long 0x10 11. "RTS,Request to send" "0,1"
newline
bitfld.long 0x10 10. "DTR,Data transmit ready" "0,1"
bitfld.long 0x10 9. "RXE,Receive enable" "0,1"
newline
bitfld.long 0x10 8. "TXE,Transmit enable" "0,1"
bitfld.long 0x10 7. "LBE,Loopback enable" "0,1"
newline
rbitfld.long 0x10 3.--6. "NU6,Reserved do not modify read as zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 2. "SIRLP,SIR low-power IrDA mode" "0,1"
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bitfld.long 0x10 1. "SIREN,SIR enable" "IrDA SIR ENDEC is disabled,IrDA SIR ENDEC is enabled"
bitfld.long 0x10 0. "UARTEN,UART enable" "UART is disabled,the UART is enabled"
line.long 0x14 "UARTIFLS,Interrupt FIFO Level Select Register. UARTIFLS"
hexmask.long 0x14 6.--31. 1. "NU8,Reserved do not modify read as zero"
bitfld.long 0x14 3.--5. "RXIFLSEL,Receive interrupt FIFO level select" "Receive FIFO becomes >= 1/8 full,Receive FIFO becomes >= 1/4 full,Receive FIFO becomes >= 1/2 full,Receive FIFO becomes >= 3/4 full,Receive FIFO becomes >= 7/8 full b101-b111 =..,?..."
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bitfld.long 0x14 0.--2. "TXIFLSEL,Transmit interrupt FIFO level select" "Transmit FIFO becomes <= 1/8 full,Transmit FIFO becomes <= 1/4 full,Transmit FIFO becomes <= 1/2 full,Transmit FIFO becomes <= 3/4 full,Transmit FIFO becomes <= 7/8 full b101-b111 =..,?..."
line.long 0x18 "UARTIMSC,Interrupt Mask Set/Clear Register. UARTIMSC"
hexmask.long.tbyte 0x18 11.--31. 1. "NU9,Reserved read as zero do not modify"
bitfld.long 0x18 10. "OEIM,Overrun error interrupt mask" "0,1"
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bitfld.long 0x18 9. "BEIM,Break error interrupt mask" "0,1"
bitfld.long 0x18 8. "PEIM,Parity error interrupt mask" "0,1"
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bitfld.long 0x18 7. "FEIM,Framing error interrupt mask" "0,1"
bitfld.long 0x18 6. "RTIM,Receive timeout interrupt mask" "0,1"
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bitfld.long 0x18 5. "TXIM,Transmit interrupt mask" "0,1"
bitfld.long 0x18 4. "RXIM,Receive interrupt mask" "0,1"
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bitfld.long 0x18 3. "DSRMIM,nUARTDSR modem interrupt mask" "0,1"
bitfld.long 0x18 2. "DCDMIM,nUARTDCD modem interrupt mask" "0,1"
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bitfld.long 0x18 1. "CTSMIM,nUARTCTS modem interrupt mask" "0,1"
bitfld.long 0x18 0. "RIMIM,nUARTRI modem interrupt mask" "0,1"
line.long 0x1C "UARTRIS,Raw Interrupt Status Register. UARTRIS"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU10,Reserved read as zero do not modify"
bitfld.long 0x1C 9. "OERIS,Overrun error interrupt status" "0,1"
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bitfld.long 0x1C 8. "PERIS,Parity error interrupt status" "0,1"
bitfld.long 0x1C 7. "FERIS,Framing error interrupt status" "0,1"
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bitfld.long 0x1C 6. "RTRIS,Receive timeout interrupt status" "0,1"
bitfld.long 0x1C 5. "TXRIS,Transmit interrupt status" "0,1"
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bitfld.long 0x1C 4. "RXRIS,Receive interrupt status" "0,1"
bitfld.long 0x1C 3. "DSRRMIS,nUARTDSR modem interrupt status" "0,1"
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bitfld.long 0x1C 2. "DCDRMIS,nUARTDCD modem interrupt status" "0,1"
bitfld.long 0x1C 1. "CTSRMIS,nUARTCTS modem interrupt status" "0,1"
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bitfld.long 0x1C 0. "RIRMIS,nUARTRI modem interrupt status" "0,1"
line.long 0x20 "UARTMIS,Masked Interrupt Status Register. UARTMIS"
hexmask.long.tbyte 0x20 11.--31. 1. "NU11,Reserved read as zero do not modify"
bitfld.long 0x20 10. "OEMIS,Overrun error masked interrupt status" "0,1"
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bitfld.long 0x20 9. "BEMIS,Break error masked interrupt status" "0,1"
bitfld.long 0x20 8. "PEMIS,Parity error masked interrupt status" "0,1"
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bitfld.long 0x20 7. "FEMIS,Framing error masked interrupt status" "0,1"
bitfld.long 0x20 6. "RTMIS,Receive timeout masked interrupt status" "0,1"
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bitfld.long 0x20 5. "TXMIS,Transmit masked interrupt status" "0,1"
bitfld.long 0x20 4. "RXMIS,Receive masked interrupt status" "0,1"
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bitfld.long 0x20 3. "DSRMMIS,nUARTDSR modem masked interrupt status" "0,1"
bitfld.long 0x20 2. "DCDMMIS,nUARTDCD modem masked interrupt status" "0,1"
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bitfld.long 0x20 1. "CTSMMIS,nUARTCTS modem masked interrupt status" "0,1"
bitfld.long 0x20 0. "RIMMIS,nUARTRI modem masked" "0,1"
line.long 0x24 "UARTICR,Interrupt Clear Register. UARTICR"
hexmask.long.tbyte 0x24 11.--31. 1. "NU12,Reserved read as zero do not modify"
bitfld.long 0x24 10. "OEIC,Overrun error interrupt clear" "0,1"
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bitfld.long 0x24 9. "BEIC,Break error interrupt clear" "0,1"
bitfld.long 0x24 8. "PEIC,Parity error interrupt clear" "0,1"
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bitfld.long 0x24 7. "FEIC,Framing error interrupt clear" "0,1"
bitfld.long 0x24 6. "RTIC,Receive timeout interrupt clear" "0,1"
newline
bitfld.long 0x24 5. "TXIC,Transmit interrupt clear" "0,1"
bitfld.long 0x24 4. "RXIC,Receive interrupt clear" "0,1"
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bitfld.long 0x24 3. "DSRMIC,nUARTDSR modem interrupt clear" "0,1"
bitfld.long 0x24 2. "DCDMIC,nUARTDCD modem interrupt clear" "0,1"
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bitfld.long 0x24 1. "CTSMIC,nUARTCTS modem interrupt clear" "0,1"
bitfld.long 0x24 0. "RIMIC,nUARTRI modem interrupt clear" "0,1"
line.long 0x28 "UARTDMACR,DMA Control Register. UARTDMACR"
hexmask.long 0x28 3.--31. 1. "NU13,Reserved read as zero do not modify"
bitfld.long 0x28 2. "DMAONERR,DMA on error" "0,1"
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bitfld.long 0x28 1. "TXDMAE,Transmit DMA enable" "0,1"
bitfld.long 0x28 0. "RXDMAE,Receive DMA enable" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFF0)++0x03
line.long 0x00 "UARTPCellID$1,PrimeCell Identification Registers UARTPCellID0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "UARTPeriphID$1,Peripheral Identification Registers UARTPeriphID0"
repeat.end
width 0x0B
tree.end
tree "RCSS_SPIA (RCSS SPIA Module Registers)"
base ad:0x5F7E800
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
newline
rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
newline
bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
newline
bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
newline
bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
newline
rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
newline
rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
newline
bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
newline
bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
newline
hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
newline
bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
newline
bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
newline
rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
newline
bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
newline
rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
newline
bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
newline
bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
newline
bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
newline
bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
newline
bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
newline
abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
newline
rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
newline
bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
newline
bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
newline
bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
newline
abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
newline
abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
newline
rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
newline
bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
newline
bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
newline
bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
newline
abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
newline
bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
newline
bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
newline
bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
newline
bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
newline
abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
newline
rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
newline
bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
newline
bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
newline
bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
newline
abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
newline
rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
newline
bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
newline
bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
newline
bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
newline
abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
newline
rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
newline
bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
newline
bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
newline
bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
newline
abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
newline
abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
newline
rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
newline
bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
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bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
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rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
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rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
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bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
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bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
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hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
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bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
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rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "RCSS_SPIB (RCSS SPIB Module Registers)"
base ad:0x5F7EA00
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
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rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
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bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
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bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
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bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
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rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
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abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
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rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
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abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
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abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
newline
bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
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bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
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abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
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rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
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bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
newline
bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
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rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
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rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
newline
bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
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bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
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hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
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bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
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rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "RCSS_TPCC_A (RCSS TPCCA Module Registers)"
base ad:0x5100000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
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bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
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bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
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bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
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bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
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bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
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bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
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bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
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bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
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bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
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bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
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bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
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bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
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bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
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bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
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bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
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bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
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bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
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bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
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bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
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bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
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bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
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bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
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bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
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bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
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bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
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hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
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hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
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bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
newline
bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
newline
bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
newline
bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
newline
bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
newline
bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
newline
bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
newline
bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
newline
bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
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bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
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bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
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bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
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bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
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bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
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bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
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bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
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bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
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bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
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bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
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bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
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bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
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bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
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bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
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bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
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bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
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bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x5160000 ad:0x5180000 )
tree "RCSS_TPTC_A$1 (RCSS TPTC A$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
tree "TOP_AURORA_TX (TOP AURORA TX Module Registers)"
base ad:0x3060000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
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bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
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bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x0F
line.long 0x00 "AURORA_TX_CONFIG,"
bitfld.long 0x00 16.--18. "NUM_LANES,Selects the number of lanes for trasnmission" "1 Lane,2 Lanes,?,?,?,?,?,8Lanes"
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bitfld.long 0x00 2. "STRICT_ALIGN,Enable Aurora Strict Alingment Rules" "0,1"
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bitfld.long 0x00 1. "PROTOCOL_SEL,Selects if the IP is in 8b/10b OR 64b/66b mode" "8b/10b,64b/66b"
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bitfld.long 0x00 0. "ENABLE,Selects if the IP is in 8b/10b OR 64b/66b mode" "8b/10b,64b/66b"
line.long 0x04 "AURORA_TX_LANE_MAP,"
bitfld.long 0x04 28.--31. "LANE7_MAP,These 3 bits determine the logical lane that is transported over the physical lane 7" "Logical lane 0 is transported over physical lane 7,Logical lane 1 is transported over physical lane 7,?,?,?,?,?,Logical lane 7 is transported over physical lane 7,?..."
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bitfld.long 0x04 24.--27. "LANE6_MAP,These 3 bits determine the logical lane that is transported over the physical lane 6" "Logical lane 0 is transported over physical lane 6,Logical lane 1 is transported over physical lane 6,?,?,?,?,?,Logical lane 7 is transported over physical lane 6,?..."
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bitfld.long 0x04 20.--23. "LANE5_MAP,These 3 bits determine the logical lane that is transported over the physical lane 5" "Logical lane 0 is transported over physical lane 5,Logical lane 1 is transported over physical lane 5,?,?,?,?,?,Logical lane 7 is transported over physical lane 5,?..."
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bitfld.long 0x04 16.--19. "LANE4_MAP,These 3 bits determine the logical lane that is transported over the physical lane 4" "Logical lane 0 is transported over physical lane 4,Logical lane 1 is transported over physical lane 4,?,?,?,?,?,Logical lane 7 is transported over physical lane 4,?..."
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bitfld.long 0x04 12.--15. "LANE3_MAP,These 3 bits determine the logical lane that is transported over the physical lane 3" "Logical lane 0 is transported over physical lane 3,Logical lane 1 is transported over physical lane 3,?,?,?,?,?,Logical lane 7 is transported over physical lane 3,?..."
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bitfld.long 0x04 8.--11. "LANE2_MAP,These 3 bits determine the logical lane that is transported over the physical lane 2" "Logical lane 0 is transported over physical lane 2,Logical lane 1 is transported over physical lane 2,?,?,?,?,?,Logical lane 7 is transported over physical lane 2,?..."
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bitfld.long 0x04 4.--7. "LANE1_MAP,These 3 bits determine the logical lane that is transported over the physical lane 1" "Logical lane 0 is transported over physical lane 1,Logical lane 1 is transported over physical lane 1,?,?,?,?,?,Logical lane 7 is transported over physical lane 1,?..."
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bitfld.long 0x04 0.--3. "LANE0_MAP,These 3 bits determine the logical lane that is transported over the physical lane 0" "Logical lane 0 is transported over physical lane 0,Logical lane 0 is transported over physical lane 1,?,?,?,?,?,Logical lane 7 is transported over physical lane 0,?..."
line.long 0x08 "AURORA_TX_UDP_CONFIG,"
bitfld.long 0x08 16.--20. "FRAME_HEADER_EN,Header Enable configuration" "Disable Header transmission,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Number of 32 bit Header to be transmmited,?..."
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bitfld.long 0x08 8. "BYPASS_EN,Writing a value of" "Normal Mode - Framing is done as per aurora..,Bypass the aurora protocol"
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bitfld.long 0x08 7. "TEST_PATTERN_EN,Writing a value of" "0,1"
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bitfld.long 0x08 6. "TWP_SYNC_COMPRESSION_EN,Writing a value of" "Disable the TWP padding packet filter,Enables the compression of incoming.."
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bitfld.long 0x08 5. "CRC_EN,Writing a value of" "Disable UDP CRC calculation,Enable the UDP CRC calculation"
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bitfld.long 0x08 4. "TWP_IDLE_FILTER_EN,Writing a value of" "Disable the TWP padding packet filter,Filters out the incoming TWP Padding Packet from.."
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bitfld.long 0x08 0.--1. "PACK_MODE_SEL,Configure to select AURORATX_UDP_SIZE format" "Number of TWP Packets,Number of Bytes,?,SW only"
line.long 0x0C "AURORA_TX_UDP_SIZE,"
group.long 0x64++0x0F
line.long 0x00 "AURORA_TX_UFC_MSG_CTRL,"
bitfld.long 0x00 0. "UFC_MSG_SENT_STS,This bit indicates that the message send triggered by the SEND_MSG bit has been completed" "No effect,Clears this bit"
line.long 0x04 "AURORA_TX_UFC_MESSAGE0,"
line.long 0x08 "AURORA_TX_UFC_MESSAGE1,"
line.long 0x0C "AURORA_TX_TWP_SYNC_CNT,"
hexmask.long.word 0x0C 0.--9. 1. "SYNC_CNT,Number of TWP Sync Packet that would be sent if AURORA_TX_UDP_CONFIG::A_TX_UDP_CONFIG_TWP_SYNC_COMPRESSION_EN is 0x1"
group.long 0x80++0x1F
line.long 0x00 "AURORA_TX_INITIALIZE_REQ,"
bitfld.long 0x00 1. "TX_INIT,The single bit input to trigger the initialization sequence" "0,1"
line.long 0x04 "AURORA_TX_UFC_MSG_REQ,"
bitfld.long 0x04 0. "SEND_MSG,The bit that triggers the controller to send the MESSAGE0 and MESSAGE1 register contents as a UFC packet" "0,1"
line.long 0x08 "AURORA_TX_FLUSH_REQ,"
bitfld.long 0x08 0. "TRIGGER,Selects the number of lanes for trasnmission" "1 Lane,2 Lanes"
line.long 0x0C "AURORA_TX_EOP_REQ,"
bitfld.long 0x0C 0. "TRIGGER,SW End of Packet trigger to aurora dataframer" "0,1"
line.long 0x10 "AURORA_TX_DATA_START_REQ,"
bitfld.long 0x10 1. "DATA_START,The single bit input to trigger the initialization sequence" "0,1"
line.long 0x14 "AURORA_TX_DATA_STOP_REQ,"
bitfld.long 0x14 1. "DATA_STOP,The single bit input to trigger the Start of Data Transmission" "0,1"
line.long 0x18 "AURORA_TX_TESTPATTERN_START_REQ,"
bitfld.long 0x18 1. "TEST_PATTERN_START,The single bit input to trigger the Stop of Data Transmission" "0,1"
line.long 0x1C "AURORA_TX_TESTPATTERN_STOP_REQ,"
bitfld.long 0x1C 1. "TEST_PATTERN_STOP,The single bit input to trigger the Start of TestPattern Transmission" "0,1"
group.long 0x100++0x1F
line.long 0x00 "AURORA_TX_OVERRIDE,"
bitfld.long 0x00 22. "CC1_OVR_TYP,This read write bit indicates whether the CC1_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 21. "CC0_OVR_TYP,This read write bit indicates whether the CC0_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 20. "INIT_V3_OVR_TYP,This read write bit indicates whether the INIT_V3_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 19. "INIT_V2_OVR_TYP,This read write bit indicates whether the INIT_V2_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 18. "INIT_V1_OVR_TYP,This read write bit indicates whether the INIT_V1_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 17. "INIT_V0_OVR_TYP,This read write bit indicates whether the INIT_V0_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 16. "INIT_SP3_OVR_TYP,This read write bit indicates whether the INIT_SP3_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 15. "INIT_SP2_OVR_TYP,This read write bit indicates whether the INIT_SP2_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 14. "INIT_SP1_OVR_TYP,This read write bit indicates whether the INIT_SP1_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 13. "INIT_SP0_OVR_TYP,This read write bit indicates whether the INIT_SP0_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 12. "UFC_SUF_OVR_TYP,This read write bit indicates whether the UFC_SUF_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 11. "I2_OVR_TYP,This read write bit indicates whether the I2_OVR symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 10. "I1_OVR_TYP,This read write bit indicates whether the I1_OVR symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 9. "I0_OVR_TYP,This read write bit indicates whether the I0_OVR symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 8. "SYM_OVR_EN,This read write bit allows the symbols used in the various sequences to be overridden with the values used in the AURORA_TX_SYM register" "0,1"
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bitfld.long 0x00 4.--7. "TX_STATE_OVR_VAL,These bits take effect to enforce a certain transmission state if the TX_ST_OVR_EN bit is set" "Reset no transmission,Initialization,Clock Compensation,Idle,UFC,Run (data),Test (data),Reserved,?,?,?,?,?,?,?,Reserved"
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bitfld.long 0x00 0. "TX_STATE_OVR_EN,This read write bit allows the user to force the IP to remain in a given transmission state" "0,1"
line.long 0x04 "AURORA_TX_8B10B_OVERRIDE0,"
hexmask.long.byte 0x04 24.--31. 1. "UFC_SUF,The 8B/10B protocol defines Start of User Flow Control PDU symbol /SUF/"
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hexmask.long.byte 0x04 16.--23. 1. "I2,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence"
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hexmask.long.byte 0x04 8.--15. 1. "I1,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence"
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hexmask.long.byte 0x04 0.--7. 1. "I0,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence"
line.long 0x08 "AURORA_TX_8B10B_OVERRIDE1,"
hexmask.long.byte 0x08 24.--31. 1. "SP3,The 8B/10B protocol defines the /D10.2/ as the fourth octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
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hexmask.long.byte 0x08 16.--23. 1. "SP2,The 8B/10B protocol defines the /D10.2/ as the third octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
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hexmask.long.byte 0x08 8.--15. 1. "SP1,The 8B/10B protocol defines the /D10.2/ as the second octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
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hexmask.long.byte 0x08 0.--7. 1. "SP0,The 8B/10B protocol defines the /K28.5/ as the first octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
line.long 0x0C "AURORA_TX_8B10B_OVERRIDE2,"
hexmask.long.byte 0x0C 24.--31. 1. "V3,The 8B/10B protocol defines the /D8.7/ as the fourth octet to be used in the Verification sequence during lane initialization"
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hexmask.long.byte 0x0C 16.--23. 1. "V2,The 8B/10B protocol defines the /D8.7/ as the third octet to be used in the Verification sequence during lane initialization"
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hexmask.long.byte 0x0C 8.--15. 1. "V1,The 8B/10B protocol defines the /D8.7/ as the second octet to be used in the Verification sequence during lane inititialization"
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hexmask.long.byte 0x0C 0.--7. 1. "V0,The 8B/10B protocol defines the /K28.5/ as the first octet to be used in the Verification sequence during lane inititialization"
line.long 0x10 "AURORA_TX_8B10B_OVERRIDE3,"
hexmask.long.byte 0x10 8.--15. 1. "CC1,The 8B/10B protocol defines the /K23.7/ as the second octet to be used in the Clock Compensation sequence"
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hexmask.long.byte 0x10 0.--7. 1. "CC0,The 8B/10B protocol defines the /K23.7/ as the first octet to be used in the Clock Compensation sequence"
line.long 0x14 "AURORA_TX_64B66B_OVERRIDE1,"
hexmask.long.byte 0x14 24.--31. 1. "CB_BITS,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Idle Blocks"
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hexmask.long.byte 0x14 16.--23. 1. "CB_BTF,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks"
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hexmask.long.byte 0x14 8.--15. 1. "IDLE_BITS,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Idle Blocks"
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hexmask.long.byte 0x14 0.--7. 1. "IDLE_BTF,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks"
line.long 0x18 "AURORA_TX_64B66B_OVERRIDE2,"
hexmask.long.byte 0x18 16.--23. 1. "CC_BITS,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Channel Bonding Blocks"
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hexmask.long.byte 0x18 8.--15. 1. "CC_BTF,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks"
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hexmask.long.byte 0x18 0.--7. 1. "UFC_BTF,The 64B/66B protocol defines the value of 0x2D as the BTF for the UFC code block"
line.long 0x1C "AURORA_TX_64B66B_OVERRIDE2,"
hexmask.long.byte 0x1C 8.--15. 1. "SEP7_BTF,The 64B/66B protocol defines the value of 0xE1 as the BTF for the Separator-7"
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hexmask.long.byte 0x1C 0.--7. 1. "SEP_BTF,The 64B/66B protocol defines the value of 0x1E as the BTF for the Separator"
group.long 0x124++0x57
line.long 0x00 "AURORA_TX_INIT_CNT_LRC,"
line.long 0x04 "AURORA_TX_INIT_CNT_ALIGN,"
bitfld.long 0x04 16.--19. "ALIGN_MUL,Alignment pattern multiplier" "Alignment pattern multiplier is 32,Reserved,Reserved,Reserved,Reserved,?..."
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hexmask.long.word 0x04 0.--12. 1. "ALIGN_LEN,The number of times the Aurora alignment pattern is sent"
line.long 0x08 "AURORA_TX_INIT_CNT_BONDING,"
abitfld.long 0x08 20.--27. "rw,The 64B standard mentions that There must be at least four Idle blocks between each Channel Bonding block" "0x01=No of Idle Blocks between Channel Bonding..,0x02=No of Idle Blocks between Channel Bonding..,0xFF=No of Idle Blocks between Channel Bonding.."
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bitfld.long 0x08 16.--19. "BOND_MUL,Bond pattern multiplier" "Bond pattern multiplier is 4,Reserved,?..."
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hexmask.long.word 0x08 0.--8. 1. "BOND_LEN,The number of times the Aurora bonding pattern is sent"
line.long 0x0C "AURORA_TX_INIT_CNT_VERIFY,"
bitfld.long 0x0C 16.--19. "VERIFY_MUL,Verify pattern multiplier" "Verify pattern multiplier is 4,Reserved,?..."
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hexmask.long.word 0x0C 0.--8. 1. "VERIFY_LEN,The number of times the Aurora verification pattern is sent"
line.long 0x10 "AURORA_TX_INIT_CTRL,"
bitfld.long 0x10 2. "TX_VERIFIED,The single bit input to trigger the transition from the verification state to the channel ready state" "0,1"
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bitfld.long 0x10 1. "TX_BONDED,The single bit input to trigger the transition from the bonding to the verification state" "0,1"
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bitfld.long 0x10 0. "TX_ALIGNED,The single bit input to trigger the Stop of TestPattern Transmission" "0,1"
line.long 0x14 "AURORA_TX_IDLE_CTRL,"
bitfld.long 0x14 2.--5. "SEED,The 4-bit value used to seed the pseudo random integer used in the idle sequence generator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "AURORA_TX_IDLE_REQ,"
bitfld.long 0x18 0. "SEND_IDLE,This bit is used to trigger the insertion of the IDLE sequence by the software" "0,1"
line.long 0x1C "AURORA_TX_CC_REQ,"
bitfld.long 0x1C 1. "SEND_CC,The single bit input that can trigger a CC sequence" "0,1"
line.long 0x20 "AURORA_TX_CC_CNT,"
hexmask.long.word 0x20 0.--15. 1. "SYNC_COUNT,The 16-bit count value used to indicate the number of code group octets after which the CC sequence should be transmitted"
line.long 0x24 "AURORA_TX_CB_STATUS,"
bitfld.long 0x24 0. "CB_COMP,This bit reflects the state of the Channel Bonding FSM" "No effect,Clears the bit"
line.long 0x28 "AURORA_TX_CB_REQ,"
bitfld.long 0x28 1. "SEND_CB,The single bit input that can trigger a Channel Bonding Block" "0,1"
line.long 0x2C "AURORA_TX_CB_CNT,"
hexmask.long.word 0x2C 0.--15. 1. "CB_COUNT,The 16-bit count value used to indicate the number of data blocks after which the Channel Bonding sequence should be transmitted"
line.long 0x30 "AURORA_TX_RESET_REQ,"
bitfld.long 0x30 0. "TX_RESET,The single bit input to reset the Tx process" "0,1"
line.long 0x34 "AURORA_TX_SERIALIZER_OVERRIDE0,"
line.long 0x38 "AURORA_TX_SERIALIZER_OVERRIDE1,"
line.long 0x3C "AURORA_TX_DATA_BYTE_REVERSE,"
bitfld.long 0x3C 1. "crc_byte_reverse_en,Enable Byte reversal on the CRC value" "0,1"
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bitfld.long 0x3C 0. "byte_reverse_en,Enable Byte reversal on the input data" "0,1"
line.long 0x40 "AURORA_TX_64B66B_SCRAMBLER_INIT0,"
line.long 0x44 "AURORA_TX_64B66B_SCRAMBLER_INIT1,"
bitfld.long 0x44 31. "load,Write 0x1 to loaf the scrambler lfsr init value" "0,1"
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hexmask.long 0x44 0.--25. 1. "val,Initial value in the LFSR scrambler bits[57:32]"
line.long 0x48 "AURORA_TX_TESTPATTERN_CTRL,"
bitfld.long 0x48 0. "ramp_en,Enable a ramp patten as the testpattern" "0,1"
line.long 0x4C "AURORA_TX_CC_SEQ_CNT,"
bitfld.long 0x4C 16.--19. "count_64b66b,Configure the number of 64b66b Clock Compensation block to be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x4C 0.--3. "count_8b10b,Configure the number of 8b10b Clock Compensation octets to be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "AURORA_TX_EOP_DELAY,"
bitfld.long 0x50 16. "enable,Write 0x1 to this fiel to enable the delay configured in AURORA_TX_EOP_DEALY::DELAY" "0,1"
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hexmask.long.word 0x50 0.--15. 1. "delay,Internal Delay between the Data Framer and the Controller Block to stall data to the controller and force IDLES to be inserted by the controller after an ECP of a UDP"
line.long 0x54 "AURORA_TX_FLUSH_DELAY,"
hexmask.long.byte 0x54 0.--7. 1. "delay,Write 0x1 to this fiel to enable the delay configured in AURORA_TX_EOP_DEALY::DELAY"
rgroup.long 0x200++0x27
line.long 0x00 "AURORA_TX_STATUS,"
abitfld.long 0x00 16.--31. "DATAFRAMER,Dataframer Status fields Bit" "0x0000=OFF,0x0001=INIT DONE,0x000A=TEST MODE,0x000B=DATA MODE,0x0010=Write on Full FIFO Bit,0x0011=Read on Empty FIFO Bits [20:18],0x0064=WAITING FOR GLOBAL FLUSH DONE,0x0065=FLUSH IN PROGRESS Bits [26:21]"
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bitfld.long 0x00 0.--3. "TX_STATE,These read only bits indicate the state of the transmitter in 8B/10B and 64B/66B" "Reset no transmission,Initialization,Clock Compensation,Idle,UFC,Run (data),Test (data),Reserved,?,?,?,?,?,?,?,Reserved The user must note.."
line.long 0x04 "AURORA_TX_INIT_STATUS,"
bitfld.long 0x04 4. "TX_CH_RDY,The status bit that indicates that the channel ready state has been reached" "0,1"
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bitfld.long 0x04 3. "TX_TXCB0,The status bit that indicates that the TX_ TXCB0 state has been completed" "0,1"
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bitfld.long 0x04 2. "TX_INIT0,The status bit that indicates that the TX_INIT0 state has been completed" "0,1"
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bitfld.long 0x04 1. "TX_RESET1,The status bit that indicates that the TX_RESET1 state has been completed" "0,1"
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bitfld.long 0x04 0. "TX_RESET0,The status bit that indicates that the TX_RESET0 state has been completed" "0,1"
line.long 0x08 "AURORA_TX_CC_STATUS,"
bitfld.long 0x08 0. "CC_COMP,This bit reflects the state of the CC FSM" "No effect,Clears the bit"
line.long 0x0C "AURORA_TX_IDLE_STATUS,"
bitfld.long 0x0C 0. "IDLE_COMP,This bit reflects the state of the IDLE FSM" "No effect,Clears the bit"
line.long 0x10 "AURORA_TX_INTAGG_MASK,"
bitfld.long 0x10 15. "int15,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 14. "int14,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 13. "int13,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 12. "int12,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 11. "int11,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 10. "int10,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 9. "int9,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 8. "int8,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 7. "int7,Mask Interrupt AURORA_TX_HEADER_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 6. "int6,Mask Interrupt AURORA_TX_EOP_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 5. "int5,Mask Interrupt DATA_STOP_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 4. "int4,Mask Interrupt AURORA_TX_CC_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 3. "int3,Mask Interrupt AURORA_TX_UFC_SENT" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 2. "int2,Mask Interrupt AURORA_TX_EXT_FLUSH_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 1. "int1,Mask Interrupt AURORA_TX_FLUSH_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 0. "int0,Mask Interrupt AURORA_TX_INIT_DONE" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x14 "AURORA_TX_INTAGG_STATUS,"
bitfld.long 0x14 15. "int15,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 14. "int14,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 13. "int13,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 12. "int12,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 11. "int11,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 10. "int10,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 9. "int9,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 8. "int8,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 7. "int7,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 6. "int6,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 5. "int5,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 4. "int4,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 3. "int3,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 2. "int2,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 1. "int1,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 0. "int0,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
line.long 0x18 "AURORA_TX_INTAGG_STATUS_RAW,"
bitfld.long 0x18 15. "int15,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 14. "int14,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 13. "int13,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 12. "int12,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 11. "int11,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 10. "int10,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 9. "int9,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 8. "int8,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 7. "int7,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 6. "int6,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 5. "int5,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 4. "int4,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 3. "int3,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 2. "int2,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 1. "int1,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 0. "int0,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
line.long 0x1C "AURORA_TX_ERRAGG_MASK,"
bitfld.long 0x1C 15. "err15,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 14. "err14,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 13. "err13,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 12. "err12,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 11. "err11,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 10. "err10,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 9. "err9,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 8. "err8,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 7. "err7,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 6. "err6,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 5. "err5,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 4. "err4,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 3. "err3,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 2. "err2,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 1. "err1,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 0. "err0,Mask error AURORA_TX_UFC_ERR" "Error is Unmasked,Error is Masked"
line.long 0x20 "AURORA_TX_ERRAGG_STATUS,"
bitfld.long 0x20 15. "err15,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 14. "err14,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 13. "err13,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 12. "err12,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 11. "err11,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 10. "err10,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 9. "err9,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 8. "err8,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 7. "err7,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 6. "err6,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 5. "err5,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 4. "err4,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 3. "err3,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 2. "err2,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 1. "err1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 0. "err0,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
line.long 0x24 "AURORA_TX_ERRAGG_STATUS_RAW,"
bitfld.long 0x24 15. "err15,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 14. "err14,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 13. "err13,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 12. "err12,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 11. "err11,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 10. "err10,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 9. "err9,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 8. "err8,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 7. "err7,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 6. "err6,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 5. "err5,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 4. "err4,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 3. "err3,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 2. "err2,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 1. "err1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 0. "err0,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
rgroup.long 0x230++0x03
line.long 0x00 "AURORA_TX_TPIU_DATA_PACKED,"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x228)++0x03
line.long 0x00 "AURORA_TX_SERIALIZER_STATUS$1,"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x24)++0x03
line.long 0x00 "AURORA_TX_UDP_FRAME_HEADER$1,"
repeat.end
width 0x0B
tree.end
tree "TOP_CTRL (TOP Control Module Registers)"
base ad:0x30E0000
rgroup.long 0x00++0x0F
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MDO_CTRL,"
bitfld.long 0x04 4. "SRC_SELECT,Select the source IP of LVDS Data" "Aurora on LVDS,CBUFF on LVDS"
bitfld.long 0x04 0. "AURORATX_SRC_SELECT,Select the TPIU source to TOP_AURORATX IP" "Measurement Data,Trace Data"
line.long 0x08 "PROBE_BUS_SEL0,"
line.long 0x0C "PROBE_BUS_SEL1,"
rgroup.long 0x21C++0x0B
line.long 0x00 "EFUSE_UID3,"
hexmask.long.tbyte 0x00 0.--23. 1. "val,EFUSE UID[120:96]"
line.long 0x04 "EFUSE_DEVICE_TYPE,"
hexmask.long.word 0x04 0.--15. 1. "val,EFUSE Device Type"
line.long 0x08 "EFUSE_FROM0_CHECKSUM,"
rgroup.long 0x400++0xA7
line.long 0x00 "EFUSE0_ROW_61,"
hexmask.long 0x00 0.--25. 1. "EFUSE0_ROW_61,Captures the EFUSE Value"
line.long 0x04 "EFUSE0_ROW_62,"
hexmask.long 0x04 0.--25. 1. "EFUSE0_ROW_62,Captures the EFUSE Value"
line.long 0x08 "EFUSE0_ROW_63,"
hexmask.long 0x08 0.--25. 1. "EFUSE0_ROW_63,Captures the EFUSE Value"
line.long 0x0C "EFUSE1_ROW_5,"
hexmask.long 0x0C 0.--25. 1. "EFUSE1_ROW_5,Captures the EFUSE Value"
line.long 0x10 "EFUSE1_ROW_6,"
hexmask.long 0x10 0.--25. 1. "EFUSE1_ROW_6,Captures the EFUSE Value"
line.long 0x14 "EFUSE1_ROW_7,"
hexmask.long 0x14 0.--25. 1. "EFUSE1_ROW_7,Captures the EFUSE Value"
line.long 0x18 "EFUSE1_ROW_8,"
hexmask.long 0x18 0.--25. 1. "EFUSE1_ROW_8,Captures the EFUSE Value"
line.long 0x1C "EFUSE1_ROW_9,"
hexmask.long 0x1C 0.--25. 1. "EFUSE1_ROW_9,Captures the EFUSE Value"
line.long 0x20 "EFUSE1_ROW_10,"
hexmask.long 0x20 0.--25. 1. "EFUSE1_ROW_10,Captures the EFUSE Value"
line.long 0x24 "EFUSE1_ROW_11,"
hexmask.long 0x24 0.--25. 1. "EFUSE1_ROW_11,Captures the EFUSE Value"
line.long 0x28 "EFUSE1_ROW_12,"
hexmask.long 0x28 0.--25. 1. "EFUSE1_ROW_12,Captures the EFUSE Value"
line.long 0x2C "EFUSE1_ROW_13,"
hexmask.long 0x2C 0.--25. 1. "EFUSE1_ROW_13,Captures the EFUSE Value"
line.long 0x30 "EFUSE1_ROW_14,"
hexmask.long 0x30 0.--25. 1. "EFUSE1_ROW_14,Captures the EFUSE Value"
line.long 0x34 "EFUSE1_ROW_15,"
hexmask.long 0x34 0.--25. 1. "EFUSE1_ROW_15,Captures the EFUSE Value"
line.long 0x38 "EFUSE1_ROW_16,"
hexmask.long 0x38 0.--25. 1. "EFUSE1_ROW_16,Captures the EFUSE Value"
line.long 0x3C "EFUSE1_ROW_17,"
hexmask.long 0x3C 0.--25. 1. "EFUSE1_ROW_17,Captures the EFUSE Value"
line.long 0x40 "EFUSE1_ROW_18,"
hexmask.long 0x40 0.--25. 1. "EFUSE1_ROW_18,Captures the EFUSE Value"
line.long 0x44 "EFUSE1_ROW_19,"
hexmask.long 0x44 0.--25. 1. "EFUSE1_ROW_19,Captures the EFUSE Value"
line.long 0x48 "EFUSE1_ROW_20,"
hexmask.long 0x48 0.--25. 1. "EFUSE1_ROW_20,Captures the EFUSE Value"
line.long 0x4C "EFUSE1_ROW_21,"
hexmask.long 0x4C 0.--25. 1. "EFUSE1_ROW_21,Captures the EFUSE Value"
line.long 0x50 "EFUSE1_ROW_22,"
hexmask.long 0x50 0.--25. 1. "EFUSE1_ROW_22,Captures the EFUSE Value"
line.long 0x54 "EFUSE1_ROW_23,"
hexmask.long 0x54 0.--25. 1. "EFUSE1_ROW_23,Captures the EFUSE Value"
line.long 0x58 "EFUSE1_ROW_24,"
hexmask.long 0x58 0.--25. 1. "EFUSE1_ROW_24,Captures the EFUSE Value"
line.long 0x5C "EFUSE1_ROW_25,"
hexmask.long 0x5C 0.--25. 1. "EFUSE1_ROW_25,Captures the EFUSE Value"
line.long 0x60 "EFUSE1_ROW_26,"
hexmask.long 0x60 0.--25. 1. "EFUSE1_ROW_26,Captures the EFUSE Value"
line.long 0x64 "EFUSE1_ROW_27,"
hexmask.long 0x64 0.--25. 1. "EFUSE1_ROW_27,Captures the EFUSE Value"
line.long 0x68 "EFUSE1_ROW_28,"
hexmask.long 0x68 0.--25. 1. "EFUSE1_ROW_28,Captures the EFUSE Value"
line.long 0x6C "EFUSE1_ROW_29,"
hexmask.long 0x6C 0.--25. 1. "EFUSE1_ROW_29,Captures the EFUSE Value"
line.long 0x70 "EFUSE1_ROW_30,"
hexmask.long 0x70 0.--25. 1. "EFUSE1_ROW_30,Captures the EFUSE Value"
line.long 0x74 "EFUSE1_ROW_31,"
hexmask.long 0x74 0.--25. 1. "EFUSE1_ROW_31,Captures the EFUSE Value"
line.long 0x78 "EFUSE1_ROW_32,"
hexmask.long 0x78 0.--25. 1. "EFUSE1_ROW_32,Captures the EFUSE Value"
line.long 0x7C "EFUSE1_ROW_33,"
hexmask.long 0x7C 0.--25. 1. "EFUSE1_ROW_33,Captures the EFUSE Value"
line.long 0x80 "EFUSE1_ROW_34,"
hexmask.long 0x80 0.--25. 1. "EFUSE1_ROW_34,Captures the EFUSE Value"
line.long 0x84 "EFUSE1_ROW_35,"
hexmask.long 0x84 0.--25. 1. "EFUSE1_ROW_35,Captures the EFUSE Value"
line.long 0x88 "EFUSE1_ROW_36,"
hexmask.long 0x88 0.--25. 1. "EFUSE1_ROW_36,Captures the EFUSE Value"
line.long 0x8C "EFUSE1_ROW_37,"
hexmask.long 0x8C 0.--25. 1. "EFUSE1_ROW_37,Captures the EFUSE Value"
line.long 0x90 "EFUSE1_ROW_38,"
hexmask.long 0x90 0.--25. 1. "EFUSE1_ROW_38,Captures the EFUSE Value"
line.long 0x94 "EFUSE1_ROW_39,"
hexmask.long 0x94 0.--25. 1. "EFUSE1_ROW_39,Captures the EFUSE Value"
line.long 0x98 "EFUSE1_ROW_40,"
hexmask.long 0x98 0.--25. 1. "EFUSE1_ROW_40,Captures the EFUSE Value"
line.long 0x9C "EFUSE1_ROW_41,"
hexmask.long 0x9C 0.--25. 1. "EFUSE1_ROW_41,Captures the EFUSE Value"
line.long 0xA0 "EFUSE1_ROW_42,"
hexmask.long 0xA0 0.--25. 1. "EFUSE1_ROW_42,Captures the EFUSE Value"
line.long 0xA4 "EFUSE1_ROW_43,"
hexmask.long 0xA4 0.--25. 1. "EFUSE1_ROW_43,Captures the EFUSE Value"
group.long 0x800++0x4B
line.long 0x00 "EFUSE_OVERRIDE_HSM_HALT_ON_ROM_ECC_ERR_EN,"
bitfld.long 0x00 4. "override_val,Override MMR value" "0,1"
bitfld.long 0x00 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x04 "EFUSE_OVERRIDE_MEM_MARGINCTRL,"
bitfld.long 0x04 28.--29. "brg_margin,Override MMR value" "0,1,2,3"
bitfld.long 0x04 24.--26. "brg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
newline
bitfld.long 0x04 20.--21. "byg_margin,Override MMR value" "0,1,2,3"
bitfld.long 0x04 16.--18. "byg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
newline
bitfld.long 0x04 12.--15. "gwg_margin,Override MMR value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 8.--10. "gwg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
newline
bitfld.long 0x04 4.--5. "glg_margin,Override MMR value" "0,1,2,3"
bitfld.long 0x04 0.--2. "glg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x08 "EFUSE_OVERRIDE_LVDS_BGAP_TRIM,"
bitfld.long 0x08 4.--9. "override_val,Override MMR value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x0C "EFUSE_OVERRIDE_XTAL_STABLIZATION_WAIT,"
bitfld.long 0x0C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x10 "EFUSE_OVERRIDE_SLICER_BIAS_RTRIM,"
bitfld.long 0x10 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x14 "EFUSE_OVERRIDE_XO_OUTPUT_DRIVE,"
bitfld.long 0x14 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x18 "EFUSE_OVERRIDE_RCOSC_TRIM_CODE,"
bitfld.long 0x18 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x1C "EFUSE_OVERRIDE_IP1_BG1_RTRIM,"
bitfld.long 0x1C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x20 "EFUSE_OVERRIDE_IP1_BG1_SLOPE,"
bitfld.long 0x20 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x24 "EFUSE_OVERRIDE_IP1_BG1_MAG,"
bitfld.long 0x24 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x28 "EFUSE_OVERRIDE_RS232_CLKMODE,"
bitfld.long 0x28 4. "override_val,Override value for RS232 Clock Mode" "Autobaud,Fixed Interval"
bitfld.long 0x28 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x2C "EFUSE_OVERRIDE_VMON_VDD_OV_UV_TRIM,"
bitfld.long 0x2C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x30 "EFUSE_OVERRIDE_VMON_VDDS_3P3_UV_TRIM,"
bitfld.long 0x30 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x34 "EFUSE_OVERRIDE_VMON_VDDA_OSC_TRIM,"
bitfld.long 0x34 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x38 "EFUSE_OVERRIDE_VDD_VT_DET,"
bitfld.long 0x38 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x3C "EFUSE_OVERRIDE_MASK_CPU_CLK_OUT_CTRL_LOWV_VAL,"
bitfld.long 0x3C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x40 "EFUSE_OVERRIDE_MASK_CPU_CLK_OUT_CTRL_LOWV_SEL,"
bitfld.long 0x40 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x44 "EFUSE_OVERRIDE_EN_VOL_MON_FUNC,"
bitfld.long 0x44 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x48 "EFUSE_OVERRIDE_BYPASS_HOLDBUFFER_ENABLE,"
bitfld.long 0x48 4. "override_val,Override value for Hold Buffer Enable" "Disabled,Enabled"
bitfld.long 0x48 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
rgroup.long ($2+0x228)++0x03
line.long 0x00 "EFUSE_ROM_SEQ_UPDATE$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x210)++0x03
line.long 0x00 "EFUSE_UID$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x200)++0x03
line.long 0x00 "EFUSE_DIEID$1,"
repeat.end
width 0x0B
tree.end
tree "TOP_MDO_INFRA (TOP MDO INFRA Module Registers)"
base ad:0x3080000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x14F
line.long 0x00 "SRC0_CTRL,"
bitfld.long 0x00 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x00 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x00 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x00 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x00 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x04 "SRC0_RANGE_START0,"
line.long 0x08 "SRC0_RANGE_END0,"
line.long 0x0C "SRC0_RANGE_START1,"
line.long 0x10 "SRC0_RANGE_END1,"
line.long 0x14 "SRC0_RANGE_START2,"
line.long 0x18 "SRC0_RANGE_END2,"
line.long 0x1C "SRC0_RANGE_START3,"
line.long 0x20 "SRC0_RANGE_END3,"
line.long 0x24 "SRC0_SW_TRIGGER,"
bitfld.long 0x24 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x24 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x28 "SRC0_THRESHOLD,"
hexmask.long.word 0x28 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x2C "SRC0_BW_CTRL,"
bitfld.long 0x2C 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x2C 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x2C 0. "write_mode," "0,1"
line.long 0x30 "SRC0_CHANNEL,"
line.long 0x34 "SRC0_CHANNEL_CFG,"
bitfld.long 0x34 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x34 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x34 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x34 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x34 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0x38 "SRC1_CTRL,"
bitfld.long 0x38 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x38 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x38 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x38 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x38 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x38 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x38 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x3C "SRC1_RANGE_START0,"
line.long 0x40 "SRC1_RANGE_END0,"
line.long 0x44 "SRC1_RANGE_START1,"
line.long 0x48 "SRC1_RANGE_END1,"
line.long 0x4C "SRC1_RANGE_START2,"
line.long 0x50 "SRC1_RANGE_END2,"
line.long 0x54 "SRC1_RANGE_START3,"
line.long 0x58 "SRC1_RANGE_END3,"
line.long 0x5C "SRC1_SW_TRIGGER,"
bitfld.long 0x5C 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x5C 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x60 "SRC1_THRESHOLD,"
hexmask.long.word 0x60 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x64 "SRC1_BW_CTRL,"
bitfld.long 0x64 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x64 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x64 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x64 0. "write_mode," "0,1"
line.long 0x68 "SRC1_CHANNEL,"
line.long 0x6C "SRC1_CHANNEL_CFG,"
bitfld.long 0x6C 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x6C 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x6C 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x6C 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x6C 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0x70 "SRC2_CTRL,"
bitfld.long 0x70 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x70 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x70 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x70 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x70 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x70 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x70 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x74 "SRC2_RANGE_START0,"
line.long 0x78 "SRC2_RANGE_END0,"
line.long 0x7C "SRC2_RANGE_START1,"
line.long 0x80 "SRC2_RANGE_END1,"
line.long 0x84 "SRC2_RANGE_START2,"
line.long 0x88 "SRC2_RANGE_END2,"
line.long 0x8C "SRC2_RANGE_START3,"
line.long 0x90 "SRC2_RANGE_END3,"
line.long 0x94 "SRC2_SW_TRIGGER,"
bitfld.long 0x94 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x94 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x98 "SRC2_THRESHOLD,"
hexmask.long.word 0x98 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x9C "SRC2_BW_CTRL,"
bitfld.long 0x9C 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x9C 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x9C 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x9C 0. "write_mode," "0,1"
line.long 0xA0 "SRC2_CHANNEL,"
line.long 0xA4 "SRC2_CHANNEL_CFG,"
bitfld.long 0xA4 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xA4 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0xA4 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xA4 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0xA4 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0xA8 "SRC3_CTRL,"
bitfld.long 0xA8 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0xA8 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0xA8 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xA8 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0xA8 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0xA8 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0xA8 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0xAC "SRC3_RANGE_START0,"
line.long 0xB0 "SRC3_RANGE_END0,"
line.long 0xB4 "SRC3_RANGE_START1,"
line.long 0xB8 "SRC3_RANGE_END1,"
line.long 0xBC "SRC3_RANGE_START2,"
line.long 0xC0 "SRC3_RANGE_END2,"
line.long 0xC4 "SRC3_RANGE_START3,"
line.long 0xC8 "SRC3_RANGE_END3,"
line.long 0xCC "SRC3_SW_TRIGGER,"
bitfld.long 0xCC 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0xCC 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0xD0 "SRC3_THRESHOLD,"
hexmask.long.word 0xD0 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0xD4 "SRC3_BW_CTRL,"
bitfld.long 0xD4 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0xD4 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0xD4 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0xD4 0. "write_mode," "0,1"
line.long 0xD8 "SRC3_CHANNEL,"
line.long 0xDC "SRC3_CHANNEL_CFG,"
bitfld.long 0xDC 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xDC 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0xDC 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xDC 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0xDC 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0xE0 "SRC4_CTRL,"
bitfld.long 0xE0 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0xE0 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0xE0 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xE0 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0xE0 4. "port_sel,Select which bus to capture" "DSS_HWA_DMA0,DSS_HWA_DMA1"
bitfld.long 0xE0 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
newline
bitfld.long 0xE0 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
bitfld.long 0xE0 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0xE4 "SRC4_RANGE_START0,"
line.long 0xE8 "SRC4_RANGE_END0,"
line.long 0xEC "SRC4_RANGE_START1,"
line.long 0xF0 "SRC4_RANGE_END1,"
line.long 0xF4 "SRC4_RANGE_START2,"
line.long 0xF8 "SRC4_RANGE_END2,"
line.long 0xFC "SRC4_RANGE_START3,"
line.long 0x100 "SRC4_RANGE_END3,"
line.long 0x104 "SRC4_SW_TRIGGER,"
bitfld.long 0x104 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x104 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x108 "SRC4_THRESHOLD,"
hexmask.long.word 0x108 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x10C "SRC4_BW_CTRL,"
bitfld.long 0x10C 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x10C 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x10C 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x10C 0. "write_mode," "0,1"
line.long 0x110 "SRC4_CHANNEL,"
line.long 0x114 "SRC4_CHANNEL_CFG,"
bitfld.long 0x114 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x114 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x114 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x114 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x114 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0x118 "SRC5_CTRL,"
bitfld.long 0x118 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x118 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x118 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x118 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x118 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x118 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x118 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x11C "SRC5_RANGE_START0,"
line.long 0x120 "SRC5_RANGE_END0,"
line.long 0x124 "SRC5_RANGE_START1,"
line.long 0x128 "SRC5_RANGE_END1,"
line.long 0x12C "SRC5_RANGE_START2,"
line.long 0x130 "SRC5_RANGE_END2,"
line.long 0x134 "SRC5_RANGE_START3,"
line.long 0x138 "SRC5_RANGE_END3,"
line.long 0x13C "SRC5_SW_TRIGGER,"
bitfld.long 0x13C 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x13C 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x140 "SRC5_THRESHOLD,"
hexmask.long.word 0x140 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x144 "SRC5_BW_CTRL,"
bitfld.long 0x144 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x144 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x144 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x144 0. "write_mode," "0,1"
line.long 0x148 "SRC5_CHANNEL,"
line.long 0x14C "SRC5_CHANNEL_CFG,"
bitfld.long 0x14C 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x14C 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x14C 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x14C 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x14C 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
group.long 0x1D4++0x1B
line.long 0x00 "SRC0_STATUS,"
hexmask.long.word 0x00 16.--31. 1. "status,Status of the Sniffer for Source 0"
bitfld.long 0x00 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x00 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x00 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x00 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x04 "SRC1_STATUS,"
hexmask.long.word 0x04 16.--31. 1. "status,Status of the Sniffer for Source 1"
bitfld.long 0x04 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x04 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x04 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x04 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x08 "SRC2_STATUS,"
hexmask.long.word 0x08 16.--31. 1. "status,Status of the Sniffer for Source 2"
bitfld.long 0x08 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x08 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x08 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x08 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x0C "SRC3_STATUS,"
hexmask.long.word 0x0C 16.--31. 1. "status,Status of the Sniffer for Source 3"
bitfld.long 0x0C 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x0C 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x0C 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x0C 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x10 "SRC4_STATUS,"
hexmask.long.word 0x10 16.--31. 1. "status,Status of the Sniffer for Source 4"
bitfld.long 0x10 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x10 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x10 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x10 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x14 "SRC5_STATUS,"
hexmask.long.word 0x14 16.--31. 1. "status,Status of the Sniffer for Source 5"
bitfld.long 0x14 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x14 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x14 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x14 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x18 "INTERRUPT_MASK,"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "proxy_err,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "addr_err,Addressing violation error" "0,1"
bitfld.long 0x08 0. "prot_err,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "enabled_proxy_err,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "enabled_kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "enabled_addr_err,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "fault_ns,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "fault_type,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "fault_xid,XID"
hexmask.long.word 0x24 8.--19. 1. "fault_routeid,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "fault_privid,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "fault_clr,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "TOP_PBIST (TOP PBIST Module Registers)"
base ad:0x2F79400
hgroup.long 0x120++0x07
hide.long 0x00 "PBIST_DD10,DD0 Data Register 16 (D0)"
hide.long 0x04 "PBIST_DE10,DE0 Data Register 16 (D0)"
group.long 0x160++0x03
line.long 0x00 "PBIST_RAMT,RAM Configuration (RAMT -RAM)"
hexmask.long.byte 0x00 24.--31. 1. "RGS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 16.--23. 1. "RDS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 8.--15. 1. "DWR,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 0.--7. 1. "RAM,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
group.word 0x164++0x01
line.word 0x00 "PBIST_DLR,Datalogger 0"
hexmask.word.byte 0x00 8.--15. 1. "DLR1,Datalogger Register [8] : Reserevd [9] : Default Testing Mode"
hexmask.word.byte 0x00 0.--7. 1. "DLR0,Datalogger Register [1:0] : Reserved [2] : ROM-based testing mode"
group.byte 0x168++0x00
line.byte 0x00 "PBIST_CMS,Clock mux select"
bitfld.byte 0x00 0.--3. "PBIST_CMS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x16C++0x00
line.byte 0x00 "PBIST_PC,Program Control"
bitfld.byte 0x00 0.--4. "PBIST_PC,TI Internal Register.Reserved for HW RnD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x178++0x03
line.long 0x00 "PBIST_CS,Chip Select 0"
hexmask.long.byte 0x00 24.--31. 1. "CS3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "CS2,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 8.--15. 1. "CS1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "CS0,TI Internal Register.Reserved for HW RnD"
group.byte 0x17C++0x00
line.byte 0x00 "PBIST_FDLY,Fail Delay"
group.byte 0x180++0x00
line.byte 0x00 "PBIST_PACT,Pbist Active"
bitfld.byte 0x00 0. "PBIST_PACT,Pbist Active/ROM Clock Enable Register [0]: This bit must be set to turn on internal PBIST clocks" "Disable internal PBIST clocks Value,Enable internal PBIST clocks"
group.byte 0x184++0x00
line.byte 0x00 "PBIST_ID,PBIST ID"
bitfld.byte 0x00 0.--4. "PBIST_ID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hgroup.long 0x188++0x03
hide.long 0x00 "PBIST_OVR,PBIST Overrides"
rgroup.byte 0x190++0x00
line.byte 0x00 "PBIST_FSFR0,Fail status fail - port 0"
bitfld.byte 0x00 0. "PBIST_FSFR0,Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x194++0x00
line.byte 0x00 "PBIST_FSFR1,Fail status fail - port 1"
bitfld.byte 0x00 0. "PBIST_FSFR1,Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x198++0x00
line.byte 0x00 "PBIST_FSRCR0,Fail Count fail - port 0"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR0,Fail Status Count - Port 0 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x19C++0x00
line.byte 0x00 "PBIST_FSRCR1,Fail Count fail - port 1"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR1,Fail Status Count - Port 1 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1A0++0x03
hide.long 0x00 "PBIST_FSRA0,Fail status address - port 0"
rgroup.word 0x1A4++0x01
line.word 0x00 "PBIST_FSRA1,Fail status address - port 1"
hgroup.long 0x1B4++0x0B
hide.long 0x00 "PBIST_MARGIN,Margin Mode"
hide.long 0x04 "PBIST_WRENZ,WRENZ"
hide.long 0x08 "PBIST_PGS,PAGE/PGS"
group.byte 0x1C0++0x00
line.byte 0x00 "PBIST_ROM,Rom Mask"
bitfld.byte 0x00 0.--1. "PBIST_ROM,Rom Mask" "No information is used from ROM Value,Only RAM Group information from ROM Vaule,Only Algorithm information from ROM Value,Both Algorithm and RAM information from ROM"
group.long 0x1C4++0x0B
line.long 0x00 "PBIST_ALGO,ROM Algorithm Mask 0"
hexmask.long.byte 0x00 24.--31. 1. "ALGO3,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 16.--23. 1. "ALGO2,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 8.--15. 1. "ALGO1,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 0.--7. 1. "ALGO0,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
line.long 0x04 "PBIST_RINFOL,RAM Info Mask Lower 0"
hexmask.long.byte 0x04 24.--31. 1. "RINFOL3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 16.--23. 1. "RINFOL2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 8.--15. 1. "RINFOL1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 0.--7. 1. "RINFOL0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
line.long 0x08 "PBIST_RINFOU,RAM Info Mask Upper 0"
hexmask.long.byte 0x08 24.--31. 1. "RINFOU3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 16.--23. 1. "RINFOU2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 8.--15. 1. "RINFOU1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 0.--7. 1. "RINFOU0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
repeat 2. (list 0. 1. )(list 0x00 0x08 )
rgroup.long ($2+0x1A8)++0x03
line.long 0x00 "PBIST_FSRDL$1,Fail status Data - port 0"
repeat.end
repeat 2. (list 1. 4. )(list 0x00 0x04 )
group.long ($2+0x170)++0x03
line.long 0x00 "PBIST_SCR$1,Address Scramble 0 -3"
hexmask.long.byte 0x00 24.--31. 1. "SCR3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "SCR2,TI Internal Register.Reserved for HW RnD"
newline
hexmask.long.byte 0x00 8.--15. 1. "SCR1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "SCR0,TI Internal Register.Reserved for HW RnD"
repeat.end
repeat 2. (list 2. 3. )(list 0x00 0x04 )
group.word ($2+0x158)++0x01
line.word 0x00 "PBIST_CI$1,Constant Increment Register2"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
hgroup.long ($2+0x150)++0x03
hide.long 0x00 "PBIST_CI$1,Constant Increment Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x140)++0x03
hide.long 0x00 "PBIST_CL$1,Constant Loop Count Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x130)++0x03
hide.long 0x00 "PBIST_CA$1,Constant Address Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x110)++0x03
hide.long 0x00 "PBIST_L$1,Variable Loop Count Register L0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x100)++0x03
hide.long 0x00 "PBIST_A$1,Variable Address Register0"
repeat.end
width 0x0B
tree.end
endif
sif (cpuis("AM2732DSP"))
tree "DSS_CBUFF (DSS CBUFF Module Registers)"
base ad:0x6040000
group.long 0x00++0x1B
line.long 0x00 "CONFIG_REG_0,Basic Config register"
bitfld.long 0x00 28.--31. "dbussel,TI Internal feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 27. "cswcrst,CBUFF controller SW Reset" "RELEASE RESET for CBUFF Controller,RESET the CBUFF Controller"
newline
bitfld.long 0x00 26. "cswlrst,TI Internal Feature" "RELEASE RESET,RESET the FSM"
newline
bitfld.long 0x00 25. "CFG_FRAME_START_TRIG,SW Trigger generation : Write 1 to this bit to generate a Frame Start SW Trigger" "0,1"
newline
bitfld.long 0x00 24. "CFG_CHIRP_AVAIL_TRIG,SW Trigger generation : Write 1 to this bit to generate a Chirp Available SW Trigger" "0,1"
newline
bitfld.long 0x00 20.--23. "CFG_VBUSP_BURST_EN,TI Internal Feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "dbusen,TC2 Mode selection" "Normal,When in TC2 mode.."
newline
bitfld.long 0x00 18. "ccfwpen,TI Internal Feature" "Use the fifo_free_words directly from CSI2 by..,Process the fifo_free_words and use it by.."
newline
bitfld.long 0x00 16.--17. "cvc3en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 3 is..,A VSYNC End packet on Virtual Channel 3 is..,A VSYNC Start packet on Virtual Channel 3 is.."
newline
bitfld.long 0x00 14.--15. "cvc2en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 2 is..,A VSYNC End packet on Virtual Channel 2 is..,A VSYNC Start packet on Virtual Channel 2 is.."
newline
bitfld.long 0x00 12.--13. "cvc1en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 1 is..,A VSYNC End packet on Virtual Channel 1 is..,A VSYNC Start packet on Virtual Channel 1 is.."
newline
bitfld.long 0x00 10.--11. "cvc0en,CSI2 only Programming" "No Vsync packet is sent at Frame boundary,A VSYNC Start packet on Virtual Channel 0 is..,A VSYNC End packet on Virtual Channel 0 is..,A VSYNC Start packet on Virtual Channel 0 is.."
newline
bitfld.long 0x00 9. "crdthsel,TI Internal Feature" "The read threshold is selected based on the..,The read threshold is selected based on the Read.."
newline
bitfld.long 0x00 8. "ccfwlen,TI Internal Feature" "0,1"
newline
rbitfld.long 0x00 4.--7. "NU1," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "CFG_SW_TRIG_EN,Select Chirp Available Trigger Source" "Chirp Available trigger will be generated by HW,Chirp Available trigger will be generated by SW"
newline
bitfld.long 0x00 2. "cftrigen,Select Frame Start Trigger Source" "Frame trigger will be generated by HW,Frame trigger will be generated by SW"
newline
bitfld.long 0x00 1. "CFG_ECC_EN," "0,1"
newline
bitfld.long 0x00 0. "CFG_1LVDS_0CSI," "0,1"
line.long 0x04 "CFG_SPHDR_ADDRESS,Short Packet Header Address"
line.long 0x08 "CFG_CMD_HSVAL,HSYNC Value"
line.long 0x0C "CFG_CMD_HEVAL,HEND Value"
line.long 0x10 "CFG_CMD_VSVAL,VSYNC Value"
line.long 0x14 "CFG_CMD_VEVAL,VEND Value"
line.long 0x18 "CFG_LPHDR_ADDRESS,Long Packet Address"
group.long 0x20++0x1D3
line.long 0x00 "CFG_CHIRPS_PER_FRAME,Number of Chirps per Frame"
line.long 0x04 "CFG_FIFO_FREE_THRESHOLD,CSI2 FIFO threshold for transferring data from CBUFF to CSI2"
hexmask.long.byte 0x04 24.--31. 1. "CFG_FIFO_FREE_THRESHOLD3,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO3 in the CSI Protocol engine"
newline
hexmask.long.byte 0x04 16.--23. 1. "CFG_FIFO_FREE_THRESHOLD2,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO2 in the CSI Protocol engine"
newline
hexmask.long.byte 0x04 8.--15. 1. "CFG_FIFO_FREE_THRESHOLD1,TI Internal Feature CSI2 only Programming : Configure the threshold used to fill the FIFO1 in the CSI Protocol engine"
newline
hexmask.long.byte 0x04 0.--7. 1. "CFG_FIFO_FREE_THRESHOLD0,CSI2 only Programming : Configure the threshold used to fill the FIFO0 in the CSI Protocol engine"
line.long 0x08 "CFG_LPPYLD_ADDRESS,Long payload Address"
line.long 0x0C "CFG_DELAY_CONFIG,Delay Config Registers"
hexmask.long.byte 0x0C 24.--31. 1. "NU,"
newline
hexmask.long.byte 0x0C 16.--23. 1. "CFG_DATA_WR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Long packet Payload"
newline
hexmask.long.byte 0x0C 8.--15. 1. "CFG_LPHDR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Long packet Header"
newline
hexmask.long.byte 0x0C 0.--7. 1. "CFG_SPHDR_DELAY,TI Internal Feature CSI2 only Programming : Configure an additional delay after sending a Short packet"
line.long 0x10 "CFG_DATA_LL0,Payload Description : Linked list entry 0"
bitfld.long 0x10 31. "LL0_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10 30. "LL0_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10 29. "LL0_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10 28. "LL0_CRC_EN," "0,1"
newline
bitfld.long 0x10 27. "LL0_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x10 26. "LL0_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x10 23.--25. "LL0_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 9.--22. 1. "LL0_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x10 8. "LL0_FMT_IN," "0,1"
newline
bitfld.long 0x10 7. "LL0_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x10 5.--6. "LL0_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x10 3.--4. "LL0_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x10 2. "LL0_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x10 1. "LL0_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x10 0. "LL0_VALID," "0,1"
line.long 0x14 "CFG_DATA_LL0_LPHDR_VAL,Payload Description : Linked list entry 0"
line.long 0x18 "CFG_DATA_LL0_THRESHOLD,"
hexmask.long.word 0x18 19.--31. 1. "NU3,"
newline
bitfld.long 0x18 16.--18. "ll0dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x18 15. "NU2," "0,1"
newline
hexmask.long.byte 0x18 8.--14. 1. "LL0_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x18 7. "NU1," "0,1"
newline
hexmask.long.byte 0x18 0.--6. 1. "LL0_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x1C "CFG_DATA_LL1,"
bitfld.long 0x1C 31. "LL1_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x1C 30. "LL1_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x1C 29. "LL1_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x1C 28. "LL1_CRC_EN," "0,1"
newline
bitfld.long 0x1C 27. "LL1_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x1C 26. "LL1_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x1C 23.--25. "LL1_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 9.--22. 1. "LL1_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x1C 8. "LL1_FMT_IN," "0,1"
newline
bitfld.long 0x1C 7. "LL1_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x1C 5.--6. "LL1_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x1C 3.--4. "LL1_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x1C 2. "LL1_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x1C 1. "LL1_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x1C 0. "LL1_VALID," "0,1"
line.long 0x20 "CFG_DATA_LL1_LPHDR_VAL,"
line.long 0x24 "CFG_DATA_LL1_THRESHOLD,"
hexmask.long.word 0x24 19.--31. 1. "NU3,"
newline
bitfld.long 0x24 16.--18. "ll1dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x24 15. "NU2," "0,1"
newline
hexmask.long.byte 0x24 8.--14. 1. "LL1_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x24 7. "NU1," "0,1"
newline
hexmask.long.byte 0x24 0.--6. 1. "LL1_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x28 "CFG_DATA_LL2,"
bitfld.long 0x28 31. "LL2_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x28 30. "LL2_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x28 29. "LL2_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x28 28. "LL2_CRC_EN," "0,1"
newline
bitfld.long 0x28 27. "LL2_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x28 26. "LL2_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x28 23.--25. "LL2_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 9.--22. 1. "LL2_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x28 8. "LL2_FMT_IN," "0,1"
newline
bitfld.long 0x28 7. "LL2_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x28 5.--6. "LL2_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x28 3.--4. "LL2_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x28 2. "LL2_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x28 1. "LL2_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x28 0. "LL2_VALID," "0,1"
line.long 0x2C "CFG_DATA_LL2_LPHDR_VAL,"
line.long 0x30 "CFG_DATA_LL2_THRESHOLD,"
hexmask.long.word 0x30 19.--31. 1. "NU3,"
newline
bitfld.long 0x30 16.--18. "ll2dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x30 15. "NU2," "0,1"
newline
hexmask.long.byte 0x30 8.--14. 1. "LL2_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x30 7. "NU1," "0,1"
newline
hexmask.long.byte 0x30 0.--6. 1. "LL2_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x34 "CFG_DATA_LL3,"
bitfld.long 0x34 31. "LL3_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x34 30. "LL3_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x34 29. "LL3_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x34 28. "LL3_CRC_EN," "0,1"
newline
bitfld.long 0x34 27. "LL3_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x34 26. "LL3_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x34 23.--25. "LL3_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 9.--22. 1. "LL3_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x34 8. "LL3_FMT_IN," "0,1"
newline
bitfld.long 0x34 7. "LL3_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x34 5.--6. "LL3_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x34 3.--4. "LL3_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x34 2. "LL3_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x34 1. "LL3_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x34 0. "LL3_VALID," "0,1"
line.long 0x38 "CFG_DATA_LL3_LPHDR_VAL,"
line.long 0x3C "CFG_DATA_LL3_THRESHOLD,"
hexmask.long.word 0x3C 19.--31. 1. "NU3,"
newline
bitfld.long 0x3C 16.--18. "ll3dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x3C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x3C 8.--14. 1. "LL3_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x3C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x3C 0.--6. 1. "LL3_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x40 "CFG_DATA_LL4,"
bitfld.long 0x40 31. "LL4_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x40 30. "LL4_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x40 29. "LL4_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x40 28. "LL4_CRC_EN," "0,1"
newline
bitfld.long 0x40 27. "LL4_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x40 26. "LL4_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x40 23.--25. "LL4_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x40 9.--22. 1. "LL4_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x40 8. "LL4_FMT_IN," "0,1"
newline
bitfld.long 0x40 7. "LL4_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x40 5.--6. "LL4_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x40 3.--4. "LL4_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x40 2. "LL4_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x40 1. "LL4_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x40 0. "LL4_VALID," "0,1"
line.long 0x44 "CFG_DATA_LL4_LPHDR_VAL,"
line.long 0x48 "CFG_DATA_LL4_THRESHOLD,"
hexmask.long.word 0x48 19.--31. 1. "NU3,"
newline
bitfld.long 0x48 16.--18. "ll4dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x48 15. "NU2," "0,1"
newline
hexmask.long.byte 0x48 8.--14. 1. "LL4_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x48 7. "NU1," "0,1"
newline
hexmask.long.byte 0x48 0.--6. 1. "LL4_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x4C "CFG_DATA_LL5,"
bitfld.long 0x4C 31. "LL5_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x4C 30. "LL5_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x4C 29. "LL5_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x4C 28. "LL5_CRC_EN," "0,1"
newline
bitfld.long 0x4C 27. "LL5_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x4C 26. "LL5_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x4C 23.--25. "LL5_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x4C 9.--22. 1. "LL5_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x4C 8. "LL5_FMT_IN," "0,1"
newline
bitfld.long 0x4C 7. "LL5_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x4C 5.--6. "LL5_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x4C 3.--4. "LL5_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x4C 2. "LL5_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x4C 1. "LL5_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x4C 0. "LL5_VALID," "0,1"
line.long 0x50 "CFG_DATA_LL5_LPHDR_VAL,"
line.long 0x54 "CFG_DATA_LL5_THRESHOLD,"
hexmask.long.word 0x54 19.--31. 1. "NU3,"
newline
bitfld.long 0x54 16.--18. "ll5dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x54 15. "NU2," "0,1"
newline
hexmask.long.byte 0x54 8.--14. 1. "LL5_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x54 7. "NU1," "0,1"
newline
hexmask.long.byte 0x54 0.--6. 1. "LL5_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x58 "CFG_DATA_LL6,"
bitfld.long 0x58 31. "LL6_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x58 30. "LL6_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x58 29. "LL6_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x58 28. "LL6_CRC_EN," "0,1"
newline
bitfld.long 0x58 27. "LL6_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x58 26. "LL6_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x58 23.--25. "LL6_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x58 9.--22. 1. "LL6_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x58 8. "LL6_FMT_IN," "0,1"
newline
bitfld.long 0x58 7. "LL6_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x58 5.--6. "LL6_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x58 3.--4. "LL6_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x58 2. "LL6_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x58 1. "LL6_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x58 0. "LL6_VALID," "0,1"
line.long 0x5C "CFG_DATA_LL6_LPHDR_VAL,"
line.long 0x60 "CFG_DATA_LL6_THRESHOLD,"
hexmask.long.word 0x60 19.--31. 1. "NU3,"
newline
bitfld.long 0x60 16.--18. "ll6dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x60 15. "NU2," "0,1"
newline
hexmask.long.byte 0x60 8.--14. 1. "LL6_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x60 7. "NU1," "0,1"
newline
hexmask.long.byte 0x60 0.--6. 1. "LL6_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x64 "CFG_DATA_LL7,"
bitfld.long 0x64 31. "LL7_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x64 30. "LL7_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x64 29. "LL7_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x64 28. "LL7_CRC_EN," "0,1"
newline
bitfld.long 0x64 27. "LL7_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x64 26. "LL7_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x64 23.--25. "LL7_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x64 9.--22. 1. "LL7_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x64 8. "LL7_FMT_IN," "0,1"
newline
bitfld.long 0x64 7. "LL7_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x64 5.--6. "LL7_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x64 3.--4. "LL7_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x64 2. "LL7_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x64 1. "LL7_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x64 0. "LL7_VALID," "0,1"
line.long 0x68 "CFG_DATA_LL7_LPHDR_VAL,"
line.long 0x6C "CFG_DATA_LL7_THRESHOLD,"
hexmask.long.word 0x6C 19.--31. 1. "NU3,"
newline
bitfld.long 0x6C 16.--18. "ll7dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x6C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x6C 8.--14. 1. "LL7_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x6C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x6C 0.--6. 1. "LL7_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x70 "CFG_DATA_LL8,"
bitfld.long 0x70 31. "LL8_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x70 30. "LL8_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x70 29. "LL8_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x70 28. "LL8_CRC_EN," "0,1"
newline
bitfld.long 0x70 27. "LL8_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x70 26. "LL8_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x70 23.--25. "LL8_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x70 9.--22. 1. "LL8_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x70 8. "LL8_FMT_IN," "0,1"
newline
bitfld.long 0x70 7. "LL8_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x70 5.--6. "LL8_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x70 3.--4. "LL8_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x70 2. "LL8_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x70 1. "LL8_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x70 0. "LL8_VALID," "0,1"
line.long 0x74 "CFG_DATA_LL8_LPHDR_VAL,"
line.long 0x78 "CFG_DATA_LL8_THRESHOLD,"
hexmask.long.word 0x78 19.--31. 1. "NU3,"
newline
bitfld.long 0x78 16.--18. "ll8dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x78 15. "NU2," "0,1"
newline
hexmask.long.byte 0x78 8.--14. 1. "LL8_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x78 7. "NU1," "0,1"
newline
hexmask.long.byte 0x78 0.--6. 1. "LL8_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x7C "CFG_DATA_LL9,"
bitfld.long 0x7C 31. "LL9_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x7C 30. "LL9_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x7C 29. "LL9_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x7C 28. "LL9_CRC_EN," "0,1"
newline
bitfld.long 0x7C 27. "LL9_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x7C 26. "LL9_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x7C 23.--25. "LL9_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x7C 9.--22. 1. "LL9_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x7C 8. "LL9_FMT_IN," "0,1"
newline
bitfld.long 0x7C 7. "LL9_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x7C 5.--6. "LL9_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x7C 3.--4. "LL9_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x7C 2. "LL9_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x7C 1. "LL9_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x7C 0. "LL9_VALID," "0,1"
line.long 0x80 "CFG_DATA_LL9_LPHDR_VAL,"
line.long 0x84 "CFG_DATA_LL9_THRESHOLD,"
hexmask.long.word 0x84 19.--31. 1. "NU3,"
newline
bitfld.long 0x84 16.--18. "ll9dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x84 15. "NU2," "0,1"
newline
hexmask.long.byte 0x84 8.--14. 1. "LL9_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x84 7. "NU1," "0,1"
newline
hexmask.long.byte 0x84 0.--6. 1. "LL9_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x88 "CFG_DATA_LL10,"
bitfld.long 0x88 31. "LL10_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x88 30. "LL10_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x88 29. "LL10_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x88 28. "LL10_CRC_EN," "0,1"
newline
bitfld.long 0x88 27. "LL10_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x88 26. "LL10_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x88 23.--25. "LL10_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x88 9.--22. 1. "LL10_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x88 8. "LL10_FMT_IN," "0,1"
newline
bitfld.long 0x88 7. "LL10_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x88 5.--6. "LL10_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x88 3.--4. "LL10_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x88 2. "LL10_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x88 1. "LL10_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x88 0. "LL10_VALID," "0,1"
line.long 0x8C "CFG_DATA_LL10_LPHDR_VAL,"
line.long 0x90 "CFG_DATA_LL10_THRESHOLD,"
hexmask.long.word 0x90 19.--31. 1. "NU3,"
newline
bitfld.long 0x90 16.--18. "ll10dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x90 15. "NU2," "0,1"
newline
hexmask.long.byte 0x90 8.--14. 1. "LL10_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x90 7. "NU1," "0,1"
newline
hexmask.long.byte 0x90 0.--6. 1. "LL10_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x94 "CFG_DATA_LL11,"
bitfld.long 0x94 31. "LL11_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x94 30. "LL11_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
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bitfld.long 0x94 29. "LL11_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x94 28. "LL11_CRC_EN," "0,1"
newline
bitfld.long 0x94 27. "LL11_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x94 26. "LL11_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x94 23.--25. "LL11_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x94 9.--22. 1. "LL11_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x94 8. "LL11_FMT_IN," "0,1"
newline
bitfld.long 0x94 7. "LL11_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x94 5.--6. "LL11_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x94 3.--4. "LL11_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x94 2. "LL11_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x94 1. "LL11_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
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bitfld.long 0x94 0. "LL11_VALID," "0,1"
line.long 0x98 "CFG_DATA_LL11_LPHDR_VAL,"
line.long 0x9C "CFG_DATA_LL11_THRESHOLD,"
hexmask.long.word 0x9C 19.--31. 1. "NU3,"
newline
bitfld.long 0x9C 16.--18. "ll11dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x9C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x9C 8.--14. 1. "LL11_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x9C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x9C 0.--6. 1. "LL11_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xA0 "CFG_DATA_LL12,"
bitfld.long 0xA0 31. "LL12_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xA0 30. "LL12_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xA0 29. "LL12_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xA0 28. "LL12_CRC_EN," "0,1"
newline
bitfld.long 0xA0 27. "LL12_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xA0 26. "LL12_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xA0 23.--25. "LL12_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xA0 9.--22. 1. "LL12_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xA0 8. "LL12_FMT_IN," "0,1"
newline
bitfld.long 0xA0 7. "LL12_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xA0 5.--6. "LL12_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xA0 3.--4. "LL12_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xA0 2. "LL12_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xA0 1. "LL12_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xA0 0. "LL12_VALID," "0,1"
line.long 0xA4 "CFG_DATA_LL12_LPHDR_VAL,"
line.long 0xA8 "CFG_DATA_LL12_THRESHOLD,"
hexmask.long.word 0xA8 19.--31. 1. "NU3,"
newline
bitfld.long 0xA8 16.--18. "ll12dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xA8 15. "NU2," "0,1"
newline
hexmask.long.byte 0xA8 8.--14. 1. "LL12_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xA8 7. "NU1," "0,1"
newline
hexmask.long.byte 0xA8 0.--6. 1. "LL12_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xAC "CFG_DATA_LL13,"
bitfld.long 0xAC 31. "LL13_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xAC 30. "LL13_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xAC 29. "LL13_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xAC 28. "LL13_CRC_EN," "0,1"
newline
bitfld.long 0xAC 27. "LL13_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xAC 26. "LL13_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xAC 23.--25. "LL13_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xAC 9.--22. 1. "LL13_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xAC 8. "LL13_FMT_IN," "0,1"
newline
bitfld.long 0xAC 7. "LL13_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xAC 5.--6. "LL13_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xAC 3.--4. "LL13_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xAC 2. "LL13_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xAC 1. "LL13_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xAC 0. "LL13_VALID," "0,1"
line.long 0xB0 "CFG_DATA_LL13_LPHDR_VAL,"
line.long 0xB4 "CFG_DATA_LL13_THRESHOLD,"
hexmask.long.word 0xB4 19.--31. 1. "NU3,"
newline
bitfld.long 0xB4 16.--18. "ll13dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xB4 15. "NU2," "0,1"
newline
hexmask.long.byte 0xB4 8.--14. 1. "LL13_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xB4 7. "NU1," "0,1"
newline
hexmask.long.byte 0xB4 0.--6. 1. "LL13_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xB8 "CFG_DATA_LL14,"
bitfld.long 0xB8 31. "LL14_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xB8 30. "LL14_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xB8 29. "LL14_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xB8 28. "LL14_CRC_EN," "0,1"
newline
bitfld.long 0xB8 27. "LL14_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xB8 26. "LL14_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xB8 23.--25. "LL14_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xB8 9.--22. 1. "LL14_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xB8 8. "LL14_FMT_IN," "0,1"
newline
bitfld.long 0xB8 7. "LL14_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xB8 5.--6. "LL14_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xB8 3.--4. "LL14_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xB8 2. "LL14_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xB8 1. "LL14_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xB8 0. "LL14_VALID," "0,1"
line.long 0xBC "CFG_DATA_LL14_LPHDR_VAL,"
line.long 0xC0 "CFG_DATA_LL14_THRESHOLD,"
hexmask.long.word 0xC0 19.--31. 1. "NU3,"
newline
bitfld.long 0xC0 16.--18. "ll14dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xC0 15. "NU2," "0,1"
newline
hexmask.long.byte 0xC0 8.--14. 1. "LL14_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xC0 7. "NU1," "0,1"
newline
hexmask.long.byte 0xC0 0.--6. 1. "LL14_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xC4 "CFG_DATA_LL15,"
bitfld.long 0xC4 31. "LL15_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xC4 30. "LL15_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xC4 29. "LL15_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xC4 28. "LL15_CRC_EN," "0,1"
newline
bitfld.long 0xC4 27. "LL15_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xC4 26. "LL15_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xC4 23.--25. "LL15_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xC4 9.--22. 1. "LL15_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xC4 8. "LL15_FMT_IN," "0,1"
newline
bitfld.long 0xC4 7. "LL15_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xC4 5.--6. "LL15_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xC4 3.--4. "LL15_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xC4 2. "LL15_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xC4 1. "LL15_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xC4 0. "LL15_VALID," "0,1"
line.long 0xC8 "CFG_DATA_LL15_LPHDR_VAL,"
line.long 0xCC "CFG_DATA_LL15_THRESHOLD,"
hexmask.long.word 0xCC 19.--31. 1. "NU3,"
newline
bitfld.long 0xCC 16.--18. "ll15dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xCC 15. "NU2," "0,1"
newline
hexmask.long.byte 0xCC 8.--14. 1. "LL15_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xCC 7. "NU1," "0,1"
newline
hexmask.long.byte 0xCC 0.--6. 1. "LL15_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xD0 "CFG_DATA_LL16,"
bitfld.long 0xD0 31. "LL16_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xD0 30. "LL16_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xD0 29. "LL16_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xD0 28. "LL16_CRC_EN," "0,1"
newline
bitfld.long 0xD0 27. "LL16_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xD0 26. "LL16_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xD0 23.--25. "LL16_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xD0 9.--22. 1. "LL16_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xD0 8. "LL16_FMT_IN," "0,1"
newline
bitfld.long 0xD0 7. "LL16_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xD0 5.--6. "LL16_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xD0 3.--4. "LL16_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xD0 2. "LL16_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xD0 1. "LL16_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xD0 0. "LL16_VALID," "0,1"
line.long 0xD4 "CFG_DATA_LL16_LPHDR_VAL,"
line.long 0xD8 "CFG_DATA_LL16_THRESHOLD,"
hexmask.long.word 0xD8 19.--31. 1. "NU3,"
newline
bitfld.long 0xD8 16.--18. "ll16dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xD8 15. "NU2," "0,1"
newline
hexmask.long.byte 0xD8 8.--14. 1. "LL16_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xD8 7. "NU1," "0,1"
newline
hexmask.long.byte 0xD8 0.--6. 1. "LL16_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xDC "CFG_DATA_LL17,"
bitfld.long 0xDC 31. "LL17_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xDC 30. "LL17_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xDC 29. "LL17_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xDC 28. "LL17_CRC_EN," "0,1"
newline
bitfld.long 0xDC 27. "LL17_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xDC 26. "LL17_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xDC 23.--25. "LL17_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xDC 9.--22. 1. "LL17_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xDC 8. "LL17_FMT_IN," "0,1"
newline
bitfld.long 0xDC 7. "LL17_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xDC 5.--6. "LL17_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xDC 3.--4. "LL17_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xDC 2. "LL17_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xDC 1. "LL17_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xDC 0. "LL17_VALID," "0,1"
line.long 0xE0 "CFG_DATA_LL17_LPHDR_VAL,"
line.long 0xE4 "CFG_DATA_LL17_THRESHOLD,"
hexmask.long.word 0xE4 19.--31. 1. "NU3,"
newline
bitfld.long 0xE4 16.--18. "ll17dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xE4 15. "NU2," "0,1"
newline
hexmask.long.byte 0xE4 8.--14. 1. "LL17_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xE4 7. "NU1," "0,1"
newline
hexmask.long.byte 0xE4 0.--6. 1. "LL17_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xE8 "CFG_DATA_LL18,"
bitfld.long 0xE8 31. "LL18_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xE8 30. "LL18_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xE8 29. "LL18_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xE8 28. "LL18_CRC_EN," "0,1"
newline
bitfld.long 0xE8 27. "LL18_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xE8 26. "LL18_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xE8 23.--25. "LL18_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xE8 9.--22. 1. "LL18_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xE8 8. "LL18_FMT_IN," "0,1"
newline
bitfld.long 0xE8 7. "LL18_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xE8 5.--6. "LL18_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xE8 3.--4. "LL18_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xE8 2. "LL18_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xE8 1. "LL18_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xE8 0. "LL18_VALID," "0,1"
line.long 0xEC "CFG_DATA_LL18_LPHDR_VAL,"
line.long 0xF0 "CFG_DATA_LL18_THRESHOLD,"
hexmask.long.word 0xF0 19.--31. 1. "NU3,"
newline
bitfld.long 0xF0 16.--18. "ll18dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xF0 15. "NU2," "0,1"
newline
hexmask.long.byte 0xF0 8.--14. 1. "LL18_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xF0 7. "NU1," "0,1"
newline
hexmask.long.byte 0xF0 0.--6. 1. "LL18_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0xF4 "CFG_DATA_LL19,"
bitfld.long 0xF4 31. "LL19_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xF4 30. "LL19_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xF4 29. "LL19_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0xF4 28. "LL19_CRC_EN," "0,1"
newline
bitfld.long 0xF4 27. "LL19_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0xF4 26. "LL19_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0xF4 23.--25. "LL19_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0xF4 9.--22. 1. "LL19_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0xF4 8. "LL19_FMT_IN," "0,1"
newline
bitfld.long 0xF4 7. "LL19_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0xF4 5.--6. "LL19_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0xF4 3.--4. "LL19_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0xF4 2. "LL19_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0xF4 1. "LL19_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0xF4 0. "LL19_VALID," "0,1"
line.long 0xF8 "CFG_DATA_LL19_LPHDR_VAL,"
line.long 0xFC "CFG_DATA_LL19_THRESHOLD,"
hexmask.long.word 0xFC 19.--31. 1. "NU3,"
newline
bitfld.long 0xFC 16.--18. "ll19dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0xFC 15. "NU2," "0,1"
newline
hexmask.long.byte 0xFC 8.--14. 1. "LL19_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0xFC 7. "NU1," "0,1"
newline
hexmask.long.byte 0xFC 0.--6. 1. "LL19_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x100 "CFG_DATA_LL20,"
bitfld.long 0x100 31. "LL20_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x100 30. "LL20_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x100 29. "LL20_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x100 28. "LL20_CRC_EN," "0,1"
newline
bitfld.long 0x100 27. "LL20_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x100 26. "LL20_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x100 23.--25. "LL20_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x100 9.--22. 1. "LL20_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x100 8. "LL20_FMT_IN," "0,1"
newline
bitfld.long 0x100 7. "LL20_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x100 5.--6. "LL20_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x100 3.--4. "LL20_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x100 2. "LL20_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x100 1. "LL20_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x100 0. "LL20_VALID," "0,1"
line.long 0x104 "CFG_DATA_LL20_LPHDR_VAL,"
line.long 0x108 "CFG_DATA_LL20_THRESHOLD,"
hexmask.long.word 0x108 19.--31. 1. "NU3,"
newline
bitfld.long 0x108 16.--18. "ll20dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x108 15. "NU2," "0,1"
newline
hexmask.long.byte 0x108 8.--14. 1. "LL20_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x108 7. "NU1," "0,1"
newline
hexmask.long.byte 0x108 0.--6. 1. "LL20_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x10C "CFG_DATA_LL21,"
bitfld.long 0x10C 31. "LL21_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10C 30. "LL21_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10C 29. "LL21_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x10C 28. "LL21_CRC_EN," "0,1"
newline
bitfld.long 0x10C 27. "LL21_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x10C 26. "LL21_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x10C 23.--25. "LL21_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10C 9.--22. 1. "LL21_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x10C 8. "LL21_FMT_IN," "0,1"
newline
bitfld.long 0x10C 7. "LL21_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x10C 5.--6. "LL21_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x10C 3.--4. "LL21_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x10C 2. "LL21_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x10C 1. "LL21_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x10C 0. "LL21_VALID," "0,1"
line.long 0x110 "CFG_DATA_LL21_LPHDR_VAL,"
line.long 0x114 "CFG_DATA_LL21_THRESHOLD,"
hexmask.long.word 0x114 19.--31. 1. "NU3,"
newline
bitfld.long 0x114 16.--18. "ll21dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x114 15. "NU2," "0,1"
newline
hexmask.long.byte 0x114 8.--14. 1. "LL21_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x114 7. "NU1," "0,1"
newline
hexmask.long.byte 0x114 0.--6. 1. "LL21_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x118 "CFG_DATA_LL22,"
bitfld.long 0x118 31. "LL22_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x118 30. "LL22_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x118 29. "LL22_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x118 28. "LL22_CRC_EN," "0,1"
newline
bitfld.long 0x118 27. "LL22_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x118 26. "LL22_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x118 23.--25. "LL22_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x118 9.--22. 1. "LL22_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x118 8. "LL22_FMT_IN," "0,1"
newline
bitfld.long 0x118 7. "LL22_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x118 5.--6. "LL22_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x118 3.--4. "LL22_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x118 2. "LL22_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x118 1. "LL22_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x118 0. "LL22_VALID," "0,1"
line.long 0x11C "CFG_DATA_LL22_LPHDR_VAL,"
line.long 0x120 "CFG_DATA_LL22_THRESHOLD,"
hexmask.long.word 0x120 19.--31. 1. "NU3,"
newline
bitfld.long 0x120 16.--18. "ll22dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x120 15. "NU2," "0,1"
newline
hexmask.long.byte 0x120 8.--14. 1. "LL22_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x120 7. "NU1," "0,1"
newline
hexmask.long.byte 0x120 0.--6. 1. "LL22_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x124 "CFG_DATA_LL23,"
bitfld.long 0x124 31. "LL23_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x124 30. "LL23_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x124 29. "LL23_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x124 28. "LL23_CRC_EN," "0,1"
newline
bitfld.long 0x124 27. "LL23_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x124 26. "LL23_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x124 23.--25. "LL23_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x124 9.--22. 1. "LL23_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x124 8. "LL23_FMT_IN," "0,1"
newline
bitfld.long 0x124 7. "LL23_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x124 5.--6. "LL23_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x124 3.--4. "LL23_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x124 2. "LL23_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x124 1. "LL23_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x124 0. "LL23_VALID," "0,1"
line.long 0x128 "CFG_DATA_LL23_LPHDR_VAL,"
line.long 0x12C "CFG_DATA_LL23_THRESHOLD,"
hexmask.long.word 0x12C 19.--31. 1. "NU3,"
newline
bitfld.long 0x12C 16.--18. "ll23dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x12C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x12C 8.--14. 1. "LL23_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x12C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x12C 0.--6. 1. "LL23_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x130 "CFG_DATA_LL24,"
bitfld.long 0x130 31. "LL24_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x130 30. "LL24_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x130 29. "LL24_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x130 28. "LL24_CRC_EN," "0,1"
newline
bitfld.long 0x130 27. "LL24_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x130 26. "LL24_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x130 23.--25. "LL24_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x130 9.--22. 1. "LL24_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x130 8. "LL24_FMT_IN," "0,1"
newline
bitfld.long 0x130 7. "LL24_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x130 5.--6. "LL24_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x130 3.--4. "LL24_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x130 2. "LL24_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x130 1. "LL24_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x130 0. "LL24_VALID," "0,1"
line.long 0x134 "CFG_DATA_LL24_LPHDR_VAL,"
line.long 0x138 "CFG_DATA_LL24_THRESHOLD,"
hexmask.long.word 0x138 19.--31. 1. "NU3,"
newline
bitfld.long 0x138 16.--18. "ll24dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x138 15. "NU2," "0,1"
newline
hexmask.long.byte 0x138 8.--14. 1. "LL24_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x138 7. "NU1," "0,1"
newline
hexmask.long.byte 0x138 0.--6. 1. "LL24_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x13C "CFG_DATA_LL25,"
bitfld.long 0x13C 31. "LL25_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x13C 30. "LL25_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x13C 29. "LL25_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x13C 28. "LL25_CRC_EN," "0,1"
newline
bitfld.long 0x13C 27. "LL25_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x13C 26. "LL25_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x13C 23.--25. "LL25_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x13C 9.--22. 1. "LL25_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x13C 8. "LL25_FMT_IN," "0,1"
newline
bitfld.long 0x13C 7. "LL25_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x13C 5.--6. "LL25_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x13C 3.--4. "LL25_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x13C 2. "LL25_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x13C 1. "LL25_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x13C 0. "LL25_VALID," "0,1"
line.long 0x140 "CFG_DATA_LL25_LPHDR_VAL,"
line.long 0x144 "CFG_DATA_LL25_THRESHOLD,"
hexmask.long.word 0x144 19.--31. 1. "NU3,"
newline
bitfld.long 0x144 16.--18. "ll25dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x144 15. "NU2," "0,1"
newline
hexmask.long.byte 0x144 8.--14. 1. "LL25_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x144 7. "NU1," "0,1"
newline
hexmask.long.byte 0x144 0.--6. 1. "LL25_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x148 "CFG_DATA_LL26,"
bitfld.long 0x148 31. "LL26_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x148 30. "LL26_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x148 29. "LL26_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x148 28. "LL26_CRC_EN," "0,1"
newline
bitfld.long 0x148 27. "LL26_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x148 26. "LL26_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x148 23.--25. "LL26_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x148 9.--22. 1. "LL26_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x148 8. "LL26_FMT_IN," "0,1"
newline
bitfld.long 0x148 7. "LL26_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x148 5.--6. "LL26_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x148 3.--4. "LL26_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x148 2. "LL26_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x148 1. "LL26_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x148 0. "LL26_VALID," "0,1"
line.long 0x14C "CFG_DATA_LL26_LPHDR_VAL,"
line.long 0x150 "CFG_DATA_LL26_THRESHOLD,"
hexmask.long.word 0x150 19.--31. 1. "NU3,"
newline
bitfld.long 0x150 16.--18. "ll26dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x150 15. "NU2," "0,1"
newline
hexmask.long.byte 0x150 8.--14. 1. "LL26_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x150 7. "NU1," "0,1"
newline
hexmask.long.byte 0x150 0.--6. 1. "LL26_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x154 "CFG_DATA_LL27,"
bitfld.long 0x154 31. "LL27_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x154 30. "LL27_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x154 29. "LL27_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x154 28. "LL27_CRC_EN," "0,1"
newline
bitfld.long 0x154 27. "LL27_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x154 26. "LL27_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x154 23.--25. "LL27_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x154 9.--22. 1. "LL27_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x154 8. "LL27_FMT_IN," "0,1"
newline
bitfld.long 0x154 7. "LL27_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x154 5.--6. "LL27_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x154 3.--4. "LL27_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x154 2. "LL27_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x154 1. "LL27_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x154 0. "LL27_VALID," "0,1"
line.long 0x158 "CFG_DATA_LL27_LPHDR_VAL,"
line.long 0x15C "CFG_DATA_LL27_THRESHOLD,"
hexmask.long.word 0x15C 19.--31. 1. "NU3,"
newline
bitfld.long 0x15C 16.--18. "ll27dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x15C 15. "NU2," "0,1"
newline
hexmask.long.byte 0x15C 8.--14. 1. "LL27_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x15C 7. "NU1," "0,1"
newline
hexmask.long.byte 0x15C 0.--6. 1. "LL27_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x160 "CFG_DATA_LL28,"
bitfld.long 0x160 31. "LL28_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x160 30. "LL28_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x160 29. "LL28_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x160 28. "LL28_CRC_EN," "0,1"
newline
bitfld.long 0x160 27. "LL28_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x160 26. "LL28_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x160 23.--25. "LL28_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x160 9.--22. 1. "LL28_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x160 8. "LL28_FMT_IN," "0,1"
newline
bitfld.long 0x160 7. "LL28_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x160 5.--6. "LL28_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x160 3.--4. "LL28_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x160 2. "LL28_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x160 1. "LL28_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x160 0. "LL28_VALID," "0,1"
line.long 0x164 "CFG_DATA_LL28_LPHDR_VAL,"
line.long 0x168 "CFG_DATA_LL28_THRESHOLD,"
hexmask.long.word 0x168 19.--31. 1. "NU3,"
newline
bitfld.long 0x168 16.--18. "ll28dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x168 15. "NU2," "0,1"
newline
hexmask.long.byte 0x168 8.--14. 1. "LL28_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x168 7. "NU1," "0,1"
newline
hexmask.long.byte 0x168 0.--6. 1. "LL28_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x16C "CFG_DATA_LL29,"
bitfld.long 0x16C 31. "LL29_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x16C 30. "LL29_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x16C 29. "LL29_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x16C 28. "LL29_CRC_EN," "0,1"
newline
bitfld.long 0x16C 27. "LL29_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x16C 26. "LL29_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x16C 23.--25. "LL29_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x16C 9.--22. 1. "LL29_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x16C 8. "LL29_FMT_IN," "0,1"
newline
bitfld.long 0x16C 7. "LL29_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x16C 5.--6. "LL29_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x16C 3.--4. "LL29_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x16C 2. "LL29_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x16C 1. "LL29_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x16C 0. "LL29_VALID," "0,1"
line.long 0x170 "CFG_DATA_LL29_LPHDR_VAL,"
line.long 0x174 "CFG_DATA_LL29_THRESHOLD,"
hexmask.long.word 0x174 19.--31. 1. "NU3,"
newline
bitfld.long 0x174 16.--18. "ll29dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
newline
rbitfld.long 0x174 15. "NU2," "0,1"
newline
hexmask.long.byte 0x174 8.--14. 1. "LL29_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
newline
rbitfld.long 0x174 7. "NU1," "0,1"
newline
hexmask.long.byte 0x174 0.--6. 1. "LL29_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x178 "CFG_DATA_LL30,"
bitfld.long 0x178 31. "LL30_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x178 30. "LL30_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x178 29. "LL30_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
newline
bitfld.long 0x178 28. "LL30_CRC_EN," "0,1"
newline
bitfld.long 0x178 27. "LL30_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
newline
bitfld.long 0x178 26. "LL30_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
newline
bitfld.long 0x178 23.--25. "LL30_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x178 9.--22. 1. "LL30_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
newline
bitfld.long 0x178 8. "LL30_FMT_IN," "0,1"
newline
bitfld.long 0x178 7. "LL30_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
newline
bitfld.long 0x178 5.--6. "LL30_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
newline
bitfld.long 0x178 3.--4. "LL30_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
newline
bitfld.long 0x178 2. "LL30_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
newline
bitfld.long 0x178 1. "LL30_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
newline
bitfld.long 0x178 0. "LL30_VALID," "0,1"
line.long 0x17C "CFG_DATA_LL30_LPHDR_VAL,"
line.long 0x180 "CFG_DATA_LL30_THRESHOLD,"
hexmask.long.word 0x180 19.--31. 1. "NU3,"
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bitfld.long 0x180 16.--18. "ll30dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
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rbitfld.long 0x180 15. "NU2," "0,1"
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hexmask.long.byte 0x180 8.--14. 1. "LL30_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
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rbitfld.long 0x180 7. "NU1," "0,1"
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hexmask.long.byte 0x180 0.--6. 1. "LL30_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x184 "CFG_DATA_LL31,"
bitfld.long 0x184 31. "LL31_DATA_WR_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
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bitfld.long 0x184 30. "LL31_LONG_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
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bitfld.long 0x184 29. "LL31_SHORT_PKT_DELAY_EN,TI Internal Feature CSI2 only Programming : Use the Packet Delay configured in CFG_DELAY_CONFIG" "0,1"
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bitfld.long 0x184 28. "LL31_CRC_EN," "0,1"
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bitfld.long 0x184 27. "LL31_LPHDR_EN,CSI2 Programming" "Entry is not the start of the new LVDS Frame,Entry is start of a new LVDS Frame"
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bitfld.long 0x184 26. "LL31_WAITFOR_PKTSENT,TI Internal Feature Reserved for furture debug enhancement" "Do not wait for packet sent,Wait for packet sent signal ack from CSI2 to.."
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bitfld.long 0x184 23.--25. "LL31_BITPOS_SEL,TI Internal Feature" "0,1,2,3,4,5,6,7"
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hexmask.long.word 0x184 9.--22. 1. "LL31_SIZE,Configure the Size of the data in terms of the numer of samples (not in terms of number of bytes)"
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bitfld.long 0x184 8. "LL31_FMT_IN," "0,1"
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bitfld.long 0x184 7. "LL31_FMT_MAP,LVDS only" "Choose CFG_LVDS_MAPPING_LANEx_FMT_0_y,Choose CFG_LVDS_MAPPING_LANEx_FMT_1_y"
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bitfld.long 0x184 5.--6. "LL31_FMT,Specify the LVDS/CSI2 output format" "0,1,2,3"
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bitfld.long 0x184 3.--4. "LL31_VCNUM,CSI-2 : Configure the Virtual Channel Number for the Long Packet over which this data is sent" "0,1,2,3"
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bitfld.long 0x184 2. "LL31_HS,CSI-2" "Entry is not the first data of LVDS Frame,Entry is the first data in the LVDS Frame"
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bitfld.long 0x184 1. "LL31_HE,CSI-2" "Entry is not the last data of LVDS Frame,Entry is the last data in the LVDS Frame"
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bitfld.long 0x184 0. "LL31_VALID," "0,1"
line.long 0x188 "CFG_DATA_LL31_LPHDR_VAL,"
line.long 0x18C "CFG_DATA_LL31_THRESHOLD,"
hexmask.long.word 0x18C 19.--31. 1. "NU3,"
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bitfld.long 0x18C 16.--18. "ll31dman,If the long Packet Header is enabled CBUFF can generate a DMA request to trigger the DMA trasnfer for the new packet" "Send a Request on DMA HW Req output line 0,Send a Request on DMA HW Req output line 1,Send a Request on DMA HW Req output line 2,Send a Request on DMA HW Req output line 3,Send a Request on DMA HW Req output line 4,Send a Request on DMA HW Req output line 5,Send a Request on DMA HW Req output line 6,Do not generate dma trigger"
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rbitfld.long 0x18C 15. "NU2," "0,1"
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hexmask.long.byte 0x18C 8.--14. 1. "LL31_WR_THRESHOLD,Configure the CBUFF FIFO Write threshold over which CBUFF will stall the DMA write to the CBUFF"
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rbitfld.long 0x18C 7. "NU1," "0,1"
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hexmask.long.byte 0x18C 0.--6. 1. "LL31_RD_THRESHOLD,Configure the CBUFF Read threshold to be Reached before sending the data over CSI2/LVDS and start draining the CBUFF FIFO"
line.long 0x190 "CFG_LVDS_MAPPING_LANE0_FMT_0,"
bitfld.long 0x190 28.--31. "CFG_LVDS_MAPPING_LANE0_FMT_0_H,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 24.--27. "CFG_LVDS_MAPPING_LANE0_FMT_0_G,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 20.--23. "CFG_LVDS_MAPPING_LANE0_FMT_0_F,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 16.--19. "CFG_LVDS_MAPPING_LANE0_FMT_0_E,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 12.--15. "CFG_LVDS_MAPPING_LANE0_FMT_0_D,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 8.--11. "CFG_LVDS_MAPPING_LANE0_FMT_0_C,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 4.--7. "CFG_LVDS_MAPPING_LANE0_FMT_0_B,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x190 0.--3. "CFG_LVDS_MAPPING_LANE0_FMT_0_A,Lane 0 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
line.long 0x194 "CFG_LVDS_MAPPING_LANE1_FMT_0,"
bitfld.long 0x194 28.--31. "CFG_LVDS_MAPPING_LANE1_FMT_0_H,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 24.--27. "CFG_LVDS_MAPPING_LANE1_FMT_0_G,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 20.--23. "CFG_LVDS_MAPPING_LANE1_FMT_0_F,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 16.--19. "CFG_LVDS_MAPPING_LANE1_FMT_0_E,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 12.--15. "CFG_LVDS_MAPPING_LANE1_FMT_0_D,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 8.--11. "CFG_LVDS_MAPPING_LANE1_FMT_0_C,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 4.--7. "CFG_LVDS_MAPPING_LANE1_FMT_0_B,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
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bitfld.long 0x194 0.--3. "CFG_LVDS_MAPPING_LANE1_FMT_0_A,Lane 1 mapping if Format 0 is selected" "Entry is not valid,Entry is valid Please refer to LVDS Mapping..,?..."
line.long 0x198 "CFG_LVDS_MAPPING_LANE2_FMT_0,"
bitfld.long 0x198 28.--31. "CFG_LVDS_MAPPING_LANE2_FMT_0_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 24.--27. "CFG_LVDS_MAPPING_LANE2_FMT_0_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 20.--23. "CFG_LVDS_MAPPING_LANE2_FMT_0_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 16.--19. "CFG_LVDS_MAPPING_LANE2_FMT_0_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 12.--15. "CFG_LVDS_MAPPING_LANE2_FMT_0_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 8.--11. "CFG_LVDS_MAPPING_LANE2_FMT_0_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 4.--7. "CFG_LVDS_MAPPING_LANE2_FMT_0_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x198 0.--3. "CFG_LVDS_MAPPING_LANE2_FMT_0_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "CFG_LVDS_MAPPING_LANE3_FMT_0,"
bitfld.long 0x19C 28.--31. "CFG_LVDS_MAPPING_LANE3_FMT_0_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 24.--27. "CFG_LVDS_MAPPING_LANE3_FMT_0_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 20.--23. "CFG_LVDS_MAPPING_LANE3_FMT_0_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 16.--19. "CFG_LVDS_MAPPING_LANE3_FMT_0_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 12.--15. "CFG_LVDS_MAPPING_LANE3_FMT_0_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 8.--11. "CFG_LVDS_MAPPING_LANE3_FMT_0_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 4.--7. "CFG_LVDS_MAPPING_LANE3_FMT_0_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x19C 0.--3. "CFG_LVDS_MAPPING_LANE3_FMT_0_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "CFG_LVDS_MAPPING_LANE0_FMT_1,"
bitfld.long 0x1A0 28.--31. "CFG_LVDS_MAPPING_LANE0_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 24.--27. "CFG_LVDS_MAPPING_LANE0_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 20.--23. "CFG_LVDS_MAPPING_LANE0_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 16.--19. "CFG_LVDS_MAPPING_LANE0_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 12.--15. "CFG_LVDS_MAPPING_LANE0_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 8.--11. "CFG_LVDS_MAPPING_LANE0_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 4.--7. "CFG_LVDS_MAPPING_LANE0_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A0 0.--3. "CFG_LVDS_MAPPING_LANE0_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "CFG_LVDS_MAPPING_LANE1_FMT_1,"
bitfld.long 0x1A4 28.--31. "CFG_LVDS_MAPPING_LANE1_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 24.--27. "CFG_LVDS_MAPPING_LANE1_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 20.--23. "CFG_LVDS_MAPPING_LANE1_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 16.--19. "CFG_LVDS_MAPPING_LANE1_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 12.--15. "CFG_LVDS_MAPPING_LANE1_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 8.--11. "CFG_LVDS_MAPPING_LANE1_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 4.--7. "CFG_LVDS_MAPPING_LANE1_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A4 0.--3. "CFG_LVDS_MAPPING_LANE1_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "CFG_LVDS_MAPPING_LANE2_FMT_1,"
bitfld.long 0x1A8 28.--31. "CFG_LVDS_MAPPING_LANE2_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 24.--27. "CFG_LVDS_MAPPING_LANE2_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 20.--23. "CFG_LVDS_MAPPING_LANE2_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 16.--19. "CFG_LVDS_MAPPING_LANE2_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 12.--15. "CFG_LVDS_MAPPING_LANE2_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 8.--11. "CFG_LVDS_MAPPING_LANE2_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 4.--7. "CFG_LVDS_MAPPING_LANE2_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1A8 0.--3. "CFG_LVDS_MAPPING_LANE2_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "CFG_LVDS_MAPPING_LANE3_FMT_1,"
bitfld.long 0x1AC 28.--31. "CFG_LVDS_MAPPING_LANE3_FMT_1_H,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 24.--27. "CFG_LVDS_MAPPING_LANE3_FMT_1_G,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 20.--23. "CFG_LVDS_MAPPING_LANE3_FMT_1_F,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 16.--19. "CFG_LVDS_MAPPING_LANE3_FMT_1_E,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 12.--15. "CFG_LVDS_MAPPING_LANE3_FMT_1_D,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 8.--11. "CFG_LVDS_MAPPING_LANE3_FMT_1_C,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 4.--7. "CFG_LVDS_MAPPING_LANE3_FMT_1_B,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1AC 0.--3. "CFG_LVDS_MAPPING_LANE3_FMT_1_A,Please refer to LVDS Mapping Format section for confiuration details" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "CFG_LVDS_GEN_0,"
bitfld.long 0x1B0 30.--31. "cpz,LVDS Clock config" "0,1,2,3"
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bitfld.long 0x1B0 29. "cblpen,TI Internal CFG_LASTPULSE_EN" "0,1"
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bitfld.long 0x1B0 28. "cbcrcen,LVDS Frame CRC" "CRC is not sent at the end of LVDS Frame,CRC is sent at the end of the LVDS Frame"
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bitfld.long 0x1B0 24.--27. "cfdly,LVDS FIFO Initial Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1B0 23. "cmsbf," "0,1"
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bitfld.long 0x1B0 22. "cpossel," "0,1"
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bitfld.long 0x1B0 16.--21. "cckdiv,TI Internal feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x1B0 15. "cclksel1,TRM Description" "DDR mode clock mux,SDR mode clock mux TI Restricted Description"
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bitfld.long 0x1B0 14. "cclksel,TI Internal feature" "0,1"
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bitfld.long 0x1B0 12.--13. "ckchar,TI Internal feature" "0,1,2,3"
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bitfld.long 0x1B0 11. "ccsmen,TRM Description : As per alignment TI Restricted Description" "Regular operation,Continuous Streaming Mode Enabled (Not supported.."
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bitfld.long 0x1B0 10. "CFG_BIT_CLK_MODE,Bit Clock Mode" "SDR clocking mode,DDR clocking mode"
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bitfld.long 0x1B0 8.--9. "CFG_LINE_MODE,TI Internal feature" "0,1,2,3"
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bitfld.long 0x1B0 7. "cpkfmt,TI Internal feature" "0,1"
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bitfld.long 0x1B0 6. "cacdsel,TI Internal feature" "If the LVDS clock frequency (SDR) is >= 200MHz,If the LVDS clock frequency (SDR) is < 200MHz"
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bitfld.long 0x1B0 5. "ctc2en,TI Internal feature" "Regular operation,TC2MODE Enable (Not supported internally also in.."
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bitfld.long 0x1B0 4. "CFG_8B10B_EN,TI Internal Feature" "No encoding,8B10B encoding"
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bitfld.long 0x1B0 3. "CFG_LVDS_LANE3_EN,LVDS only programming" "LVDS Lane 3 is disbaled,LVDS Lane 3 is enabled"
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bitfld.long 0x1B0 2. "CFG_LVDS_LANE2_EN,LVDS only programming" "LVDS Lane 2 is disbaled,LVDS Lane 2 is enabled"
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bitfld.long 0x1B0 1. "CFG_LVDS_LANE1_EN,LVDS only programming" "LVDS Lane 1 is disbaled,LVDS Lane 1 is enabled"
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bitfld.long 0x1B0 0. "CFG_LVDS_LANE0_EN,LVDS only programming" "LVDS Lane 0 is disbaled,LVDS Lane 0 is enabled"
line.long 0x1B4 "CFG_LVDS_GEN_1,"
hexmask.long.word 0x1B4 19.--31. 1. "NU2,RESERVED"
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bitfld.long 0x1B4 18. "cgbcen,TI Internal Feature" "Bit clk is free running,Bit clk is valid only during the valid frame"
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bitfld.long 0x1B4 17. "cfcpol,TI Internal Feature" "During IDLE Frame clock will be 0,During IDLE"
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bitfld.long 0x1B4 16. "clfven,TI Internal feature" "Regular Operation,The frame_valid would start early by about 10.."
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bitfld.long 0x1B4 14.--15. "ctpsel3,TI Internal feature" "0,1,2,3"
newline
bitfld.long 0x1B4 12.--13. "ctpsel2,TI Internal feature" "0,1,2,3"
newline
bitfld.long 0x1B4 10.--11. "ctpsel1,TI Internal feature" "0,1,2,3"
newline
bitfld.long 0x1B4 8.--9. "ctpsel0,TI Internal feature" "0,1,2,3"
newline
rbitfld.long 0x1B4 7. "NU1,RESERVED" "0,1"
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bitfld.long 0x1B4 4.--6. "ctiddly,TI Internal feature" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x1B4 3. "NU3," "0,1"
newline
bitfld.long 0x1B4 2. "c3c3l,LVDS Only Programming" "Regular Operation,Enable 3Ch-3Lane mode in LVDS"
newline
bitfld.long 0x1B4 1. "csdrinv,TI Internal feature" "No inversion,Inversion"
newline
bitfld.long 0x1B4 0. "ctpen,TI Internal feature" "Regular Operation,LVDS Testpattern Enable"
line.long 0x1B8 "CFG_LVDS_GEN_2,"
line.long 0x1BC "CFG_MASK_REG0,"
line.long 0x1C0 "CFG_MASK_REG1,"
line.long 0x1C4 "CFG_MASK_REG2,"
line.long 0x1C8 "CFG_MASK_REG3,"
line.long 0x1CC "STAT_CBUFF_REG0,"
hexmask.long.tbyte 0x1CC 13.--31. 1. "STAT_CBUFF_REG0_OTHERS,Reseved for future enhancement"
newline
bitfld.long 0x1CC 12. "S_FRAME_DONE,Indicates that CBUFF has completed sending out data for the current Frame" "0,1"
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bitfld.long 0x1CC 11. "S_CHIRP_DONE,Indicates that CBUFF has completed sending out data for the current Chirp" "0,1"
newline
bitfld.long 0x1CC 6.--10. "S_LL_INDEX,TI Internal Feature" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1CC 5. "S_CSI_PKT_LP_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Long Data Packet" "0,1"
newline
bitfld.long 0x1CC 4. "S_CSI_PKT_HE_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Hsync End Packet" "0,1"
newline
bitfld.long 0x1CC 3. "S_CSI_PKT_HS_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Hsync Start Packet" "0,1"
newline
bitfld.long 0x1CC 2. "S_CSI_PKT_VE_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Vsync End Packet" "0,1"
newline
bitfld.long 0x1CC 1. "S_CSI_PKT_VS_RCVD_STATE,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine after Vsync Start Packet" "0,1"
newline
bitfld.long 0x1CC 0. "S_CSI_PKT_RCVD,TI Internal Feature Indicates that the CSI-2 Packet Received is sent to the CBUFF from the Protocol Engine" "0,1"
line.long 0x1D0 "STAT_CBUFF_REG1,"
hexmask.long.word 0x1D0 21.--31. 1. "S1_UNUSED3,"
newline
bitfld.long 0x1D0 20. "S_CBFIFO_READY_IN_FSM,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 19. "S_CBFIFO_EMPTY_IN_FSM,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 18. "S_PKTRCV_ERR,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 17. "S_FRAME_ERR,Indicates the FrameStart arrived before CBUFF has completed sending out data for all the Chirps programmed" "0,1"
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bitfld.long 0x1D0 16. "S_CHIRP_ERR,Indicates tha the chirpAvailable from ADCBuffer arrived before CBUFF has completed sending out the previous Chirp data" "0,1"
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bitfld.long 0x1D0 12.--15. "S1_UNUSED2,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1D0 11. "S_CBFIFO_EMPTY,TI Internal Feature" "0,1"
newline
bitfld.long 0x1D0 10. "S_CBFIFO_FULL,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 9. "S_CBPUSH_ERR,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 8. "S_CBPOP_ERR,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 3.--7. "S1_UNUSED1,RESERVED" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1D0 2. "S_LCLPUSH_ERR,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 1. "S_LCLPOP_ERR,TI Internal Feature" "0,1"
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bitfld.long 0x1D0 0. "S_LCLFSM_ERR,TI Internal Feature" "0,1"
rgroup.long 0x1FC++0x03
line.long 0x00 "STAT_LVDS_REG0,"
group.long 0x20C++0x27
line.long 0x00 "CLR_CBUFF_REG0,"
hexmask.long.tbyte 0x00 13.--31. 1. "CLR_CBUFF_REG0_OTHERS,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0"
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bitfld.long 0x00 12. "C_FRAME_DONE,Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 11. "C_CHIRP_DONE,Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 6.--10. "C_LL_INDEX,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 5. "C_CSI_PKT_LP_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 4. "C_CSI_PKT_HE_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 3. "C_CSI_PKT_HS_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 2. "C_CSI_PKT_VE_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 1. "C_CSI_PKT_VS_RCVD_STATE,TI Internal Feature.Clear Register field corresponding to STAT_CBUFF_REG0" "0,1"
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bitfld.long 0x00 0. "C_CSI_PKT_RCVD,TI Internal Feature" "0,1"
line.long 0x04 "CLR_CBUFF_REG1,"
line.long 0x08 "CLR_LVDS_REG0,"
line.long 0x0C "CLR_LVDS_REG1,"
line.long 0x10 "STAT_CBUFF_ECC_REG,"
hexmask.long.tbyte 0x10 10.--31. 1. "NU2,"
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bitfld.long 0x10 9. "seccdbe," "0,1"
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bitfld.long 0x10 8. "seccsbe," "0,1"
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bitfld.long 0x10 6.--7. "NU1," "0,1,2,3"
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bitfld.long 0x10 0.--5. "seccadd,6-bit address where the ECC error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "MASK_CBUFF_ECC_REG,"
hexmask.long.tbyte 0x14 10.--31. 1. "NU2,"
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bitfld.long 0x14 9. "meccdbe," "0,1"
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bitfld.long 0x14 8. "meccsbe," "0,1"
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hexmask.long.byte 0x14 0.--7. 1. "NU1,"
line.long 0x18 "CLR_CBUFF_ECC_REG,"
hexmask.long.tbyte 0x18 10.--31. 1. "NU2,"
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bitfld.long 0x18 9. "ceccdbe,Clear Register field corresponding to STAT_CBUFF_ECC" "0,1"
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bitfld.long 0x18 8. "ceccsbe,Clear Register field corresponding to STAT_CBUFF_ECC" "0,1"
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hexmask.long.byte 0x18 1.--7. 1. "NU1,"
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bitfld.long 0x18 0. "ceccadd,Clear Register field corresponding to STAT_CBUFF_ECC" "0,1"
line.long 0x1C "STAT_SAFETY,"
hexmask.long.tbyte 0x1C 9.--31. 1. "SAF_UNUSED1,RESERVED"
newline
bitfld.long 0x1C 8. "SAF_CHIRP_ERR,Safety Error" "0,1"
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abitfld.long 0x1C 0.--7. "SAF_CRC,TRM Desccription : Indicates a CRC error between ADCBuffer and CBUFF" "0x00=CRC for col-0 - [15:0],0x01=CRC for col-1 [31:16],0x02=CRC for col-2 [47:32],0x03=CRC for col-3 [63:48],0x04=CRC for col-4 - [79:64],0x05=CRC for col-5 [95:80],0x06=CRC for col-6 [111 :96,0x07=for col-7 [127:112]"
line.long 0x20 "MASK_SAFETY,"
line.long 0x24 "CLR_SAFETY,"
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x200)++0x03
line.long 0x00 "STAT_LVDS_REG$1,"
repeat.end
repeat 2. (list 2. 3. )(list 0x00 0x04 )
rgroup.long ($2+0x1F4)++0x03
line.long 0x00 "STAT_CBUFF_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_CM4_CTRL (DSS CM4 Control Module Registers)"
base ad:0x48020000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 11.--15. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "UNDEFINED_NAME," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x7F
line.long 0x00 "HWA_CM4_B0_MEMINIT_START,"
bitfld.long 0x00 0. "hwa_cm4_b0_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x04 "HWA_CM4_B0_MEMINIT_STATUS,"
bitfld.long 0x04 0. "hwa_cm4_b0_meminit_status,Status field" "0,1"
line.long 0x08 "HWA_CM4_B0_MEMINIT_DONE,"
bitfld.long 0x08 0. "hwa_cm4_b0_meminit_done,Status field" "0,1"
line.long 0x0C "HWA_CM4_B1_MEMINIT_START,"
bitfld.long 0x0C 0. "hwa_cm4_b1_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x10 "HWA_CM4_B1_MEMINIT_STATUS,"
bitfld.long 0x10 0. "hwa_cm4_b1_meminit_status,Status field" "0,1"
line.long 0x14 "HWA_CM4_B1_MEMINIT_DONE,"
bitfld.long 0x14 0. "hwa_cm4_b1_meminit_done,Status field" "0,1"
line.long 0x18 "HWA_CM4_B2_MEMINIT_START,"
bitfld.long 0x18 0. "hwa_cm4_b2_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x1C "HWA_CM4_B2_MEMINIT_STATUS,"
bitfld.long 0x1C 0. "hwa_cm4_b2_meminit_status,Status field" "0,1"
line.long 0x20 "HWA_CM4_B2_MEMINIT_DONE,"
bitfld.long 0x20 0. "hwa_cm4_b2_meminit_done,Status field" "0,1"
line.long 0x24 "HWA_CM4_MBOX_MEMINIT_START,"
bitfld.long 0x24 0. "hwa_cm4_mbox_meminit_start,Start Memory intialization of Param memory" "0,1"
line.long 0x28 "HWA_CM4_MBOX_MEMINIT_STATUS,"
bitfld.long 0x28 0. "hwa_cm4_mbox_meminit_status,Status field" "0,1"
line.long 0x2C "HWA_CM4_MBOX_MEMINIT_DONE,"
bitfld.long 0x2C 0. "hwa_cm4_mbox_meminit_done,Status field" "0,1"
line.long 0x30 "HWA_CM4_MBOX_WRITE_DONE,"
bitfld.long 0x30 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
bitfld.long 0x30 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
newline
bitfld.long 0x30 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
bitfld.long 0x30 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
newline
bitfld.long 0x30 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
bitfld.long 0x30 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
newline
bitfld.long 0x30 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
bitfld.long 0x30 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0x34 "HWA_CM4_MBOX_READ_REQ,"
bitfld.long 0x34 28. "proc_7,This is request from processor 7 to HSM" "0,1"
bitfld.long 0x34 24. "proc_6,This is request from processor 6 to HSM" "0,1"
newline
bitfld.long 0x34 20. "proc_5,This is request from processor 5 to HSM" "0,1"
bitfld.long 0x34 16. "proc_4,This is request from processor 4 to HSM" "0,1"
newline
bitfld.long 0x34 12. "proc_3,This is request from processor 3 to HSM" "0,1"
bitfld.long 0x34 8. "proc_2,This is request from processor 2 to HSM" "0,1"
newline
bitfld.long 0x34 4. "proc_1,This is request from processor 1 to HSM" "0,1"
bitfld.long 0x34 0. "proc_0,This is request from processor 0 to HSM" "0,1"
line.long 0x38 "HWA_CM4_MBOX_READ_DONE,"
bitfld.long 0x38 28. "proc_7,This register should be written once finishing reading from hsm's mailbox written by proc 7" "0,1"
bitfld.long 0x38 24. "proc_6,This register should be written once finishing reading from hsm's mailbox written by proc 6" "0,1"
newline
bitfld.long 0x38 20. "proc_5,This register should be written once finishing reading from hsm's mailbox written by proc 5" "0,1"
bitfld.long 0x38 16. "proc_4,This register should be written once finishing reading from hsm's mailbox written by proc 4" "0,1"
newline
bitfld.long 0x38 12. "proc_3,This register should be written once finishing reading from hsm's mailbox written by proc 3" "0,1"
bitfld.long 0x38 8. "proc_2,This register should be written once finishing reading from hsm's mailbox written by proc 2" "0,1"
newline
bitfld.long 0x38 4. "proc_1,This register should be written once finishing reading from hsm's mailbox written by proc 1" "0,1"
bitfld.long 0x38 0. "proc_0,This register should be written once finishing reading from hsm's mailbox written by proc 0" "0,1"
line.long 0x3C "HWA_CM4_IRQ_REQ,"
bitfld.long 0x3C 0.--1. "select,Software configration for INT Request" "0,1,2,3"
line.long 0x40 "HWA_CM4_POR_RST_CTRL,"
bitfld.long 0x40 0.--2. "assert,Por reset control for CM4" "0,1,2,3,4,5,6,7"
line.long 0x44 "HWA_CM4_SYS_RST_CTRL,"
bitfld.long 0x44 0.--2. "assert,Reset control for CM4" "0,1,2,3,4,5,6,7"
line.long 0x48 "HWA_CM4_CFG,"
bitfld.long 0x48 12.--14. "cm4_sys_reset_hold,In development mode by default cm4 will be held in reset" "0,1,2,3,4,5,6,7"
bitfld.long 0x48 8. "cm4_clk_gate,CM4 Clock Gate" "Un-gate the clock,Clock gated"
newline
bitfld.long 0x48 2. "wicenreq,WIC mode Request from PMU" "0,1"
bitfld.long 0x48 1. "sleep_hold_reqn,Hold core in sleep mode" "0,1"
newline
bitfld.long 0x48 0. "force_hclk_active,Force HCLK to run overrides GATEHCLK" "0,1"
line.long 0x4C "HWA_CM4_RST_CAUSE_CLR,"
bitfld.long 0x4C 0.--2. "clear,Writing '111' will clear the HWA_CM4_RST_STATUS_REG" "0,1,2,3,4,5,6,7"
line.long 0x50 "HWA_CM4_RST_CAUSE,"
hexmask.long.byte 0x50 0.--7. 1. "status,Reset Cause Register"
line.long 0x54 "HWA_CM4_FSM_RST_CTRL,"
bitfld.long 0x54 28.--30. "rst_fsm_trig,writing '111' will triggger the reset fsm for CM4" "0,1,2,3,4,5,6,7"
bitfld.long 0x54 24.--26. "rst_wficheck,writing '111' will check for WFI before asserting reset to CM4" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x54 16.--23. 1. "rst_assertdly_common,This field the decides number of cycles reset to CM4 should be asserted"
hexmask.long.byte 0x54 8.--15. 1. "rst2assertdly,This field the decides number cycles for which the reset should be held before asserting reset for CM4"
line.long 0x58 "HWA_CM4_WFI_OVERRIDE,"
bitfld.long 0x58 0.--2. "wfi_override,writing '111' will override the wfi signal from CM4" "0,1,2,3,4,5,6,7"
line.long 0x5C "HWA_CM4_PERIPH_ERRAGG_MASK,"
bitfld.long 0x5C 11. "rcss_ctrl_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 10. "rcss_ctrl_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 9. "rcss_rcm_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 8. "rcss_rcm_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 7. "dss_hwa_cfg_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 6. "dss_hwa_cfg_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 5. "dss_cm4_ctrl_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 4. "dss_cm4_ctrl_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 3. "dss_ctrl_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 2. "dss_ctrl_rd,Writing '1' will mask the respective peripheral error line" "0,1"
newline
bitfld.long 0x5C 1. "dss_rcm_wr,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x5C 0. "dss_rcm_rd,Writing '1' will mask the respective peripheral error line" "0,1"
line.long 0x60 "HWA_CM4_PERIPH_ERRAGG_STATUS,"
bitfld.long 0x60 11. "rcss_ctrl_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 10. "rcss_ctrl_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 9. "rcss_rcm_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 8. "rcss_rcm_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 7. "dss_hwa_cfg_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 6. "dss_hwa_cfg_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 5. "dss_cm4_ctrl_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 4. "dss_cm4_ctrl_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 3. "dss_ctrl_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 2. "dss_ctrl_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x60 1. "dss_rcm_wr,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x60 0. "dss_rcm_rd,Indicates the post mask status of the respective peripheral error line" "0,1"
line.long 0x64 "HWA_CM4_PERIPH_ERRAGG_STATUS_RAW,"
bitfld.long 0x64 11. "rcss_ctrl_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 10. "rcss_ctrl_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 9. "rcss_rcm_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 8. "rcss_rcm_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 7. "dss_hwa_cfg_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 6. "dss_hwa_cfg_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 5. "dss_cm4_ctrl_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 4. "dss_cm4_ctrl_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 3. "dss_ctrl_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 2. "dss_ctrl_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
newline
bitfld.long 0x64 1. "dss_rcm_wr,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x64 0. "dss_rcm_rd,Indicates the pre mask status of the respective peripheral error line" "0,1"
line.long 0x68 "HWA_CM4_AHB_ERRAGG_MASK,"
bitfld.long 0x68 2. "sbus_write,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x68 1. "dbus_write,Writing '1' will mask the respective peripheral error line" "0,1"
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bitfld.long 0x68 0. "ibus_write,Writing '1' will mask the respective peripheral error line" "0,1"
line.long 0x6C "HWA_CM4_AHB_ERRAGG_STATUS,"
bitfld.long 0x6C 2. "sbus_write,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x6C 1. "dbus_write,Indicates the post mask status of the respective peripheral error line" "0,1"
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bitfld.long 0x6C 0. "ibus_write,Indicates the post mask status of the respective peripheral error line" "0,1"
line.long 0x70 "HWA_CM4_AHB_ERRAGG_STATUS_RAW,"
bitfld.long 0x70 2. "sbus_write,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x70 1. "dbus_write,Indicates the pre mask status of the respective peripheral error line" "0,1"
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bitfld.long 0x70 0. "ibus_write,Indicates the pre mask status of the respective peripheral error line" "0,1"
line.long 0x74 "HWA_CM4_ECC_ERRAGG_MASK,"
bitfld.long 0x74 3. "mbox_ded,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x74 2. "bank2_ded,Writing '1' will mask the respective peripheral error line" "0,1"
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bitfld.long 0x74 1. "bank1_ded,Writing '1' will mask the respective peripheral error line" "0,1"
bitfld.long 0x74 0. "bank0_ded,Writing '1' will mask the respective peripheral error line" "0,1"
line.long 0x78 "HWA_CM4_ECC_ERRAGG_STATUS,"
bitfld.long 0x78 3. "mbox_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x78 2. "bank2_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
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bitfld.long 0x78 1. "bank1_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
bitfld.long 0x78 0. "bank0_ded,Indicates the post mask status of the respective peripheral error line" "0,1"
line.long 0x7C "HWA_CM4_ECC_ERRAGG_STATUS_RAW,"
bitfld.long 0x7C 3. "mbox_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x7C 2. "bank2_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
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bitfld.long 0x7C 1. "bank1_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
bitfld.long 0x7C 0. "bank0_ded,Indicates the pre mask status of the respective peripheral error line" "0,1"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "UNDEFINED_NAME,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "UNDEFINED_NAME,Kick access violation error" "0,1"
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bitfld.long 0x08 1. "UNDEFINED_NAME,Addressing violation error" "0,1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "UNDEFINED_NAME,Kick access violation error" "0,1"
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bitfld.long 0x0C 1. "UNDEFINED_NAME,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "UNDEFINED_NAME,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "UNDEFINED_NAME,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "UNDEFINED_NAME,Kick access violation error enable" "0,1"
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bitfld.long 0x10 1. "UNDEFINED_NAME,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "UNDEFINED_NAME,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "UNDEFINED_NAME,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "UNDEFINED_NAME,Kick access violation error enable clear" "0,1"
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bitfld.long 0x14 1. "UNDEFINED_NAME,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "UNDEFINED_NAME,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "UNDEFINED_NAME,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "UNDEFINED_NAME,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "UNDEFINED_NAME,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "UNDEFINED_NAME,XID"
hexmask.long.word 0x24 8.--19. 1. "UNDEFINED_NAME,Route ID"
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hexmask.long.byte 0x24 0.--7. 1. "UNDEFINED_NAME,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "UNDEFINED_NAME,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_CM4_STC (DSS DSP STC Module Registers)"
base ad:0x6F79200
group.long 0x00++0x11B
line.long 0x00 "STCGCR0,Self test Global control Reg0"
hexmask.long.word 0x00 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run"
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rbitfld.long 0x00 11.--15. "NU0,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval" "Continue NSTC run from previous interval,Restart NSTC run from ROM address 0 1X = Start..,?..."
line.long 0x04 "STCGCR1,Self test Global control Reg1"
hexmask.long.tbyte 0x04 12.--31. 1. "NU2,Reserved bits"
newline
bitfld.long 0x04 8.--11. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x04 7. "NU3,Reserved bits" "0,1"
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bitfld.long 0x04 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode" "XOR mode,Spread mode"
newline
bitfld.long 0x04 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration" "Operates in Normal Scan Mode,Operates in Low Power Scan Mode"
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bitfld.long 0x04 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
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bitfld.long 0x04 0.--3. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "STCTPR,Time out counter preload register"
line.long 0x0C "STC_CADDR,Current Address register for CORE1"
line.long 0x10 "STCCICR,Current Interval count register"
hexmask.long.word 0x10 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well"
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hexmask.long.word 0x10 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run"
line.long 0x14 "STCGSTAT,Global Status Register"
hexmask.long.tbyte 0x14 12.--31. 1. "NU4,Reserved bits"
newline
bitfld.long 0x14 8.--11. "ST_ACTIVE,Tells whether self test is currently active or not" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 2.--7. "NU5,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)" "Self test run has not failed,SelfTest run has failed"
newline
bitfld.long 0x14 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)" "Not completed,SelfTest run Completed"
line.long 0x18 "STCFSTAT,Fail Status Register"
hexmask.long 0x18 5.--31. 1. "NU6,Reserved bits"
newline
bitfld.long 0x18 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur" "Failure on Segment 0,Failure on Segment 1,Failure on Segment 2,Failure on Segment 3"
newline
bitfld.long 0x18 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)" "No time out error occurred,SelfTest run failed due to a timeout error"
newline
bitfld.long 0x18 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)" "No MISR mismatch for CORE2,Self test run failed due to MISR mismatch for.."
newline
bitfld.long 0x18 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments" "No MISR mismatch for CORE1,Self test run failed due to MISR mismatch for.."
line.long 0x1C "STCSCSCR,Signature compare Self Check Register"
hexmask.long 0x1C 5.--31. 1. "NU7,Reserved bits"
newline
bitfld.long 0x1C 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)" "No fault insertion,Inserts fault in the logic unedr test which will.."
newline
bitfld.long 0x1C 0.--3. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "STC_CADDR2,Current Address register for CORE2"
line.long 0x24 "STC_CLKDIV,Clock Divider Register"
rbitfld.long 0x24 27.--31. "NU8,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 19.--23. "NU9,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 11.--15. "NU10,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 3.--7. "NU11,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
line.long 0x28 "STC_SEGPLR,Segment 1st interval Preload Register"
hexmask.long 0x28 2.--31. 1. "NU12,Reserved bits"
newline
bitfld.long 0x28 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter" "Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of.."
line.long 0x2C "SEG0_START_ADDR,ROM Start address for Segment0"
hexmask.long.word 0x2C 20.--31. 1. "NU13,Reserved bits"
newline
hexmask.long.tbyte 0x2C 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x30 "SEG1_START_ADDR,ROM Start address for Segment1"
hexmask.long.word 0x30 20.--31. 1. "NU14,Reserved bits"
newline
hexmask.long.tbyte 0x30 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x34 "SEG2_START_ADDR,ROM Start address for Segment2"
hexmask.long.word 0x34 20.--31. 1. "NU15,Reserved bits"
newline
hexmask.long.tbyte 0x34 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x38 "SEG3_START_ADDR,ROM Start address for Segment3"
hexmask.long.word 0x38 20.--31. 1. "NU16,Reserved bits"
newline
hexmask.long.tbyte 0x38 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x3C "CORE1_CURMISR_0,Holds the MISR signature for CORE1"
line.long 0x40 "CORE1_CURMISR_1,Holds the MISR signature for CORE1"
line.long 0x44 "CORE1_CURMISR_2,Holds the MISR signature for CORE1"
line.long 0x48 "CORE1_CURMISR_3,Holds the MISR signature for CORE1"
line.long 0x4C "CORE1_CURMISR_4,Holds the MISR signature for CORE1"
line.long 0x50 "CORE1_CURMISR_5,Holds the MISR signature for CORE1"
line.long 0x54 "CORE1_CURMISR_6,Holds the MISR signature for CORE1"
line.long 0x58 "CORE1_CURMISR_7,Holds the MISR signature for CORE1"
line.long 0x5C "CORE1_CURMISR_8,Holds the MISR signature for CORE1"
line.long 0x60 "CORE1_CURMISR_9,Holds the MISR signature for CORE1"
line.long 0x64 "CORE1_CURMISR_10,Holds the MISR signature for CORE1"
line.long 0x68 "CORE1_CURMISR_11,Holds the MISR signature for CORE1"
line.long 0x6C "CORE1_CURMISR_12,Holds the MISR signature for CORE1"
line.long 0x70 "CORE1_CURMISR_13,Holds the MISR signature for CORE1"
line.long 0x74 "CORE1_CURMISR_14,Holds the MISR signature for CORE1"
line.long 0x78 "CORE1_CURMISR_15,Holds the MISR signature for CORE1"
line.long 0x7C "CORE1_CURMISR_16,Holds the MISR signature for CORE1"
line.long 0x80 "CORE1_CURMISR_17,Holds the MISR signature for CORE1"
line.long 0x84 "CORE1_CURMISR_18,Holds the MISR signature for CORE1"
line.long 0x88 "CORE1_CURMISR_19,Holds the MISR signature for CORE1"
line.long 0x8C "CORE1_CURMISR_20,Holds the MISR signature for CORE1"
line.long 0x90 "CORE1_CURMISR_21,Holds the MISR signature for CORE1"
line.long 0x94 "CORE1_CURMISR_22,Holds the MISR signature for CORE1"
line.long 0x98 "CORE1_CURMISR_23,Holds the MISR signature for CORE1"
line.long 0x9C "CORE1_CURMISR_24,Holds the MISR signature for CORE1"
line.long 0xA0 "CORE1_CURMISR_25,Holds the MISR signature for CORE1"
line.long 0xA4 "CORE1_CURMISR_26,Holds the MISR signature for CORE1"
line.long 0xA8 "CORE1_CURMISR_27,Holds the MISR signature for CORE1"
line.long 0xAC "CORE2_CURMISR_0,Holds the MISR signature for CORE2"
line.long 0xB0 "CORE2_CURMISR_1,Holds the MISR signature for CORE2"
line.long 0xB4 "CORE2_CURMISR_2,Holds the MISR signature for CORE2"
line.long 0xB8 "CORE2_CURMISR_3,Holds the MISR signature for CORE2"
line.long 0xBC "CORE2_CURMISR_4,Holds the MISR signature for CORE2"
line.long 0xC0 "CORE2_CURMISR_5,Holds the MISR signature for CORE2"
line.long 0xC4 "CORE2_CURMISR_6,Holds the MISR signature for CORE2"
line.long 0xC8 "CORE2_CURMISR_7,Holds the MISR signature for CORE2"
line.long 0xCC "CORE2_CURMISR_8,Holds the MISR signature for CORE2"
line.long 0xD0 "CORE2_CURMISR_9,Holds the MISR signature for CORE2"
line.long 0xD4 "CORE2_CURMISR_10,Holds the MISR signature for CORE2"
line.long 0xD8 "CORE2_CURMISR_11,Holds the MISR signature for CORE2"
line.long 0xDC "CORE2_CURMISR_12,Holds the MISR signature for CORE2"
line.long 0xE0 "CORE2_CURMISR_13,Holds the MISR signature for CORE2"
line.long 0xE4 "CORE2_CURMISR_14,Holds the MISR signature for CORE2"
line.long 0xE8 "CORE2_CURMISR_15,Holds the MISR signature for CORE2"
line.long 0xEC "CORE2_CURMISR_16,Holds the MISR signature for CORE2"
line.long 0xF0 "CORE2_CURMISR_17,Holds the MISR signature for CORE2"
line.long 0xF4 "CORE2_CURMISR_18,Holds the MISR signature for CORE2"
line.long 0xF8 "CORE2_CURMISR_19,Holds the MISR signature for CORE2"
line.long 0xFC "CORE2_CURMISR_20,Holds the MISR signature for CORE2"
line.long 0x100 "CORE2_CURMISR_21,Holds the MISR signature for CORE2"
line.long 0x104 "CORE2_CURMISR_22,Holds the MISR signature for CORE2"
line.long 0x108 "CORE2_CURMISR_23,Holds the MISR signature for CORE2"
line.long 0x10C "CORE2_CURMISR_24,Holds the MISR signature for CORE2"
line.long 0x110 "CORE2_CURMISR_25,Holds the MISR signature for CORE2"
line.long 0x114 "CORE2_CURMISR_26,Holds the MISR signature for CORE2"
line.long 0x118 "CORE2_CURMISR_27,Holds the MISR signature for CORE2"
width 0x0B
tree.end
tree "DSS_CTRL (DSS CTRL Module Registers)"
base ad:0x6020000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x5B
line.long 0x00 "DSS_SW_INT,"
bitfld.long 0x00 0.--3. "dss_swint,DSS SW Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DSS_TPCC_A_ERRAGG_MASK,"
bitfld.long 0x04 26. "tptc_a1_read_access_error,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 25. "tptc_a0_read_access_error,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 24. "tpcc_a_read_access_error,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 18. "tptc_a1_write_access_error,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPTC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 17. "tptc_a0_write_access_error,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPTC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 16. "tpcc_a_write_access_error,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 8. "tpcc_a_parity_err,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 3. "tptc_a1_err,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 2. "tptc_a0_err,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 1. "tpcc_a_mpint,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x04 0. "tpcc_a_errint,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x08 "DSS_TPCC_A_ERRAGG_STATUS,"
bitfld.long 0x08 26. "tptc_a1_read_access_error,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 25. "tptc_a0_read_access_error,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 24. "tpcc_a_read_access_error,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 18. "tptc_a1_write_access_error,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 17. "tptc_a0_write_access_error,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 16. "tpcc_a_write_access_error,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 8. "tpcc_a_parity_err,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 3. "tptc_a1_err,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 2. "tptc_a0_err,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 1. "tpcc_a_mpint,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 0. "tpcc_a_errint,Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x0C "DSS_TPCC_A_ERRAGG_STATUS_RAW,"
bitfld.long 0x0C 26. "tptc_a1_read_access_error,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x0C 25. "tptc_a0_read_access_error,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x0C 24. "tpcc_a_read_access_error,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 18. "tptc_a1_write_access_error,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x0C 17. "tptc_a0_write_access_error,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x0C 16. "tpcc_a_write_access_error,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 8. "tpcc_a_parity_err,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 3. "tptc_a1_err,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x0C 2. "tptc_a0_err,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x0C 1. "tpcc_a_mpint,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x0C 0. "tpcc_a_errint,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x10 "DSS_TPCC_A_INTAGG_MASK,"
bitfld.long 0x10 17. "tptc_a1,Mask Interrupt from DSS_TPTC_A1 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 16. "tptc_a0,Mask Interrupt from DSS_TPTC_A0 to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 8. "tpcc_a_int7,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 7. "tpcc_a_int6,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 6. "tpcc_a_int5,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 5. "tpcc_a_int4,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 4. "tpcc_a_int3,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 3. "tpcc_a_int2,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 2. "tpcc_a_int1,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 1. "tpcc_a_int0,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 0. "tpcc_a_intg,Mask Interrupt from DSS_TPCC_A to aggregated Interrupt DSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x14 "DSS_TPCC_A_INTAGG_STATUS,"
bitfld.long 0x14 17. "tptc_a1,Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x14 16. "tptc_a0,Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x14 8. "tpcc_a_int7,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 7. "tpcc_a_int6,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 6. "tpcc_a_int5,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 5. "tpcc_a_int4,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 4. "tpcc_a_int3,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 3. "tpcc_a_int2,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 2. "tpcc_a_int1,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 1. "tpcc_a_int0,Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 0. "tpcc_a_intg,Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x18 "DSS_TPCC_A_INTAGG_STATUS_RAW,"
bitfld.long 0x18 17. "tptc_a1,Raw Status of Interrupt from DSS_TPTC_A1" "0,1"
newline
bitfld.long 0x18 16. "tptc_a0,Raw Status of Interrupt from DSS_TPTC_A0" "0,1"
newline
bitfld.long 0x18 8. "tpcc_a_int7,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 7. "tpcc_a_int6,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 6. "tpcc_a_int5,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 5. "tpcc_a_int4,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 4. "tpcc_a_int3,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 3. "tpcc_a_int2,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 2. "tpcc_a_int1,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 1. "tpcc_a_int0,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
newline
bitfld.long 0x18 0. "tpcc_a_intg,Raw Status of Interrupt from DSS_TPCC_A" "0,1"
line.long 0x1C "DSS_TPCC_B_ERRAGG_MASK,"
bitfld.long 0x1C 26. "tptc_b1_read_access_error,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 25. "tptc_b0_read_access_error,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 24. "tpcc_b_read_access_error,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 18. "tptc_b1_write_access_error,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 17. "tptc_b0_write_access_error,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 16. "tpcc_b_write_access_error,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 8. "tpcc_b_parity_err,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 3. "tptc_b1_err,Mask Error from DSS_TPTC_B1 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 2. "tptc_b0_err,Mask Error from DSS_TPTC_B0 to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 1. "tpcc_b_mpint,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x1C 0. "tpcc_b_errint,Mask Error from DSS_TPCC_B to aggregated Error DSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x20 "DSS_TPCC_B_ERRAGG_STATUS,"
bitfld.long 0x20 26. "tptc_b1_read_access_error,Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x20 25. "tptc_b0_read_access_error,Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x20 24. "tpcc_b_read_access_error,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 18. "tptc_b1_write_access_error,Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x20 17. "tptc_b0_write_access_error,Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x20 16. "tpcc_b_write_access_error,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 8. "tpcc_b_parity_err,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 3. "tptc_b1_err,Status of Error from DSS_TPCC_B1" "0,1"
newline
bitfld.long 0x20 2. "tptc_b0_err,Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x20 1. "tpcc_b_mpint,Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x20 0. "tpcc_b_errint,Status of Error from DSS_TPCC_B" "0,1"
line.long 0x24 "DSS_TPCC_B_ERRAGG_STATUS_RAW,"
bitfld.long 0x24 26. "tptc_b1_read_access_error,Raw Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x24 25. "tptc_b0_read_access_error,Raw Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x24 24. "tpcc_b_read_access_error,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 18. "tptc_b1_write_access_error,Raw Status of Error from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x24 17. "tptc_b0_write_access_error,Raw Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x24 16. "tpcc_b_write_access_error,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 8. "tpcc_b_parity_err,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 3. "tptc_b1_err,Raw Status of Error from DSS_TPCC_B1" "0,1"
newline
bitfld.long 0x24 2. "tptc_b0_err,Raw Status of Error from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x24 1. "tpcc_b_mpint,Raw Status of Error from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x24 0. "tpcc_b_errint,Raw Status of Error from DSS_TPCC_B" "0,1"
line.long 0x28 "DSS_TPCC_B_INTAGG_MASK,"
bitfld.long 0x28 17. "tptc_b1,Mask Interrupt from DSS_TPTC_B1 to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 16. "tptc_b0,Mask Interrupt from DSS_TPTC_B0 to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 8. "tpcc_b_int7,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 7. "tpcc_b_int6,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 6. "tpcc_b_int5,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 5. "tpcc_b_int4,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 4. "tpcc_b_int3,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 3. "tpcc_b_int2,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 2. "tpcc_b_int1,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 1. "tpcc_b_int0,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x28 0. "tpcc_b_intg,Mask Interrupt from DSS_TPCC_B to aggregated Interrupt DSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x2C "DSS_TPCC_B_INTAGG_STATUS,"
bitfld.long 0x2C 17. "tptc_b1,Status of Interrupt from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x2C 16. "tptc_b0,Status of Interrupt from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x2C 8. "tpcc_b_int7,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 7. "tpcc_b_int6,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 6. "tpcc_b_int5,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 5. "tpcc_b_int4,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 4. "tpcc_b_int3,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 3. "tpcc_b_int2,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 2. "tpcc_b_int1,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 1. "tpcc_b_int0,Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x2C 0. "tpcc_b_intg,Status of Interrupt from DSS_TPCC_B" "0,1"
line.long 0x30 "DSS_TPCC_B_INTAGG_STATUS_RAW,"
bitfld.long 0x30 17. "tptc_b1,Raw Status of Interrupt from DSS_TPTC_B1" "0,1"
newline
bitfld.long 0x30 16. "tptc_b0,Raw Status of Interrupt from DSS_TPTC_B0" "0,1"
newline
bitfld.long 0x30 8. "tpcc_b_int7,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 7. "tpcc_b_int6,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 6. "tpcc_b_int5,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 5. "tpcc_b_int4,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 4. "tpcc_b_int3,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 3. "tpcc_b_int2,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 2. "tpcc_b_int1,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 1. "tpcc_b_int0,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
newline
bitfld.long 0x30 0. "tpcc_b_intg,Raw Status of Interrupt from DSS_TPCC_B" "0,1"
line.long 0x34 "DSS_TPCC_C_ERRAGG_MASK,"
bitfld.long 0x34 30. "tptc_c5_read_access_error,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 29. "tptc_c4_read_access_error,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 28. "tptc_c3_read_access_error,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 27. "tptc_c2_read_access_error,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 26. "tptc_c1_read_access_error,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 25. "tptc_c0_read_access_error,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 24. "tpcc_c_read_access_error,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 22. "tptc_c5_write_access_error,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 21. "tptc_c4_write_access_error,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 20. "tptc_c3_write_access_error,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 19. "tptc_c2_write_access_error,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 18. "tptc_c1_write_access_error,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 17. "tptc_c0_write_access_error,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 16. "tpcc_c_write_access_error,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 8. "tpcc_c_parity_err,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 7. "tptc_c5_err,Mask Error from DSS_TPTC_C5 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 6. "tptc_c4_err,Mask Error from DSS_TPTC_C4 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 5. "tptc_c3_err,Mask Error from DSS_TPTC_C3 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 4. "tptc_c2_err,Mask Error from DSS_TPTC_C2 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 3. "tptc_c1_err,Mask Error from DSS_TPTC_C1 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 2. "tptc_c0_err,Mask Error from DSS_TPTC_C0 to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 1. "tpcc_c_mpint,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x34 0. "tpcc_c_errint,Mask Error from DSS_TPCC_C to aggregated Error DSS_TPCC_C_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x38 "DSS_TPCC_C_ERRAGG_STATUS,"
bitfld.long 0x38 30. "tptc_c5_read_access_error,Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x38 29. "tptc_c4_read_access_error,Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x38 28. "tptc_c3_read_access_error,Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x38 27. "tptc_c2_read_access_error,Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x38 26. "tptc_c1_read_access_error,Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x38 25. "tptc_c0_read_access_error,Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x38 24. "tpcc_c_read_access_error,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 22. "tptc_c5_write_access_error,Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x38 21. "tptc_c4_write_access_error,Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x38 20. "tptc_c3_write_access_error,Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x38 19. "tptc_c2_write_access_error,Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x38 18. "tptc_c1_write_access_error,Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x38 17. "tptc_c0_write_access_error,Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x38 16. "tpcc_c_write_access_error,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 8. "tpcc_c_parity_err,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 7. "tptc_c5_err,Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x38 6. "tptc_c4_err,Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x38 5. "tptc_c3_err,Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x38 4. "tptc_c2_err,Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x38 3. "tptc_c1_err,Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x38 2. "tptc_c0_err,Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x38 1. "tpcc_c_mpint,Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x38 0. "tpcc_c_errint,Status of Error from DSS_TPCC_C" "0,1"
line.long 0x3C "DSS_TPCC_C_ERRAGG_STATUS_RAW,"
bitfld.long 0x3C 30. "tptc_c5_read_access_error,Raw Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x3C 29. "tptc_c4_read_access_error,Raw Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x3C 28. "tptc_c3_read_access_error,Raw Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x3C 27. "tptc_c2_read_access_error,Raw Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x3C 26. "tptc_c1_read_access_error,Raw Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x3C 25. "tptc_c0_read_access_error,Raw Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x3C 24. "tpcc_c_read_access_error,Raw Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x3C 22. "tptc_c5_write_access_error,Raw Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x3C 21. "tptc_c4_write_access_error,Raw Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x3C 20. "tptc_c3_write_access_error,Raw Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x3C 19. "tptc_c2_write_access_error,Raw Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x3C 18. "tptc_c1_write_access_error,Raw Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x3C 17. "tptc_c0_write_access_error,Raw Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x3C 16. "tpcc_c_write_access_error,Raw Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x3C 8. "tpcc_c_parity_err,Raw Status of Error from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x3C 7. "tptc_c5_err,Raw Status of Error from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x3C 6. "tptc_c4_err,Raw Status of Error from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x3C 5. "tptc_c3_err,Raw Status of Error from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x3C 4. "tptc_c2_err,Raw Status of Error from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x3C 3. "tptc_c1_err,Raw Status of Error from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x3C 2. "tptc_c0_err,Raw Status of Error from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x3C 1. "tpcc_c_mpint,Raw Status of Error from DSS_TPCC_C0" "0,1"
newline
bitfld.long 0x3C 0. "tpcc_c_errint,Raw Status of Error from DSS_TPCC_C" "0,1"
line.long 0x40 "DSS_TPCC_C_INTAGG_MASK,"
bitfld.long 0x40 21. "tptc_c5,Mask Interrupt from DSS_TPTC_C5 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 20. "tptc_c4,Mask Interrupt from DSS_TPTC_C4 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 19. "tptc_c3,Mask Interrupt from DSS_TPTC_C3 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 18. "tptc_c2,Mask Interrupt from DSS_TPTC_C2 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 17. "tptc_c1,Mask Interrupt from DSS_TPTC_C1 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 16. "tptc_c0,Mask Interrupt from DSS_TPTC_C0 to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 8. "tpcc_c_int7,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 7. "tpcc_c_int6,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 6. "tpcc_c_int5,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 5. "tpcc_c_int4,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 4. "tpcc_c_int3,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 3. "tpcc_c_int2,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 2. "tpcc_c_int1,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 1. "tpcc_c_int0,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x40 0. "tpcc_c_intg,Mask Interrupt from DSS_TPCC_C to aggregated Interrupt DSS_TPCC_C_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x44 "DSS_TPCC_C_INTAGG_STATUS,"
bitfld.long 0x44 21. "tptc_c5,Status of Interrupt from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x44 20. "tptc_c4,Status of Interrupt from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x44 19. "tptc_c3,Status of Interrupt from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x44 18. "tptc_c2,Status of Interrupt from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x44 17. "tptc_c1,Status of Interrupt from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x44 16. "tptc_c0,Status of Interrupt from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x44 8. "tpcc_c_int7,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 7. "tpcc_c_int6,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 6. "tpcc_c_int5,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 5. "tpcc_c_int4,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 4. "tpcc_c_int3,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 3. "tpcc_c_int2,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 2. "tpcc_c_int1,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 1. "tpcc_c_int0,Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x44 0. "tpcc_c_intg,Status of Interrupt from DSS_TPCC_C" "0,1"
line.long 0x48 "DSS_TPCC_C_INTAGG_STATUS_RAW,"
bitfld.long 0x48 21. "tptc_c5,Raw Status of Interrupt from DSS_TPTC_C5" "0,1"
newline
bitfld.long 0x48 20. "tptc_c4,Raw Status of Interrupt from DSS_TPTC_C4" "0,1"
newline
bitfld.long 0x48 19. "tptc_c3,Raw Status of Interrupt from DSS_TPTC_C3" "0,1"
newline
bitfld.long 0x48 18. "tptc_c2,Raw Status of Interrupt from DSS_TPTC_C2" "0,1"
newline
bitfld.long 0x48 17. "tptc_c1,Raw Status of Interrupt from DSS_TPTC_C1" "0,1"
newline
bitfld.long 0x48 16. "tptc_c0,Raw Status of Interrupt from DSS_TPTC_C0" "0,1"
newline
bitfld.long 0x48 8. "tpcc_c_int7,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 7. "tpcc_c_int6,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 6. "tpcc_c_int5,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 5. "tpcc_c_int4,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 4. "tpcc_c_int3,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 3. "tpcc_c_int2,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 2. "tpcc_c_int1,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 1. "tpcc_c_int0,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
newline
bitfld.long 0x48 0. "tpcc_c_intg,Raw Status of Interrupt from DSS_TPCC_C" "0,1"
line.long 0x4C "DSS_TPCC_MEMINIT_START,"
bitfld.long 0x4C 2. "tpcc_c_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x4C 1. "tpcc_b_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x4C 0. "tpcc_a_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
line.long 0x50 "DSS_TPCC_MEMINIT_STATUS,"
bitfld.long 0x50 2. "tpcc_c_meminit_status,Status field" "0,1"
newline
bitfld.long 0x50 1. "tpcc_b_meminit_status,Status field" "0,1"
newline
bitfld.long 0x50 0. "tpcc_a_meminit_status,Status field" "0,1"
line.long 0x54 "DSS_TPCC_MEMINIT_DONE,"
bitfld.long 0x54 2. "tpcc_c_meminit_done,Status field" "0,1"
newline
bitfld.long 0x54 1. "tpcc_b_meminit_done,Status field" "0,1"
newline
bitfld.long 0x54 0. "tpcc_a_meminit_done,Status field" "0,1"
line.long 0x58 "DSS_DSP_L2RAM_PARITY_CTRL,"
hexmask.long.byte 0x58 8.--15. 1. "err_clear,Write to bit N to clear L2 Parity Error line N"
newline
hexmask.long.byte 0x58 0.--7. 1. "enable,Write to bit N to enable L2 Parity N"
group.long 0x80++0x23
line.long 0x00 "DSS_DSP_L2RAM_MEMINIT_START,"
bitfld.long 0x00 7. "vb31,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 6. "vb30,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 5. "vb21,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 4. "vb20,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 3. "vb11,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 2. "vb10,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 1. "vb01,Start Memory intialization of DSP L2 memory" "0,1"
newline
bitfld.long 0x00 0. "vb00,Start Memory intialization of DSP L2 memory" "0,1"
line.long 0x04 "DSS_DSP_L2RAM_MEMINIT_STATUS,"
bitfld.long 0x04 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x04 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x04 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x04 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x04 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x04 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x04 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x04 0. "vb00,Status field" "0,1"
line.long 0x08 "DSS_DSP_L2RAM_MEMINIT_DONE,"
bitfld.long 0x08 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x08 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x08 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x08 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x08 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x08 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x08 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x08 0. "vb00,Status field" "0,1"
line.long 0x0C "DSS_DSP_L2RAM_PARITY_MEMINIT_START,"
bitfld.long 0x0C 7. "vb31,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 6. "vb30,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 5. "vb21,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 4. "vb20,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 3. "vb11,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 2. "vb10,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 1. "vb01,Start Memory intialization of DSP L2 Parity memory" "0,1"
newline
bitfld.long 0x0C 0. "vb00,Start Memory intialization of DSP L2 Parity memory" "0,1"
line.long 0x10 "DSS_DSP_L2RAM_PARITY_MEMINIT_STATUS,"
bitfld.long 0x10 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x10 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x10 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x10 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x10 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x10 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x10 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x10 0. "vb00,Status field" "0,1"
line.long 0x14 "DSS_DSP_L2RAM_PARITY_MEMINIT_DONE,"
bitfld.long 0x14 7. "vb31,Status field" "0,1"
newline
bitfld.long 0x14 6. "vb30,Status field" "0,1"
newline
bitfld.long 0x14 5. "vb21,Status field" "0,1"
newline
bitfld.long 0x14 4. "vb20,Status field" "0,1"
newline
bitfld.long 0x14 3. "vb11,Status field" "0,1"
newline
bitfld.long 0x14 2. "vb10,Status field" "0,1"
newline
bitfld.long 0x14 1. "vb01,Status field" "0,1"
newline
bitfld.long 0x14 0. "vb00,Status field" "0,1"
line.long 0x18 "DSS_L3RAM_MEMINIT_START,"
bitfld.long 0x18 3. "l3ram3_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x18 2. "l3ram2_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x18 1. "l3ram1_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
newline
bitfld.long 0x18 0. "l3ram0_meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
line.long 0x1C "DSS_L3RAM_MEMINIT_STATUS,"
bitfld.long 0x1C 3. "l3ram3_meminit_status,Status field" "0,1"
newline
bitfld.long 0x1C 2. "l3ram2_meminit_status,Status field" "0,1"
newline
bitfld.long 0x1C 1. "l3ram1_meminit_status,Status field" "0,1"
newline
bitfld.long 0x1C 0. "l3ram0_meminit_status,Status field" "0,1"
line.long 0x20 "DSS_L3RAM_MEMINIT_DONE,"
bitfld.long 0x20 3. "l3ram3_meminit_done,Status field" "0,1"
newline
bitfld.long 0x20 2. "l3ram2_meminit_done,Status field" "0,1"
newline
bitfld.long 0x20 1. "l3ram1_meminit_done,Status field" "0,1"
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bitfld.long 0x20 0. "l3ram0_meminit_done,Status field" "0,1"
group.long 0xB0++0x33
line.long 0x00 "DSS_MAILBOX_MEMINIT_START,"
bitfld.long 0x00 0. "meminit_start,Start Memory intialization of TPCC A Param memory" "0,1"
line.long 0x04 "DSS_MAILBOX_MEMINIT_STATUS,"
bitfld.long 0x04 0. "meminit_status,Status field" "0,1"
line.long 0x08 "DSS_MAILBOX_MEMINIT_DONE,"
bitfld.long 0x08 0. "meminit_done,Status field" "0,1"
line.long 0x0C "DSS_TPCC_A_PARITY_CTRL,"
bitfld.long 0x0C 2. "parity_err_clr,Write 0x1 to clear the Parit Error status for TPCC" "0,1"
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bitfld.long 0x0C 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
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bitfld.long 0x0C 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x10 "DSS_TPCC_B_PARITY_CTRL,"
bitfld.long 0x10 2. "parity_err_clr,Write 0x1 to clear the Parit Error status for TPCC" "0,1"
newline
bitfld.long 0x10 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
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bitfld.long 0x10 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x14 "DSS_TPCC_C_PARITY_CTRL,"
bitfld.long 0x14 2. "parity_err_clr,Write 0x1 to clear the Parit Error status for TPCC" "0,1"
newline
bitfld.long 0x14 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
newline
bitfld.long 0x14 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x18 "DSS_TPCC_A_PARITY_STATUS,"
hexmask.long.byte 0x18 0.--7. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x1C "DSS_TPCC_B_PARITY_STATUS,"
hexmask.long.byte 0x1C 0.--7. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x20 "DSS_TPCC_C_PARITY_STATUS,"
hexmask.long.word 0x20 0.--8. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x24 "TPTC_DBS_CONFIG,"
bitfld.long 0x24 18.--19. "tptc_c5,Max Burst size tieoff value for TPTC C5" "0,1,2,3"
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bitfld.long 0x24 16.--17. "tptc_c4,Max Burst size tieoff value for TPTC C4" "0,1,2,3"
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bitfld.long 0x24 14.--15. "tptc_c3,Max Burst size tieoff value for TPTC C3" "0,1,2,3"
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bitfld.long 0x24 12.--13. "tptc_c2,Max Burst size tieoff value for TPTC C2" "0,1,2,3"
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bitfld.long 0x24 10.--11. "tptc_c1,Max Burst size tieoff value for TPTC C1" "0,1,2,3"
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bitfld.long 0x24 8.--9. "tptc_c0,Max Burst size tieoff value for TPTC C0" "0,1,2,3"
newline
bitfld.long 0x24 6.--7. "tptc_b1,Max Burst size tieoff value for TPTC B0" "0,1,2,3"
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bitfld.long 0x24 4.--5. "tptc_b0,Max Burst size tieoff value for TPTC B0" "0,1,2,3"
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bitfld.long 0x24 2.--3. "tptc_a1,Max Burst size tieoff value for TPTC A1" "0,1,2,3"
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bitfld.long 0x24 0.--1. "tptc_a0,Max Burst size tieoff value for TPTC A0" "0,1,2,3"
line.long 0x28 "DSS_DSP_BOOTCFG,"
bitfld.long 0x28 25. "L1P_CACHE_MODE,DSP Boot Configuration : L1P Cache Mode" "0,1"
newline
bitfld.long 0x28 24. "L1D_CACHE_MODE,DSP Boot Configuration : L1D Cache Mode" "0,1"
newline
hexmask.long.tbyte 0x28 0.--21. 1. "ISTP_RST_VAL,DSP Boot Configuration : Reset Vector"
line.long 0x2C "DSS_DSP_NMI_GATE,"
bitfld.long 0x2C 0.--2. "gate,Write 3'b111 to gate the Non Maskable Interrupt to the DSP" "0,1,2,3,4,5,6,7"
line.long 0x30 "DSS_PBIST_KEY_RESET,"
bitfld.long 0x30 4.--7. "dss_pbist_st_reset,DSS PBIST controller will be brought out of reset when value is 0xA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x30 0.--3. "dss_pbist_st_key,DSS PBIST Selftest Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0xEC++0x17
line.long 0x00 "DSS_TPTC_BOUNDARY_CFG0,"
bitfld.long 0x00 24.--29. "tptc_b1_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 16.--21. "tptc_b0_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--13. "tptc_a1_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--5. "tptc_a0_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DSS_TPTC_BOUNDARY_CFG1,"
bitfld.long 0x04 24.--29. "tptc_c3_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 16.--21. "tptc_c2_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 8.--13. "tptc_c1_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 0.--5. "tptc_c0_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DSS_TPTC_BOUNDARY_CFG2,"
bitfld.long 0x08 8.--13. "tptc_c5_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 0.--5. "tptc_c4_size,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DSS_TPTC_XID_REORDER_CFG0,"
bitfld.long 0x0C 24. "tptc_b1_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x0C 16. "tptc_b0_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x0C 8. "tptc_a1_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x0C 0. "tptc_a0_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
line.long 0x10 "DSS_TPTC_XID_REORDER_CFG1,"
bitfld.long 0x10 24. "tptc_c3_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x10 16. "tptc_c2_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x10 8. "tptc_c1_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x10 0. "tptc_c0_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
line.long 0x14 "DSS_TPTC_XID_REORDER_CFG2,"
bitfld.long 0x14 8. "tptc_c5_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
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bitfld.long 0x14 0. "tptc_c4_disable,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1"
group.long 0x108++0x0F
line.long 0x00 "ESM_GATING0,"
line.long 0x04 "ESM_GATING1,"
line.long 0x08 "ESM_GATING2,"
line.long 0x0C "ESM_GATING3,"
group.long 0x560++0x37
line.long 0x00 "DSS_PERIPH_ERRAGG_MASK0,"
bitfld.long 0x00 11. "rcss_ctrl_wr,Mask the Write error from RCSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 10. "rcss_ctrl_rd,Mask the Read error from RCSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 9. "rcss_rcm_wr,Mask the Write error from RCSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 8. "rcss_rcm_rd,Mask the Read error from RCSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 7. "dss_hwa_cfg_wr,Mask the Write error from DSS_HWA_CFG space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
newline
bitfld.long 0x00 6. "dss_hwa_cfg_rd,Mask the Read error from DSS_HWA_CFG space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
newline
bitfld.long 0x00 5. "dss_cm4_ctrl_wr,Mask the Write error from DSS_CM4_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 4. "dss_cm4_ctrl_rd,Mask the Read error from DSS_CM4_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 3. "dss_ctrl_wr,Mask the Write error from DSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 2. "dss_ctrl_rd,Mask the Read error from DSS_CTRL space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 1. "dss_rcm_wr,Mask the Write error from DSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
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bitfld.long 0x00 0. "dss_rcm_rd,Mask the Read error from DSS_RCM space from generating an error DSS_PERIPH_ERRAGG to the Processor" "0,1"
line.long 0x04 "DSS_PERIPH_ERRAGG_STATUS0,"
bitfld.long 0x04 11. "rcss_ctrl_wr,Status of the Write error from RCSS_CTRL space" "0,1"
newline
bitfld.long 0x04 10. "rcss_ctrl_rd,Status of the Read error from RCSS_CTRL space" "0,1"
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bitfld.long 0x04 9. "rcss_rcm_wr,Status of the Write error from RCSS_RCM space" "0,1"
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bitfld.long 0x04 8. "rcss_rcm_rd,Status of the Read error from RCSS_RCM space" "0,1"
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bitfld.long 0x04 7. "dss_hwa_cfg_wr,Status of the Write error from DSS_HWA_CFG space" "0,1"
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bitfld.long 0x04 6. "dss_hwa_cfg_rd,Status of the Read error from DSS_HWA_CFG space" "0,1"
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bitfld.long 0x04 5. "dss_cm4_ctrl_wr,Status of the Write error from DSS_CM4_CTRL space" "0,1"
newline
bitfld.long 0x04 4. "dss_cm4_ctrl_rd,Status of the Read error from DSS_CM4_CTRL space" "0,1"
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bitfld.long 0x04 3. "dss_ctrl_wr,Status of the Write error from DSS_CTRL space" "0,1"
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bitfld.long 0x04 2. "dss_ctrl_rd,Status of the Read error from DSS_CTRL space" "0,1"
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bitfld.long 0x04 1. "dss_rcm_wr,Status of the Write error from DSS_RCM space" "0,1"
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bitfld.long 0x04 0. "dss_rcm_rd,Status of the Read error from DSS_RCM space" "0,1"
line.long 0x08 "DSS_PERIPH_ERRAGG_STATUS_RAW0,"
bitfld.long 0x08 11. "rcss_ctrl_wr,Raw Status of the Write error from RCSS_CTRL space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 10. "rcss_ctrl_rd,Raw Status of the Read error from RCSS_CTRL space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 9. "rcss_rcm_wr,Raw Status of the Write error from RCSS_RCM space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 8. "rcss_rcm_rd,Raw Status of the Read error from RCSS_RCM space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 7. "dss_hwa_cfg_wr,Raw Status of the Write error from DSS_HWA_CFG space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 6. "dss_hwa_cfg_rd,Raw Status of the Read error from DSS_HWA_CFG space irrespective of it being masked" "0,1"
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bitfld.long 0x08 5. "dss_cm4_ctrl_wr,Raw Status of the Write error from DSS_CM4_CTRL space irrespective of it being masked" "0,1"
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bitfld.long 0x08 4. "dss_cm4_ctrl_rd,Raw Status of the Read error from DSS_CM4_CTRL space irrespective of it being masked" "0,1"
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bitfld.long 0x08 3. "dss_ctrl_wr,Raw Status of the Write error from DSS_CTRL space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 2. "dss_ctrl_rd,Raw Status of the Read error from DSS_CTRL space irrespective of it being masked" "0,1"
newline
bitfld.long 0x08 1. "dss_rcm_wr,Raw Status of the Write error from DSS_RCM space irrespective of it being masked" "0,1"
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bitfld.long 0x08 0. "dss_rcm_rd,Raw Status of the Read error from DSS_RCM space irrespective of it being masked" "0,1"
line.long 0x0C "DSS_DSP_MBOX_WRITE_DONE,"
bitfld.long 0x0C 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
newline
bitfld.long 0x0C 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
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bitfld.long 0x0C 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
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bitfld.long 0x0C 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
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bitfld.long 0x0C 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
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bitfld.long 0x0C 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
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bitfld.long 0x0C 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
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bitfld.long 0x0C 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0x10 "DSS_DSP_MBOX_READ_REQ,"
bitfld.long 0x10 28. "proc_7,This is request from processor 7 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 24. "proc_6,This is request from processor 6 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 20. "proc_5,This is request from processor 5 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 16. "proc_4,This is request from processor 4 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 12. "proc_3,This is request from processor 3 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 8. "proc_2,This is request from processor 2 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 4. "proc_1,This is request from processor 1 to DSS_DSP" "0,1"
newline
bitfld.long 0x10 0. "proc_0,This is request from processor 0 to DSS_DSP" "0,1"
line.long 0x14 "DSS_DSP_MBOX_READ_DONE,"
bitfld.long 0x14 28. "proc_7,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 7" "0,1"
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bitfld.long 0x14 24. "proc_6,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 6" "0,1"
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bitfld.long 0x14 20. "proc_5,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 5" "0,1"
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bitfld.long 0x14 16. "proc_4,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 4" "0,1"
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bitfld.long 0x14 12. "proc_3,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 3" "0,1"
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bitfld.long 0x14 8. "proc_2,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 2" "0,1"
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bitfld.long 0x14 4. "proc_1,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 1" "0,1"
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bitfld.long 0x14 0. "proc_0,This register should be written once finishing reading from DSS_DSP's mailbox written by proc 0" "0,1"
line.long 0x18 "DSS_WDT_EVENT_CAPTURE_SEL,"
hexmask.long.byte 0x18 8.--14. 1. "cap1,Select the DSS_WDT Capture Event 1 from the DSS DSP Interrupt Map"
newline
hexmask.long.byte 0x18 0.--6. 1. "cap0,Select the DSS_WDT Capture Event 0 from the DSS DSP Interrupt Map"
line.long 0x1C "DSS_RTIA_EVENT_CAPTURE_SEL,"
hexmask.long.byte 0x1C 8.--14. 1. "cap1,Select the DSS_RTIA Capture Event 1 from the DSS DSP Interrupt Map"
newline
hexmask.long.byte 0x1C 0.--6. 1. "cap0,Select the DSS_RTIA Capture Event 0 from the DSS DSP Interrupt Map"
line.long 0x20 "DSS_RTIB_EVENT_CAPTURE_SEL,"
hexmask.long.byte 0x20 8.--14. 1. "cap1,Select the DSS_RTIB Capture Event 1 from the DSS DSP Interrupt Map"
newline
hexmask.long.byte 0x20 0.--6. 1. "cap0,Select the DSS_RTIB Capture Event 0 from the DSS DSP Interrupt Map"
line.long 0x24 "DBG_ACK_CPU_CTRL,"
bitfld.long 0x24 0. "sel,Select the Processor Suspend that is used to Suspend the DSS Peripehrals" "DSP,MSS CR5"
line.long 0x28 "DBG_ACK_CTL0,"
bitfld.long 0x28 20.--22. "DSS_WDT,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 16.--18. "DSS_SCIA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 12.--14. "DSS_RTIB,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 8.--10. "DSS_RTIA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
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bitfld.long 0x28 4.--6. "DSS_DCCB,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x28 0.--2. "DSS_DCCA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x2C "DBG_ACK_CTL1,"
bitfld.long 0x2C 28.--30. "DSS_HWA,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x2C 24.--26. "DSS_MCRC,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x30 "DSS_DSP_INT_SEL,"
bitfld.long 0x30 0.--2. "RCSS_CSI2_ICSSM,DSS DSP Interrupt selcet" "CSI2 Interrupts are propagated to DSP,?,?,?,?,?,?,ICSSM Interrupts are propagted to DSP"
line.long 0x34 "DSS_CBUFF_TRIGGER_SEL,"
hexmask.long.byte 0x34 0.--6. 1. "sel,DSS CBUFF HW Trigger select from DSS DSP Interrupt Map"
group.long 0x800++0x17
line.long 0x00 "DSS_BUS_SAFETY_CTRL,"
bitfld.long 0x00 4.--6. "clk_disable,Option to clock gate the safety infrastructure is Safety is disabled" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x04 "DSS_BUS_SAFETY_SEC_ERR_STAT0,"
bitfld.long 0x04 28. "DSS_MDO_FIFO,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 27. "DSS_CBUFF_FIFO,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 26. "DSS_PCR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 25. "DSS_TPTC_C5_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 24. "DSS_TPTC_C4_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 23. "DSS_TPTC_C3_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 22. "DSS_TPTC_C2_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 21. "DSS_TPTC_C1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 20. "DSS_TPTC_C0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 19. "DSS_TPTC_B1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 18. "DSS_TPTC_B0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 17. "DSS_TPTC_A1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 16. "DSS_TPTC_A0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 15. "DSS_TPTC_C5_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 14. "DSS_TPTC_C4_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 13. "DSS_TPTC_C3_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 12. "DSS_TPTC_C2_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 11. "DSS_TPTC_C1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 10. "DSS_TPTC_C0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 9. "DSS_TPTC_B1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 8. "DSS_TPTC_B0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 7. "DSS_TPTC_A1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 6. "DSS_TPTC_A0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 5. "DSS_DSP_SDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 4. "DSS_L3_BANKD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 3. "DSS_L3_BANKC,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 2. "DSS_L3_BANKB,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 1. "DSS_L3_BANKA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0. "DSS_DSP_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x08 "DSS_BUS_SAFETY_SEC_ERR_STAT1,"
bitfld.long 0x08 5. "DSS_MBOX,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 4. "DSS_CM4_S,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 3. "DSS_CM4_M,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 2. "DSS_HWA_DMA1,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 1. "DSS_HWA_DMA0,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 0. "DSS_MCRC,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x0C "DSS_DSP_MDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x0C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x0C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x0C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x10 "DSS_DSP_MDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x10 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x14 "DSS_DSP_MDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x14 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x820++0x1B
line.long 0x00 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKA_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x844++0x1B
line.long 0x00 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKB_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKB_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x868++0x1B
line.long 0x00 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKC_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x88C++0x1B
line.long 0x00 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_L3_BANKD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_L3_BANKD_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_L3_BANKD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x8B0++0x277
line.long 0x00 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x04 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x08 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x0C "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x10 "DSS_DSP_SDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x10 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSS_DSP_SDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x14 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x18 "DSS_DSP_SDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x18 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1C "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x20 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x24 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x28 "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x2C "DSS_DSP_SDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x30 "DSS_TPTC_A0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x30 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x30 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x30 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x34 "DSS_TPTC_A0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x34 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x34 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x34 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x34 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x34 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x38 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x38 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x38 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x38 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x38 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3C "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x40 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x44 "DSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x48 "DSS_TPTC_A1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x48 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x48 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x48 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4C "DSS_TPTC_A1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x4C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x50 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x50 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x50 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x50 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x50 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x54 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x54 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x54 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x54 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x54 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x58 "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x5C "DSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x60 "DSS_TPTC_B0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x60 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x60 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x60 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x64 "DSS_TPTC_B0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x64 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x64 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x68 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x68 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x6C "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x6C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x70 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x74 "DSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x78 "DSS_TPTC_B1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x78 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x78 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x78 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x7C "DSS_TPTC_B1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x7C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x7C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x7C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x7C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x7C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x80 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x80 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x80 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x80 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x80 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x84 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x84 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x88 "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x8C "DSS_TPTC_B1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x90 "DSS_TPTC_C0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x90 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x90 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x90 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x94 "DSS_TPTC_C0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x94 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x94 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x94 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x94 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x94 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x98 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x98 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x98 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x98 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x98 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x9C "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x9C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x9C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x9C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x9C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xA0 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xA4 "DSS_TPTC_C0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xA8 "DSS_TPTC_C1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xA8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xAC "DSS_TPTC_C1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xAC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xAC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xAC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xB0 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xB0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB4 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xB4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xB4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB8 "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xBC "DSS_TPTC_C1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xC0 "DSS_TPTC_C2_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xC0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xC4 "DSS_TPTC_C2_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xC4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xC8 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xC8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xCC "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xCC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xD0 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xD4 "DSS_TPTC_C2_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xD8 "DSS_TPTC_C3_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xD8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xD8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xD8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xDC "DSS_TPTC_C3_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xDC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xDC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xDC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xDC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xDC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xE0 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xE0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xE4 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xE4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xE4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xE8 "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xEC "DSS_TPTC_C3_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xF0 "DSS_TPTC_C4_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xF0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xF0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xF4 "DSS_TPTC_C4_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0xF4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xF4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xF4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xF8 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0xF8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xF8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xFC "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xFC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xFC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xFC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xFC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x100 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x104 "DSS_TPTC_C4_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x108 "DSS_TPTC_C5_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x108 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x108 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x108 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x10C "DSS_TPTC_C5_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x10C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x10C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x10C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x10C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x110 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x110 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x110 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x110 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x110 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x114 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x114 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x114 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x114 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x114 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x118 "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x11C "DSS_TPTC_C5_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x120 "DSS_TPTC_A0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x120 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x120 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x120 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x124 "DSS_TPTC_A0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x124 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x124 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x124 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x124 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x124 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x128 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x128 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x128 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x128 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x128 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x12C "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x12C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x12C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x12C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x12C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x130 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x134 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x138 "DSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x13C "DSS_TPTC_A1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x13C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x13C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x13C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x140 "DSS_TPTC_A1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x140 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x140 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x140 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x140 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x140 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x144 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x144 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x144 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x144 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x144 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x148 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x148 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x148 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x148 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x148 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x14C "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x150 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x154 "DSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x158 "DSS_TPTC_B0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x158 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x158 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x158 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x15C "DSS_TPTC_B0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x15C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x15C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x15C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x15C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x15C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x160 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x160 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x160 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x160 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x160 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x164 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x164 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x164 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x164 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x164 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x168 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x16C "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x170 "DSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x174 "DSS_TPTC_B1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x174 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x174 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x174 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x178 "DSS_TPTC_B1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x178 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x178 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x178 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x178 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x178 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x17C "DSS_TPTC_B1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x17C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x17C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x17C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x17C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x180 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x180 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x180 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x180 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x180 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x184 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x188 "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x18C "DSS_TPTC_B1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x190 "DSS_TPTC_C0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x190 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x190 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x190 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x194 "DSS_TPTC_C0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x194 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x194 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x194 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x194 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x194 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x198 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x198 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x198 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x198 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x198 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x19C "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x19C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x19C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x19C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x19C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1A0 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1A4 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1A8 "DSS_TPTC_C0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1AC "DSS_TPTC_C1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1AC 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1AC 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1AC 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "DSS_TPTC_C1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1B0 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B0 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B0 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1B0 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1B4 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1B4 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B8 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1B8 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1BC "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1C0 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1C4 "DSS_TPTC_C1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1C8 "DSS_TPTC_C2_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1C8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1CC "DSS_TPTC_C2_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1CC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1CC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1CC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1CC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1CC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1D0 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1D0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1D4 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1D4 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D4 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1D8 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1DC "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1E0 "DSS_TPTC_C2_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1E4 "DSS_TPTC_C3_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1E4 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E4 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1E8 "DSS_TPTC_C3_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1E8 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E8 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E8 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1EC "DSS_TPTC_C3_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1EC 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1F0 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1F0 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F0 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1F4 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1F8 "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1FC "DSS_TPTC_C3_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x200 "DSS_TPTC_C4_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x200 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x200 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x200 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x204 "DSS_TPTC_C4_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x204 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x204 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x208 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x208 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x20C "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x20C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x210 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x214 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x218 "DSS_TPTC_C4_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x21C "DSS_TPTC_C5_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x21C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x21C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x21C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x220 "DSS_TPTC_C5_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x220 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x220 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x220 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x220 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x224 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x224 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x228 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x228 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x22C "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x230 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x234 "DSS_TPTC_C5_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x238 "DSS_MDO_FIFO_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x238 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x238 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x238 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x23C "DSS_MDO_FIFO_BUS_SAFETY_FI,"
hexmask.long.byte 0x23C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x23C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x23C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x23C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x23C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x240 "DSS_MDO_FIFO_BUS_SAFETY_ERR,"
hexmask.long.byte 0x240 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x240 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x240 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x240 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x244 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x244 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x244 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x244 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x244 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x248 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x24C "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x250 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x254 "DSS_MDO_FIFO_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x258 "DSS_CBUFF_FIFO_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x258 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x258 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x258 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x25C "DSS_CBUFF_FIFO_BUS_SAFETY_FI,"
hexmask.long.byte 0x25C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x25C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x25C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x25C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x25C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x260 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR,"
hexmask.long.byte 0x260 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x260 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x260 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x260 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x264 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x264 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x264 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x264 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x264 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x268 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x26C "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x270 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x274 "DSS_CBUFF_FIFO_BUS_SAFETY_ERR_STAT_WRITERESP,"
group.long 0xBC8++0xDF
line.long 0x00 "DSS_MCRC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x00 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x00 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x00 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x04 "DSS_MCRC_BUS_SAFETY_FI,"
hexmask.long.byte 0x04 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x04 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x08 "DSS_MCRC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x08 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x0C "DSS_MCRC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x0C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x10 "DSS_MCRC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x14 "DSS_MCRC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x18 "DSS_MCRC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1C "DSS_MCRC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x20 "DSS_PCR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x20 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x20 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x20 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x24 "DSS_PCR_BUS_SAFETY_FI,"
hexmask.long.byte 0x24 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x24 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x28 "DSS_PCR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x28 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2C "DSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x30 "DSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x34 "DSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x38 "DSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3C "DSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x40 "DSS_HWA_DMA0_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x40 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x40 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x40 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x44 "DSS_HWA_DMA0_BUS_SAFETY_FI,"
hexmask.long.byte 0x44 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x44 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x48 "DSS_HWA_DMA0_BUS_SAFETY_ERR,"
hexmask.long.byte 0x48 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4C "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x50 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x54 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x58 "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x5C "DSS_HWA_DMA0_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x60 "DSS_HWA_DMA1_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x60 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x60 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x60 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x64 "DSS_HWA_DMA1_BUS_SAFETY_FI,"
hexmask.long.byte 0x64 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x64 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x68 "DSS_HWA_DMA1_BUS_SAFETY_ERR,"
hexmask.long.byte 0x68 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x6C "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x6C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x70 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x74 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x78 "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x7C "DSS_HWA_DMA1_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x80 "DSS_CM4_M_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x80 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x80 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x80 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x84 "DSS_CM4_M_BUS_SAFETY_FI,"
hexmask.long.byte 0x84 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x84 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x88 "DSS_CM4_M_BUS_SAFETY_ERR,"
hexmask.long.byte 0x88 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x8C "DSS_CM4_M_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x8C 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x90 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x94 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x98 "DSS_CM4_M_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x9C "DSS_CM4_M_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xA0 "DSS_CM4_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xA0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xA4 "DSS_CM4_S_BUS_SAFETY_FI,"
hexmask.long.byte 0xA4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xA8 "DSS_CM4_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0xA8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xAC "DSS_CM4_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xAC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB0 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xB4 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0xB8 "DSS_CM4_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xBC "DSS_CM4_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xC0 "DSS_MBOX_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xC0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xC4 "DSS_MBOX_BUS_SAFETY_FI,"
hexmask.long.byte 0xC4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xC4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xC4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xC8 "DSS_MBOX_BUS_SAFETY_ERR,"
hexmask.long.byte 0xC8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xC8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xCC "DSS_MBOX_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xCC 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xCC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xD0 "DSS_MBOX_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xD4 "DSS_MBOX_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0xD8 "DSS_MBOX_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xDC "DSS_MBOX_BUS_SAFETY_ERR_STAT_WRITERESP,"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x8A8)++0x03
line.long 0x00 "DSS_L3_BANKD_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x884)++0x03
line.long 0x00 "DSS_L3_BANKC_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x860)++0x03
line.long 0x00 "DSS_L3_BANKB_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x83C)++0x03
line.long 0x00 "DSS_L3_BANKA_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x818)++0x03
line.long 0x00 "DSS_DSP_MDMA_BUS_SAFETY_ERR_STAT_DATA$1,"
hexmask.long.byte 0x00 24.--31. 1. "d3,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 16.--23. 1. "d2,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
group.long ($2+0xE4)++0x03
line.long 0x00 "DSS_PBIST_REG$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x70)++0x03
line.long 0x00 "DSS_DSP_L2RAM_PARITY_ERR_STATUS_VB$1,"
hexmask.long.word 0x00 16.--27. 1. "addr1,Error address 1 for Virtual Bank 0"
hexmask.long.word 0x00 0.--11. 1. "addr0,Error address 0 for Virtual Bank 0"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_DCCA (DSS DCCA Module Registers)"
base ad:0x6F79C00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "DSS_DCCB (DSS DCCB Module Registers)"
base ad:0x6F79D00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "DSS_DSP_PBIST (DSS DSP PBIST Module Registers)"
base ad:0x6F79000
hgroup.long 0x120++0x07
hide.long 0x00 "PBIST_DD10,DD0 Data Register 16 (D0)"
hide.long 0x04 "PBIST_DE10,DE0 Data Register 16 (D0)"
group.long 0x160++0x03
line.long 0x00 "PBIST_RAMT,RAM Configuration (RAMT -RAM)"
hexmask.long.byte 0x00 24.--31. 1. "RGS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 16.--23. 1. "RDS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 8.--15. 1. "DWR,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 0.--7. 1. "RAM,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
group.word 0x164++0x01
line.word 0x00 "PBIST_DLR,Datalogger 0"
hexmask.word.byte 0x00 8.--15. 1. "DLR1,Datalogger Register [8] : Reserevd [9] : Default Testing Mode"
hexmask.word.byte 0x00 0.--7. 1. "DLR0,Datalogger Register [1:0] : Reserved [2] : ROM-based testing mode"
group.byte 0x168++0x00
line.byte 0x00 "PBIST_CMS,Clock mux select"
bitfld.byte 0x00 0.--3. "PBIST_CMS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x16C++0x00
line.byte 0x00 "PBIST_PC,Program Control"
bitfld.byte 0x00 0.--4. "PBIST_PC,TI Internal Register.Reserved for HW RnD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x178++0x03
line.long 0x00 "PBIST_CS,Chip Select 0"
hexmask.long.byte 0x00 24.--31. 1. "CS3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "CS2,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 8.--15. 1. "CS1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "CS0,TI Internal Register.Reserved for HW RnD"
group.byte 0x17C++0x00
line.byte 0x00 "PBIST_FDLY,Fail Delay"
group.byte 0x180++0x00
line.byte 0x00 "PBIST_PACT,Pbist Active"
bitfld.byte 0x00 0. "PBIST_PACT,Pbist Active/ROM Clock Enable Register [0]: This bit must be set to turn on internal PBIST clocks" "Disable internal PBIST clocks Value,Enable internal PBIST clocks"
group.byte 0x184++0x00
line.byte 0x00 "PBIST_ID,PBIST ID"
bitfld.byte 0x00 0.--4. "PBIST_ID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hgroup.long 0x188++0x03
hide.long 0x00 "PBIST_OVR,PBIST Overrides"
rgroup.byte 0x190++0x00
line.byte 0x00 "PBIST_FSFR0,Fail status fail - port 0"
bitfld.byte 0x00 0. "PBIST_FSFR0,Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x194++0x00
line.byte 0x00 "PBIST_FSFR1,Fail status fail - port 1"
bitfld.byte 0x00 0. "PBIST_FSFR1,Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x198++0x00
line.byte 0x00 "PBIST_FSRCR0,Fail Count fail - port 0"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR0,Fail Status Count - Port 0 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x19C++0x00
line.byte 0x00 "PBIST_FSRCR1,Fail Count fail - port 1"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR1,Fail Status Count - Port 1 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1A0++0x03
hide.long 0x00 "PBIST_FSRA0,Fail status address - port 0"
rgroup.word 0x1A4++0x01
line.word 0x00 "PBIST_FSRA1,Fail status address - port 1"
hgroup.long 0x1B4++0x0B
hide.long 0x00 "PBIST_MARGIN,Margin Mode"
hide.long 0x04 "PBIST_WRENZ,WRENZ"
hide.long 0x08 "PBIST_PGS,PAGE/PGS"
group.byte 0x1C0++0x00
line.byte 0x00 "PBIST_ROM,Rom Mask"
bitfld.byte 0x00 0.--1. "PBIST_ROM,Rom Mask" "No information is used from ROM Value,Only RAM Group information from ROM Vaule,Only Algorithm information from ROM Value,Both Algorithm and RAM information from ROM"
group.long 0x1C4++0x0B
line.long 0x00 "PBIST_ALGO,ROM Algorithm Mask 0"
hexmask.long.byte 0x00 24.--31. 1. "ALGO3,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 16.--23. 1. "ALGO2,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 8.--15. 1. "ALGO1,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 0.--7. 1. "ALGO0,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
line.long 0x04 "PBIST_RINFOL,RAM Info Mask Lower 0"
hexmask.long.byte 0x04 24.--31. 1. "RINFOL3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 16.--23. 1. "RINFOL2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 8.--15. 1. "RINFOL1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 0.--7. 1. "RINFOL0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
line.long 0x08 "PBIST_RINFOU,RAM Info Mask Upper 0"
hexmask.long.byte 0x08 24.--31. 1. "RINFOU3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 16.--23. 1. "RINFOU2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 8.--15. 1. "RINFOU1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 0.--7. 1. "RINFOU0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
repeat 2. (list 0. 1. )(list 0x00 0x08 )
rgroup.long ($2+0x1A8)++0x03
line.long 0x00 "PBIST_FSRDL$1,Fail status Data - port 0"
repeat.end
repeat 2. (list 1. 4. )(list 0x00 0x04 )
group.long ($2+0x170)++0x03
line.long 0x00 "PBIST_SCR$1,Address Scramble 0 -3"
hexmask.long.byte 0x00 24.--31. 1. "SCR3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "SCR2,TI Internal Register.Reserved for HW RnD"
newline
hexmask.long.byte 0x00 8.--15. 1. "SCR1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "SCR0,TI Internal Register.Reserved for HW RnD"
repeat.end
repeat 2. (list 2. 3. )(list 0x00 0x04 )
group.word ($2+0x158)++0x01
line.word 0x00 "PBIST_CI$1,Constant Increment Register2"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
hgroup.long ($2+0x150)++0x03
hide.long 0x00 "PBIST_CI$1,Constant Increment Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x140)++0x03
hide.long 0x00 "PBIST_CL$1,Constant Loop Count Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x130)++0x03
hide.long 0x00 "PBIST_CA$1,Constant Address Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x110)++0x03
hide.long 0x00 "PBIST_L$1,Variable Loop Count Register L0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x100)++0x03
hide.long 0x00 "PBIST_A$1,Variable Address Register0"
repeat.end
width 0x0B
tree.end
tree "DSS_DSP_STC (DSS DSP STC Module Registers)"
base ad:0x6F79200
group.long 0x00++0x11B
line.long 0x00 "STCGCR0,Self test Global control Reg0"
hexmask.long.word 0x00 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run"
newline
rbitfld.long 0x00 11.--15. "NU0,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval" "Continue NSTC run from previous interval,Restart NSTC run from ROM address 0 1X = Start..,?..."
line.long 0x04 "STCGCR1,Self test Global control Reg1"
hexmask.long.tbyte 0x04 12.--31. 1. "NU2,Reserved bits"
newline
bitfld.long 0x04 8.--11. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x04 7. "NU3,Reserved bits" "0,1"
newline
bitfld.long 0x04 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode" "XOR mode,Spread mode"
newline
bitfld.long 0x04 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration" "Operates in Normal Scan Mode,Operates in Low Power Scan Mode"
newline
bitfld.long 0x04 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
newline
bitfld.long 0x04 0.--3. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "STCTPR,Time out counter preload register"
line.long 0x0C "STC_CADDR,Current Address register for CORE1"
line.long 0x10 "STCCICR,Current Interval count register"
hexmask.long.word 0x10 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well"
newline
hexmask.long.word 0x10 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run"
line.long 0x14 "STCGSTAT,Global Status Register"
hexmask.long.tbyte 0x14 12.--31. 1. "NU4,Reserved bits"
newline
bitfld.long 0x14 8.--11. "ST_ACTIVE,Tells whether self test is currently active or not" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 2.--7. "NU5,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)" "Self test run has not failed,SelfTest run has failed"
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bitfld.long 0x14 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)" "Not completed,SelfTest run Completed"
line.long 0x18 "STCFSTAT,Fail Status Register"
hexmask.long 0x18 5.--31. 1. "NU6,Reserved bits"
newline
bitfld.long 0x18 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur" "Failure on Segment 0,Failure on Segment 1,Failure on Segment 2,Failure on Segment 3"
newline
bitfld.long 0x18 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)" "No time out error occurred,SelfTest run failed due to a timeout error"
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bitfld.long 0x18 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)" "No MISR mismatch for CORE2,Self test run failed due to MISR mismatch for.."
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bitfld.long 0x18 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments" "No MISR mismatch for CORE1,Self test run failed due to MISR mismatch for.."
line.long 0x1C "STCSCSCR,Signature compare Self Check Register"
hexmask.long 0x1C 5.--31. 1. "NU7,Reserved bits"
newline
bitfld.long 0x1C 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)" "No fault insertion,Inserts fault in the logic unedr test which will.."
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bitfld.long 0x1C 0.--3. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "STC_CADDR2,Current Address register for CORE2"
line.long 0x24 "STC_CLKDIV,Clock Divider Register"
rbitfld.long 0x24 27.--31. "NU8,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 19.--23. "NU9,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x24 11.--15. "NU10,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 3.--7. "NU11,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
line.long 0x28 "STC_SEGPLR,Segment 1st interval Preload Register"
hexmask.long 0x28 2.--31. 1. "NU12,Reserved bits"
newline
bitfld.long 0x28 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter" "Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of.."
line.long 0x2C "SEG0_START_ADDR,ROM Start address for Segment0"
hexmask.long.word 0x2C 20.--31. 1. "NU13,Reserved bits"
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hexmask.long.tbyte 0x2C 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x30 "SEG1_START_ADDR,ROM Start address for Segment1"
hexmask.long.word 0x30 20.--31. 1. "NU14,Reserved bits"
newline
hexmask.long.tbyte 0x30 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x34 "SEG2_START_ADDR,ROM Start address for Segment2"
hexmask.long.word 0x34 20.--31. 1. "NU15,Reserved bits"
newline
hexmask.long.tbyte 0x34 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x38 "SEG3_START_ADDR,ROM Start address for Segment3"
hexmask.long.word 0x38 20.--31. 1. "NU16,Reserved bits"
newline
hexmask.long.tbyte 0x38 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x3C "CORE1_CURMISR_0,Holds the MISR signature for CORE1"
line.long 0x40 "CORE1_CURMISR_1,Holds the MISR signature for CORE1"
line.long 0x44 "CORE1_CURMISR_2,Holds the MISR signature for CORE1"
line.long 0x48 "CORE1_CURMISR_3,Holds the MISR signature for CORE1"
line.long 0x4C "CORE1_CURMISR_4,Holds the MISR signature for CORE1"
line.long 0x50 "CORE1_CURMISR_5,Holds the MISR signature for CORE1"
line.long 0x54 "CORE1_CURMISR_6,Holds the MISR signature for CORE1"
line.long 0x58 "CORE1_CURMISR_7,Holds the MISR signature for CORE1"
line.long 0x5C "CORE1_CURMISR_8,Holds the MISR signature for CORE1"
line.long 0x60 "CORE1_CURMISR_9,Holds the MISR signature for CORE1"
line.long 0x64 "CORE1_CURMISR_10,Holds the MISR signature for CORE1"
line.long 0x68 "CORE1_CURMISR_11,Holds the MISR signature for CORE1"
line.long 0x6C "CORE1_CURMISR_12,Holds the MISR signature for CORE1"
line.long 0x70 "CORE1_CURMISR_13,Holds the MISR signature for CORE1"
line.long 0x74 "CORE1_CURMISR_14,Holds the MISR signature for CORE1"
line.long 0x78 "CORE1_CURMISR_15,Holds the MISR signature for CORE1"
line.long 0x7C "CORE1_CURMISR_16,Holds the MISR signature for CORE1"
line.long 0x80 "CORE1_CURMISR_17,Holds the MISR signature for CORE1"
line.long 0x84 "CORE1_CURMISR_18,Holds the MISR signature for CORE1"
line.long 0x88 "CORE1_CURMISR_19,Holds the MISR signature for CORE1"
line.long 0x8C "CORE1_CURMISR_20,Holds the MISR signature for CORE1"
line.long 0x90 "CORE1_CURMISR_21,Holds the MISR signature for CORE1"
line.long 0x94 "CORE1_CURMISR_22,Holds the MISR signature for CORE1"
line.long 0x98 "CORE1_CURMISR_23,Holds the MISR signature for CORE1"
line.long 0x9C "CORE1_CURMISR_24,Holds the MISR signature for CORE1"
line.long 0xA0 "CORE1_CURMISR_25,Holds the MISR signature for CORE1"
line.long 0xA4 "CORE1_CURMISR_26,Holds the MISR signature for CORE1"
line.long 0xA8 "CORE1_CURMISR_27,Holds the MISR signature for CORE1"
line.long 0xAC "CORE2_CURMISR_0,Holds the MISR signature for CORE2"
line.long 0xB0 "CORE2_CURMISR_1,Holds the MISR signature for CORE2"
line.long 0xB4 "CORE2_CURMISR_2,Holds the MISR signature for CORE2"
line.long 0xB8 "CORE2_CURMISR_3,Holds the MISR signature for CORE2"
line.long 0xBC "CORE2_CURMISR_4,Holds the MISR signature for CORE2"
line.long 0xC0 "CORE2_CURMISR_5,Holds the MISR signature for CORE2"
line.long 0xC4 "CORE2_CURMISR_6,Holds the MISR signature for CORE2"
line.long 0xC8 "CORE2_CURMISR_7,Holds the MISR signature for CORE2"
line.long 0xCC "CORE2_CURMISR_8,Holds the MISR signature for CORE2"
line.long 0xD0 "CORE2_CURMISR_9,Holds the MISR signature for CORE2"
line.long 0xD4 "CORE2_CURMISR_10,Holds the MISR signature for CORE2"
line.long 0xD8 "CORE2_CURMISR_11,Holds the MISR signature for CORE2"
line.long 0xDC "CORE2_CURMISR_12,Holds the MISR signature for CORE2"
line.long 0xE0 "CORE2_CURMISR_13,Holds the MISR signature for CORE2"
line.long 0xE4 "CORE2_CURMISR_14,Holds the MISR signature for CORE2"
line.long 0xE8 "CORE2_CURMISR_15,Holds the MISR signature for CORE2"
line.long 0xEC "CORE2_CURMISR_16,Holds the MISR signature for CORE2"
line.long 0xF0 "CORE2_CURMISR_17,Holds the MISR signature for CORE2"
line.long 0xF4 "CORE2_CURMISR_18,Holds the MISR signature for CORE2"
line.long 0xF8 "CORE2_CURMISR_19,Holds the MISR signature for CORE2"
line.long 0xFC "CORE2_CURMISR_20,Holds the MISR signature for CORE2"
line.long 0x100 "CORE2_CURMISR_21,Holds the MISR signature for CORE2"
line.long 0x104 "CORE2_CURMISR_22,Holds the MISR signature for CORE2"
line.long 0x108 "CORE2_CURMISR_23,Holds the MISR signature for CORE2"
line.long 0x10C "CORE2_CURMISR_24,Holds the MISR signature for CORE2"
line.long 0x110 "CORE2_CURMISR_25,Holds the MISR signature for CORE2"
line.long 0x114 "CORE2_CURMISR_26,Holds the MISR signature for CORE2"
line.long 0x118 "CORE2_CURMISR_27,Holds the MISR signature for CORE2"
width 0x0B
tree.end
tree "DSS_ECC_AGG (DSS ECC AGG Module Registers)"
base ad:0x60A0000
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 22. "RCSS_TPTC_B1_PEND,Interrupt Pending Status for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x04 21. "RCSS_TPTC_B0_PEND,Interrupt Pending Status for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x04 20. "RCSS_TPTC_A1_PEND,Interrupt Pending Status for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x04 19. "RCSS_TPTC_A0_PEND,Interrupt Pending Status for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x04 18. "DSS_TPTC_C5_PEND,Interrupt Pending Status for dss_tptc_c5_pend" "0,1"
bitfld.long 0x04 17. "DSS_TPTC_C4_PEND,Interrupt Pending Status for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x04 16. "DSS_TPTC_C3_PEND,Interrupt Pending Status for dss_tptc_c3_pend" "0,1"
bitfld.long 0x04 15. "DSS_TPTC_C2_PEND,Interrupt Pending Status for dss_tptc_c2_pend" "0,1"
bitfld.long 0x04 14. "DSS_TPTC_C1_PEND,Interrupt Pending Status for dss_tptc_c1_pend" "0,1"
bitfld.long 0x04 13. "DSS_TPTC_C0_PEND,Interrupt Pending Status for dss_tptc_c0_pend" "0,1"
bitfld.long 0x04 12. "DSS_TPTC_B1_PEND,Interrupt Pending Status for dss_tptc_b1_pend" "0,1"
bitfld.long 0x04 11. "DSS_TPTC_B0_PEND,Interrupt Pending Status for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x04 10. "DSS_TPTC_A1_PEND,Interrupt Pending Status for dss_tptc_a1_pend" "0,1"
bitfld.long 0x04 9. "DSS_TPTC_A0_PEND,Interrupt Pending Status for dss_tptc_a0_pend" "0,1"
bitfld.long 0x04 8. "HWACM4_MAILBOX_PEND,Interrupt Pending Status for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x04 7. "HWACM4_RAM_B2_PEND,Interrupt Pending Status for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x04 6. "HWACM4_RAM_B1_PEND,Interrupt Pending Status for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x04 5. "HWACM4_RAM_B0_PEND,Interrupt Pending Status for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x04 4. "DSS_MAILBOX_PEND,Interrupt Pending Status for dss_mailbox_pend" "0,1"
bitfld.long 0x04 3. "DSS_L3RAM3_PEND,Interrupt Pending Status for dss_l3ram3_pend" "0,1"
bitfld.long 0x04 2. "DSS_L3RAM2_PEND,Interrupt Pending Status for dss_l3ram2_pend" "0,1"
bitfld.long 0x04 1. "DSS_L3RAM1_PEND,Interrupt Pending Status for dss_l3ram1_pend" "0,1"
bitfld.long 0x04 0. "DSS_L3RAM0_PEND,Interrupt Pending Status for dss_l3ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 22. "RCSS_TPTC_B1_PEND,Interrupt Pending Status for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x04 21. "RCSS_TPTC_B0_PEND,Interrupt Pending Status for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x04 20. "RCSS_TPTC_A1_PEND,Interrupt Pending Status for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x04 19. "RCSS_TPTC_A0_PEND,Interrupt Pending Status for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x04 18. "DSS_TPTC_C5_PEND,Interrupt Pending Status for dss_tptc_c5_pend" "0,1"
bitfld.long 0x04 17. "DSS_TPTC_C4_PEND,Interrupt Pending Status for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x04 16. "DSS_TPTC_C3_PEND,Interrupt Pending Status for dss_tptc_c3_pend" "0,1"
bitfld.long 0x04 15. "DSS_TPTC_C2_PEND,Interrupt Pending Status for dss_tptc_c2_pend" "0,1"
bitfld.long 0x04 14. "DSS_TPTC_C1_PEND,Interrupt Pending Status for dss_tptc_c1_pend" "0,1"
bitfld.long 0x04 13. "DSS_TPTC_C0_PEND,Interrupt Pending Status for dss_tptc_c0_pend" "0,1"
bitfld.long 0x04 12. "DSS_TPTC_B1_PEND,Interrupt Pending Status for dss_tptc_b1_pend" "0,1"
bitfld.long 0x04 11. "DSS_TPTC_B0_PEND,Interrupt Pending Status for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x04 10. "DSS_TPTC_A1_PEND,Interrupt Pending Status for dss_tptc_a1_pend" "0,1"
bitfld.long 0x04 9. "DSS_TPTC_A0_PEND,Interrupt Pending Status for dss_tptc_a0_pend" "0,1"
bitfld.long 0x04 8. "HWACM4_MAILBOX_PEND,Interrupt Pending Status for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x04 7. "HWACM4_RAM_B2_PEND,Interrupt Pending Status for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x04 6. "HWACM4_RAM_B1_PEND,Interrupt Pending Status for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x04 5. "HWACM4_RAM_B0_PEND,Interrupt Pending Status for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x04 4. "DSS_MAILBOX_PEND,Interrupt Pending Status for dss_mailbox_pend" "0,1"
bitfld.long 0x04 3. "DSS_L3RAM3_PEND,Interrupt Pending Status for dss_l3ram3_pend" "0,1"
bitfld.long 0x04 2. "DSS_L3RAM2_PEND,Interrupt Pending Status for dss_l3ram2_pend" "0,1"
bitfld.long 0x04 1. "DSS_L3RAM1_PEND,Interrupt Pending Status for dss_l3ram1_pend" "0,1"
bitfld.long 0x04 0. "DSS_L3RAM0_PEND,Interrupt Pending Status for dss_l3ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_SET,Interrupt Enable Set Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_SET,Interrupt Enable Set Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_SET,Interrupt Enable Set Register for dss_l3ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 22. "RCSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b1_pend" "0,1"
bitfld.long 0x00 21. "RCSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_b0_pend" "0,1"
bitfld.long 0x00 20. "RCSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a1_pend" "0,1"
bitfld.long 0x00 19. "RCSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for rcss_tptc_a0_pend" "0,1"
bitfld.long 0x00 18. "DSS_TPTC_C5_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c5_pend" "0,1"
bitfld.long 0x00 17. "DSS_TPTC_C4_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c4_pend" "0,1"
newline
bitfld.long 0x00 16. "DSS_TPTC_C3_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c3_pend" "0,1"
bitfld.long 0x00 15. "DSS_TPTC_C2_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c2_pend" "0,1"
bitfld.long 0x00 14. "DSS_TPTC_C1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c1_pend" "0,1"
bitfld.long 0x00 13. "DSS_TPTC_C0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_c0_pend" "0,1"
bitfld.long 0x00 12. "DSS_TPTC_B1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b1_pend" "0,1"
bitfld.long 0x00 11. "DSS_TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_b0_pend" "0,1"
newline
bitfld.long 0x00 10. "DSS_TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a1_pend" "0,1"
bitfld.long 0x00 9. "DSS_TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for dss_tptc_a0_pend" "0,1"
bitfld.long 0x00 8. "HWACM4_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_mailbox_pend" "0,1"
bitfld.long 0x00 7. "HWACM4_RAM_B2_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b2_pend" "0,1"
bitfld.long 0x00 6. "HWACM4_RAM_B1_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b1_pend" "0,1"
bitfld.long 0x00 5. "HWACM4_RAM_B0_ENABLE_CLR,Interrupt Enable Clear Register for hwacm4_ram_b0_pend" "0,1"
newline
bitfld.long 0x00 4. "DSS_MAILBOX_ENABLE_CLR,Interrupt Enable Clear Register for dss_mailbox_pend" "0,1"
bitfld.long 0x00 3. "DSS_L3RAM3_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram3_pend" "0,1"
bitfld.long 0x00 2. "DSS_L3RAM2_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram2_pend" "0,1"
bitfld.long 0x00 1. "DSS_L3RAM1_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram1_pend" "0,1"
bitfld.long 0x00 0. "DSS_L3RAM0_ENABLE_CLR,Interrupt Enable Clear Register for dss_l3ram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "DSS_ESM (DSS ESM Module Registers)"
base ad:0x6F7D000
group.long 0x00++0x5B
line.long 0x00 "ESMIEPSR1,ESM Enable ERROR Pin Action/Response Register 1"
line.long 0x04 "ESMIEPCR1,ESM Disable ERROR Pin Action/Response Register 1"
line.long 0x08 "ESMIESR1,ESM Interrupt Enable Set/Status Register 1"
line.long 0x0C "ESMIECR1,ESM Interrupt Enable Clear/Status Register 1"
line.long 0x10 "ESMILSR1,Interrupt Level Set/Status Register 1"
line.long 0x14 "ESMILCR1,Interrupt Level Clear/Status Register 1"
line.long 0x18 "ESMSR1,ESM Status Register 1"
line.long 0x1C "ESMSR2,ESM Status Register 2"
line.long 0x20 "ESMSR3,ESM Status Register 3"
line.long 0x24 "ESMEPSR,ESM ERROR Pin Status Register"
hexmask.long 0x24 1.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EPSF,ERROR Pin Status Flag" "0,1"
line.long 0x28 "ESMIOFFHR,ESM Interrupt Offset High Register"
hexmask.long.tbyte 0x28 9.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x28 0.--8. 1. "INTOFFH,Offset High Level Interrupt"
line.long 0x2C "ESMIOFFLR,ESM Interrupt Offset Low Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x2C 0.--7. 1. "INTOFFL,Offset Low Level Interrupt"
line.long 0x30 "ESMLTCR,ESM Low-Time Counter Register"
hexmask.long.word 0x30 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x30 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin"
line.long 0x34 "ESMLTCPR,ESM Low-Time Counter Preload Register"
hexmask.long.word 0x34 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x34 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter"
line.long 0x38 "ESMEKR,ESM Error Key Register"
hexmask.long 0x38 4.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0.--3. "EKEY,Error Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "ESMSSR2,ESM Status Shadow Register 2"
line.long 0x40 "ESMIEPSR4,ESM Enable ERROR Pin Action/Response Register 4"
line.long 0x44 "ESMIEPCR4,ESM Disable ERROR Pin Action/Response Register 4"
line.long 0x48 "ESMIESR4,ESM Interrupt Enable Set/Status Register 4"
line.long 0x4C "ESMIECR4,ESM Interrupt Enable Clear/Status Register 4"
line.long 0x50 "ESMILSR4,Interrupt Level Set/Status Register 4"
line.long 0x54 "ESMILCR4,Interrupt Level Clear/Status Register 4"
line.long 0x58 "ESMSR4,ESM Status Register 4"
group.long 0x80++0x1B
line.long 0x00 "ESMIEPSR7,ESM Enable ERROR Pin Action/Response Register 7"
line.long 0x04 "ESMIEPCR7,ESM Disable ERROR Pin Action/Response Register 7"
line.long 0x08 "ESMIESR7,ESM Interrupt Enable Set/Status Register 7"
line.long 0x0C "ESMIECR7,ESM Interrupt Enable Clear/Status Register 7"
line.long 0x10 "ESMILSR7,Interrupt Level Set/Status Register 7"
line.long 0x14 "ESMILCR7,Interrupt Level Clear/Status Register 7"
line.long 0x18 "ESMSR7,ESM Status Register 7"
group.long 0xC0++0x1B
line.long 0x00 "ESMIEPSR10,ESM Enable ERROR Pin Action/Response Register 10"
line.long 0x04 "ESMIEPCR10,ESM Disable ERROR Pin Action/Response Register 10"
line.long 0x08 "ESMIESR10,ESM Interrupt Enable Set/Status Register 10"
line.long 0x0C "ESMIECR10,ESM Interrupt Enable Clear/Status Register 10"
line.long 0x10 "ESMILSR10,Interrupt Level Set/Status Register 10"
line.long 0x14 "ESMILCR10,Interrupt Level Clear/Status Register 10"
line.long 0x18 "ESMSR10,ESM Status Register 10"
width 0x0B
tree.end
tree "DSS_HWA_CFG (DSS HWA CFG Module Registers)"
base ad:0x6062000
rgroup.long 0x00++0x457
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
newline
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PARAM_RAM_IDX,"
hexmask.long.word 0x04 16.--25. 1. "param_end_idx,The state machine starts at the parameter-set specified by PARAM_START_IDX and loads each parameter-set one after another and runs the accelerator as per that configuration"
newline
hexmask.long.word 0x04 0.--9. 1. "param_start_idx,The state machine starts at the parameter-set specified by PARAM_START_IDX and loads each parameter-set one after another and runs the accelerator as per that configuration"
line.long 0x08 "PARAM_RAM_LOOP,"
hexmask.long.word 0x08 0.--11. 1. "numloops,Number of loops: This register controls the number of times the State Machine will loop through the parameter-sets (from a programmed start index till a programmed end index) and run them"
line.long 0x0C "PARAM_RAM_IDX_ALT,"
hexmask.long.word 0x0C 16.--25. 1. "param_end_idx,PARAM_END_IDX for alternate thread"
newline
hexmask.long.word 0x0C 0.--9. 1. "param_start_idx,PARAM_START_IDX for alternate thread"
line.long 0x10 "PARAM_RAM_LOOP_ALT,"
hexmask.long.word 0x10 0.--11. 1. "numloops,NUMLOOPS for alternate thread"
line.long 0x14 "PREVIOUS_NAME,"
bitfld.long 0x14 24. "hwa_dyn_clk_en,Dynamic Clock-gating Control: Setting this register bit to '1' enables the capability to clock gate the 4 Radar Accelerator core IPs (FFT datapath CFAR Memory compression Local Maxima) based on the ParamSet being executed" "0,1"
newline
bitfld.long 0x14 16.--18. "hwa_reset,Software Reset Control: This register provides software reset control for the Radar Hardware Accelerator" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 8.--10. "hwa_clk_en,Clock-gating Control: This register controls the enable/disable for the clock of the Radar Accelerator" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 0.--2. "hwa_en,Enable/Disable Control: A value of ACC_ENABLE = 111b enables the Radar Hardware Accelerator and any other value of the register keeps the Accelerator Engine in disabled state" "0,1,2,3,4,5,6,7"
line.long 0x18 "CS_CONFIG,"
bitfld.long 0x18 16.--20. "cs_trgsrc,In case of DMA trigger this specifies which DMA channel (which bit in DMA2HWA_TRIG register) to wait for In case of HW-based trigger this specifies which CSI2 trigger signal (out of the 20 possible trigger signals) to wait for" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--11. "cs_trigmode,Trigger mode for context switching" "?,?,?,DMA-based trigger (used in conjunction with..,Hardware based trigger (used in conjunction with..,Software trigger (used in conjunction with..,?..."
newline
bitfld.long 0x18 0. "cs_enable,Master enable for the Conxtext switching feature.Setting this bit will allow context switching to ALT thread if it is enabled in the Param set" "0,1"
line.long 0x1C "FW2DMA_TRIG,"
line.long 0x20 "DMA2HWA_TRIG,"
line.long 0x24 "SIGDMACH0DONE,"
line.long 0x28 "SIGDMACH1DONE,"
line.long 0x2C "SIGDMACH2DONE,"
line.long 0x30 "SIGDMACH3DONE,"
line.long 0x34 "SIGDMACH4DONE,"
line.long 0x38 "SIGDMACH5DONE,"
line.long 0x3C "SIGDMACH6DONE,"
line.long 0x40 "SIGDMACH7DONE,"
line.long 0x44 "SIGDMACH8DONE,"
line.long 0x48 "SIGDMACH9DONE,"
line.long 0x4C "SIGDMACH10DONE,"
line.long 0x50 "SIGDMACH11DONE,"
line.long 0x54 "SIGDMACH12DONE,"
line.long 0x58 "SIGDMACH13DONE,"
line.long 0x5C "SIGDMACH14DONE,"
line.long 0x60 "SIGDMACH15DONE,"
line.long 0x64 "SIGDMACH16DONE,"
line.long 0x68 "SIGDMACH17DONE,"
line.long 0x6C "SIGDMACH18DONE,"
line.long 0x70 "SIGDMACH19DONE,"
line.long 0x74 "SIGDMACH20DONE,"
line.long 0x78 "SIGDMACH21DONE,"
line.long 0x7C "SIGDMACH22DONE,"
line.long 0x80 "SIGDMACH23DONE,"
line.long 0x84 "SIGDMACH24DONE,"
line.long 0x88 "SIGDMACH25DONE,"
line.long 0x8C "SIGDMACH26DONE,"
line.long 0x90 "SIGDMACH27DONE,"
line.long 0x94 "SIGDMACH28DONE,"
line.long 0x98 "SIGDMACH29DONE,"
line.long 0x9C "SIGDMACH30DONE,"
line.long 0xA0 "SIGDMACH31DONE,"
line.long 0xA4 "FW2HWA_TRIG_0,"
bitfld.long 0xA4 0. "fw2hwa_trigger_0,Software trigger bit" "0,1"
line.long 0xA8 "FW2HWA_TRIG_1,"
bitfld.long 0xA8 0. "fw2hwa_trigger_1,Software trigger bit" "0,1"
line.long 0xAC "CS_FW2ACC_TRIG,"
bitfld.long 0xAC 0. "fw2hwa_trigger_cs,CPU can set this register bit to trigger a context switch when CS_TRIGMODE = 101b It s a Self clearing bit" "0,1"
line.long 0xB0 "BPM_PATTERN_0,"
line.long 0xB4 "BPM_PATTERN_1,"
line.long 0xB8 "BPM_PATTERN_2,"
line.long 0xBC "BPM_PATTERN_3,"
line.long 0xC0 "BPM_PATTERN_4,"
line.long 0xC4 "BPM_PATTERN_5,"
line.long 0xC8 "BPM_PATTERN_6,"
line.long 0xCC "BPM_PATTERN_7,"
line.long 0xD0 "BPM_RATE,"
hexmask.long.word 0xD0 0.--9. 1. "bpm_rate,BPM rate: Specifies the number of input samples corresponding to each BPM bit"
line.long 0xD4 "PARAM_DONE_SET_STATUS_0,"
line.long 0xD8 "PARAM_DONE_SET_STATUS_1,"
line.long 0xDC "PARAM_DONE_CLR_0,"
line.long 0xE0 "PARAM_DONE_CLR_1,"
line.long 0xE4 "TRIGGER_SET_STATUS_0,"
line.long 0xE8 "TRIGGER_SET_STATUS_1,"
line.long 0xEC "TRIGGER_SET_IN_CLR_0,"
bitfld.long 0xEC 0. "trigger_set_in_clr_0,Clear trigger_set_status : This register-bit when set clears the trigger status register TRIGGER_SET_STATUS_0 described above It s a Self clearing bit" "0,1"
line.long 0xF0 "TRIGGER_SET_IN_CLR_1,"
bitfld.long 0xF0 0. "trigger_set_in_clr_1,Clear trigger_set_status : This register-bit when set clears the trigger status register TRIGGER_SET_STATUS_1 described above It s a Self clearing bit" "0,1"
line.long 0xF4 "DC_EST_RESET_SW,"
bitfld.long 0xF4 0. "dc_est_reset_sw,Reset for all 12 DC estimation accumulators It s a Self clearing bit" "0,1"
line.long 0xF8 "DC_EST_CTRL,"
bitfld.long 0xF8 16.--19. "dc_est_shift,Programmable shift applied to all 12 accumulator outputs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0xF8 0.--8. 1. "dc_est_scale,9-bit scale applied to all 12 accumulators"
line.long 0xFC "DC_EST_I_0_VAL,"
hexmask.long.tbyte 0xFC 0.--23. 1. "dc_est_i_0_val,This read only register provide the DC estimates I for bcnt= 0"
line.long 0x100 "DC_EST_I_1_VAL,"
hexmask.long.tbyte 0x100 0.--23. 1. "dc_est_i_1_val,This read only register provide the DC estimates I for bcnt= 1"
line.long 0x104 "DC_EST_I_2_VAL,"
hexmask.long.tbyte 0x104 0.--23. 1. "dc_est_i_2_val,This read only register provide the DC estimates I for bcnt= 2"
line.long 0x108 "DC_EST_I_3_VAL,"
hexmask.long.tbyte 0x108 0.--23. 1. "dc_est_i_3_val,This read only register provide the DC estimates I for bcnt= 3"
line.long 0x10C "DC_EST_I_4_VAL,"
hexmask.long.tbyte 0x10C 0.--23. 1. "dc_est_i_4_val,This read only register provide the DC estimates I for bcnt= 4"
line.long 0x110 "DC_EST_I_5_VAL,"
hexmask.long.tbyte 0x110 0.--23. 1. "dc_est_i_5_val,This read only register provide the DC estimates I for bcnt= 5"
line.long 0x114 "DC_EST_I_6_VAL,"
hexmask.long.tbyte 0x114 0.--23. 1. "dc_est_i_6_val,This read only register provide the DC estimates I for bcnt= 6"
line.long 0x118 "DC_EST_I_7_VAL,"
hexmask.long.tbyte 0x118 0.--23. 1. "dc_est_i_7_val,This read only register provide the DC estimates I for bcnt= 7"
line.long 0x11C "DC_EST_I_8_VAL,"
hexmask.long.tbyte 0x11C 0.--23. 1. "dc_est_i_8_val,This read only register provide the DC estimates I for bcnt= 8"
line.long 0x120 "DC_EST_I_9_VAL,"
hexmask.long.tbyte 0x120 0.--23. 1. "dc_est_i_9_val,This read only register provide the DC estimates I for bcnt= 9"
line.long 0x124 "DC_EST_I_10_VAL,"
hexmask.long.tbyte 0x124 0.--23. 1. "dc_est_i_10_val,This read only register provide the DC estimates I for bcnt= 10"
line.long 0x128 "DC_EST_I_11_VAL,"
hexmask.long.tbyte 0x128 0.--23. 1. "dc_est_i_11_val,This read only register provide the DC estimates I for bcnt= 11"
line.long 0x12C "DC_EST_Q_0_VAL,"
hexmask.long.tbyte 0x12C 0.--23. 1. "dc_est_q_0_val,This read only register provide the DC estimates Q for bcnt= 0"
line.long 0x130 "DC_EST_Q_1_VAL,"
hexmask.long.tbyte 0x130 0.--23. 1. "dc_est_q_1_val,This read only register provide the DC estimates Q for bcnt= 1"
line.long 0x134 "DC_EST_Q_2_VAL,"
hexmask.long.tbyte 0x134 0.--23. 1. "dc_est_q_2_val,This read only register provide the DC estimates Q for bcnt= 2"
line.long 0x138 "DC_EST_Q_3_VAL,"
hexmask.long.tbyte 0x138 0.--23. 1. "dc_est_q_3_val,This read only register provide the DC estimates Q for bcnt= 3"
line.long 0x13C "DC_EST_Q_4_VAL,"
hexmask.long.tbyte 0x13C 0.--23. 1. "dc_est_q_4_val,This read only register provide the DC estimates Q for bcnt= 4"
line.long 0x140 "DC_EST_Q_5_VAL,"
hexmask.long.tbyte 0x140 0.--23. 1. "dc_est_q_5_val,This read only register provide the DC estimates Q for bcnt= 5"
line.long 0x144 "DC_EST_Q_6_VAL,"
hexmask.long.tbyte 0x144 0.--23. 1. "dc_est_q_6_val,This read only register provide the DC estimates Q for bcnt= 6"
line.long 0x148 "DC_EST_Q_7_VAL,"
hexmask.long.tbyte 0x148 0.--23. 1. "dc_est_q_7_val,This read only register provide the DC estimates Q for bcnt= 7"
line.long 0x14C "DC_EST_Q_8_VAL,"
hexmask.long.tbyte 0x14C 0.--23. 1. "dc_est_q_8_val,This read only register provide the DC estimates Q for bcnt= 8"
line.long 0x150 "DC_EST_Q_9_VAL,"
hexmask.long.tbyte 0x150 0.--23. 1. "dc_est_q_9_val,This read only register provide the DC estimates Q for bcnt= 9"
line.long 0x154 "DC_EST_Q_10_VAL,"
hexmask.long.tbyte 0x154 0.--23. 1. "dc_est_q_10_val,This read only register provide the DC estimates Q for bcnt= 10"
line.long 0x158 "DC_EST_Q_11_VAL,"
hexmask.long.tbyte 0x158 0.--23. 1. "dc_est_q_11_val,This read only register provide the DC estimates Q for bcnt= 11"
line.long 0x15C "DC_ACC_I_0_VAL_LSB,"
line.long 0x160 "DC_ACC_I_0_VAL_MSB,"
bitfld.long 0x160 0.--3. "dc_acc_i_0_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "DC_ACC_I_1_VAL_LSB,"
line.long 0x168 "DC_ACC_I_1_VAL_MSB,"
bitfld.long 0x168 0.--3. "dc_acc_i_1_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "DC_ACC_I_2_VAL_LSB,"
line.long 0x170 "DC_ACC_I_2_VAL_MSB,"
bitfld.long 0x170 0.--3. "dc_acc_i_2_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "DC_ACC_I_3_VAL_LSB,"
line.long 0x178 "DC_ACC_I_3_VAL_MSB,"
bitfld.long 0x178 0.--3. "dc_acc_i_3_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "DC_ACC_I_4_VAL_LSB,"
line.long 0x180 "DC_ACC_I_4_VAL_MSB,"
bitfld.long 0x180 0.--3. "dc_acc_i_4_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "DC_ACC_I_5_VAL_LSB,"
line.long 0x188 "DC_ACC_I_5_VAL_MSB,"
bitfld.long 0x188 0.--3. "dc_acc_i_5_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "DC_ACC_I_6_VAL_LSB,"
line.long 0x190 "DC_ACC_I_6_VAL_MSB,"
bitfld.long 0x190 0.--3. "dc_acc_i_6_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "DC_ACC_I_7_VAL_LSB,"
line.long 0x198 "DC_ACC_I_7_VAL_MSB,"
bitfld.long 0x198 0.--3. "dc_acc_i_7_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "DC_ACC_I_8_VAL_LSB,"
line.long 0x1A0 "DC_ACC_I_8_VAL_MSB,"
bitfld.long 0x1A0 0.--3. "dc_acc_i_8_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "DC_ACC_I_9_VAL_LSB,"
line.long 0x1A8 "DC_ACC_I_9_VAL_MSB,"
bitfld.long 0x1A8 0.--3. "dc_acc_i_9_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "DC_ACC_I_10_VAL_LSB,"
line.long 0x1B0 "DC_ACC_I_10_VAL_MSB,"
bitfld.long 0x1B0 0.--3. "dc_acc_i_10_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "DC_ACC_I_11_VAL_LSB,"
line.long 0x1B8 "DC_ACC_I_11_VAL_MSB,"
bitfld.long 0x1B8 0.--3. "dc_acc_i_11_val_msb,This read only register provide the MSB 4 bits value of DC accumulator I channel value for bcnt=11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "DC_ACC_Q_0_VAL_LSB,"
line.long 0x1C0 "DC_ACC_Q_0_VAL_MSB,"
bitfld.long 0x1C0 0.--3. "dc_acc_q_0_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "DC_ACC_Q_1_VAL_LSB,"
line.long 0x1C8 "DC_ACC_Q_1_VAL_MSB,"
bitfld.long 0x1C8 0.--3. "dc_acc_q_1_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "DC_ACC_Q_2_VAL_LSB,"
line.long 0x1D0 "DC_ACC_Q_2_VAL_MSB,"
bitfld.long 0x1D0 0.--3. "dc_acc_q_2_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "DC_ACC_Q_3_VAL_LSB,"
line.long 0x1D8 "DC_ACC_Q_3_VAL_MSB,"
bitfld.long 0x1D8 0.--3. "dc_acc_q_3_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "DC_ACC_Q_4_VAL_LSB,"
line.long 0x1E0 "DC_ACC_Q_4_VAL_MSB,"
bitfld.long 0x1E0 0.--3. "dc_acc_q_4_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "DC_ACC_Q_5_VAL_LSB,"
line.long 0x1E8 "DC_ACC_Q_5_VAL_MSB,"
bitfld.long 0x1E8 0.--3. "dc_acc_q_5_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1EC "DC_ACC_Q_6_VAL_LSB,"
line.long 0x1F0 "DC_ACC_Q_6_VAL_MSB,"
bitfld.long 0x1F0 0.--3. "dc_acc_q_6_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F4 "DC_ACC_Q_7_VAL_LSB,"
line.long 0x1F8 "DC_ACC_Q_7_VAL_MSB,"
bitfld.long 0x1F8 0.--3. "dc_acc_q_7_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1FC "DC_ACC_Q_8_VAL_LSB,"
line.long 0x200 "DC_ACC_Q_8_VAL_MSB,"
bitfld.long 0x200 0.--3. "dc_acc_q_8_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x204 "DC_ACC_Q_9_VAL_LSB,"
line.long 0x208 "DC_ACC_Q_9_VAL_MSB,"
bitfld.long 0x208 0.--3. "dc_acc_q_9_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20C "DC_ACC_Q_10_VAL_LSB,"
line.long 0x210 "DC_ACC_Q_10_VAL_MSB,"
bitfld.long 0x210 0.--3. "dc_acc_q_10_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x214 "DC_ACC_Q_11_VAL_LSB,"
line.long 0x218 "DC_ACC_Q_11_VAL_MSB,"
bitfld.long 0x218 0.--3. "dc_acc_q_11_val_msb,This read only register provide the MSB 4 bits value of DC accumulator Q channel value for bcnt=11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x21C "DC_ACC_CLIP_STATUS,"
hexmask.long.word 0x21C 0.--11. 1. "dc_acc_clip_status,This register contains the clip status of both I/Q of DC accumulators 0 to 11"
line.long 0x220 "DC_EST_CLIP_STATUS,"
hexmask.long.word 0x220 0.--11. 1. "dc_est_clip_status,This register contains the clip status of DC estimates (both I & Q combined)"
line.long 0x224 "DC_I0_SW,"
hexmask.long.tbyte 0x224 0.--23. 1. "dc_i0_sw,SW programmed DC I value(for bcnt =0 ) used in DC subtraction"
line.long 0x228 "DC_I1_SW,"
hexmask.long.tbyte 0x228 0.--23. 1. "dc_i1_sw,SW programmed DC I value(for bcnt =1) used in DC subtraction"
line.long 0x22C "DC_I2_SW,"
hexmask.long.tbyte 0x22C 0.--23. 1. "dc_i2_sw,SW programmed DC I value(for bcnt =2 ) used in DC subtraction"
line.long 0x230 "DC_I3_SW,"
hexmask.long.tbyte 0x230 0.--23. 1. "dc_i3_sw,SW programmed DC I value(for bcnt =3) used in DC subtraction"
line.long 0x234 "DC_I4_SW,"
hexmask.long.tbyte 0x234 0.--23. 1. "dc_i4_sw,SW programmed DC I value(for bcnt =4 ) used in DC subtraction"
line.long 0x238 "DC_I5_SW,"
hexmask.long.tbyte 0x238 0.--23. 1. "dc_i5_sw,SW programmed DC I value(for bcnt =5 ) used in DC subtraction"
line.long 0x23C "DC_I6_SW,"
hexmask.long.tbyte 0x23C 0.--23. 1. "dc_i6_sw,SW programmed DC I value(for bcnt =6 ) used in DC subtraction"
line.long 0x240 "DC_I7_SW,"
hexmask.long.tbyte 0x240 0.--23. 1. "dc_i7_sw,SW programmed DC I value(for bcnt =7 ) used in DC subtraction"
line.long 0x244 "DC_I8_SW,"
hexmask.long.tbyte 0x244 0.--23. 1. "dc_i8_sw,SW programmed DC I value(for bcnt =8) used in DC subtraction"
line.long 0x248 "DC_I9_SW,"
hexmask.long.tbyte 0x248 0.--23. 1. "dc_i9_sw,SW programmed DC I value(for bcnt =9 ) used in DC subtraction"
line.long 0x24C "DC_I10_SW,"
hexmask.long.tbyte 0x24C 0.--23. 1. "dc_i10_sw,SW programmed DC I value(for bcnt =10 ) used in DC subtraction"
line.long 0x250 "DC_I11_SW,"
hexmask.long.tbyte 0x250 0.--23. 1. "dc_i11_sw,SW programmed DC I value(for bcnt =11) used in DC subtraction"
line.long 0x254 "DC_Q0_SW,"
hexmask.long.tbyte 0x254 0.--23. 1. "dc_q0_sw,SW programmed DC Q value(for bcnt =0 ) used in DC subtraction"
line.long 0x258 "DC_Q1_SW,"
hexmask.long.tbyte 0x258 0.--23. 1. "dc_q1_sw,SW programmed DC Q value(for bcnt =1) used in DC subtraction"
line.long 0x25C "DC_Q2_SW,"
hexmask.long.tbyte 0x25C 0.--23. 1. "dc_q2_sw,SW programmed DC Q value(for bcnt =2 ) used in DC subtraction"
line.long 0x260 "DC_Q3_SW,"
hexmask.long.tbyte 0x260 0.--23. 1. "dc_q3_sw,SW programmed DC Q value(for bcnt =3) used in DC subtraction"
line.long 0x264 "DC_Q4_SW,"
hexmask.long.tbyte 0x264 0.--23. 1. "dc_q4_sw,SW programmed DC Q value(for bcnt =4 ) used in DC subtraction"
line.long 0x268 "DC_Q5_SW,"
hexmask.long.tbyte 0x268 0.--23. 1. "dc_q5_sw,SW programmed DC Q value(for bcnt =5 ) used in DC subtraction"
line.long 0x26C "DC_Q6_SW,"
hexmask.long.tbyte 0x26C 0.--23. 1. "dc_q6_sw,SW programmed DC Q value(for bcnt =6 ) used in DC subtraction"
line.long 0x270 "DC_Q7_SW,"
hexmask.long.tbyte 0x270 0.--23. 1. "dc_q7_sw,SW programmed DC Q value(for bcnt =7 ) used in DC subtraction"
line.long 0x274 "DC_Q8_SW,"
hexmask.long.tbyte 0x274 0.--23. 1. "dc_q8_sw,SW programmed DC Q value(for bcnt =8) used in DC subtraction"
line.long 0x278 "DC_Q9_SW,"
hexmask.long.tbyte 0x278 0.--23. 1. "dc_q9_sw,SW programmed DC Q value(for bcnt =9 ) used in DC subtraction"
line.long 0x27C "DC_Q10_SW,"
hexmask.long.tbyte 0x27C 0.--23. 1. "dc_q10_sw,SW programmed DC Q value(for bcnt =10 ) used in DC subtraction"
line.long 0x280 "DC_Q11_SW,"
hexmask.long.tbyte 0x280 0.--23. 1. "dc_q11_sw,SW programmed DC Q value(for bcnt =11) used in DC subtraction"
line.long 0x284 "DC_SUB_CLIP,"
bitfld.long 0x284 0. "DC_SUB_CLIP,Indicates the DC subtraction clip status" "0,1"
line.long 0x288 "DC_RESERVED_2,"
line.long 0x28C "DC_RESERVED_3,"
line.long 0x290 "DC_RESERVED_4,"
line.long 0x294 "DC_RESERVED_5,"
line.long 0x298 "INTF_STATS_RESET_SW,"
bitfld.long 0x298 0. "intf_stats_reset_sw,SW reset for Interference stats module" "0,1"
line.long 0x29C "INTF_STATS_CTRL,"
hexmask.long.byte 0x29C 24.--31. 1. "intf_stats_magdiff_scale,Unsigned scaler (5.3) applied to INTERFSUM_MAGDIFFn from interference statistics block"
newline
hexmask.long.byte 0x29C 16.--23. 1. "intf_stats_mag_scale,Unsigned scaler (5.3) applied to INTERFSUM_MAGn from interference statistics block"
newline
bitfld.long 0x29C 4.--6. "intf_stats_magdiff_shift,Right shift applied after scaling - 2^(6+INTERFSUM_MAGDIFF_SHIFT)" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x29C 0.--2. "intf_stats_mag_shift,Right shift applied after scaling - 2^(6+INTERSUM_MAGS_SHIFT)" "0,1,2,3,4,5,6,7"
line.long 0x2A0 "INTF_LOC_THRESH_MAG0_VAL,"
hexmask.long.tbyte 0x2A0 0.--23. 1. "intf_loc_thresh_mag0_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =0"
line.long 0x2A4 "INTF_LOC_THRESH_MAG1_VAL,"
hexmask.long.tbyte 0x2A4 0.--23. 1. "intf_loc_thresh_mag1_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =1"
line.long 0x2A8 "INTF_LOC_THRESH_MAG2_VAL,"
hexmask.long.tbyte 0x2A8 0.--23. 1. "intf_loc_thresh_mag2_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =2"
line.long 0x2AC "INTF_LOC_THRESH_MAG3_VAL,"
hexmask.long.tbyte 0x2AC 0.--23. 1. "intf_loc_thresh_mag3_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =3"
line.long 0x2B0 "INTF_LOC_THRESH_MAG4_VAL,"
hexmask.long.tbyte 0x2B0 0.--23. 1. "intf_loc_thresh_mag4_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =4"
line.long 0x2B4 "INTF_LOC_THRESH_MAG5_VAL,"
hexmask.long.tbyte 0x2B4 0.--23. 1. "intf_loc_thresh_mag5_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =5"
line.long 0x2B8 "INTF_LOC_THRESH_MAG6_VAL,"
hexmask.long.tbyte 0x2B8 0.--23. 1. "intf_loc_thresh_mag6_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =6"
line.long 0x2BC "INTF_LOC_THRESH_MAG7_VAL,"
hexmask.long.tbyte 0x2BC 0.--23. 1. "intf_loc_thresh_mag7_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =7"
line.long 0x2C0 "INTF_LOC_THRESH_MAG8_VAL,"
hexmask.long.tbyte 0x2C0 0.--23. 1. "intf_loc_thresh_mag8_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =8"
line.long 0x2C4 "INTF_LOC_THRESH_MAG9_VAL,"
hexmask.long.tbyte 0x2C4 0.--23. 1. "intf_loc_thresh_mag9_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =9"
line.long 0x2C8 "INTF_LOC_THRESH_MAG10_VAL,"
hexmask.long.tbyte 0x2C8 0.--23. 1. "intf_loc_thresh_mag10_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =10"
line.long 0x2CC "INTF_LOC_THRESH_MAG11_VAL,"
hexmask.long.tbyte 0x2CC 0.--23. 1. "intf_loc_thresh_mag11_val,Interference magnitude threshold value from Interference stats module ( read only) for bcnt =11"
line.long 0x2D0 "INTF_LOC_THRESH_MAGDIFF0_VAL,"
hexmask.long.tbyte 0x2D0 0.--23. 1. "intf_loc_thresh_magdiff0_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =0"
line.long 0x2D4 "INTF_LOC_THRESH_MAGDIFF1_VAL,"
hexmask.long.tbyte 0x2D4 0.--23. 1. "intf_loc_thresh_magdiff1_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =1"
line.long 0x2D8 "INTF_LOC_THRESH_MAGDIFF2_VAL,"
hexmask.long.tbyte 0x2D8 0.--23. 1. "intf_loc_thresh_magdiff2_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =2"
line.long 0x2DC "INTF_LOC_THRESH_MAGDIFF3_VAL,"
hexmask.long.tbyte 0x2DC 0.--23. 1. "intf_loc_thresh_magdiff3_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =3"
line.long 0x2E0 "INTF_LOC_THRESH_MAGDIFF4_VAL,"
hexmask.long.tbyte 0x2E0 0.--23. 1. "intf_loc_thresh_magdiff4_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =4"
line.long 0x2E4 "INTF_LOC_THRESH_MAGDIFF5_VAL,"
hexmask.long.tbyte 0x2E4 0.--23. 1. "intf_loc_thresh_magdiff5_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =5"
line.long 0x2E8 "INTF_LOC_THRESH_MAGDIFF6_VAL,"
hexmask.long.tbyte 0x2E8 0.--23. 1. "intf_loc_thresh_magdiff6_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =6"
line.long 0x2EC "INTF_LOC_THRESH_MAGDIFF7_VAL,"
hexmask.long.tbyte 0x2EC 0.--23. 1. "intf_loc_thresh_magdiff7_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =7"
line.long 0x2F0 "INTF_LOC_THRESH_MAGDIFF8_VAL,"
hexmask.long.tbyte 0x2F0 0.--23. 1. "intf_loc_thresh_magdiff8_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =8"
line.long 0x2F4 "INTF_LOC_THRESH_MAGDIFF9_VAL,"
hexmask.long.tbyte 0x2F4 0.--23. 1. "intf_loc_thresh_magdiff9_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =9"
line.long 0x2F8 "INTF_LOC_THRESH_MAGDIFF10_VAL,"
hexmask.long.tbyte 0x2F8 0.--23. 1. "intf_loc_thresh_magdiff10_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =10"
line.long 0x2FC "INTF_LOC_THRESH_MAGDIFF11_VAL,"
hexmask.long.tbyte 0x2FC 0.--23. 1. "intf_loc_thresh_magdiff11_val,Interference magnitude difference threshold value from Interference stats module ( read only) for bcnt =11"
line.long 0x300 "INTF_LOC_COUNT_ALL_CHIRP,"
hexmask.long.word 0x300 0.--11. 1. "intf_loc_count_all_chirp,Number of samples that exceeded the threshold in a chirp"
line.long 0x304 "INTF_LOC_COUNT_ALL_FRAME,"
hexmask.long.tbyte 0x304 0.--19. 1. "intf_loc_count_all_frame,Number of samples that exceeded the threshold in a frame"
line.long 0x308 "INTF_STATS_MAG_ACC_0_LSB,"
line.long 0x30C "INTF_STATS_MAG_ACC_0_MSB,"
bitfld.long 0x30C 0.--3. "intf_stats_mag_acc_0_msb,This read only register contains the accumulator value of interference magnitude(MSB 4 bits) for bcnt = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x310 "INTF_STATS_MAG_ACC_1_LSB,"
line.long 0x314 "INTF_STATS_MAG_ACC_1_MSB,"
bitfld.long 0x314 0.--3. "intf_stats_mag_acc_1_msb,This read only contains the accumulator value of interference magnitude (MSB 4 bits) for bcnt = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x318 "INTF_STATS_MAG_ACC_2_LSB,"
line.long 0x31C "INTF_STATS_MAG_ACC_2_MSB,"
bitfld.long 0x31C 0.--3. "intf_stats_mag_acc_2_msb,This read only register contains the accumulator value of interference magnitude (MSB 4 bits) for bcnt = 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x320 "INTF_STATS_MAG_ACC_3_LSB,"
line.long 0x324 "INTF_STATS_MAG_ACC_3_MSB,"
bitfld.long 0x324 0.--3. "intf_stats_mag_acc_3_msb,This read only register contains the accumulator value of the interference magnitude(for MSB 4 bits) for bcnt = 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x328 "INTF_STATS_MAG_ACC_4_LSB,"
line.long 0x32C "INTF_STATS_MAG_ACC_4_MSB,"
bitfld.long 0x32C 0.--3. "intf_stats_mag_acc_4_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x330 "INTF_STATS_MAG_ACC_5_LSB,"
line.long 0x334 "INTF_STATS_MAG_ACC_5_MSB,"
bitfld.long 0x334 0.--3. "intf_stats_mag_acc_5_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x338 "INTF_STATS_MAG_ACC_6_LSB,"
line.long 0x33C "INTF_STATS_MAG_ACC_6_MSB,"
bitfld.long 0x33C 0.--3. "intf_stats_mag_acc_6_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits)for bcnt = 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x340 "INTF_STATS_MAG_ACC_7_LSB,"
line.long 0x344 "INTF_STATS_MAG_ACC_7_MSB,"
bitfld.long 0x344 0.--3. "intf_stats_mag_acc_7_msb,This read only register contains the accumulator value of the interference magnitude (MSB4 bits)for bcnt = 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x348 "INTF_STATS_MAG_ACC_8_LSB,"
line.long 0x34C "INTF_STATS_MAG_ACC_8_MSB,"
bitfld.long 0x34C 0.--3. "intf_stats_mag_acc_8_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x350 "INTF_STATS_MAG_ACC_9_LSB,"
line.long 0x354 "INTF_STATS_MAG_ACC_9_MSB,"
bitfld.long 0x354 0.--3. "intf_stats_mag_acc_9_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x358 "INTF_STATS_MAG_ACC_10_LSB,"
line.long 0x35C "INTF_STATS_MAG_ACC_10_MSB,"
bitfld.long 0x35C 0.--3. "intf_stats_mag_acc_10_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x360 "INTF_STATS_MAG_ACC_11_LSB,"
line.long 0x364 "INTF_STATS_MAG_ACC_11_MSB,"
bitfld.long 0x364 0.--3. "intf_stats_mag_acc_11_msb,This read only register contains the accumulator value of the interference magnitude (MSB 4 bits) for bcnt = 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x368 "INTF_STATS_MAGDIFF_ACC_0_LSB,"
line.long 0x36C "INTF_STATS_MAGDIFF_ACC_0_MSB,"
bitfld.long 0x36C 0.--3. "intf_stats_magdiff_acc_0_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x370 "INTF_STATS_MAGDIFF_ACC_1_LSB,"
line.long 0x374 "INTF_STATS_MAGDIFF_ACC_1_MSB,"
bitfld.long 0x374 0.--3. "intf_stats_magdiff_acc_1_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x378 "INTF_STATS_MAGDIFF_ACC_2_LSB,"
line.long 0x37C "INTF_STATS_MAGDIFF_ACC_2_MSB,"
bitfld.long 0x37C 0.--3. "intf_stats_magdiff_acc_2_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x380 "INTF_STATS_MAGDIFF_ACC_3_LSB,"
line.long 0x384 "INTF_STATS_MAGDIFF_ACC_3_MSB,"
bitfld.long 0x384 0.--3. "intf_stats_magdiff_acc_3_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x388 "INTF_STATS_MAGDIFF_ACC_4_LSB,"
line.long 0x38C "INTF_STATS_MAGDIFF_ACC_4_MSB,"
bitfld.long 0x38C 0.--3. "intf_stats_magdiff_acc_4_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x390 "INTF_STATS_MAGDIFF_ACC_5_LSB,"
line.long 0x394 "INTF_STATS_MAGDIFF_ACC_5_MSB,"
bitfld.long 0x394 0.--3. "intf_stats_magdiff_acc_5_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x398 "INTF_STATS_MAGDIFF_ACC_6_LSB,"
line.long 0x39C "INTF_STATS_MAGDIFF_ACC_6_MSB,"
bitfld.long 0x39C 0.--3. "intf_stats_magdiff_acc_6_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A0 "INTF_STATS_MAGDIFF_ACC_7_LSB,"
line.long 0x3A4 "INTF_STATS_MAGDIFF_ACC_7_MSB,"
bitfld.long 0x3A4 0.--3. "intf_stats_magdiff_acc_7_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A8 "INTF_STATS_MAGDIFF_ACC_8_LSB,"
line.long 0x3AC "INTF_STATS_MAGDIFF_ACC_8_MSB,"
bitfld.long 0x3AC 0.--3. "intf_stats_magdiff_acc_8_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B0 "INTF_STATS_MAGDIFF_ACC_9_LSB,"
line.long 0x3B4 "INTF_STATS_MAGDIFF_ACC_9_MSB,"
bitfld.long 0x3B4 0.--3. "intf_stats_magdiff_acc_9_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 9" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B8 "INTF_STATS_MAGDIFF_ACC_10_LSB,"
line.long 0x3BC "INTF_STATS_MAGDIFF_ACC_10_MSB,"
bitfld.long 0x3BC 0.--3. "intf_stats_magdiff_acc_10_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 10" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C0 "INTF_STATS_MAGDIFF_ACC_11_LSB,"
line.long 0x3C4 "INTF_STATS_MAGDIFF_ACC_11_MSB,"
bitfld.long 0x3C4 0.--3. "intf_stats_magdiff_acc_11_msb,This read only register contains the accumulator value of the interference magnitude difference (MSB 4 bits) for bcnt = 11" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C8 "INTF_LOC_THRESH_MAG0_SW,"
hexmask.long.tbyte 0x3C8 0.--23. 1. "intf_loc_thresh_mag0_sw,SW programmed interface threshold magnitude for bcnt=0"
line.long 0x3CC "INTF_LOC_THRESH_MAG1_SW,"
hexmask.long.tbyte 0x3CC 0.--23. 1. "intf_loc_thresh_mag1_sw,SW programmed interface threshold magnitude for bcnt=1"
line.long 0x3D0 "INTF_LOC_THRESH_MAG2_SW,"
hexmask.long.tbyte 0x3D0 0.--23. 1. "intf_loc_thresh_mag2_sw,SW programmed interface threshold magnitude for bcnt=2"
line.long 0x3D4 "INTF_LOC_THRESH_MAG3_SW,"
hexmask.long.tbyte 0x3D4 0.--23. 1. "intf_loc_thresh_mag3_sw,SW programmed interface threshold magnitude for bcnt=3"
line.long 0x3D8 "INTF_LOC_THRESH_MAG4_SW,"
hexmask.long.tbyte 0x3D8 0.--23. 1. "intf_loc_thresh_mag4_sw,SW programmed interface threshold magnitude for bcnt=4"
line.long 0x3DC "INTF_LOC_THRESH_MAG5_SW,"
hexmask.long.tbyte 0x3DC 0.--23. 1. "intf_loc_thresh_mag5_sw,SW programmed interface threshold magnitude for bcnt=5"
line.long 0x3E0 "INTF_LOC_THRESH_MAG6_SW,"
hexmask.long.tbyte 0x3E0 0.--23. 1. "intf_loc_thresh_mag6_sw,SW programmed interface threshold magnitude for bcnt=6"
line.long 0x3E4 "INTF_LOC_THRESH_MAG7_SW,"
hexmask.long.tbyte 0x3E4 0.--23. 1. "intf_loc_thresh_mag7_sw,SW programmed interface threshold magnitude for bcnt=7"
line.long 0x3E8 "INTF_LOC_THRESH_MAG8_SW,"
hexmask.long.tbyte 0x3E8 0.--23. 1. "intf_loc_thresh_mag8_sw,SW programmed interface threshold magnitude for bcnt=8"
line.long 0x3EC "INTF_LOC_THRESH_MAG9_SW,"
hexmask.long.tbyte 0x3EC 0.--23. 1. "intf_loc_thresh_mag9_sw,SW programmed interface threshold magnitude for bcnt=9"
line.long 0x3F0 "INTF_LOC_THRESH_MAG10_SW,"
hexmask.long.tbyte 0x3F0 0.--23. 1. "intf_loc_thresh_mag10_sw,SW programmed interface threshold magnitude for bcnt=10"
line.long 0x3F4 "INTF_LOC_THRESH_MAG11_SW,"
hexmask.long.tbyte 0x3F4 0.--23. 1. "intf_loc_thresh_mag11_sw,SW programmed interface threshold magnitude for bcnt=11"
line.long 0x3F8 "INTF_LOC_THRESH_MAGDIFF0_SW,"
hexmask.long.tbyte 0x3F8 0.--23. 1. "intf_loc_thresh_magdiff0_sw,SW programmed interface threshold magnitude difference for bcnt=0"
line.long 0x3FC "INTF_LOC_THRESH_MAGDIFF1_SW,"
hexmask.long.tbyte 0x3FC 0.--23. 1. "intf_loc_thresh_magdiff1_sw,SW programmed interface threshold magnitude difference for bcnt=1"
line.long 0x400 "INTF_LOC_THRESH_MAGDIFF2_SW,"
hexmask.long.tbyte 0x400 0.--23. 1. "intf_loc_thresh_magdiff2_sw,SW programmed interface threshold magnitude difference for bcnt=2"
line.long 0x404 "INTF_LOC_THRESH_MAGDIFF3_SW,"
hexmask.long.tbyte 0x404 0.--23. 1. "intf_loc_thresh_magdiff3_sw,SW programmed interface threshold magnitude difference for bcnt=3"
line.long 0x408 "INTF_LOC_THRESH_MAGDIFF4_SW,"
hexmask.long.tbyte 0x408 0.--23. 1. "intf_loc_thresh_magdiff4_sw,SW programmed interface threshold magnitude difference for bcnt=4"
line.long 0x40C "INTF_LOC_THRESH_MAGDIFF5_SW,"
hexmask.long.tbyte 0x40C 0.--23. 1. "intf_loc_thresh_magdiff5_sw,SW programmed interface threshold magnitude difference for bcnt=5"
line.long 0x410 "INTF_LOC_THRESH_MAGDIFF6_SW,"
hexmask.long.tbyte 0x410 0.--23. 1. "intf_loc_thresh_magdiff6_sw,SW programmed interface threshold magnitude difference for bcnt=6"
line.long 0x414 "INTF_LOC_THRESH_MAGDIFF7_SW,"
hexmask.long.tbyte 0x414 0.--23. 1. "intf_loc_thresh_magdiff7_sw,SW programmed interface threshold magnitude difference for bcnt=7"
line.long 0x418 "INTF_LOC_THRESH_MAGDIFF8_SW,"
hexmask.long.tbyte 0x418 0.--23. 1. "intf_loc_thresh_magdiff8_sw,SW programmed interface threshold magnitude difference for bcnt=8"
line.long 0x41C "INTF_LOC_THRESH_MAGDIFF9_SW,"
hexmask.long.tbyte 0x41C 0.--23. 1. "intf_loc_thresh_magdiff9_sw,SW programmed interface threshold magnitude difference for bcnt=9"
line.long 0x420 "INTF_LOC_THRESH_MAGDIFF10_SW,"
hexmask.long.tbyte 0x420 0.--23. 1. "intf_loc_thresh_magdiff10_sw,SW programmed interface threshold magnitude difference for bcnt=10"
line.long 0x424 "INTF_LOC_THRESH_MAGDIFF11_SW,"
hexmask.long.tbyte 0x424 0.--23. 1. "intf_loc_thresh_magdiff11_sw,SW programmed interface threshold magnitude difference for bcnt=11"
line.long 0x428 "INTF_STATS_ACC_CLIP_STATUS,"
hexmask.long.word 0x428 16.--27. 1. "intf_stats_magdiff_accumulator_clip_status,Interference magnitue difference accumulator Clip status"
newline
hexmask.long.word 0x428 0.--11. 1. "intf_stats_mag_accumulator_clip_status,Interference magnitue accumulator Clip status"
line.long 0x42C "INTF_STATS_THRESH_CLIP_STATUS,"
hexmask.long.word 0x42C 16.--27. 1. "intf_stats_thresh_magdiff_clip_status,Interference magnitude difference threshold Clip status"
newline
hexmask.long.word 0x42C 0.--11. 1. "intf_stats_thresh_mag_clip_status,Interference magnitude threshold Clip status"
line.long 0x430 "INTF_MITG_WINDOW_PARAM_0,"
bitfld.long 0x430 0.--4. "intf_mitg_window_param_0,This is a programmable array of window parameters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x434 "INTF_MITG_WINDOW_PARAM_1,"
bitfld.long 0x434 0.--4. "intf_mitg_window_param_1,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x438 "INTF_MITG_WINDOW_PARAM_2,"
bitfld.long 0x438 0.--4. "intf_mitg_window_param_2,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x43C "INTF_MITG_WINDOW_PARAM_3,"
bitfld.long 0x43C 0.--4. "intf_mitg_window_param_3,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x440 "INTF_MITG_WINDOW_PARAM_4,"
bitfld.long 0x440 0.--4. "intf_mitg_window_param_4,Refer description of INTF_MITG_WINDOW_PARAM_0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x444 "INTF_STATS_SUM_MAG_VAL,"
hexmask.long.tbyte 0x444 0.--23. 1. "intf_stats_sum_mag_val,Indicates the sum of mag values ; Only Configured BCNT mag values are added"
line.long 0x448 "INTF_STATS_SUM_MAG_VAL_CLIP_STATUS,"
bitfld.long 0x448 0. "intf_stats_sum_mag_val_clip_status,Indicates the clip status of sum of mag values" "0,1"
line.long 0x44C "INTF_STATS_SUM_MAGDIFF_VAL,"
hexmask.long.tbyte 0x44C 0.--23. 1. "intf_stats_sum_magdiff_val,Indicates the sum of magdiff values ; Only Configured BCNT magdiff values are added"
line.long 0x450 "INTF_STATS_SUM_MAGDIFF_VAL_CLIP_STATUS,"
bitfld.long 0x450 0. "intf_stats_sum_magdiff_val_clip_status,indicates the clip status of sum of magdiff values" "0,1"
line.long 0x454 "INTERF_RESERVED_5,"
group.long 0x4B8++0x1BB
line.long 0x00 "TWID_INCR_DELTA_FRAC,"
hexmask.long.word 0x00 0.--9. 1. "twid_incr_delta_frac,Used in complex multiplier mode 10 Delta Fractional frequency increment per param-set looping Instantaneous frequency is (TWIDINCR << 10) +TWID_INCR_DELTA_ FRAC*c c is current execution count of the parameter set"
line.long 0x04 "RECWIN_RESET_SW,"
bitfld.long 0x04 0. "recwin_reset_sw,This resets the param set counter / execution counter used in Complex multiplier mode 8" "0,1"
line.long 0x08 "TWID_INCR_DELTA_FRAC_RESET_SW,"
bitfld.long 0x08 0. "twid_incr_delta_frac_reset_sw,This resets the param set counter used in Complex multiplier mode 10" "0,1"
line.long 0x0C "TWID_INCR_DELTA_FRAC_CLIP_STATUS,"
bitfld.long 0x0C 0. "twid_incr_delta_frac_clip_status,Indicates the clip status for TWID_INCR_DELTA_FRAC accumulator" "0,1"
line.long 0x10 "RECWIN_INIT_KVAL,"
hexmask.long.word 0x10 0.--11. 1. "recwin_init_kval,Indicates the initialization value of execution counter in recursive window mode"
line.long 0x14 "CMULT_RESERVED_2,"
line.long 0x18 "CHAN_COMB_SIZE,"
hexmask.long.byte 0x18 0.--7. 1. "chan_comb_size,Number of samples after combination"
line.long 0x1C "CHAN_COMB_VEC_0,"
line.long 0x20 "CHAN_COMB_VEC_1,"
line.long 0x24 "CHAN_COMB_VEC_2,"
line.long 0x28 "CHAN_COMB_VEC_3,"
line.long 0x2C "CHAN_COMB_VEC_4,"
line.long 0x30 "CHAN_COMB_VEC_5,"
line.long 0x34 "CHAN_COMB_VEC_6,"
line.long 0x38 "CHAN_COMB_VEC_7,"
line.long 0x3C "CHANNEL_COMB_CLIP_STATUS,"
bitfld.long 0x3C 0. "channel_comb_clip_status,Indicates the clip status of the channel combination" "0,1"
line.long 0x40 "ZERO_INSERT_NUM,"
hexmask.long.byte 0x40 0.--7. 1. "zero_insert_num,Number of zeros to be inserted in an iteration"
line.long 0x44 "ZERO_INSERT_MASK_0,"
line.long 0x48 "ZERO_INSERT_MASK_1,"
line.long 0x4C "ZERO_INSERT_MASK_2,"
line.long 0x50 "ZERO_INSERT_MASK_3,"
line.long 0x54 "ZERO_INSERT_MASK_4,"
line.long 0x58 "ZERO_INSERT_MASK_5,"
line.long 0x5C "ZERO_INSERT_MASK_6,"
line.long 0x60 "ZERO_INSERT_MASK_7,"
line.long 0x64 "ZERO_INSERT_RESERVED_1,"
line.long 0x68 "ZERO_INSERT_RESERVED_2,"
line.long 0x6C "ZERO_INSERT_RESERVED_3,"
line.long 0x70 "ZERO_INSERT_RESERVED_4,"
line.long 0x74 "LFSR_SEED,"
hexmask.long 0x74 0.--28. 1. "lfsr_seed,Seed for LFSR (random pattern): For twiddle factor dithering there is an LFSR that is used whose seed value is loaded by writing to this 29-bit LFSRSEED register"
line.long 0x78 "LFSR_LOAD,"
bitfld.long 0x78 0. "lfsr_load,Its self clearing bit" "0,1"
line.long 0x7C "DITHER_TWID_EN,"
bitfld.long 0x7C 0. "dither_twid_en,Twiddle factor dithering enable: This register-bit is used to enable and disable dithering of twiddle factors in the FFT" "0,1"
line.long 0x80 "FFT_CLIP,"
hexmask.long.word 0x80 0.--12. 1. "fft_clip,FFT Clip Status (read-only): This is a read-only status register which indicates any saturation/clipping events that have happened in the FFT butterfly stages"
line.long 0x84 "CLR_FFTCLIP,"
bitfld.long 0x84 0. "clr_fftclip,Clear FFT Clip Status register: This register bit when set clears the FFTCLIP register" "0,1"
line.long 0x88 "CLR_CLIP_MISC,"
bitfld.long 0x88 0. "clr_clip_status,This clears the following clip register channel_comb_clip_status dc_acc_clip_status dc_est_clip_status intf_stats_mag_accumulator_clip_status intf_stats_magdiff_accumulator_clip_status intf_stats_thresh_mag_clip_status.." "0,1"
line.long 0x8C "IP_OP_FORMATTER_CLIP_STATUS,"
bitfld.long 0x8C 16. "op_formatter_clip_status,Indicates the output formatter clip status" "0,1"
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bitfld.long 0x8C 0. "ip_formatter_clip_status,Indicates the input formatter clip status" "0,1"
line.long 0x90 "FFT_RESERVED_1,"
line.long 0x94 "FFT_RESERVED_2,"
line.long 0x98 "FFT_RESERVED_3,"
line.long 0x9C "MAX1_VALUE,"
hexmask.long.tbyte 0x9C 0.--23. 1. "max1_value,These registers contain the max value on a per-iteration basis"
line.long 0xA0 "MAX2_VALUE,"
hexmask.long.tbyte 0xA0 0.--23. 1. "max2_value,These registers contain the max value on a per-iteration basis"
line.long 0xA4 "MAX3_VALUE,"
hexmask.long.tbyte 0xA4 0.--23. 1. "max3_value,These registers contain the max value on a per-iteration basis"
line.long 0xA8 "MAX4_VALUE,"
hexmask.long.tbyte 0xA8 0.--23. 1. "max4_value,These registers contain the max value on a per-iteration basis"
line.long 0xAC "MAX1_INDEX,"
hexmask.long.word 0xAC 0.--11. 1. "max1_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xB0 "MAX2_INDEX,"
hexmask.long.word 0xB0 0.--11. 1. "max2_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xB4 "MAX3_INDEX,"
hexmask.long.word 0xB4 0.--11. 1. "max3_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xB8 "MAX4_INDEX,"
hexmask.long.word 0xB8 0.--11. 1. "max4_index,These registers contain the max index on a per-iteration basis corresponding to each max value in the MAXn_VALUE registers"
line.long 0xBC "I_SUM1_LSB,"
line.long 0xC0 "I_SUM1_MSB,"
bitfld.long 0xC0 0.--3. "i_sum1_msb,I Sum value 1 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "I_SUM2_LSB,"
line.long 0xC8 "I_SUM2_MSB,"
bitfld.long 0xC8 0.--3. "i_sum2_msb,I Sum value 2 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "I_SUM3_LSB,"
line.long 0xD0 "I_SUM3_MSB,"
bitfld.long 0xD0 0.--3. "i_sum3_msb,I Sum value 3 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "I_SUM4_LSB,"
line.long 0xD8 "I_SUM4_MSB,"
bitfld.long 0xD8 0.--3. "i_sum4_msb,I Sum value 4 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "Q_SUM1_LSB,"
line.long 0xE0 "Q_SUM1_MSB,"
bitfld.long 0xE0 0.--3. "q_sum1_msb,Q Sum value 1 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "Q_SUM2_LSB,"
line.long 0xE8 "Q_SUM2_MSB,"
bitfld.long 0xE8 0.--3. "q_sum2_msb,Q Sum value 2 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "Q_SUM3_LSB,"
line.long 0xF0 "Q_SUM3_MSB,"
bitfld.long 0xF0 0.--3. "q_sum3_msb,Q Sum value 3 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "Q_SUM4_LSB,"
line.long 0xF8 "Q_SUM4_MSB,"
bitfld.long 0xF8 0.--3. "q_sum4_msb,Q Sum value 4 MSB 4 bits These registers contain the sum of the I outputs and Q outputs on a per-iteration basis" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "FFTSUMDIV,"
bitfld.long 0xFC 0.--4. "fftsumdiv,Right-shifting for Sum statistic: This register specifies the number of bits to right-shift the sum statistic before it is written to destination memory" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x100 "MAX2D_OFFSET_DIM1,"
hexmask.long.tbyte 0x100 0.--23. 1. "max2d_offset_dim1,Offset to be added to dimension 1 Maxima results"
line.long 0x104 "MAX2D_OFFSET_DIM2,"
hexmask.long.tbyte 0x104 0.--23. 1. "max2d_offset_dim2,Offset to be added to dimension 2 Maxima results"
line.long 0x108 "CDF_CNT_THRESH,"
hexmask.long.word 0x108 0.--11. 1. "cdf_cnt_thresh,This register is applicable in CDF_CNT_THRESH mode of operation"
line.long 0x10C "STATS_RESERVED_1,"
line.long 0x110 "STATS_RESERVED_2,"
line.long 0x114 "STATS_RESERVED_3,"
line.long 0x118 "STATS_RESERVED_4,"
line.long 0x11C "STATS_RESERVED_5,"
line.long 0x120 "CFAR_PEAKCNT,"
hexmask.long.word 0x120 0.--11. 1. "cfar_peakcnt,CFAR detected peak count: This is a read-only register that contains the number of detected peaks that are logged in the destination memory when CFAR Engine is configured in Detected Peaks List mode"
line.long 0x124 "CFAR_DET_THR,"
hexmask.long.tbyte 0x124 0.--23. 1. "cfar_det_thr,To be added"
line.long 0x128 "CFAR_TEST_REG,"
hexmask.long.tbyte 0x128 0.--23. 1. "cfar_test_reg,To be added"
line.long 0x12C "CFAR_THRESH,"
hexmask.long.tbyte 0x12C 0.--17. 1. "cfar_thresh,Threshold scale factor: This register is used to specify the threshold scale factor"
line.long 0x130 "CFAR_RESERVED_1,"
line.long 0x134 "CFAR_RESERVED_2,"
line.long 0x138 "CFAR_RESERVED_3,"
line.long 0x13C "CFAR_RESERVED_4,"
line.long 0x140 "CMP_EGE_K0123,"
bitfld.long 0x140 24.--28. "cmp_ege_k3,3th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 16.--20. "cmp_ege_k2,2th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 8.--12. "cmp_ege_k1,1th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 0.--4. "cmp_ege_k0,0th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x144 "CMP_EGE_K4567,"
bitfld.long 0x144 24.--28. "cmp_ege_k7,7th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x144 16.--20. "cmp_ege_k6,6th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x144 8.--12. "cmp_ege_k5,5th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x144 0.--4. "cmp_ege_k4,4th K-param value should be loaded here which would be used in the First-pass of EGE Compression" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x148 "MEM_INIT_START,"
bitfld.long 0x148 14. "hist_odd_ram,writing 1'b1 would start the memory initialization for the Histogram memory 2 It s a self clearing bit" "0,1"
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bitfld.long 0x148 13. "hist_even_ram,writing 1'b1 would start the memory initialization for the Histogram memory 1 It s a self clearing bit" "0,1"
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bitfld.long 0x148 12. "per_iter_max_val_ram,writing 1'b1 would start the memory initialization for the 2D MAX per iteration RAM It s a self clearing bit" "0,1"
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bitfld.long 0x148 11. "per_sample_max_val_odd_ram,writing 1'b1 would start the memory initialization for the 2D MAX per sample RAM 2 It s a self clearing bit" "0,1"
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bitfld.long 0x148 10. "per_sample_max_val_even_ram,writing 1'b1 would start the memory initialization for the 2D MAX per sample RAM 1 It s a self clearing bit" "0,1"
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bitfld.long 0x148 9. "window_ram,writing 1'b1 would start the memory initialization for the window memory It s a self clearing bit" "0,1"
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bitfld.long 0x148 8. "param_ram,writing 1'b1 would start the memory initialization for the Param memory It s a self clearing bit" "0,1"
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bitfld.long 0x148 7. "dmem7,writing 1'b1 would start the memory initialization for the DMEM7 It s a self clearing bit" "0,1"
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bitfld.long 0x148 6. "dmem6,writing 1'b1 would start the memory initialization for the DMEM6 It s a self clearing bit" "0,1"
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bitfld.long 0x148 5. "dmem5,writing 1'b1 would start the memory initialization for the DMEM5 It s a self clearing bit" "0,1"
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bitfld.long 0x148 4. "dmem4,writing 1'b1 would start the memory initialization for the DMEM4 It s a self clearing bit" "0,1"
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bitfld.long 0x148 3. "dmem3,writing 1'b1 would start the memory initialization for the DMEM3 It s a self clearing bit" "0,1"
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bitfld.long 0x148 2. "dmem2,writing 1'b1 would start the memory initialization for the DMEM2 It s a self clearing bit" "0,1"
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bitfld.long 0x148 1. "dmem1,writing 1'b1 would start the memory initialization for the DMEM1" "0,1"
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bitfld.long 0x148 0. "dmem0,writing 1'b1 would start the memory initialization for the DMEM0 It s a self clearing bit" "0,1"
line.long 0x14C "MEM_INIT_DONE,"
bitfld.long 0x14C 14. "hist_odd_ram,Will be 1'b1 after cmpletion of memory initialization for hist_odd_ram" "0,1"
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bitfld.long 0x14C 13. "hist_even_ram,Will be 1'b1 after cmpletion of memory initialization for hist_even_ram" "0,1"
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bitfld.long 0x14C 12. "per_iteration_max_val_ram,Will be 1'b1 after cmpletion of memory initialization for per_iteration_max_val_ram" "0,1"
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bitfld.long 0x14C 11. "per_sample_max_val_odd_ram,Will be 1'b1 after cmpletion of memory initialization for per_sample_max_val_odd_ram" "0,1"
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bitfld.long 0x14C 10. "per_sample_max_val_even_ram,Will be 1'b1 after cmpletion of memory initialization for per_sample_max_val_even_ram" "0,1"
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bitfld.long 0x14C 9. "window_ram,Will be 1'b1 after cmpletion of memory initialization for window_ram" "0,1"
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bitfld.long 0x14C 8. "param_ram,Will be 1'b1 after cmpletion of memory initialization for param_ram" "0,1"
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bitfld.long 0x14C 7. "dmem7,Will be 1'b1 after cmpletion of memory initialization for dmem7" "0,1"
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bitfld.long 0x14C 6. "dmem6,Will be 1'b1 after cmpletion of memory initialization for dmem6" "0,1"
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bitfld.long 0x14C 5. "dmem5,Will be 1'b1 after cmpletion of memory initialization for dmem5" "0,1"
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bitfld.long 0x14C 4. "dmem4,Will be 1'b1 after cmpletion of memory initialization for dmem4" "0,1"
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bitfld.long 0x14C 3. "dmem3,Will be 1'b1 after cmpletion of memory initialization for dmem3" "0,1"
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bitfld.long 0x14C 2. "dmem2,Will be 1'b1 after cmpletion of memory initialization for dmem2" "0,1"
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bitfld.long 0x14C 1. "dmem1,Will be 1'b1 after cmpletion of memory initialization for dmem1" "0,1"
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bitfld.long 0x14C 0. "dmem0,Will be 1'b1 after cmpletion of memory initialization for dmem0" "0,1"
line.long 0x150 "MEM_INIT_STATUS,"
bitfld.long 0x150 14. "hist_odd_ram,Will be 1'b1 during memory initialization for hist_odd_ram" "0,1"
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bitfld.long 0x150 13. "hist_even_ram,Will be 1'b1 during memory initialization for hist_even_ram" "0,1"
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bitfld.long 0x150 12. "per_iteration_max_val_ram,Will be 1'b1 during memory initialization for per_iteration_max_val_ram" "0,1"
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bitfld.long 0x150 11. "per_sample_max_val_odd_ram,Will be 1'b1 during memory initialization for per_sample_max_val_odd_ram" "0,1"
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bitfld.long 0x150 10. "per_sample_max_val_even_ram,Will be 1'b1 during memory initialization for per_sample_max_val_even_ram" "0,1"
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bitfld.long 0x150 9. "window_ram,Will be 1'b1 during memory initialization for window_ram" "0,1"
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bitfld.long 0x150 8. "param_ram,Will be 1'b1 during memory initialization for param_ram" "0,1"
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bitfld.long 0x150 7. "dmem7,Will be 1'b1 during memory initialization for dmem7" "0,1"
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bitfld.long 0x150 6. "dmem6,Will be 1'b1 during memory initialization for dmem6" "0,1"
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bitfld.long 0x150 5. "dmem5,Will be 1'b1 during memory initialization for dmem5" "0,1"
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bitfld.long 0x150 4. "dmem4,Will be 1'b1 during memory initialization for dmem4" "0,1"
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bitfld.long 0x150 3. "dmem3,Will be 1'b1 during memory initialization for dmem3" "0,1"
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bitfld.long 0x150 2. "dmem2,Will be 1'b1 during memory initialization for dmem2" "0,1"
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bitfld.long 0x150 1. "dmem1,Will be 1'b1 during memory initialization for dmem1" "0,1"
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bitfld.long 0x150 0. "dmem0,Will be 1'b1 during memory initialization for dmem0" "0,1"
line.long 0x154 "LM_THRESH_VAL,"
hexmask.long.word 0x154 16.--31. 1. "dimc_thresh_val,Threshold value configured for Dimension C"
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hexmask.long.word 0x154 0.--15. 1. "dimb_thresh_val,Threshold value configured for Dimension B"
line.long 0x158 "LM_2DSTATS_BASE_ADDR,"
hexmask.long.word 0x158 16.--27. 1. "base_addr_dimc,Base Address in Stats RAM for the Threshold values corresponding to dimension C"
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hexmask.long.word 0x158 0.--11. 1. "base_addr_dimb,Base Address in Stats RAM for the Threshold values corresponding to dimension B"
line.long 0x15C "HWA_SAFETY_EN,"
bitfld.long 0x15C 3. "cfg_dmem_parity_en,Writing 1'b1 would enable the parity chekcer for the 8 DMEM memories" "0,1"
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bitfld.long 0x15C 2. "cfg_window_ram_parity_en,Writing 1'b1 enables parity for windowing RAM" "0,1"
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bitfld.long 0x15C 1. "cfg_fsm_lockstep_inv_en,Writing 1'b1 will invert the redundant FSM outputs" "0,1"
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bitfld.long 0x15C 0. "cfg_fsm_lockstep_en,Writing 1'b1 would enable the lockstep logic for FSM" "0,1"
line.long 0x160 "HWA_SAFETY_ERR_MASK,"
bitfld.long 0x160 9. "fsm_lockstep," "FSM lockstep error is not masked,FSM lockstep error is masked"
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bitfld.long 0x160 8. "window_ram," "window RAM parity error is not masked,window RAM parity error is masked"
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bitfld.long 0x160 7. "dmem7," "DMEM7 parity error is not masked,DMEM7 parity error is masked"
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bitfld.long 0x160 6. "dmem6," "DMEM6 parity error is not masked,DMEM6 parity error is masked"
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bitfld.long 0x160 5. "dmem5," "DMEM5 parity error is not masked,DMEM5 parity error is masked"
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bitfld.long 0x160 4. "dmem4," "DMEM4 parity error is not masked,DMEM4 parity error is masked"
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bitfld.long 0x160 3. "dmem3," "DMEM3 parity error is not masked,DMEM3 parity error is masked"
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bitfld.long 0x160 2. "dmem2," "DMEM2 parity error is not masked,DMEM2 parity error is masked"
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bitfld.long 0x160 1. "dmem1," "DMEM1 parity error is not masked,DMEM1 parity error is masked"
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bitfld.long 0x160 0. "dmem0," "DMEM0 parity error is not masked,DMEM0 parity error is masked"
line.long 0x164 "HWA_SAFETY_ERR_STATUS,"
bitfld.long 0x164 9. "fsm_lockstep,Indicates the FSM lockstep error (Masked status)" "0,1"
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bitfld.long 0x164 8. "window_ram,Indicates the parity error in window RAM (Masked status)" "0,1"
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bitfld.long 0x164 7. "dmem7,Indicates the parity error in dmem7 (Masked status)" "0,1"
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bitfld.long 0x164 6. "dmem6,Indicates the parity error in dmem6 (Masked status)" "0,1"
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bitfld.long 0x164 5. "dmem5,Indicates the parity error in dmem5 (Masked status)" "0,1"
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bitfld.long 0x164 4. "dmem4,Indicates the parity error in dmem4 (Masked status)" "0,1"
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bitfld.long 0x164 3. "dmem3,Indicates the parity error in dmem3 (Masked status)" "0,1"
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bitfld.long 0x164 2. "dmem2,Indicates the parity error in dmem2 (Masked status)" "0,1"
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bitfld.long 0x164 1. "dmem1,Indicates the parity error in dmem1 (Masked status)" "0,1"
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bitfld.long 0x164 0. "dmem0,Indicates the parity error in dmem0 (Masked status)" "0,1"
line.long 0x168 "HWA_SAFETY_ERR_STATUS_RAW,"
bitfld.long 0x168 9. "fsm_lockstep,Indicates the FSM lockstep error (raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 9" "0,1"
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bitfld.long 0x168 8. "window_ram,Indicates the parity error in window RAM(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 8" "0,1"
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bitfld.long 0x168 7. "dmem7,Indicates the parity error in dmem7(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 7" "0,1"
newline
bitfld.long 0x168 6. "dmem6,Indicates the parity error in dmem6(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 6" "0,1"
newline
bitfld.long 0x168 5. "dmem5,Indicates the parity error in dmem5(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 5" "0,1"
newline
bitfld.long 0x168 4. "dmem4,Indicates the parity error in dmem4(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 4" "0,1"
newline
bitfld.long 0x168 3. "dmem3,Indicates the parity error in dmem3(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 3" "0,1"
newline
bitfld.long 0x168 2. "dmem2,Indicates the parity error in dmem2(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 2" "0,1"
newline
bitfld.long 0x168 1. "dmem1,Indicates the parity error in dmem1(raw status) Set irrespective of HWA_SAFETY_ERR_MASK bit 1" "0,1"
newline
bitfld.long 0x168 0. "dmem0,Indicates the parity error in dmem0(raw status)" "0,1"
line.long 0x16C "HWA_SAFETY_DMEM0_ERR_ADDR,"
hexmask.long.word 0x16C 0.--9. 1. "dmem0_err_addr,Captures the address where parity error occured for dmem0"
line.long 0x170 "HWA_SAFETY_DMEM1_ERR_ADDR,"
hexmask.long.word 0x170 0.--9. 1. "dmem1_err_addr,Captures the address where parity error occured for dmem1"
line.long 0x174 "HWA_SAFETY_DMEM2_ERR_ADDR,"
hexmask.long.word 0x174 0.--9. 1. "dmem2_err_addr,Captures the address where parity error occured for dmem2"
line.long 0x178 "HWA_SAFETY_DMEM3_ERR_ADDR,"
hexmask.long.word 0x178 0.--9. 1. "dmem3_err_addr,Captures the address where parity error occured for dmem3"
line.long 0x17C "HWA_SAFETY_DMEM4_ERR_ADDR,"
hexmask.long.word 0x17C 0.--9. 1. "dmem4_err_addr,Captures the address where parity error occured for dmem4"
line.long 0x180 "HWA_SAFETY_DMEM5_ERR_ADDR,"
hexmask.long.word 0x180 0.--9. 1. "dmem5_err_addr,Captures the address where parity error occured for dmem5"
line.long 0x184 "HWA_SAFETY_DMEM6_ERR_ADDR,"
hexmask.long.word 0x184 0.--9. 1. "dmem6_err_addr,Captures the address where parity error occured for dmem6"
line.long 0x188 "HWA_SAFETY_DMEM7_ERR_ADDR,"
hexmask.long.word 0x188 0.--9. 1. "dmem7_err_addr,Captures the address where parity error occured for dmem7"
line.long 0x18C "HWA_SAFETY_WINDOW_RAM_ERR_ADDR,"
hexmask.long.word 0x18C 0.--10. 1. "window_ram_err_addr,Captures the address where parity error occured for window RAM"
line.long 0x190 "MEM_ACCESS_ERR_STATUS,"
bitfld.long 0x190 7. "dmem7,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem7 at the same time" "0,1"
newline
bitfld.long 0x190 6. "dmem6,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem6 at the same time" "0,1"
newline
bitfld.long 0x190 5. "dmem5,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem5 at the same time" "0,1"
newline
bitfld.long 0x190 4. "dmem4,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem4 at the same time" "0,1"
newline
bitfld.long 0x190 3. "dmem3,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem3 at the same time" "0,1"
newline
bitfld.long 0x190 2. "dmem2,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem2 at the same time" "0,1"
newline
bitfld.long 0x190 1. "dmem1,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem1 at the same time" "0,1"
newline
bitfld.long 0x190 0. "dmem0,Indicates if more than 1 master ( DMA CM4 Accelerator) are trying to access the dmem0 at the same time" "0,1"
line.long 0x194 "LOOP_CNT,"
hexmask.long.word 0x194 16.--27. 1. "loop_cnt_alt,Loop count for alternate thread"
newline
hexmask.long.word 0x194 0.--11. 1. "loop_cnt,Loop count"
line.long 0x198 "PARAMADDR,"
bitfld.long 0x198 0.--5. "paramaddr,Index of the current parameter set being executed from PARAM RAM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x19C "PARAMADDR_CPUINTR0,"
bitfld.long 0x19C 0.--5. "paramaddr,Index of the parameter set when PARAM_DONE_INTR0 is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1A0 "PARAMADDR_CPUINTR1,"
bitfld.long 0x1A0 0.--5. "paramaddr,Index of the parameter set when PARAM_DONE_INTR1 is generated" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1A4 "FSM_STATE,"
bitfld.long 0x1A4 0.--2. "fsm_state,Current state of the state machine" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "SINGLE_STEP_EN,"
bitfld.long 0x1A8 0. "single_step_en,Single step enable" "0,1"
line.long 0x1AC "SINGLE_STEP_TRIG,"
bitfld.long 0x1AC 0. "single_step_trig,This is a self clearing sofware trigger bit" "0,1"
line.long 0x1B0 "HWA_DMEM_A_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "HWA_DMEM_A_BUS_SAFETY_FI,"
hexmask.long.byte 0x1B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1B8 "HWA_DMEM_A_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x678++0x0F
line.long 0x00 "HWA_DMEM_A_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x04 "HWA_DMEM_B_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x04 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x04 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x08 "HWA_DMEM_B_BUS_SAFETY_FI,"
hexmask.long.byte 0x08 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x08 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x08 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x0C "HWA_DMEM_B_BUS_SAFETY_ERR,"
hexmask.long.byte 0x0C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
rgroup.long 0x68C++0x03
line.long 0x00 "HWA_DMEM_B_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x00 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x00 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "proxy_err,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "prot_err,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "enabled_proxy_err,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "enabled_kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "fault_ns,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "fault_type,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "fault_xid,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "fault_routeid,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "fault_privid,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "fault_clr,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x488)++0x03
line.long 0x00 "QCMULT_SCALE$1,"
hexmask.long.tbyte 0x00 0.--20. 1. "qcmult_scale0,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11 per-iteration based.."
repeat.end
repeat 12. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C )
group.long ($2+0x458)++0x03
line.long 0x00 "ICMULT_SCALE$1,"
hexmask.long.tbyte 0x00 0.--20. 1. "icmult_scale0,Complex scalars used in CMULT_MODE = 0101 0110 & 0111 In CMULT_MODE : 0101 If set CMULT_SCALE_EN is 1 the input samples are multiplied by a different complex scalar ICMULTSCALE0 QMULTSCALE0 to ICMULTSCALE11 QMULTSCALE11 per-iteration based.."
repeat.end
width 0x0B
tree.end
tree "DSS_MCRC (DSS MCRC Module Registers)"
base ad:0x83300000
group.long 0x00++0x03
line.long 0x00 "CRC_CTRL0,Contains sw reset control bit to reset PSA"
rbitfld.long 0x00 31. "NU12,Reserved" "0,1"
rbitfld.long 0x00 30. "NU11,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "NU10,Reserved" "0,1"
rbitfld.long 0x00 27.--28. "NU9,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 25.--26. "NU8,Reserved" "0,1,2,3"
rbitfld.long 0x00 24. "NU7,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "NU6,Reserved" "0,1"
rbitfld.long 0x00 22. "NU5,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "NU4,Reserved" "0,1"
rbitfld.long 0x00 19.--20. "NU3,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 17.--18. "NU2,Reserved" "0,1,2,3"
rbitfld.long 0x00 16. "NU1,Reserved" "0,1"
newline
bitfld.long 0x00 15. "CH2_CRC_SEL2,Refer 'CH2_DW_SEL' field description" "0,1"
bitfld.long 0x00 14. "CH2_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 13. "CH2_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 11.--12. "CH2_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 9.--10. "CH2_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 8. "CH2_PSA_SWREST,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 7. "CH1_CRC_SEL2,Refer 'CH1_DW_SEL' field description" "0,1"
bitfld.long 0x00 6. "CH1_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 5. "CH1_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 3.--4. "CH1_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 1.--2. "CH1_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 0. "CH1_PSA_SWREST,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
group.long 0x08++0x03
line.long 0x00 "CRC_CTRL1,Contains power down control bit"
hexmask.long 0x00 1.--31. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode"
group.long 0x10++0x03
line.long 0x00 "CRC_CTRL2,Contains channel mode. data trace enable control bits"
rbitfld.long 0x00 26.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "NU14,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 18.--23. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 16.--17. "NU13,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 10.--15. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode: 0" "reserved 1,Full-CPU mode,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved2,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable" "Data Trace disable,Data Trace enable"
newline
rbitfld.long 0x00 2.--3. "Reserved1,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode: 0" "reserved 1,Full-CPU mode,?..."
group.long 0x18++0x03
line.long 0x00 "CRC_INTS,Write one to a bit to enable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU22,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU21,Reserved" "0,1"
rbitfld.long 0x00 26. "NU20,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU19,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU18,Reserved" "0,1"
rbitfld.long 0x00 19. "NU17,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU16,Reserved" "0,1"
rbitfld.long 0x00 17. "NU15,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENS,Channel 2 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENS,Channel 1 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
bitfld.long 0x00 1. "CH1_CRCFAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x20++0x03
line.long 0x00 "CRC_INTR,Write one to a bit to disable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU30,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU29,Reserved" "0,1"
rbitfld.long 0x00 26. "NU28,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU27,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU26,Reserved" "0,1"
rbitfld.long 0x00 19. "NU25,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU24,Reserved" "0,1"
rbitfld.long 0x00 17. "NU23,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENR,Channel 2 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
newline
bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENR,Channel 1 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
newline
bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
bitfld.long 0x00 1. "CH1_CRCFAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x28++0x03
line.long 0x00 "CRC_STATUS_REG,Contains interrupt flags for different types of interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU38,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU37,Reserved" "0,1"
rbitfld.long 0x00 26. "NU36,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU35,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU34,Reserved" "0,1"
rbitfld.long 0x00 19. "NU33,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU32,Reserved" "0,1"
rbitfld.long 0x00 17. "NU31,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUT,Channel 2 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 9. "CH2_CRCFAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUT,Channel 1 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
bitfld.long 0x00 1. "CH1_CRCFAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x30++0x03
line.long 0x00 "CRC_INT_OFFSET_REG,Contains the interrupt offset vector address"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "OFSTREG,CRC Interrupt Offset"
rgroup.long 0x38++0x03
line.long 0x00 "CRC_BUSY,Contains the busy flag for each channel"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "NU40,Reserved" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved3,Reserved"
bitfld.long 0x00 16. "NU39,Reserved" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved2,Reserved"
bitfld.long 0x00 8. "Ch2_BUSY,Ch2_BUSY" "0,1"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "CH1_BUSY,CH1_BUSY" "0,1"
group.long 0x40++0x13
line.long 0x00 "CRC_PCOUNT_REG1,Channel 1 preload register for the pattern count"
hexmask.long.word 0x00 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register"
line.long 0x04 "CRC_SCOUNT_REG1,Channel 1 preload register for the sector count"
hexmask.long.word 0x04 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register"
line.long 0x08 "CRC_CURSEC_REG1,Channel 1 current sector register contains the sector number which causes CRC failure"
hexmask.long.word 0x08 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register"
line.long 0x0C "CRC_WDTOPLD1,Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register"
line.long 0x10 "CRC_BCTOPLD1,Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x10 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Regis- ter"
group.long 0x60++0x33
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA signature low register"
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA signature high register"
line.long 0x08 "CRC_REGL1,Channel 1 CRC value low register"
line.long 0x0C "CRC_REGH1,Channel 1 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL1,Channel 1 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH1,Channel 1 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL1,Channel 1 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH1,Channel 1 un-compressed raw data high register"
line.long 0x20 "CRC_PCOUNT_REG2,Channel 2 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,Channel 2 Pattern Counter Preload Register"
line.long 0x24 "CRC_SCOUNT_REG2,Channel 2 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register"
line.long 0x28 "CRC_CURSEC_REG2,Channel 2 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register"
line.long 0x2C "CRC_WDTOPLD2,Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register"
line.long 0x30 "CRC_BCTOPLD2,Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Regis- ter"
group.long 0xA0++0x33
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA signature low register"
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA signature high register"
line.long 0x08 "CRC_REGL2,Channel 2 CRC value low register"
line.long 0x0C "CRC_REGH2,Channel 2 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL2,Channel 2 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH2,Channel 2 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL2,Channel 2 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH2,Channel 2 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG3,Channel 3 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU41,Reserved"
line.long 0x24 "CRC_SCOUNT_REG3,Channel 3 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU42,Reserved"
line.long 0x28 "CRC_CURSEC_REG3,Channel 3 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU43,Reserved"
line.long 0x2C "CRC_WDTOPLD3,Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU44,Reserved"
line.long 0x30 "CRC_BCTOPLD3,Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU45,Reserved"
rgroup.long 0xE0++0x33
line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA signature low register"
line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA signature high register"
line.long 0x08 "CRC_REGL3,Channel 3 CRC value low register"
line.long 0x0C "CRC_REGH3,Channel 3 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL3,Channel 3 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH3,Channel 3 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL3,Channel 3 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH3,Channel 3 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG4,Channel 4 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU54,Reserved"
line.long 0x24 "CRC_SCOUNT_REG4,Channel 4 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU55,Reserved"
line.long 0x28 "CRC_CURSEC_REG4,Channel 4 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU56,Reserved"
line.long 0x2C "CRC_WDTOPLD4,Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU57,Reserved"
line.long 0x30 "CRC_BCTOPLD4,Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU58,Reserved"
rgroup.long 0x120++0x27
line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA signature low register"
line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA signature high register"
line.long 0x08 "CRC_REGL4,Channel 4 CRC value low register"
line.long 0x0C "CRC_REGH4,Channel 4 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL4,Channel 4 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH4,Channel 4 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL4,Channel 4 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH4,Channel 4 un-compressed raw data high Register"
line.long 0x20 "MCRC_BUS_SEL,Disables either or all tracing of data buses"
hexmask.long 0x20 3.--31. 1. "NU67,Reserved"
bitfld.long 0x20 2. "MEn,MEn" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled"
newline
bitfld.long 0x20 1. "DTCMEn,DTCMEn" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.."
bitfld.long 0x20 0. "ITCMEn,ITCMEn" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled"
line.long 0x24 "MCRC_RESERVED,0x144 to 0x1FF is reserved area"
width 0x0B
tree.end
tree "DSS_PCR (DSS PCR Module Registers)"
base ad:0x6F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "DSS_RCM (DSS RCM Module Registers)"
base ad:0x6000000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x27
line.long 0x00 "DSP_PD_CTRL,"
bitfld.long 0x00 4. "proc_halt,Controls the unhalting on the processor during the power-up sequence" "The processor is unhalted at the end of the..,The DSP is kept in halt state at the end of the.."
newline
bitfld.long 0x00 0. "interrupt_mask,Masks interrupts to the DSP" "Send the interrupts to the DSP after power on,Mask interrupts to the DSP before powering off.."
line.long 0x04 "DSP_PD_TRIGGER_WAKUP,"
bitfld.long 0x04 0. "wakeup_trigger,Write pulse bit field: Trigger Power Up of the DSP" "0,1"
line.long 0x08 "DSP_PD_TRIGGER_SLEEP,"
bitfld.long 0x08 0. "sleep_trigger,Write pulse bit field: Trigger Power Down of the DSP" "0,1"
line.long 0x0C "DSP_PD_STATUS,"
bitfld.long 0x0C 8. "pwrsm_dbg_ovrd,Status bit indicating if there is an override for the DSP from Debug SubSystem" "No override from DebugSS,Override from DebugSS"
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bitfld.long 0x0C 4.--5. "pd_status,Power Mode status of DSP" "Powered OFF,Transitioning from OFF to ON..,Transitioning from ON to OFF..,Powered ON"
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bitfld.long 0x0C 0. "proc_halted,Processor is halted" "0,1"
line.long 0x10 "DSP_PD_CTRL_MISC0,"
bitfld.long 0x10 24.--29. "pwrsm_grst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of GRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 18.--23. "pwrsm_porrst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of POR during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 12.--17. "pwrsm_lrst_assertcnt,TI Internal Feature No of cycles to wait after assertion of LRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 6.--11. "pwrsm_grst_assertcnt,TI Internal Feature No of cycles to wait after assertion of GRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 0.--5. "pwrsm_porrst_assertcnt,TI Internal Feature No of cycles to wait after assertion of POR during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x14 "DSP_PD_CTRL_MISC1,"
bitfld.long 0x14 24.--26. "iso_sync_bypass,HW RnD reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20.--22. "rst_sync_bypass,HW RnD reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 18. "pwrsm_lresetout_mask,TI Internal Feature" "0,1"
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bitfld.long 0x14 12.--17. "pwrsm_isoen_assertcnt,TI Internal Feature No of cycles to wait after assertion of ISO_ENABLE during GEM power-down sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 6.--11. "pwrsm_clkstop_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of GEM_CLK_STOP_REQ during GEM Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 0.--5. "pwrsm_lrst_deassertcnt,TI Internal Feature No of cycles to wait after de-assertion of LRSTN during DSP Power-up sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x18 "DSP_PD_STATUS_MISC0,"
bitfld.long 0x18 17. "pwrsm_lrstout,TI Internal Feature Lreset output indication from GEM" "0,1"
newline
bitfld.long 0x18 16. "pwrsm_c66_clkstop_ack,TI Internal Feature Clock stop request ack from GEM" "0,1"
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bitfld.long 0x18 15. "pwrsm_sdma_async2scr_clkstop_ack,TI Internal Feature SDMA slave disable Done from clock stop ack from the master port of the async bridge present in the SDMA port" "0,1"
newline
bitfld.long 0x18 14. "pwrsm_sdma_async2rcm_clkstop_req,TI Internal Feature SDMA Slave disable Ack from Interconnect" "0,1"
newline
bitfld.long 0x18 13. "pwrsm_sdma_scr2async_clkstop_req,TI Internal Feature Clock Stop request from SCR to SDMA Async Bridge" "0,1"
newline
bitfld.long 0x18 12. "pwrsm_mem_agoodout,TI Internal Feature Memory AGOOD Output from GEM (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 11. "pwrsm_mem_aonout,TI Internal Feature Memory AON Output from GEM (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 10. "pwrsm_mem_pgoodout,TI Internal Feature Memory PGOOD Output from DSP (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 9. "pwrsm_mem_ponout,TI Internal Feature Memory PON Output from DSP (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 8. "pwrsm_pgoodout,TI Internal Feature Logic PGOOD Output from DSP (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 7. "pwrsm_ponout,TI Internal Feature Logic PON Output from DSP (synchronized to Bus clock)" "0,1"
newline
bitfld.long 0x18 0.--5. "state,This is the internal state of the DSP power State machine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "DSP_PD_WAKEUP_MASK0,"
line.long 0x20 "DSP_PD_WAKEUP_MASK1,"
line.long 0x24 "DSP_PD_WAKEUP_MASK2,"
group.long 0x48++0x10B
line.long 0x00 "DSP_PD_WAKEUP_STATUS0_CLR,"
line.long 0x04 "DSP_PD_WAKEUP_STATUS1_CLR,"
line.long 0x08 "DSP_PD_WAKEUP_STATUS2_CLR,"
line.long 0x0C "DSP_PD_MISSED_EVENT_MASK0,"
line.long 0x10 "DSP_PD_MISSED_EVENT_MASK1,"
line.long 0x14 "DSP_PD_MISSED_EVENT_MASK2,"
line.long 0x18 "DSP_PD_MISSED_EVENT_STATUS0,"
line.long 0x1C "DSP_PD_MISSED_EVENT_STATUS1,"
line.long 0x20 "DSP_PD_MISSED_EVENT_STATUS2,"
line.long 0x24 "DSP_RST_CAUSE,"
abitfld.long 0x24 16.--23. "por_cause,DSP POR reset Bitwise Indication : Bit" "0x00=Por Reset Bit,0x01=Sub system Reset from TOPRCM Bit,0x02=Reset from DSS_RCM,0x03=Reset from Power FSM Bit,0x04=Reset from STC FSM"
newline
abitfld.long 0x24 8.--15. "grst_cause,DSP Greset Bitwise Indication : Bit" "0x00=Por Reset Bit,0x01=Sub system Reset from TOPRCM Bit,0x02=Reset from DSS_RCM,0x03=Reset from Power FSM Bit,0x04=Reset from STC FSM"
newline
abitfld.long 0x24 0.--7. "lrst_cause,DSP Lreset Bitwise Indication : Bit" "0x00=Por Reset Bit,0x01=Sub system Reset from TOPRCM Bit,0x02=Reset from DSS_RCM,0x03=Reset from Debugss Bit,0x04=Reset from Power FSM Bit,0x05=Reset from STC FSM"
line.long 0x28 "DSP_RST_CAUSE_CLR,"
bitfld.long 0x28 0. "clear,Write pulse bit field: Write 0x1 to clear the reset cause register for any previous resets : Its a wspecial access type write to this field will generate a pulse" "0,1"
line.long 0x2C "DSP_STC_PBIST_CTRL,"
bitfld.long 0x2C 16.--21. "pbist_tmode_vlct_assertcnt,No of clocks (in terms of 200 MHz DSPSS Bus clock) after asserting GEM TMODE VLCT signal before proceeding to the next state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x2C 10.--15. "pbist_tmode_vlct_deassertcnt,No of clocks (in terms of 200 MHz DSPSS Bus clock) after De-asserting GEM TMODE VLCT signal before proceeding to the next state" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x2C 6.--9. "pbist_selftest_key,[4:1] DSP PBIST SELFTEST KEY = 4'b1010" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x2C 5. "stc_b2b_en,Enables back to Back STC.Needs to be set to 1 for self test" "0,1"
newline
bitfld.long 0x2C 4. "stc_clk_stp_ack_mask,Mask bit for ignoring the clock stop ack from GEM" "0,1"
newline
bitfld.long 0x2C 3. "proc_halt,Configuration to halt the state machine before the final de-assertion of LRST to enable program download" "0,1"
newline
bitfld.long 0x2C 2. "stc_boot_en,Enable GEM STC during GEM power UP" "0,1"
newline
bitfld.long 0x2C 0.--1. "mode_enable,Enable for PBIST and STC" "0,1,2,3"
line.long 0x30 "DSP_STC_PBIST_STATUS,"
bitfld.long 0x30 2.--7. "stc_pbist_sm_status,PBIST status from GEM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x30 0.--1. "pbist_status,Current state of STC PBIST state machine" "0,1,2,3"
line.long 0x34 "DSP_STC_PBIST_CTRL_MISC0,"
hexmask.long.word 0x34 16.--31. 1. "byp_value,DSP PBIST STC misc Control"
newline
hexmask.long.word 0x34 0.--15. 1. "byp_en,DSP PBIST STC misc Control"
line.long 0x38 "DSP_STC_PBIST_CTRL_MISC1,"
bitfld.long 0x38 4.--9. "sm_ovr_val,TI Internal Register.Reserved for HW RnD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x38 3. "sm_ovr_en,TI Internal Register.Reserved for HW RnD" "0,1"
line.long 0x3C "DSP_STC_PBIST_START,"
bitfld.long 0x3C 0. "sm_trig,Write pulse bit field: Trigger pulse for the STC PBIST state machine" "0,1"
line.long 0x40 "DSP_STC_PBIST_STATUS_CLR,"
bitfld.long 0x40 0. "clear,Write pulse bit field: Clear bit for PBIST Status : Its a wspecial access type write to this field will generate a pulse" "0,1"
line.long 0x44 "DSS_DSP_CLK_SRC_SEL,"
hexmask.long.word 0x44 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS DSP"
line.long 0x48 "DSS_HWA_CLK_SRC_SEL,"
bitfld.long 0x48 0.--2. "clksrcsel,Select line for selecting source clock for DSS HWA" "TOPRCM_CR5_CLK,?,?,?,?,?,?,TOPRCM_SYS_CLK"
line.long 0x4C "DSS_RTIA_CLK_SRC_SEL,"
hexmask.long.word 0x4C 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS_RTIA"
line.long 0x50 "DSS_RTIB_CLK_SRC_SEL,"
hexmask.long.word 0x50 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS RTIB"
line.long 0x54 "DSS_WDT_CLK_SRC_SEL,"
hexmask.long.word 0x54 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS Watchdog"
line.long 0x58 "DSS_SCIA_CLK_SRC_SEL,"
hexmask.long.word 0x58 0.--11. 1. "clksrcsel,Select line for selecting source clock for DSS SCIA"
line.long 0x5C "DSS_DSP_CLK_DIV_VAL,"
hexmask.long.word 0x5C 0.--11. 1. "clkdiv,Divider value for DSS DSP selected clock"
line.long 0x60 "DSS_RTIA_CLK_DIV_VAL,"
hexmask.long.word 0x60 0.--11. 1. "clkdiv,Divider value for DSS RTIA selected clock"
line.long 0x64 "DSS_RTIB_CLK_DIV_VAL,"
hexmask.long.word 0x64 0.--11. 1. "clkdiv,Divider value for DSS RTIB selected clock"
line.long 0x68 "DSS_WDT_CLK_DIV_VAL,"
hexmask.long.word 0x68 0.--11. 1. "clkdiv,Divider value for DSS Watchdog selected clock"
line.long 0x6C "DSS_SCIA_CLK_DIV_VAL,"
hexmask.long.word 0x6C 0.--11. 1. "clkdiv,Divider value for DSS SCIA selected clock"
line.long 0x70 "DSS_DSP_CLK_GATE,"
bitfld.long 0x70 0.--2. "gated,Clock gatring config for DSS DSP" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x74 "DSS_HWA_CLK_GATE,"
bitfld.long 0x74 0.--2. "gated,Clock gatring config for DSS HWA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x78 "DSS_RTIA_CLK_GATE,"
bitfld.long 0x78 0.--2. "gated,Clock gatring config for DSS RTA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x7C "DSS_RTIB_CLK_GATE,"
bitfld.long 0x7C 0.--2. "gated,Clock gatring config for DSS RTIB Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x80 "DSS_WDT_CLK_GATE,"
bitfld.long 0x80 0.--2. "gated,Clock gatring config for DSS Watchdog Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x84 "DSS_SCIA_CLK_GATE,"
bitfld.long 0x84 0.--2. "gated,Clock gatring config for DSS SCIA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x88 "DSS_CBUFF_CLK_GATE,"
bitfld.long 0x88 0.--2. "gated,Not Supported" "0,1,2,3,4,5,6,7"
line.long 0x8C "DSS_DSP_CLK_STATUS,"
hexmask.long.byte 0x8C 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS DSP Clock"
newline
hexmask.long.byte 0x8C 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS DSP Clock"
line.long 0x90 "DSS_HWA_CLK_STATUS,"
bitfld.long 0x90 0.--1. "clkinuse,Status shows the source clock slected for DSS HWA Clock" "0,1,2,3"
line.long 0x94 "DSS_RTIA_CLK_STATUS,"
hexmask.long.byte 0x94 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS RTIA Clock"
newline
hexmask.long.byte 0x94 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS RTIA Clock"
line.long 0x98 "DSS_RTIB_CLK_STATUS,"
hexmask.long.byte 0x98 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS RTIB Clock"
newline
hexmask.long.byte 0x98 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS RTIB Clock"
line.long 0x9C "DSS_WDT_CLK_STATUS,"
hexmask.long.byte 0x9C 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS Watchdog Clock"
newline
hexmask.long.byte 0x9C 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS Watchdog Clock"
line.long 0xA0 "DSS_SCIA_CLK_STATUS,"
hexmask.long.byte 0xA0 8.--15. 1. "currdivider,Status shows the current divider value choosen for DSS SCIA Clock"
newline
hexmask.long.byte 0xA0 0.--7. 1. "clkinuse,Status shows the source clock slected for DSS SCIA Clock"
line.long 0xA4 "DSS_DSP_RST_CTRL,"
bitfld.long 0xA4 8.--10. "assert_local,Local Reset control for DSS DSP Data should be loaded as multibit" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0xA4 4.--6. "assert_global,Global Reset control forDSS DSP Data should be loaded as multibit" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0xA4 0.--2. "assert_por,Power on Reset control for DSS DSP Data should be loaded as multibit" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0xA8 "DSS_ESM_RST_CTRL,"
bitfld.long 0xA8 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xAC "DSS_SCIA_RST_CTRL,"
bitfld.long 0xAC 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xB0 "DSS_RTIA_RST_CTRL,"
bitfld.long 0xB0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xB4 "DSS_RTIB_RST_CTRL,"
bitfld.long 0xB4 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xB8 "DSS_WDT_RST_CTRL,"
bitfld.long 0xB8 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xBC "DSS_DCCA_RST_CTRL,"
bitfld.long 0xBC 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xC0 "DSS_DCCB_RST_CTRL,"
bitfld.long 0xC0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xC4 "DSS_MCRC_RST_CTRL,"
bitfld.long 0xC4 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0xC8 "DSP_DFT_DIV_CTRL,"
bitfld.long 0xC8 4.--6. "clk_disable,DSP DFT Control for clock_disable" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xC8 0.--3. "div_factor,DSP DFT Control for div factor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "DSS_DSP_L2_PD_CTRL,"
bitfld.long 0xCC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xCC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xCC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xD0 "DSS_L3_BANKA0_PD_CTRL,"
bitfld.long 0xD0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xD4 "DSS_L3_BANKA1_PD_CTRL,"
bitfld.long 0xD4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xD8 "DSS_L3_BANKA2_PD_CTRL,"
bitfld.long 0xD8 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD8 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xD8 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xDC "DSS_L3_BANKA3_PD_CTRL,"
bitfld.long 0xDC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xDC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xDC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xE0 "DSS_L3_BANKB0_PD_CTRL,"
bitfld.long 0xE0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xE4 "DSS_L3_BANKB1_PD_CTRL,"
bitfld.long 0xE4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xE8 "DSS_L3_BANKB2_PD_CTRL,"
bitfld.long 0xE8 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE8 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE8 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xEC "DSS_L3_BANKB3_PD_CTRL,"
bitfld.long 0xEC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xEC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xEC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xF0 "DSS_L3_BANKC0_PD_CTRL,"
bitfld.long 0xF0 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF0 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF0 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xF4 "DSS_L3_BANKC1_PD_CTRL,"
bitfld.long 0xF4 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF4 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF4 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xF8 "DSS_L3_BANKC2_PD_CTRL,"
bitfld.long 0xF8 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0xFC "DSS_L3_BANKC3_PD_CTRL,"
bitfld.long 0xFC 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xFC 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xFC 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x100 "DSS_L3_BANKD0_PD_CTRL,"
bitfld.long 0x100 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x104 "DSS_L3_BANKD1_PD_CTRL,"
bitfld.long 0x104 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x108 "DSS_L3_BANKD2_PD_CTRL,"
bitfld.long 0x108 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x108 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x108 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
group.long 0x158++0x43
line.long 0x00 "DSS_HWA_PD_CTRL,"
bitfld.long 0x00 16.--18. "pgoodin,SW Control for <IP>_PD_CTRL Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "ponin,SW Control for <IP>_PD_CTRL Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "agoodin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "aonin,SW Control for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "iso,SW Control for <IP>_PD_CTRL Isolation" "0,1,2,3,4,5,6,7"
line.long 0x04 "DSS_DSP_L2_PD_STATUS,"
bitfld.long 0x04 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x04 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x08 "DSS_L3_BANKA0_PD_STATUS,"
bitfld.long 0x08 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x08 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x08 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x08 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x0C "DSS_L3_BANKA1_PD_STATUS,"
bitfld.long 0x0C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x0C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x0C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x0C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x10 "DSS_L3_BANKA2_PD_STATUS,"
bitfld.long 0x10 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x10 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x10 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x10 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x14 "DSS_L3_BANKA3_PD_STATUS,"
bitfld.long 0x14 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x14 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x14 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x14 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x18 "DSS_L3_BANKB0_PD_STATUS,"
bitfld.long 0x18 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x18 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x18 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x18 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x1C "DSS_L3_BANKB1_PD_STATUS,"
bitfld.long 0x1C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x1C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x1C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x1C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x20 "DSS_L3_BANKB2_PD_STATUS,"
bitfld.long 0x20 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x20 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x20 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x20 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x24 "DSS_L3_BANKB3_PD_STATUS,"
bitfld.long 0x24 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x24 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x24 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x24 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x28 "DSS_L3_BANKC0_PD_STATUS,"
bitfld.long 0x28 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x28 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x28 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x28 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x2C "DSS_L3_BANKC1_PD_STATUS,"
bitfld.long 0x2C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x2C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x2C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x2C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x30 "DSS_L3_BANKC2_PD_STATUS,"
bitfld.long 0x30 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x30 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x30 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x30 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x34 "DSS_L3_BANKC3_PD_STATUS,"
bitfld.long 0x34 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x34 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x34 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x34 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x38 "DSS_L3_BANKD0_PD_STATUS,"
bitfld.long 0x38 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x38 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x38 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x38 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x3C "DSS_L3_BANKD1_PD_STATUS,"
bitfld.long 0x3C 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x3C 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x3C 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x3C 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x40 "DSS_L3_BANKD2_PD_STATUS,"
bitfld.long 0x40 3. "agoodin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x40 2. "aonin,Status for sticky control <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
newline
bitfld.long 0x40 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x40 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
rgroup.long 0x1A0++0x43
line.long 0x00 "DSS_HWA_PD_STATUS,"
bitfld.long 0x00 3. "pgoodout,Status for <IP>_PD_CTRL Power up CRTL1" "0,1"
newline
bitfld.long 0x00 2. "ponout,Status for <IP>_PD_CTRL Power up CRTL0" "0,1"
newline
bitfld.long 0x00 1. "agoodout,Status for <IP>_PD_CTRL Memory Array Power up CRTL1" "0,1"
newline
bitfld.long 0x00 0. "aonout,Status for <IP>_PD_CTRL Memory Array Power up CRTL0" "0,1"
line.long 0x04 "DSS_DSP_TRCCLK_DIVRATIO,"
bitfld.long 0x04 0.--3. "divratio,DSP Trace Clock Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "DSS_DSP_TCLK_DIVRATIO,"
bitfld.long 0x08 0.--3. "divratio,DSP TCLK Divide Ratio" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "DSS_DSP_DITHERED_CLK_CTRL,"
bitfld.long 0x0C 31. "load,Write pulse bit field: DSP Dithered Clock LFSR Load" "0,1"
newline
bitfld.long 0x0C 28.--30. "enable,DSP Dithered Clock Enable" "Disabled,?,?,?,?,?,?,Enabled"
newline
hexmask.long 0x0C 0.--27. 1. "seed,DSP Dithered Clock LFSR Seed"
line.long 0x10 "DSS_L3_PD_CTRL_STICKYBIT,"
bitfld.long 0x10 0.--2. "set,Sticky bit for DSS L3 PD CTRL" "0,1,2,3,4,5,6,7"
line.long 0x14 "DSP_PD_CTRL_MISC2,"
hexmask.long.word 0x14 16.--31. 1. "pwrsm_agood_assertcnt,Value of agood asertion delay"
newline
hexmask.long.word 0x14 0.--15. 1. "pwrsm_pgood_assertcnt,Value of pgood asertion delay"
line.long 0x18 "DSP_PD_CTRL_MISC3,"
bitfld.long 0x18 16. "lreset_req_gate,Gate the lreset request from GEM" "0,1"
newline
hexmask.long.word 0x18 0.--15. 1. "pwrs_pd_waitcnt,Value of power down wait delay"
line.long 0x1C "DSP_PD_CTRL_OVERRIDE0,"
bitfld.long 0x1C 24.--29. "state_bypass_val,DSS DSP power FSM state bypass control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.tbyte 0x1C 0.--23. 1. "bypass_val,DSS DSP power FSM bypass control"
line.long 0x20 "DSP_PD_CTRL_OVERRIDE1,"
bitfld.long 0x20 24. "state_bypass_en,DSS DSP power FSM state bypass control enable.For debug pupose" "0,1"
newline
hexmask.long.tbyte 0x20 0.--23. 1. "bypass_en,DSS DSP power FSM bypass control enable.For debug pupose"
line.long 0x24 "DSP_PD_CTRL_OVERRIDE2,"
bitfld.long 0x24 0.--2. "override_enable,DSS DSP power FSM override enable .For debug pupose" "0,1,2,3,4,5,6,7"
line.long 0x28 "DSS_HWA_RST_CTRL,"
bitfld.long 0x28 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x2C "DSS_HWA_RST_CTRL,"
bitfld.long 0x2C 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x30 "DSS_EDMA_RST_CTRL,"
bitfld.long 0x30 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x34 "DSS_EDMA_RST_CTRL,"
bitfld.long 0x34 0.--2. "assert,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x38 "DSS_EDMA_RST_CTRL,"
bitfld.long 0x38 4.--6. "assert_tc1,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x38 0.--2. "assert_tc0,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x3C "DSS_EDMA_RST_CTRL,"
bitfld.long 0x3C 4.--6. "assert_tc1,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x3C 0.--2. "assert_tc0,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x40 "DSS_TPTCC_RST_CTRL,"
bitfld.long 0x40 20.--22. "assert_tc5,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 16.--18. "assert_tc4,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 12.--14. "assert_tc3,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 8.--10. "assert_tc2,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 4.--6. "assert_tc1,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
newline
bitfld.long 0x40 0.--2. "assert_tc0,This register is for Debug Purposes only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x3C)++0x03
line.long 0x00 "DSP_PD_WAKEUP_STATUS$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "DSS_RTIA (DSS RTIA Module Registers)"
base ad:0x6F7A000
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "DSS_RTIB (DSS RTIB Module Registers)"
base ad:0x6F7A100
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "DSS_SCIA (DSS SCIA Module Registers)"
base ad:0x6F7B000
group.long 0x00++0x5F
line.long 0x00 "SCIGCR0,The SCIGCR0 register defines the module reset"
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
newline
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
line.long 0x04 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
rbitfld.long 0x04 26.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
newline
bitfld.long 0x04 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
newline
rbitfld.long 0x04 18.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
newline
bitfld.long 0x04 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
newline
rbitfld.long 0x04 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
newline
bitfld.long 0x04 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function" "0,1"
newline
bitfld.long 0x04 7. "SW_nRESET,Software reset (active low)" "0,1"
newline
rbitfld.long 0x04 6. "RESERVED1,Reserved" "0,1"
newline
bitfld.long 0x04 5. "CLOCK,SCI internal clock enable" "0,1"
newline
bitfld.long 0x04 4. "STOP,SCI number of stop bits" "0,1"
newline
bitfld.long 0x04 3. "PARITY,SCI parity odd/even selection" "0,1"
newline
bitfld.long 0x04 2. "PARITY_ENA,SCI parity enable" "0,1"
newline
bitfld.long 0x04 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0,1"
newline
bitfld.long 0x04 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0,1"
line.long 0x08 "RESERVED1,Reserved"
line.long 0x0C "SCISETINT,SCI Set Interrupt Register"
rbitfld.long 0x0C 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x0C 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request for address and data frames"
newline
bitfld.long 0x0C 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x0C 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x0C 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 8. "SET_TX_INT,Set Transmitter interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x0C 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x0C 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x0C 0. "SET_BRKDT_INT,Set Break-detect interrupt" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x10 "SCICLEARINT,SCI Clear Interrupt Register"
rbitfld.long 0x10 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 25. "CLR_OE_INT,Clear Overrun-Error Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 24. "CLR_PE_INT,Clear Parity Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
rbitfld.long 0x10 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 18. "CLR_RX_DMA_ALL,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request for address frames"
newline
bitfld.long 0x10 17. "CLR_RX_DMA,Clear RX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x10 16. "CLR_TX_DMA,Clear TX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
newline
rbitfld.long 0x10 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 9. "CLR_RX_INT,Clear Receiver interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 8. "CLR_TX_INT,Clear Transmitter interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
rbitfld.long 0x10 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x10 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x10 0. "CLR_BRKDT_INT,Clear Break-detect interrupt" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x14 "SCISETINTLVL,SCI Set Interrupt Level Register"
rbitfld.long 0x14 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
bitfld.long 0x14 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
bitfld.long 0x14 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
newline
rbitfld.long 0x14 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read)" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x14 15. "SET_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x14 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
line.long 0x18 "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
rbitfld.long 0x18 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x18 15. "CLR_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x18 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x18 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
line.long 0x1C "SCIFLR,SCI Flags Register"
rbitfld.long 0x1C 27.--31. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 26. "FE,SCI framing error flag Read" "No effect,Clears this bit to 0"
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rbitfld.long 0x1C 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
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rbitfld.long 0x1C 24. "PE,SCI parity error flag" "0,1"
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hexmask.long.word 0x1C 13.--23. 1. "RESERVED2,Reserved"
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rbitfld.long 0x1C 12. "RXWAKE,Receiver wake-up detect flag" "0,1"
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rbitfld.long 0x1C 11. "TX_EMPTY,Transmitter empty flag" "0,1"
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bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wake-up method select" "0,1"
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rbitfld.long 0x1C 9. "RXRDY,SCI receiver ready flag" "0,1"
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rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag" "0,1"
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rbitfld.long 0x1C 4.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame" "0,1"
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rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state" "0,1"
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rbitfld.long 0x1C 1. "WAKEUP,Wake-up flag" "0,1"
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rbitfld.long 0x1C 0. "BRKDT,SCI break-detect flag" "0,1"
line.long 0x20 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x20 0.--3. "INTVECT0,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x24 0.--3. "INTVECT1,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "SCICHAR,SCI Character Control Register"
hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x28 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
line.long 0x2C "SCIBAUD,SCI Baud Rate Selection Register"
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED,Reserved"
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hexmask.long.tbyte 0x2C 0.--23. 1. "BAUD,SCI 24-bit baud selection"
line.long 0x30 "SCIED,Receiver Emulation Data Buffer"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x30 0.--7. 1. "ED,Receiver Emulation Data Buffer"
line.long 0x34 "SCIRD,Receiver Data Buffer"
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x34 0.--7. 1. "RD,Contains received data"
line.long 0x38 "SCITD,Transmit Data Buffer Register"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x38 0.--7. 1. "TD,Contains Data to be transmitted"
line.long 0x3C "SCIPIO0,SCI Pin I/O Control Register 0"
hexmask.long 0x3C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x3C 2. "TX_FUNC,Defines the function of pin SCITX" "SCIRX is a general-purpose digital I/O pin,SCIRX is the SCI receive pin"
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bitfld.long 0x3C 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x3C 0. "CLK_FUNC,Clock function" "SCICLK is a general-purpose digital I/O pin,SCICLK is the SCI serial clock pin"
line.long 0x40 "SCIPIO1,SCI Pin I/O Control Register 1"
hexmask.long 0x40 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x40 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0)" "SCITX is a general-purpose input pin,SCITX is a general-purpose output pin"
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bitfld.long 0x40 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x40 0. "CLK_DIR,Clock data direction" "0,1"
line.long 0x44 "SCIPIO2,SCI Pin I/O Control Register 2"
hexmask.long 0x44 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x44 2. "TX_DATA_IN,Contains current value on the SCITX pin" "SCITX value is logic low,SCITX value is logic high"
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bitfld.long 0x44 1. "RX_DATA_IN,Contains current value on the SCIRX pin" "SCIRX value is logic low,SCIRX value is logic high"
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bitfld.long 0x44 0. "CLK_DATA_IN,Contains the current value on pin SCICLK" "Pin SCICLK value is logic low,Pin SCICLK value is logic high"
line.long 0x48 "SCIPIO3,SCI Pin I/O Control Register 3"
hexmask.long 0x48 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x48 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "Output value on SCITX is a 0 (logic low),Output value on SCITX is a 1 (logic high)"
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bitfld.long 0x48 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "Output value on SCIRX is 0 (logic low),Output value on SCIRX is 1 (logic high)"
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bitfld.long 0x48 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "Output value on SCICLK is a 0 (logic low),Output value on SCICLK is a 1 (logic high)"
line.long 0x4C "SCIPIO4,SCI Pin I/O Control Register 4"
hexmask.long 0x4C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4C 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
line.long 0x50 "SCIPIO5,SCI Pin I/O Control Register 5"
hexmask.long 0x50 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x50 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
line.long 0x54 "SCIPIO6,SCI Pin I/O Control Register 6"
hexmask.long 0x54 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x54 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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bitfld.long 0x54 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x54 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
line.long 0x58 "SCIPIO7,SCI Pin I/O Control Register 7"
hexmask.long 0x58 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x58 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX" "Pull Control on SCITX pin is enabled,Pull Control on SCITX pin is disabled"
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bitfld.long 0x58 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX" "Pull Control on SCIRX pin is enabled,Pull Control on SCIRX pin is disabled"
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bitfld.long 0x58 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK" "Pull Control on SCICLK pin is enabled,Pull Control on SCICLK pin is disabled"
line.long 0x5C "SCIPIO8,SCI Pin I/O Control Register 8"
hexmask.long 0x5C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x5C 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX" "Pull-Down is on SCITX pin,Pull-Up is on SCITX pin"
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bitfld.long 0x5C 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX" "Pull-Down is on SCIRX pin,Pull-Up is on SCIRX pin"
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bitfld.long 0x5C 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK" "Pull-Down is on SCICLK pin,Pull-Up is on SCICLK pin"
group.long 0x80++0x03
line.long 0x00 "SCIPIO9,SCI Pin I/O Control Register 9"
hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 2. "TX_SL,This bit controls the slew rate for the SCITX pin" "The normal output buffer is used for SCITX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 1. "RX_SL,This bit controls the slew rate for the SCIRX pin" "The normal output buffer is used for SCIRX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin" "The normal output buffer is used for SCICLK pin,The output buffer with slew control is used for.."
group.long 0x90++0x03
line.long 0x00 "SCIIODCTRL,SCI IO DFT Control"
rbitfld.long 0x00 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 26. "FEN,Frame Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 25. "PEN,Parity Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 24. "BRKDT_ENA,Break Detect Error Enable" "No effect,This bit is used to.."
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rbitfld.long 0x00 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry" "0,1,2,3"
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bitfld.long 0x00 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 12.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "LBP_ENA,Module loopback enable" "Digital loopback is enabled,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x00 0. "RXP_ENA,Module Analog loopback through receive pin enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
repeat 8. (list 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "DSS_TPCC_A (DSS TPCCA Module Registers)"
base ad:0x6100000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
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bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
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bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
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bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
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bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
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bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
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bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
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bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
newline
hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
newline
hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
newline
bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
newline
bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
newline
bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
newline
bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
newline
bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
newline
bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
newline
bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
newline
bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
newline
bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
newline
bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
newline
bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
newline
bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
newline
bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
newline
bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
newline
bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
newline
bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
newline
bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
newline
bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
newline
bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
tree "DSS_TPCC_B (DSS TPCCB Module Registers)"
base ad:0x6120000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
newline
hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
newline
hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
newline
bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
newline
bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
newline
bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
newline
bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
newline
bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
newline
bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
newline
bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
newline
bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
newline
bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
newline
bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
newline
bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
newline
bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
newline
bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
newline
bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
newline
bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
newline
bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
newline
bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
tree "DSS_TPCC_C (DSS TPCCC Module Registers)"
base ad:0x6140000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
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bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
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bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
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bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
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bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
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bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
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bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
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bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
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bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
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bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
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bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
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bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
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bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
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bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
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bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
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bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
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bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
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bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
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bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
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bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
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bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
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bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
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bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
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bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
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bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
newline
hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
newline
hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
newline
bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
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bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
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bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
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bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
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bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
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bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
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bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
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bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
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bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
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bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
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bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
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bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
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bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
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bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
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bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
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bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
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bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
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bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
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bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
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bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
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bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
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bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
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bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
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bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
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bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
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bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
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bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
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bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
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bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
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bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
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bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
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bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
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bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
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bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
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bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
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bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
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bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
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bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
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bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
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bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
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bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
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bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
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bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
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bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
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bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
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bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
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bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
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bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
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bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
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bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
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bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
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bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
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bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
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bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
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bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
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bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
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bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
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bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
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bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
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bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
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bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
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bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
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bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
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bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
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bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
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bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
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bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
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bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
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bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
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bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
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bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
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bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
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bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
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bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
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bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
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bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
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bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
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bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
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bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
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bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
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bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
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bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x6160000 ad:0x6180000 )
tree "DSS_TPTC_A$1 (DSS TPTC A$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
repeat 2. (list 0. 1. )(list ad:0x61A0000 ad:0x61C0000 )
tree "DSS_TPTC_B$1 (DSS TPTC B$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
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bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
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bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
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bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
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bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list ad:0x61E0000 ad:0x6200000 ad:0x6220000 ad:0x6240000 ad:0x6260000 ad:0x6280000 )
tree "DSS_TPTC_C$1 (DSS TPTC C$1 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
tree "DSS_WDT (DSS WDT Module Registers)"
base ad:0x6F7A200
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x401A0000 ad:0x401C0000 )
tree "MPU_DSS_HWA_DMA$1 (DSS HWA DMA$1 MPU Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
repeat.end
tree "MPU_DSS_HWA_PROC (DSS HWA PROC MPU Module Registers)"
base ad:0x401E0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKA (DSS L3 BANKA MPU Module Registers)"
base ad:0x40120000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKB (DSS L3 BANKB MPU Module Registers)"
base ad:0x40140000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKC (DSS L3 BANKC MPU Module Registers)"
base ad:0x40160000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_L3_BANKD (MSS L3 BANKD MPU Module Registers)"
base ad:0x40180000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_DSS_MBOX (DSS MBOX MPU Module Registers)"
base ad:0x40200000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_CR5A_AXIS (MSS CR5A AXIS MPU Module Registers)"
base ad:0x400E0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_CR5B_AXIS (MSS CR5B AXIS MPU Module Registers)"
base ad:0x40100000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_L2_BANKA (MSS L2 BANKA MPU Module Registers)"
base ad:0x40020000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_L2_BANKB (MSS L2 BANKB MPU Module Registers)"
base ad:0x40040000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_MBOX (MPU MSS MBOX Module Registers)"
base ad:0x40080000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_PCRA (MSS PCRA MPU Module Registers)"
base ad:0x400A0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MPU_MSS_QSPI (MSS QSPI MPU Module Registers)"
base ad:0x400C0000
rgroup.long 0x00++0x07
line.long 0x00 "Revision,Revision"
bitfld.long 0x00 30.--31. "scheme,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "reserved,Always read a s0" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "modID,Module ID field"
bitfld.long 0x00 11.--15. "revrtl,RTL revision.Will vary depending on release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "revmaj,Majo revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "revcustom,Custom revision" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "revmin,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "Configuration,Configuration"
hexmask.long.byte 0x04 24.--31. 1. "address_align,Address alignment for range checking"
bitfld.long 0x04 20.--23. "num_fixed,Number of fixed address ranges Configurable as 0 or 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 16.--19. "num_prog,Number of programmable address ranges.Value is determined by configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 12.--15. "num_fixed_aids,Number of supported AIDs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x04 1.--11. 1. "reserved,Always read as 0"
bitfld.long 0x04 0. "assumed_allowed,Assumed allowed mode" "assumed disallowed,assumed allowed"
group.long 0x10++0x17
line.long 0x00 "Interrupt Raw Status/Set,Interrupt Raw Status/Set"
hexmask.long 0x00 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x00 1. "addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x00 0. "prot_err,Protection violation error" "0,1"
line.long 0x04 "Interrupt Enabled Status/Clear,Interrupt Enabled Status/Clear"
hexmask.long 0x04 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x04 1. "enabled_addr_err,Addressing violation error" "0,1"
newline
bitfld.long 0x04 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x08 "Interrupt Enable,Interrupt Enable"
hexmask.long 0x08 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 1. "addr_err_en,Addressing violation error enable" "0,1"
newline
bitfld.long 0x08 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x0C "Interrupt Enable Clear,Interrupt Enable Clear"
hexmask.long 0x0C 2.--31. 1. "reserved,Always read as 0"
bitfld.long 0x0C 1. "addr_err_en_clr,Addressing violation error enable" "0,1"
newline
bitfld.long 0x0C 0. "prot_err_en_clr,Protection violation error enable" "0,1"
line.long 0x10 "EOI,EOI"
hexmask.long.tbyte 0x10 8.--31. 1. "reserved,Always read as 0"
hexmask.long.byte 0x10 0.--7. 1. "eoi_vector,EOI vector value.Write this with the interrupt distribution value in the chip"
line.long 0x14 "Interrupt Vector,Interrupt Vector"
rgroup.long 0x100++0x0B
line.long 0x00 "Fixed Start Address,Fixed Start Address"
line.long 0x04 "Fixed End Address,Fixed End Address"
line.long 0x08 "Fixed MPPA,Fixed MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
group.long 0x200++0x0B
line.long 0x00 "Programmable 1 Start Address,Programmable 1 Start Address"
line.long 0x04 "Programmable 1 End Address,Programmable 1 End Address"
line.long 0x08 "Programmable 1 MPPA,Programmable 1 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x210++0x0B
line.long 0x00 "Programmable 2 Start Address,Programmable 2 Start Address"
line.long 0x04 "Programmable 2 End Address,Programmable 2 End Address"
line.long 0x08 "Programmable 2 MPPA,Programmable 2 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x220++0x0B
line.long 0x00 "Programmable 3 Start Address,Programmable 3 Start Address"
line.long 0x04 "Programmable 3 End Address,Programmable 3 End Address"
line.long 0x08 "Programmable 3 MPPA,Programmable 3 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x230++0x0B
line.long 0x00 "Programmable 4 Start Address,Programmable 4 Start Address"
line.long 0x04 "Programmable 4 End Address,Programmable 4 End Address"
line.long 0x08 "Programmable 4 MPPA,Programmable 4 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x240++0x0B
line.long 0x00 "Programmable 5 Start Address,Programmable 5 Start Address"
line.long 0x04 "Programmable 5 End Address,Programmable 5 End Address"
line.long 0x08 "Programmable 5 MPPA,Programmable 5 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x250++0x0B
line.long 0x00 "Programmable 6 Start Address,Programmable 6 Start Address"
line.long 0x04 "Programmable 6 End Address,Programmable 6 End Address"
line.long 0x08 "Programmable 6 MPPA,Programmable 6 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x260++0x0B
line.long 0x00 "Programmable 7 Start Address,Programmable 7 Start Address"
line.long 0x04 "Programmable 7 End Address,Programmable 7 End Address"
line.long 0x08 "Programmable 7 MPPA,Programmable 7 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
group.long 0x270++0x0B
line.long 0x00 "Programmable 8 Start Address,Programmable 8 Start Address"
line.long 0x04 "Programmable 8 End Address,Programmable 8 End Address"
line.long 0x08 "Programmable 8 MPPA,Programmable 8 MPPA"
rbitfld.long 0x08 26.--31. "reserved,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
abitfld.long 0x08 10.--25. "AID15_0,AIDs checked for this region" "0x0000=AID is not checked for these permissions,0x0001=AID is checked for these permissions"
newline
bitfld.long 0x08 9. "AIDX,Additional AIDs checked" "0,1"
rbitfld.long 0x08 8. "reserved1,Always read as 0" "0,1"
newline
bitfld.long 0x08 7. "ns,Non-secure permission" "0,1"
bitfld.long 0x08 6. "emu,Debug permission" "0,1"
newline
bitfld.long 0x08 5. "sr,Supervisor read permission" "0,1"
bitfld.long 0x08 4. "sw,Supervisor write permission" "0,1"
newline
bitfld.long 0x08 3. "sx,Supervisor executable permission" "0,1"
bitfld.long 0x08 2. "ur,User read permission" "0,1"
newline
bitfld.long 0x08 1. "uw,User write permission" "0,1"
bitfld.long 0x08 0. "ux,User executable permission" "0,1"
rgroup.long 0x280++0x0B
line.long 0x00 "Programmable 9 Start Address,Programmable 9 Start Address"
line.long 0x04 "Programmable 9 End Address,Programmable 9 End Address"
line.long 0x08 "Programmable 9 MPPA,Programmable 9 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x290++0x0B
line.long 0x00 "Programmable 10 Start Address,Programmable 10 Start Address"
line.long 0x04 "Programmable 10 End Address,Programmable 10 End Address"
line.long 0x08 "Programmable 10 MPPA,Programmable 10 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2A0++0x0B
line.long 0x00 "Programmable 11 Start Address,Programmable 11 Start Address"
line.long 0x04 "Programmable 11 End Address,Programmable 11 End Address"
line.long 0x08 "Programmable 11 MPPA,Programmable 11 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2B0++0x0B
line.long 0x00 "Programmable 12 Start Address,Programmable 12 Start Address"
line.long 0x04 "Programmable 12 End Address,Programmable 12 End Address"
line.long 0x08 "Programmable 12 MPPA,Programmable 12 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2C0++0x0B
line.long 0x00 "Programmable 13 Start Address,Programmable 13 Start Address"
line.long 0x04 "Programmable 13 End Address,Programmable 13 End Address"
line.long 0x08 "Programmable 13 MPPA,Programmable 13 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2D0++0x0B
line.long 0x00 "Programmable 14 Start Address,Programmable 14 Start Address"
line.long 0x04 "Programmable 14 End Address,Programmable 14 End Address"
line.long 0x08 "Programmable 14 MPPA,Programmable 14 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2E0++0x0B
line.long 0x00 "Programmable 15 Start Address,Programmable 15 Start Address"
line.long 0x04 "Programmable 15 End Address,Programmable 15 End Address"
line.long 0x08 "Programmable 15 MPPA,Programmable 15 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x2F0++0x0B
line.long 0x00 "Programmable 16 Start Address,Programmable 16 Start Address"
line.long 0x04 "Programmable 16 End Address,Programmable 16 End Address"
line.long 0x08 "Programmable 16 MPPA,Programmable 16 MPPA"
bitfld.long 0x08 26.--31. "reserved,Reserved not used in Design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 10.--25. 1. "AID15_0,Reserved not used in Design"
newline
bitfld.long 0x08 9. "AIDX,Reserved not used in Design" "0,1"
bitfld.long 0x08 8. "reserved1,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 7. "ns,Reserved not used in Design" "0,1"
bitfld.long 0x08 6. "emu,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 5. "sr,Reserved not used in Design" "0,1"
bitfld.long 0x08 4. "sw,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 3. "sx,Reserved not used in Design" "0,1"
bitfld.long 0x08 2. "ur,Reserved not used in Design" "0,1"
newline
bitfld.long 0x08 1. "uw,Reserved not used in Design" "0,1"
bitfld.long 0x08 0. "ux,Reserved not used in Design" "0,1"
rgroup.long 0x300++0x0B
line.long 0x00 "Fault Address,Fault Address"
line.long 0x04 "Fault Status,Fault Status"
hexmask.long.byte 0x04 24.--31. 1. "id,Transfer ID"
hexmask.long.byte 0x04 16.--23. 1. "mstid,Master ID"
newline
bitfld.long 0x04 13.--15. "reserved,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 9.--12. "privid,Privilege ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 8. "reserved1,Always read as 0" "0,1"
bitfld.long 0x04 7. "ns,Non-secure access" "0,1"
newline
bitfld.long 0x04 6. "reserved2,Always read as 0" "0,1"
bitfld.long 0x04 0.--5. "fault_type,Fault type" "no fault,user execute fault,user write fault,?,user read fault,?,?,?,supervisor execute fault,?,?,?,?,?,?,?,supervisor write fault,?,relaxed cache writeback fault,?,?,?,?,?,?,?,?,?,?,?,?,?,supervisor read fault,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,relaxed cache linefill fault"
line.long 0x08 "Fault Clear,Fault Clear"
hexmask.long 0x08 1.--31. 1. "reserved,Always read as 0"
bitfld.long 0x08 0. "fault_clr,Fault clear" "0,1"
width 0x0B
tree.end
tree "MSS_CCMR (MSS CCMR Module Registers)"
base ad:0x2F7AC00
group.long 0x00++0x1B
line.long 0x00 "CCMSR1,CPU Compare Status Register"
hexmask.long.word 0x00 17.--31. 1. "NU2,Reserved"
bitfld.long 0x00 16. "CMPE1,Compare Error" "CPU signals are identical,CPU signal compare mismatch Writes '1' to clear.."
newline
hexmask.long.byte 0x00 9.--15. 1. "NU1,Reserved"
bitfld.long 0x00 8. "STC1,Self Test Complete" "self test on-going if self test mode asserted,self test is complete Writes have no effect"
newline
bitfld.long 0x00 2.--7. "NU0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 1. "STET1,Self Test Error Type" "self test failed during Compare Match test,self test failed during Compare mismatch test.."
newline
bitfld.long 0x00 0. "STE1,Self Test Error" "self test passed,self test failed Writes have no effect"
line.long 0x04 "CCMKEYR1,CPU Compare Key Register"
hexmask.long 0x04 4.--31. 1. "NU3,Reserved"
bitfld.long 0x04 0.--3. "MKEY1,Mode Key" "lock step mode,?,?,?,?,?,self test mode,?,?,error forcing mode,?,?,?,?,?,self test error forcing mode"
line.long 0x08 "CCMSR2,VIM Compare Status Register"
hexmask.long.word 0x08 17.--31. 1. "NU6,Reserved"
bitfld.long 0x08 16. "CMPE2,Compare Error" "VIM signals are identical,VIM signal compare mismatch Writes '1' to clear.."
newline
hexmask.long.byte 0x08 9.--15. 1. "NU5,Reserved"
bitfld.long 0x08 8. "STC2,Self Test Complete" "self test on-going if self test mode asserted,self test is complete Writes have no effect"
newline
bitfld.long 0x08 2.--7. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 1. "STET2,Self Test Error Type" "self test failed during Compare Match test,self test failed during Compare mismatch test.."
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bitfld.long 0x08 0. "STE2,Self Test Error" "self test passed,self test failed Writes have no effect"
line.long 0x0C "CCMKEYR2,VIM Compare Key Register"
hexmask.long 0x0C 4.--31. 1. "NU7,Reserved"
bitfld.long 0x0C 0.--3. "MKEY2,Mode Key" "lock step mode,?,?,?,?,?,self test mode,?,?,error forcing mode,?,?,?,?,?,self test error forcing mode"
line.long 0x10 "CCMSR3,Inactivity Monitor Status Register"
hexmask.long.word 0x10 17.--31. 1. "NU10,Reserved"
bitfld.long 0x10 16. "CMPE3,Compare Error" "Inactivity monitor signals are identical,Inactivity monitor signal compare mismatch.."
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hexmask.long.byte 0x10 9.--15. 1. "NU9,Reserved"
bitfld.long 0x10 8. "STC3,Self Test Complete" "self test on-going if self test mode asserted,self test is complete Writes have no effect"
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bitfld.long 0x10 2.--7. "NU8,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x10 1. "STET3,Self Test Error Type" "self test failed during Compare Match test,self test failed during Compare mismatch test.."
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bitfld.long 0x10 0. "STE3,Self Test Error" "self test passed,self test failed Writes have no effect"
line.long 0x14 "CCMKEYR3,Inactivity Monitor Key Register"
hexmask.long 0x14 4.--31. 1. "NU11,Reserved"
bitfld.long 0x14 0.--3. "MKEY3,Mode Key" "lock step mode,?,?,?,?,?,self test mode,?,?,error forcing mode,?,?,?,?,?,self test error forcing mode"
line.long 0x18 "CCMPOLCNTRL,CPU Compare Polarity Control Register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU12,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "POL_INV,This value is used to invert the 8 XOR of the CPU1 to create compare fail in functional active compare mode"
width 0x0B
tree.end
tree "MSS_CPSW (MSS CPSW Module Registers)"
base ad:0x7000000
rgroup.long 0x00++0x0F
line.long 0x00 "SS_IDVER_REG,SS ID Version Register"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "SS_SYNCE_COUNT_REG,SS SYNCE Count Register"
line.long 0x08 "SS_SYNCE_MUX_REG,SS Synce Mux Register"
bitfld.long 0x08 0.--5. "SYNCE_SEL,Sync E Select Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "SS_CONTROL_REG,SS Control Register"
bitfld.long 0x0C 1. "EEE_PHY_ONLY,Energy Efficient Enable Phy Only Mode" "The low power indicate state includes gating off..,The low power indicate state does not gate the.."
newline
bitfld.long 0x0C 0. "EEE_EN,Energy Efficient Ethernet Enable" "EEE is disabled,EEE is enabled"
group.long 0x18++0x07
line.long 0x00 "SS_INT_CONTROL_REG,SS Interrupt Control Register"
bitfld.long 0x00 31. "INT_TEST,Interrupt Test" "0,1"
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bitfld.long 0x00 16.--21. "INT_BYPASS,Interrupt Bypass Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x00 0.--11. 1. "INT_PRESCALE,Interrupt Prescale Value"
line.long 0x04 "SS_STATUS_REG,SS Status Register"
bitfld.long 0x04 0. "EEE_CLKSTOP_ACK,Energy Efficient Ethernet clockstop acknowledge from CPSW" "0,1"
rgroup.long 0x30++0x03
line.long 0x00 "SS_RGMII1_STATUS_REG,RGMII1 Status Register"
bitfld.long 0x00 3. "FULLDUPLEX,Rgmii full dulex" "Half-duplex,Full-duplex"
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bitfld.long 0x00 1.--2. "SPEED,Rgmii1 speed" "0,1,2,3"
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bitfld.long 0x00 0. "LINK,Rgmii1 link indicator" "Link is down,Link is up"
group.long 0x80++0x0F
line.long 0x00 "SS_TH_THRESH_PULSE_EN_REG,THost Threshold Pulse Interrupt Enable Register"
hexmask.long.byte 0x00 0.--7. 1. "TH_THRESH_PULSE_EN,THost Threshold Pulse Interrupt Enable Register"
line.long 0x04 "SS_TH_PULSE_EN_REG,THost Pulse Interrupt Enable Register"
hexmask.long.byte 0x04 0.--7. 1. "TH_PULSE_EN,THost Pulse Interrupt Enable Register"
line.long 0x08 "SS_FH_PULSE_EN_REG,FHost Pulse Interrupt Enable Register"
hexmask.long.byte 0x08 0.--7. 1. "FH_PULSE_EN,FHost Pulse Interrupt Enable Register"
line.long 0x0C "SS_MISC_EN_REG,Misc Interrupt Enable Register"
bitfld.long 0x0C 6. "DED_PEND_EN,MISC DED Memory Protect Error Interrupt Enable" "0,1"
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bitfld.long 0x0C 5. "SEC_PEND_EN,MISC SEC Memory Protect Error Interrupt Enable" "0,1"
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bitfld.long 0x0C 4. "EVNT_PEND_EN,MISC CPTS Event Interrupt Enable" "0,1"
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bitfld.long 0x0C 3. "STAT_PEND_EN,MISC Statistics Interrupt Enable - OR of bits n downto 0" "0,1"
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bitfld.long 0x0C 2. "HOST_PEND_EN,MISC Host Interrupt Enable" "0,1"
newline
bitfld.long 0x0C 1. "MDIO_LINKINT_EN,MISC MDIO linkint - OR of bits 1 and 0" "0,1"
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bitfld.long 0x0C 0. "MDIO_USERINT_EN,MISC_MDIO userint interrupt enable - OR of bits 1 and 0" "0,1"
rgroup.long 0xB0++0x0F
line.long 0x00 "SS_TH_THRESH_PULSE_STATUS_REG,THost Threshold Pulse Interrupt Status Register"
hexmask.long.byte 0x00 0.--7. 1. "TH_THRESH_PULSE_ST,THost Threshold Pulse Interrupt Status Register"
line.long 0x04 "SS_TH_PULSE_STATUS_REG,THost Pulse Interrupt Status Register"
hexmask.long.byte 0x04 0.--7. 1. "TH_PULSE_STATUS,THost Pulse Interrupt Status Register"
line.long 0x08 "SS_FH_PULSE_STATUS_REG,FHost Pulse Interrupt Status Register"
hexmask.long.byte 0x08 0.--7. 1. "FH_PULSE_STATUS,FHost Pulse Interrupt Status Register"
line.long 0x0C "SS_MISC_STATUS_REG,Misc Interrupt Status Register - Set bits in this register indicate that an enabled interrupt is asserted"
bitfld.long 0x0C 6. "DED_PEND,MISC DED Memory Protect Error Interrupt" "0,1"
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bitfld.long 0x0C 5. "SEC_PEND,MISC SEC Memory Protect Error Interrupt" "0,1"
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bitfld.long 0x0C 4. "EVNT_PEND,MISC CPTS Event Interrupt" "0,1"
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bitfld.long 0x0C 3. "STAT_PEND,MISC Statistics Interrupt - OR of bits n downto 0" "0,1"
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bitfld.long 0x0C 2. "HOST_PEND,MISC Host Interrupt Enable" "0,1"
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bitfld.long 0x0C 1. "MDIO_LINKINT,MISC MDIO linkint - OR of bits 1 and 0" "0,1"
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bitfld.long 0x0C 0. "MDIO_USERINT,MISC_MDIO userint interrupt - OR of bits 1 and 0" "0,1"
group.long 0xE0++0x07
line.long 0x00 "SS_TH_IMAX_REG,THost Interrupt Max Register Register"
bitfld.long 0x00 0.--5. "TH_IMAX,THost Interrupt Max Register Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SS_FH_IMAX_REG,FHost Interrupt Max Register Register"
bitfld.long 0x04 0.--5. "FH_IMAX,FHost Interrupt Max Register Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0xF00++0x47
line.long 0x00 "MDIO_VERSION_REG,MDIO Version Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
newline
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CONTROL_REG,MDIO Control Register"
rbitfld.long 0x04 31. "IDLE,MDIO state machine idle" "0,1"
newline
bitfld.long 0x04 30. "ENABLE,Enable control" "0,1"
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rbitfld.long 0x04 24.--28. "HIGHEST_USER_CHANNEL,Highest user channel" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 20. "PREAMBLE,Preamble disable" "0,1"
newline
bitfld.long 0x04 19. "FAULT,Fault indicator" "0,1"
newline
bitfld.long 0x04 18. "FAULT_DETECT_ENABLE,Fault detect enable" "0,1"
newline
bitfld.long 0x04 17. "INT_TEST_ENABLE,Interrupt test enable" "0,1"
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hexmask.long.word 0x04 0.--15. 1. "CLKDIV,Clock divider"
line.long 0x08 "ALIVE_REG,MDIO Alive Register"
line.long 0x0C "LINK_REG,MDIO Link Register"
line.long 0x10 "LINK_INT_RAW_REG,MDIO Link Interrupt Raw Register"
bitfld.long 0x10 0.--1. "LINKINTRAW,MDIO link change event raw value" "0,1,2,3"
line.long 0x14 "LINK_INT_MASKED_REG,MDIO Link Interrupt Masked Register"
bitfld.long 0x14 0.--1. "LINKINTMASKED,MDIO link change interrupt masked value" "0,1,2,3"
line.long 0x18 "LINK_INT_MASK_SET_REG,MDIO Link Interrupt Mask Set Register"
bitfld.long 0x18 0. "LINKINTMASKSET,MDIO link interrupt mask set" "0,1"
line.long 0x1C "LINK_INT_MASK_CLEAR_REG,MDIO Link Interrupt Mask Clear Register"
bitfld.long 0x1C 0. "LINKINTMASKCLR,MDIO link interrupt mask clear" "0,1"
line.long 0x20 "USER_INT_RAW_REG,MDIO User Interrupt Raw Register"
bitfld.long 0x20 0.--1. "USERINTRAW,User interrupt raw" "0,1,2,3"
line.long 0x24 "USER_INT_MASKED_REG,MDIO User Interrupt Masked Register"
bitfld.long 0x24 0.--1. "USERINTMASKED,User interrupt masked" "0,1,2,3"
line.long 0x28 "USER_INT_MASK_SET_REG,MDIO User Interrupt Mask Set Register"
bitfld.long 0x28 0.--1. "USERINTMASKSET,MDIO user interrupt mask set" "0,1,2,3"
line.long 0x2C "USER_INT_MASK_CLEAR_REG,MDIO User Interrupt Mask Clear Register"
bitfld.long 0x2C 0.--1. "USERINTMASKCLR,MDIO user interrupt mask clear" "0,1,2,3"
line.long 0x30 "MANUAL_IF_REG,MDIO Manual Interface Register"
bitfld.long 0x30 2. "MDIO_MDCLK_O,MDIO Clock Output" "0,1"
newline
bitfld.long 0x30 1. "MDIO_OE,MDIO Output Enable" "0,1"
newline
bitfld.long 0x30 0. "MDIO_PIN,MDIO Pin" "0,1"
line.long 0x34 "POLL_REG,MDIO Poll Register"
bitfld.long 0x34 31. "MANUALMODE,MDIO Manual Mode" "0,1"
newline
bitfld.long 0x34 30. "STATECHANGEMODE,MDIO State Change Mode" "0,1"
newline
hexmask.long.byte 0x34 0.--7. 1. "IPG,MDIO IPG"
line.long 0x38 "POLL_EN_REG,MDIO Poll Enable Register"
line.long 0x3C "CLAUS45_REG,MDIO Clause45 Register"
line.long 0x40 "USER_ADDR0_REG,MDIO Address 0 Register"
hexmask.long.word 0x40 0.--15. 1. "USER_ADDR0,MDIO USER Address 0"
line.long 0x44 "USER_ADDR1_REG,MDIO Address 1 Register"
hexmask.long.word 0x44 0.--15. 1. "USER_ADDR1,MDIO USER Address 1"
group.long 0xF80++0x07
line.long 0x00 "USER_ACCESS_REG,MDIO User Access Register"
bitfld.long 0x00 31. "GO,Go" "0,1"
newline
bitfld.long 0x00 30. "WRITE," "0,1"
newline
bitfld.long 0x00 29. "ACK,Acknowledge" "0,1"
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bitfld.long 0x00 21.--25. "REGADR,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PHYADR,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x00 0.--15. 1. "DATA,User data"
line.long 0x04 "USER_PHY_SEL_REG,MDIO User PHY Select Register"
bitfld.long 0x04 7. "LINKSEL,Link status determination select" "0,1"
newline
bitfld.long 0x04 6. "LINKINT_ENABLE,Link change interrupt enable" "0,1"
newline
bitfld.long 0x04 0.--4. "PHYADR_MON,PHY address whose link status is monitored" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x20000++0x07
line.long 0x00 "CPSW_ID_VER_REG,CPSW ID Version"
hexmask.long.word 0x00 16.--31. 1. "IDENT,Identification Value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major Version Value" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM_VER,Custom Version Value" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR_VER,Minor Version Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CONTROL_REG,CPSW Switch Control"
bitfld.long 0x04 31. "ECC_CRC_MODE,ECC CRC Mode" "0,1"
newline
bitfld.long 0x04 18. "EST_ENABLE,Intersperced Express Traffic enable" "0,1"
newline
bitfld.long 0x04 17. "UNUSED,Unused" "0,1"
newline
bitfld.long 0x04 16. "EEE_ENABLE,Energy Efficient Ethernet enable" "0,1"
newline
bitfld.long 0x04 15. "P0_RX_PASS_CRC_ERR,Port 0 Pass Received CRC errors" "0,1"
newline
bitfld.long 0x04 14. "P0_RX_PAD,Port 0 Receive Short Packet Pad" "0,1"
newline
bitfld.long 0x04 13. "P0_TX_CRC_REMOVE,Port 0 Transmit CRC remove" "0,1"
newline
bitfld.long 0x04 11. "P8_PASS_PRI_TAGGED,Port 8 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 10. "P7_PASS_PRI_TAGGED,Port 7 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 9. "P6_PASS_PRI_TAGGED,Port 6 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 8. "P5_PASS_PRI_TAGGED,Port 5 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 7. "P4_PASS_PRI_TAGGED,Port 4 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 6. "P3_PASS_PRI_TAGGED,Port 3 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 5. "P2_PASS_PRI_TAGGED,Port 2 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 4. "P1_PASS_PRI_TAGGED,Port 1 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 3. "P0_PASS_PRI_TAGGED,Port 0 Pass Priority Tagged" "0,1"
newline
bitfld.long 0x04 2. "P0_ENABLE,Port 0 Enable" "0,1"
newline
bitfld.long 0x04 1. "VLAN_AWARE,VLAN Aware Mode" "0,1"
newline
bitfld.long 0x04 0. "S_CN_SWITCH,VLAN Aware Mode" "0,1"
group.long 0x20010++0x37
line.long 0x00 "EM_CONTROL_REG,CPSW Emulation Control"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
newline
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "STAT_PORT_EN_REG,CPSW Statistics Port Enable"
bitfld.long 0x04 8. "P8_STAT_EN,Port 8 Statistics Enable" "0,1"
newline
bitfld.long 0x04 7. "P7_STAT_EN,Port 7 Statistics Enable" "0,1"
newline
bitfld.long 0x04 6. "P6_STAT_EN,Port 6 Statistics Enable" "0,1"
newline
bitfld.long 0x04 5. "P5_STAT_EN,Port 5 Statistics Enable" "0,1"
newline
bitfld.long 0x04 4. "P4_STAT_EN,Port 4 Statistics Enable" "0,1"
newline
bitfld.long 0x04 3. "P3_STAT_EN,Port 3 Statistics Enable" "0,1"
newline
bitfld.long 0x04 2. "P2_STAT_EN,Port 2 Statistics Enable" "0,1"
newline
bitfld.long 0x04 1. "P1_STAT_EN,Port 1 Statistics Enable" "0,1"
newline
bitfld.long 0x04 0. "P0_STAT_EN,Port 0 Statistics Enable" "0,1"
line.long 0x08 "PTYPE_REG,CPSW Transmit Priority Type"
bitfld.long 0x08 16. "P8_PTYPE_ESC,Port 8 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 15. "P7_PTYPE_ESC,Port 7 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 14. "P6_PTYPE_ESC,Port 6 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 13. "P5_PTYPE_ESC,Port 5 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 12. "P4_PTYPE_ESC,Port 4 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 11. "P3_PTYPE_ESC,Port 3 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 10. "P2_PTYPE_ESC,Port 2 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 9. "P1_PTYPE_ESC,Port 1 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 8. "P0_PTYPE_ESC,Port 0 Priority Type Escalate" "0,1"
newline
bitfld.long 0x08 0.--4. "ESC_PRI_LD_VAL,Escalate Priority Load Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "SOFT_IDLE_REG,CPSW Software Idle"
bitfld.long 0x0C 0. "SOFT_IDLE,Software Idle" "0,1"
line.long 0x10 "THRU_RATE_REG,CPSW Thru Rate"
bitfld.long 0x10 12.--15. "SL_RX_THRU_RATE,Switch FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 0.--3. "P0_RX_THRU_RATE,CPPI FIFO receive through rate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "GAP_THRESH_REG,CPSW Transmit FIFO Short Gap Threshold"
bitfld.long 0x14 0.--4. "GAP_THRESH,Short Gap Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "TX_START_WDS_REG,CPSW Transmit FIFO Start Words"
hexmask.long.word 0x18 0.--10. 1. "TX_START_WDS,FIFO Packet Transmit Start Words"
line.long 0x1C "EEE_PRESCALE_REG,CPSW Energy Efficient Ethernet Prescale Value"
hexmask.long.word 0x1C 0.--11. 1. "EEE_PRESCALE,Energy Efficient Ethernet Pre-scale count load value"
line.long 0x20 "TX_G_OFLOW_THRESH_SET_REG,CPSW PFC Tx Global Out Flow Threshold Set"
bitfld.long 0x20 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "TX_G_OFLOW_THRESH_CLR_REG,CPSW PFC Tx Global Out Flow Threshold Clear"
bitfld.long 0x24 28.--31. "PRI7,Priority Based Flow Control Global Outflow Usage Threshold for Pri 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 24.--27. "PRI6,Priority Based Flow Control Global Outflow Usage Threshold for Pri 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 20.--23. "PRI5,Priority Based Flow Control Global Outflow Usage Threshold for Pri 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 16.--19. "PRI4,Priority Based Flow Control Global Outflow Usage Threshold for Pri 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 12.--15. "PRI3,Priority Based Flow Control Global Outflow Usage Threshold for Pri 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 8.--11. "PRI2,Priority Based Flow Control Global Outflow Usage Threshold for Pri 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 4.--7. "PRI1,Priority Based Flow Control Global Outflow Usage Threshold for Pri 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 0.--3. "PRI0,Priority Based Flow Control Global Outflow Usage Threshold for Pri 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "TX_G_BUF_THRESH_SET_L_REG,CPSW PFC Global Tx Buffer Threshold Set Low"
hexmask.long.byte 0x28 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
newline
hexmask.long.byte 0x28 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
newline
hexmask.long.byte 0x28 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
newline
hexmask.long.byte 0x28 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x2C "TX_G_BUF_THRESH_SET_H_REG,CPSW PFC Global Tx Buffer Threshold Set High"
hexmask.long.byte 0x2C 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
newline
hexmask.long.byte 0x2C 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
newline
hexmask.long.byte 0x2C 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
newline
hexmask.long.byte 0x2C 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
line.long 0x30 "TX_G_BUF_THRESH_CLR_L_REG,CPSW PFC Global Tx Buffer Threshold Clear Low"
hexmask.long.byte 0x30 24.--31. 1. "PRI3,Priority Based Flow Control Global Buffer Usage Threshold for Priority 3"
newline
hexmask.long.byte 0x30 16.--23. 1. "PRI2,Priority Based Flow Control Global Buffer Usage Threshold for Priority 2"
newline
hexmask.long.byte 0x30 8.--15. 1. "PRI1,Priority Based Flow Control Global Buffer Usage Threshold for Priority 1"
newline
hexmask.long.byte 0x30 0.--7. 1. "PRI0,Priority Based Flow Control Global Buffer Usage Threshold for Priority 0"
line.long 0x34 "TX_G_BUF_THRESH_CLR_H_REG,CPSW PFC Global Tx Buffer Threshold Clear High"
hexmask.long.byte 0x34 24.--31. 1. "PRI7,Priority Based Flow Control Global Buffer Usage Threshold for Priority 7"
newline
hexmask.long.byte 0x34 16.--23. 1. "PRI6,Priority Based Flow Control Global Buffer Usage Threshold for Priority 6"
newline
hexmask.long.byte 0x34 8.--15. 1. "PRI5,Priority Based Flow Control Global Buffer Usage Threshold for Priority 5"
newline
hexmask.long.byte 0x34 0.--7. 1. "PRI4,Priority Based Flow Control Global Buffer Usage Threshold for Priority 4"
group.long 0x20050++0x07
line.long 0x00 "VLAN_LTYPE_REG,VLAN Length/type"
hexmask.long.word 0x00 16.--31. 1. "VLAN_LTYPE_OUTER,Outer VLAN LType"
newline
hexmask.long.word 0x00 0.--15. 1. "VLAN_LTYPE_INNER,Inner VLAN LType"
line.long 0x04 "EST_TS_DOMAIN_REG,Enhanced Scheduled Traffic Host Event Domain"
hexmask.long.byte 0x04 0.--7. 1. "EST_TS_DOMAIN,Enhanced Scheduled Traffic Host Event Domain"
group.long 0x20100++0x1F
line.long 0x00 "TX_PRI0_MAXLEN_REG,Transmit Priority 0 Maximum Length"
hexmask.long.word 0x00 0.--13. 1. "TX_PRI0_MAXLEN,Transmit Priority 0 Maximum Length"
line.long 0x04 "TX_PRI1_MAXLEN_REG,Transmit Priority 1 Maximum Length"
hexmask.long.word 0x04 0.--13. 1. "TX_PRI1_MAXLEN,Transmit Priority 1 Maximum Length"
line.long 0x08 "TX_PRI2_MAXLEN_REG,Transmit Priority 2 Maximum Length"
hexmask.long.word 0x08 0.--13. 1. "TX_PRI2_MAXLEN,Transmit Priority 2 Maximum Length"
line.long 0x0C "TX_PRI3_MAXLEN_REG,Transmit Priority 3 Maximum Length"
hexmask.long.word 0x0C 0.--13. 1. "TX_PRI3_MAXLEN,Transmit Priority 3 Maximum Length"
line.long 0x10 "TX_PRI4_MAXLEN_REG,Transmit Priority 4 Maximum Length"
hexmask.long.word 0x10 0.--13. 1. "TX_PRI4_MAXLEN,Transmit Priority 4 Maximum Length"
line.long 0x14 "TX_PRI5_MAXLEN_REG,Transmit Priority 5 Maximum Length"
hexmask.long.word 0x14 0.--13. 1. "TX_PRI5_MAXLEN,Transmit Priority 5 Maximum Length"
line.long 0x18 "TX_PRI6_MAXLEN_REG,Transmit Priority 6 Maximum Length"
hexmask.long.word 0x18 0.--13. 1. "TX_PRI6_MAXLEN,Transmit Priority 6 Maximum Length"
line.long 0x1C "TX_PRI7_MAXLEN_REG,Transmit Priority 7 Maximum Length"
hexmask.long.word 0x1C 0.--13. 1. "TX_PRI7_MAXLEN,Transmit Priority 7 Maximum Length"
group.long 0x21004++0x07
line.long 0x00 "P0_CONTROL_REG,CPPI Port 0 Control"
bitfld.long 0x00 18. "RX_REMAP_DSCP_V6,Port 0 Remap DSCP_V6 Enable" "0,1"
newline
bitfld.long 0x00 17. "RX_REMAP_DSCP_V4,Port 0 Remap DSCP_V4 Enable" "0,1"
newline
bitfld.long 0x00 16. "RX_REMAP_VLAN,Port 0 Remap VLAN Enable" "0,1"
newline
bitfld.long 0x00 15. "RX_ECC_ERR_EN,Port 0 Receive ECC Error Enable" "0,1"
newline
bitfld.long 0x00 14. "TX_ECC_ERR_EN,Port 0 Transmit ECC Error Enable" "0,1"
newline
bitfld.long 0x00 2. "DSCP_IPV6_EN,Port 0 IPv6 DSCP enable" "0,1"
newline
bitfld.long 0x00 1. "DSCP_IPV4_EN,Port 0 IPv4 DSCP enable" "0,1"
newline
bitfld.long 0x00 0. "RX_CHECKSUM_EN,Port 0 Receive Checksum Enable" "0,1"
line.long 0x04 "P0_FLOW_ID_OFFSET_REG,CPPI Port 0 Flow ID Offset"
hexmask.long.word 0x04 0.--13. 1. "VALUE,This value is added to the thread/Flow_ID in CPPI transmit PSI Info Word 0"
rgroup.long 0x21010++0x1B
line.long 0x00 "P0_BLK_CNT_REG,CPPI Port 0 FIFO Block Usage Count"
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Port 0 Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--5. "RX_BLK_CNT,Port 0 Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "P0_PORT_VLAN_REG,CPPI Port 0 VLAN"
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
newline
hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
line.long 0x08 "P0_TX_PRI_MAP_REG,CPPI Port 0 Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x08 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x0C "P0_PRI_CTL_REG,CPPI Port 0 Priority Control"
hexmask.long.byte 0x0C 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
newline
bitfld.long 0x0C 8. "RX_PTYPE,Receive Priority Type" "0,1"
line.long 0x10 "P0_RX_PRI_MAP_REG,CPPI Port 0 RX Pkt Pri to Header Pri Map"
bitfld.long 0x10 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "P0_RX_MAXLEN_REG,CPPI Port 0 Receive Frame Max Length"
hexmask.long.word 0x14 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length"
line.long 0x18 "P0_TX_BLKS_PRI_REG,CPPI Port 0 Transmit Block Sub Per Priority"
bitfld.long 0x18 28.--31. "PRI7,Priority 7 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 24.--27. "PRI6,Priority 6 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 20.--23. "PRI5,Priority 5 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 16.--19. "PRI4,Priority 4 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 12.--15. "PRI3,Priority 3 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 8.--11. "PRI2,Priority 2 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 4.--7. "PRI1,Priority 1 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "PRI0,Priority 0 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x21030++0x0F
line.long 0x00 "P0_IDLE2LPI_REG,Port 0 EEE Idle to LPI counter"
hexmask.long.tbyte 0x00 0.--23. 1. "COUNT,Port 0 EEE Idle to LPI counter load value"
line.long 0x04 "P0_LPI2WAKE_REG,Port 0 EEE LPI to wake counter"
hexmask.long.tbyte 0x04 0.--23. 1. "COUNT,Port 0 EEE LPI to wake counter load value"
line.long 0x08 "P0_EEE_STATUS_REG,Port 0 EEE status"
bitfld.long 0x08 6. "TX_FIFO_EMPTY,CPPI port 0 transmit FIFO (switch egress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x08 5. "RX_FIFO_EMPTY,CPPI port 0 receive FIFO (switch ingress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x08 4. "TX_FIFO_HOLD,CPPI port 0 transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
newline
bitfld.long 0x08 3. "TX_WAKE,CPPI port 0 transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
newline
bitfld.long 0x08 2. "TX_LPI,CPPI port 0 transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
newline
bitfld.long 0x08 1. "RX_LPI,CPPI port 0 receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
newline
bitfld.long 0x08 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
line.long 0x0C "P0_RX_PKTS_PRI_REG,CPPI Port Receive Packets per priority"
bitfld.long 0x0C 28.--31. "PRI7,Priority 7 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 24.--27. "PRI6,Priority 6 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 20.--23. "PRI5,Priority 5 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 16.--19. "PRI4,Priority 4 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 12.--15. "PRI3,Priority 3 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 8.--11. "PRI2,Priority 2 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 4.--7. "PRI1,Priority 1 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 0.--3. "PRI0,Priority 0 Port Port 0 Receive Packets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2104C++0x07
line.long 0x00 "P0_RX_GAP_REG,Port 0 Receive Gap Register"
hexmask.long.word 0x00 16.--25. 1. "RX_GAP_CNT,Port 0 Receive Gap Count"
newline
hexmask.long.byte 0x00 0.--7. 1. "RX_GAP_EN,Port 0 Receive Gap Enable"
line.long 0x04 "P0_FIFO_STATUS_REG,Port 0 FIFO Status"
hexmask.long.byte 0x04 0.--7. 1. "TX_PRI_ACTIVE,Port 0 FIFO Status"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x21120)++0x03
line.long 0x00 "P0_RX_DSCP_MAP_REG_$1,CPPI Port 0 Receive IPV4/IPV6 DSCP Map N"
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x21140)++0x03
line.long 0x00 "P0_PRI_CIR_REG_$1,CPPI Port 0 Rx Priority P Committed Information Rate"
hexmask.long 0x00 0.--27. 1. "PRI_CIR,Priority N CIR"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x21160)++0x03
line.long 0x00 "P0_PRI_EIR_REG_$1,CPPI Port 0 Rx Priority P Excess Information Rate"
hexmask.long 0x00 0.--27. 1. "PRI_EIR,Priority N EIR"
repeat.end
group.long 0x21180++0x1F
line.long 0x00 "P0_TX_D_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "P0_TX_D_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Destination Threshold Set High"
bitfld.long 0x04 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "P0_TX_D_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Destination Threshold Clr Low"
bitfld.long 0x08 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "P0_TX_D_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Destination Threshold Clr High"
bitfld.long 0x0C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "P0_TX_G_BUF_THRESH_SET_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x10 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "P0_TX_G_BUF_THRESH_SET_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x14 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "P0_TX_G_BUF_THRESH_CLR_L_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x18 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "P0_TX_G_BUF_THRESH_CLR_H_REG,CPPI Port 0 Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x1C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x21300++0x07
line.long 0x00 "P0_SRC_ID_A_REG,CPPI Port 0 CPPI Source ID A"
hexmask.long.byte 0x00 24.--31. 1. "PORT4,Port 4 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x00 16.--23. 1. "PORT3,Port 3 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x00 8.--15. 1. "PORT2,Port 2 CPPI Info Word0 Source ID Value"
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hexmask.long.byte 0x00 0.--7. 1. "PORT1,Port 1 CPPI Info Word0 Source ID Value"
line.long 0x04 "P0_SRC_ID_B_REG,CPPI Port 0 CPPI Source ID B"
hexmask.long.byte 0x04 24.--31. 1. "PORT8,Port 8 CPPI Info Word0 Source ID Value"
newline
hexmask.long.byte 0x04 16.--23. 1. "PORT7,Port 7 CPPI Info Word0 Source ID Value"
newline
hexmask.long.byte 0x04 8.--15. 1. "PORT6,Port 6 CPPI Info Word0 Source ID Value"
newline
hexmask.long.byte 0x04 0.--7. 1. "PORT5,Port 5 CPPI Info Word0 Source ID Value"
group.long 0x21320++0x03
line.long 0x00 "P0_HOST_BLKS_PRI_REG,CPPI Port 0 Host Blocks Priority"
bitfld.long 0x00 28.--31. "PRI7,Priority 7 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 24.--27. "PRI6,Priority 6 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 20.--23. "PRI5,Priority 5 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 16.--19. "PRI4,Priority 4 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 12.--15. "PRI3,Priority 3 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 8.--11. "PRI2,Priority 2 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4.--7. "PRI1,Priority 1 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "PRI0,Priority 0 Host Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0x22000++0x0B
line.long 0x00 "PN_RESERVED_REG,Reserved"
line.long 0x04 "PN_CONTROL_REG,Enet Port N Control"
bitfld.long 0x04 17. "EST_PORT_EN,EST Port Enable" "0,1"
newline
bitfld.long 0x04 15. "RX_ECC_ERR_EN,Port 0 Receive ECC Error Enable" "0,1"
newline
bitfld.long 0x04 14. "TX_ECC_ERR_EN,Port 0 Transmit ECC Error Enable" "0,1"
newline
bitfld.long 0x04 12. "TX_LPI_CLKSTOP_EN,Transmit LPI clockstop enable" "0,1"
newline
bitfld.long 0x04 2. "DSCP_IPV6_EN,IPv6 DSCP enable" "0,1"
newline
bitfld.long 0x04 1. "DSCP_IPV4_EN,IPv4 DSCP enable" "0,1"
line.long 0x08 "PN_MAX_BLKS_REG,Enet Port N FIFO Max Blocks"
hexmask.long.byte 0x08 8.--15. 1. "TX_MAX_BLKS,Transmit FIFO maximum blocks"
newline
hexmask.long.byte 0x08 0.--7. 1. "RX_MAX_BLKS,Receive FIFO maximum blocks"
rgroup.long 0x22010++0x2B
line.long 0x00 "PN_BLK_CNT_REG,Enet Port N FIFO Block Usage Count"
bitfld.long 0x00 16.--21. "RX_BLK_CNT_P,Receive Prempt Queue Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--12. "TX_BLK_CNT,Transmit Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--5. "RX_BLK_CNT_E,Receive Block Count Usage" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "PN_PORT_VLAN_REG,Enet Port N VLAN"
bitfld.long 0x04 13.--15. "PORT_PRI,Port VLAN Priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 12. "PORT_CFI,Port CFI bit" "0,1"
newline
hexmask.long.word 0x04 0.--11. 1. "PORT_VID,Port VLAN ID"
line.long 0x08 "PN_TX_PRI_MAP_REG,Enet Port N Tx Header Pri to Switch Pri Mapping"
bitfld.long 0x08 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x08 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x0C "PN_PRI_CTL_REG,Enet Port N Priority Control"
hexmask.long.byte 0x0C 24.--31. 1. "TX_FLOW_PRI,Transmit Priority Based Flow Control Enable (per priority)"
newline
hexmask.long.byte 0x0C 16.--23. 1. "RX_FLOW_PRI,Receive Priority Based Flow Control Enable (per priority)"
newline
bitfld.long 0x0C 12.--15. "TX_HOST_BLKS_REM,Transmit FIFO Blocks that must be free before a non rate-limited CPPI Port 0 receive thread can begin sending a packet" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "PN_RX_PRI_MAP_REG,Enet Port N RX Pkt Pri to Header Pri Map"
bitfld.long 0x10 28.--30. "PRI7,Priority 7" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 24.--26. "PRI6,Priority 6" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 20.--22. "PRI5,Priority 5" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 16.--18. "PRI4,Priority 4" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 12.--14. "PRI3,Priority 3" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 8.--10. "PRI2,Priority 2" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 4.--6. "PRI1,Priority 1" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x10 0.--2. "PRI0,Priority 0" "0,1,2,3,4,5,6,7"
line.long 0x14 "PN_RX_MAXLEN_REG,Enet Port N Receive Frame Max Length"
hexmask.long.word 0x14 0.--13. 1. "RX_MAXLEN,Rx Maximum Frame Length"
line.long 0x18 "PN_TX_BLKS_PRI_REG,Enet Port N Transmit Block Sub Per Priority"
bitfld.long 0x18 28.--31. "PRI7,Priority 7 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 24.--27. "PRI6,Priority 6 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 20.--23. "PRI5,Priority 5 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 16.--19. "PRI4,Priority 4 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 12.--15. "PRI3,Priority 3 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 8.--11. "PRI2,Priority 2 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 4.--7. "PRI1,Priority 1 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 0.--3. "PRI0,Priority 0 Port Transmit Blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "PN_RX_FLOW_THRESH_REG,Enet MAC Receive Flow Threshold in Receive Buffer Words"
hexmask.long.word 0x1C 0.--8. 1. "COUNT,Receive Flow Threshold in Words"
line.long 0x20 "PN_IDLE2LPI_REG,Enet Port N EEE Idle to LPI counter"
hexmask.long.tbyte 0x20 0.--23. 1. "COUNT,EEE Idle to LPI counter load value"
line.long 0x24 "PN_LPI2WAKE_REG,Enet Port N EEE LPI to wake counter"
hexmask.long.tbyte 0x24 0.--23. 1. "COUNT,EEE LPI to wake counter load value"
line.long 0x28 "PN_EEE_STATUS_REG,Enet Port N EEE status"
bitfld.long 0x28 6. "TX_FIFO_EMPTY,Transmit FIFO (switch egress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x28 5. "RX_FIFO_EMPTY,Receive FIFO (switch ingress) is empty - contains no packets" "0,1"
newline
bitfld.long 0x28 4. "TX_FIFO_HOLD,Transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time" "0,1"
newline
bitfld.long 0x28 3. "TX_WAKE,Transmit wakeup - asserted in the transmit LPI2WAKE count time" "0,1"
newline
bitfld.long 0x28 2. "TX_LPI,Transmit LPI state - asserted when the port 0 transmit is in the LPI state" "0,1"
newline
bitfld.long 0x28 1. "RX_LPI,Receive LPI state - asserted when the port 0 receive is in the LPI state" "0,1"
newline
bitfld.long 0x28 0. "WAIT_IDLE2LPI,CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time" "0,1"
rgroup.long 0x22050++0x03
line.long 0x00 "PN_FIFO_STATUS_REG,Enet Port N FIFO STATUS"
bitfld.long 0x00 18. "EST_BUFACT,Transmit FIFO EST Buffer Active" "0,1"
newline
bitfld.long 0x00 17. "EST_ADD_ERR,Transmit FIFO EST Address Error" "0,1"
newline
bitfld.long 0x00 16. "EST_CNT_ERR,Transmit FIFO EST Count Error" "0,1"
newline
hexmask.long.byte 0x00 8.--15. 1. "TX_E_MAC_ALLOW,Transmit FIFO Express Queue Priority Allow"
newline
hexmask.long.byte 0x00 0.--7. 1. "TX_PRI_ACTIVE,Transmit FIFO Priority Active"
group.long 0x22060++0x03
line.long 0x00 "PN_EST_CONTROL_REG,Enet Port N EST CONTROL"
hexmask.long.word 0x00 16.--25. 1. "EST_FILL_MARGIN,Transmit FIFO EST Fill Margin"
newline
hexmask.long.byte 0x00 9.--15. 1. "EST_PREMPT_COMP,Transmit FIFO EST Prempt Comparision Value"
newline
bitfld.long 0x00 8. "EST_FILL_EN,Transmit FIFO EST Fill Enable" "0,1"
newline
bitfld.long 0x00 5.--7. "EST_TS_PRI,Transmit FIFO EST TimeStamp Priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4. "EST_TS_ONEPRI,Transmit FIFO EST TimeStamp One Priority" "0,1"
newline
bitfld.long 0x00 3. "EST_TS_FIRST,Transmit FIFO EST TimeStamp First Express Packet" "0,1"
newline
bitfld.long 0x00 2. "EST_TS_EN,Transmit FIFO EST TimeStamp Enable" "0,1"
newline
bitfld.long 0x00 1. "EST_BUFSEL,Transmit FIFO EST Buffer Select" "0,1"
newline
bitfld.long 0x00 0. "EST_ONEBUF,Transmit FIFO EST One Buffer" "0,1"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22120)++0x03
line.long 0x00 "PN_RX_DSCP_MAP_REG_$1,Enet Port N Receive IPV4/IPV6 DSCP Map M"
bitfld.long 0x00 28.--30. "PRI7,A DSCP IPV4/V6 packet TOS of N*8+7 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 24.--26. "PRI6,A DSCP IPV4/V6 packet TOS of N*8+6 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 20.--22. "PRI5,A DSCP IPV4/V6 packet TOS of N*8+5 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "PRI4,A DSCP IPV4/V6 packet TOS of N*8+4 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 12.--14. "PRI3,A DSCP IPV4/V6 packet TOS of N*8+3 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "PRI2,A DSCP IPV4/V6 packet TOS of N*8+2 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 4.--6. "PRI1,A DSCP IPV4/V6 packet TOS of N*8+1 is mapped to this received priority" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "PRI0,A DSCP IPV4/V6 packet TOS of N*8+0 is mapped to this received priority" "0,1,2,3,4,5,6,7"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22140)++0x03
line.long 0x00 "PN_PRI_CIR_REG_$1,Enet Port N Rx Priority P Committed Information Rate Value"
hexmask.long 0x00 0.--27. 1. "PRI_CIR,Priority N committed information rate"
repeat.end
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22160)++0x03
line.long 0x00 "PN_PRI_EIR_REG_$1,Enet Port N Rx Priority P Excess Informatoin Rate Value"
hexmask.long 0x00 0.--27. 1. "PRI_EIR,Priority N Excess Information Rate count"
repeat.end
group.long 0x22180++0x1F
line.long 0x00 "PN_TX_D_THRESH_SET_L_REG,Enet Port N Tx PFC Destination Threshold Set Low"
bitfld.long 0x00 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "PN_TX_D_THRESH_SET_H_REG,Enet Port N Tx PFC Destination Threshold Set High"
bitfld.long 0x04 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "PN_TX_D_THRESH_CLR_L_REG,Enet Port N Tx PFC Destination Threshold Clr Low"
bitfld.long 0x08 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x08 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "PN_TX_D_THRESH_CLR_H_REG,Enet Port N Tx PFC Destination Threshold Clr High"
bitfld.long 0x0C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x0C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "PN_TX_G_BUF_THRESH_SET_L_REG,Enet Port N Tx PFC Global Buffer Threshold Set Low"
bitfld.long 0x10 24.--28. "PRI3,Port Priority Based Flow Control Threshold Set Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 16.--20. "PRI2,Port Priority Based Flow Control Threshold Set Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 8.--12. "PRI1,Port Priority Based Flow Control Threshold Set Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x10 0.--4. "PRI0,Port Priority Based Flow Control Threshold Set Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "PN_TX_G_BUF_THRESH_SET_H_REG,Enet Port N Tx PFC Global Buffer Threshold Set High"
bitfld.long 0x14 24.--28. "PRI7,Port Priority Based Flow Control Threshold Set Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 16.--20. "PRI6,Port Priority Based Flow Control Threshold Set Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 8.--12. "PRI5,Port Priority Based Flow Control Threshold Set Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 0.--4. "PRI4,Port Priority Based Flow Control Threshold Set Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "PN_TX_G_BUF_THRESH_CLR_L_REG,Enet Port N Tx PFC Global Buffer Threshold Clr Low"
bitfld.long 0x18 24.--28. "PRI3,Port Priority Based Flow Control Threshold Clear Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 16.--20. "PRI2,Port Priority Based Flow Control Threshold Clear Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 8.--12. "PRI1,Port Priority Based Flow Control Threshold Clear Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 0.--4. "PRI0,Port Priority Based Flow Control Threshold Clear Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "PN_TX_G_BUF_THRESH_CLR_H_REG,Enet Port N Tx PFC Global Buffer Threshold Clr High"
bitfld.long 0x1C 24.--28. "PRI7,Port Priority Based Flow Control Threshold Clear Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 16.--20. "PRI6,Port Priority Based Flow Control Threshold Clear Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 8.--12. "PRI5,Port Priority Based Flow Control Threshold Clear Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x1C 0.--4. "PRI4,Port Priority Based Flow Control Threshold Clear Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x22300++0x23
line.long 0x00 "PN_TX_D_OFLOW_ADDVAL_L_REG,Enet Port N Tx Destination Out Flow Add Values Low"
bitfld.long 0x00 24.--28. "PRI3,Port PFC Destination Based Out Flow Add Value for Priority 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 16.--20. "PRI2,Port PFC Destination Based Out Flow Add Value for Priority 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--12. "PRI1,Port PFC Destination Based Out Flow Add Value for Priority 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 0.--4. "PRI0,Port PFC Destination Based Out Flow Add Value for Priority 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x04 "PN_TX_D_OFLOW_ADDVAL_H_REG,Enet Port N Tx Destination Out Flow Add Values High"
bitfld.long 0x04 24.--28. "PRI7,Port PFC Destination Based Out Flow Add Value for Priority 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 16.--20. "PRI6,Port PFC Destination Based Out Flow Add Value for Priority 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 8.--12. "PRI5,Port PFC Destination Based Out Flow Add Value for Priority 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 0.--4. "PRI4,Port PFC Destination Based Out Flow Add Value for Priority 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "PN_SA_L_REG,Enet Port N Tx Pause Frame Source Address Low"
hexmask.long.byte 0x08 8.--15. 1. "MACSRCADDR_7_0,Source Address Lower 8 bits"
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hexmask.long.byte 0x08 0.--7. 1. "MACSRCADDR_15_8,Source Address bits 15:8"
line.long 0x0C "PN_SA_H_REG,Enet Port N Tx Pause Frame Source Address High"
hexmask.long.byte 0x0C 24.--31. 1. "MACSRCADDR_23_16,Source Address bits 23:16"
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hexmask.long.byte 0x0C 16.--23. 1. "MACSRCADDR_31_24,Source Address bits 31:24"
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hexmask.long.byte 0x0C 8.--15. 1. "MACSRCADDR_39_32,Source Address bits 39:32"
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hexmask.long.byte 0x0C 0.--7. 1. "MACSRCADDR_47_40,Source Address bits 47:40"
line.long 0x10 "PN_TS_CTL_REG,Enet Port N Time Sync Control"
hexmask.long.word 0x10 16.--31. 1. "TS_MSG_TYPE_EN,Time Sync Message Type Enable"
newline
bitfld.long 0x10 11. "TS_TX_HOST_TS_EN,Time Sync Transmit Host Time Stamp Enable" "0,1"
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bitfld.long 0x10 10. "TS_TX_ANNEX_E_EN,Time Synce Transmit Annex E Enable" "0,1"
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bitfld.long 0x10 9. "TS_RX_ANNEX_E_EN,Time Synce Receive Annex E Enable" "0,1"
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bitfld.long 0x10 8. "TS_LTYPE2_EN,Time Sync LTYPE 2 enable transmit and receive" "0,1"
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bitfld.long 0x10 7. "TS_TX_ANNEX_D_EN,Time Synce Transmit Annex D Enable" "0,1"
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bitfld.long 0x10 6. "TS_TX_VLAN_LTYPE2_E,Time Sync Transmit VLAN LTYPE 2 enable" "0,1"
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bitfld.long 0x10 5. "TS_TX_VLAN_LTYPE1_E,Time Sync Transmit VLAN LTYPE 1 enable" "0,1"
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bitfld.long 0x10 4. "TS_TX_ANNEX_F_EN,Time Synce Transmit Annex F Enable" "0,1"
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bitfld.long 0x10 3. "TS_RX_ANNEX_D_EN,Time Synce Receive Annex D Enable" "0,1"
newline
bitfld.long 0x10 2. "TS_RX_VLAN_LTYPE2_E,Time Sync Receive VLAN LTYPE 2 enable" "0,1"
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bitfld.long 0x10 1. "TS_RX_VLAN_LTYPE1_E,Time Sync Receive VLAN LTYPE 1 enable" "0,1"
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bitfld.long 0x10 0. "TS_RX_ANNEX_F_EN,Time Synce Receive Annex F Enable" "0,1"
line.long 0x14 "PN_TS_SEQ_LTYPE_REG,Enet Port N Time Sync LTYPE (and SEQ_ID_OFFSET)"
bitfld.long 0x14 16.--21. "TS_SEQ_ID_OFFSET,Time Sync Sequence ID Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x14 0.--15. 1. "TS_LTYPE1,Time Sync LTYPE1"
line.long 0x18 "PN_TS_VLAN_LTYPE_REG,Enet Port N Time Sync VLAN2 and VLAN2"
hexmask.long.word 0x18 16.--31. 1. "TS_VLAN_LTYPE2,Time Sync VLAN LTYPE2"
newline
hexmask.long.word 0x18 0.--15. 1. "TS_VLAN_LTYPE1,Time Sync VLAN LTYPE1"
line.long 0x1C "PN_TS_CTL_LTYPE2_REG,Enet Port N Time Sync Control and LTYPE 2"
bitfld.long 0x1C 24. "TS_UNI_EN,Time Sync Unicast Enable" "0,1"
newline
bitfld.long 0x1C 23. "TS_TTL_NONZERO,Time Sync Time to Live Non-zero Enable" "0,1"
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bitfld.long 0x1C 22. "TS_320,Time Sync Destination IP Address 320 Enable" "0,1"
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bitfld.long 0x1C 21. "TS_319,Time Sync Destination IP Address 319 Enable" "0,1"
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bitfld.long 0x1C 20. "TS_132,Time Sync Destination IP Address 132 Enable" "0,1"
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bitfld.long 0x1C 19. "TS_131,Time Sync Destination IP Address 131 Enable" "0,1"
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bitfld.long 0x1C 18. "TS_130,Time Sync Destination IP Address 130 Enable" "0,1"
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bitfld.long 0x1C 17. "TS_129,Time Sync Destination IP Address 129 Enable" "0,1"
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bitfld.long 0x1C 16. "TS_107,Time Sync Destination IP Address 107 Enable" "0,1"
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hexmask.long.word 0x1C 0.--15. 1. "TS_LTYPE2,Time Sync LTYPE2"
line.long 0x20 "PN_TS_CTL2_REG,Enet Port N Time Sync Control 2"
bitfld.long 0x20 16.--21. "TS_DOMAIN_OFFSET,Time Sync Domain Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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hexmask.long.word 0x20 0.--15. 1. "TS_MCAST_TYPE_EN,Time Sync Multicast Destination Address Type Enable"
group.long 0x22330++0x13
line.long 0x00 "PN_MAC_CONTROL_REG,Enet Port N Mac Control"
bitfld.long 0x00 24. "RX_CMF_EN,RX Copy MAC Control Frames Enable" "0,1"
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bitfld.long 0x00 23. "RX_CSF_EN,RX Copy Short Frames Enable" "0,1"
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bitfld.long 0x00 22. "RX_CEF_EN,RX Copy Error Frames Enable" "0,1"
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bitfld.long 0x00 21. "TX_SHORT_GAP_LIM_EN,Transmit Short Gap Limit Enable" "0,1"
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bitfld.long 0x00 20. "EXT_TX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
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bitfld.long 0x00 19. "EXT_RX_FLOW_EN,External Receive Flow Control Enable" "0,1"
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bitfld.long 0x00 18. "EXT_EN,External Enable" "0,1"
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bitfld.long 0x00 17. "GIG_FORCE,Gigabit Mode Force" "0,1"
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bitfld.long 0x00 16. "IFCTL_B,Interface Control B" "0,1"
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bitfld.long 0x00 15. "IFCTL_A,Interface Control A" "0,1"
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bitfld.long 0x00 12. "CRC_TYPE,Port CRC Type" "0,1"
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bitfld.long 0x00 11. "CMD_IDLE,Command Idle" "0,1"
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bitfld.long 0x00 10. "TX_SHORT_GAP_ENABLE,Transmit Short Gap Enable" "0,1"
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bitfld.long 0x00 7. "GIG,Gigabit Mode" "0,1"
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bitfld.long 0x00 6. "TX_PACE,Transmit Pacing Enable" "0,1"
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bitfld.long 0x00 5. "GMII_EN,GMII Enable" "0,1"
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bitfld.long 0x00 4. "TX_FLOW_EN,Transmit Flow Control Enable" "0,1"
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bitfld.long 0x00 3. "RX_FLOW_EN,Receive Flow Control Enable" "0,1"
newline
bitfld.long 0x00 2. "MTEST,Manufacturing Test Mode" "0,1"
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bitfld.long 0x00 1. "LOOPBACK,Loop Back Mode" "0,1"
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bitfld.long 0x00 0. "FULLDUPLEX,Full Duplex mode" "0,1"
line.long 0x04 "PN_MAC_STATUS_REG,Enet Port N Mac Status"
bitfld.long 0x04 31. "IDLE,cpxmac_sl IDLE" "0,1"
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bitfld.long 0x04 30. "E_IDLE,Express cpxmac_sl IDLE" "0,1"
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bitfld.long 0x04 28. "MAC_TX_IDLE,Prempt and Express cpxmac_sl Transmit IDLE" "0,1"
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bitfld.long 0x04 27. "TORF,Top of receive FIFO flow control trigger occurred" "0,1"
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bitfld.long 0x04 24.--26. "TORF_PRI,The lowest priority that caused top of receive FIFO flow control trigger since the last write to clear" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x04 16.--23. 1. "TX_PFC_FLOW_ACT,Transmit Priority Based Flow Control Active (priority 7 down to 0)"
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hexmask.long.byte 0x04 8.--15. 1. "RX_PFC_FLOW_ACT,Receive Priority Based Flow Control Active (priority 7 down to 0)"
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bitfld.long 0x04 6. "EXT_RX_FLOW_EN,External Transmit Flow Control Enable" "0,1"
newline
bitfld.long 0x04 5. "EXT_TX_FLOW_EN,External Receive Flow Control Enable" "0,1"
newline
bitfld.long 0x04 4. "EXT_GIG,External GIG mode" "0,1"
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bitfld.long 0x04 3. "EXT_FULLDUPLEX,External Fullduplex" "0,1"
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bitfld.long 0x04 1. "RX_FLOW_ACT,Receive Flow Control Active" "0,1"
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bitfld.long 0x04 0. "TX_FLOW_ACT,Transmit Flow Control Active" "0,1"
line.long 0x08 "PN_MAC_SOFT_RESET_REG,Enet Port N Mac Soft Reset"
bitfld.long 0x08 0. "SOFT_RESET,Software reset" "0,1"
line.long 0x0C "PN_MAC_BOFFTEST_REG,Enet Port N Mac Backoff Test"
bitfld.long 0x0C 26.--30. "PACEVAL,Pacing Register Current Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x0C 16.--25. 1. "RNDNUM,Backoff Random Number Generator"
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rbitfld.long 0x0C 12.--15. "COLL_COUNT,Collision Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x0C 0.--9. 1. "TX_BACKOFF,Backoff Count"
line.long 0x10 "PN_MAC_RX_PAUSETIMER_REG,Enet Port N 802.3 Receive Pause Timer"
hexmask.long.word 0x10 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22350)++0x03
line.long 0x00 "PN_MAC_RXN_PAUSETIMER_REG_$1,Enet Port N PFC Priority P Rx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "RX_PAUSETIMER,RX Pause Timer Value"
repeat.end
group.long 0x22370++0x03
line.long 0x00 "PN_MAC_TX_PAUSETIMER_REG,Enet Port N 802.3 Tx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value"
repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C )
group.long ($2+0x22380)++0x03
line.long 0x00 "PN_MAC_TXN_PAUSETIMER_REG_$1,Enet Port N PFC Priority P Tx Pause Timer"
hexmask.long.word 0x00 0.--15. 1. "TX_PAUSETIMER,TX Pause Timer Value"
repeat.end
group.long 0x223A0++0x07
line.long 0x00 "PN_MAC_EMCONTROL_REG,Enet Port N Emulation Control"
bitfld.long 0x00 1. "SOFT,Emulation Soft Bit" "0,1"
newline
bitfld.long 0x00 0. "FREE,Emulation Free Bit" "0,1"
line.long 0x04 "PN_MAC_TX_GAP_REG,Enet Port N Tx Inter Packet Gap"
hexmask.long.word 0x04 0.--15. 1. "TX_GAP,Transmit Inter-Packet Gap"
group.long 0x223AC++0x13
line.long 0x00 "PN_INTERVLAN_OPX_POINTER_REG,Enet Port N Tx Egress InterVLAN Operation Pointer"
bitfld.long 0x00 0.--2. "PN_INTERVLAN_OPX_POINTER_REG,Egress InterVLAN Operation Pointer" "0,1,2,3,4,5,6,7"
line.long 0x04 "PN_INTERVLAN_OPX_A_REG,Enet Port N Tx Egress InterVLAN A"
line.long 0x08 "PN_INTERVLAN_OPX_B_REG,Enet Port N Tx Egress InterVLAN B"
line.long 0x0C "PN_INTERVLAN_OPX_C_REG,Enet Port N Tx Egress InterVLAN C"
line.long 0x10 "PN_INTERVLAN_OPX_D_REG,Enet Port N Tx Egress InterVLAN D"
hexmask.long.word 0x10 0.--15. 1. "INTERVLAN_OPX_D,Egress InterVLAN D"
repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC )
group.long ($2+0x32000)++0x03
line.long 0x00 "FETCH_LOC_$1,The Revision Register contains the ID and revision information"
hexmask.long.tbyte 0x00 0.--21. 1. "LOC,RAM Location"
repeat.end
rgroup.long 0x34000++0x0B
line.long 0x00 "CPDMA_FH_IDVER_REG,CPDMA Transmit IDVER"
line.long 0x04 "CPDMA_FH_CONTROL_REG,CPDMA Transmit Control Register"
bitfld.long 0x04 0. "FH_EN,CPDMA Transmit DMA Enable" "0,1"
line.long 0x08 "CPDMA_FH_TEARDOWN_REG,CPDMA Transmit Teardown Register"
bitfld.long 0x08 31. "FH_TDN_RDY,CPDMA Transmit Teardown Ready" "0,1"
newline
bitfld.long 0x08 0.--2. "FH_TDN_CH,CPDMA Transmit Teardown Channel" "0,1,2,3,4,5,6,7"
rgroup.long 0x34010++0x1F
line.long 0x00 "CPDMA_TH_IDVER_REG,CPDMA Receive IDVER"
line.long 0x04 "CPDMA_TH_CONTROL_REG,CPDMA Receive Control Register"
bitfld.long 0x04 0. "TH_EN,CPDMA Receive DMA Enable" "0,1"
line.long 0x08 "CPDMA_TH_TEARDOWN_REG,CPDMA Receive Teardown Register"
bitfld.long 0x08 31. "TH_TDN_RDY,CPDMA Receive Teardown Ready" "0,1"
newline
bitfld.long 0x08 0.--2. "TH_TDN_CH,CPDMA Receive Teardown Channel" "0,1,2,3,4,5,6,7"
line.long 0x0C "CPDMA_SOFT_RESET_REG,CPDMA Soft Reset Register"
bitfld.long 0x0C 0. "SOFT_RESET,CPDMA and CPSW Soft Reset Enable" "0,1"
line.long 0x10 "CPDMA_CONTROL_REG,CPDMA Control Register"
bitfld.long 0x10 6. "TH_TS_ENCAP,CPDMA Receive TimeStamp Encapsulated" "0,1"
newline
bitfld.long 0x10 5. "TH_VLAN_ENCAP,CPDMA Receive VLAN Encapsulated" "0,1"
newline
bitfld.long 0x10 4. "TH_CEF,CPDMA Receive Copy Error Frames" "0,1"
newline
bitfld.long 0x10 3. "CMD_IDLE,CPDMA Command Idle" "0,1"
newline
bitfld.long 0x10 2. "TH_OFFLEN_BLOCK,CPDMA Receive Offset/Length Word Write Block" "0,1"
newline
bitfld.long 0x10 1. "TH_OWNERSHIP,CPDMA Receive Ownership Write Bit Value" "0,1"
newline
bitfld.long 0x10 0. "FH_PTYPE,CPDMA Transmit Queue Priority Type" "0,1"
line.long 0x14 "CPDMA_STATUS_REG,CPDMA Status Register"
bitfld.long 0x14 31. "IDLE,CPDMA Transmit Host Error Code" "0,1"
newline
bitfld.long 0x14 20.--23. "FH_HOST_ERROR_CODE,CPDMA Transmit Host Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 16.--18. "FH_ERR_CH,CPDMA Transmit Error Channel Number" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x14 12.--15. "TH_HOST_ERROR_CODE,CPDMA Receive Host Error Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 8.--10. "TH_ERR_CH,CPDMA Receive Error Channel Number" "0,1,2,3,4,5,6,7"
line.long 0x18 "CPDMA_TH_BUFFER_OFFSET_REG,CPDMA Receive Buffer Offset Register"
hexmask.long.word 0x18 0.--10. 1. "TH_BUFFER_OFFSET,CPDMA Receive Buffer Offset Register"
line.long 0x1C "CPDMA_EMULATION_CONTROL_REG,CPDMA Receive Buffer Offset Register"
bitfld.long 0x1C 1. "FREE,CPDMA Receive Buffer Offset Register" "0,1"
newline
bitfld.long 0x1C 0. "SOFT,CPDMA Receive Buffer Offset Register" "0,1"
rgroup.long 0x34080++0x17
line.long 0x00 "CPDMA_FH_INTSTAT_RAW_REG,CPDMA FHost Interrupt Status RAW"
bitfld.long 0x00 7. "FH7_PEND_RAW,CPDMA FHost Channel 7 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 6. "FH6_PEND_RAW,CPDMA FHost Channel 6 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 5. "FH5_PEND_RAW,CPDMA FHost Channel 5 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 4. "FH4_PEND_RAW,CPDMA FHost Channel 4 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 3. "FH3_PEND_RAW,CPDMA FHost Channel 3 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 2. "FH2_PEND_RAW,CPDMA FHost Channel 2 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 1. "FH1_PEND_RAW,CPDMA FHost Channel 1 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 0. "FH0_PEND_RAW,CPDMA FHost Channel 0 Interrupt Pending RAW" "0,1"
line.long 0x04 "CPDMA_FH_INTSTAT_MASKED_REG,CPDMA FHost Interrupt Status MASKED"
bitfld.long 0x04 7. "FH7_PEND_MASKED,CPDMA FHost Channel 7 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 6. "FH6_PEND_MASKED,CPDMA FHost Channel 6 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 5. "FH5_PEND_MASKED,CPDMA FHost Channel 5 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 4. "FH4_PEND_MASKED,CPDMA FHost Channel 4 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 3. "FH3_PEND_MASKED,CPDMA FHost Channel 3 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 2. "FH2_PEND_MASKED,CPDMA FHost Channel 2 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 1. "FH1_PEND_MASKED,CPDMA FHost Channel 1 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 0. "FH0_PEND_MASKED,CPDMA FHost Channel 0 Interrupt Pending MASKED" "0,1"
line.long 0x08 "CPDMA_FH_INTSTAT_MASKED_SET_REG,CPDMA FHost Interrupt Masked SET"
bitfld.long 0x08 7. "FH7_PEND_MASKED_SET,CPDMA FHost Channel 7 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 6. "FH6_PEND_MASKED_SET,CPDMA FHost Channel 6 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 5. "FH5_PEND_MASKED_SET,CPDMA FHost Channel 5 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 4. "FH4_PEND_MASKED_SET,CPDMA FHost Channel 4 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 3. "FH3_PEND_MASKED_SET,CPDMA FHost Channel 3 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 2. "FH2_PEND_MASKED_SET,CPDMA FHost Channel 2 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 1. "FH1_PEND_MASKED_SET,CPDMA FHost Channel 1 Interrupt Pending MASKED Set" "0,1"
newline
bitfld.long 0x08 0. "FH0_PEND_MASKED_SET,CPDMA FHost Channel 0 Interrupt Pending MASKED Set" "0,1"
line.long 0x0C "CPDMA_FH_INTSTAT_MASKED_CLR_REG,CPDMA FHost Interrupt Masked CLR"
bitfld.long 0x0C 7. "FH7_PEND_MASKED_CLR,CPDMA FHost Channel 7 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 6. "FH6_PEND_MASKED_CLR,CPDMA FHost Channel 6 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 5. "FH5_PEND_MASKED_CLR,CPDMA FHost Channel 5 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 4. "FH4_PEND_MASKED_CLR,CPDMA FHost Channel 4 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 3. "FH3_PEND_MASKED_CLR,CPDMA FHost Channel 3 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 2. "FH2_PEND_MASKED_CLR,CPDMA FHost Channel 2 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 1. "FH1_PEND_MASKED_CLR,CPDMA FHost Channel 1 Interrupt Pending MASKED Clr" "0,1"
newline
bitfld.long 0x0C 0. "FH0_PEND_MASKED_CLR,CPDMA FHost Channel 0 Interrupt Pending MASKED Clr" "0,1"
line.long 0x10 "CPDMA_IN_VECTOR_REG,CPDMA DMA IN Vector"
line.long 0x14 "CPDMA_EOI_VECTOR_REG,CPDMA DMA EOI Vector"
bitfld.long 0x14 0.--4. "DMA_EOI_VECTOR,CPDMA DMA EOI Vector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x340A0++0x5F
line.long 0x00 "CPDMA_TH_INTSTAT_RAW_REG,CPDMA Receive Interrupt Status RAW"
bitfld.long 0x00 15. "TH7_THRESH_PEND_RAW,CPDMA Receive Channel 7 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 14. "TH6_THRESH_PEND_RAW,CPDMA Receive Channel 6 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 13. "TH5_THRESH_PEND_RAW,CPDMA Receive Channel 5 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 12. "TH4_THRESH_PEND_RAW,CPDMA Receive Channel 4 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 11. "TH3_THRESH_PEND_RAW,CPDMA Receive Channel 3 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 10. "TH2_THRESH_PEND_RAW,CPDMA Receive Channel 2 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 9. "TH1_THRESH_PEND_RAW,CPDMA Receive Channel 1 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 8. "TH0_THRESH_PEND_RAW,CPDMA Receive Channel 0 Threshold Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 7. "TH7_PEND_RAW,CPDMA Receive Channel 7 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 6. "TH6_PEND_RAW,CPDMA Receive Channel 6 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 5. "TH5_PEND_RAW,CPDMA Receive Channel 5 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 4. "TH4_PEND_RAW,CPDMA Receive Channel 4 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 3. "TH3_PEND_RAW,CPDMA Receive Channel 3 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 2. "TH2_PEND_RAW,CPDMA Receive Channel 2 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 1. "TH1_PEND_RAW,CPDMA Receive Channel 1 Interrupt Pending RAW" "0,1"
newline
bitfld.long 0x00 0. "TH0_PEND_RAW,CPDMA Receive Channel 0 Interrupt Pending RAW" "0,1"
line.long 0x04 "CPDMA_TH_INTSTAT_MASKED_REG,CPDMA Receive Interrupt Status MASKED"
bitfld.long 0x04 15. "TH7_THRESH_PEND_MASKED,CPDMA Receive Channel 7 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 14. "TH6_THRESH_PEND_MASKED,CPDMA Receive Channel 6 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 13. "TH5_THRESH_PEND_MASKED,CPDMA Receive Channel 5 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 12. "TH4_THRESH_PEND_MASKED,CPDMA Receive Channel 4 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 11. "TH3_THRESH_PEND_MASKED,CPDMA Receive Channel 3 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 10. "TH2_THRESH_PEND_MASKED,CPDMA Receive Channel 2 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 9. "TH1_THRESH_PEND_MASKED,CPDMA Receive Channel 1 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 8. "TH0_THRESH_PEND_MASKED,CPDMA Receive Channel 0 Threshold Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 7. "TH7_PEND_MASKED,CPDMA Receive Channel 7 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 6. "TH6_PEND_MASKED,CPDMA Receive Channel 6 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 5. "TH5_PEND_MASKED,CPDMA Receive Channel 5 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 4. "TH4_PEND_MASKED,CPDMA Receive Channel 4 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 3. "TH3_PEND_MASKED,CPDMA Receive Channel 3 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 2. "TH2_PEND_MASKED,CPDMA Receive Channel 2 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 1. "TH1_PEND_MASKED,CPDMA Receive Channel 1 Interrupt Pending MASKED" "0,1"
newline
bitfld.long 0x04 0. "TH0_PEND_MASKED,CPDMA Receive Channel 0 Interrupt Pending MASKED" "0,1"
line.long 0x08 "CPDMA_TH_INTSTAT_SET_REG,CPDMA THost Interrupt Masked SET"
bitfld.long 0x08 15. "TH7_THRESH_PEND_MASKED_SET,CPDMA THost Channel 7 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 14. "TH6_THRESH_PEND_MASKED_SET,CPDMA THost Channel 6 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 13. "TH5_THRESH_PEND_MASKED_SET,CPDMA THost Channel 5 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 12. "TH4_THRESH_PEND_MASKED_SET,CPDMA THost Channel 4 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 11. "TH3_THRESH_PEND_MASKED_SET,CPDMA THost Channel 3 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 10. "TH2_THRESH_PEND_MASKED_SET,CPDMA THost Channel 2 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 9. "TH1_THRESH_PEND_MASKED_SET,CPDMA THost Channel 1 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 8. "TH0_THRESH_PEND_MASKED_SET,CPDMA THost Channel 0 Threshold Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 7. "TH7_PEND_MASKED_SET,CPDMA THost Channel 7 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 6. "TH6_PEND_MASKED_SET,CPDMA THost Channel 6 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 5. "TH5_PEND_MASKED_SET,CPDMA THost Channel 5 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 4. "TH4_PEND_MASKED_SET,CPDMA THost Channel 4 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 3. "TH3_PEND_MASKED_SET,CPDMA THost Channel 3 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 2. "TH2_PEND_MASKED_SET,CPDMA THost Channel 2 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 1. "TH1_PEND_MASKED_SET,CPDMA THost Channel 1 Interrupt Pending SET" "0,1"
newline
bitfld.long 0x08 0. "TH0_PEND_MASKED_SET,CPDMA THost Channel 0 Interrupt Pending SET" "0,1"
line.long 0x0C "CPDMA_TH_INTSTAT_CLR_REG,CPDMA THost Interrupt Masked CLR"
bitfld.long 0x0C 15. "TH7_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 7 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 14. "TH6_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 6 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 13. "TH5_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 5 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 12. "TH4_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 4 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 11. "TH3_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 3 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 10. "TH2_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 2 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 9. "TH1_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 1 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 8. "TH0_THRESH_PEND_MASKED_CLR,CPDMA THost Channel 0 Threshold Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 7. "TH7_PEND_MASKED_CLR,CPDMA THost Channel 7 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 6. "TH6_PEND_MASKED_CLR,CPDMA THost Channel 6 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 5. "TH5_PEND_MASKED_CLR,CPDMA THost Channel 5 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 4. "TH4_PEND_MASKED_CLR,CPDMA THost Channel 4 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 3. "TH3_PEND_MASKED_CLR,CPDMA THost Channel 3 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 2. "TH2_PEND_MASKED_CLR,CPDMA THost Channel 2 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 1. "TH1_PEND_MASKED_CLR,CPDMA THost Channel 1 Interrupt Pending CLR" "0,1"
newline
bitfld.long 0x0C 0. "TH0_PEND_MASKED_CLR,CPDMA THost Channel 0 Interrupt Pending CLR" "0,1"
line.long 0x10 "CPDMA_INTSTAT_RAW_REG,CPDMA DMA Interrupt Status RAW"
bitfld.long 0x10 1. "HOST_PEND_RAW,CPDMA HOST Interrupt Pending RAW" "0,1"
line.long 0x14 "CPDMA_INTSTAT_MASKED_REG,CPDMA DMA Interrupt Status MASKED"
bitfld.long 0x14 1. "HOST_PEND,CPDMA HOST Interrupt Pending MASKED" "0,1"
line.long 0x18 "CPDMA_INTSTAT_SET_REG,CPDMA DMA Interrupt Status SET"
bitfld.long 0x18 1. "HOST_PEND_MASKED_SET,CPDMA HOST Interrupt Masked SET" "0,1"
line.long 0x1C "CPDMA_INTSTAT_CLR_REG,CPDMA DMA Interrupt Status CLR"
bitfld.long 0x1C 1. "HOST_PEND_MASKED_CLR,CPDMA HOST Interrupt Masked CLR" "0,1"
line.long 0x20 "CPDMA_TH0_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x20 0.--7. 1. "TH0_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x24 "CPDMA_TH1_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x24 0.--7. 1. "TH1_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x28 "CPDMA_TH2_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x28 0.--7. 1. "TH2_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x2C "CPDMA_TH3_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x2C 0.--7. 1. "TH3_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x30 "CPDMA_TH4_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x30 0.--7. 1. "TH4_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x34 "CPDMA_TH5_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x34 0.--7. 1. "TH5_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x38 "CPDMA_TH6_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x38 0.--7. 1. "TH6_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x3C "CPDMA_TH7_PENDTHRESH_REG,CPDMA THost Threshold Pending Register"
hexmask.long.byte 0x3C 0.--7. 1. "TH7_PENDTHRESH,CPDMA THost Threshold Pending Register"
line.long 0x40 "CPDMA_TH0_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x40 0.--14. 1. "TH0_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x44 "CPDMA_TH1_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x44 0.--14. 1. "TH1_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x48 "CPDMA_TH2_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x48 0.--14. 1. "TH2_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x4C "CPDMA_TH3_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x4C 0.--14. 1. "TH3_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x50 "CPDMA_TH4_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x50 0.--14. 1. "TH4_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x54 "CPDMA_TH5_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x54 0.--14. 1. "TH5_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x58 "CPDMA_TH6_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x58 0.--14. 1. "TH6_FREEBUFFER,CPDMA THost Free Buffer Count Register"
line.long 0x5C "CPDMA_TH7_FREEBUFFER_REG,CPDMA THost Free Buffer Count Register"
hexmask.long.word 0x5C 0.--14. 1. "TH7_FREEBUFFER,CPDMA THost Free Buffer Count Register"
group.long 0x34200++0x7F
line.long 0x00 "CPDMA_FH0_HDP_REG,CPDMA FHost Channel 0 Head Descriptor Pointer"
line.long 0x04 "CPDMA_FH1_HDP_REG,CPDMA FHost Channel 1 Head Descriptor Pointer"
line.long 0x08 "CPDMA_FH2_HDP_REG,CPDMA FHost Channel 2 Head Descriptor Pointer"
line.long 0x0C "CPDMA_FH3_HDP_REG,CPDMA FHost Channel 3 Head Descriptor Pointer"
line.long 0x10 "CPDMA_FH4_HDP_REG,CPDMA FHost Channel 4 Head Descriptor Pointer"
line.long 0x14 "CPDMA_FH5_HDP_REG,CPDMA FHost Channel 5 Head Descriptor Pointer"
line.long 0x18 "CPDMA_FH6_HDP_REG,CPDMA FHost Channel 6 Head Descriptor Pointer"
line.long 0x1C "CPDMA_FH7_HDP_REG,CPDMA FHost Channel 7 Head Descriptor Pointer"
line.long 0x20 "CPDMA_TH0_HDP_REG,CPDMA THost Channel 0 Head Descriptor Pointer"
line.long 0x24 "CPDMA_TH1_HDP_REG,CPDMA THost Channel 1 Head Descriptor Pointer"
line.long 0x28 "CPDMA_TH2_HDP_REG,CPDMA THost Channel 2 Head Descriptor Pointer"
line.long 0x2C "CPDMA_TH3_HDP_REG,CPDMA THost Channel 3 Head Descriptor Pointer"
line.long 0x30 "CPDMA_TH4_HDP_REG,CPDMA THost Channel 4 Head Descriptor Pointer"
line.long 0x34 "CPDMA_TH5_HDP_REG,CPDMA THost Channel 5 Head Descriptor Pointer"
line.long 0x38 "CPDMA_TH6_HDP_REG,CPDMA THost Channel 6 Head Descriptor Pointer"
line.long 0x3C "CPDMA_TH7_HDP_REG,CPDMA THost Channel 7 Head Descriptor Pointer"
line.long 0x40 "CPDMA_FH0_CP_REG,CPDMA FHost Channel 0 Completion Pointer"
line.long 0x44 "CPDMA_FH1_CP_REG,CPDMA FHost Channel 1 Completion Pointer"
line.long 0x48 "CPDMA_FH2_CP_REG,CPDMA FHost Channel 2 Completion Pointer"
line.long 0x4C "CPDMA_FH3_CP_REG,CPDMA FHost Channel 3 Completion Pointer"
line.long 0x50 "CPDMA_FH4_CP_REG,CPDMA FHost Channel 4 Completion Pointer"
line.long 0x54 "CPDMA_FH5_CP_REG,CPDMA FHost Channel 5 Completion Pointer"
line.long 0x58 "CPDMA_FH6_CP_REG,CPDMA FHost Channel 6 Completion Pointer"
line.long 0x5C "CPDMA_FH7_CP_REG,CPDMA FHost Channel 7 Completion Pointer"
line.long 0x60 "CPDMA_TH0_CP_REG,CPDMA THost Channel 0 Completion Pointer"
line.long 0x64 "CPDMA_TH1_CP_REG,CPDMA THost Channel 1 Completion Pointer"
line.long 0x68 "CPDMA_TH2_CP_REG,CPDMA THost Channel 2 Completion Pointer"
line.long 0x6C "CPDMA_TH3_CP_REG,CPDMA THost Channel 3 Completion Pointer"
line.long 0x70 "CPDMA_TH4_CP_REG,CPDMA THost Channel 4 Completion Pointer"
line.long 0x74 "CPDMA_TH5_CP_REG,CPDMA THost Channel 5 Completion Pointer"
line.long 0x78 "CPDMA_TH6_CP_REG,CPDMA THost Channel 6 Completion Pointer"
line.long 0x7C "CPDMA_TH7_CP_REG,CPDMA THost Channel 7 Completion Pointer"
group.long 0x34300++0x7F
line.long 0x00 "TEST_CPDMA_FH0_HDP_REG,Test CPDMA FHost Channel 0 Head Descriptor Pointer"
line.long 0x04 "TEST_CPDMA_FH1_HDP_REG,Test CPDMA FHost Channel 1 Head Descriptor Pointer"
line.long 0x08 "TEST_CPDMA_FH2_HDP_REG,Test CPDMA FHost Channel 2 Head Descriptor Pointer"
line.long 0x0C "TEST_CPDMA_FH3_HDP_REG,Test CPDMA FHost Channel 3 Head Descriptor Pointer"
line.long 0x10 "TEST_CPDMA_FH4_HDP_REG,Test CPDMA FHost Channel 4 Head Descriptor Pointer"
line.long 0x14 "TEST_CPDMA_FH5_HDP_REG,Test CPDMA FHost Channel 5 Head Descriptor Pointer"
line.long 0x18 "TEST_CPDMA_FH6_HDP_REG,Test CPDMA FHost Channel 6 Head Descriptor Pointer"
line.long 0x1C "TEST_CPDMA_FH7_HDP_REG,Test CPDMA FHost Channel 7 Head Descriptor Pointer"
line.long 0x20 "TEST_CPDMA_TH0_HDP_REG,Test CPDMA THost Channel 0 Head Descriptor Pointer"
line.long 0x24 "TEST_CPDMA_TH1_HDP_REG,Test CPDMA THost Channel 1 Head Descriptor Pointer"
line.long 0x28 "TEST_CPDMA_TH2_HDP_REG,Test CPDMA THost Channel 2 Head Descriptor Pointer"
line.long 0x2C "TEST_CPDMA_TH3_HDP_REG,Test CPDMA THost Channel 3 Head Descriptor Pointer"
line.long 0x30 "TEST_CPDMA_TH4_HDP_REG,Test CPDMA THost Channel 4 Head Descriptor Pointer"
line.long 0x34 "TEST_CPDMA_TH5_HDP_REG,Test CPDMA THost Channel 5 Head Descriptor Pointer"
line.long 0x38 "TEST_CPDMA_TH6_HDP_REG,Test CPDMA THost Channel 6 Head Descriptor Pointer"
line.long 0x3C "TEST_CPDMA_TH7_HDP_REG,Test CPDMA THost Channel 7 Head Descriptor Pointer"
line.long 0x40 "TEST_CPDMA_FH0_CP_REG,Test CPDMA FHost Channel 0 Completion Pointer"
line.long 0x44 "TEST_CPDMA_FH1_CP_REG,Test CPDMA FHost Channel 1 Completion Pointer"
line.long 0x48 "TEST_CPDMA_FH2_CP_REG,Test CPDMA FHost Channel 2 Completion Pointer"
line.long 0x4C "TEST_CPDMA_FH3_CP_REG,Test CPDMA FHost Channel 3 Completion Pointer"
line.long 0x50 "TEST_CPDMA_FH4_CP_REG,Test CPDMA FHost Channel 4 Completion Pointer"
line.long 0x54 "TEST_CPDMA_FH5_CP_REG,Test CPDMA FHost Channel 5 Completion Pointer"
line.long 0x58 "TEST_CPDMA_FH6_CP_REG,Test CPDMA FHost Channel 6 Completion Pointer"
line.long 0x5C "TEST_CPDMA_FH7_CP_REG,Test CPDMA FHost Channel 7 Completion Pointer"
line.long 0x60 "TEST_CPDMA_TH0_CP_REG,Test CPDMA THost Channel 0 Completion Pointer"
line.long 0x64 "TEST_CPDMA_TH1_CP_REG,Test CPDMA THost Channel 1 Completion Pointer"
line.long 0x68 "TEST_CPDMA_TH2_CP_REG,Test CPDMA THost Channel 2 Completion Pointer"
line.long 0x6C "TEST_CPDMA_TH3_CP_REG,Test CPDMA THost Channel 3 Completion Pointer"
line.long 0x70 "TEST_CPDMA_TH4_CP_REG,Test CPDMA THost Channel 4 Completion Pointer"
line.long 0x74 "TEST_CPDMA_TH5_CP_REG,Test CPDMA THost Channel 5 Completion Pointer"
line.long 0x78 "TEST_CPDMA_TH6_CP_REG,Test CPDMA THost Channel 6 Completion Pointer"
line.long 0x7C "TEST_CPDMA_TH7_CP_REG,Test CPDMA THost Channel 7 Completion Pointer"
group.long 0x3A000++0x0B
line.long 0x00 "RXGOODFRAMES,Total number of good frames received"
line.long 0x04 "RXBROADCASTFRAMES,Total number of good broadcast frames received"
line.long 0x08 "RXMULTICASTFRAMES,Total number of good multicast frames received"
group.long 0x3A010++0x03
line.long 0x00 "RXCRCERRORS,Total number of CRC errors frames received"
group.long 0x3A018++0x03
line.long 0x00 "RXOVERSIZEDFRAMES,Total number of oversized frames received"
group.long 0x3A020++0x1F
line.long 0x00 "RXUNDERSIZEDFRAMES,Total number of undersized frames received"
line.long 0x04 "RXFRAGMENTS,Total number of fragmented frames received"
line.long 0x08 "ALE_DROP,Total number of frames dropped by the ALE"
line.long 0x0C "ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
line.long 0x10 "RXOCTETS,Total number of received bytes in good frames"
line.long 0x14 "TXGOODFRAMES,Total number of good frames transmitted"
line.long 0x18 "TXBROADCASTFRAMES,Total number of good broadcast frames transmitted"
line.long 0x1C "TXMULTICASTFRAMES,Total number of good multicast frames transmitted"
group.long 0x3A04C++0x07
line.long 0x00 "TXSINGLECOLLFRAMES,Total number of transmitted frames experiencing a single collision"
line.long 0x04 "TXMULTCOLLFRAMES,Total number of transmitted frames experiencing multiple collisions"
group.long 0x3A064++0x7B
line.long 0x00 "TXOCTETS,Total number of bytes in all good frames transmitted"
line.long 0x04 "OCTETFRAMES64,Total number of 64-byte frames received and transmitted"
line.long 0x08 "OCTETFRAMES65T127,Total number of frames of size 65 to 127 bytes received and transmitted"
line.long 0x0C "OCTETFRAMES128T255,Total number of frames of size 128 to 255 bytes received and transmitted"
line.long 0x10 "OCTETFRAMES256T511,Total number of frames of size 256 to 511 bytes received and transmitted"
line.long 0x14 "OCTETFRAMES512T1023,Total number of frames of size 512 to 1023 bytes received and transmitted"
line.long 0x18 "OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
line.long 0x1C "NETOCTETS,Total number of bytes received and transmitted"
line.long 0x20 "RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop"
line.long 0x24 "PORTMASK_DROP,Total number of dropped frames received due to portmask"
line.long 0x28 "RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop"
line.long 0x2C "ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting"
line.long 0x30 "ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress"
line.long 0x34 "ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA"
line.long 0x38 "ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode"
line.long 0x3C "ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode"
line.long 0x40 "ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication"
line.long 0x44 "ALE_UNKN_UNI,ALE Receive Unknown Unicast"
line.long 0x48 "ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount"
line.long 0x4C "ALE_UNKN_MLT,ALE Receive Unknown Multicast"
line.long 0x50 "ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount"
line.long 0x54 "ALE_UNKN_BRD,ALE Receive Unknown Broadcast"
line.long 0x58 "ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount"
line.long 0x5C "ALE_POL_MATCH,ALE Policer Matched"
line.long 0x60 "ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red"
line.long 0x64 "ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow"
line.long 0x68 "ALE_MULT_SA_DROP,ALE Multicast Source Address Drop"
line.long 0x6C "ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop"
line.long 0x70 "ALE_LEN_ERROR_DROP,ALE Length Error Drop"
line.long 0x74 "ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop"
line.long 0x78 "ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop"
group.long 0x3A17C++0x03
line.long 0x00 "TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error"
group.long 0x3A200++0xDF
line.long 0x00 "RXGOODFRAMES,Total number of good frames received"
line.long 0x04 "RXBROADCASTFRAMES,Total number of good broadcast frames received"
line.long 0x08 "RXMULTICASTFRAMES,Total number of good multicast frames received"
line.long 0x0C "RXPAUSEFRAMES,Total number of pause frames received"
line.long 0x10 "RXCRCERRORS,Total number of CRC errors frames received"
line.long 0x14 "RXALIGNCODEERRORS,Total number of alignment/code errors received"
line.long 0x18 "RXOVERSIZEDFRAMES,Total number of oversized frames received"
line.long 0x1C "RXJABBERFRAMES,Total number of jabber frames received"
line.long 0x20 "RXUNDERSIZEDFRAMES,Total number of undersized frames received"
line.long 0x24 "RXFRAGMENTS,Total number of fragmented frames received"
line.long 0x28 "ALE_DROP,Total number of frames dropped by the ALE"
line.long 0x2C "ALE_OVERRUN_DROP,Total number of overrun frames dropped by the ALE"
line.long 0x30 "RXOCTETS,Total number of received bytes in good frames"
line.long 0x34 "TXGOODFRAMES,Total number of good frames transmitted"
line.long 0x38 "TXBROADCASTFRAMES,Total number of good broadcast frames transmitted"
line.long 0x3C "TXMULTICASTFRAMES,Total number of good multicast frames transmitted"
line.long 0x40 "TXPAUSEFRAMES,Total number of pause frames transmitted"
line.long 0x44 "TXDEFERREDFRAMES,Total number of deferred frames transmitted"
line.long 0x48 "TXCOLLISIONFRAMES,Total number of transmitted frames experiencing a collision"
line.long 0x4C "TXSINGLECOLLFRAMES,Total number of transmitted frames experiencing a single collision"
line.long 0x50 "TXMULTCOLLFRAMES,Total number of transmitted frames experiencing multiple collisions"
line.long 0x54 "TXEXCESSIVECOLLISIONS,Total number of transmitted frames abandoned due to excessive collisions"
line.long 0x58 "TXLATECOLLISIONS,Total number of transmitted frames abandoned due to a late collision"
line.long 0x5C "RXIPGERROR,Total number of receive inter-packet gap errors (10G only)"
line.long 0x60 "TXCARRIERSENSEERRORS,Total number of transmitted frames that experienced a carrier loss"
line.long 0x64 "TXOCTETS,Total number of bytes in all good frames transmitted"
line.long 0x68 "OCTETFRAMES64,Total number of 64-byte frames received and transmitted"
line.long 0x6C "OCTETFRAMES65T127,Total number of frames of size 65 to 127 bytes received and transmitted"
line.long 0x70 "OCTETFRAMES128T255,Total number of frames of size 128 to 255 bytes received and transmitted"
line.long 0x74 "OCTETFRAMES256T511,Total number of frames of size 256 to 511 bytes received and transmitted"
line.long 0x78 "OCTETFRAMES512T1023,Total number of frames of size 512 to 1023 bytes received and transmitted"
line.long 0x7C "OCTETFRAMES1024TUP,Total number of frames of size 1024 to rx_maxlen bytes received and 1024 bytes or greater transmitted"
line.long 0x80 "NETOCTETS,Total number of bytes received and transmitted"
line.long 0x84 "RX_BOTTOM_OF_FIFO_DROP,Receive Bottom of FIFO Drop"
line.long 0x88 "PORTMASK_DROP,Total number of dropped frames received due to portmask"
line.long 0x8C "RX_TOP_OF_FIFO_DROP,Receive Top of FIFO Drop"
line.long 0x90 "ALE_RATE_LIMIT_DROP,Total number of dropped frames due to ALE Rate Limiting"
line.long 0x94 "ALE_VID_INGRESS_DROP,Total number of dropped frames due to ALE VID Ingress"
line.long 0x98 "ALE_DA_EQ_SA_DROP,Total number of dropped frames due to DA=SA"
line.long 0x9C "ALE_BLOCK_DROP,Total number of dropped frames due to ALE Block Mode"
line.long 0xA0 "ALE_SECURE_DROP,Total number of dropped frames due to ALE Secure Mode"
line.long 0xA4 "ALE_AUTH_DROP,Total number of dropped frames due to ALE Authentication"
line.long 0xA8 "ALE_UNKN_UNI,ALE Receive Unknown Unicast"
line.long 0xAC "ALE_UNKN_UNI_BCNT,ALE Receive Unknown Unicast Bytecount"
line.long 0xB0 "ALE_UNKN_MLT,ALE Receive Unknown Multicast"
line.long 0xB4 "ALE_UNKN_MLT_BCNT,ALE Receive Unknown Multicast Bytecount"
line.long 0xB8 "ALE_UNKN_BRD,ALE Receive Unknown Broadcast"
line.long 0xBC "ALE_UNKN_BRD_BCNT,ALE Receive Unknown Broadcast Bytecount"
line.long 0xC0 "ALE_POL_MATCH,ALE Policer Matched"
line.long 0xC4 "ALE_POL_MATCH_RED,ALE Policer Matched and Condition Red"
line.long 0xC8 "ALE_POL_MATCH_YELLOW,ALE Policer Matched and Condition Yellow"
line.long 0xCC "ALE_MULT_SA_DROP,ALE Multicast Source Address Drop"
line.long 0xD0 "ALE_DUAL_VLAN_DROP,ALE Dual VLAN Drop"
line.long 0xD4 "ALE_LEN_ERROR_DROP,ALE Length Error Drop"
line.long 0xD8 "ALE_IP_NEXT_HDR_DROP,ALE IP Next Header Drop"
line.long 0xDC "ALE_IPV4_FRAG_DROP,ALE IPV4 Frag Drop"
group.long 0x3A37C++0x83
line.long 0x00 "TX_MEMORY_PROTECT_ERROR,Transmit Memory Protect CRC Error"
hexmask.long.byte 0x00 0.--7. 1. "COUNT,Transmit Memory Protect CRC Error"
line.long 0x04 "ENET_PN_TX_PRI_REG_0,ENET Port n PRIORITY N Packet Count"
line.long 0x08 "ENET_PN_TX_PRI_REG_1,ENET Port n PRIORITY N Packet Count"
line.long 0x0C "ENET_PN_TX_PRI_REG_2,ENET Port n PRIORITY N Packet Count"
line.long 0x10 "ENET_PN_TX_PRI_REG_3,ENET Port n PRIORITY N Packet Count"
line.long 0x14 "ENET_PN_TX_PRI_REG_4,ENET Port n PRIORITY N Packet Count"
line.long 0x18 "ENET_PN_TX_PRI_REG_5,ENET Port n PRIORITY N Packet Count"
line.long 0x1C "ENET_PN_TX_PRI_REG_6,ENET Port n PRIORITY N Packet Count"
line.long 0x20 "ENET_PN_TX_PRI_REG_7,ENET Port n PRIORITY N Packet Count"
line.long 0x24 "ENET_PN_TX_PRI_BCNT_REG_0,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x28 "ENET_PN_TX_PRI_BCNT_REG_1,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x2C "ENET_PN_TX_PRI_BCNT_REG_2,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x30 "ENET_PN_TX_PRI_BCNT_REG_3,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x34 "ENET_PN_TX_PRI_BCNT_REG_4,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x38 "ENET_PN_TX_PRI_BCNT_REG_5,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x3C "ENET_PN_TX_PRI_BCNT_REG_6,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x40 "ENET_PN_TX_PRI_BCNT_REG_7,ENET Port n PRIORITY N Packet Byte Count"
line.long 0x44 "ENET_PN_TX_PRI_DROP_REG_0,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x48 "ENET_PN_TX_PRI_DROP_REG_1,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x4C "ENET_PN_TX_PRI_DROP_REG_2,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x50 "ENET_PN_TX_PRI_DROP_REG_3,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x54 "ENET_PN_TX_PRI_DROP_REG_4,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x58 "ENET_PN_TX_PRI_DROP_REG_5,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x5C "ENET_PN_TX_PRI_DROP_REG_6,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x60 "ENET_PN_TX_PRI_DROP_REG_7,ENET Port n PRIORITY N Packet Drop Count"
line.long 0x64 "ENET_PN_TX_PRI_DROP_BCNT_REG_0,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x68 "ENET_PN_TX_PRI_DROP_BCNT_REG_1,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x6C "ENET_PN_TX_PRI_DROP_BCNT_REG_2,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x70 "ENET_PN_TX_PRI_DROP_BCNT_REG_3,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x74 "ENET_PN_TX_PRI_DROP_BCNT_REG_4,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x78 "ENET_PN_TX_PRI_DROP_BCNT_REG_5,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x7C "ENET_PN_TX_PRI_DROP_BCNT_REG_6,ENET Port n PRIORITY N Packet Drop Byte Count"
line.long 0x80 "ENET_PN_TX_PRI_DROP_BCNT_REG_7,ENET Port n PRIORITY N Packet Drop Byte Count"
rgroup.long 0x3D000++0x5B
line.long 0x00 "IDVER_REG,Identification and Version Register"
hexmask.long.word 0x00 16.--31. 1. "TX_IDENT,Identification value"
newline
bitfld.long 0x00 11.--15. "RTL_VER,RTL version value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR_VER,Major version value" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x00 0.--7. 1. "MINOR_VER,Minor version value"
line.long 0x04 "CONTROL_REG,Time Sync Control Register"
bitfld.long 0x04 28.--31. "TS_SYNC_SEL,TS_SYNC output timestamp counter bit select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 17. "TS_GENF_CLR_EN,Enable for GENF clear when length is zero" "0,1"
newline
bitfld.long 0x04 16. "TS_RX_NO_EVENT,Receive Produces no Events" "0,1"
newline
bitfld.long 0x04 15. "HW8_TS_PUSH_EN,Hardware push 8 enable" "0,1"
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bitfld.long 0x04 14. "HW7_TS_PUSH_EN,Hardware push 7 enable" "0,1"
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bitfld.long 0x04 13. "HW6_TS_PUSH_EN,Hardware push 6 enable" "0,1"
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bitfld.long 0x04 12. "HW5_TS_PUSH_EN,Hardware push 5 enable" "0,1"
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bitfld.long 0x04 11. "HW4_TS_PUSH_EN,Hardware push 4 enable" "0,1"
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bitfld.long 0x04 10. "HW3_TS_PUSH_EN,Hardware push 3 enable" "0,1"
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bitfld.long 0x04 9. "HW2_TS_PUSH_EN,Hardware push 2 enable" "0,1"
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bitfld.long 0x04 8. "HW1_TS_PUSH_EN,Hardware push 1 enable" "0,1"
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bitfld.long 0x04 7. "TS_PPM_DIR,Timestamp PPM Direction" "0,1"
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bitfld.long 0x04 6. "TS_COMP_TOG,Timestamp Compare Toggle mode" "TS_COMP is in non-toggle mode,TS_COMP is in toggle mode"
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bitfld.long 0x04 5. "MODE,Timestamp mode" "0,1"
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bitfld.long 0x04 4. "SEQUENCE_EN,Sequence Enable" "0,1"
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bitfld.long 0x04 3. "TSTAMP_EN,Host Receive Timestamp Enable" "0,1"
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bitfld.long 0x04 2. "TS_COMP_POLARITY,TS_COMP polarity" "0,1"
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bitfld.long 0x04 1. "INT_TEST,Interrupt test" "0,1"
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bitfld.long 0x04 0. "CPTS_EN,Time sync enable" "0,1"
line.long 0x08 "RFTCLK_SEL_REG,RFTCLK Select Register"
bitfld.long 0x08 0.--4. "RFTCLK_SEL,Reference clock select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "TS_PUSH_REG,Time Stamp Event Push Register"
bitfld.long 0x0C 0. "TS_PUSH,Time stamp event push" "0,1"
line.long 0x10 "TS_LOAD_VAL_REG,Time Stamp Load Low Value Register"
line.long 0x14 "TS_LOAD_EN_REG,Time Stamp Load Enable Register"
bitfld.long 0x14 0. "TS_LOAD_EN,Time stamp load enable" "0,1"
line.long 0x18 "TS_COMP_VAL_REG,Time Stamp Comparison Low Value Register"
line.long 0x1C "TS_COMP_LEN_REG,Time Stamp Comparison Length Register"
line.long 0x20 "INTSTAT_RAW_REG,Interrupt Status Register Raw"
bitfld.long 0x20 0. "TS_PEND_RAW,TS_PEND_RAW int read (before enable)" "0,1"
line.long 0x24 "INTSTAT_MASKED_REG,Interrupt Status Register Masked"
bitfld.long 0x24 0. "TS_PEND,TS_PEND masked interrupt read (after enable)" "0,1"
line.long 0x28 "INT_ENABLE_REG,Interrupt Enable Register"
bitfld.long 0x28 0. "TS_PEND_EN,TS_PEND masked interrupt enable" "0,1"
line.long 0x2C "TS_COMP_NUDGE_REG,Time Stamp Comparison Nudge Register"
hexmask.long.byte 0x2C 0.--7. 1. "NUDGE,This 2s complement number is added to the ts_comp_length value to increase or decrease the TS_COMP length by the nudge amount"
line.long 0x30 "EVENT_POP_REG,Event Pop Register"
bitfld.long 0x30 0. "EVENT_POP,Event pop" "0,1"
line.long 0x34 "EVENT_0_REG,Event 0 Register"
line.long 0x38 "EVENT_1_REG,Event 1 Register"
bitfld.long 0x38 29. "PREMPT_QUEUE,Prempt QUEUE" "0,1"
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bitfld.long 0x38 24.--28. "PORT_NUMBER,Port number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x38 20.--23. "EVENT_TYPE,Event type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x38 16.--19. "MESSAGE_TYPE,Message type" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x38 0.--15. 1. "SEQUENCE_ID,Sequence ID"
line.long 0x3C "EVENT_2_REG,Event 2 Register"
hexmask.long.byte 0x3C 0.--7. 1. "DOMAIN,Domain"
line.long 0x40 "EVENT_3_REG,Event 3 Register"
line.long 0x44 "TS_LOAD_HIGH_VAL_REG,Time Stamp Load High Value Register"
line.long 0x48 "TS_COMP_HIGH_VAL_REG,Time Stamp Comparison High Value Register"
line.long 0x4C "TS_ADD_VAL_REG,TS Add Value Register"
bitfld.long 0x4C 0.--2. "ADD_VAL,Add Value" "0,1,2,3,4,5,6,7"
line.long 0x50 "TS_PPM_LOW_VAL_REG,Time Stamp PPM Low Value Register"
line.long 0x54 "TS_PPM_HIGH_VAL_REG,Time Stamp PPM High Value Register"
hexmask.long.word 0x54 0.--9. 1. "TS_PPM_HIGH_VAL,Time stamp PPM High value"
line.long 0x58 "TS_NUDGE_VAL_REG,Time Stamp Nudge Value Register"
hexmask.long.byte 0x58 0.--7. 1. "TS_NUDGE_VAL,Time stamp Nudge value"
group.long 0x3D0E0++0x1B
line.long 0x00 "COMP_LOW_REG,Time Stamp Generate Function Comparison Low Value"
line.long 0x04 "COMP_HIGH_REG,Time Stamp Generate Function Comparison high Value"
line.long 0x08 "CONTROL_REG,Time Stamp Generate Function Control"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp Generate Function Polarity Invert" "0,1"
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bitfld.long 0x08 0. "PPM_DIR,Time Stamp Generate Function PPM Direction" "0,1"
line.long 0x0C "LENGTH_REG,Time Stamp Generate Function Length Value"
line.long 0x10 "PPM_LOW_REG,Time Stamp Generate Function PPM Low Value"
line.long 0x14 "PPM_HIGH_REG,Time Stamp Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp Generate Function PPM High Value"
line.long 0x18 "NUDGE_REG,Time Stamp Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp Generate Function Nudge Value"
group.long 0x3D200++0x1B
line.long 0x00 "COMP_LOW_REG,Time Stamp ESTF Generate Function Comparison Low Value"
line.long 0x04 "COMP_HIGH_REG,Time Stamp ESTF Generate Function Comparison high Value"
line.long 0x08 "CONTROL_REG,Time Stamp ESTF Generate Function Control"
bitfld.long 0x08 1. "POLARITY_INV,Time Stamp ESTF Generate Function Polarity Invert" "0,1"
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bitfld.long 0x08 0. "PPM_DIR,Time Stamp ESTF Generate Function PPM Direction" "0,1"
line.long 0x0C "LENGTH_REG,Time Stamp ESTF Generate Function Length Value"
line.long 0x10 "PPM_LOW_REG,Time Stamp ESTF Generate Function PPM Low Value"
line.long 0x14 "PPM_HIGH_REG,Time Stamp ESTF Generate Function PPM High Value"
hexmask.long.word 0x14 0.--9. 1. "PPM_HIGH,Time Stamp ESTF Generate Function PPM High Value"
line.long 0x18 "NUDGE_REG,Time Stamp ESTF Generate Function Nudge Value"
hexmask.long.byte 0x18 0.--7. 1. "NUDGE,Time Stamp ESTF Generate Function Nudge Value"
rgroup.long 0x3E000++0x17
line.long 0x00 "MOD_VER,The Module and Version Register identifies the module identifier and revision of the ALE_2g32 module"
hexmask.long.word 0x00 16.--31. 1. "MODULE_ID,ALE_2g32 module ID"
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bitfld.long 0x00 11.--15. "RTL_VERSION,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR_REVISION,Major Revision" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM_REVISION,Custom Revision" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR_REVISION,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "ALE_STATUS,The ALE status provides information on the ALE configuration and state"
bitfld.long 0x04 31. "UREGANDREGMSK12,When set the unregistered multicast field is a mask versus an index on 12 bit boundary in the ALE table" "0,1"
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bitfld.long 0x04 30. "UREGANDREGMSK08,When set the unregistered multicast field is a mask versus an index on 8 bit boundary in the ALE table" "0,1"
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hexmask.long.byte 0x04 8.--15. 1. "POLCNTDIV8,This is the number of policer engines the ALE implements divided by 8"
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bitfld.long 0x04 7. "RAMDEPTH128,The number of ALE entries per slice of the table when this is set it indicates the depth is 128 if both ramdepth128 and ramdepth32 are zero the depth is 64" "0,1"
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bitfld.long 0x04 6. "RAMDEPTH32,The number of ALE entries per slice of the table when this is set it indicates the depth is 32 if both ramdepth128 and ramdepth32 are zero the depth is 64" "0,1"
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bitfld.long 0x04 0.--4. "KLUENTRIES,This is the number of table entries total divided by 1024" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "ALE_CONTROL,The ALE Control Register is used to set the ALE modes used for all ports"
bitfld.long 0x08 31. "ENABLE_ALE,Enable ALE " "Drop all packets,Enable ALE packet processing"
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bitfld.long 0x08 30. "CLEAR_TABLE,Clear ALE address table - Setting this bit causes the ALE hardware to write all table bit values to zero" "0,1"
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bitfld.long 0x08 29. "AGE_OUT_NOW,Age Out Address Table Now - Setting this bit causes the ALE hardware to remove (free up) any ageable table entry that does not have a set touch bit" "0,1"
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bitfld.long 0x08 24. "MIRROR_DP,Mirror Destination Port - This field defines the port to which destination traffic destined will be duplicated" "0,1"
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bitfld.long 0x08 21.--23. "UPD_BW_CTRL,The ~iupd_bw_ctrl field allows for up to 8 times the rate in which adds updates touches writes and aging updates can occur" "0,1,2,3,4,5,6,7"
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bitfld.long 0x08 16. "MIRROR_TOP,Mirror To Port - This field defines the destination port for the mirror traffic" "0,1"
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bitfld.long 0x08 15. "UPD_STATIC,Update Static Entries - A static Entry is an entry that is not agable" "0,1"
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bitfld.long 0x08 13. "UVLAN_NO_LEARN,Unknown VLAN No Learn - This field when set will prevent source addresses of unknown VLAN IDs from being automatically added into the look up table if learning is enabled" "0,1"
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bitfld.long 0x08 12. "MIRROR_MEN,Mirror Match Entry Enable - This field enables the match mirror option" "0,1"
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bitfld.long 0x08 11. "MIRROR_DEN,Mirror Destination Port Enable - This field enables the destination port mirror option" "0,1"
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bitfld.long 0x08 10. "MIRROR_SEN,Mirror Source Port Enable - This field enables the source port mirror option" "0,1"
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bitfld.long 0x08 8. "EN_HOST_UNI_FLOOD,Unknown unicast packets flood to host " "unknown unicast packets are not sent to the host,unknown unicast packets flood to host port as.."
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bitfld.long 0x08 7. "LEARN_NO_VLANID,Learn No VID - " "VID is learned with the source address,VID is not learned with the source address.."
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bitfld.long 0x08 6. "ENABLE_VID0_MODE,Enable VLAN ID = 0 Mode " "Process the priority tagged packet with VID =..,Process the priority tagged packet with VID = 0"
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bitfld.long 0x08 5. "ENABLE_OUI_DENY,Enable OUI Deny Mode - When set any packet with a non-matching OUI source address will be dropped to the host unless the packet destination address matches a supervisory destination address table entry" "0,1"
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bitfld.long 0x08 4. "ENABLE_BYPASS,ALE Bypass - When set packets received on non-host ports are sent to the host" "no bypass,bypass the ALE"
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bitfld.long 0x08 3. "BCAST_MCAST_CTL,Rate Limit Transmit mode " "Broadcast and multicast rate limit counters are..,Broadcast and multicast rate limit counters are.."
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bitfld.long 0x08 2. "ALE_VLAN_AWARE,ALE VLAN Aware - Determines how traffic is forwarded using VLAN rules. " "Simple switch rules packets forwarded to all..,VLAN Aware rules packets forwarded based on VLAN.."
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bitfld.long 0x08 1. "ENABLE_AUTH_MODE,Enable MAC Authorization Mode - Mac authorization mode requires that all table entries be made by the host software" "The ALE is not in MAC authorization mode,The ALE is in MAC authorization mode"
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bitfld.long 0x08 0. "ENABLE_RATE_LIMIT,Enable Broadcast and Multicast Rate Limit " "Broadcast/Multicast rates not limited,Broadcast/Multicast packet reception limited to.."
line.long 0x0C "ALE_CTRL2,The ALE Control 2 Register is used to set the extended features used for all ports"
bitfld.long 0x0C 31. "TRK_EN_DST,Trunk Enable Destination Address - This field enables the destination MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 30. "TRK_EN_SRC,Trunk Enable Source Address - This field enables the source MAC address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 29. "TRK_EN_PRI,Trunk Enable Priority - This field enables the VLAN Priority bits to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 27. "TRK_EN_IVLAN,Trunk Enable Inner VLAN - This field enables the inner VLAN ID value (C-VLANID) to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination" "0,1"
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bitfld.long 0x0C 25. "TRK_EN_SIP,Trunk Enable Source IP Address - This field enables the source IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged VLAN tagged.." "0,1"
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bitfld.long 0x0C 24. "TRK_EN_DIP,Trunk Enable Destination IP Address - This field enables the destination IP address to be used with the hash function G(X) = 1 + X + X^3 and affect the trunk port transmit link determination. This feature supports No tag Priority tagged.." "0,1"
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bitfld.long 0x0C 23. "DROP_BADLEN,Drop Bad Length will drop any packet that the 802.3 length field is larger than the packet" "0,1"
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bitfld.long 0x0C 22. "NODROP_SRCMCST,No Drop Source Multicast will disable the dropping of any source address with the multicast bit set" "0,1"
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bitfld.long 0x0C 21. "DEFNOFRAG,Default No Frag field will cause an IPv4 fragmented packet to be dropped if a VLAN entry is not found" "0,1"
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bitfld.long 0x0C 20. "DEFLMTNXTHDR,Default limit next header field will cause an IPv4 protocol or IPv6 next header packet to be dropped if a VLAN entry is not found and the protocol or next header does not match the ~iALE_NXT_HDR register values" "0,1"
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bitfld.long 0x0C 16.--18. "TRK_BASE,Trunk Base - This field is the hash formula starting value" "?,~i00000000,~i01010101,~i02102102,~i03210321,?..."
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bitfld.long 0x0C 0.--4. "MIRROR_MIDX,Mirror Index - This field is the ALE lookup table entry index that when a match occurs will cause this traffic to be mirrored to the ~imirror_top port" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "ALE_PRESCALE,The ALE Prescale Register is used to set the Broadcast and Multicast rate limiting prescaler value"
hexmask.long.tbyte 0x10 0.--19. 1. "ALE_PRESCALE,ALE Prescale - The input clock is divided by this value for use in the multicast/broadcast rate limiters"
line.long 0x14 "ALE_AGING_CTRL,The ALE Aging Control sets the aging interval which will cause periodic aging to occur"
bitfld.long 0x14 31. "PRESCALE_2_DISABLE,ALE Prescaler 2 Disable - When set will divide the aging interval by 1000" "0,1"
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bitfld.long 0x14 30. "PRESCALE_1_DISABLE,ALE Prescaler 1 Disable - When set will divide the aging interval by 1000" "0,1"
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hexmask.long.tbyte 0x14 0.--23. 1. "ALE_AGING_TIMER,ALE Aging Timer - This field specifies the number of clock cycles times 1 000 000 between aging operations"
group.long 0x3E01C++0x07
line.long 0x00 "ALE_NXT_HDR,The ALE Next Header is used to limit the IPv6 Next header or IPv4 Protocol values found in the IP header"
hexmask.long.byte 0x00 24.--31. 1. "IP_NXT_HDR3,The ~iip_nxt_hdr3 is the forth protocol or next header compared when enabled"
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hexmask.long.byte 0x00 16.--23. 1. "IP_NXT_HDR2,The ~iip_nxt_hdr2 is the third protocol or next header compared when enabled"
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hexmask.long.byte 0x00 8.--15. 1. "IP_NXT_HDR1,The ~iip_nxt_hdr1 is the second protocol or next header compared when enabled"
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hexmask.long.byte 0x00 0.--7. 1. "IP_NXT_HDR0,The ~iip_nxt_hdr0 is the first protocol or next header compared when enabled"
line.long 0x04 "ALE_TBLCTL,The ALE table control register is used to read or write that ALE table entries"
bitfld.long 0x04 31. "TABLEWR,Table Write - This bit is used to write the table words to the lookup table. " "Table Read Operation is performed,Table write operation is performed"
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bitfld.long 0x04 0.--4. "TABLEIDX,The table index is used to determine which lookup table entry is read or written" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3E034++0x0B
line.long 0x00 "ALE_TBLW2,The ALE Table Word 2 is the most significant word of an ALE table entry"
hexmask.long.byte 0x00 0.--6. 1. "TABLEWRD2,Table Entry bits [71:64]"
line.long 0x04 "ALE_TBLW1,The ALE Table Word 1 is the middle word of an ALE table entry"
line.long 0x08 "ALE_TBLW0,The ALE Table Word 0 is the least significant word of an ALE table entry"
repeat 2. (list 0x0 0x1 )(list 0x0 0x4 )
group.long ($2+0x3E040)++0x03
line.long 0x00 "I0_ALE_PORTCTL0_$1,The ALE Port Control Register sets the port specific modes of operation"
hexmask.long.byte 0x00 24.--31. 1. "I0_REG_P0_BCAST_LIMIT,Broadcast Packet Rate Limit - Each prescale pulse loads this field into the port broadcast rate limit counter"
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hexmask.long.byte 0x00 16.--23. 1. "I0_REG_P0_MCAST_LIMIT,Multicast Packet Rate Limit - Each prescale pulse loads this field into the port multicast rate limit counter"
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bitfld.long 0x00 15. "I0_REG_P0_DROP_DOUBLE_VLAN,Drop Double VLAN - When set cause any received packet with double VLANs to be dropped" "0,1"
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bitfld.long 0x00 14. "I0_REG_P0_DROP_DUAL_VLAN,Drop Dual VLAN - When set will cause any received packet with dual VLAN stag followed by ctag to be dropped" "0,1"
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bitfld.long 0x00 13. "I0_REG_P0_MACONLY_CAF,Mac Only Copy All Frames - When set a Mac Only port will transfer all received good frames to the host" "0,1"
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bitfld.long 0x00 12. "I0_REG_P0_DIS_PAUTHMOD,Disable Port" "0,1"
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bitfld.long 0x00 11. "I0_REG_P0_MACONLY,MAC Only - When set enables this port be treated like a MAC port for the host" "0,1"
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bitfld.long 0x00 10. "I0_REG_P0_TRUNKEN,Trunk Enable - This field is used to enable a port into a trunk" "0,1"
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bitfld.long 0x00 8.--9. "I0_REG_P0_TRUNKNUM,Trunk Number - This field is used as the trunk number when the ~ip0_trunken is also set" "0,1,2,3"
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bitfld.long 0x00 7. "I0_REG_P0_MIRROR_SP,Mirror Source Port - This field enables the source port mirror option" "0,1"
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bitfld.long 0x00 5. "I0_REG_P0_NO_SA_UPDATE,No Source Address Update - When set will not update the source addresses for this port" "0,1"
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bitfld.long 0x00 4. "I0_REG_P0_NO_LEARN,No Learn - When set will not learn the source addresses for this port" "0,1"
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bitfld.long 0x00 3. "I0_REG_P0_VID_INGRESS_CHECK,VLAN Ingress" "0,1"
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bitfld.long 0x00 2. "I0_REG_P0_DROP_UN_TAGGED,If Drop Untagged - When set will drop packets without a VLAN tag" "0,1"
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bitfld.long 0x00 0.--1. "I0_REG_P0_PORTSTATE,Port State - Defins the current port state used for lookup operations. " "Disabled,Blocked,Learning,Forwarding"
repeat.end
group.long 0x3E090++0x0F
line.long 0x00 "ALE_UVLAN_MEMBER,The ALE Unknown VLAN Member Mask Register is used to specify the member list for unknown VLAN ID"
bitfld.long 0x00 0.--1. "UVLAN_MEMBER_LIST,Unknown VLAN Member List - Each bit represents the port member status for unknown VLANs" "0,1,2,3"
line.long 0x04 "ALE_UVLAN_URCAST,The ALE Unknown VLAN Unregistered Multicast Flood Mask Register is used to specify which egress ports unregistered multicast addresses egress for the unregistered VLAN ID"
bitfld.long 0x04 0.--1. "UVLAN_UNREG_MCAST,Unknown VLAN Unregister Multicast Flood Mask - Each bit represents the port to which unregistered multicast are sent for unregistered VLANs" "0,1,2,3"
line.long 0x08 "ALE_UVLAN_RMCAST,The ALE Unknown VLAN Registered Multicast Flood Mask Register is used to specify which egress ports registered multicast addresses egress for the unregistered VLAN ID"
bitfld.long 0x08 0.--1. "UVLAN_REG_MCAST_FLOOD_MASK,Unknown VLAN Register Multicast Flood Mask - Each bit represents the port to which registered multicast are sent for unregistered VLANs" "0,1,2,3"
line.long 0x0C "ALE_UVLAN_UNTAG,The ALE Unknown VLAN force Untagged Egress Mask Register is used to specify which egress ports the VLAN ID will be removed"
bitfld.long 0x0C 0.--1. "UVLAN_FORCE_UNTAGGED_EGRESS,Unknown VLAN Force Untagged Egress Mask - Each bit represents the port where the VLAN will be removed for unregistered VLANs" "0,1,2,3"
group.long 0x3E0B8++0x0B
line.long 0x00 "ALE_STAT_DIAG,The ALE Statistic Output Diagnostic Register allows the output statistics to diagnose the SW counters"
bitfld.long 0x00 15. "PBCAST_DIAG,When set and the ~iport_diag is set to zero will allow all ports to see the same stat diagnostic increment" "0,1"
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bitfld.long 0x00 8. "PORT_DIAG,The port selected that a received packet will cause the selected error to increment" "0,1"
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bitfld.long 0x00 0.--3. "STAT_DIAG,When non-zero will cause the selected statistic to increment on the next frame received" "Disabled,Destination Equal Source Drop Stat will count,VLAN Ingress Check Drop Stat will count,Source Multicast Drop Stat will count,Dual VLAN Drop Stat will count,Ether Type length error Drop Stat will count,Next Hop Limit Drop Stat will count,IPv4 Fragment Drop Stat will count,Classifier Hit Stat will count,Classifier Red Drop Stat will count,Classifier Yellow Drop Stat will count,ALE Overflow Drop Stat will count,Rate Limit Drop Stat will count,Blocked Address Drop Stat will count,Secure Address Drop Stat will count,Authorization Drop Stat will count"
line.long 0x04 "ALE_OAM_LB_CTRL,The ALE OAM Control allows ports to be put into OAM Loopback. only non-supervisor packet are looped back to the source port"
bitfld.long 0x04 0.--1. "OAM_LB_CTRL,The ~ioam_lb_ctrl allows any port to be put into OAM loopback that is any packet received will be returned to the same port with an egressop of 0xFF which swaps the source and destination address" "0,1,2,3"
line.long 0x08 "ALE_MSK_MUX0,VLAN Mask Mux x - The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for vlan registered and unregister mask respectively"
bitfld.long 0x08 0.--1. "VLAN_MASK_MUX_0,VLAN Mask Mux x - When selected by the VLAN lookup table entry FwdUnRegIdx or FwdAllRegIdx is used as the FwdUnRegMask or FwdUnRegMask values anded with the member list to determine the forwarding of packets" "0,1,2,3"
repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x4 0x8 )
group.long ($2+0x3E0C4)++0x03
line.long 0x00 "I1_ALE_MSK_MUX1_$1,VLAN Mask Mux x - The ALE Mask Mux registers are used along with the VLAN registered/unregistered index selectors from the Lookup Table to determine the value for vlan registered and unregister mask respectively"
bitfld.long 0x00 0.--1. "I1_REG_VLAN_MASK_MUX_1,VLAN Mask Mux x - When selected by the VLAN lookup table entry FwdUnRegIdx or FwdAllRegIdx is used as the FwdUnRegMask or FwdUnRegMask values anded with the member list to determine the forwarding of packets" "0,1,2,3"
repeat.end
group.long 0x3E0FC++0x17
line.long 0x00 "EGRESSOP,The Egress Operation register allows enabled classifiers with IPSA or IPDA match to use the CPSW Egress Packet Operations Inter VLAN Routing sub functions"
abitfld.long 0x00 24.--31. "EGRESS_OP,The Egress Operation defines the operation performed by the CPSW Egress Packet Operations " "0x00=NOP,0xFF=Swap SA and DA of packet this is intended.."
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bitfld.long 0x00 21.--23. "EGRESS_TRK,The Egress Trunk Index is the calculated trunk index from the SA DA or VLAN if modified to that InterVLAN routing will work on trunks as well" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 20. "TTL_CHECK,The TTL Check will cause any packet that fails TTL checks to not be routed to the Inter VLAN Routing sub functions" "0,1"
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bitfld.long 0x00 0.--1. "DEST_PORTS,The Destination Ports is a list of the ports the classified packet will be set to" "0,1,2,3"
line.long 0x04 "POLICECFG0,The Policing Config 0 holds the port. frame priority and ONU address index as well as match enables for port. frame priority and ONU address matching"
bitfld.long 0x04 31. "PORT_MEN,Port Match Enable - Enabled port match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 30. "TRUNKID,Trunk ID - When set indicates the port number is a trunk group" "0,1"
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bitfld.long 0x04 25. "PORT_NUM,Port Number - Specifies the port address to match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 19. "PRI_MEN,Priority Match Enable - Enables frame priority match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 16.--18. "PRI_VAL,Priority Value - Specifies the frame priority to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 15. "ONU_MEN,OUI Match Enable - Enables frame ONU address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x04 0.--4. "ONU_INDEX,OUI Table Entry Index - Specifies the ALE ONU address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "POLICECFG1,The Policing Config 1 holds the match enable/match index for the L2 Destination and L2 source addresses"
bitfld.long 0x08 31. "DST_MEN,Destination Address Match Enable - Enables frame L2 destination address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x08 16.--20. "DST_INDEX,Destination Address Table Entry Index - Specifies the ALE L2 destination address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 15. "SRC_MEN,Source Address Match Enable - Enables frame L2 source address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x08 0.--4. "SRC_INDEX,Source Address Table Entry Index - Specifies the ALE L2 source address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "POLICECFG2,The Policing Config 2 holds the match enable/match index for the Outer VLAN and Inner VLAN addresses"
bitfld.long 0x0C 31. "OVLAN_MEN,Outer VLAN Match Enable - Enables frame Outer VLAN address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x0C 16.--20. "OVLAN_INDEX,Outer VLAN Table Entry Index - Specifies the ALE Outer VLAN address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 15. "IVLAN_MEN,Inner VLAN Match Enable - Enables frame Inner VLAN address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x0C 0.--4. "IVLAN_INDEX,Inner VLAN Table Entry Index - Specifies the ALE Inner VLAN address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x10 "POLICECFG3,The Policing Config 3 holds the match enable/match index for the Ether Type and IP Source address"
bitfld.long 0x10 31. "ETHERTYPE_MEN,EtherType Match Enable - Enables frame Ether Type match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x10 16.--20. "ETHERTYPE_INDEX,EtherType Table Entry Index - Specifies the ALE Ether Type lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 15. "IPSRC_MEN,IP Source Address Match Enable - Enables frame IP Source address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x10 0.--4. "IPSRC_INDEX,IP Source Address Table Entry Index - Specifies the ALE IP Source address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x14 "POLICECFG4,The Policing Config 4 holds the match enable/match index for the IP Destination address"
bitfld.long 0x14 31. "IPDST_MEN,IP Destination Address Match Enable - Enables frame IP Destination address match for the selected policing/classifier entry" "0,1"
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bitfld.long 0x14 16.--20. "IPDST_INDEX,IP Destination Address Table Entry Index - Specifies the ALE IP Destination address lookup table index to match for the selected policing/classifier entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x3E118++0x17
line.long 0x00 "POLICECFG6,The PIR counter is a 37 bit internal counter where ~ipir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED at LUT time"
line.long 0x04 "POLICECFG7,The CIR counter is a 37 bit internal counter where ~icir_idle_inc_val is added every clock and the frame size << 18 is subtracted at EOF if not RED or YELLOW at LUT time"
line.long 0x08 "POLICETBLCTL,The Policing Table Control is used to read or write the selected policing/classifier entry"
bitfld.long 0x08 31. "WRITE_ENABLE,Write Enable - Setting this bit will write the POLICECFG0-7 to the ~ipol_tbl_idx selected policing/classifier entry" "0,1"
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bitfld.long 0x08 0.--1. "POL_TBL_IDX,Policer Entry Index - This field specifies the policing/classifier entry to be read or written" "0,1,2,3"
line.long 0x0C "POLICECONTROL,The Control Enables color marking as well as internal ALE packet dropping rules"
bitfld.long 0x0C 31. "POLICING_EN,Policing Enable - Enables the policing to color the packets this also enables red or yellow drop capabilities" "0,1"
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bitfld.long 0x0C 29. "RED_DROP_EN,RED Drop Enable - Enables the ALE to drop the red colored packets" "0,1"
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bitfld.long 0x0C 28. "YELLOW_DROP_EN,WELLOW Drop Enable - Enables the ALE to drop yellow packets based on the ~iyellowthresh value" "0,1"
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bitfld.long 0x0C 24.--26. "YELLOWTHRESH,Yellow Threshold - When set enables a portion of the yellow packets to be dropped based on the ~iyellow_drop_en enable. 0-100% " "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 22.--23. "POLMCHMODE,Policing Match Mode - This field determines what happens to packets that fail to hit any policing/classifier entry. " "No Hit packets are marked GREEN,No Hit packets are marked YELLOW,No Hit packets are marked RED,No Hit packets are marked based on.."
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bitfld.long 0x0C 21. "PRIORITY_THREAD_EN,Priority Thread Enable - This field determines if priority is OR'd to the default thread when no classifiers hit and the default thread is enabled" "0,1"
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bitfld.long 0x0C 20. "MAC_ONLY_DEF_DIS,MAC Only Default Disable - This field when set disables the default thread on MAC Only Ports" "0,1"
line.long 0x10 "POLICETESTCTL,The Policing Test Control enables the ability to determine which policing entry has been hit and whether they reported a red or yellow rate condition"
bitfld.long 0x10 31. "POL_CLRALL_HIT,Policer Clear - This bit clears all the policing/classifier hit bits" "0,1"
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bitfld.long 0x10 30. "POL_CLRALL_REDHIT,Policer Clear RED - This bit clears all the policing/classifier RED hit bits" "0,1"
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bitfld.long 0x10 29. "POL_CLRALL_YELLOWHIT,Policer Clear YELLOW - This bit clears all the policing/classifier YELLOW hit bits" "0,1"
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bitfld.long 0x10 28. "POL_CLRSEL_ALL,Police Clear Selected - This bit clears the selected policing/classifier hit redhit and yellowhit bits" "0,1"
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bitfld.long 0x10 0.--1. "POL_TEST_IDX,Policer Test Index - This field selects which policing/classifier hit bits will be read or written" "0,1,2,3"
line.long 0x14 "POLICEHSTAT,The policing hit status is a read only register that reads the hit bits of the selected policing/classifier"
bitfld.long 0x14 31. "POL_HIT,Policer Hit - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit by a packet seen on any port that matches the policing/classifier entry match" "0,1"
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bitfld.long 0x14 30. "POL_REDHIT,Policer Hit RED - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit during a RED condition by a packet seen on any port that matches the policing/classifier entry match" "0,1"
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bitfld.long 0x14 29. "POL_YELLOWHIT,Policer Hit YELLOW - This indicates that the selected policing/classifier via the ~ipol_test_idx field has been hit during a YELLOW condition by a packet seen on any port that matches the policing/classifier entry match" "0,1"
group.long 0x3E134++0x0B
line.long 0x00 "THREADMAPDEF,The THREAD Mapping Default Value register is used to set the default thread ID when no classifier is matched."
bitfld.long 0x00 15. "DEFTHREAD_EN,Default Tread Enable - When set the switch will use the ~idefthreadval for the host interface thread ID if no classifier is matched" "0,1"
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bitfld.long 0x00 0.--5. "DEFTHREADVAL,Default Thread Value - This field specifies the default thread ID value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "THREADMAPCTL,The THREAD Mapping Control register allows the highest matched classifier to return a particular thread ID for traffic sent to the host"
bitfld.long 0x04 0.--1. "CLASSINDEX,Classifier Index - This is the classifier index entry that the thread enable and thread value will be read or written by the ~bTHREADMAPVAL register" "0,1,2,3"
line.long 0x08 "THREADMAPVAL,The THREAD Mapping Value register is used to set the thread ID for a particular classifier entry"
bitfld.long 0x08 15. "THREAD_EN,Thread Enable - When set the switch will use the ~ithreadval for the selected classifier match" "0,1"
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bitfld.long 0x08 0.--5. "THREADVAL,Thread Value - This field is the thread ID value that is used to map a classifier hit to thread ID for host traffic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.long 0x3F000++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
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bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
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bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
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bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x3F008++0x27
line.long 0x00 "vector,ECC Vector Register"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
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hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
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bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
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hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "reserved_svbus_0,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x0C "reserved_svbus_1,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x10 "reserved_svbus_2,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x14 "reserved_svbus_3,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x18 "reserved_svbus_4,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x1C "reserved_svbus_5,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x20 "reserved_svbus_6,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
line.long 0x24 "reserved_svbus_7,Reference other documents that contain the ECC RAM wrapper and EDC controller serial vbus register sets"
group.long 0x3F03C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
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bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
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bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
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bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
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bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
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bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
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bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
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bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
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bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
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bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
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bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
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bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
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bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
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bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
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bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
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bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
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bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
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bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
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bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
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bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x3F080++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
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bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
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bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
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bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
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bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
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bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
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bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
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bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
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bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
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bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
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bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
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bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
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bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
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bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
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bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
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bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
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bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
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bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
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bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
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bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x3F0C0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
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bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
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bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
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bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
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bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
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bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
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bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
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bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
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bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
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bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
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bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
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bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
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bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
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bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
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bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
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bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
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bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
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bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
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bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
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bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x3F13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 19. "RAMECC19_PEND,Interrupt Pending Status for ramecc19_pend" "0,1"
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bitfld.long 0x04 18. "RAMECC18_PEND,Interrupt Pending Status for ramecc18_pend" "0,1"
newline
bitfld.long 0x04 17. "RAMECC17_PEND,Interrupt Pending Status for ramecc17_pend" "0,1"
newline
bitfld.long 0x04 16. "RAMECC16_PEND,Interrupt Pending Status for ramecc16_pend" "0,1"
newline
bitfld.long 0x04 15. "RAMECC15_PEND,Interrupt Pending Status for ramecc15_pend" "0,1"
newline
bitfld.long 0x04 14. "RAMECC14_PEND,Interrupt Pending Status for ramecc14_pend" "0,1"
newline
bitfld.long 0x04 13. "RAMECC13_PEND,Interrupt Pending Status for ramecc13_pend" "0,1"
newline
bitfld.long 0x04 12. "RAMECC12_PEND,Interrupt Pending Status for ramecc12_pend" "0,1"
newline
bitfld.long 0x04 11. "RAMECC11_PEND,Interrupt Pending Status for ramecc11_pend" "0,1"
newline
bitfld.long 0x04 10. "RAMECC10_PEND,Interrupt Pending Status for ramecc10_pend" "0,1"
newline
bitfld.long 0x04 9. "RAMECC9_PEND,Interrupt Pending Status for ramecc9_pend" "0,1"
newline
bitfld.long 0x04 8. "RAMECC8_PEND,Interrupt Pending Status for ramecc8_pend" "0,1"
newline
bitfld.long 0x04 7. "RAMECC7_PEND,Interrupt Pending Status for ramecc7_pend" "0,1"
newline
bitfld.long 0x04 6. "RAMECC6_PEND,Interrupt Pending Status for ramecc6_pend" "0,1"
newline
bitfld.long 0x04 5. "RAMECC5_PEND,Interrupt Pending Status for ramecc5_pend" "0,1"
newline
bitfld.long 0x04 4. "RAMECC4_PEND,Interrupt Pending Status for ramecc4_pend" "0,1"
newline
bitfld.long 0x04 3. "RAMECC3_PEND,Interrupt Pending Status for ramecc3_pend" "0,1"
newline
bitfld.long 0x04 2. "RAMECC2_PEND,Interrupt Pending Status for ramecc2_pend" "0,1"
newline
bitfld.long 0x04 1. "RAMECC1_PEND,Interrupt Pending Status for ramecc1_pend" "0,1"
newline
bitfld.long 0x04 0. "RAMECC0_PEND,Interrupt Pending Status for ramecc0_pend" "0,1"
group.long 0x3F180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_SET,Interrupt Enable Set Register for ramecc19_pend" "0,1"
newline
bitfld.long 0x00 18. "RAMECC18_ENABLE_SET,Interrupt Enable Set Register for ramecc18_pend" "0,1"
newline
bitfld.long 0x00 17. "RAMECC17_ENABLE_SET,Interrupt Enable Set Register for ramecc17_pend" "0,1"
newline
bitfld.long 0x00 16. "RAMECC16_ENABLE_SET,Interrupt Enable Set Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_SET,Interrupt Enable Set Register for ramecc15_pend" "0,1"
newline
bitfld.long 0x00 14. "RAMECC14_ENABLE_SET,Interrupt Enable Set Register for ramecc14_pend" "0,1"
newline
bitfld.long 0x00 13. "RAMECC13_ENABLE_SET,Interrupt Enable Set Register for ramecc13_pend" "0,1"
newline
bitfld.long 0x00 12. "RAMECC12_ENABLE_SET,Interrupt Enable Set Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_SET,Interrupt Enable Set Register for ramecc11_pend" "0,1"
newline
bitfld.long 0x00 10. "RAMECC10_ENABLE_SET,Interrupt Enable Set Register for ramecc10_pend" "0,1"
newline
bitfld.long 0x00 9. "RAMECC9_ENABLE_SET,Interrupt Enable Set Register for ramecc9_pend" "0,1"
newline
bitfld.long 0x00 8. "RAMECC8_ENABLE_SET,Interrupt Enable Set Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_SET,Interrupt Enable Set Register for ramecc7_pend" "0,1"
newline
bitfld.long 0x00 6. "RAMECC6_ENABLE_SET,Interrupt Enable Set Register for ramecc6_pend" "0,1"
newline
bitfld.long 0x00 5. "RAMECC5_ENABLE_SET,Interrupt Enable Set Register for ramecc5_pend" "0,1"
newline
bitfld.long 0x00 4. "RAMECC4_ENABLE_SET,Interrupt Enable Set Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_SET,Interrupt Enable Set Register for ramecc3_pend" "0,1"
newline
bitfld.long 0x00 2. "RAMECC2_ENABLE_SET,Interrupt Enable Set Register for ramecc2_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC1_ENABLE_SET,Interrupt Enable Set Register for ramecc1_pend" "0,1"
newline
bitfld.long 0x00 0. "RAMECC0_ENABLE_SET,Interrupt Enable Set Register for ramecc0_pend" "0,1"
group.long 0x3F1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 19. "RAMECC19_ENABLE_CLR,Interrupt Enable Clear Register for ramecc19_pend" "0,1"
newline
bitfld.long 0x00 18. "RAMECC18_ENABLE_CLR,Interrupt Enable Clear Register for ramecc18_pend" "0,1"
newline
bitfld.long 0x00 17. "RAMECC17_ENABLE_CLR,Interrupt Enable Clear Register for ramecc17_pend" "0,1"
newline
bitfld.long 0x00 16. "RAMECC16_ENABLE_CLR,Interrupt Enable Clear Register for ramecc16_pend" "0,1"
newline
bitfld.long 0x00 15. "RAMECC15_ENABLE_CLR,Interrupt Enable Clear Register for ramecc15_pend" "0,1"
newline
bitfld.long 0x00 14. "RAMECC14_ENABLE_CLR,Interrupt Enable Clear Register for ramecc14_pend" "0,1"
newline
bitfld.long 0x00 13. "RAMECC13_ENABLE_CLR,Interrupt Enable Clear Register for ramecc13_pend" "0,1"
newline
bitfld.long 0x00 12. "RAMECC12_ENABLE_CLR,Interrupt Enable Clear Register for ramecc12_pend" "0,1"
newline
bitfld.long 0x00 11. "RAMECC11_ENABLE_CLR,Interrupt Enable Clear Register for ramecc11_pend" "0,1"
newline
bitfld.long 0x00 10. "RAMECC10_ENABLE_CLR,Interrupt Enable Clear Register for ramecc10_pend" "0,1"
newline
bitfld.long 0x00 9. "RAMECC9_ENABLE_CLR,Interrupt Enable Clear Register for ramecc9_pend" "0,1"
newline
bitfld.long 0x00 8. "RAMECC8_ENABLE_CLR,Interrupt Enable Clear Register for ramecc8_pend" "0,1"
newline
bitfld.long 0x00 7. "RAMECC7_ENABLE_CLR,Interrupt Enable Clear Register for ramecc7_pend" "0,1"
newline
bitfld.long 0x00 6. "RAMECC6_ENABLE_CLR,Interrupt Enable Clear Register for ramecc6_pend" "0,1"
newline
bitfld.long 0x00 5. "RAMECC5_ENABLE_CLR,Interrupt Enable Clear Register for ramecc5_pend" "0,1"
newline
bitfld.long 0x00 4. "RAMECC4_ENABLE_CLR,Interrupt Enable Clear Register for ramecc4_pend" "0,1"
newline
bitfld.long 0x00 3. "RAMECC3_ENABLE_CLR,Interrupt Enable Clear Register for ramecc3_pend" "0,1"
newline
bitfld.long 0x00 2. "RAMECC2_ENABLE_CLR,Interrupt Enable Clear Register for ramecc2_pend" "0,1"
newline
bitfld.long 0x00 1. "RAMECC1_ENABLE_CLR,Interrupt Enable Clear Register for ramecc1_pend" "0,1"
newline
bitfld.long 0x00 0. "RAMECC0_ENABLE_CLR,Interrupt Enable Clear Register for ramecc0_pend" "0,1"
group.long 0x3F200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
newline
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
newline
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
newline
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_CTRL (MSS CTRL Module Registers)"
base ad:0x2120000
rgroup.long 0x00++0x517
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MSS_SW_INT,"
bitfld.long 0x04 0.--4. "pulse,Write_pulse bit field: writing 1'b1 to each bit will trigger MSS_SW_INT<0-4> respectively to CR5A/B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "MSS_CAPEVNT_SEL,"
hexmask.long.byte 0x08 8.--15. 1. "src1,Writing a value 'N' will select Nth interrupt from CR5A/B interrupt mapping to trigger CAP-EVENT1 to all MSS_RTIs"
newline
hexmask.long.byte 0x08 0.--7. 1. "src0,Writing a value 'N' will select Nth interrupt from CR5A/B interrupt mapping to trigger CAP-EVENT0 to all MSS_RTIs"
line.long 0x0C "MSS_DMA_REQ_SEL,"
line.long 0x10 "MSS_DMA1_REQ_SEL,"
line.long 0x14 "MSS_IRQ_REQ_SEL,"
line.long 0x18 "MSS_SPI_TRIG_SRC,"
hexmask.long.word 0x18 16.--26. 1. "trig_spib,Writing 1'b1 to each bit will trigger MSS_SPIB Trigger<0-10> respectively"
newline
bitfld.long 0x18 0.--1. "trig_spia,Writing 1'b1 to each bit will trigger MSS_SPIA Trigger<0-1> respectively" "0,1,2,3"
line.long 0x1C "MSS_ATCM_MEM_INIT,"
bitfld.long 0x1C 0. "mem_init,Write_pulse bit field: Writing 1'b1 will start initializing the ATCM banks of CR5A/B" "0,1"
line.long 0x20 "MSS_ATCM_MEM_INIT_DONE,"
bitfld.long 0x20 0. "mem_init_done,This field will be high once initialization of ATCM banks is finished" "0,1"
line.long 0x24 "MSS_ATCM_MEM_INIT_STATUS,"
bitfld.long 0x24 0. "mem_status," "0,1"
line.long 0x28 "MSS_BTCM_MEM_INIT,"
bitfld.long 0x28 0. "mem_init,Write_pulse bit field: Writing 1'b1 will start initializing the B0/1TCM banks of CR5A/B" "0,1"
line.long 0x2C "MSS_BTCM_MEM_INIT_DONE,"
bitfld.long 0x2C 0. "mem_init_done,This field will be high once initialization of B0/1TCM banks is finished" "0,1"
line.long 0x30 "MSS_BTCM_MEM_INIT_STATUS,"
bitfld.long 0x30 0. "mem_status," "0,1"
line.long 0x34 "MSS_L2_MEM_INIT,"
bitfld.long 0x34 1. "partition1,Write_pulse bit field: Writing 1'b1 will start initializing the L2 Bank1" "0,1"
newline
bitfld.long 0x34 0. "partition0,Write_pulse bit field: Writing 1'b1 will start initializing the L2 Bank0" "0,1"
line.long 0x38 "MSS_L2_MEM_INIT_DONE,"
bitfld.long 0x38 1. "partition1,This field will be high once intialization of L2 bank1 is finished" "0,1"
newline
bitfld.long 0x38 0. "partition0,This field will be high once intialization of L2 bank0 is finished" "0,1"
line.long 0x3C "MSS_L2_MEM_INIT_STATUS,"
bitfld.long 0x3C 1. "partition1," "0,1"
newline
bitfld.long 0x3C 0. "partition0," "0,1"
line.long 0x40 "MSS_MAILBOX_MEM_INIT,"
bitfld.long 0x40 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_MBOX" "0,1"
line.long 0x44 "MSS_MAIlBOX_MEM_INIT_DONE,"
bitfld.long 0x44 0. "mem0_done,This field will be high once intialization of MSS_MBOX is finished" "0,1"
line.long 0x48 "MSS_MAILBOX_MEM_INIT_STATUS,"
bitfld.long 0x48 0. "mem0_status," "0,1"
line.long 0x4C "MSS_RETRAM_MEM_INIT,"
bitfld.long 0x4C 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_RETRAM" "0,1"
line.long 0x50 "MSS_RETRAM_MEM_INIT_DONE,"
bitfld.long 0x50 0. "mem0_done,This field will be high once intialization of MSS_RETRAM is finished" "0,1"
line.long 0x54 "MSS_RETRAM_MEM_INIT_STATUS,"
bitfld.long 0x54 0. "mem0_status," "0,1"
line.long 0x58 "MSS_SPIA_MEM_INIT,"
bitfld.long 0x58 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_SPIA" "0,1"
line.long 0x5C "MSS_SPIA_MEM_INIT_DONE,"
bitfld.long 0x5C 0. "mem0_done,This field will be high once intialization of MSS_SPIA is finished" "0,1"
line.long 0x60 "MSS_SPIA_MEM_INIT_STATUS,"
bitfld.long 0x60 0. "mem0_status," "0,1"
line.long 0x64 "MSS_SPIB_MEM_INIT,"
bitfld.long 0x64 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_SPIB" "0,1"
line.long 0x68 "MSS_SPIB_MEM_INIT_DONE,"
bitfld.long 0x68 0. "mem0_done,This field will be high once intialization of MSS_SPIB is finished" "0,1"
line.long 0x6C "MSS_SPIB_MEM_INIT_STATUS,"
bitfld.long 0x6C 0. "mem0_status," "0,1"
line.long 0x70 "MSS_TPCC_MEMINIT_START,"
bitfld.long 0x70 16. "tpcc_b_meminit_start,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_TPCCB" "0,1"
newline
bitfld.long 0x70 0. "tpcc_a_meminit_start,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_TPCCA" "0,1"
line.long 0x74 "MSS_TPCC_MEMINIT_DONE,"
bitfld.long 0x74 16. "tpcc_b_meminit_done,This field will be high once intialization of MSS_TPCCB is finished" "0,1"
newline
bitfld.long 0x74 0. "tpcc_a_meminit_done,This field will be high once intialization of MSS_TPCCA is finished" "0,1"
line.long 0x78 "MSS_TPCC_MEMINIT_STATUS,"
bitfld.long 0x78 16. "tpcc_b_meminit_status," "0,1"
newline
bitfld.long 0x78 0. "tpcc_a_meminit_status," "0,1"
line.long 0x7C "MSS_GPADC_MEM_INIT,"
bitfld.long 0x7C 0. "mem0_init,Write_pulse bit field: Writing 1'b1 will start initializing the MSS_GPADC_DATA_MEM" "0,1"
line.long 0x80 "MSS_GPADC_MEM_INIT_DONE,"
bitfld.long 0x80 0. "mem0_done,This field will be high once intialization of MSS_GPADC_DATA_MEM is finished" "0,1"
line.long 0x84 "MSS_GPADC_MEM_INIT_STATUS,"
bitfld.long 0x84 0. "mem0_status," "0,1"
line.long 0x88 "MSS_SPIA_CFG,"
bitfld.long 0x88 24. "spia_int_trig_polarity,SPIA trigger source polarity select" "0,1"
newline
bitfld.long 0x88 16. "spia_trig_gate_en,When set the TRIGGER s are un-gated only when chip-select is active" "0,1"
newline
bitfld.long 0x88 8. "spia_cs_trigsrc_en,MIBSPIB CS Trigger SRC enable" "0,1"
newline
bitfld.long 0x88 0.--2. "spiasync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x8C "MSS_SPIB_CFG,"
bitfld.long 0x8C 24. "spib_int_trig_polarity,SPIB trigger source polarity select" "0,1"
newline
bitfld.long 0x8C 16. "spib_trig_gate_en,When set the TRIGGER s are un-gated only when chip-select is active" "0,1"
newline
bitfld.long 0x8C 8. "spib_cs_trigsrc_en,MIBSPIB CS Trigger SRC enable" "0,1"
newline
bitfld.long 0x8C 0.--2. "spibsync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x90 "MSS_EPWM_CFG,"
line.long 0x94 "MSS_GIO_CFG,"
line.long 0x98 "MSS_MCAN_FE_SELECT,"
bitfld.long 0x98 16.--18. "mcanb_fe_select,writing a value'N' would select Nth filter interrupt combination for hwa_cm4 interrupt and also HW_SYNC_IN Example: writing 3'd<1-7> selects MSS_MCANB_FE_INT<1-7> respectively" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x98 0.--2. "mcana_fe_select,writing a value'N' would select Nth filter interrupt combination for hwa_cm4 interrupt and also HW_SYNC_IN Example: writing 3'd<1-7> would select MSS_MCANA_FE_INT<1-7> respectively" "0,1,2,3,4,5,6,7"
line.long 0x9C "HW_SPARE_REG1,"
line.long 0xA0 "MSS_MCANA_INT_CLR,"
line.long 0xA4 "MSS_MCANA_INT_MASK,"
line.long 0xA8 "MSS_MCANA_INT_STAT,"
line.long 0xAC "HW_SPARE_REG2,"
line.long 0xB0 "CCC_ERR_STATUS,"
hexmask.long.byte 0xB0 16.--23. 1. "cccb_errot_status,CCCB Error Status (for Debug) {3'd0 counter_error counter_done timeout_error counter_error counter_done}"
newline
hexmask.long.byte 0xB0 0.--7. 1. "ccca_errot_status,CCCA Error Status (for Debug) {3'd0 counter_error counter_done timeout_error counter_error counter_done}"
line.long 0xB4 "CCCA_CFG0,"
hexmask.long.word 0xB4 16.--31. 1. "ccca_margin_count,Margin value for clock comparison in terms of counter1 clock.CCC error will not be generated if counter1 counter value is within count1_expected_val +/- MARGIN_COUNT"
newline
hexmask.long.byte 0xB4 9.--15. 1. "Reserved,Not used"
newline
bitfld.long 0xB4 8. "ccca_single_shot_mode," "0,1"
newline
bitfld.long 0xB4 7. "ccca_enable_module," "0,1"
newline
bitfld.long 0xB4 6. "ccca_disable_clocks," "0,1"
newline
bitfld.long 0xB4 3.--5. "ccca_clk1_sel,Selection for Clock 1" "Select clock0_src0 as source for counter1,Select clock0_src1 as source for counter1,Select clock0_src2 as source for counter1,?,?,?,?,Select clock0_src7 as source for counter1"
newline
bitfld.long 0xB4 0.--2. "ccca_clk0_sel,Selection for Clock 0" "Select clock0_src0 as source for counter0,Select clock0_src1 as source for counter0,Select clock0_src2 as source for counter0,?,?,?,?,Select clock0_src7 as source for counter0"
line.long 0xB8 "CCCA_CFG1,"
line.long 0xBC "CCCA_CFG2,"
line.long 0xC0 "CCCA_CFG3,"
line.long 0xC4 "CCCA_CNTVAL,"
line.long 0xC8 "CCCB_CFG0,"
hexmask.long.word 0xC8 16.--31. 1. "cccb_margin_count,Margin value for clock comparison in terms of counter1 clock.CCC error will not be generated if counter1 counter value is within count1_expected_val +/- MARGIN_COUNT"
newline
hexmask.long.byte 0xC8 9.--15. 1. "Reserved,Not used"
newline
bitfld.long 0xC8 8. "cccb_single_shot_mode," "0,1"
newline
bitfld.long 0xC8 7. "cccb_enable_module," "0,1"
newline
bitfld.long 0xC8 6. "cccb_disable_clocks," "0,1"
newline
bitfld.long 0xC8 3.--5. "CCCB_clk1_sel,Selection for Clock 1" "Select clock0_src0 as source for counter1,Select clock0_src1 as source for counter1,Select clock0_src2 as source for counter1,?,?,?,?,Select clock0_src7 as source for counter1"
newline
bitfld.long 0xC8 0.--2. "CCCB_clk0_sel,Selection for Clock 0" "Select clock0_src0 as source for counter0,Select clock0_src1 as source for counter0,Select clock0_src2 as source for counter0,?,?,?,?,Select clock0_src7 as source for counter0"
line.long 0xCC "CCCB_CFG1,"
line.long 0xD0 "CCCB_CFG2,"
line.long 0xD4 "CCCB_CFG3,"
line.long 0xD8 "CCCB_CNTVAL,"
line.long 0xDC "CCC_DCC_COMMON,"
bitfld.long 0xDC 12. "enable_cccb_err_nmi," "0,1"
newline
bitfld.long 0xDC 8. "enable_cccb_err_rstn," "0,1"
line.long 0xE0 "R5_GLOBAL_CONFIG,"
bitfld.long 0xE0 0. "teinit,Exception handling state at reset" "0,1"
line.long 0xE4 "R5_AHB_EN,"
bitfld.long 0xE4 16.--18. "cpu1_ahb_init,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xE4 0.--2. "cpu0_ahb_init,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0xE8 "R5A_AHB_BASE,"
hexmask.long.tbyte 0xE8 0.--19. 1. "ahb_base,Ti internal Register"
line.long 0xEC "R5A_AHB_SIZE,"
bitfld.long 0xEC 0.--4. "ahb_size,Ti internal Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xF0 "R5B_AHB_BASE,"
hexmask.long.tbyte 0xF0 0.--19. 1. "ahb_base,Ti internal Register"
line.long 0xF4 "R5B_AHB_SIZE,"
bitfld.long 0xF4 0.--4. "ahb_size,Ti internal Register" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xF8 "R5_TCM_EXT_ERR_EN,"
bitfld.long 0xF8 16.--18. "cpu1_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xF8 0.--2. "cpu0_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0xFC "R5_TCM_ERR_EN,"
bitfld.long 0xFC 16.--18. "cpu1_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0xFC 0.--2. "cpu0_tcm,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0x100 "R5_INIT_TCM,"
bitfld.long 0x100 20.--22. "lockzram_cpu1,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 16.--18. "tcmb_cpu1,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 12.--14. "tcma_cpu1,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 8.--10. "lockzram_cpu0,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 4.--6. "tcmb_cpu0,Ti internal Register" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x100 0.--2. "tcma_cpu0,Ti internal Register" "0,1,2,3,4,5,6,7"
line.long 0x104 "R5_TCM_ECC_WRENZ_EN,"
bitfld.long 0x104 20.--22. "cpu1_tcmb1_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 16.--18. "cpu1_tcmb0_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 12.--14. "cpu1_tcma_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 8.--10. "cpu0_tcmb1_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 4.--6. "cpu0_tcmb0_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMB0-RAM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x104 0.--2. "cpu0_tcma_wrenz_en,writing '000' blocks the writes to ECC-bits of TCMA-RAM of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x108 "ESM_GATING0,"
line.long 0x10C "ESM_GATING1,"
line.long 0x110 "ESM_GATING2,"
line.long 0x114 "ESM_GATING3,"
line.long 0x118 "ESM_GATING4,"
line.long 0x11C "ESM_GATING5,"
line.long 0x120 "ESM_GATING6,"
line.long 0x124 "ESM_GATING7,"
line.long 0x128 "ERR_PARITY_ATCM0,"
hexmask.long.tbyte 0x128 0.--19. 1. "addr,Address lathched when parity error is occurred for ATCM of CR5A"
line.long 0x12C "ERR_PARITY_ATCM1,"
hexmask.long.tbyte 0x12C 0.--19. 1. "addr,Address lathched when parity error is occurred for ATCM of CR5B"
line.long 0x130 "ERR_PARITY_B0TCM0,"
hexmask.long.tbyte 0x130 0.--19. 1. "addr,Address lathched when parity error is occurred for B0TCM of CR5A"
line.long 0x134 "ERR_PARITY_B0TCM1,"
hexmask.long.tbyte 0x134 0.--19. 1. "addr,Address lathched when parity error is occurred for B0TCM of CR5B"
line.long 0x138 "ERR_PARITY_B1TCM0,"
hexmask.long.tbyte 0x138 0.--19. 1. "addr,Address lathched when parity error is occurred for B1TCM of CR5A"
line.long 0x13C "ERR_PARITY_B1TCM1,"
hexmask.long.tbyte 0x13C 0.--19. 1. "addr,Address lathched when parity error is occurred for B1TCM of CR5B"
line.long 0x140 "TCM_PARITY_CTRL,"
bitfld.long 0x140 20.--22. "b1tcm1_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 16.--18. "b1tcm0_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 12.--14. "b0cm1_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 8.--10. "b0tcm0_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 4.--6. "atcm1_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x140 0.--2. "atcm0_erraddr_clr,Pulse bit-field writing 3'b111 clears the Address latched after parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x144 "TCM_PARITY_ERRFRC,"
bitfld.long 0x144 20.--22. "b1tcm1,Pulse bit-field writing 3'b111 forces a parity error for B1TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 16.--18. "b1tcm0,Pulse bit-field writing 3'b111 forces a parity error for B1TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 12.--14. "b0tcm1,Pulse bit-field writing 3'b111 forces a parity error for B0TCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 8.--10. "b0tcm0,Pulse bit-field writing 3'b111 forces a parity error for B0TCM of CR5A" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 4.--6. "atcm1,Pulse bit-field writing 3'b111 forces a parity error for ATCM of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x144 0.--2. "atcm0,Pulse bit-field writing 3'b111 forces a parity error for ATCM of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x148 "HW_SPARE_REG3,"
line.long 0x14C "SPIA_IO_CFG,"
bitfld.long 0x14C 16.--18. "miso_oen_by_cs,MIBSPIA MISO OE_N Control based on Chip selectCS-applicable in slave mode" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
newline
bitfld.long 0x14C 8.--10. "cs_pol,MIBSPIA CS polarity-slave mode" "Active low,Active high,?..."
newline
bitfld.long 0x14C 0.--2. "cs_deact," "0,1,2,3,4,5,6,7"
line.long 0x150 "SPIB_IO_CFG,"
bitfld.long 0x150 16.--18. "miso_oen_by_cs,MIBSPIB MISO OE_N Control based on Chip selectCS-applicable in slave mode" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
newline
bitfld.long 0x150 8.--10. "cs_pol,MIBSPIB CS polarity-slave mode" "Active low,Active high,?..."
newline
bitfld.long 0x150 0.--2. "cs_deact," "0,1,2,3,4,5,6,7"
line.long 0x154 "SPI_HOST_IRQ,"
bitfld.long 0x154 0.--2. "host_irq,HOST IRQ" "0,1,2,3,4,5,6,7"
line.long 0x158 "TPTC_DBS_CONFIG,"
bitfld.long 0x158 8.--9. "tptc_b0,Default burst size tieoff value for TPTC_B0" "0,1,2,3"
newline
bitfld.long 0x158 4.--5. "tptc_a1,Default burst size tieoff value for TPTC_A1" "0,1,2,3"
newline
bitfld.long 0x158 0.--1. "tptc_a0,Default burst size tieoff value for TPTC_A0" "0,1,2,3"
line.long 0x15C "TPCC_PARITY_CTRL,"
bitfld.long 0x15C 20. "tpcc_b_parity_err_clr,parity clear bit" "0,1"
newline
bitfld.long 0x15C 16. "tpcc_a_parity_err_clr,parity clear bit" "0,1"
newline
bitfld.long 0x15C 12. "tpcc_b_parity_testen,parity test enable for tpcc b" "0,1"
newline
bitfld.long 0x15C 8. "tpcc_b_parity_en,parity en for tpcc b" "0,1"
newline
bitfld.long 0x15C 4. "tpcc_a_parity_testen,parity test enable for tpcc a" "0,1"
newline
bitfld.long 0x15C 0. "tpcc_a_parity_en,writing 1'b1 enables parity for TPCC_A" "0,1"
line.long 0x160 "TPCC_PARITY_STATUS,"
hexmask.long.byte 0x160 16.--23. 1. "tpcc_b_parity_addr,address where parity error happened for tpccb"
newline
hexmask.long.byte 0x160 0.--7. 1. "tpcc_a_parity_addr,address where parity error happened for tpcca"
line.long 0x164 "MSS_DBG_ACK_CTL0,"
bitfld.long 0x164 24.--26. "cpsw,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 20.--22. "dccd,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 16.--18. "dccc,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 12.--14. "dccb,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 8.--10. "dcca,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 4.--6. "cccb,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x164 0.--2. "ccca,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x168 "MSS_DBG_ACK_CTL1,"
bitfld.long 0x168 24.--26. "scib,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 20.--22. "scia,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 16.--18. "i2c,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 12.--14. "mcrc,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 8.--10. "wdt,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 4.--6. "rti,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
newline
bitfld.long 0x168 0.--2. "dcan,Enable Suspend control for the peripheral" "Peripheral not suspended along with processor,Peripehal Suspended along with procesor,?..."
line.long 0x16C "CPSW_CONTROL,"
bitfld.long 0x16C 16. "rgmii1_id_mode,writing 1'b1 would disable the internal clock delays" "0,1"
newline
bitfld.long 0x16C 8. "rmii_ref_clk_oe_n,To select the rmii_ref_clk from PAD or from MSS_RCM" "clock will be from mss_rcm through..,will be from"
newline
bitfld.long 0x16C 0.--2. "port1_mode_sel,Port 1 Interface" "GMII/MII,RMII,RGMII,Not Supported,?..."
line.long 0x170 "MSS_TPCC_A_ERRAGG_MASK,"
bitfld.long 0x170 26. "tptc_a1_read_access_error,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 25. "tptc_a0_read_access_error,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 24. "tpcc_a_read_access_error,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 18. "tptc_a1_write_access_error,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 17. "tptc_a0_write_access_error,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 16. "tpcc_a_write_access_error,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 4. "tpcc_a_par_err,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 3. "tptc_a1_err,Mask Error from MSS_TPTC_A1 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 2. "tptc_a0_err,Mask Error from MSS_TPTC_A0 to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 1. "tpcc_a_mpint,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x170 0. "tpcc_a_errint,Mask Error from MSS_TPCC_A to aggregated Error MSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x174 "MSS_TPCC_A_ERRAGG_STATUS,"
bitfld.long 0x174 26. "tptc_a1_read_access_error,Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x174 25. "tptc_a0_read_access_error,Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x174 24. "tpcc_a_read_access_error,Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x174 18. "tptc_a1_write_access_error,Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x174 17. "tptc_a0_write_access_error,Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x174 16. "tpcc_a_write_access_error,Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x174 4. "tpcc_a_par_err,Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x174 3. "tptc_a1_err,Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x174 2. "tptc_a0_err,Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x174 1. "tpcc_a_mpint,Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x174 0. "tpcc_a_errint,Status of Error from MSS_TPCC_A" "0,1"
line.long 0x178 "MSS_TPCC_A_ERRAGG_STATUS_RAW,"
bitfld.long 0x178 26. "tptc_a1_read_access_error,Raw Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x178 25. "tptc_a0_read_access_error,Raw Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x178 24. "tpcc_a_read_access_error,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 18. "tptc_a1_write_access_error,Raw Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x178 17. "tptc_a0_write_access_error,Raw Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x178 16. "tpcc_a_write_access_error,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 4. "tpcc_a_par_err,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 3. "tptc_a1_err,Raw Status of Error from MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x178 2. "tptc_a0_err,Raw Status of Error from MSS_TPTC_A0" "0,1"
newline
bitfld.long 0x178 1. "tpcc_a_mpint,Raw Status of Error from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x178 0. "tpcc_a_errint,Raw Status of Error from MSS_TPCC_A" "0,1"
line.long 0x17C "MSS_TPCC_A_INTAGG_MASK,"
bitfld.long 0x17C 17. "tptc_a1,Mask Interrupt from TPTC A1 to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 16. "tptc_a0,Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 8. "tpcc_a_int7,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 7. "tpcc_a_int6,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 6. "tpcc_a_int5,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 5. "tpcc_a_int4,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 4. "tpcc_a_int3,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 3. "tpcc_a_int2,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 2. "tpcc_a_int1,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 1. "tpcc_a_int0,Mask Interrupt from TPCC A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x17C 0. "tpcc_a_intg,Mask Interrupt from MSS_TPCC_A to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x180 "MSS_TPCC_A_INTAGG_STATUS,"
bitfld.long 0x180 17. "tptc_a1,Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x180 16. "tptc_a0,Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x180 8. "tpcc_a_int7,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 7. "tpcc_a_int6,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 6. "tpcc_a_int5,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 5. "tpcc_a_int4,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 4. "tpcc_a_int3,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 3. "tpcc_a_int2,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 2. "tpcc_a_int1,Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x180 1. "tpcc_a_int0,Status of Interrupt from TPCC A Set only if Interupt is unmasked in MSS_TPCC_A_INTAGG_MASK Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x180 0. "tpcc_a_intg,Status of Interrupt from MSS_TPCC_A" "0,1"
line.long 0x184 "MSS_TPCC_A_INTAGG_STATUS_RAW,"
bitfld.long 0x184 17. "tptc_a1,Raw Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x184 16. "tptc_a0,Raw Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x184 8. "tpcc_a_int7,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 7. "tpcc_a_int6,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 6. "tpcc_a_int5,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 5. "tpcc_a_int4,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 4. "tpcc_a_int3,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 3. "tpcc_a_int2,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 2. "tpcc_a_int1,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
newline
bitfld.long 0x184 1. "tpcc_a_int0,Raw Status of Interrupt from TPCC A" "0,1"
newline
bitfld.long 0x184 0. "tpcc_a_intg,Raw Status of Interrupt from MSS_TPCC_A" "0,1"
line.long 0x188 "MSS_TPCC_B_ERRAGG_MASK,"
bitfld.long 0x188 25. "tptc_b0_read_access_error,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 24. "tpcc_b_read_access_error,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 17. "tptc_b0_write_access_error,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 16. "tpcc_b_write_access_error,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 4. "tpcc_b_par_err,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 2. "tptc_b0_err,Mask Error from MSS_TPTC_B0 to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 1. "tpcc_b_mpint,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x188 0. "tpcc_b_errint,Mask Error from MSS_TPCC_B to aggregated Error MSS_TPCC_B_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x18C "MSS_TPCC_B_ERRAGG_STATUS,"
bitfld.long 0x18C 25. "tptc_b0_read_access_error,Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x18C 24. "tpcc_b_read_access_error,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 17. "tptc_b0_write_access_error,Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x18C 16. "tpcc_b_write_access_error,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 4. "tpcc_b_par_err,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 2. "tptc_b0_err,Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x18C 1. "tpcc_b_mpint,Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x18C 0. "tpcc_b_errint,Status of Error from MSS_TPCC_B" "0,1"
line.long 0x190 "MSS_TPCC_B_ERRAGG_STATUS_RAW,"
bitfld.long 0x190 25. "tptc_b0_read_access_error,Raw Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x190 24. "tpcc_b_read_access_error,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 17. "tptc_b0_write_access_error,Raw Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x190 16. "tpcc_b_write_access_error,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 4. "tpcc_b_par_err,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 2. "tptc_b0_err,Raw Status of Error from MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x190 1. "tpcc_b_mpint,Raw Status of Error from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x190 0. "tpcc_b_errint,Raw Status of Error from MSS_TPCC_B" "0,1"
line.long 0x194 "MSS_TPCC_B_INTAGG_MASK,"
bitfld.long 0x194 16. "tptc_b0,Mask Interrupt from TPTC A0 to aggregated Interrupt MSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 8. "tpcc_b_int7,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 7. "tpcc_b_int6,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 6. "tpcc_b_int5,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 5. "tpcc_b_int4,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 4. "tpcc_b_int3,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 3. "tpcc_b_int2,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 2. "tpcc_b_int1,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 1. "tpcc_b_int0,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x194 0. "tpcc_b_intg,Mask Interrupt from MSS_TPCC_B to aggregated Interrupt MSS_TPCC_B_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x198 "MSS_TPCC_B_INTAGG_STATUS,"
bitfld.long 0x198 16. "tptc_b0,Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x198 8. "tpcc_b_int7,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 7. "tpcc_b_int6,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 6. "tpcc_b_int5,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 5. "tpcc_b_int4,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 4. "tpcc_b_int3,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 3. "tpcc_b_int2,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 2. "tpcc_b_int1,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 1. "tpcc_b_int0,Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x198 0. "tpcc_b_intg,Status of Interrupt from MSS_TPCC_B" "0,1"
line.long 0x19C "MSS_TPCC_B_INTAGG_STATUS_RAW,"
bitfld.long 0x19C 16. "tptc_b0,Raw Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x19C 8. "tpcc_b_int7,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 7. "tpcc_b_int6,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 6. "tpcc_b_int5,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 5. "tpcc_b_int4,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 4. "tpcc_b_int3,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 3. "tpcc_b_int2,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 2. "tpcc_b_int1,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 1. "tpcc_b_int0,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
newline
bitfld.long 0x19C 0. "tpcc_b_intg,Raw Status of Interrupt from MSS_TPCC_B" "0,1"
line.long 0x1A0 "MSS_BUS_SAFETY_CTRL,"
bitfld.long 0x1A0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1A4 "MSS_CR5A_AXI_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1A4 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A4 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "MSS_CR5A_AXI_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x1A8 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A8 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A8 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1AC "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1AC 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B0 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1B0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1B0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B4 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1B8 "MSS_CR5A_AXI_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1BC "MSS_CR5B_AXI_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1BC 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1BC 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1BC 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "MSS_CR5B_AXI_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x1C0 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C0 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C0 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C0 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1C4 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1C4 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1C8 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1C8 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1CC "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1D0 "MSS_CR5B_AXI_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1D4 "MSS_CR5A_AXI_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1D4 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1D4 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D4 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1D8 "MSS_CR5A_AXI_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1D8 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D8 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1D8 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1D8 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1D8 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1DC "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1DC 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1DC 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1DC 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1DC 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1E0 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1E0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1E4 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1E8 "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1EC "MSS_CR5A_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1F0 "MSS_CR5B_AXI_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1F0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1F0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1F4 "MSS_CR5B_AXI_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1F4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1F4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1F4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1F8 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1F8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1F8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1FC "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1FC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1FC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x200 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x204 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x208 "MSS_CR5B_AXI_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x20C "MSS_CR5A_AXI_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x20C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x20C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x20C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x210 "MSS_CR5A_AXI_S_BUS_SAFETY_FI,"
hexmask.long.byte 0x210 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x210 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x210 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x210 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x210 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x214 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0x214 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x214 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x214 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x214 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x218 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x218 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x218 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x21C "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x220 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x224 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x228 "MSS_CR5A_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x22C "MSS_CR5B_AXI_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x22C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x22C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x22C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x230 "MSS_CR5B_AXI_S_BUS_SAFETY_FI,"
hexmask.long.byte 0x230 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x230 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x230 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x230 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x230 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x234 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0x234 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x234 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x234 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x234 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x238 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x238 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x238 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x23C "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x240 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x244 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x248 "MSS_CR5B_AXI_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x24C "MSS_TPTC_A0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x24C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x24C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x250 "MSS_TPTC_A0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x250 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x250 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x250 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x250 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x250 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x254 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x254 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x254 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x254 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x254 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x258 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x258 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x258 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x25C "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x260 "MSS_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x264 "MSS_TPTC_A1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x264 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x264 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x264 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x268 "MSS_TPTC_A1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x268 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x268 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x268 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x268 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x268 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x26C "MSS_TPTC_A1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x26C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x26C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x26C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x26C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x270 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x270 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x270 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x274 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x278 "MSS_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x27C "MSS_TPTC_B0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x27C 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x27C 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x27C 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x280 "MSS_TPTC_B0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x280 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x280 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x280 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x280 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x280 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x284 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x284 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x284 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x284 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x284 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x288 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x288 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x288 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x28C "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x290 "MSS_TPTC_B0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x294 "MSS_TPTC_A0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x294 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x294 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x294 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x298 "MSS_TPTC_A0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x298 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x298 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x298 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x298 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x298 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x29C "MSS_TPTC_A0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x29C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x29C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x29C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x29C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2A0 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2A0 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2A0 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2A4 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2A8 "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x2AC "MSS_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x2B0 "MSS_TPTC_A1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x2B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x2B4 "MSS_TPTC_A1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x2B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x2B8 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x2B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2BC "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2BC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2BC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2C0 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2C4 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x2C8 "MSS_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x2CC "MSS_TPTC_B0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x2CC 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2CC 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2CC 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x2D0 "MSS_TPTC_B0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x2D0 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D0 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D0 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2D0 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2D0 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x2D4 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x2D4 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D4 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D4 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D4 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2D8 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2D8 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2D8 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2DC "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2E0 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x2E4 "MSS_TPTC_B0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x2E8 "HSM_TPTC_A0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x2E8 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2E8 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2E8 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x2EC "HSM_TPTC_A0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x2EC 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2EC 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2EC 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x2EC 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x2EC 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x2F0 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x2F0 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F0 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F0 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F0 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2F4 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2F4 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2F4 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2F8 "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x2FC "HSM_TPTC_A0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x300 "HSM_TPTC_A1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x300 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x300 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x300 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x304 "HSM_TPTC_A1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x304 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x304 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x304 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x304 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x304 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x308 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x308 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x308 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x308 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x308 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x30C "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x30C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x30C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x310 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x314 "HSM_TPTC_A1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x318 "HSM_TPTC_A0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x318 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x318 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x318 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x31C "HSM_TPTC_A0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x31C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x31C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x31C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x31C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x31C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x320 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x320 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x320 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x320 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x320 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x324 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x324 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x324 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x328 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x32C "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x330 "HSM_TPTC_A0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x334 "HSM_TPTC_A1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x334 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x334 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x334 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x338 "HSM_TPTC_A1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x338 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x338 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x338 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x338 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x338 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x33C "HSM_TPTC_A1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x33C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x33C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x33C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x33C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x340 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x340 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x340 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x344 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x348 "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x34C "HSM_TPTC_A1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x350 "MSS_QSPI_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x350 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x350 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x350 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x354 "MSS_QSPI_BUS_SAFETY_FI,"
hexmask.long.byte 0x354 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x354 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x354 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x354 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x354 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x358 "MSS_QSPI_BUS_SAFETY_ERR,"
hexmask.long.byte 0x358 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x358 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x358 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x358 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x35C "MSS_QSPI_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x35C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x35C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x360 "MSS_QSPI_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x364 "MSS_QSPI_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x368 "MSS_QSPI_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x36C "MSS_QSPI_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x370 "HSM_DTHE_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x370 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x370 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x370 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x374 "HSM_DTHE_BUS_SAFETY_FI,"
hexmask.long.byte 0x374 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x374 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x374 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x374 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x374 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x378 "HSM_DTHE_BUS_SAFETY_ERR,"
hexmask.long.byte 0x378 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x378 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x378 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x378 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x37C "HSM_DTHE_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x37C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x37C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x380 "HSM_DTHE_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x384 "HSM_DTHE_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x388 "HSM_DTHE_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x38C "HSM_DTHE_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x390 "MSS_CPSW_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x390 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x390 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x390 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x394 "MSS_CPSW_BUS_SAFETY_FI,"
hexmask.long.byte 0x394 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x394 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x394 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x394 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x394 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x398 "MSS_CPSW_BUS_SAFETY_ERR,"
hexmask.long.byte 0x398 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x398 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x398 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x398 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x39C "MSS_CPSW_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x39C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x39C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3A0 "MSS_CPSW_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x3A4 "MSS_CPSW_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x3A8 "MSS_CPSW_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3AC "MSS_CPSW_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x3B0 "MSS_MCRC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x3B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x3B4 "MSS_MCRC_BUS_SAFETY_FI,"
hexmask.long.byte 0x3B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x3B8 "MSS_MCRC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x3B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3BC "MSS_MCRC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3BC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3BC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3C0 "MSS_MCRC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x3C4 "MSS_MCRC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x3C8 "MSS_MCRC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3CC "MSS_MCRC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x3D0 "MSS_PCR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x3D0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3D0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x3D4 "MSS_PCR_BUS_SAFETY_FI,"
hexmask.long.byte 0x3D4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3D4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3D4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x3D8 "MSS_PCR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x3D8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3D8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3DC "MSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3DC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3DC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3E0 "MSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x3E4 "MSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x3E8 "MSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3EC "MSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x3F0 "MSS_PCR2_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x3F0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3F0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x3F4 "MSS_PCR2_BUS_SAFETY_FI,"
hexmask.long.byte 0x3F4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x3F4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x3F4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x3F8 "MSS_PCR2_BUS_SAFETY_ERR,"
hexmask.long.byte 0x3F8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3F8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x3FC "MSS_PCR2_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x3FC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x3FC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x400 "MSS_PCR2_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x404 "MSS_PCR2_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x408 "MSS_PCR2_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x40C "MSS_PCR2_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x410 "HSM_M_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x410 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x410 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x410 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x414 "HSM_M_BUS_SAFETY_FI,"
hexmask.long.byte 0x414 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x414 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x414 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x414 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x414 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x418 "HSM_M_BUS_SAFETY_ERR,"
hexmask.long.byte 0x418 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x418 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x418 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x418 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x41C "HSM_M_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x41C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x41C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x420 "HSM_M_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x424 "HSM_M_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x428 "HSM_M_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x42C "HSM_M_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x430 "HSM_S_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x430 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x430 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x430 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x434 "HSM_S_BUS_SAFETY_FI,"
hexmask.long.byte 0x434 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x434 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x434 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x434 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x434 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x438 "HSM_S_BUS_SAFETY_ERR,"
hexmask.long.byte 0x438 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x438 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x438 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x438 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x43C "HSM_S_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x43C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x43C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x440 "HSM_S_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x444 "HSM_S_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x448 "HSM_S_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x44C "HSM_S_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x450 "DAP_R232_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x450 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x450 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x450 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x454 "DAP_R232_BUS_SAFETY_FI,"
hexmask.long.byte 0x454 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x454 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x454 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x454 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x454 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x458 "DAP_R232_BUS_SAFETY_ERR,"
hexmask.long.byte 0x458 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x458 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x458 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x458 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x45C "DAP_R232_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x45C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x45C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x460 "DAP_R232_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x464 "DAP_R232_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x468 "DAP_R232_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x46C "DAP_R232_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x470 "MSS_L2_A_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x470 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x470 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x470 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x474 "MSS_L2_A_BUS_SAFETY_FI,"
hexmask.long.byte 0x474 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x474 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x474 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x474 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x474 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x478 "MSS_L2_A_BUS_SAFETY_ERR,"
hexmask.long.byte 0x478 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x478 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x478 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x478 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x47C "MSS_L2_A_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x47C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x47C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x480 "MSS_L2_A_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x484 "MSS_L2_A_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x488 "MSS_L2_A_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x48C "MSS_L2_A_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x490 "MSS_L2_B_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x490 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x490 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x490 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x494 "MSS_L2_B_BUS_SAFETY_FI,"
hexmask.long.byte 0x494 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x494 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x494 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x494 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x494 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x498 "MSS_L2_B_BUS_SAFETY_ERR,"
hexmask.long.byte 0x498 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x498 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x498 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x498 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x49C "MSS_L2_B_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x49C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x49C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4A0 "MSS_L2_B_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x4A4 "MSS_L2_B_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x4A8 "MSS_L2_B_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x4AC "MSS_L2_B_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x4B0 "MSS_MBOX_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x4B0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4B0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4B4 "MSS_MBOX_BUS_SAFETY_FI,"
hexmask.long.byte 0x4B4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4B4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4B4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x4B8 "MSS_MBOX_BUS_SAFETY_ERR,"
hexmask.long.byte 0x4B8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4B8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4BC "MSS_MBOX_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4BC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4BC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4C0 "MSS_MBOX_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x4C4 "MSS_MBOX_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x4C8 "MSS_MBOX_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x4CC "MSS_MBOX_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x4D0 "MSS_SWBUF_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x4D0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4D0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4D4 "MSS_SWBUF_BUS_SAFETY_FI,"
hexmask.long.byte 0x4D4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4D4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4D4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x4D8 "MSS_SWBUF_BUS_SAFETY_ERR,"
hexmask.long.byte 0x4D8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4D8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4DC "MSS_SWBUF_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4DC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4DC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4E0 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x4E4 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x4E8 "MSS_SWBUF_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x4EC "MSS_SWBUF_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x4F0 "MSS_GPADC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x4F0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4F0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x4F4 "MSS_GPADC_BUS_SAFETY_FI,"
hexmask.long.byte 0x4F4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x4F4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x4F4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x4F8 "MSS_GPADC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x4F8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4F8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4FC "MSS_GPADC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4FC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4FC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x500 "MSS_GPADC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x504 "MSS_GPADC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x508 "MSS_GPADC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x50C "MSS_GPADC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x510 "MSS_BUS_SAFETY_SEC_ERR_STAT0,"
bitfld.long 0x510 31. "mss_dmmslv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 30. "mss_dmm,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 29. "gpadc,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 28. "mss_swbuf,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 27. "mss_mbox,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 26. "l2ram1,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 25. "l2ram0,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 24. "dthe,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 23. "hsm_s,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 22. "per_pcr2,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 21. "per_pcr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 20. "mcrc,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 19. "qspi,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 18. "hsm_tptc_A1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 17. "hsm_tptc_A1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 16. "hsm_tptc_A0_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 15. "hsm_tptc_A0_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 14. "mss_tptc_B1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 13. "mss_tptc_A1_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 12. "mss_tptc_A0_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 11. "mss_tptc_B1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 10. "mss_tptc_A1_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 9. "mss_tptc_A0_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 8. "cpsw,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 7. "hsm,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 6. "dap_rs232,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 5. "cr5b_slv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 4. "cr5a_slv,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 3. "cr5b_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 2. "cr5a_wr,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 1. "cr5b_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
newline
bitfld.long 0x510 0. "cr5a_rd,Bus safety single-bit-error of Node mentioned in the field" "0,1"
line.long 0x514 "MSS_BUS_SAFETY_SEC_ERR_STAT1,"
bitfld.long 0x514 24. "mss_to_mdo,Bus safety single-bit-error of Node mentioned in the field" "0,1"
group.long 0x520++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x538++0xDF
line.long 0x00 "MSS_DMM_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x00 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x00 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x00 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x04 "MSS_DMM_BUS_SAFETY_FI,"
hexmask.long.byte 0x04 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x04 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x04 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x04 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x08 "MSS_DMM_BUS_SAFETY_ERR,"
hexmask.long.byte 0x08 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x08 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x0C "MSS_DMM_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x0C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x0C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x10 "MSS_DMM_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x14 "MSS_DMM_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x18 "MSS_DMM_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1C "MSS_DMM_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x20 "MSS_DMM_SLV_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x20 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x20 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x20 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x24 "MSS_DMM_SLV_BUS_SAFETY_FI,"
hexmask.long.byte 0x24 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x24 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x24 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x24 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x28 "MSS_DMM_SLV_BUS_SAFETY_ERR,"
hexmask.long.byte 0x28 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x28 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x2C "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x2C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x2C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x30 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x34 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x38 "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x3C "MSS_DMM_SLV_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x40 "MSS_TO_MDO_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x40 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x40 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x40 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x44 "MSS_TO_MDO_BUS_SAFETY_FI,"
hexmask.long.byte 0x44 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x44 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x44 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x44 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x48 "MSS_TO_MDO_BUS_SAFETY_ERR,"
hexmask.long.byte 0x48 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x48 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x4C "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x4C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x4C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x50 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x54 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x58 "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x5C "MSS_TO_MDO_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x60 "MSS_SCRP_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x60 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x60 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x60 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x64 "MSS_SCRP_BUS_SAFETY_FI,"
hexmask.long.byte 0x64 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x64 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x64 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x64 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x68 "MSS_SCRP_BUS_SAFETY_ERR,"
hexmask.long.byte 0x68 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x68 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x6C "MSS_SCRP_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x6C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x6C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x70 "MSS_SCRP_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x74 "MSS_SCRP_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x78 "MSS_SCRP_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x7C "MSS_SCRP_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x80 "MSS_CR5A_AHB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x80 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x80 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x80 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x84 "MSS_CR5A_AHB_BUS_SAFETY_FI,"
hexmask.long.byte 0x84 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x84 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x84 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x84 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x88 "MSS_CR5A_AHB_BUS_SAFETY_ERR,"
hexmask.long.byte 0x88 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x88 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x8C "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x8C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x8C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x90 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x94 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x98 "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x9C "MSS_CR5A_AHB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xA0 "MSS_CR5B_AHB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0xA0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0xA4 "MSS_CR5B_AHB_BUS_SAFETY_FI,"
hexmask.long.byte 0xA4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0xA4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0xA4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0xA8 "MSS_CR5B_AHB_BUS_SAFETY_ERR,"
hexmask.long.byte 0xA8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xA8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0xAC "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0xAC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0xAC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0xB0 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0xB4 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0xB8 "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0xBC "MSS_CR5B_AHB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0xC0 "DMM_CTRL_REG,"
bitfld.long 0xC0 0. "dmm_pad_select," "0,1"
line.long 0xC4 "MSS_CR5A_MBOX_WRITE_DONE,"
bitfld.long 0xC4 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
newline
bitfld.long 0xC4 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
newline
bitfld.long 0xC4 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
newline
bitfld.long 0xC4 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
newline
bitfld.long 0xC4 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
newline
bitfld.long 0xC4 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
newline
bitfld.long 0xC4 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
newline
bitfld.long 0xC4 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0xC8 "MSS_CR5A_MBOX_READ_REQ,"
bitfld.long 0xC8 28. "proc_7,This is request from processor 7 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 24. "proc_6,This is request from processor 6 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 20. "proc_5,This is request from processor 5 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 16. "proc_4,This is request from processor 4 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 12. "proc_3,This is request from processor 3 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 8. "proc_2,This is request from processor 2 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 4. "proc_1,This is request from processor 1 to mss_cr5a" "0,1"
newline
bitfld.long 0xC8 0. "proc_0,This is request from processor 0 to mss_cr5a" "0,1"
line.long 0xCC "MSS_CR5A_MBOX_READ_DONE,"
bitfld.long 0xCC 28. "proc_7,This register should be written once finishing reading from CR5A's mailbox written by proc 7" "0,1"
newline
bitfld.long 0xCC 24. "proc_6,This register should be written once finishing reading from CR5A's mailbox written by proc 6" "0,1"
newline
bitfld.long 0xCC 20. "proc_5,This register should be written once finishing reading from CR5A's mailbox written by proc 5" "0,1"
newline
bitfld.long 0xCC 16. "proc_4,This register should be written once finishing reading from CR5A's mailbox written by proc 4" "0,1"
newline
bitfld.long 0xCC 12. "proc_3,This register should be written once finishing reading from CR5A's mailbox written by proc 3" "0,1"
newline
bitfld.long 0xCC 8. "proc_2,This register should be written once finishing reading from CR5A's mailbox written by proc 2" "0,1"
newline
bitfld.long 0xCC 4. "proc_1,This register should be written once finishing reading from CR5A's mailbox written by proc 1" "0,1"
newline
bitfld.long 0xCC 0. "proc_0,This register should be written once finishing reading from CR5A's mailbox written by proc 0" "0,1"
line.long 0xD0 "MSS_CR5B_MBOX_WRITE_DONE,"
bitfld.long 0xD0 28. "proc_7,This register should be written once finishing writing into the mailbox memory of processor 7" "0,1"
newline
bitfld.long 0xD0 24. "proc_6,This register should be written once finishing writing into the mailbox memory of processor 6" "0,1"
newline
bitfld.long 0xD0 20. "proc_5,This register should be written once finishing writing into the mailbox memory of processor 5" "0,1"
newline
bitfld.long 0xD0 16. "proc_4,This register should be written once finishing writing into the mailbox memory of processor 4" "0,1"
newline
bitfld.long 0xD0 12. "proc_3,This register should be written once finishing writing into the mailbox memory of processor 3" "0,1"
newline
bitfld.long 0xD0 8. "proc_2,This register should be written once finishing writing into the mailbox memory of processor 2" "0,1"
newline
bitfld.long 0xD0 4. "proc_1,This register should be written once finishing writing into the mailbox memory of processor 1" "0,1"
newline
bitfld.long 0xD0 0. "proc_0,This register should be written once finishing writing into the mailbox memory of processor 0" "0,1"
line.long 0xD4 "MSS_CR5B_MBOX_READ_REQ,"
bitfld.long 0xD4 28. "proc_7,This is request from processor 7 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 24. "proc_6,This is request from processor 6 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 20. "proc_5,This is request from processor 5 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 16. "proc_4,This is request from processor 4 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 12. "proc_3,This is request from processor 3 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 8. "proc_2,This is request from processor 2 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 4. "proc_1,This is request from processor 1 to mss_CR5B" "0,1"
newline
bitfld.long 0xD4 0. "proc_0,This is request from processor 0 to mss_CR5B" "0,1"
line.long 0xD8 "MSS_CR5B_MBOX_READ_DONE,"
bitfld.long 0xD8 28. "proc_7,This register should be written once finishing reading from CR5B's mailbox written by proc 7" "0,1"
newline
bitfld.long 0xD8 24. "proc_6,This register should be written once finishing reading from CR5B's mailbox written by proc 6" "0,1"
newline
bitfld.long 0xD8 20. "proc_5,This register should be written once finishing reading from CR5B's mailbox written by proc 5" "0,1"
newline
bitfld.long 0xD8 16. "proc_4,This register should be written once finishing reading from CR5B's mailbox written by proc 4" "0,1"
newline
bitfld.long 0xD8 12. "proc_3,This register should be written once finishing reading from CR5B's mailbox written by proc 3" "0,1"
newline
bitfld.long 0xD8 8. "proc_2,This register should be written once finishing reading from CR5B's mailbox written by proc 2" "0,1"
newline
bitfld.long 0xD8 4. "proc_1,This register should be written once finishing reading from CR5B's mailbox written by proc 1" "0,1"
newline
bitfld.long 0xD8 0. "proc_0,This register should be written once finishing reading from CR5B's mailbox written by proc 0" "0,1"
line.long 0xDC "MSS_PBIST_KEY_RST,"
bitfld.long 0xDC 4.--7. "pbist_st_rst,MSS PBIST controller will be brought out of reset when value is 0xA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0xDC 0.--3. "pbist_st_key,Top PBIST Selftest Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x624++0x0F
line.long 0x00 "MSS_QSPI_CONFIG,"
bitfld.long 0x00 8.--10. "clk_loopback,Write 3'b111 to take board level loop back clock for QSPI" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "ext_clk,Write 3'b111 to external clock as QSPI baud clock source needed for DFT IO char" "0,1,2,3,4,5,6,7"
line.long 0x04 "MSS_STC_CONTROL,"
bitfld.long 0x04 0.--2. "cr5_wfi_overide,writing 3'b111 will bypass the wfi signals from R5SS" "0,1,2,3,4,5,6,7"
line.long 0x08 "MSS_CTI_TRIG_SEL,"
hexmask.long.byte 0x08 0.--7. 1. "trig8_sel,Used for selecting the trigger source for 8th trigger of MSS_CTI"
line.long 0x0C "MSS_DBGSS_CTI_TRIG_SEL,"
hexmask.long.byte 0x0C 16.--23. 1. "trig3,Used for selecting the trigger source for 3rd trigger of ONE_MCU_CTI"
newline
hexmask.long.byte 0x0C 8.--15. 1. "trig2,Used for selecting the trigger source for 2nd trigger of ONE_MCU_CTI"
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hexmask.long.byte 0x0C 0.--7. 1. "trig1,Used for selecting the trigger source for 1st trigger of ONE_MCU_CTI"
group.long 0x654++0x8B
line.long 0x00 "MSS_TPTC_ECCAGGR_CLK_CNTRL,"
bitfld.long 0x00 2. "tptc_B0,Writing '0' will gate the clock to TPTC_B0-FIFO during ECC-AGGR interaction(fault injection)" "0,1"
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bitfld.long 0x00 1. "tptc_A1,Writing '0' will gate the clock to TPTC_A1-FIFO during ECC-AGGR interaction(fault injection)" "0,1"
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bitfld.long 0x00 0. "tptc_A0,Writing '0' will gate the clock to TPTC_A0-FIFO during ECC-AGGR interaction(fault injection)" "0,1"
line.long 0x04 "MSS_PERIPH_ERRAGG_MASK0,"
bitfld.long 0x04 27. "top_mdo_wr,Mask Interrupt from TOP_MDO to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 26. "top_mdo_rd,Mask Interrupt from TOP_MDO to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 25. "rcss_rcm_wr,Mask Interrupt from RCSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 24. "rcss_rcm_rd,Mask Interrupt from RCSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 23. "rcss_ctrl_wr,Mask Interrupt from RCSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 22. "rcss_ctrl_rd,Mask Interrupt from RCSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 21. "hwa_cfg_wr,Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 20. "hwa_cfg_rd,Mask Interrupt from HWA_CFG to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 19. "dss_cm4_ctrl_wr,Mask Interrupt from DSS_CM4_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 18. "dss_cm4_ctrl_rd,Mask Interrupt from DSS_CM4_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 17. "dss_rcm_wr,Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 16. "dss_rcm_rd,Mask Interrupt from DSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 15. "dss_ctrl_wr,Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 14. "dss_ctrl_rd,Mask Interrupt from DSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 13. "hsm_ctrl_wr,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 12. "hsm_ctrl_rd,Mask Interrupt from HSM_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 11. "hsm_soc_ctrl_wr,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 10. "hsm_soc_ctrl_rd,Mask Interrupt from HSM_SOC_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 9. "top_aurora_wr,Mask Interrupt from TOP_AURORA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 8. "top_aurora_rd,Mask Interrupt from TOP_AURORA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 7. "top_rcm_wr,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 6. "top_rcm_rd,Mask Interrupt from TOP_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 5. "top_ctrl_wr,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 4. "top_ctrl_rd,Mask Interrupt from TOP_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 3. "mss_rcm_wr,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 2. "mss_rcm_rd,Mask Interrupt from MSS_RCM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 1. "mss_ctrl_wr,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x04 0. "mss_ctrl_rd,Mask Interrupt from MSS_CTRL to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x08 "MSS_PERIPH_ERRAGG_STATUS0,"
bitfld.long 0x08 27. "top_mdo_wr,Status of Interrupt from TOP_MDO Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 26. "top_mdo_rd,Status of Interrupt from TOP_MDO Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 25. "rcss_rcm_wr,Status of Interrupt from RCSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 24. "rcss_rcm_rd,Status of Interrupt from RCSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 23. "rcss_ctrl_wr,Status of Interrupt from RCSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 22. "rcss_ctrl_rd,Status of Interrupt from RCSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 21. "hwa_cfg_wr,Status of Interrupt from HWA_CFG Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 20. "hwa_cfg_rd,Status of Interrupt from HWA_CFG Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 19. "dss_cm4_ctrl_wr,Status of Interrupt from DSS_CM4_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 18. "dss_cm4_ctrl_rd,Status of Interrupt from DSS_CM4_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 17. "dss_rcm_wr,Status of Interrupt from DSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 16. "dss_rcm_rd,Status of Interrupt from DSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 15. "dss_ctrl_wr,Status of Interrupt from DSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 14. "dss_ctrl_rd,Status of Interrupt from DSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 13. "hsm_ctrl_wr,Status of Interrupt from HSM_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 12. "hsm_ctrl_rd,Status of Interrupt from HSM_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 11. "hsm_soc_ctrl_wr,Status of Interrupt from HSM_SOC_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 10. "hsm_soc_ctrl_rd,Status of Interrupt from HSM_SOC_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 9. "top_aurora_wr,Status of Interrupt from TOP_AURORA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 8. "top_aurora_rd,Status of Interrupt from TOP_AURORA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 7. "top_rcm_wr,Status of Interrupt from TOP_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 6. "top_rcm_rd,Status of Interrupt from TOP_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 5. "top_ctrl_wr,Status of Interrupt from TOP_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 4. "top_ctrl_rd,Status of Interrupt from TOP_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 3. "mss_rcm_wr,Status of Interrupt from MSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 2. "mss_rcm_rd,Status of Interrupt from MSS_RCM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 1. "mss_ctrl_wr,Status of Interrupt from MSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x08 0. "mss_ctrl_rd,Status of Interrupt from MSS_CTRL Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK0 Wrie 0x1 to clear this interrupt" "0,1"
line.long 0x0C "MSS_PERIPH_ERRAGG_STATUS_RAW0,"
bitfld.long 0x0C 27. "top_mdo_wr,Raw Status of Interrupt from TOP_MDO" "0,1"
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bitfld.long 0x0C 26. "top_mdo_rd,Raw Status of Interrupt from TOP_MDO" "0,1"
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bitfld.long 0x0C 25. "rcss_rcm_wr,Raw Status of Interrupt from RCSS_RCM" "0,1"
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bitfld.long 0x0C 24. "rcss_rcm_rd,Raw Status of Interrupt from RCSS_RCM" "0,1"
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bitfld.long 0x0C 23. "rcss_ctrl_wr,Raw Status of Interrupt from RCSS_CTRL" "0,1"
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bitfld.long 0x0C 22. "rcss_ctrl_rd,Raw Status of Interrupt from RCSS_CTRL" "0,1"
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bitfld.long 0x0C 21. "hwa_cfg_wr,Raw Status of Interrupt from HWA_CFG" "0,1"
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bitfld.long 0x0C 20. "hwa_cfg_rd,Raw Status of Interrupt from HWA_CFG" "0,1"
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bitfld.long 0x0C 19. "dss_cm4_ctrl_wr,Raw Status of Interrupt from DSS_CM4_CTRL" "0,1"
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bitfld.long 0x0C 18. "dss_cm4_ctrl_rd,Raw Status of Interrupt from DSS_CM4_CTRL" "0,1"
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bitfld.long 0x0C 17. "dss_rcm_wr,Raw Status of Interrupt from DSS_RCM" "0,1"
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bitfld.long 0x0C 16. "dss_rcm_rd,Raw Status of Interrupt from DSS_RCM" "0,1"
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bitfld.long 0x0C 15. "dss_ctrl_wr,Raw Status of Interrupt from DSS_CTRL" "0,1"
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bitfld.long 0x0C 14. "dss_ctrl_rd,Raw Status of Interrupt from DSS_CTRL" "0,1"
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bitfld.long 0x0C 13. "hsm_ctrl_wr,Raw Status of Interrupt from HSM_CTRL" "0,1"
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bitfld.long 0x0C 12. "hsm_ctrl_rd,Raw Status of Interrupt from HSM_CTRL" "0,1"
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bitfld.long 0x0C 11. "hsm_soc_ctrl_wr,Raw Status of Interrupt from HSM_SOC_CTRL" "0,1"
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bitfld.long 0x0C 10. "hsm_soc_ctrl_rd,Raw Status of Interrupt from HSM_SOC_CTRL" "0,1"
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bitfld.long 0x0C 9. "top_aurora_wr,Raw Status of Interrupt from TOP_AURORA" "0,1"
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bitfld.long 0x0C 8. "top_aurora_rd,Raw Status of Interrupt from TOP_AURORA" "0,1"
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bitfld.long 0x0C 7. "top_rcm_wr,Raw Status of Interrupt from TOP_RCM" "0,1"
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bitfld.long 0x0C 6. "top_rcm_rd,Raw Status of Interrupt from TOP_RCM" "0,1"
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bitfld.long 0x0C 5. "top_ctrl_wr,Raw Status of Interrupt from TOP_CTRL" "0,1"
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bitfld.long 0x0C 4. "top_ctrl_rd,Raw Status of Interrupt from TOP_CTRL" "0,1"
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bitfld.long 0x0C 3. "mss_rcm_wr,Raw Status of Interrupt from MSS_RCM" "0,1"
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bitfld.long 0x0C 2. "mss_rcm_rd,Raw Status of Interrupt from MSS_RCM" "0,1"
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bitfld.long 0x0C 1. "mss_ctrl_wr,Raw Status of Interrupt from MSS_CTRL" "0,1"
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bitfld.long 0x0C 0. "mss_ctrl_rd,Raw Status of Interrupt from MSS_CTRL" "0,1"
line.long 0x10 "MSS_PERIPH_ERRAGG_MASK1,"
bitfld.long 0x10 16. "mpu_rd_hsm,Mask Interrupt from MPU_DSS_HSM to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 15. "mpu_rd_dss_mbox,Mask Interrupt from MPU_DSS_MBOX to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 14. "mpu_rd_dss_hwa_proc,Mask Interrupt from MPU_DSS_HWA_PROC to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x10 13. "mpu_rd_dss_hwa_dma1,Mask Interrupt from MPU_DSS_HWA_DMA1 to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 12. "mpu_rd_dss_hwa_dma0,Mask Interrupt from MPU_DSS_HWA_DMA0 to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 11. "mpu_rd_dss_l3_bankd,Mask Interrupt from MPU_DSS_L3_BANKD to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 10. "mpu_rd_dss_l3_bankc,Mask Interrupt from MPU_DSS_L3_BANKC to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 9. "mpu_rd_dss_l3_bankb,Mask Interrupt from MPU_DSS_L3_BANKB to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 8. "mpu_rd_dss_l3_banka,Mask Interrupt from MPU_DSS_L3_BANKA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x10 7. "mpu_rd_mss_cr5b_axis,Mask Interrupt from MPU_MSS_CR5B_AXIS to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
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bitfld.long 0x10 6. "mpu_rd_mss_cr5a_axis,Mask Interrupt from MPU_MSS_CR5A_AXIS to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 5. "mpu_rd_mss_qspi,Mask Interrupt from MPU_MSS_QSPI to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 4. "mpu_rd_mss_pcra,Mask Interrupt from MPU_MSS_PCRA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 3. "mpu_rd_mss_mbox,Mask Interrupt from MPU_MSS_MBOX to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 2. "mpu_rd_hsm_dthe,Mask Interrupt from MPU_HSM_DTHE to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 1. "mpu_rd_mss_l2_bankb,Mask Interrupt from MPU_MSS_L2_BANKB to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 0. "mpu_rd_mss_l2_banka,Mask Interrupt from MPU_MSS_L2_BANKA to aggregated Interrupt MSS_PERIPH_ACCESS_ERRAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x14 "MSS_PERIPH_ERRAGG_STATUS1,"
bitfld.long 0x14 16. "mpu_rd_hsm,Status of Interrupt from MPU_HSM Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 15. "mpu_rd_dss_mbox,Status of Interrupt from MPU_DSS_MBOX Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 14. "mpu_rd_dss_hwa_proc,Status of Interrupt from MPU_DSS_HWA_PROC Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 13. "mpu_rd_dss_hwa_dma1,Status of Interrupt from MPU_DSS_HWA_DMA1 Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 12. "mpu_rd_dss_hwa_dma0,Status of Interrupt from MPU_DSS_HWA_DMA0 Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 11. "mpu_rd_dss_l3_bankd,Status of Interrupt from MPU_DSS_L3_BANKD Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 10. "mpu_rd_dss_l3_bankc,Status of Interrupt from MPU_DSS_L3_BANKC Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 9. "mpu_rd_dss_l3_bankb,Status of Interrupt from MPU_DSS_L3_BANKB Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 8. "mpu_rd_dss_l3_banka,Status of Interrupt from MPU_DSS_L3_BANKA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 7. "mpu_rd_mss_cr5b_axis,Status of Interrupt from MPU_MSS_CR5B_AXIS Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
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bitfld.long 0x14 6. "mpu_rd_mss_cr5a_axis,Status of Interrupt from MPU_MSS_CR5A_AXIS Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 5. "mpu_rd_mss_qspi,Status of Interrupt from MPU_MSS_QSPI Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 4. "mpu_rd_mss_pcra,Status of Interrupt from MPU_MSS_PCRA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 3. "mpu_rd_mss_mbox,Status of Interrupt from MPU_MSS_MBOX Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 2. "mpu_rd_hsm_dthe,Status of Interrupt from MPU_HSM_DTHE Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 1. "mpu_rd_mss_l2_bankb,Status of Interrupt from MPU_MSS_L2_BANKB Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
newline
bitfld.long 0x14 0. "mpu_rd_mss_l2_banka,Status of Interrupt from MPU_MSS_L2_BANKA Set only if Interupt is unmasked in MSS_PERIPH_ERRAGG_MASK1 Wrie 0x1 to clear this interrupt" "0,1"
line.long 0x18 "MSS_PERIPH_ERRAGG_STATUS_RAW1,"
bitfld.long 0x18 16. "mpu_rd_hsm,Raw Status of Interrupt from MPU_HSM" "0,1"
newline
bitfld.long 0x18 15. "mpu_rd_dss_mbox,Raw Status of Interrupt from MPU_DSS_MBOX" "0,1"
newline
bitfld.long 0x18 14. "mpu_rd_dss_hwa_proc,Raw Status of Interrupt from MPU_DSS_HWA_PROC" "0,1"
newline
bitfld.long 0x18 13. "mpu_rd_dss_hwa_dma1,Raw Status of Interrupt from MPU_DSS_HWA_DMA1" "0,1"
newline
bitfld.long 0x18 12. "mpu_rd_dss_hwa_dma0,Raw Status of Interrupt from MPU_DSS_HWA_DMA0" "0,1"
newline
bitfld.long 0x18 11. "mpu_rd_dss_l3_bankd,Raw Status of Interrupt from MPU_DSS_L3_BANKD" "0,1"
newline
bitfld.long 0x18 10. "mpu_rd_dss_l3_bankc,Raw Status of Interrupt from MPU_DSS_L3_BANKC" "0,1"
newline
bitfld.long 0x18 9. "mpu_rd_dss_l3_bankb,Raw Status of Interrupt from MPU_DSS_L3_BANKB" "0,1"
newline
bitfld.long 0x18 8. "mpu_rd_dss_l3_banka,Raw Status of Interrupt from MPU_DSS_L3_BANKA" "0,1"
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bitfld.long 0x18 7. "mpu_rd_mss_cr5b_axis,Raw Status of Interrupt from MPU_MSS_CR5B_AXIS" "0,1"
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bitfld.long 0x18 6. "mpu_rd_mss_cr5a_axis,Raw Status of Interrupt from MPU_MSS_CR5A_AXIS" "0,1"
newline
bitfld.long 0x18 5. "mpu_rd_mss_qspi,Raw Status of Interrupt from MPU_MSS_QSPI" "0,1"
newline
bitfld.long 0x18 4. "mpu_rd_mss_pcra,Raw Status of Interrupt from MPU_MSS_PCRA" "0,1"
newline
bitfld.long 0x18 3. "mpu_rd_mss_mbox,Raw Status of Interrupt from MPU_MSS_MBOX" "0,1"
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bitfld.long 0x18 2. "mpu_rd_hsm_dthe,Raw Status of Interrupt from MPU_HSM_D" "0,1"
newline
bitfld.long 0x18 1. "mpu_rd_mss_l2_bankb,Raw Status of Interrupt from MPU_MSS_L2_BANKB" "0,1"
newline
bitfld.long 0x18 0. "mpu_rd_mss_l2_banka,Raw Status of Interrupt from MPU_MSS_L2_BANKA" "0,1"
line.long 0x1C "MSS_DMM_EVENT0_REG,"
bitfld.long 0x1C 28. "event_sel3,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x1C 24. "event_trig3,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
newline
bitfld.long 0x1C 20. "event_sel2,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x1C 16. "event_trig2,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
newline
bitfld.long 0x1C 12. "event_sel1,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x1C 8. "event_trig1,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
newline
bitfld.long 0x1C 4. "event_sel0,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
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bitfld.long 0x1C 0. "event_trig0,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
line.long 0x20 "MSS_DMM_EVENT1_REG,"
bitfld.long 0x20 28. "event_sel7,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x20 24. "event_trig7,DMM trigger for RCSS_CSI2A_SOF_INT1" "0,1"
newline
bitfld.long 0x20 20. "event_sel6,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x20 16. "event_trig6,DMM trigger for RCSS_CSI2A_SOF_INT1" "0,1"
newline
bitfld.long 0x20 12. "event_sel5,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x20 8. "event_trig5,DMM trigger for RCSS_CSI2A_SOF_INT1" "0,1"
newline
bitfld.long 0x20 4. "event_sel4,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
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bitfld.long 0x20 0. "event_trig4,DMM trigger for RCSS_CSI2A_SOF_INT0" "0,1"
line.long 0x24 "MSS_DMM_EVENT2_REG,"
bitfld.long 0x24 28. "event_sel11,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 24. "event_trig11,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x24 20. "event_sel10,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 16. "event_trig10,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x24 12. "event_sel9,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 8. "event_trig9,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x24 4. "event_sel8,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x24 0. "event_trig8,DMM trigger for RCSS_CSI2A_EOL_CNTX0_INT" "0,1"
line.long 0x28 "MSS_DMM_EVENT3_REG,"
bitfld.long 0x28 28. "event_sel15,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 24. "event_trig15,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x28 20. "event_sel14,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 16. "event_trig14,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x28 12. "event_sel13,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 8. "event_trig13,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x28 4. "event_sel12,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x28 0. "event_trig12,DMM trigger for RCSS_CSI2A_EOL_CNTX1_INT" "0,1"
line.long 0x2C "MSS_DMM_EVENT4_REG,"
bitfld.long 0x2C 28. "event_sel19,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 24. "event_trig19,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x2C 20. "event_sel18,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 16. "event_trig18,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x2C 12. "event_sel17,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 8. "event_trig17,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x2C 4. "event_sel16,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x2C 0. "event_trig16,DMM trigger for RCSS_CSI2A_EOL_CNTX2_INT" "0,1"
line.long 0x30 "MSS_DMM_EVENT5_REG,"
bitfld.long 0x30 28. "event_sel23,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 24. "event_trig23,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x30 20. "event_sel22,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 16. "event_trig22,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x30 12. "event_sel21,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 8. "event_trig21,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x30 4. "event_sel20,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x30 0. "event_trig20,DMM trigger for RCSS_CSI2A_EOL_CNTX3_INT" "0,1"
line.long 0x34 "MSS_DMM_EVENT6_REG,"
bitfld.long 0x34 28. "event_sel27,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 24. "event_trig27,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
newline
bitfld.long 0x34 20. "event_sel26,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 16. "event_trig26,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
newline
bitfld.long 0x34 12. "event_sel25,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 8. "event_trig25,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
newline
bitfld.long 0x34 4. "event_sel24,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x34 0. "event_trig24,DMM trigger for RCSS_CSI2A_EOL_CNTX4_INT" "0,1"
line.long 0x38 "MSS_DMM_EVENT7_REG,"
bitfld.long 0x38 28. "event_sel31,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 24. "event_trig31,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
newline
bitfld.long 0x38 20. "event_sel30,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 16. "event_trig30,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
newline
bitfld.long 0x38 12. "event_sel29,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 8. "event_trig29,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
newline
bitfld.long 0x38 4. "event_sel28,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x38 0. "event_trig28,DMM trigger for RCSS_CSI2A_EOL_CNTX5_INT" "0,1"
line.long 0x3C "MSS_DMM_EVENT8_REG,"
bitfld.long 0x3C 28. "event_sel35,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 24. "event_trig35,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
newline
bitfld.long 0x3C 20. "event_sel34,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 16. "event_trig34,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
newline
bitfld.long 0x3C 12. "event_sel33,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 8. "event_trig33,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
newline
bitfld.long 0x3C 4. "event_sel32,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x3C 0. "event_trig32,DMM trigger for RCSS_CSI2A_EOL_CNTX6_INT" "0,1"
line.long 0x40 "MSS_DMM_EVENT9_REG,"
bitfld.long 0x40 28. "event_sel39,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 24. "event_trig39,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
newline
bitfld.long 0x40 20. "event_sel38,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 16. "event_trig38,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
newline
bitfld.long 0x40 12. "event_sel37,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 8. "event_trig37,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
newline
bitfld.long 0x40 4. "event_sel36,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x40 0. "event_trig36,DMM trigger for RCSS_CSI2A_EOL_CNTX7_INT" "0,1"
line.long 0x44 "MSS_DMM_EVENT10_REG,"
bitfld.long 0x44 28. "event_sel43,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 24. "event_trig43,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
newline
bitfld.long 0x44 20. "event_sel42,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 16. "event_trig42,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
newline
bitfld.long 0x44 12. "event_sel41,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 8. "event_trig41,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
newline
bitfld.long 0x44 4. "event_sel40,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x44 0. "event_trig40,DMM trigger for RCSS_CSI2B_SOF_INT0" "0,1"
line.long 0x48 "MSS_DMM_EVENT11_REG,"
bitfld.long 0x48 28. "event_sel47,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 24. "event_trig47,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
newline
bitfld.long 0x48 20. "event_sel46,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 16. "event_trig46,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
newline
bitfld.long 0x48 12. "event_sel45,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 8. "event_trig45,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
newline
bitfld.long 0x48 4. "event_sel44,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x48 0. "event_trig44,DMM trigger for RCSS_CSI2B_SOF_INT1" "0,1"
line.long 0x4C "MSS_DMM_EVENT12_REG,"
bitfld.long 0x4C 28. "event_sel51,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 24. "event_trig51,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x4C 20. "event_sel50,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 16. "event_trig50,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x4C 12. "event_sel49,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 8. "event_trig49,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
newline
bitfld.long 0x4C 4. "event_sel48,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x4C 0. "event_trig48,DMM trigger for RCSS_CSI2B_EOL_CNTX0_INT" "0,1"
line.long 0x50 "MSS_DMM_EVENT13_REG,"
bitfld.long 0x50 28. "event_sel55,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 24. "event_trig55,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x50 20. "event_sel54,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 16. "event_trig54,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x50 12. "event_sel53,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 8. "event_trig53,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
newline
bitfld.long 0x50 4. "event_sel52,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x50 0. "event_trig52,DMM trigger for RCSS_CSI2B_EOL_CNTX1_INT" "0,1"
line.long 0x54 "MSS_DMM_EVENT14_REG,"
bitfld.long 0x54 28. "event_sel59,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 24. "event_trig59,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x54 20. "event_sel58,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 16. "event_trig58,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x54 12. "event_sel57,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 8. "event_trig57,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
newline
bitfld.long 0x54 4. "event_sel56,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x54 0. "event_trig56,DMM trigger for RCSS_CSI2B_EOL_CNTX2_INT" "0,1"
line.long 0x58 "MSS_DMM_EVENT15_REG,"
bitfld.long 0x58 28. "event_sel63,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 24. "event_trig63,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x58 20. "event_sel62,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 16. "event_trig62,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x58 12. "event_sel61,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 8. "event_trig61,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
newline
bitfld.long 0x58 4. "event_sel60,Writing" "Selects actual interrupt as interrupt source,Selects DMM event_trig as interrupt source"
newline
bitfld.long 0x58 0. "event_trig60,DMM trigger for RCSS_CSI2B_EOL_CNTX3_INT" "0,1"
line.long 0x5C "MSS_TPTC_BOUNDARY_CFG,"
bitfld.long 0x5C 16.--21. "tptc_b0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_B0 Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x5C 8.--13. "tptc_a1_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A1 Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x5C 0.--5. "tptc_a0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of MSS_TPTC_A0 Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x60 "MSS_TPTC_XID_REORDER_CFG,"
bitfld.long 0x60 16. "tptc_b0_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_B0" "0,1"
newline
bitfld.long 0x60 8. "tptc_a1_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A1" "0,1"
newline
bitfld.long 0x60 0. "tptc_a0_disable,writing 1'b1 will disable the CID-RID-SID reodering feature for MSS_TPTC_A0" "0,1"
line.long 0x64 "GPADC_CTRL,"
bitfld.long 0x64 8.--12. "gpadc_trigin_sel,Writing below decimal values to this regiter will select corresponding interrupt as GPADC trigger source" "GPIO_0,GPIO_1,GPIO_2,GPIO_3,RSS_CSI2A_EOL_INT,RSS_CSI2A_SOF_INT0,RSS_CSI2A_SOF_INT1,RSS_CSI2A_SOF_INT,RSS_CSI2B_SOF_INT,HW_Sync_FE1,HW_Sync_FE2,DSS_RTIA_1,DSS_RTIB_1,MSS_RTIA_INT1,MSS_RTIB_INT1,MMR based SW trigger,?..."
newline
bitfld.long 0x64 0. "gpadc_sw_trig,Writing 1'b1 will give MMR based SW trigger to GPADC" "0,1"
line.long 0x68 "HW_Sync_FE_CTRL,"
bitfld.long 0x68 8. "fe2_sel,Writing" "Selects MCANA filter event as HW_Sync_FE2,Selects MCANB filter event as HW_Sync_FE2"
newline
bitfld.long 0x68 0. "fe1_sel,Writing" "Selects MCANA filter event as HW_Sync_FE1,Selects MCANB filter event as HW_Sync_FE1"
line.long 0x6C "DEBUGSS_CSETB_FLUSH,"
rbitfld.long 0x6C 10. "CSETB_FULL,When HIGH indicates that the ETB RAM has overflowed or wrapped around to address zero" "0,1"
newline
rbitfld.long 0x6C 9. "CSETB_ACQ_COMPLETE,When HIGH indicates that trace acquisition is complete by ETB that is the trigger counter is at zero" "0,1"
newline
rbitfld.long 0x6C 8. "CSETB_FLUSHINACK,Return acknowledgement to CSETBFLUSHIN" "0,1"
newline
bitfld.long 0x6C 0. "CSETB_FLUSHIN,External control used to assert the ATB signal AFVALIDS and drain any historical FIFO information on the bus" "0,1"
line.long 0x70 "ANALOG_WU_STATUS_REG_POLARITY_INV,"
line.long 0x74 "ANALOG_CLK_STATUS_REG_POLARITY_INV,"
line.long 0x78 "ANALOG_WU_STATUS_REG_GRP1_MASK,"
line.long 0x7C "ANALOG_CLK_STATUS_REG_GRP1_MASK,"
line.long 0x80 "ANALOG_WU_STATUS_REG_GRP2_MASK,"
line.long 0x84 "ANALOG_CLK_STATUS_REG_GRP2_MASK,"
line.long 0x88 "NERROR_MASK,"
bitfld.long 0x88 0.--2. "mask,writing 3'b111 will mask the Nerror propagation to pad Writing 3'b000 will unmask the Nerror propagation to pad" "0,1,2,3,4,5,6,7"
group.long 0x800++0x13
line.long 0x00 "R5_CONTROL,"
bitfld.long 0x00 24.--26. "rom_wait_state,writing '111' enables a single cycle wait state with respect to CR5A_clk for rom access" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16.--18. "reset_fsm_trigger,writing 3'b111 will trigger the reset FSM" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "lock_step_switch_wait,writing 3'b111 ensures switch happens only after R5SS reset" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "lock_step,writing 3'b000 ensures R5 to be in Dual-Core mode" "0,1,2,3,4,5,6,7"
line.long 0x04 "R5_ROM_ECLIPSE,"
bitfld.long 0x04 8.--10. "memswap_wait,writing 3'b111 ensures ROM-Eclipsing happens only after R5SS reset" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 0.--2. "memswap,writing '111' ensures eclipsing of CR5A_ROM immediately if memswap_wait is not set" "0,1,2,3,4,5,6,7"
line.long 0x08 "R5_COREA_HALT,"
bitfld.long 0x08 0.--2. "halt,writing '000' will unhalt CR5A" "0,1,2,3,4,5,6,7"
line.long 0x0C "R5_COREB_HALT,"
bitfld.long 0x0C 0.--2. "halt,writing '000' will unhalt for CR5B" "0,1,2,3,4,5,6,7"
line.long 0x10 "R5_STATUS_REG,"
bitfld.long 0x10 8. "lock_step,Reading" "confirms R5SS is in Dual-core mode,confirms R5SS is in lockstep mode"
newline
bitfld.long 0x10 0. "memswap,reading" "0,1"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 8. (list 0. 1. 2. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x634)++0x03
line.long 0x00 "MSS_BOOT_INFO_REG$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
group.long ($2+0x618)++0x03
line.long 0x00 "MSS_PBIST_REG$1,"
repeat.end
repeat 7. (list 0. 1. 3. 4. 5. 6. 7. )(list 0x00 0x04 0x0C 0x10 0x14 0x18 0x1C )
group.long ($2+0x518)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_DCCA (MSS DCCA Module Registers)"
base ad:0x2F79C00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DCCB (MSS DCCB Module Registers)"
base ad:0x2F79D00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DCCC (MSS DCCC Module Registers)"
base ad:0x2F79E00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DCCD (MSS DCCD Module Registers)"
base ad:0x2F79F00
group.long 0x00++0x2B
line.long 0x00 "DCCGCTRL,Starts / stops the counters clears the error signal"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
bitfld.long 0x00 12.--15. "DONENA,The DONEENA bit enables/disables the done signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 8.--11. "SINGLESHOT,Single/Continuous checking mode" "?,?,?,?,?,Continuous &,?,?,?,?,Single,?..."
bitfld.long 0x00 4.--7. "ERRENA,The ERRENA bit enables/disables the error signal" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
bitfld.long 0x00 0.--3. "DCCENA,The DCCENA bit starts and stops the operation of the dcc" "?,?,?,?,?,disabled &,?,?,?,?,enabled,?..."
line.long 0x04 "DCCREV,Module version"
bitfld.long 0x04 31. "NU2,Reserved" "0,1"
bitfld.long 0x04 28.--30. "SCHEME,SCHEME" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 26.--27. "NU1,Reserved" "0,1,2,3"
hexmask.long.word 0x04 14.--25. 1. "FUNC,Functional release number - (RO )"
bitfld.long 0x04 9.--13. "RTL,Design Release Number - (RO )" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--8. "MAJOR,Major Revision Number - (RO )" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 5. "CUSTOM,Indicates a special version of the module" "0,1"
bitfld.long 0x04 0.--4. "MINOR,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x08 "DCCCNTSEED0,Seed value for the counter attached to clock source 0"
hexmask.long.word 0x08 20.--31. 1. "NU3,Reserved"
hexmask.long.tbyte 0x08 0.--19. 1. "COUNTSEED0,The seed value for Counter 0"
line.long 0x0C "DCCVALIDSEED0,Seed value for the timeout counter attached to clock source 0"
hexmask.long.word 0x0C 16.--31. 1. "NU4,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "VALIDSEED0,The seed value for Valid Duration Counter 0.The seed value that gets loaded into the valid duration counter for clock source 0"
line.long 0x10 "DCCCNTSEED1,Seed value for the counter attached to clock source 1"
hexmask.long.word 0x10 20.--31. 1. "NU5,Reserved"
hexmask.long.tbyte 0x10 0.--19. 1. "COUNTSEED1,The seed value for Counter 1"
line.long 0x14 "DCCSTAT,Contains the error & done flag bit"
hexmask.long 0x14 2.--31. 1. "NU6,Reserved"
bitfld.long 0x14 1. "DONE,Indicates whether or not an done has occured" "0,1"
bitfld.long 0x14 0. "ERR,Indicates whether or not an error has occured" "0,1"
line.long 0x18 "DCCCNT0,Value of the counter attached to clock source 0"
hexmask.long.word 0x18 20.--31. 1. "NU7,Reserved"
hexmask.long.tbyte 0x18 0.--19. 1. "COUNT0,This field contains the current value of counter 0"
line.long 0x1C "DCCVALID0,Value of the valid counter attached to clock source 0"
hexmask.long.word 0x1C 16.--31. 1. "NU8,Reserved"
hexmask.long.word 0x1C 0.--15. 1. "VALID0,This field contains the current value of valid counter 0"
line.long 0x20 "DCCCNT1,Value of the counter attached to clock source 1"
hexmask.long.word 0x20 20.--31. 1. "NU9,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "COUNT1,This field contains the current value of counter 1"
line.long 0x24 "DCCCLKSSRC1,Clock source1 selection control"
hexmask.long.word 0x24 16.--31. 1. "NU11,Reserved"
bitfld.long 0x24 12.--15. "KEY_B4,Key Programing (1010 is the KEY Value)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x24 4.--11. 1. "NU10,Reserved"
bitfld.long 0x24 0.--3. "CLK_SRC1,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "VCLK,DSS_CLK,BSS_CLK,QSPI_CLK,FDCAN_CLK,REF_CLK,CPU_CLK,RC_CLK,?..."
line.long 0x28 "DCCCLKSSRC0,Clock source0 selection control"
hexmask.long 0x28 4.--31. 1. "NU12,Reserved"
bitfld.long 0x28 0.--3. "CLK_SRC0,Clock source selection for Source 0 DCC-A Clock source-0 selection Program value and its respective clock selected" "PLL_600 A - VCLK,?,?,?,?,CPU_CLK,?..."
width 0x0B
tree.end
tree "MSS_DMM_A (MSS DMMA Module Registers)"
base ad:0x3F79C00
group.long 0x00++0x8F
line.long 0x00 "GLBCTRL,Sets the global configuration of the module"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "BUSY,BUSY User and privilege mode (read)" "the DMM does not currently receive data and has..,the module is currently receiving data or has.."
newline
rbitfld.long 0x00 19.--23. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18. "CONTCLK,CONTCLK" "suspend RTPCLK between packets,enable free running clock between packets"
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bitfld.long 0x00 17. "COS,COS" "disable data reception while in suspend mode,enable data reception while in suspend mode"
bitfld.long 0x00 16. "RESET,RESET This bit resets the statemachine and the registers to its reset value except the RESET bit itself" "no reset of DMM module,reset DMM module to its reset state"
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rbitfld.long 0x00 11.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9.--10. "DDM_WIDTH,DDM_WIDTH: Packet Width in Direct Data Mode User and privilege mode read and write operation: Bit Encoding Transfer Size 00 8 bit 01 16 bit 10 32 bit 11 Reserved" "0,1,2,3"
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bitfld.long 0x00 8. "TM_DMM,TM_DMM: Packet Format If this bit is set the DMM module assumes to receive packets by the Direct Data Mode" "enable Trace Mode,enable Direct Data Mode"
rbitfld.long 0x00 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "ONOFF,ON/OFF User and privilege mode (read)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTSET       ,Enables interrupts"
hexmask.long.word 0x04 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x04 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Set This enables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Set This enables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,enable interrupt when BMM HRESP = Error"
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bitfld.long 0x04 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Set This enables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Set This enables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,enable interrupt"
bitfld.long 0x04 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
newline
bitfld.long 0x04 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Set This enables the interrupt generation in case of an error condition" "no influence on bit,enable interrupt (sets corresponding bit in.."
line.long 0x08 "INTCLR,Disables interrupts"
hexmask.long.word 0x08 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x08 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Clear This disables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Clear This disables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,disable interrupt on BMM HRESP = Error"
newline
bitfld.long 0x08 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Clear This disables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Clear This disables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
newline
bitfld.long 0x08 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Clear This disables the interrupt generation in case of an error condition" "no influence on bit,disable interrupt (clears corresponding bit in.."
line.long 0x0C "INTLVL,Selects high or low priority interrupt level"
hexmask.long.word 0x0C 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x0C 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
newline
bitfld.long 0x0C 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
line.long 0x10 "INTFLAG,Interrupt Flags"
hexmask.long.word 0x10 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x10 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 7. "BUSERROR,BUSERROR: BMM Bus Error Response This bit is set when the BMM HRESP = Error" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
newline
bitfld.long 0x10 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
line.long 0x14 "OFF1,Interrupt offset for high priority level"
hexmask.long 0x14 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x14 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "OFF2,Interrupt offset for low priority level"
hexmask.long 0x18 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x18 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "DDMDEST,Configuration of Buffer for Direct Data Mode"
line.long 0x20 "DDMBL,Defines the blocksize for the buffer in Direct Data Mode"
hexmask.long 0x20 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x20 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DDMPT,Pointer to the last written entry in the buffer"
hexmask.long.tbyte 0x24 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x24 0.--14. 1. "POINTER,POINTER These bits hold the pointer to the next entry to be written in the buffer"
line.long 0x28 "INTPT,Programmable Interrupt Pointer"
hexmask.long.tbyte 0x28 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x28 0.--14. 1. "INTPT,INTPT: Interrupt Pointer When the buffer pointer (DMMDDMPT) matches the programmed value in DMMINTPT and the PROG_BUF interrupt is set a interrupt is generated"
line.long 0x2C "DEST0REG1,Defines Region 1 for Destination 0"
hexmask.long.word 0x2C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x2C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x30 "DEST0BL1,Defines the blocksize for the buffer for Destination 0 Region 1"
hexmask.long 0x30 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x30 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DEST0REG2,Defines Region 2 for Destination 0"
hexmask.long.word 0x34 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x34 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x38 "DEST0BL2,Defines the blocksize for the buffer for Destination 0 Region 2"
hexmask.long 0x38 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x38 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "DEST1REG1,Defines Region 1 for Destination1"
hexmask.long.word 0x3C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x3C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x40 "DEST1BL1,Defines the blocksize for the buffer for Destination 1 Region 1"
hexmask.long 0x40 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x40 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "DEST1REG2,Defines Region 2 for Destination 1"
hexmask.long.word 0x44 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x44 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x48 "DEST1BL2,Defines the blocksize for the buffer for Destination 1 Region 2"
hexmask.long 0x48 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x48 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "DEST2REG1,Defines Region 1 for Destination 2"
hexmask.long.word 0x4C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x4C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x50 "DEST2BL1,Defines the blocksize for the buffer for Destination 2 Region 1"
hexmask.long 0x50 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x50 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "DEST2REG2,Defines Region 2 for Destination 2"
hexmask.long.word 0x54 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x54 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x58 "DEST2BL2,Defines the blocksize for the buffer for Destination 2 Region 2"
hexmask.long 0x58 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x58 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "DEST3REG1,Defines Region 1 for Destination 3"
hexmask.long.word 0x5C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x5C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x60 "DEST3BL1,Defines the blocksize for the buffer for Destination 3 Region 1"
hexmask.long 0x60 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x60 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "DEST3REG2,Defines Region 2 for Destination 3"
hexmask.long.word 0x64 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x64 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x68 "DEST3BL2,Defines the blocksize for the buffer for Destination 3 Region 2"
hexmask.long 0x68 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x68 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "DMMPC0,Defines functional or GIO mode of pins"
hexmask.long.word 0x6C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x6C 18. "ENAFUNC,ENAFUNC: Functional mode of DMMENA pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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abitfld.long 0x6C 2.--17. "DATAxFUNC,DATAxFUNC: Functional mode of DMMDATA[x] pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "0x0000=Pin is used in GIO mode,0x0001=Pin is used in Functional model mode"
bitfld.long 0x6C 1. "CLKFUNC,CLKFUNC: Functional mode of DMMCLK pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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bitfld.long 0x6C 0. "SYNCFUNC,SYNCFUNC: Functional mode of DMMSYNC pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
line.long 0x70 "DMMPC1,Defines direction of pins"
hexmask.long.word 0x70 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x70 18. "ENADIR,ENADIR: Direction of DMMENA pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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abitfld.long 0x70 2.--17. "DATAxDIR,DATAxDIR: Direction of DMMDATA[x] pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "0x0000=Pin is set to input,0x0001=Pin is set to output"
bitfld.long 0x70 1. "CLKDIR,CLKDIR: Direction of DMMCLK pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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bitfld.long 0x70 0. "SYNCDIR,SYNCDIR: Direction of DMMSYNC pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
line.long 0x74 "DMMPC2,Input level of pins"
hexmask.long.word 0x74 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x74 18. "ENAIN,ENAIN: DMMENA input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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abitfld.long 0x74 2.--17. "DATAxIN,DATAxIN: DMMDATA[x] input This bit reflects the state of the pin in all modes User and privilege mode (read)" "0x0000=Logic low (input voltage is VIL or lower),0x0001=Logic high (input voltage is VIH or.."
bitfld.long 0x74 1. "CLKIN,CLKIN: DMMCLK input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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bitfld.long 0x74 0. "SYNCIN,SYNCIN: DMMSYNC input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
line.long 0x78 "DMMPC3,Sets pins to high or low"
hexmask.long.word 0x78 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x78 18. "ENAOUT,ENAOUT: Output state of DMMENA pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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abitfld.long 0x78 2.--17. "DATAxOUT,DATAxOUT: Output state of DMMDATA[x] pin This bit sets the pin to logic low or high level User and privilege mode (read)" "0x0000=Logic low (output voltage is set to VOL..,0x0001=Logic high (output voltage is set to VOH.."
bitfld.long 0x78 1. "CLKOUT,CLKOUT: Output state of DMMCLK pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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bitfld.long 0x78 0. "SYNCOUT,SYNCOUT: Output state of DMMSYNC pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
line.long 0x7C "DMMPC4,Sets pins to high"
hexmask.long.word 0x7C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x7C 18. "ENASET,ENASET: Sets output state of DMMENA pin to logic high Value in the ENASET bit sets the data output control register bit to 1 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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abitfld.long 0x7C 2.--17. "DATAxSET,DATAxSET: Sets output state of DMMDATA[x] pin to logic high Value in the DATAxSET bit sets the data output control register bit to 1 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=Sets the pin to Logic high (output.."
bitfld.long 0x7C 1. "CLKSET,CLKSET: Sets output state of DMMCLK pin to logic high Value in the CLKSET bit sets the data output control register bit to 1 regardless of the current value in the CLKOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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bitfld.long 0x7C 0. "SYNCSET,SYNCSET: Sets output state of DMMSYNC pin logic high Value in the SYNCSET bit sets the data output control register bit to 1 regardless of the current value in the SYNCOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
line.long 0x80 "DMMPC5,Sets pins to low"
hexmask.long.word 0x80 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x80 18. "ENACLR,ENACLR: Sets output state of DMMENA pin to logic low Value in the ENACLR bit clears the data output control register bit to 0 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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abitfld.long 0x80 2.--17. "DATAxCLR,DATAxCLR: Sets output state of DMMDATA[x] pin to logic low Value in the DATAxCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=clears the pin to logic low (output.."
bitfld.long 0x80 1. "CLKCLR,CLKCLR: Sets output state of DMMCLK pin to logic low Value in the CLKCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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bitfld.long 0x80 0. "SYNCCLR,SYNCCLR: Sets output state of DMMSYNC pin to logic low Value in the SYNCCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
line.long 0x84 "DMMPC6,Configures open drain functionality of pin"
hexmask.long.word 0x84 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x84 18. "ENAPDR,ENAPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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abitfld.long 0x84 2.--17. "DATAxPDR,DATAxPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "0x0000=configures pin as push/pull,0x0001=configures pin as open drain"
bitfld.long 0x84 1. "CLKPDR,CLKPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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bitfld.long 0x84 0. "SYNCPDR,SYNCPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
line.long 0x88 "DMMPC7,Enables/Disables pullup/pulldown structure of pin"
hexmask.long.word 0x88 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x88 18. "ENAPDIS,ENAPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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abitfld.long 0x88 2.--17. "DATAxPDIS,DATAxPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "0x0000=enables pullup/pulldown functionality,0x0001=disables pullup/pulldown functionality"
bitfld.long 0x88 1. "CLKPDIS,CLKPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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bitfld.long 0x88 0. "SYNCPDIS,SYNCPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
line.long 0x8C "DMMPC8,Enables pullup or pulldown structure of pin"
hexmask.long.word 0x8C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x8C 18. "ENAPSEL,ENAPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
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abitfld.long 0x8C 2.--17. "DATAxPSEL,DATAxPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "0x0000=enables pulldown functionality,0x0001=enables pullup functionality"
bitfld.long 0x8C 1. "CLKPDSEL,CLKPDSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
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bitfld.long 0x8C 0. "SYNCPSEL,SYNCPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
width 0x0B
tree.end
tree "MSS_DMM_B (MSS DMMB Module Registers)"
base ad:0x3F79E00
group.long 0x00++0x8F
line.long 0x00 "GLBCTRL,Sets the global configuration of the module"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "BUSY,BUSY User and privilege mode (read)" "the DMM does not currently receive data and has..,the module is currently receiving data or has.."
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rbitfld.long 0x00 19.--23. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 18. "CONTCLK,CONTCLK" "suspend RTPCLK between packets,enable free running clock between packets"
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bitfld.long 0x00 17. "COS,COS" "disable data reception while in suspend mode,enable data reception while in suspend mode"
bitfld.long 0x00 16. "RESET,RESET This bit resets the statemachine and the registers to its reset value except the RESET bit itself" "no reset of DMM module,reset DMM module to its reset state"
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rbitfld.long 0x00 11.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 9.--10. "DDM_WIDTH,DDM_WIDTH: Packet Width in Direct Data Mode User and privilege mode read and write operation: Bit Encoding Transfer Size 00 8 bit 01 16 bit 10 32 bit 11 Reserved" "0,1,2,3"
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bitfld.long 0x00 8. "TM_DMM,TM_DMM: Packet Format If this bit is set the DMM module assumes to receive packets by the Direct Data Mode" "enable Trace Mode,enable Direct Data Mode"
rbitfld.long 0x00 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "ONOFF,ON/OFF User and privilege mode (read)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTSET       ,Enables interrupts"
hexmask.long.word 0x04 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x04 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Set This enables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Set This enables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Set This enables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,enable interrupt when BMM HRESP = Error"
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bitfld.long 0x04 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Set This enables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Set This enables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,enable interrupt"
bitfld.long 0x04 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
bitfld.long 0x04 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Set This enables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,enable interrupt (sets corresponding bit in.."
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bitfld.long 0x04 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Set This enables the interrupt generation in case of an error condition" "no influence on bit,enable interrupt (sets corresponding bit in.."
line.long 0x08 "INTCLR,Disables interrupts"
hexmask.long.word 0x08 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x08 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Clear This disables the interrupt generation in case the buffer pointer equals the programmed value in the DMMINTPT register" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Clear This disables the interrupt generation in case data was written to the last entry in the buffer and the pointer wrapped around" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 3 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 2 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 1 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Clear This disables the interrupt generation in case data was accessed at the startaddress of Destination 0 Region 1" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "no influence on bit,disable interrupt on BMM HRESP = Error"
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bitfld.long 0x08 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Clear This disables the interrupt generation in case new data is received while the previous data is still in the deserializer" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Clear This disables the interrupt generation in case a overflow was denoted in the STAT bits of the received packet" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST3REG1/DMMDEST3BL1 or DMMDEST3REG2/DMMDEST3BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST2REG1/DMMDEST2BL1 or DMMDEST2REG2/DMMDEST2BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST1REG1/DMMDEST1BL1 or DMMDEST1REG2/DMMDEST1BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
bitfld.long 0x08 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Clear This disables the interrupt generation in case data should be written into a address not specified by DMMDEST0REG1/DMMDEST0BL1 or DMMDEST0REG2/DMMDEST0BL2" "no influence on bit,disable interrupt (clears corresponding bit in.."
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bitfld.long 0x08 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Clear This disables the interrupt generation in case of an error condition" "no influence on bit,disable interrupt (clears corresponding bit in.."
line.long 0x0C "INTLVL,Selects high or low priority interrupt level"
hexmask.long.word 0x0C 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x0C 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 7. "BUSERROR,BUSERROR: BMM Bus Error Response User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
bitfld.long 0x0C 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
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bitfld.long 0x0C 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Level User and privilege mode (read)" "interrupt will be mapped to level 0,interrupt will be mapped to level 1"
line.long 0x10 "INTFLAG,Interrupt Flags"
hexmask.long.word 0x10 18.--31. 1. "Reserved,Reserved"
bitfld.long 0x10 17. "PROG_BUFF,PROG_BUFF: Programmable Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 16. "EO_BUFF,EO_BUFF: End of Buffer Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 15. "DEST3REG2,DEST3REG2: Destination 3 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 14. "DEST3REG1,DEST3REG1: Destination 3 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 13. "DEST2REG2,DEST2REG2: Destination 2 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 12. "DEST2REG1,DEST2REG1: Destination 2 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 11. "DEST1REG2,DEST1REG2: Destination 1 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 10. "DEST1REG1,DEST1REG1: Destination 1 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 9. "DEST0REG2,DEST0REG2: Destination 0 Region 2 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 8. "DEST0REG1,DEST0REG1: Destination 0 Region 1 Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 7. "BUSERROR,BUSERROR: BMM Bus Error Response This bit is set when the BMM HRESP = Error" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 6. "BUFF_OVF,BUFF_OVF: Write Buffer Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 5. "SRC_OVF,SRC_OVF: Source Overflow Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 4. "DEST3_ERRENA,DEST3_ERRENA: Destination 3 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 3. "DEST2_ERRENA,DEST2_ERRENA: Destination 2 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 2. "DEST1_ERRENA,DEST1_ERRENA: Destination 1 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
bitfld.long 0x10 1. "DEST0_ERRENA,DEST0_ERRENA: Destination 0 Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
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bitfld.long 0x10 0. "PACKET_ERR_INT,PACKET_ERR_INT: Packet Error Interrupt Flag User and privilege mode (read)" "no influence on bit,bit will be cleared"
line.long 0x14 "OFF1,Interrupt offset for high priority level"
hexmask.long 0x14 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x14 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x18 "OFF2,Interrupt offset for low priority level"
hexmask.long 0x18 5.--31. 1. "Reserved,Reserved"
bitfld.long 0x18 0.--4. "OFFSET,OFFSET User and privilege mode (read): Bit Encoding Interrupt 00000 Phantom 00001 Packet Error 00010 Destination 0 Error 00011 Destination 1 Error 00100 Destination 2 Error 00101 Destination 3 Error 00110 Source Overflow 00111 Buffer Overflow.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x1C "DDMDEST,Configuration of Buffer for Direct Data Mode"
line.long 0x20 "DDMBL,Defines the blocksize for the buffer in Direct Data Mode"
hexmask.long 0x20 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x20 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "DDMPT,Pointer to the last written entry in the buffer"
hexmask.long.tbyte 0x24 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x24 0.--14. 1. "POINTER,POINTER These bits hold the pointer to the next entry to be written in the buffer"
line.long 0x28 "INTPT,Programmable Interrupt Pointer"
hexmask.long.tbyte 0x28 15.--31. 1. "Reserved,Reserved"
hexmask.long.word 0x28 0.--14. 1. "INTPT,INTPT: Interrupt Pointer When the buffer pointer (DMMDDMPT) matches the programmed value in DMMINTPT and the PROG_BUF interrupt is set a interrupt is generated"
line.long 0x2C "DEST0REG1,Defines Region 1 for Destination 0"
hexmask.long.word 0x2C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x2C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x30 "DEST0BL1,Defines the blocksize for the buffer for Destination 0 Region 1"
hexmask.long 0x30 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x30 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "DEST0REG2,Defines Region 2 for Destination 0"
hexmask.long.word 0x34 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x34 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x38 "DEST0BL2,Defines the blocksize for the buffer for Destination 0 Region 2"
hexmask.long 0x38 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x38 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "DEST1REG1,Defines Region 1 for Destination1"
hexmask.long.word 0x3C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x3C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x40 "DEST1BL1,Defines the blocksize for the buffer for Destination 1 Region 1"
hexmask.long 0x40 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x40 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "DEST1REG2,Defines Region 2 for Destination 1"
hexmask.long.word 0x44 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x44 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x48 "DEST1BL2,Defines the blocksize for the buffer for Destination 1 Region 2"
hexmask.long 0x48 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x48 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "DEST2REG1,Defines Region 1 for Destination 2"
hexmask.long.word 0x4C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x4C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x50 "DEST2BL1,Defines the blocksize for the buffer for Destination 2 Region 1"
hexmask.long 0x50 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x50 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "DEST2REG2,Defines Region 2 for Destination 2"
hexmask.long.word 0x54 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x54 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x58 "DEST2BL2,Defines the blocksize for the buffer for Destination 2 Region 2"
hexmask.long 0x58 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x58 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "DEST3REG1,Defines Region 1 for Destination 3"
hexmask.long.word 0x5C 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x5C 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x60 "DEST3BL1,Defines the blocksize for the buffer for Destination 3 Region 1"
hexmask.long 0x60 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x60 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "DEST3REG2,Defines Region 2 for Destination 3"
hexmask.long.word 0x64 18.--31. 1. "BASEADDR,BASEADDR[31:18] These bits define the base address of the 256kB region where the buffer is located"
hexmask.long.tbyte 0x64 0.--17. 1. "BLOCKADDR,BLOCKADDR[17:0] These bits define the starting address of the buffer in the 256kB page"
line.long 0x68 "DEST3BL2,Defines the blocksize for the buffer for Destination 3 Region 2"
hexmask.long 0x68 4.--31. 1. "Reserved,Reserved"
bitfld.long 0x68 0.--3. "BLOCKSIZE,BLOCKSIZE These bits define the length of the buffer region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "DMMPC0,Defines functional or GIO mode of pins"
hexmask.long.word 0x6C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x6C 18. "ENAFUNC,ENAFUNC: Functional mode of DMMENA pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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abitfld.long 0x6C 2.--17. "DATAxFUNC,DATAxFUNC: Functional mode of DMMDATA[x] pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "0x0000=Pin is used in GIO mode,0x0001=Pin is used in Functional model mode"
bitfld.long 0x6C 1. "CLKFUNC,CLKFUNC: Functional mode of DMMCLK pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
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bitfld.long 0x6C 0. "SYNCFUNC,SYNCFUNC: Functional mode of DMMSYNC pin This bit defines whether the pin is used in functional mode or in GIO mode User and privilege mode (read)" "Pin is used in GIO mode,Pin is used in Functional mode"
line.long 0x70 "DMMPC1,Defines direction of pins"
hexmask.long.word 0x70 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x70 18. "ENADIR,ENADIR: Direction of DMMENA pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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abitfld.long 0x70 2.--17. "DATAxDIR,DATAxDIR: Direction of DMMDATA[x] pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "0x0000=Pin is set to input,0x0001=Pin is set to output"
bitfld.long 0x70 1. "CLKDIR,CLKDIR: Direction of DMMCLK pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
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bitfld.long 0x70 0. "SYNCDIR,SYNCDIR: Direction of DMMSYNC pin This bit defines whether the pin is used as input or output in GIO mode User and privilege mode (read)" "Pin is set to input,Pin is set to output"
line.long 0x74 "DMMPC2,Input level of pins"
hexmask.long.word 0x74 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x74 18. "ENAIN,ENAIN: DMMENA input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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abitfld.long 0x74 2.--17. "DATAxIN,DATAxIN: DMMDATA[x] input This bit reflects the state of the pin in all modes User and privilege mode (read)" "0x0000=Logic low (input voltage is VIL or lower),0x0001=Logic high (input voltage is VIH or.."
bitfld.long 0x74 1. "CLKIN,CLKIN: DMMCLK input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
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bitfld.long 0x74 0. "SYNCIN,SYNCIN: DMMSYNC input This bit reflects the state of the pin in all modes User and privilege mode (read)" "Logic low (input voltage is VIL or lower),Logic high (input voltage is VIH or higher).."
line.long 0x78 "DMMPC3,Sets pins to high or low"
hexmask.long.word 0x78 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x78 18. "ENAOUT,ENAOUT: Output state of DMMENA pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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abitfld.long 0x78 2.--17. "DATAxOUT,DATAxOUT: Output state of DMMDATA[x] pin This bit sets the pin to logic low or high level User and privilege mode (read)" "0x0000=Logic low (output voltage is set to VOL..,0x0001=Logic high (output voltage is set to VOH.."
bitfld.long 0x78 1. "CLKOUT,CLKOUT: Output state of DMMCLK pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
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bitfld.long 0x78 0. "SYNCOUT,SYNCOUT: Output state of DMMSYNC pin This bit sets the pin to logic low or high level User and privilege mode (read)" "Logic low (output voltage is set to VOL or lower),Logic high (output voltage is set to VOH or.."
line.long 0x7C "DMMPC4,Sets pins to high"
hexmask.long.word 0x7C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x7C 18. "ENASET,ENASET: Sets output state of DMMENA pin to logic high Value in the ENASET bit sets the data output control register bit to 1 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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abitfld.long 0x7C 2.--17. "DATAxSET,DATAxSET: Sets output state of DMMDATA[x] pin to logic high Value in the DATAxSET bit sets the data output control register bit to 1 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=Sets the pin to Logic high (output.."
bitfld.long 0x7C 1. "CLKSET,CLKSET: Sets output state of DMMCLK pin to logic high Value in the CLKSET bit sets the data output control register bit to 1 regardless of the current value in the CLKOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
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bitfld.long 0x7C 0. "SYNCSET,SYNCSET: Sets output state of DMMSYNC pin logic high Value in the SYNCSET bit sets the data output control register bit to 1 regardless of the current value in the SYNCOUT bit User and privilege mode (read)" "leaves the pin unchanged,Sets the pin to Logic high (output voltage is.."
line.long 0x80 "DMMPC5,Sets pins to low"
hexmask.long.word 0x80 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x80 18. "ENACLR,ENACLR: Sets output state of DMMENA pin to logic low Value in the ENACLR bit clears the data output control register bit to 0 regardless of the current value in the ENAOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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abitfld.long 0x80 2.--17. "DATAxCLR,DATAxCLR: Sets output state of DMMDATA[x] pin to logic low Value in the DATAxCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "0x0000=leaves the pin unchanged,0x0001=clears the pin to logic low (output.."
bitfld.long 0x80 1. "CLKCLR,CLKCLR: Sets output state of DMMCLK pin to logic low Value in the CLKCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
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bitfld.long 0x80 0. "SYNCCLR,SYNCCLR: Sets output state of DMMSYNC pin to logic low Value in the SYNCCLR bit clears the data output control register bit to 0 regardless of the current value in the DATAxOUT bit User and privilege mode (read)" "leaves the pin unchanged,clears the pin to logic low (output voltage is.."
line.long 0x84 "DMMPC6,Configures open drain functionality of pin"
hexmask.long.word 0x84 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x84 18. "ENAPDR,ENAPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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abitfld.long 0x84 2.--17. "DATAxPDR,DATAxPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "0x0000=configures pin as push/pull,0x0001=configures pin as open drain"
bitfld.long 0x84 1. "CLKPDR,CLKPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
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bitfld.long 0x84 0. "SYNCPDR,SYNCPDR: Open Drain enable Enables open drain functionality on pin if pin is configured as GIO output (DMMPC0.x=0; DMMPC1.x=1)" "configures pin as push/pull,configures pin as open drain"
line.long 0x88 "DMMPC7,Enables/Disables pullup/pulldown structure of pin"
hexmask.long.word 0x88 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x88 18. "ENAPDIS,ENAPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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abitfld.long 0x88 2.--17. "DATAxPDIS,DATAxPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "0x0000=enables pullup/pulldown functionality,0x0001=disables pullup/pulldown functionality"
bitfld.long 0x88 1. "CLKPDIS,CLKPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
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bitfld.long 0x88 0. "SYNCPDIS,SYNCPDIS: Pull disable Removes internal pullup/pulldown functionality from pin when configured as input pin (DMMPC1.x=0)" "enables pullup/pulldown functionality,disables pullup/pulldown functionality"
line.long 0x8C "DMMPC8,Enables pullup or pulldown structure of pin"
hexmask.long.word 0x8C 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x8C 18. "ENAPSEL,ENAPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
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abitfld.long 0x8C 2.--17. "DATAxPSEL,DATAxPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "0x0000=enables pulldown functionality,0x0001=enables pullup functionality"
bitfld.long 0x8C 1. "CLKPDSEL,CLKPDSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
newline
bitfld.long 0x8C 0. "SYNCPSEL,SYNCPSEL: Pull select Configures pullup or pulldown functionality if DMMPC7.x=0" "enables pulldown functionality,enables pullup functionality"
width 0x0B
tree.end
tree "MSS_ECC_AGG_MSS (MSS ECC Aggregator MSS Module Registers)"
base ad:0x2F7C000
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 7. "TPTC_B0_PEND,Interrupt Pending Status for tptc_b0_pend" "0,1"
bitfld.long 0x04 6. "TPTC_A1_PEND,Interrupt Pending Status for tptc_a1_pend" "0,1"
bitfld.long 0x04 5. "TPTC_A0_PEND,Interrupt Pending Status for tptc_a0_pend" "0,1"
bitfld.long 0x04 4. "GPADC_PEND,Interrupt Pending Status for gpadc_pend" "0,1"
bitfld.long 0x04 3. "MSS_RETRAM_PEND,Interrupt Pending Status for mss_retram_pend" "0,1"
bitfld.long 0x04 2. "MSS_MBOX_PEND,Interrupt Pending Status for mss_mbox_pend" "0,1"
newline
bitfld.long 0x04 1. "MSS_L2SLV1_PEND,Interrupt Pending Status for mss_l2slv1_pend" "0,1"
bitfld.long 0x04 0. "MSS_L2SLV0_PEND,Interrupt Pending Status for mss_l2slv0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_SET,Interrupt Enable Set Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_SET,Interrupt Enable Set Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_SET,Interrupt Enable Set Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_CLR,Interrupt Enable Clear Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_CLR,Interrupt Enable Clear Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_CLR,Interrupt Enable Clear Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 7. "TPTC_B0_PEND,Interrupt Pending Status for tptc_b0_pend" "0,1"
bitfld.long 0x04 6. "TPTC_A1_PEND,Interrupt Pending Status for tptc_a1_pend" "0,1"
bitfld.long 0x04 5. "TPTC_A0_PEND,Interrupt Pending Status for tptc_a0_pend" "0,1"
bitfld.long 0x04 4. "GPADC_PEND,Interrupt Pending Status for gpadc_pend" "0,1"
bitfld.long 0x04 3. "MSS_RETRAM_PEND,Interrupt Pending Status for mss_retram_pend" "0,1"
bitfld.long 0x04 2. "MSS_MBOX_PEND,Interrupt Pending Status for mss_mbox_pend" "0,1"
newline
bitfld.long 0x04 1. "MSS_L2SLV1_PEND,Interrupt Pending Status for mss_l2slv1_pend" "0,1"
bitfld.long 0x04 0. "MSS_L2SLV0_PEND,Interrupt Pending Status for mss_l2slv0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_SET,Interrupt Enable Set Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_SET,Interrupt Enable Set Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_SET,Interrupt Enable Set Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_SET,Interrupt Enable Set Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_SET,Interrupt Enable Set Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_SET,Interrupt Enable Set Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_SET,Interrupt Enable Set Register for mss_l2slv0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 7. "TPTC_B0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_b0_pend" "0,1"
bitfld.long 0x00 6. "TPTC_A1_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a1_pend" "0,1"
bitfld.long 0x00 5. "TPTC_A0_ENABLE_CLR,Interrupt Enable Clear Register for tptc_a0_pend" "0,1"
bitfld.long 0x00 4. "GPADC_ENABLE_CLR,Interrupt Enable Clear Register for gpadc_pend" "0,1"
bitfld.long 0x00 3. "MSS_RETRAM_ENABLE_CLR,Interrupt Enable Clear Register for mss_retram_pend" "0,1"
bitfld.long 0x00 2. "MSS_MBOX_ENABLE_CLR,Interrupt Enable Clear Register for mss_mbox_pend" "0,1"
newline
bitfld.long 0x00 1. "MSS_L2SLV1_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv1_pend" "0,1"
bitfld.long 0x00 0. "MSS_L2SLV0_ENABLE_CLR,Interrupt Enable Clear Register for mss_l2slv0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_ECC_AGG_R5A (MSS ECC Aggregator R5A Module Registers)"
base ad:0x2F7B800
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU0_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM0_BANK1_PEND,Interrupt Pending Status for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM0_BANK0_PEND,Interrupt Pending Status for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM0_BANK1_PEND,Interrupt Pending Status for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM0_BANK0_PEND,Interrupt Pending Status for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM0_BANK1_PEND,Interrupt Pending Status for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM0_BANK0_PEND,Interrupt Pending Status for atcm0_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU0_DDATA_RAM7_PEND,Interrupt Pending Status for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU0_DDATA_RAM6_PEND,Interrupt Pending Status for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU0_DDATA_RAM5_PEND,Interrupt Pending Status for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU0_DDATA_RAM4_PEND,Interrupt Pending Status for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU0_DDATA_RAM3_PEND,Interrupt Pending Status for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU0_DDATA_RAM2_PEND,Interrupt Pending Status for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU0_DDATA_RAM1_PEND,Interrupt Pending Status for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU0_DDATA_RAM0_PEND,Interrupt Pending Status for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU0_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU0_DTAG_RAM3_PEND,Interrupt Pending Status for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU0_DTAG_RAM2_PEND,Interrupt Pending Status for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU0_DTAG_RAM1_PEND,Interrupt Pending Status for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU0_DTAG_RAM0_PEND,Interrupt Pending Status for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU0_IDATA_BANK3_PEND,Interrupt Pending Status for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU0_IDATA_BANK2_PEND,Interrupt Pending Status for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU0_IDATA_BANK1_PEND,Interrupt Pending Status for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU0_IDATA_BANK0_PEND,Interrupt Pending Status for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU0_ITAG_RAM3_PEND,Interrupt Pending Status for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU0_ITAG_RAM2_PEND,Interrupt Pending Status for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU0_ITAG_RAM1_PEND,Interrupt Pending Status for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU0_ITAG_RAM0_PEND,Interrupt Pending Status for cpu0_itag_ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU0_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm0_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm0_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM0_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM0_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm0_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU0_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU0_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU0_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU0_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU0_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU0_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU0_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU0_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU0_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU0_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU0_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU0_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU0_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU0_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU0_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU0_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU0_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU0_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU0_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU0_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU0_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu0_itag_ram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_ECC_AGG_R5B (MSS ECC Aggregator R5B Module Registers)"
base ad:0x2F7BC00
rgroup.long 0x00++0x03
line.long 0x00 "rev,Revision parameters"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x23
line.long 0x00 "vector,ECC Vector Register"
rbitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDRESS,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
hexmask.long.word 0x00 0.--10. 1. "ECC_VECTOR,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "stat,Misc Status"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
line.long 0x08 "wrap_rev,Revision parameters"
bitfld.long 0x08 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x08 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x08 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x08 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x08 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 6.--7. "CUSTOM,Custom version" "0,1,2,3"
newline
bitfld.long 0x08 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "ctrl,ECC Control Register"
bitfld.long 0x0C 8. "CHECK_SVBUS_TIMEOUT,check for svbus timeout errors" "0,1"
bitfld.long 0x0C 7. "CHECK_PARITY,check for parity errors" "0,1"
bitfld.long 0x0C 6. "ERROR_ONCE,Force Error only once" "0,1"
bitfld.long 0x0C 5. "FORCE_N_ROW,Force Error on any RAM" "0,1"
bitfld.long 0x0C 4. "FORCE_DED,Force Double Bit Error" "0,1"
bitfld.long 0x0C 3. "FORCE_SEC,Force Single Bit Error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLE_RMW,Enable rmw" "0,1"
bitfld.long 0x0C 1. "ECC_CHECK,Enable ECC check" "0,1"
bitfld.long 0x0C 0. "ECC_ENABLE,Enable ECC" "0,1"
line.long 0x10 "err_ctrl1,ECC Error Control1 Register"
line.long 0x14 "err_ctrl2,ECC Error Control2 Register"
hexmask.long.word 0x14 16.--31. 1. "ECC_BIT2,Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x14 0.--15. 1. "ECC_BIT1,Data bit that needs to be flipped when force_sec is set"
line.long 0x18 "err_stat1,ECC Error Status1 Register"
hexmask.long.word 0x18 16.--31. 1. "ECC_BIT1,Data bit that corresponds to the single-bit error"
bitfld.long 0x18 15. "CLR_CTRL_REG_ERR,Clear control reg error Error Status you must also re write the contorl ergister itself to clear this" "0,1"
bitfld.long 0x18 13.--14. "CLR_PARITY_ERR,Clear parity Error Status" "0,1,2,3"
bitfld.long 0x18 12. "CLR_ECC_OTHER,Clear other Error Status" "0,1"
bitfld.long 0x18 10.--11. "CLR_ECC_DED,Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 8.--9. "CLR_ECC_SEC,Clear Single Bit Error Status" "0,1,2,3"
newline
bitfld.long 0x18 7. "CTR_REG_ERR,control register error pending Level interrupt" "0,1"
bitfld.long 0x18 5.--6. "PARITY_ERR,Level parity error Error Status" "0,1,2,3"
bitfld.long 0x18 4. "ECC_OTHER,successive single-bit errors have occurred while a writeback is still pending Level interrupt" "0,1"
bitfld.long 0x18 2.--3. "ECC_DED,Level Double Bit Error Status" "0,1,2,3"
bitfld.long 0x18 0.--1. "ECC_SEC,Level Single Bit Error Status" "0,1,2,3"
line.long 0x1C "err_stat2,ECC Error Status2 Register"
line.long 0x20 "err_stat3,ECC Error Status3 Register"
bitfld.long 0x20 9. "CLR_SVBUS_TIMEOUT_ERR,Clear svbus timeout Error Status" "0,1"
bitfld.long 0x20 1. "SVBUS_TIMEOUT_ERR,Level svbus timeout error Error Status" "0,1"
rbitfld.long 0x20 0. "WB_PEND,delayed write back pending Status" "0,1"
group.long 0x3C++0x07
line.long 0x00 "sec_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "sec_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "sec_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "sec_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "ded_eoi_reg,EOI Register"
bitfld.long 0x00 0. "EOI_WR,EOI Register" "0,1"
line.long 0x04 "ded_status_reg0,Interrupt Status Register 0"
bitfld.long 0x04 27. "CPU1_KS_VIM_RAMECC_PEND,Interrupt Pending Status for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x04 26. "B1TCM1_BANK1_PEND,Interrupt Pending Status for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x04 25. "B1TCM1_BANK0_PEND,Interrupt Pending Status for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x04 24. "B0TCM1_BANK1_PEND,Interrupt Pending Status for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x04 23. "B0TCM1_BANK0_PEND,Interrupt Pending Status for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x04 22. "ATCM1_BANK1_PEND,Interrupt Pending Status for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x04 21. "ATCM1_BANK0_PEND,Interrupt Pending Status for atcm1_bank0_pend" "0,1"
bitfld.long 0x04 20. "CPU1_DDATA_RAM7_PEND,Interrupt Pending Status for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x04 19. "CPU1_DDATA_RAM6_PEND,Interrupt Pending Status for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x04 18. "CPU1_DDATA_RAM5_PEND,Interrupt Pending Status for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x04 17. "CPU1_DDATA_RAM4_PEND,Interrupt Pending Status for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x04 16. "CPU1_DDATA_RAM3_PEND,Interrupt Pending Status for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x04 15. "CPU1_DDATA_RAM2_PEND,Interrupt Pending Status for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x04 14. "CPU1_DDATA_RAM1_PEND,Interrupt Pending Status for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x04 13. "CPU1_DDATA_RAM0_PEND,Interrupt Pending Status for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x04 12. "CPU1_DDIRTY_RAM_PEND,Interrupt Pending Status for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x04 11. "CPU1_DTAG_RAM3_PEND,Interrupt Pending Status for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x04 10. "CPU1_DTAG_RAM2_PEND,Interrupt Pending Status for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x04 9. "CPU1_DTAG_RAM1_PEND,Interrupt Pending Status for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x04 8. "CPU1_DTAG_RAM0_PEND,Interrupt Pending Status for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x04 7. "CPU1_IDATA_BANK3_PEND,Interrupt Pending Status for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x04 6. "CPU1_IDATA_BANK2_PEND,Interrupt Pending Status for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x04 5. "CPU1_IDATA_BANK1_PEND,Interrupt Pending Status for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x04 4. "CPU1_IDATA_BANK0_PEND,Interrupt Pending Status for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x04 3. "CPU1_ITAG_RAM3_PEND,Interrupt Pending Status for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x04 2. "CPU1_ITAG_RAM2_PEND,Interrupt Pending Status for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x04 1. "CPU1_ITAG_RAM1_PEND,Interrupt Pending Status for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x04 0. "CPU1_ITAG_RAM0_PEND,Interrupt Pending Status for cpu1_itag_ram0_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "ded_enable_set_reg0,Interrupt Enable Set Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_SET,Interrupt Enable Set Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_SET,Interrupt Enable Set Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_SET,Interrupt Enable Set Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_SET,Interrupt Enable Set Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_SET,Interrupt Enable Set Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "ded_enable_clr_reg0,Interrupt Enable Clear Register 0"
bitfld.long 0x00 27. "CPU1_KS_VIM_RAMECC_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ks_vim_ramecc_pend" "0,1"
bitfld.long 0x00 26. "B1TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank1_pend" "0,1"
bitfld.long 0x00 25. "B1TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b1tcm1_bank0_pend" "0,1"
bitfld.long 0x00 24. "B0TCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank1_pend" "0,1"
bitfld.long 0x00 23. "B0TCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for b0tcm1_bank0_pend" "0,1"
bitfld.long 0x00 22. "ATCM1_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank1_pend" "0,1"
newline
bitfld.long 0x00 21. "ATCM1_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for atcm1_bank0_pend" "0,1"
bitfld.long 0x00 20. "CPU1_DDATA_RAM7_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram7_pend" "0,1"
bitfld.long 0x00 19. "CPU1_DDATA_RAM6_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram6_pend" "0,1"
bitfld.long 0x00 18. "CPU1_DDATA_RAM5_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram5_pend" "0,1"
bitfld.long 0x00 17. "CPU1_DDATA_RAM4_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram4_pend" "0,1"
bitfld.long 0x00 16. "CPU1_DDATA_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram3_pend" "0,1"
newline
bitfld.long 0x00 15. "CPU1_DDATA_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram2_pend" "0,1"
bitfld.long 0x00 14. "CPU1_DDATA_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram1_pend" "0,1"
bitfld.long 0x00 13. "CPU1_DDATA_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddata_ram0_pend" "0,1"
bitfld.long 0x00 12. "CPU1_DDIRTY_RAM_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_ddirty_ram_pend" "0,1"
bitfld.long 0x00 11. "CPU1_DTAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram3_pend" "0,1"
bitfld.long 0x00 10. "CPU1_DTAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram2_pend" "0,1"
newline
bitfld.long 0x00 9. "CPU1_DTAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram1_pend" "0,1"
bitfld.long 0x00 8. "CPU1_DTAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_dtag_ram0_pend" "0,1"
bitfld.long 0x00 7. "CPU1_IDATA_BANK3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank3_pend" "0,1"
bitfld.long 0x00 6. "CPU1_IDATA_BANK2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank2_pend" "0,1"
bitfld.long 0x00 5. "CPU1_IDATA_BANK1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank1_pend" "0,1"
bitfld.long 0x00 4. "CPU1_IDATA_BANK0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_idata_bank0_pend" "0,1"
newline
bitfld.long 0x00 3. "CPU1_ITAG_RAM3_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram3_pend" "0,1"
bitfld.long 0x00 2. "CPU1_ITAG_RAM2_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram2_pend" "0,1"
bitfld.long 0x00 1. "CPU1_ITAG_RAM1_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram1_pend" "0,1"
bitfld.long 0x00 0. "CPU1_ITAG_RAM0_ENABLE_CLR,Interrupt Enable Clear Register for cpu1_itag_ram0_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "aggr_enable_set,AGGR interrupt enable set Register"
bitfld.long 0x00 1. "TIMEOUT,interrupt enable set for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,interrupt enable set for parity errors" "0,1"
line.long 0x04 "aggr_enable_clr,AGGR interrupt enable clear Register"
bitfld.long 0x04 1. "TIMEOUT,interrupt enable clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,interrupt enable clear for parity errors" "0,1"
line.long 0x08 "aggr_status_set,AGGR interrupt status set Register"
bitfld.long 0x08 2.--3. "TIMEOUT,interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "aggr_status_clr,AGGR interrupt status clear Register"
bitfld.long 0x0C 2.--3. "TIMEOUT,interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_ESM (MSS ESM Module Registers)"
base ad:0x2F7A400
group.long 0x00++0x5B
line.long 0x00 "ESMIEPSR1,ESM Enable ERROR Pin Action/Response Register 1"
line.long 0x04 "ESMIEPCR1,ESM Disable ERROR Pin Action/Response Register 1"
line.long 0x08 "ESMIESR1,ESM Interrupt Enable Set/Status Register 1"
line.long 0x0C "ESMIECR1,ESM Interrupt Enable Clear/Status Register 1"
line.long 0x10 "ESMILSR1,Interrupt Level Set/Status Register 1"
line.long 0x14 "ESMILCR1,Interrupt Level Clear/Status Register 1"
line.long 0x18 "ESMSR1,ESM Status Register 1"
line.long 0x1C "ESMSR2,ESM Status Register 2"
line.long 0x20 "ESMSR3,ESM Status Register 3"
line.long 0x24 "ESMEPSR,ESM ERROR Pin Status Register"
hexmask.long 0x24 1.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x24 0. "EPSF,ERROR Pin Status Flag" "0,1"
line.long 0x28 "ESMIOFFHR,ESM Interrupt Offset High Register"
hexmask.long.tbyte 0x28 9.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x28 0.--8. 1. "INTOFFH,Offset High Level Interrupt"
line.long 0x2C "ESMIOFFLR,ESM Interrupt Offset Low Register"
hexmask.long.tbyte 0x2C 8.--31. 1. "RESERVED,Read returns 0"
hexmask.long.byte 0x2C 0.--7. 1. "INTOFFL,Offset Low Level Interrupt"
line.long 0x30 "ESMLTCR,ESM Low-Time Counter Register"
hexmask.long.word 0x30 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x30 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter 16bit pre-loadable down-counter to control low-time of ERROR pin"
line.long 0x34 "ESMLTCPR,ESM Low-Time Counter Preload Register"
hexmask.long.word 0x34 16.--31. 1. "RESERVED,Read returns 0"
hexmask.long.word 0x34 0.--15. 1. "LTCP,ERROR Pin Low-Time Counter Pre-load Value 16bit pre-load value for the ERROR pin low-time counter"
line.long 0x38 "ESMEKR,ESM Error Key Register"
hexmask.long 0x38 4.--31. 1. "RESERVED,Read returns 0"
bitfld.long 0x38 0.--3. "EKEY,Error Key" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "ESMSSR2,ESM Status Shadow Register 2"
line.long 0x40 "ESMIEPSR4,ESM Enable ERROR Pin Action/Response Register 4"
line.long 0x44 "ESMIEPCR4,ESM Disable ERROR Pin Action/Response Register 4"
line.long 0x48 "ESMIESR4,ESM Interrupt Enable Set/Status Register 4"
line.long 0x4C "ESMIECR4,ESM Interrupt Enable Clear/Status Register 4"
line.long 0x50 "ESMILSR4,Interrupt Level Set/Status Register 4"
line.long 0x54 "ESMILCR4,Interrupt Level Clear/Status Register 4"
line.long 0x58 "ESMSR4,ESM Status Register 4"
group.long 0x80++0x1B
line.long 0x00 "ESMIEPSR7,ESM Enable ERROR Pin Action/Response Register 7"
line.long 0x04 "ESMIEPCR7,ESM Disable ERROR Pin Action/Response Register 7"
line.long 0x08 "ESMIESR7,ESM Interrupt Enable Set/Status Register 7"
line.long 0x0C "ESMIECR7,ESM Interrupt Enable Clear/Status Register 7"
line.long 0x10 "ESMILSR7,Interrupt Level Set/Status Register 7"
line.long 0x14 "ESMILCR7,Interrupt Level Clear/Status Register 7"
line.long 0x18 "ESMSR7,ESM Status Register 7"
group.long 0xC0++0x1B
line.long 0x00 "ESMIEPSR10,ESM Enable ERROR Pin Action/Response Register 10"
line.long 0x04 "ESMIEPCR10,ESM Disable ERROR Pin Action/Response Register 10"
line.long 0x08 "ESMIESR10,ESM Interrupt Enable Set/Status Register 10"
line.long 0x0C "ESMIECR10,ESM Interrupt Enable Clear/Status Register 10"
line.long 0x10 "ESMILSR10,Interrupt Level Set/Status Register 10"
line.long 0x14 "ESMILCR10,Interrupt Level Clear/Status Register 10"
line.long 0x18 "ESMSR10,ESM Status Register 10"
width 0x0B
tree.end
tree "MSS_ETPWMA (MSS ETPWMA Module Registers)"
base ad:0x3F78C00
group.long 0x00++0x3F
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
hexmask.long.word 0x00 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x00 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value" "0,1"
bitfld.long 0x00 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred" "0,1"
bitfld.long 0x00 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit" "0,1"
newline
bitfld.long 0x00 14.--15. "TBCTL_FREE,_SOFT,Emulation Mode Bits" "0,1,2,3"
bitfld.long 0x00 13. "TBCTL_PHSDIR,Phase Direction Bit" "0,1"
bitfld.long 0x00 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0" "0,1"
bitfld.long 0x00 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select" "0,1,2,3"
bitfld.long 0x00 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero" "0,1"
bitfld.long 0x00 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
newline
bitfld.long 0x00 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation" "0,1,2,3"
line.long 0x04 "TBPHS,Time-Base Phase Register"
hexmask.long.word 0x04 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal"
hexmask.long.word 0x04 0.--15. 1. "Reserved,Reserved"
line.long 0x08 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
hexmask.long.word 0x08 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter"
hexmask.long.word 0x08 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value"
line.long 0x0C "CMPCTL,Counter-Compare Control Register"
rbitfld.long 0x0C 26.--31. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
bitfld.long 0x0C 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made" "0,1"
rbitfld.long 0x0C 23. "Reserved3,Reserved" "0,1"
newline
bitfld.long 0x0C 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode" "0,1"
rbitfld.long 0x0C 21. "Reserved2,Reserved" "0,1"
bitfld.long 0x0C 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode" "0,1"
bitfld.long 0x0C 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1)" "0,1,2,3"
newline
bitfld.long 0x0C 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "0,1,2,3"
hexmask.long.word 0x0C 0.--15. 1. "Reserved1,Reserved"
line.long 0x10 "CMPA,Counter-Compare A Register"
hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR)"
hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
rbitfld.long 0x14 28.--31. "Reserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
newline
bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period" "0,1,2,3"
bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero" "0,1,2,3"
hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR)"
line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is.." "0,1,2,3"
bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
newline
bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low High High Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
rbitfld.long 0x18 12.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
newline
bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period" "0,1,2,3"
newline
bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero" "0,1,2,3"
line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled" "0,1"
hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28" "0,1,2,3"
bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28" "0,1,2,3"
newline
bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28" "0,1,2,3"
hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
rbitfld.long 0x20 26.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count"
rbitfld.long 0x20 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count"
line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
rbitfld.long 0x24 28.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation" "0,1"
rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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rbitfld.long 0x28 12.--15. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3"
bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3"
line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect" "0,1"
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hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred" "0,1"
bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred" "0,1"
bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated" "0,1"
line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB" "0,1"
bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated" "0,1,2,3,4,5,6,7"
bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA" "0,1"
bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x30 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored" "0,1"
bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored" "0,1"
rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB" "0,1"
bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set" "0,1"
rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated" "0,1"
bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred" "0,1,2,3"
bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated" "0,1,2,3"
bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred" "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated" "0,1,2,3"
rbitfld.long 0x34 4.--7. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred" "0,1,2,3"
bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated" "0,1,2,3"
line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit" "0,1"
bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit" "0,1"
rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit" "0,1"
hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
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rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
line.long 0x3C "PCCTL,PWM-Chopper Control Register"
hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 1.--4. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
group.long 0x60++0x13
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
rbitfld.long 0x00 26.--31. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
rbitfld.long 0x00 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x00 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x00 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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bitfld.long 0x00 12.--15. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
hexmask.long.word 0x04 22.--31. 1. "Reserved3,Reserved"
bitfld.long 0x04 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
bitfld.long 0x04 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
bitfld.long 0x04 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
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bitfld.long 0x04 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
rbitfld.long 0x04 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x04 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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rbitfld.long 0x04 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x04 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x04 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x04 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
hexmask.long.word 0x08 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied"
hexmask.long.word 0x08 2.--15. 1. "Reserved,Reserved"
bitfld.long 0x08 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode" "0,1"
bitfld.long 0x08 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture" "0,1"
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated"
hexmask.long.word 0x0C 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter"
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1"
hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_ETPWMB (MSS ETPWMB Module Registers)"
base ad:0x3F78D00
group.long 0x00++0x3F
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
hexmask.long.word 0x00 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x00 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value" "0,1"
bitfld.long 0x00 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred" "0,1"
bitfld.long 0x00 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit" "0,1"
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bitfld.long 0x00 14.--15. "TBCTL_FREE,_SOFT,Emulation Mode Bits" "0,1,2,3"
bitfld.long 0x00 13. "TBCTL_PHSDIR,Phase Direction Bit" "0,1"
bitfld.long 0x00 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0" "0,1"
bitfld.long 0x00 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select" "0,1,2,3"
bitfld.long 0x00 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero" "0,1"
bitfld.long 0x00 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
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bitfld.long 0x00 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation" "0,1,2,3"
line.long 0x04 "TBPHS,Time-Base Phase Register"
hexmask.long.word 0x04 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal"
hexmask.long.word 0x04 0.--15. 1. "Reserved,Reserved"
line.long 0x08 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
hexmask.long.word 0x08 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter"
hexmask.long.word 0x08 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value"
line.long 0x0C "CMPCTL,Counter-Compare Control Register"
rbitfld.long 0x0C 26.--31. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
bitfld.long 0x0C 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made" "0,1"
rbitfld.long 0x0C 23. "Reserved3,Reserved" "0,1"
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bitfld.long 0x0C 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode" "0,1"
rbitfld.long 0x0C 21. "Reserved2,Reserved" "0,1"
bitfld.long 0x0C 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode" "0,1"
bitfld.long 0x0C 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1)" "0,1,2,3"
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bitfld.long 0x0C 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "0,1,2,3"
hexmask.long.word 0x0C 0.--15. 1. "Reserved1,Reserved"
line.long 0x10 "CMPA,Counter-Compare A Register"
hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR)"
hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
rbitfld.long 0x14 28.--31. "Reserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period" "0,1,2,3"
bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero" "0,1,2,3"
hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR)"
line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is.." "0,1,2,3"
bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low High High Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
rbitfld.long 0x18 12.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period" "0,1,2,3"
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bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero" "0,1,2,3"
line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled" "0,1"
hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28" "0,1,2,3"
bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28" "0,1,2,3"
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bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28" "0,1,2,3"
hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
rbitfld.long 0x20 26.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count"
rbitfld.long 0x20 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count"
line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
rbitfld.long 0x24 28.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation" "0,1"
rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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rbitfld.long 0x28 12.--15. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3"
bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3"
line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect" "0,1"
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hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred" "0,1"
bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred" "0,1"
bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated" "0,1"
line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB" "0,1"
bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated" "0,1,2,3,4,5,6,7"
bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA" "0,1"
bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x30 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored" "0,1"
bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored" "0,1"
rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB" "0,1"
bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set" "0,1"
rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated" "0,1"
bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred" "0,1,2,3"
bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated" "0,1,2,3"
bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred" "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated" "0,1,2,3"
rbitfld.long 0x34 4.--7. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred" "0,1,2,3"
bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated" "0,1,2,3"
line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit" "0,1"
bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit" "0,1"
rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit" "0,1"
hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
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rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
line.long 0x3C "PCCTL,PWM-Chopper Control Register"
hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 1.--4. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
group.long 0x60++0x13
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
rbitfld.long 0x00 26.--31. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
rbitfld.long 0x00 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x00 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x00 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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bitfld.long 0x00 12.--15. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
hexmask.long.word 0x04 22.--31. 1. "Reserved3,Reserved"
bitfld.long 0x04 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
bitfld.long 0x04 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
bitfld.long 0x04 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
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bitfld.long 0x04 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
rbitfld.long 0x04 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x04 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
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rbitfld.long 0x04 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x04 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x04 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
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bitfld.long 0x04 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
hexmask.long.word 0x08 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied"
hexmask.long.word 0x08 2.--15. 1. "Reserved,Reserved"
bitfld.long 0x08 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode" "0,1"
bitfld.long 0x08 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture" "0,1"
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated"
hexmask.long.word 0x0C 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter"
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1"
hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_ETPWMC (MSS ETPWMC Module Registers)"
base ad:0x3F78E00
group.long 0x00++0x3F
line.long 0x00 "TBCTL_TBSTS,Time-Base Control Register/ Status Register"
hexmask.long.word 0x00 19.--31. 1. "Reserved,Reserved"
bitfld.long 0x00 18. "TBSTS_CTRMAX,Time-Base Counter Max Latched Status Bit 0 Read: Indicates the time-base counter never reached its maximum value" "0,1"
bitfld.long 0x00 17. "TBSTS_SYNCI,Input Synchronization Latched Status Bit 0 Read: Indicates no external synchronization event has occurred" "0,1"
bitfld.long 0x00 16. "TBSTS_CTRDIR,Time-Base Counter Direction Status Bit" "0,1"
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bitfld.long 0x00 14.--15. "TBCTL_FREE,_SOFT,Emulation Mode Bits" "0,1,2,3"
bitfld.long 0x00 13. "TBCTL_PHSDIR,Phase Direction Bit" "0,1"
bitfld.long 0x00 10.--12. "TBCTL_CLKDIV,Time-base Clock Prescale Bits These bits determine part of the time-base clock prescale value" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 7.--9. "TBCTL_HSPCLKDIV,High Speed Time-base Clock Prescale Bits" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6. "TBCTL_SWFSYNC,Software Forced Synchronization Pulse 0 Writing a 0 has no effect and reads always return a 0" "0,1"
bitfld.long 0x00 4.--5. "TBCTL_SYNCOSEL,Synchronization Output Select" "0,1,2,3"
bitfld.long 0x00 3. "TBCTL_PRDLD,Active Period Register Load From Shadow Register Select 0 The period register (TBPRD) is loaded from its shadow register when the time-base counter TBCTR is equal to zero" "0,1"
bitfld.long 0x00 2. "TBCTL_PHSEN,Counter Register Load From Phase Register Enable 0 Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS) 1 Load the time-base counter with the phase register when an EPWMxSYNCI input signal occurs or when a.." "0,1"
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bitfld.long 0x00 0.--1. "TBCTL_CTRMODE,Counter Mode The time-base counter mode is normally configured once and not changed during normal operation" "0,1,2,3"
line.long 0x04 "TBPHS,Time-Base Phase Register"
hexmask.long.word 0x04 16.--31. 1. "TBPHS,Time-Base Phase Register These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal"
hexmask.long.word 0x04 0.--15. 1. "Reserved,Reserved"
line.long 0x08 "TBCTR_TBPRD,Time-Base Counter Register/ Period Register"
hexmask.long.word 0x08 16.--31. 1. "TBPRD,Time-Base Period Register These bits determine the period of the time-base counter"
hexmask.long.word 0x08 0.--15. 1. "TBCTR,Time-Base Counter Register Reading these bits gives the current time-base counter value"
line.long 0x0C "CMPCTL,Counter-Compare Control Register"
rbitfld.long 0x0C 26.--31. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 25. "SHDWBFULL,Counter-compare B (CMPB) Shadow Register Full Status Flag This bit self clears once a load-strobe occurs" "0,1"
bitfld.long 0x0C 24. "SHDWAFULL,Counter-compare A (CMPA) Shadow Register Full Status Flag The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made" "0,1"
rbitfld.long 0x0C 23. "Reserved3,Reserved" "0,1"
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bitfld.long 0x0C 22. "SHDWBMODE,Counter-compare B (CMPB) Register Operating Mode 0 Shadow mode" "0,1"
rbitfld.long 0x0C 21. "Reserved2,Reserved" "0,1"
bitfld.long 0x0C 20. "SHDWAMODE,Counter-compare A (CMPA) Register Operating Mode 0 Shadow mode" "0,1"
bitfld.long 0x0C 18.--19. "LOADBMODE,Active Counter-Compare B (CMPB) Load From Shadow Select Mode This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1)" "0,1,2,3"
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bitfld.long 0x0C 16.--17. "LOADAMODE,Active Counter-Compare A (CMPA) Load From Shadow Select Mode" "0,1,2,3"
hexmask.long.word 0x0C 0.--15. 1. "Reserved1,Reserved"
line.long 0x10 "CMPA,Counter-Compare A Register"
hexmask.long.word 0x10 16.--31. 1. "CMPA,Counter-Compare A Register The value in the active CMPA register is continuously compared to the time-base counter (TBCTR)"
hexmask.long.word 0x10 0.--15. 1. "Reserved,Reserved"
line.long 0x14 "CMPB_AQCTLA,Counter-Compare B Register/ Action-Qualifier Control Register for Output A (EPWMxA)"
rbitfld.long 0x14 28.--31. "Reserved,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x14 26.--27. "AQCTLA_CBD,Action when the time-base counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x14 24.--25. "AQCTLA_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 22.--23. "AQCTLA_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x14 20.--21. "AQCTLA_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x14 18.--19. "AQCTLA_PRD,Action when the counter equals the period" "0,1,2,3"
bitfld.long 0x14 16.--17. "AQCTLA_ZRO,Action when counter equals zero" "0,1,2,3"
hexmask.long.word 0x14 0.--15. 1. "CMPB,The value in the active CMPB register is continuously compared to the time-base counter (TBCTR)"
line.long 0x18 "AQCTLB_AQSFRC,Action-Qualifier Control Register for Output B (EPWMxB)/ Action-Qualifier Software Force Register"
hexmask.long.byte 0x18 24.--31. 1. "Reserved1,Reserved"
bitfld.long 0x18 22.--23. "AQSFRC_RLDCSF,AQCSFRC Active Register Reload From Shadow Options 0 Load on event counter equals zero 1h Load on event counter equals period 2h Load on event counter equals zero or counter equals period 3h Load immediately (the active register is.." "0,1,2,3"
bitfld.long 0x18 21. "AQSFRC_OTSFB,One-Time Software Forced Event on Output B 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 19.--20. "AQSFRC_ACTSFB,Action when One-Time Software Force B Is invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low -> High High -> Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
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bitfld.long 0x18 18. "AQSFRC_OTSFA,One-Time Software Forced Event on Output A 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x18 16.--17. "AQSFRC_ACTSFA,Action When One-Time Software Force A Is Invoked 0 Does nothing (action disabled) 1h Clear (low) 2h Set (high) 3h Toggle (Low High High Low) Note: This action is not qualified by counter direction (CNT_dir)" "0,1,2,3"
rbitfld.long 0x18 12.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x18 10.--11. "AQCTLB_CBD,Action when the counter equals the active CMPB register and the counter is decrementing" "0,1,2,3"
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bitfld.long 0x18 8.--9. "AQCTLB_CBU,Action when the counter equals the active CMPB register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 6.--7. "AQCTLB_CAD,Action when the counter equals the active CMPA register and the counter is decrementing" "0,1,2,3"
bitfld.long 0x18 4.--5. "AQCTLB_CAU,Action when the counter equals the active CMPA register and the counter is incrementing" "0,1,2,3"
bitfld.long 0x18 2.--3. "AQCTLB_PRD,Action when the counter equals the period" "0,1,2,3"
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bitfld.long 0x18 0.--1. "AQCTLB_ZRO,Action when counter equals zero" "0,1,2,3"
line.long 0x1C "AQCSFRC_DBCTL,Dead-Band Generator Control Register/ Action-Qualifier Continuous S/W Force Register Set"
bitfld.long 0x1C 31. "DBCTL_HALFCYCLE,Half Cycle Clocking Enable Bit: 0 Full cycle clocking enabled" "0,1"
hexmask.long.word 0x1C 22.--30. 1. "Reserved1,Reserved"
bitfld.long 0x1C 20.--21. "DBCTL_IN_MODE,Dead Band Input Mode Control Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown in Figure 35-28" "0,1,2,3"
bitfld.long 0x1C 18.--19. "DBCTL_POLSEL,Polarity Select Control Bit 3 controls the S3 switch and bit 2 controls the S2 switch shown in Figure 35-28" "0,1,2,3"
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bitfld.long 0x1C 16.--17. "DBCTL_OUT_MODE,Dead-band Output Mode Control Bit 1 controls the S1 switch and bit 0 controls the S0 switch shown in Figure 35-28" "0,1,2,3"
hexmask.long.word 0x1C 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x1C 2.--3. "AQCSFRC_CSFB,Continuous Software Force on Output B In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
bitfld.long 0x1C 0.--1. "AQCSFRC_CSFA,Continuous Software Force on Output A In immediate mode a continuous force takes effect on the next TBCLK edge" "0,1,2,3"
line.long 0x20 "DBRED_DBFED,Dead-Band Generator Rising Edge Delay Count Register/ Dead-Band Generator Falling Edge Delay Count Register"
rbitfld.long 0x20 26.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 16.--25. 1. "DBFED_DEL,Falling Edge Delay Count"
rbitfld.long 0x20 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "DBRED_DEL,Rising Edge Delay Count"
line.long 0x24 "TZSEL_TZDCSEL,Trip Zone Digital Compare Select Register/ Trip-Zone Select Register"
rbitfld.long 0x24 28.--31. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 25.--27. "TZDCSEL_DCBEVT2,Digital Compare Output B Event 2 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 22.--24. "TZDCSEL_DCBEVT1,Digital Compare Output B Event 1 Selection 0 Event disabled 1h DCBH = low DCBL = don't care 2h DCBH = high DCBL = don't care 3h DCBL = low DCBH = don't care 4h DCBL = high DCBH = don't care 5h DCBL = high DCBH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 19.--21. "TZDCSEL_DCAEVT2,Digital Compare Output A Event 2 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x24 16.--18. "TZDCSEL_DCAEVT1,Digital Compare Output A Event 1 Selection 0 Event disabled 1h DCAH = low DCAL = don't care 2h DCAH = high DCAL = don't care 3h DCAL = low DCAH = don't care 4h DCAL = high DCAH = don't care 5h DCAL = high DCAH = low 6h-7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x24 15. "TZSEL_DCBEVT1,Digital Compare Output B Event 1 Select 0 Disable DCBEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 14. "TZSEL_DCAEVT1,Digital Compare Output A Event 1 Select 0 Disable DCAEVT1 as one-shot-trip source for this ePWM module" "0,1"
bitfld.long 0x24 13. "TZSEL_OSHT6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 12. "TZSEL_OSHT5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a one-shot trip source for this ePWM module 1 Enable TZ5 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 11. "TZSEL_OSHT4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a one-shot trip source for this ePWM module 1 Enable TZ4 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 10. "TZSEL_OSHT3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a one-shot trip source for this ePWM module 1 Enable TZ3 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 9. "TZSEL_OSHT2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a one-shot trip source for this ePWM module 1 Enable TZ2 as a one-shot trip source for this ePWM module" "0,1"
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bitfld.long 0x24 8. "TZSEL_OSHT1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a one-shot trip source for this ePWM module 1 Enable TZ1 as a one-shot trip source for this ePWM module" "0,1"
bitfld.long 0x24 7. "TZSEL_DCBEVT2,Digital Compare Output B Event 2 Select 0 Disable DCBEVT2 as a CBC trip source for this ePWM module 1 Enable DCBEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 6. "TZSEL_DCAEVT2,Digital Compare Output A Event 2 Select 0 Disable DCAEVT2 as a CBC trip source for this ePWM module 1 Enable DCAEVT2 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 5. "TZSEL_CBC6,Trip-zone 6 (TZ6) Select 0 Disable TZ6 as a CBC trip source for this ePWM module 1 Enable TZ6 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 4. "TZSEL_CBC5,Trip-zone 5 (TZ5) Select 0 Disable TZ5 as a CBC trip source for this ePWM module 1 Enable TZ5 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 3. "TZSEL_CBC4,Trip-zone 4 (TZ4) Select 0 Disable TZ4 as a CBC trip source for this ePWM module 1 Enable TZ4 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 2. "TZSEL_CBC3,Trip-zone 3 (TZ3) Select 0 Disable TZ3 as a CBC trip source for this ePWM module 1 Enable TZ3 as a CBC trip source for this ePWM module" "0,1"
bitfld.long 0x24 1. "TZSEL_CBC2,Trip-zone 2 (TZ2) Select 0 Disable TZ2 as a CBC trip source for this ePWM module 1 Enable TZ2 as a CBC trip source for this ePWM module" "0,1"
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bitfld.long 0x24 0. "TZSEL_CBC1,Trip-zone 1 (TZ1) Select 0 Disable TZ1 as a CBC trip source for this ePWM module 1 Enable TZ1 as a CBC trip source for this ePWM module" "0,1"
line.long 0x28 "TZCTL_TZEINT,Trip-Zone Control Register/ Trip-Zone Enable Interrupt Register"
hexmask.long.word 0x28 23.--31. 1. "Reserved3,Reserved"
bitfld.long 0x28 22. "TZEINT_DCBEVT2,Digital Comparator Output B Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 21. "TZEINT_DCBEVT1,Digital Comparator Output B Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 20. "TZEINT_DCAEVT2,Digital Comparator Output A Event 2 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
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bitfld.long 0x28 19. "TZEINT_DCAEVT1,Digital Comparator Output A Event 1 Interrupt Enable 0 Disabled 1 Enabled" "0,1"
bitfld.long 0x28 18. "TZEINT_OST,Trip-zone One-Shot Interrupt Enable 0 Disable one-shot interrupt generation 1 Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT VIM interrupt" "0,1"
bitfld.long 0x28 17. "TZEINT_CBC,Trip-zone Cycle-by-Cycle Interrupt Enable 0 Disable cycle-by-cycle interrupt generation" "0,1"
rbitfld.long 0x28 16. "Reserved2,Reserved" "0,1"
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rbitfld.long 0x28 12.--15. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x28 10.--11. "TZCTL_DCBEVT2,Digital Compare Output B Event 2 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 8.--9. "TZCTL_DCBEVT1,Digital Compare Output B Event 1 Action On EPWMxB: 0 High-impedance (EPWMxB = High-impedance state) 1h Force EPWMxB to a high state" "0,1,2,3"
bitfld.long 0x28 6.--7. "TZCTL_DCAEVT2,Digital Compare Output A Event 2 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
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bitfld.long 0x28 4.--5. "TZCTL_DCAEVT1,Digital Compare Output A Event 1 Action On EPWMxA: 0 High-impedance (EPWMxA = High-impedance state) 1h Force EPWMxA to a high state" "0,1,2,3"
bitfld.long 0x28 2.--3. "TZCTL_TZB,When a trip event occurs the following action is taken on output EPWMxB" "0,1,2,3"
bitfld.long 0x28 0.--1. "TZCTL_TZA,When a trip event occurs the following action is taken on output EPWMxA" "0,1,2,3"
line.long 0x2C "TZFLG_TZCLR,Trip-Zone Flag Register/ Trip-Zone Clear Register"
hexmask.long.word 0x2C 23.--31. 1. "Reserved1,Reserved"
bitfld.long 0x2C 22. "TZCLR_DCBEVT2,Clear Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 21. "TZCLR_DCBEVT1,Clear Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 20. "TZCLR_DCAEVT2,Clear Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x2C 19. "TZCLR_DCAEVT1,Clear Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x2C 18. "TZCLR_OST,Clear Flag for One-Shot Trip (OST) Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 17. "TZCLR_CBC,Clear Flag for Cycle-By-Cycle (CBC) Trip Latch 0 Has no effect" "0,1"
bitfld.long 0x2C 16. "TZCLR_INT,Global Interrupt Clear Flag 0 Has no effect" "0,1"
newline
hexmask.long.word 0x2C 7.--15. 1. "Reserved2,Reserved"
bitfld.long 0x2C 6. "TZFLG_DCBEVT2,Latched Status Flag for Digital Compare Output B Event 2 0 Indicates no trip event has occurred on DCBEVT2 1 Indicates a trip event has occurred for the event defined for DCBEVT2" "0,1"
bitfld.long 0x2C 5. "TZFLG_DCBEVT1,Latched Status Flag for Digital Compare Output B Event 1 0 Indicates no trip event has occurred on DCBEVT1 1 Indicates a trip event has occurred for the event defined for DCBEVT1" "0,1"
bitfld.long 0x2C 4. "TZFLG_DCAEVT2,Latched Status Flag for Digital Compare Output A Event 2 0 Indicates no trip event has occurred on DCAEVT2 1 Indicates a trip event has occurred for the event defined for DCAEVT2" "0,1"
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bitfld.long 0x2C 3. "TZFLG_DCAEVT1,Latched Status Flag for Digital Compare Output A Event 1 0 Indicates no trip event has occurred on DCAEVT1 1 Indicates a trip event has occurred for the event defined for DCAEVT1" "0,1"
bitfld.long 0x2C 2. "TZFLG_OST,Latched Status Flag for A One-Shot Trip Event 0 No one-shot trip event has occurred" "0,1"
bitfld.long 0x2C 1. "TZFLG_CBC,Latched Status Flag for Cycle-By-Cycle Trip Event 0 No cycle-by-cycle trip event has occurred" "0,1"
bitfld.long 0x2C 0. "TZFLG_INT,Latched Trip Interrupt Status Flag 0 Indicates no interrupt has been generated" "0,1"
line.long 0x30 "TZFRC_ETSEL,Trip-Zone Force Register / Event-Trigger Selection Register"
bitfld.long 0x30 31. "ETSEL_SOCBEN,Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse 0 Disable EPWMxSOCB" "0,1"
bitfld.long 0x30 28.--30. "ETSEL_SOCBSEL,EPWMxSOCB Selection Options These bits determine when a EPWMxSOCB pulse will be generated" "0,1,2,3,4,5,6,7"
bitfld.long 0x30 27. "ETSEL_SOCAEN,Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse 0 Disable EPWMxSOCA" "0,1"
bitfld.long 0x30 24.--26. "ETSEL_SOCASEL,EPWMxSOCA Selection Options These bits determine when a EPWMxSOCA pulse will be generated" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x30 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x30 19. "ETSEL_INTEN,Enable ePWM Interrupt (EPWMx_INT) Generation 0 Disable EPWMx_INT generation 1 Enable EPWMx_INT generation" "0,1"
bitfld.long 0x30 16.--18. "ETSEL_INTSEL,ePWM Interrupt (EPWMx_INT) Selection Options 0 Reserved 1h Enable event time-base counter equal to zero" "0,1,2,3,4,5,6,7"
hexmask.long.word 0x30 7.--15. 1. "Reserved3,Reserved"
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bitfld.long 0x30 6. "TZFRC_DCBEVT2,Force Flag for Digital Compare Output B Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 5. "TZFRC_DCBEVT1,Force Flag for Digital Compare Output B Event 1 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 4. "TZFRC_DCAEVT2,Force Flag for Digital Compare Output A Event 2 0 Writing 0 has no effect" "0,1"
bitfld.long 0x30 3. "TZFRC_DCAEVT1,Force Flag for Digital Compare Output A Event 1 0 Writing 0 has no effect" "0,1"
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bitfld.long 0x30 2. "TZFRC_OST,Force a One-Shot Trip Event via Software 0 Writing of 0 is ignored" "0,1"
bitfld.long 0x30 1. "TZFRC_CBC,Force a Cycle-by-Cycle Trip Event via Software 0 Writing of 0 is ignored" "0,1"
rbitfld.long 0x30 0. "Reserved2,Reserved" "0,1"
line.long 0x34 "ETPS_ETFLG,Event-Trigger Pre-Scale Register/ Event-Trigger Flag Register"
hexmask.long.word 0x34 20.--31. 1. "Reserved2,Reserved"
bitfld.long 0x34 19. "ETFLG_SOCB,Latched ePWM ADC Start-of-Conversion B (EPWMxSOCB) Status Flag 0 Indicates no EPWMxSOCB event occurred 1 Indicates that a start of conversion pulse was generated on EPWMxSOCB" "0,1"
bitfld.long 0x34 18. "ETFLG_SOCA,Latched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag Unlike the ETFLG[INT] flag the EPWMxSOCA output will continue to pulse even if the flag bit is set" "0,1"
rbitfld.long 0x34 17. "Reserved1,Reserved" "0,1"
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bitfld.long 0x34 16. "ETFLG_INT,Latched ePWM Interrupt (EPWMx_INT) Status Flag 0 Indicates no event occurred 1 Indicates that an ePWMx interrupt (EWPMx_INT) was generated" "0,1"
bitfld.long 0x34 14.--15. "ETPS_SOCBCNT,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register These bits indicate how many selected ETSEL[SOCBSEL] events have occurred: 0 No events have occurred" "0,1,2,3"
bitfld.long 0x34 12.--13. "ETPS_SOCBPRD,ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated" "0,1,2,3"
bitfld.long 0x34 10.--11. "ETPS_SOCACNT,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register These bits indicate how many selected ETSEL[SOCASEL] events have occurred: 0 No events have occurred" "0,1,2,3"
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bitfld.long 0x34 8.--9. "ETPS_SOCAPRD,ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated" "0,1,2,3"
rbitfld.long 0x34 4.--7. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x34 2.--3. "ETPS_INTCNT,ePWM Interrupt Event (EPWMx_INT) Counter Register These bits indicate how many selected ETSEL[INTSEL] events have occurred" "0,1,2,3"
bitfld.long 0x34 0.--1. "ETPS_INTPRD,ePWM Interrupt (EPWMx_INT) Period Select These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated" "0,1,2,3"
line.long 0x38 "ETCLR_ETFRC,Event-Trigger Clear Register/ Event-Trigger Force Register"
hexmask.long.word 0x38 20.--31. 1. "Reserved4,Reserved"
bitfld.long 0x38 19. "ETFRC_SOCB,SOCB Force Bit" "0,1"
bitfld.long 0x38 18. "ETFRC_SOCA,SOCA Force Bit" "0,1"
rbitfld.long 0x38 17. "Reserved3,Reserved" "0,1"
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bitfld.long 0x38 16. "ETFRC_INT,INT Force Bit" "0,1"
hexmask.long.word 0x38 4.--15. 1. "Reserved2,Reserved"
bitfld.long 0x38 3. "ETCLR_SOCB,ePWM ADC Start-of-Conversion B (EPWMxSOCB) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
bitfld.long 0x38 2. "ETCLR_SOCA,ePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
newline
rbitfld.long 0x38 1. "Reserved1,Reserved" "0,1"
bitfld.long 0x38 0. "ETCLR_INT,ePWM Interrupt (EPWMx_INT) Flag Clear Bit 0 Writing a 0 has no effect" "0,1"
line.long 0x3C "PCCTL,PWM-Chopper Control Register"
hexmask.long.tbyte 0x3C 11.--31. 1. "Reserved,Reserved"
bitfld.long 0x3C 8.--10. "CHPDUTY,Chopping Clock Duty Cycle 0 Duty = 1/8 (12.5%) 1h Duty = 2/8 (25.0%) 2h Duty = 3/8 (37.5%) 3h Duty = 4/8 (50.0%) 4h Duty = 5/8 (62.5%) 5h Duty = 6/8 (75.0%) 6h Duty = 7/8 (87.5%) 7h Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 5.--7. "CHPFREQ,Chopping Clock Frequency 0 Divide by 1 (no prescale = 12.5 MHz at 100 MHz VCLK3) 1h Divide by 2 (6.25 MHz at 100 MHz VCLK3) 2h Divide by 3 (4.16 MHz at 100 MHz VCLK3) 3h Divide by 4 (3.12 MHz at 100 MHz VCLK3) 4h Divide by 5 (2.50 MHz at 100 MHz.." "0,1,2,3,4,5,6,7"
bitfld.long 0x3C 1.--4. "OSHTWTH,One-Shot Pulse Width 0 1 x VCLK3 / 8 wide ( = 80 nS at 100 MHz VCLK3) 1h 2 x VCLK3 / 8 wide ( = 160 nS at 100 MHz VCLK3) 2h 3 x VCLK3 / 8 wide ( = 240 nS at 100 MHz VCLK3) 3h 4 x VCLK3 / 8 wide ( = 320 nS at 100 MHz VCLK3) 4h 5 x VCLK3 / 8 wide.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x3C 0. "CHPEN,PWM-chopping Enable 0 Disable (bypass) PWM chopping function 1 Enable chopping function" "0,1"
group.long 0x60++0x13
line.long 0x00 "DCTRIPSEL_DCACTL,Digital Compare Trip Select Register/ Digital Compare A Control Register"
rbitfld.long 0x00 26.--31. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 25. "DCACTL_EVT2FRC_SYNCSEL,DCAEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 24. "DCACTL_EVT2SRCSEL,DCAEVT2 Source Signal Select 0 Source Is DCAEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
rbitfld.long 0x00 20.--23. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 19. "DCACTL_EVT1SYNCE,DCAEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x00 18. "DCACTL_EVT1SOCE,DCAEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x00 17. "DCACTL_EVT1FRC_SYNCSEL,DCAEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x00 16. "DCACTL_EVT1SRCSEL,DCAEVT1 Source Signal Select 0 Source Is DCAEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
newline
bitfld.long 0x00 12.--15. "DCTRIPSEL_DCBLCOMPSEL,Digital Compare B Low Input Select Defines the source for the DCBL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "DCTRIPSEL_DCBHCOMPSEL,Digital Compare B High Input Select Defines the source for the DCBH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 4.--7. "DCTRIPSEL_DCALCOMPSEL,Digital Compare A Low Input Select Defines the source for the DCAL input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "DCTRIPSEL_DCAHCOMPSEL,Digital Compare A High Input Select Defines the source for the DCAH input" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "DCBCTL_DCFCTL,Digital Compare B Control Register/ Digital Compare Filter Control Register"
hexmask.long.word 0x04 22.--31. 1. "Reserved3,Reserved"
bitfld.long 0x04 20.--21. "DCFCTL_PULSESEL,Pulse Select For Blanking & Capture Alignment 0 Time-base counter equal to period (TBCTR = TBPRD) 1h Time-base counter equal to zero (TBCTR = 0x0000) 2h-3h Reserved" "0,1,2,3"
bitfld.long 0x04 19. "DCFCTL_BLANKINV,Blanking Window Inversion 0 Blanking window not inverted 1 Blanking window inverted" "0,1"
bitfld.long 0x04 18. "DCFCTL_BLANKE,Blanking Window Enable/Disable 0 Blanking window is disabled 1 Blanking window is enabled" "0,1"
newline
bitfld.long 0x04 16.--17. "DCFCTL_SRCSEL,Filter Block Signal Source Select 0 Source Is DCAEVT1 Signal 1h Source Is DCAEVT2 Signal 2h Source Is DCBEVT1 Signal 3h Source Is DCBEVT2 Signal" "0,1,2,3"
rbitfld.long 0x04 10.--15. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 9. "DCBCTL_EVT2FRC_SYNCSEL,DCBEVT2 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
bitfld.long 0x04 8. "DCBCTL_EVT2SRCSEL,DCBEVT2 Source Signal Select 0 Source Is DCBEVT2 Signal 1 Source Is DCEVTFILT Signal" "0,1"
newline
rbitfld.long 0x04 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 3. "DCBCTL_EVT1SYNCE,DCBEVT1 SYNC Enable/Disable 0 SYNC Generation Disabled 1 SYNC Generation Enabled" "0,1"
bitfld.long 0x04 2. "DCBCTL_EVT1SOCE,DCBEVT1 SOC Enable/Disable 0 SOC Generation Disabled 1 SOC Generation Enabled" "0,1"
bitfld.long 0x04 1. "DCBCTL_EVT1FRC_SYNCSEL,DCBEVT1 Force Synchronization Signal Select 0 Source Is Synchronous Signal 1 Source Is Asynchronous Signal" "0,1"
newline
bitfld.long 0x04 0. "DCBCTL_EVT1SRCSEL,DCBEVT1 Source Signal Select 0 Source Is DCBEVT1 Signal 1 Source Is DCEVTFILT Signal" "0,1"
line.long 0x08 "DCCAPCTL_DCFOFFSET,Digital Compare Capture Control Register/ Digital Compare Filter Offset Register"
hexmask.long.word 0x08 16.--31. 1. "DCFOFFSET_OFFSET,Blanking Window Offset These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied"
hexmask.long.word 0x08 2.--15. 1. "Reserved,Reserved"
bitfld.long 0x08 1. "DCCAPCTL_SHDWMODE,TBCTR Counter Capture Shadow Select Mode 0 Enable shadow mode" "0,1"
bitfld.long 0x08 0. "DCCAPCTL_CAPE,TBCTR Counter Capture Enable/Disable 0 Disable the time-base counter capture" "0,1"
line.long 0x0C "DCFOFFSETCNT_DCFWINDOW,Digital Compare Filter Offset Counter Register/ Digital Compare Filter Window Register"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x0C 16.--23. 1. "DCFWINDOW_WINDOW,Blanking Window Width 0 No blanking window is generated"
hexmask.long.word 0x0C 0.--15. 1. "DCFOFFSETCNT_OFFSETCNT,Blanking Offset Counter These 16-bits are read only and indicate the current value of the offset counter"
line.long 0x10 "DCFWINDOWCNT_DCCAP,Digital Compare Filter Window Counter Register/ Digital Compare Counter Capture Register"
hexmask.long.word 0x10 16.--31. 1. "DCCAP,Digital Compare Time-Base Counter Capture To enable time-base counter capture set the DCCAPCLT[CAPE] bit to 1"
hexmask.long.byte 0x10 8.--15. 1. "Reserved1,Reserved"
hexmask.long.byte 0x10 0.--7. 1. "DCFWINDOWCNT,0-FFh Blanking Window Counter These 8 bits are read only and indicate the current value of the window counter"
repeat 8. (list 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x40)++0x03
line.long 0x00 "Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_GIO (MSS GIO Module Registers)"
base ad:0x2F7B400
group.long 0x00++0x03
line.long 0x00 "GIOGCR,GIO reset"
hexmask.long 0x00 1.--31. 1. "NU0,Reserved"
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "GIOPWDN,GIO power down mode register"
bitfld.long 0x00 0. "GIOPWDN,Writing to the GIOPWDN bit is only allowed in privilege mode" "Normal operation; clocks enabled to GIO..,Power-down mode"
group.long 0x08++0x14B
line.long 0x00 "GIOINTDET,Interrupt detection select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x00 24.--31. 1. "GIOINTDET_3,Interrupt detection select for pins GIOD[7:0]"
hexmask.long.byte 0x00 16.--23. 1. "GIOINTDET_2,Interrupt detection select for pins GIOC[7:0]"
hexmask.long.byte 0x00 8.--15. 1. "GIOINTDET_1,Interrupt detection select for pins GIOB[7:0]"
hexmask.long.byte 0x00 0.--7. 1. "GIOINTDET_0,Interrupt detection select for pins GIOA[7:0]"
line.long 0x04 "GIOPOL,Interrupt polarity select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x04 24.--31. 1. "GIOPOL_3,Interrupt polarity select for pins GIOD[7:0]"
hexmask.long.byte 0x04 16.--23. 1. "GIOPOL_2,Interrupt polarity select for pins GIOC[7:0]"
hexmask.long.byte 0x04 8.--15. 1. "GIOPOL_1,Interrupt polarity select for pins GIOB[7:0]"
hexmask.long.byte 0x04 0.--7. 1. "GIOPOL_0,Interrupt polarity select for pins GIOA[7:0]"
line.long 0x08 "GIOENASET,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x08 24.--31. 1. "GIOENASET_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x08 16.--23. 1. "GIOENASET_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x08 8.--15. 1. "GIOENASET_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x08 0.--7. 1. "GIOENASET_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x0C "GIOENACLR,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x0C 24.--31. 1. "GIOENACLR_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x0C 16.--23. 1. "GIOENACLR_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x0C 8.--15. 1. "GIOENACLR_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x0C 0.--7. 1. "GIOENACLR_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x10 "GIOLVLSET,GIO high priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x10 24.--31. 1. "GIOLVLSET_3,GIO high priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x10 16.--23. 1. "GIOLVLSET_2,GIO high priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x10 8.--15. 1. "GIOLVLSET_1,GIO high priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x10 0.--7. 1. "GIOLVLSET_0,GIO high priority interrupt for pins GIOA[7:0]"
line.long 0x14 "GIOLVLCLR,GIO low priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x14 24.--31. 1. "GIOLVLCLR_3,GIO low priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x14 16.--23. 1. "GIOLVLCLR_2,GIO low priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x14 8.--15. 1. "GIOLVLCLR_1,GIO low priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x14 0.--7. 1. "GIOLVLCLR_0,GIO low priority interrupt for pins GIOA[7:0]"
line.long 0x18 "GIOFLG,GIO flag for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x18 24.--31. 1. "GIOFLG_3,GIO flag for pins GIOD[7:0]"
hexmask.long.byte 0x18 16.--23. 1. "GIOFLG_2,GIO flag for pins GIOC[7:0]"
hexmask.long.byte 0x18 8.--15. 1. "GIOFLG_1,GIO flag for pins GIOB[7:0]"
hexmask.long.byte 0x18 0.--7. 1. "GIOFLG_0,GIO flag for pins GIOA[7:0]"
line.long 0x1C "GIOOFFA,Index bits for currently pending high-priority interrupt Register A"
hexmask.long 0x1C 6.--31. 1. "NU1,Reserved"
bitfld.long 0x1C 0.--5. "GIOOFFA,Index bits for currently pending high-priority interrupt Register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "GIOOFFB,Index bits for currently pending high-priority interrupt Register B"
hexmask.long 0x20 6.--31. 1. "NU2,Reserved"
bitfld.long 0x20 0.--5. "GIOOFFB,Index bits for currently pending high-priority interrupt Register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "GIOEMUA,GIO emulation register A"
hexmask.long 0x24 6.--31. 1. "NU3,Reserved"
bitfld.long 0x24 0.--5. "GIOEMUA,GIO emulation register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "GIOEMUB,GIO emulation register B"
hexmask.long 0x28 6.--31. 1. "NU4,Reserved"
bitfld.long 0x28 0.--5. "GIOEMUB,GIO emulation register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "GIODIRA,GIO data direction of pins in Port A"
hexmask.long.tbyte 0x2C 8.--31. 1. "NU5,Reserved"
hexmask.long.byte 0x2C 0.--7. 1. "GIODIRA,GIO data direction of pins in Port A"
line.long 0x30 "GIODINA,GIO data input for pins in port A"
hexmask.long.tbyte 0x30 8.--31. 1. "NU11,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "GIODINA,GIO data input for pins in port A"
line.long 0x34 "GIODOUTA,GIO data output for pins in port A"
hexmask.long.tbyte 0x34 8.--31. 1. "NU17,Reserved"
hexmask.long.byte 0x34 0.--7. 1. "GIODOUTA,GIO data output for pins in port A"
line.long 0x38 "GIOSETA,GIO data set for port A"
hexmask.long.tbyte 0x38 8.--31. 1. "NU23,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "GIODSETA,GIO data set for port A"
line.long 0x3C "GIOCLRA,GIO data clear for port A"
hexmask.long.tbyte 0x3C 8.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x3C 0.--7. 1. "GIODCLRA,GIO data clear for port A"
line.long 0x40 "GIOPDRA,GIO open drain for port A"
hexmask.long.tbyte 0x40 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x40 0.--7. 1. "GIOPDRA,GIO open drain for port A"
line.long 0x44 "GIOPULDISA,GIO pul disable for port A"
hexmask.long.tbyte 0x44 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x44 0.--7. 1. "GIOPULDISA,GIO pull disable for port A"
line.long 0x48 "GIOPSLA,GIO pul select for port A"
hexmask.long.tbyte 0x48 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x48 0.--7. 1. "GIOPSLA,GIO pull select for port A"
line.long 0x4C "GIODIRB,GIO data direction of pins in Port B"
hexmask.long.tbyte 0x4C 8.--31. 1. "NU6,Reserved"
hexmask.long.byte 0x4C 0.--7. 1. "GIODIRB,GIO data direction of pins in Port B"
line.long 0x50 "GIODINB,GIO data input for pins in port B"
hexmask.long.tbyte 0x50 8.--31. 1. "NU12,Reserved"
hexmask.long.byte 0x50 0.--7. 1. "GIODINB,GIO data input for pins in port B"
line.long 0x54 "GIODOUTB,GIO data output for pins in port B"
hexmask.long.tbyte 0x54 8.--31. 1. "NU18,Reserved"
hexmask.long.byte 0x54 0.--7. 1. "GIODOUTB,GIO data output for pins in port B"
line.long 0x58 "GIOSETB,GIO data set for port B"
hexmask.long.tbyte 0x58 8.--31. 1. "NU24,Reserved"
hexmask.long.byte 0x58 0.--7. 1. "GIODSETB,GIO data set for port B"
line.long 0x5C "GIOCLRB,GIO data clear for port B"
hexmask.long.tbyte 0x5C 8.--31. 1. "NU30,Reserved"
hexmask.long.byte 0x5C 0.--7. 1. "GIODCLRB,GIO data clear for port B"
line.long 0x60 "GIOPDRB,GIO open drain for port B"
hexmask.long.tbyte 0x60 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x60 0.--7. 1. "GIOPDRB,GIO open drain for port B"
line.long 0x64 "GIOPULDISB,GIO pul disable for port B"
hexmask.long.tbyte 0x64 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x64 0.--7. 1. "GIOPULDISB,GIO pull disable for port B"
line.long 0x68 "GIOPSLB,GIO pul select for port B"
hexmask.long.tbyte 0x68 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x68 0.--7. 1. "GIOPSLB,GIO pull select for port B"
line.long 0x6C "GIODIRC,GIO data direction of pins in Port C"
hexmask.long.tbyte 0x6C 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x6C 0.--7. 1. "GIODIRC,GIO data direction of pins in Port C"
line.long 0x70 "GIODINC,GIO data input for pins in port C"
hexmask.long.tbyte 0x70 8.--31. 1. "NU13,Reserved"
hexmask.long.byte 0x70 0.--7. 1. "GIODINC,GIO data input for pins in port C"
line.long 0x74 "GIODOUTC,GIO data output for pins in port C"
hexmask.long.tbyte 0x74 8.--31. 1. "NU19,Reserved"
hexmask.long.byte 0x74 0.--7. 1. "GIODOUTC,GIO data output for pins in port C"
line.long 0x78 "GIOSETC,GIO data set for port C"
hexmask.long.tbyte 0x78 8.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x78 0.--7. 1. "GIODSETC,GIO data set for port C"
line.long 0x7C "GIOCLRC,GIO data clear for port C"
hexmask.long.tbyte 0x7C 8.--31. 1. "NU31,Reserved"
hexmask.long.byte 0x7C 0.--7. 1. "GIODCLRC,GIO data clear for port C"
line.long 0x80 "GIOPDRC,GIO open drain for port C"
hexmask.long.tbyte 0x80 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x80 0.--7. 1. "GIOPDRC,GIO open drain for port C"
line.long 0x84 "GIOPULDISC,GIO pul disable for port C"
hexmask.long.tbyte 0x84 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x84 0.--7. 1. "GIOPULDISC,GIO pull disable for port C"
line.long 0x88 "GIOPSLC,GIO pul select for port C"
hexmask.long.tbyte 0x88 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x88 0.--7. 1. "GIOPSLC,GIO pull select for port C"
line.long 0x8C "GIODIRD,GIO data direction of pins in Port D"
hexmask.long.tbyte 0x8C 8.--31. 1. "NU8,Reserved"
hexmask.long.byte 0x8C 0.--7. 1. "GIODIRD,GIO data direction of pins in Port D"
line.long 0x90 "GIODIND,GIO data input for pins in port D"
hexmask.long.tbyte 0x90 8.--31. 1. "NU14,Reserved"
hexmask.long.byte 0x90 0.--7. 1. "GIODIND,GIO data input for pins in port D"
line.long 0x94 "GIODOUTD,GIO data output for pins in port D"
hexmask.long.tbyte 0x94 8.--31. 1. "NU20,Reserved"
hexmask.long.byte 0x94 0.--7. 1. "GIODOUTD,GIO data output for pins in port D"
line.long 0x98 "GIOSETD,GIO data set for port D"
hexmask.long.tbyte 0x98 8.--31. 1. "NU26,Reserved"
hexmask.long.byte 0x98 0.--7. 1. "GIODSETD,GIO data set for port D"
line.long 0x9C "GIOCLRD,GIO data clear for port D"
hexmask.long.tbyte 0x9C 8.--31. 1. "NU32,Reserved"
hexmask.long.byte 0x9C 0.--7. 1. "GIODCLRD,GIO data clear for port D"
line.long 0xA0 "GIOPDRD,GIO open drain for port D"
hexmask.long.tbyte 0xA0 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA0 0.--7. 1. "GIOPDRD,GIO open drain for port D"
line.long 0xA4 "GIOPULDISD,GIO pul disable for port D"
hexmask.long.tbyte 0xA4 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA4 0.--7. 1. "GIOPULDISD,GIO pull disable for port D"
line.long 0xA8 "GIOPSLD,GIO pul select for port D"
hexmask.long.tbyte 0xA8 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA8 0.--7. 1. "GIOPSLD,GIO pull select for port D"
line.long 0xAC "GIODIRE,GIO data direction of pins in Port E"
hexmask.long.tbyte 0xAC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xAC 0.--7. 1. "GIODIRE,GIO data direction of pins in Port E"
line.long 0xB0 "GIODINE,GIO data input for pins in port E"
hexmask.long.tbyte 0xB0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xB0 0.--7. 1. "GIODINE,GIO data input for pins in port E"
line.long 0xB4 "GIODOUTE,GIO data output for pins in port E"
hexmask.long.tbyte 0xB4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xB4 0.--7. 1. "GIODOUTE,GIO data output for pins in port E"
line.long 0xB8 "GIOSETE,GIO data set for port E"
hexmask.long.tbyte 0xB8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xB8 0.--7. 1. "GIODSETE,GIO data set for port E"
line.long 0xBC "GIOCLRE,GIO data clear for port E"
hexmask.long.tbyte 0xBC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xBC 0.--7. 1. "GIODCLRE,GIO data clear for port E"
line.long 0xC0 "GIOPDRE,GIO open drain for port E"
hexmask.long.tbyte 0xC0 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC0 0.--7. 1. "GIOPDRE,GIO open drain for port E"
line.long 0xC4 "GIOPULDISE,GIO pul disable for port E"
hexmask.long.tbyte 0xC4 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC4 0.--7. 1. "GIOPULDISE,GIO pull disable for port E"
line.long 0xC8 "GIOPSLE,GIO pul select for port E"
hexmask.long.tbyte 0xC8 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC8 0.--7. 1. "GIOPSLE,GIO pull select for port E"
line.long 0xCC "GIODIRF,GIO data direction of pins in Port F"
hexmask.long.tbyte 0xCC 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0xCC 0.--7. 1. "GIODIRF,GIO data direction of pins in Port F"
line.long 0xD0 "GIODINF,GIO data input for pins in Port F"
hexmask.long.tbyte 0xD0 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0xD0 0.--7. 1. "GIODINF,GIO data input for pins in port F"
line.long 0xD4 "GIODOUTF,GIO data output for pins in Port F"
hexmask.long.tbyte 0xD4 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0xD4 0.--7. 1. "GIODOUTF,GIO data output for pins in port F"
line.long 0xD8 "GIOSETF,GIO data set for Port F"
hexmask.long.tbyte 0xD8 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0xD8 0.--7. 1. "GIODSETF,GIO data set for port F"
line.long 0xDC "GIOCLRF,GIO data clear for Port F"
hexmask.long.tbyte 0xDC 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0xDC 0.--7. 1. "GIODCLRF,GIO data clear for port F"
line.long 0xE0 "GIOPDRF,GIO open drain for Port F"
hexmask.long.tbyte 0xE0 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE0 0.--7. 1. "GIOPDRF,GIO open drain for port F"
line.long 0xE4 "GIOPULDISF,GIO pul disable for port F"
hexmask.long.tbyte 0xE4 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE4 0.--7. 1. "GIOPULDISF,GIO pull disable for port F"
line.long 0xE8 "GIOPSLF,GIO pul select for port F"
hexmask.long.tbyte 0xE8 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE8 0.--7. 1. "GIOPSLF,GIO pull select for port F"
line.long 0xEC "GIODIRG,GIO data direction of pins in Port G"
hexmask.long.tbyte 0xEC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xEC 0.--7. 1. "GIODIRG,GIO data direction of pins in Port G"
line.long 0xF0 "GIODING,GIO data input for pins in port G"
hexmask.long.tbyte 0xF0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xF0 0.--7. 1. "GIODING,GIO data input for pins in port G"
line.long 0xF4 "GIODOUTG,GIO data output for pins in port G"
hexmask.long.tbyte 0xF4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xF4 0.--7. 1. "GIODOUTG,GIO data output for pins in port G"
line.long 0xF8 "GIOSETG,GIO data set for port G"
hexmask.long.tbyte 0xF8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xF8 0.--7. 1. "GIODSETG,GIO data set for port G"
line.long 0xFC "GIOCLRG,GIO data clear for port G"
hexmask.long.tbyte 0xFC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xFC 0.--7. 1. "GIODCLRG,GIO data clear for port G"
line.long 0x100 "GIOPDRG,GIO open drain for port G"
hexmask.long.tbyte 0x100 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x100 0.--7. 1. "GIOPDRG,GIO open drain for port G"
line.long 0x104 "GIOPULDISG,GIO pul disable for port G"
hexmask.long.tbyte 0x104 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x104 0.--7. 1. "GIOPULDISG,GIO pull disable for port G"
line.long 0x108 "GIOPSLG,GIO pul select for port G"
hexmask.long.tbyte 0x108 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x108 0.--7. 1. "GIOPSLG,GIO pull select for port G"
line.long 0x10C "GIODIRH,GIO data direction of pins in Port H"
hexmask.long.tbyte 0x10C 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0x10C 0.--7. 1. "GIODIRH,GIO data direction of pins in Port H"
line.long 0x110 "GIODINH,GIO data input for pins in Port H"
hexmask.long.tbyte 0x110 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x110 0.--7. 1. "GIODINH,GIO data input for pins in port H"
line.long 0x114 "GIODOUTH,GIO data output for pins in Port H"
hexmask.long.tbyte 0x114 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0x114 0.--7. 1. "GIODOUTH,GIO data output for pins in port H"
line.long 0x118 "GIOSETH,GIO data set for Port H"
hexmask.long.tbyte 0x118 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0x118 0.--7. 1. "GIODSETH,GIO data set for port H"
line.long 0x11C "GIOCLRH,GIO data clear for Port H"
hexmask.long.tbyte 0x11C 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0x11C 0.--7. 1. "GIODCLRH,GIO data clear for port H"
line.long 0x120 "GIOPDRH,GIO open drain for Port H"
hexmask.long.tbyte 0x120 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x120 0.--7. 1. "GIOPDRH,GIO open drain for port H"
line.long 0x124 "GIOPULDISH,GIO pul disable for port H"
hexmask.long.tbyte 0x124 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x124 0.--7. 1. "GIOPULDISH,GIO pull disable for port H"
line.long 0x128 "GIOPSLH,GIO pul select for port H"
hexmask.long.tbyte 0x128 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x128 0.--7. 1. "GIOPSLH,GIO pull select for port H"
line.long 0x12C "GIOSRCA,GIO slew rate select for port A"
hexmask.long.tbyte 0x12C 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x12C 0.--7. 1. "GIOSRCA,GIO slew rate control for port A"
line.long 0x130 "GIOSRCB,GIO slew rate select for port B"
hexmask.long.tbyte 0x130 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x130 0.--7. 1. "GIOSRCB,GIO slew rate control for port B"
line.long 0x134 "GIOSRCC,GIO slew rate select for port C"
hexmask.long.tbyte 0x134 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x134 0.--7. 1. "GIOSRCC,GIO slew rate control for port C"
line.long 0x138 "GIOSRCD,GIO slew rate select for port D"
hexmask.long.tbyte 0x138 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x138 0.--7. 1. "GIOSRCD,GIO slew rate control for port D"
line.long 0x13C "GIOSRCE,GIO slew rate select for port E"
hexmask.long.tbyte 0x13C 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x13C 0.--7. 1. "GIOSRCE,GIO slew rate control for port E"
line.long 0x140 "GIOSRCF,GIO slew rate select for port F"
hexmask.long.tbyte 0x140 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x140 0.--7. 1. "GIOSRCF,GIO slew rate control for port F"
line.long 0x144 "GIOSRCG,GIO slew rate select for port G"
hexmask.long.tbyte 0x144 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x144 0.--7. 1. "GIOSRCG,GIO slew rate control for port G"
line.long 0x148 "GIOSRCH,GIO slew rate select for port H"
hexmask.long.tbyte 0x148 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x148 0.--7. 1. "GIOSRCH,GIO slew rate control for port H"
width 0x0B
tree.end
tree "MSS_GPADC_DATA_RAM (MSS GPADC DATA RAM Module Registers)"
base ad:0xC5030000
group.long 0x00++0x03
line.long 0x00 "START,"
group.long 0x7FC++0x03
line.long 0x00 "END,"
width 0x0B
tree.end
tree "MSS_GPADC_PKT_RAM (MSS GPADC PKT RAM Module Registers)"
base ad:0x30C0000
group.long 0x00++0x7FF
line.long 0x00 "INST0_0,"
line.long 0x04 "INST0_1,"
hexmask.long.byte 0x04 25.--31. 1. "NU2,"
rbitfld.long 0x04 24. "NU1," "0,1"
bitfld.long 0x04 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x04 16.--22. 1. "SKIP_SAMPLES,Number of GPADC clock cycles to skip before collecting valid samples"
hexmask.long.byte 0x04 8.--15. 1. "COLLECT_SAMPLES,Number of GPADC samples to collect"
hexmask.long.byte 0x04 0.--7. 1. "PARAM,Parameter(input to one hot encoding) to be passed to analog"
line.long 0x08 "INST1_0,"
line.long 0x0C "INST1_1,"
hexmask.long.byte 0x0C 25.--31. 1. "NU2,"
rbitfld.long 0x0C 24. "NU1," "0,1"
bitfld.long 0x0C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x0C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x0C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x0C 0.--7. 1. "PARAM,"
line.long 0x10 "INST2_0,"
line.long 0x14 "INST2_1,"
hexmask.long.byte 0x14 25.--31. 1. "NU2,"
rbitfld.long 0x14 24. "NU1," "0,1"
bitfld.long 0x14 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x14 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x14 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x14 0.--7. 1. "PARAM,"
line.long 0x18 "INST3_0,"
line.long 0x1C "INST3_1,"
hexmask.long.byte 0x1C 25.--31. 1. "NU2,"
rbitfld.long 0x1C 24. "NU1," "0,1"
bitfld.long 0x1C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1C 0.--7. 1. "PARAM,"
line.long 0x20 "INST4_0,"
line.long 0x24 "INST4_1,"
hexmask.long.byte 0x24 25.--31. 1. "NU2,"
rbitfld.long 0x24 24. "NU1," "0,1"
bitfld.long 0x24 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x24 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x24 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x24 0.--7. 1. "PARAM,"
line.long 0x28 "INST5_0,"
line.long 0x2C "INST5_1,"
hexmask.long.byte 0x2C 25.--31. 1. "NU2,"
rbitfld.long 0x2C 24. "NU1," "0,1"
bitfld.long 0x2C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2C 0.--7. 1. "PARAM,"
line.long 0x30 "INST6_0,"
line.long 0x34 "INST6_1,"
hexmask.long.byte 0x34 25.--31. 1. "NU2,"
rbitfld.long 0x34 24. "NU1," "0,1"
bitfld.long 0x34 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x34 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x34 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x34 0.--7. 1. "PARAM,"
line.long 0x38 "INST7_0,"
line.long 0x3C "INST7_1,"
hexmask.long.byte 0x3C 25.--31. 1. "NU2,"
rbitfld.long 0x3C 24. "NU1," "0,1"
bitfld.long 0x3C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3C 0.--7. 1. "PARAM,"
line.long 0x40 "INST8_0,"
line.long 0x44 "INST8_1,"
hexmask.long.byte 0x44 25.--31. 1. "NU2,"
rbitfld.long 0x44 24. "NU1," "0,1"
bitfld.long 0x44 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x44 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x44 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x44 0.--7. 1. "PARAM,"
line.long 0x48 "INST9_0,"
line.long 0x4C "INST9_1,"
hexmask.long.byte 0x4C 25.--31. 1. "NU2,"
rbitfld.long 0x4C 24. "NU1," "0,1"
bitfld.long 0x4C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4C 0.--7. 1. "PARAM,"
line.long 0x50 "INST10_0,"
line.long 0x54 "INST10_1,"
hexmask.long.byte 0x54 25.--31. 1. "NU2,"
rbitfld.long 0x54 24. "NU1," "0,1"
bitfld.long 0x54 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x54 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x54 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x54 0.--7. 1. "PARAM,"
line.long 0x58 "INST11_0,"
line.long 0x5C "INST11_1,"
hexmask.long.byte 0x5C 25.--31. 1. "NU2,"
rbitfld.long 0x5C 24. "NU1," "0,1"
bitfld.long 0x5C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5C 0.--7. 1. "PARAM,"
line.long 0x60 "INST12_0,"
line.long 0x64 "INST12_1,"
hexmask.long.byte 0x64 25.--31. 1. "NU2,"
rbitfld.long 0x64 24. "NU1," "0,1"
bitfld.long 0x64 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x64 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x64 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x64 0.--7. 1. "PARAM,"
line.long 0x68 "INST13_0,"
line.long 0x6C "INST13_1,"
hexmask.long.byte 0x6C 25.--31. 1. "NU2,"
rbitfld.long 0x6C 24. "NU1," "0,1"
bitfld.long 0x6C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6C 0.--7. 1. "PARAM,"
line.long 0x70 "INST14_0,"
line.long 0x74 "INST14_1,"
hexmask.long.byte 0x74 25.--31. 1. "NU2,"
rbitfld.long 0x74 24. "NU1," "0,1"
bitfld.long 0x74 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x74 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x74 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x74 0.--7. 1. "PARAM,"
line.long 0x78 "INST15_0,"
line.long 0x7C "INST15_1,"
hexmask.long.byte 0x7C 25.--31. 1. "NU2,"
rbitfld.long 0x7C 24. "NU1," "0,1"
bitfld.long 0x7C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7C 0.--7. 1. "PARAM,"
line.long 0x80 "INST16_0,"
line.long 0x84 "INST16_1,"
hexmask.long.byte 0x84 25.--31. 1. "NU2,"
rbitfld.long 0x84 24. "NU1," "0,1"
bitfld.long 0x84 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x84 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x84 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x84 0.--7. 1. "PARAM,"
line.long 0x88 "INST17_0,"
line.long 0x8C "INST17_1,"
hexmask.long.byte 0x8C 25.--31. 1. "NU2,"
rbitfld.long 0x8C 24. "NU1," "0,1"
bitfld.long 0x8C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x8C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x8C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x8C 0.--7. 1. "PARAM,"
line.long 0x90 "INST18_0,"
line.long 0x94 "INST18_1,"
hexmask.long.byte 0x94 25.--31. 1. "NU2,"
rbitfld.long 0x94 24. "NU1," "0,1"
bitfld.long 0x94 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x94 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x94 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x94 0.--7. 1. "PARAM,"
line.long 0x98 "INST19_0,"
line.long 0x9C "INST19_1,"
hexmask.long.byte 0x9C 25.--31. 1. "NU2,"
rbitfld.long 0x9C 24. "NU1," "0,1"
bitfld.long 0x9C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x9C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x9C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x9C 0.--7. 1. "PARAM,"
line.long 0xA0 "INST20_0,"
line.long 0xA4 "INST20_1,"
hexmask.long.byte 0xA4 25.--31. 1. "NU2,"
rbitfld.long 0xA4 24. "NU1," "0,1"
bitfld.long 0xA4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xA4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xA4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xA4 0.--7. 1. "PARAM,"
line.long 0xA8 "INST21_0,"
line.long 0xAC "INST21_1,"
hexmask.long.byte 0xAC 25.--31. 1. "NU2,"
rbitfld.long 0xAC 24. "NU1," "0,1"
bitfld.long 0xAC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xAC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xAC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xAC 0.--7. 1. "PARAM,"
line.long 0xB0 "INST22_0,"
line.long 0xB4 "INST22_1,"
hexmask.long.byte 0xB4 25.--31. 1. "NU2,"
rbitfld.long 0xB4 24. "NU1," "0,1"
bitfld.long 0xB4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xB4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xB4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xB4 0.--7. 1. "PARAM,"
line.long 0xB8 "INST23_0,"
line.long 0xBC "INST23_1,"
hexmask.long.byte 0xBC 25.--31. 1. "NU2,"
rbitfld.long 0xBC 24. "NU1," "0,1"
bitfld.long 0xBC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xBC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xBC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xBC 0.--7. 1. "PARAM,"
line.long 0xC0 "INST24_0,"
line.long 0xC4 "INST24_1,"
hexmask.long.byte 0xC4 25.--31. 1. "NU2,"
rbitfld.long 0xC4 24. "NU1," "0,1"
bitfld.long 0xC4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xC4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xC4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xC4 0.--7. 1. "PARAM,"
line.long 0xC8 "INST25_0,"
line.long 0xCC "INST25_1,"
hexmask.long.byte 0xCC 25.--31. 1. "NU2,"
rbitfld.long 0xCC 24. "NU1," "0,1"
bitfld.long 0xCC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xCC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xCC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xCC 0.--7. 1. "PARAM,"
line.long 0xD0 "INST26_0,"
line.long 0xD4 "INST26_1,"
hexmask.long.byte 0xD4 25.--31. 1. "NU2,"
rbitfld.long 0xD4 24. "NU1," "0,1"
bitfld.long 0xD4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xD4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xD4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xD4 0.--7. 1. "PARAM,"
line.long 0xD8 "INST27_0,"
line.long 0xDC "INST27_1,"
hexmask.long.byte 0xDC 25.--31. 1. "NU2,"
rbitfld.long 0xDC 24. "NU1," "0,1"
bitfld.long 0xDC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xDC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xDC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xDC 0.--7. 1. "PARAM,"
line.long 0xE0 "INST28_0,"
line.long 0xE4 "INST28_1,"
hexmask.long.byte 0xE4 25.--31. 1. "NU2,"
rbitfld.long 0xE4 24. "NU1," "0,1"
bitfld.long 0xE4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xE4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xE4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xE4 0.--7. 1. "PARAM,"
line.long 0xE8 "INST29_0,"
line.long 0xEC "INST29_1,"
hexmask.long.byte 0xEC 25.--31. 1. "NU2,"
rbitfld.long 0xEC 24. "NU1," "0,1"
bitfld.long 0xEC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xEC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xEC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xEC 0.--7. 1. "PARAM,"
line.long 0xF0 "INST30_0,"
line.long 0xF4 "INST30_1,"
hexmask.long.byte 0xF4 25.--31. 1. "NU2,"
rbitfld.long 0xF4 24. "NU1," "0,1"
bitfld.long 0xF4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xF4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xF4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xF4 0.--7. 1. "PARAM,"
line.long 0xF8 "INST31_0,"
line.long 0xFC "INST31_1,"
hexmask.long.byte 0xFC 25.--31. 1. "NU2,"
rbitfld.long 0xFC 24. "NU1," "0,1"
bitfld.long 0xFC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0xFC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0xFC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0xFC 0.--7. 1. "PARAM,"
line.long 0x100 "INST32_0,"
line.long 0x104 "INST32_1,"
hexmask.long.byte 0x104 25.--31. 1. "NU2,"
rbitfld.long 0x104 24. "NU1," "0,1"
bitfld.long 0x104 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x104 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x104 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x104 0.--7. 1. "PARAM,"
line.long 0x108 "INST33_0,"
line.long 0x10C "INST33_1,"
hexmask.long.byte 0x10C 25.--31. 1. "NU2,"
rbitfld.long 0x10C 24. "NU1," "0,1"
bitfld.long 0x10C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x10C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x10C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x10C 0.--7. 1. "PARAM,"
line.long 0x110 "INST34_0,"
line.long 0x114 "INST34_1,"
hexmask.long.byte 0x114 25.--31. 1. "NU2,"
rbitfld.long 0x114 24. "NU1," "0,1"
bitfld.long 0x114 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x114 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x114 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x114 0.--7. 1. "PARAM,"
line.long 0x118 "INST35_0,"
line.long 0x11C "INST35_1,"
hexmask.long.byte 0x11C 25.--31. 1. "NU2,"
rbitfld.long 0x11C 24. "NU1," "0,1"
bitfld.long 0x11C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x11C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x11C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x11C 0.--7. 1. "PARAM,"
line.long 0x120 "INST36_0,"
line.long 0x124 "INST36_1,"
hexmask.long.byte 0x124 25.--31. 1. "NU2,"
rbitfld.long 0x124 24. "NU1," "0,1"
bitfld.long 0x124 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x124 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x124 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x124 0.--7. 1. "PARAM,"
line.long 0x128 "INST37_0,"
line.long 0x12C "INST37_1,"
hexmask.long.byte 0x12C 25.--31. 1. "NU2,"
rbitfld.long 0x12C 24. "NU1," "0,1"
bitfld.long 0x12C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x12C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x12C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x12C 0.--7. 1. "PARAM,"
line.long 0x130 "INST38_0,"
line.long 0x134 "INST38_1,"
hexmask.long.byte 0x134 25.--31. 1. "NU2,"
rbitfld.long 0x134 24. "NU1," "0,1"
bitfld.long 0x134 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x134 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x134 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x134 0.--7. 1. "PARAM,"
line.long 0x138 "INST39_0,"
line.long 0x13C "INST39_1,"
hexmask.long.byte 0x13C 25.--31. 1. "NU2,"
rbitfld.long 0x13C 24. "NU1," "0,1"
bitfld.long 0x13C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x13C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x13C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x13C 0.--7. 1. "PARAM,"
line.long 0x140 "INST40_0,"
line.long 0x144 "INST40_1,"
hexmask.long.byte 0x144 25.--31. 1. "NU2,"
rbitfld.long 0x144 24. "NU1," "0,1"
bitfld.long 0x144 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x144 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x144 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x144 0.--7. 1. "PARAM,"
line.long 0x148 "INST41_0,"
line.long 0x14C "INST41_1,"
hexmask.long.byte 0x14C 25.--31. 1. "NU2,"
rbitfld.long 0x14C 24. "NU1," "0,1"
bitfld.long 0x14C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x14C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x14C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x14C 0.--7. 1. "PARAM,"
line.long 0x150 "INST42_0,"
line.long 0x154 "INST42_1,"
hexmask.long.byte 0x154 25.--31. 1. "NU2,"
rbitfld.long 0x154 24. "NU1," "0,1"
bitfld.long 0x154 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x154 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x154 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x154 0.--7. 1. "PARAM,"
line.long 0x158 "INST43_0,"
line.long 0x15C "INST43_1,"
hexmask.long.byte 0x15C 25.--31. 1. "NU2,"
rbitfld.long 0x15C 24. "NU1," "0,1"
bitfld.long 0x15C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x15C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x15C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x15C 0.--7. 1. "PARAM,"
line.long 0x160 "INST44_0,"
line.long 0x164 "INST44_1,"
hexmask.long.byte 0x164 25.--31. 1. "NU2,"
rbitfld.long 0x164 24. "NU1," "0,1"
bitfld.long 0x164 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x164 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x164 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x164 0.--7. 1. "PARAM,"
line.long 0x168 "INST45_0,"
line.long 0x16C "INST45_1,"
hexmask.long.byte 0x16C 25.--31. 1. "NU2,"
rbitfld.long 0x16C 24. "NU1," "0,1"
bitfld.long 0x16C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x16C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x16C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x16C 0.--7. 1. "PARAM,"
line.long 0x170 "INST46_0,"
line.long 0x174 "INST46_1,"
hexmask.long.byte 0x174 25.--31. 1. "NU2,"
rbitfld.long 0x174 24. "NU1," "0,1"
bitfld.long 0x174 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x174 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x174 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x174 0.--7. 1. "PARAM,"
line.long 0x178 "INST47_0,"
line.long 0x17C "INST47_1,"
hexmask.long.byte 0x17C 25.--31. 1. "NU2,"
rbitfld.long 0x17C 24. "NU1," "0,1"
bitfld.long 0x17C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x17C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x17C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x17C 0.--7. 1. "PARAM,"
line.long 0x180 "INST48_0,"
line.long 0x184 "INST48_1,"
hexmask.long.byte 0x184 25.--31. 1. "NU2,"
rbitfld.long 0x184 24. "NU1," "0,1"
bitfld.long 0x184 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x184 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x184 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x184 0.--7. 1. "PARAM,"
line.long 0x188 "INST49_0,"
line.long 0x18C "INST49_1,"
hexmask.long.byte 0x18C 25.--31. 1. "NU2,"
rbitfld.long 0x18C 24. "NU1," "0,1"
bitfld.long 0x18C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x18C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x18C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x18C 0.--7. 1. "PARAM,"
line.long 0x190 "INST50_0,"
line.long 0x194 "INST50_1,"
hexmask.long.byte 0x194 25.--31. 1. "NU2,"
rbitfld.long 0x194 24. "NU1," "0,1"
bitfld.long 0x194 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x194 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x194 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x194 0.--7. 1. "PARAM,"
line.long 0x198 "INST51_0,"
line.long 0x19C "INST51_1,"
hexmask.long.byte 0x19C 25.--31. 1. "NU2,"
rbitfld.long 0x19C 24. "NU1," "0,1"
bitfld.long 0x19C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x19C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x19C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x19C 0.--7. 1. "PARAM,"
line.long 0x1A0 "INST52_0,"
line.long 0x1A4 "INST52_1,"
hexmask.long.byte 0x1A4 25.--31. 1. "NU2,"
rbitfld.long 0x1A4 24. "NU1," "0,1"
bitfld.long 0x1A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1A4 0.--7. 1. "PARAM,"
line.long 0x1A8 "INST53_0,"
line.long 0x1AC "INST53_1,"
hexmask.long.byte 0x1AC 25.--31. 1. "NU2,"
rbitfld.long 0x1AC 24. "NU1," "0,1"
bitfld.long 0x1AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1AC 0.--7. 1. "PARAM,"
line.long 0x1B0 "INST54_0,"
line.long 0x1B4 "INST54_1,"
hexmask.long.byte 0x1B4 25.--31. 1. "NU2,"
rbitfld.long 0x1B4 24. "NU1," "0,1"
bitfld.long 0x1B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1B4 0.--7. 1. "PARAM,"
line.long 0x1B8 "INST55_0,"
line.long 0x1BC "INST55_1,"
hexmask.long.byte 0x1BC 25.--31. 1. "NU2,"
rbitfld.long 0x1BC 24. "NU1," "0,1"
bitfld.long 0x1BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1BC 0.--7. 1. "PARAM,"
line.long 0x1C0 "INST56_0,"
line.long 0x1C4 "INST56_1,"
hexmask.long.byte 0x1C4 25.--31. 1. "NU2,"
rbitfld.long 0x1C4 24. "NU1," "0,1"
bitfld.long 0x1C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1C4 0.--7. 1. "PARAM,"
line.long 0x1C8 "INST57_0,"
line.long 0x1CC "INST57_1,"
hexmask.long.byte 0x1CC 25.--31. 1. "NU2,"
rbitfld.long 0x1CC 24. "NU1," "0,1"
bitfld.long 0x1CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1CC 0.--7. 1. "PARAM,"
line.long 0x1D0 "INST58_0,"
line.long 0x1D4 "INST58_1,"
hexmask.long.byte 0x1D4 25.--31. 1. "NU2,"
rbitfld.long 0x1D4 24. "NU1," "0,1"
bitfld.long 0x1D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1D4 0.--7. 1. "PARAM,"
line.long 0x1D8 "INST59_0,"
line.long 0x1DC "INST59_1,"
hexmask.long.byte 0x1DC 25.--31. 1. "NU2,"
rbitfld.long 0x1DC 24. "NU1," "0,1"
bitfld.long 0x1DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1DC 0.--7. 1. "PARAM,"
line.long 0x1E0 "INST60_0,"
line.long 0x1E4 "INST60_1,"
hexmask.long.byte 0x1E4 25.--31. 1. "NU2,"
rbitfld.long 0x1E4 24. "NU1," "0,1"
bitfld.long 0x1E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1E4 0.--7. 1. "PARAM,"
line.long 0x1E8 "INST61_0,"
line.long 0x1EC "INST61_1,"
hexmask.long.byte 0x1EC 25.--31. 1. "NU2,"
rbitfld.long 0x1EC 24. "NU1," "0,1"
bitfld.long 0x1EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1EC 0.--7. 1. "PARAM,"
line.long 0x1F0 "INST62_0,"
line.long 0x1F4 "INST62_1,"
hexmask.long.byte 0x1F4 25.--31. 1. "NU2,"
rbitfld.long 0x1F4 24. "NU1," "0,1"
bitfld.long 0x1F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1F4 0.--7. 1. "PARAM,"
line.long 0x1F8 "INST63_0,"
line.long 0x1FC "INST63_1,"
hexmask.long.byte 0x1FC 25.--31. 1. "NU2,"
rbitfld.long 0x1FC 24. "NU1," "0,1"
bitfld.long 0x1FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x1FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x1FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x1FC 0.--7. 1. "PARAM,"
line.long 0x200 "INST64_0,"
line.long 0x204 "INST64_1,"
hexmask.long.byte 0x204 25.--31. 1. "NU2,"
rbitfld.long 0x204 24. "NU1," "0,1"
bitfld.long 0x204 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x204 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x204 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x204 0.--7. 1. "PARAM,"
line.long 0x208 "INST65_0,"
line.long 0x20C "INST65_1,"
hexmask.long.byte 0x20C 25.--31. 1. "NU2,"
rbitfld.long 0x20C 24. "NU1," "0,1"
bitfld.long 0x20C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x20C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x20C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x20C 0.--7. 1. "PARAM,"
line.long 0x210 "INST66_0,"
line.long 0x214 "INST66_1,"
hexmask.long.byte 0x214 25.--31. 1. "NU2,"
rbitfld.long 0x214 24. "NU1," "0,1"
bitfld.long 0x214 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x214 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x214 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x214 0.--7. 1. "PARAM,"
line.long 0x218 "INST67_0,"
line.long 0x21C "INST67_1,"
hexmask.long.byte 0x21C 25.--31. 1. "NU2,"
rbitfld.long 0x21C 24. "NU1," "0,1"
bitfld.long 0x21C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x21C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x21C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x21C 0.--7. 1. "PARAM,"
line.long 0x220 "INST68_0,"
line.long 0x224 "INST68_1,"
hexmask.long.byte 0x224 25.--31. 1. "NU2,"
rbitfld.long 0x224 24. "NU1," "0,1"
bitfld.long 0x224 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x224 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x224 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x224 0.--7. 1. "PARAM,"
line.long 0x228 "INST69_0,"
line.long 0x22C "INST69_1,"
hexmask.long.byte 0x22C 25.--31. 1. "NU2,"
rbitfld.long 0x22C 24. "NU1," "0,1"
bitfld.long 0x22C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x22C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x22C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x22C 0.--7. 1. "PARAM,"
line.long 0x230 "INST70_0,"
line.long 0x234 "INST70_1,"
hexmask.long.byte 0x234 25.--31. 1. "NU2,"
rbitfld.long 0x234 24. "NU1," "0,1"
bitfld.long 0x234 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x234 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x234 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x234 0.--7. 1. "PARAM,"
line.long 0x238 "INST71_0,"
line.long 0x23C "INST71_1,"
hexmask.long.byte 0x23C 25.--31. 1. "NU2,"
rbitfld.long 0x23C 24. "NU1," "0,1"
bitfld.long 0x23C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x23C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x23C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x23C 0.--7. 1. "PARAM,"
line.long 0x240 "INST72_0,"
line.long 0x244 "INST72_1,"
hexmask.long.byte 0x244 25.--31. 1. "NU2,"
rbitfld.long 0x244 24. "NU1," "0,1"
bitfld.long 0x244 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x244 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x244 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x244 0.--7. 1. "PARAM,"
line.long 0x248 "INST73_0,"
line.long 0x24C "INST73_1,"
hexmask.long.byte 0x24C 25.--31. 1. "NU2,"
rbitfld.long 0x24C 24. "NU1," "0,1"
bitfld.long 0x24C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x24C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x24C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x24C 0.--7. 1. "PARAM,"
line.long 0x250 "INST74_0,"
line.long 0x254 "INST74_1,"
hexmask.long.byte 0x254 25.--31. 1. "NU2,"
rbitfld.long 0x254 24. "NU1," "0,1"
bitfld.long 0x254 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x254 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x254 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x254 0.--7. 1. "PARAM,"
line.long 0x258 "INST75_0,"
line.long 0x25C "INST75_1,"
hexmask.long.byte 0x25C 25.--31. 1. "NU2,"
rbitfld.long 0x25C 24. "NU1," "0,1"
bitfld.long 0x25C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x25C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x25C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x25C 0.--7. 1. "PARAM,"
line.long 0x260 "INST76_0,"
line.long 0x264 "INST76_1,"
hexmask.long.byte 0x264 25.--31. 1. "NU2,"
rbitfld.long 0x264 24. "NU1," "0,1"
bitfld.long 0x264 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x264 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x264 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x264 0.--7. 1. "PARAM,"
line.long 0x268 "INST77_0,"
line.long 0x26C "INST77_1,"
hexmask.long.byte 0x26C 25.--31. 1. "NU2,"
rbitfld.long 0x26C 24. "NU1," "0,1"
bitfld.long 0x26C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x26C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x26C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x26C 0.--7. 1. "PARAM,"
line.long 0x270 "INST78_0,"
line.long 0x274 "INST78_1,"
hexmask.long.byte 0x274 25.--31. 1. "NU2,"
rbitfld.long 0x274 24. "NU1," "0,1"
bitfld.long 0x274 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x274 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x274 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x274 0.--7. 1. "PARAM,"
line.long 0x278 "INST79_0,"
line.long 0x27C "INST79_1,"
hexmask.long.byte 0x27C 25.--31. 1. "NU2,"
rbitfld.long 0x27C 24. "NU1," "0,1"
bitfld.long 0x27C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x27C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x27C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x27C 0.--7. 1. "PARAM,"
line.long 0x280 "INST80_0,"
line.long 0x284 "INST80_1,"
hexmask.long.byte 0x284 25.--31. 1. "NU2,"
rbitfld.long 0x284 24. "NU1," "0,1"
bitfld.long 0x284 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x284 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x284 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x284 0.--7. 1. "PARAM,"
line.long 0x288 "INST81_0,"
line.long 0x28C "INST81_1,"
hexmask.long.byte 0x28C 25.--31. 1. "NU2,"
rbitfld.long 0x28C 24. "NU1," "0,1"
bitfld.long 0x28C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x28C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x28C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x28C 0.--7. 1. "PARAM,"
line.long 0x290 "INST82_0,"
line.long 0x294 "INST82_1,"
hexmask.long.byte 0x294 25.--31. 1. "NU2,"
rbitfld.long 0x294 24. "NU1," "0,1"
bitfld.long 0x294 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x294 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x294 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x294 0.--7. 1. "PARAM,"
line.long 0x298 "INST83_0,"
line.long 0x29C "INST83_1,"
hexmask.long.byte 0x29C 25.--31. 1. "NU2,"
rbitfld.long 0x29C 24. "NU1," "0,1"
bitfld.long 0x29C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x29C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x29C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x29C 0.--7. 1. "PARAM,"
line.long 0x2A0 "INST84_0,"
line.long 0x2A4 "INST84_1,"
hexmask.long.byte 0x2A4 25.--31. 1. "NU2,"
rbitfld.long 0x2A4 24. "NU1," "0,1"
bitfld.long 0x2A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2A4 0.--7. 1. "PARAM,"
line.long 0x2A8 "INST85_0,"
line.long 0x2AC "INST85_1,"
hexmask.long.byte 0x2AC 25.--31. 1. "NU2,"
rbitfld.long 0x2AC 24. "NU1," "0,1"
bitfld.long 0x2AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2AC 0.--7. 1. "PARAM,"
line.long 0x2B0 "INST86_0,"
line.long 0x2B4 "INST86_1,"
hexmask.long.byte 0x2B4 25.--31. 1. "NU2,"
rbitfld.long 0x2B4 24. "NU1," "0,1"
bitfld.long 0x2B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2B4 0.--7. 1. "PARAM,"
line.long 0x2B8 "INST87_0,"
line.long 0x2BC "INST87_1,"
hexmask.long.byte 0x2BC 25.--31. 1. "NU2,"
rbitfld.long 0x2BC 24. "NU1," "0,1"
bitfld.long 0x2BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2BC 0.--7. 1. "PARAM,"
line.long 0x2C0 "INST88_0,"
line.long 0x2C4 "INST88_1,"
hexmask.long.byte 0x2C4 25.--31. 1. "NU2,"
rbitfld.long 0x2C4 24. "NU1," "0,1"
bitfld.long 0x2C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2C4 0.--7. 1. "PARAM,"
line.long 0x2C8 "INST89_0,"
line.long 0x2CC "INST89_1,"
hexmask.long.byte 0x2CC 25.--31. 1. "NU2,"
rbitfld.long 0x2CC 24. "NU1," "0,1"
bitfld.long 0x2CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2CC 0.--7. 1. "PARAM,"
line.long 0x2D0 "INST90_0,"
line.long 0x2D4 "INST90_1,"
hexmask.long.byte 0x2D4 25.--31. 1. "NU2,"
rbitfld.long 0x2D4 24. "NU1," "0,1"
bitfld.long 0x2D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2D4 0.--7. 1. "PARAM,"
line.long 0x2D8 "INST91_0,"
line.long 0x2DC "INST91_1,"
hexmask.long.byte 0x2DC 25.--31. 1. "NU2,"
rbitfld.long 0x2DC 24. "NU1," "0,1"
bitfld.long 0x2DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2DC 0.--7. 1. "PARAM,"
line.long 0x2E0 "INST92_0,"
line.long 0x2E4 "INST92_1,"
hexmask.long.byte 0x2E4 25.--31. 1. "NU2,"
rbitfld.long 0x2E4 24. "NU1," "0,1"
bitfld.long 0x2E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2E4 0.--7. 1. "PARAM,"
line.long 0x2E8 "INST93_0,"
line.long 0x2EC "INST93_1,"
hexmask.long.byte 0x2EC 25.--31. 1. "NU2,"
rbitfld.long 0x2EC 24. "NU1," "0,1"
bitfld.long 0x2EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2EC 0.--7. 1. "PARAM,"
line.long 0x2F0 "INST94_0,"
line.long 0x2F4 "INST94_1,"
hexmask.long.byte 0x2F4 25.--31. 1. "NU2,"
rbitfld.long 0x2F4 24. "NU1," "0,1"
bitfld.long 0x2F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2F4 0.--7. 1. "PARAM,"
line.long 0x2F8 "INST95_0,"
line.long 0x2FC "INST95_1,"
hexmask.long.byte 0x2FC 25.--31. 1. "NU2,"
rbitfld.long 0x2FC 24. "NU1," "0,1"
bitfld.long 0x2FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x2FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x2FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x2FC 0.--7. 1. "PARAM,"
line.long 0x300 "INST96_0,"
line.long 0x304 "INST96_1,"
hexmask.long.byte 0x304 25.--31. 1. "NU2,"
rbitfld.long 0x304 24. "NU1," "0,1"
bitfld.long 0x304 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x304 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x304 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x304 0.--7. 1. "PARAM,"
line.long 0x308 "INST97_0,"
line.long 0x30C "INST97_1,"
hexmask.long.byte 0x30C 25.--31. 1. "NU2,"
rbitfld.long 0x30C 24. "NU1," "0,1"
bitfld.long 0x30C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x30C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x30C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x30C 0.--7. 1. "PARAM,"
line.long 0x310 "INST98_0,"
line.long 0x314 "INST98_1,"
hexmask.long.byte 0x314 25.--31. 1. "NU2,"
rbitfld.long 0x314 24. "NU1," "0,1"
bitfld.long 0x314 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x314 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x314 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x314 0.--7. 1. "PARAM,"
line.long 0x318 "INST99_0,"
line.long 0x31C "INST99_1,"
hexmask.long.byte 0x31C 25.--31. 1. "NU2,"
rbitfld.long 0x31C 24. "NU1," "0,1"
bitfld.long 0x31C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x31C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x31C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x31C 0.--7. 1. "PARAM,"
line.long 0x320 "INST100_0,"
line.long 0x324 "INST100_1,"
hexmask.long.byte 0x324 25.--31. 1. "NU2,"
rbitfld.long 0x324 24. "NU1," "0,1"
bitfld.long 0x324 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x324 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x324 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x324 0.--7. 1. "PARAM,"
line.long 0x328 "INST101_0,"
line.long 0x32C "INST101_1,"
hexmask.long.byte 0x32C 25.--31. 1. "NU2,"
rbitfld.long 0x32C 24. "NU1," "0,1"
bitfld.long 0x32C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x32C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x32C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x32C 0.--7. 1. "PARAM,"
line.long 0x330 "INST102_0,"
line.long 0x334 "INST102_1,"
hexmask.long.byte 0x334 25.--31. 1. "NU2,"
rbitfld.long 0x334 24. "NU1," "0,1"
bitfld.long 0x334 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x334 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x334 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x334 0.--7. 1. "PARAM,"
line.long 0x338 "INST103_0,"
line.long 0x33C "INST103_1,"
hexmask.long.byte 0x33C 25.--31. 1. "NU2,"
rbitfld.long 0x33C 24. "NU1," "0,1"
bitfld.long 0x33C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x33C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x33C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x33C 0.--7. 1. "PARAM,"
line.long 0x340 "INST104_0,"
line.long 0x344 "INST104_1,"
hexmask.long.byte 0x344 25.--31. 1. "NU2,"
rbitfld.long 0x344 24. "NU1," "0,1"
bitfld.long 0x344 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x344 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x344 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x344 0.--7. 1. "PARAM,"
line.long 0x348 "INST105_0,"
line.long 0x34C "INST105_1,"
hexmask.long.byte 0x34C 25.--31. 1. "NU2,"
rbitfld.long 0x34C 24. "NU1," "0,1"
bitfld.long 0x34C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x34C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x34C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x34C 0.--7. 1. "PARAM,"
line.long 0x350 "INST106_0,"
line.long 0x354 "INST106_1,"
hexmask.long.byte 0x354 25.--31. 1. "NU2,"
rbitfld.long 0x354 24. "NU1," "0,1"
bitfld.long 0x354 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x354 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x354 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x354 0.--7. 1. "PARAM,"
line.long 0x358 "INST107_0,"
line.long 0x35C "INST107_1,"
hexmask.long.byte 0x35C 25.--31. 1. "NU2,"
rbitfld.long 0x35C 24. "NU1," "0,1"
bitfld.long 0x35C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x35C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x35C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x35C 0.--7. 1. "PARAM,"
line.long 0x360 "INST108_0,"
line.long 0x364 "INST108_1,"
hexmask.long.byte 0x364 25.--31. 1. "NU2,"
rbitfld.long 0x364 24. "NU1," "0,1"
bitfld.long 0x364 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x364 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x364 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x364 0.--7. 1. "PARAM,"
line.long 0x368 "INST109_0,"
line.long 0x36C "INST109_1,"
hexmask.long.byte 0x36C 25.--31. 1. "NU2,"
rbitfld.long 0x36C 24. "NU1," "0,1"
bitfld.long 0x36C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x36C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x36C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x36C 0.--7. 1. "PARAM,"
line.long 0x370 "INST110_0,"
line.long 0x374 "INST110_1,"
hexmask.long.byte 0x374 25.--31. 1. "NU2,"
rbitfld.long 0x374 24. "NU1," "0,1"
bitfld.long 0x374 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x374 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x374 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x374 0.--7. 1. "PARAM,"
line.long 0x378 "INST111_0,"
line.long 0x37C "INST111_1,"
hexmask.long.byte 0x37C 25.--31. 1. "NU2,"
rbitfld.long 0x37C 24. "NU1," "0,1"
bitfld.long 0x37C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x37C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x37C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x37C 0.--7. 1. "PARAM,"
line.long 0x380 "INST112_0,"
line.long 0x384 "INST112_1,"
hexmask.long.byte 0x384 25.--31. 1. "NU2,"
rbitfld.long 0x384 24. "NU1," "0,1"
bitfld.long 0x384 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x384 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x384 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x384 0.--7. 1. "PARAM,"
line.long 0x388 "INST113_0,"
line.long 0x38C "INST113_1,"
hexmask.long.byte 0x38C 25.--31. 1. "NU2,"
rbitfld.long 0x38C 24. "NU1," "0,1"
bitfld.long 0x38C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x38C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x38C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x38C 0.--7. 1. "PARAM,"
line.long 0x390 "INST114_0,"
line.long 0x394 "INST114_1,"
hexmask.long.byte 0x394 25.--31. 1. "NU2,"
rbitfld.long 0x394 24. "NU1," "0,1"
bitfld.long 0x394 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x394 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x394 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x394 0.--7. 1. "PARAM,"
line.long 0x398 "INST115_0,"
line.long 0x39C "INST115_1,"
hexmask.long.byte 0x39C 25.--31. 1. "NU2,"
rbitfld.long 0x39C 24. "NU1," "0,1"
bitfld.long 0x39C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x39C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x39C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x39C 0.--7. 1. "PARAM,"
line.long 0x3A0 "INST116_0,"
line.long 0x3A4 "INST116_1,"
hexmask.long.byte 0x3A4 25.--31. 1. "NU2,"
rbitfld.long 0x3A4 24. "NU1," "0,1"
bitfld.long 0x3A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3A4 0.--7. 1. "PARAM,"
line.long 0x3A8 "INST117_0,"
line.long 0x3AC "INST117_1,"
hexmask.long.byte 0x3AC 25.--31. 1. "NU2,"
rbitfld.long 0x3AC 24. "NU1," "0,1"
bitfld.long 0x3AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3AC 0.--7. 1. "PARAM,"
line.long 0x3B0 "INST118_0,"
line.long 0x3B4 "INST118_1,"
hexmask.long.byte 0x3B4 25.--31. 1. "NU2,"
rbitfld.long 0x3B4 24. "NU1," "0,1"
bitfld.long 0x3B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3B4 0.--7. 1. "PARAM,"
line.long 0x3B8 "INST119_0,"
line.long 0x3BC "INST119_1,"
hexmask.long.byte 0x3BC 25.--31. 1. "NU2,"
rbitfld.long 0x3BC 24. "NU1," "0,1"
bitfld.long 0x3BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3BC 0.--7. 1. "PARAM,"
line.long 0x3C0 "INST120_0,"
line.long 0x3C4 "INST120_1,"
hexmask.long.byte 0x3C4 25.--31. 1. "NU2,"
rbitfld.long 0x3C4 24. "NU1," "0,1"
bitfld.long 0x3C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3C4 0.--7. 1. "PARAM,"
line.long 0x3C8 "INST121_0,"
line.long 0x3CC "INST121_1,"
hexmask.long.byte 0x3CC 25.--31. 1. "NU2,"
rbitfld.long 0x3CC 24. "NU1," "0,1"
bitfld.long 0x3CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3CC 0.--7. 1. "PARAM,"
line.long 0x3D0 "INST122_0,"
line.long 0x3D4 "INST122_1,"
hexmask.long.byte 0x3D4 25.--31. 1. "NU2,"
rbitfld.long 0x3D4 24. "NU1," "0,1"
bitfld.long 0x3D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3D4 0.--7. 1. "PARAM,"
line.long 0x3D8 "INST123_0,"
line.long 0x3DC "INST123_1,"
hexmask.long.byte 0x3DC 25.--31. 1. "NU2,"
rbitfld.long 0x3DC 24. "NU1," "0,1"
bitfld.long 0x3DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3DC 0.--7. 1. "PARAM,"
line.long 0x3E0 "INST124_0,"
line.long 0x3E4 "INST124_1,"
hexmask.long.byte 0x3E4 25.--31. 1. "NU2,"
rbitfld.long 0x3E4 24. "NU1," "0,1"
bitfld.long 0x3E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3E4 0.--7. 1. "PARAM,"
line.long 0x3E8 "INST125_0,"
line.long 0x3EC "INST125_1,"
hexmask.long.byte 0x3EC 25.--31. 1. "NU2,"
rbitfld.long 0x3EC 24. "NU1," "0,1"
bitfld.long 0x3EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3EC 0.--7. 1. "PARAM,"
line.long 0x3F0 "INST126_0,"
line.long 0x3F4 "INST126_1,"
hexmask.long.byte 0x3F4 25.--31. 1. "NU2,"
rbitfld.long 0x3F4 24. "NU1," "0,1"
bitfld.long 0x3F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3F4 0.--7. 1. "PARAM,"
line.long 0x3F8 "INST127_0,"
line.long 0x3FC "INST127_1,"
hexmask.long.byte 0x3FC 25.--31. 1. "NU2,"
rbitfld.long 0x3FC 24. "NU1," "0,1"
bitfld.long 0x3FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x3FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x3FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x3FC 0.--7. 1. "PARAM,"
line.long 0x400 "INST128_0,"
line.long 0x404 "INST128_1,"
hexmask.long.byte 0x404 25.--31. 1. "NU2,"
rbitfld.long 0x404 24. "NU1," "0,1"
bitfld.long 0x404 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x404 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x404 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x404 0.--7. 1. "PARAM,"
line.long 0x408 "INST129_0,"
line.long 0x40C "INST129_1,"
hexmask.long.byte 0x40C 25.--31. 1. "NU2,"
rbitfld.long 0x40C 24. "NU1," "0,1"
bitfld.long 0x40C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x40C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x40C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x40C 0.--7. 1. "PARAM,"
line.long 0x410 "INST130_0,"
line.long 0x414 "INST130_1,"
hexmask.long.byte 0x414 25.--31. 1. "NU2,"
rbitfld.long 0x414 24. "NU1," "0,1"
bitfld.long 0x414 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x414 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x414 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x414 0.--7. 1. "PARAM,"
line.long 0x418 "INST131_0,"
line.long 0x41C "INST131_1,"
hexmask.long.byte 0x41C 25.--31. 1. "NU2,"
rbitfld.long 0x41C 24. "NU1," "0,1"
bitfld.long 0x41C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x41C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x41C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x41C 0.--7. 1. "PARAM,"
line.long 0x420 "INST132_0,"
line.long 0x424 "INST132_1,"
hexmask.long.byte 0x424 25.--31. 1. "NU2,"
rbitfld.long 0x424 24. "NU1," "0,1"
bitfld.long 0x424 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x424 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x424 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x424 0.--7. 1. "PARAM,"
line.long 0x428 "INST133_0,"
line.long 0x42C "INST133_1,"
hexmask.long.byte 0x42C 25.--31. 1. "NU2,"
rbitfld.long 0x42C 24. "NU1," "0,1"
bitfld.long 0x42C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x42C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x42C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x42C 0.--7. 1. "PARAM,"
line.long 0x430 "INST134_0,"
line.long 0x434 "INST134_1,"
hexmask.long.byte 0x434 25.--31. 1. "NU2,"
rbitfld.long 0x434 24. "NU1," "0,1"
bitfld.long 0x434 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x434 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x434 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x434 0.--7. 1. "PARAM,"
line.long 0x438 "INST135_0,"
line.long 0x43C "INST135_1,"
hexmask.long.byte 0x43C 25.--31. 1. "NU2,"
rbitfld.long 0x43C 24. "NU1," "0,1"
bitfld.long 0x43C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x43C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x43C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x43C 0.--7. 1. "PARAM,"
line.long 0x440 "INST136_0,"
line.long 0x444 "INST136_1,"
hexmask.long.byte 0x444 25.--31. 1. "NU2,"
rbitfld.long 0x444 24. "NU1," "0,1"
bitfld.long 0x444 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x444 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x444 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x444 0.--7. 1. "PARAM,"
line.long 0x448 "INST137_0,"
line.long 0x44C "INST137_1,"
hexmask.long.byte 0x44C 25.--31. 1. "NU2,"
rbitfld.long 0x44C 24. "NU1," "0,1"
bitfld.long 0x44C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x44C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x44C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x44C 0.--7. 1. "PARAM,"
line.long 0x450 "INST138_0,"
line.long 0x454 "INST138_1,"
hexmask.long.byte 0x454 25.--31. 1. "NU2,"
rbitfld.long 0x454 24. "NU1," "0,1"
bitfld.long 0x454 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x454 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x454 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x454 0.--7. 1. "PARAM,"
line.long 0x458 "INST139_0,"
line.long 0x45C "INST139_1,"
hexmask.long.byte 0x45C 25.--31. 1. "NU2,"
rbitfld.long 0x45C 24. "NU1," "0,1"
bitfld.long 0x45C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x45C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x45C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x45C 0.--7. 1. "PARAM,"
line.long 0x460 "INST140_0,"
line.long 0x464 "INST140_1,"
hexmask.long.byte 0x464 25.--31. 1. "NU2,"
rbitfld.long 0x464 24. "NU1," "0,1"
bitfld.long 0x464 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x464 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x464 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x464 0.--7. 1. "PARAM,"
line.long 0x468 "INST141_0,"
line.long 0x46C "INST141_1,"
hexmask.long.byte 0x46C 25.--31. 1. "NU2,"
rbitfld.long 0x46C 24. "NU1," "0,1"
bitfld.long 0x46C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x46C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x46C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x46C 0.--7. 1. "PARAM,"
line.long 0x470 "INST142_0,"
line.long 0x474 "INST142_1,"
hexmask.long.byte 0x474 25.--31. 1. "NU2,"
rbitfld.long 0x474 24. "NU1," "0,1"
bitfld.long 0x474 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x474 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x474 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x474 0.--7. 1. "PARAM,"
line.long 0x478 "INST143_0,"
line.long 0x47C "INST143_1,"
hexmask.long.byte 0x47C 25.--31. 1. "NU2,"
rbitfld.long 0x47C 24. "NU1," "0,1"
bitfld.long 0x47C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x47C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x47C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x47C 0.--7. 1. "PARAM,"
line.long 0x480 "INST144_0,"
line.long 0x484 "INST144_1,"
hexmask.long.byte 0x484 25.--31. 1. "NU2,"
rbitfld.long 0x484 24. "NU1," "0,1"
bitfld.long 0x484 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x484 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x484 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x484 0.--7. 1. "PARAM,"
line.long 0x488 "INST145_0,"
line.long 0x48C "INST145_1,"
hexmask.long.byte 0x48C 25.--31. 1. "NU2,"
rbitfld.long 0x48C 24. "NU1," "0,1"
bitfld.long 0x48C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x48C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x48C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x48C 0.--7. 1. "PARAM,"
line.long 0x490 "INST146_0,"
line.long 0x494 "INST146_1,"
hexmask.long.byte 0x494 25.--31. 1. "NU2,"
rbitfld.long 0x494 24. "NU1," "0,1"
bitfld.long 0x494 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x494 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x494 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x494 0.--7. 1. "PARAM,"
line.long 0x498 "INST147_0,"
line.long 0x49C "INST147_1,"
hexmask.long.byte 0x49C 25.--31. 1. "NU2,"
rbitfld.long 0x49C 24. "NU1," "0,1"
bitfld.long 0x49C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x49C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x49C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x49C 0.--7. 1. "PARAM,"
line.long 0x4A0 "INST148_0,"
line.long 0x4A4 "INST148_1,"
hexmask.long.byte 0x4A4 25.--31. 1. "NU2,"
rbitfld.long 0x4A4 24. "NU1," "0,1"
bitfld.long 0x4A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4A4 0.--7. 1. "PARAM,"
line.long 0x4A8 "INST149_0,"
line.long 0x4AC "INST149_1,"
hexmask.long.byte 0x4AC 25.--31. 1. "NU2,"
rbitfld.long 0x4AC 24. "NU1," "0,1"
bitfld.long 0x4AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4AC 0.--7. 1. "PARAM,"
line.long 0x4B0 "INST150_0,"
line.long 0x4B4 "INST150_1,"
hexmask.long.byte 0x4B4 25.--31. 1. "NU2,"
rbitfld.long 0x4B4 24. "NU1," "0,1"
bitfld.long 0x4B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4B4 0.--7. 1. "PARAM,"
line.long 0x4B8 "INST151_0,"
line.long 0x4BC "INST151_1,"
hexmask.long.byte 0x4BC 25.--31. 1. "NU2,"
rbitfld.long 0x4BC 24. "NU1," "0,1"
bitfld.long 0x4BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4BC 0.--7. 1. "PARAM,"
line.long 0x4C0 "INST152_0,"
line.long 0x4C4 "INST152_1,"
hexmask.long.byte 0x4C4 25.--31. 1. "NU2,"
rbitfld.long 0x4C4 24. "NU1," "0,1"
bitfld.long 0x4C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4C4 0.--7. 1. "PARAM,"
line.long 0x4C8 "INST153_0,"
line.long 0x4CC "INST153_1,"
hexmask.long.byte 0x4CC 25.--31. 1. "NU2,"
rbitfld.long 0x4CC 24. "NU1," "0,1"
bitfld.long 0x4CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4CC 0.--7. 1. "PARAM,"
line.long 0x4D0 "INST154_0,"
line.long 0x4D4 "INST154_1,"
hexmask.long.byte 0x4D4 25.--31. 1. "NU2,"
rbitfld.long 0x4D4 24. "NU1," "0,1"
bitfld.long 0x4D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4D4 0.--7. 1. "PARAM,"
line.long 0x4D8 "INST155_0,"
line.long 0x4DC "INST155_1,"
hexmask.long.byte 0x4DC 25.--31. 1. "NU2,"
rbitfld.long 0x4DC 24. "NU1," "0,1"
bitfld.long 0x4DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4DC 0.--7. 1. "PARAM,"
line.long 0x4E0 "INST156_0,"
line.long 0x4E4 "INST156_1,"
hexmask.long.byte 0x4E4 25.--31. 1. "NU2,"
rbitfld.long 0x4E4 24. "NU1," "0,1"
bitfld.long 0x4E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4E4 0.--7. 1. "PARAM,"
line.long 0x4E8 "INST157_0,"
line.long 0x4EC "INST157_1,"
hexmask.long.byte 0x4EC 25.--31. 1. "NU2,"
rbitfld.long 0x4EC 24. "NU1," "0,1"
bitfld.long 0x4EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4EC 0.--7. 1. "PARAM,"
line.long 0x4F0 "INST158_0,"
line.long 0x4F4 "INST158_1,"
hexmask.long.byte 0x4F4 25.--31. 1. "NU2,"
rbitfld.long 0x4F4 24. "NU1," "0,1"
bitfld.long 0x4F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4F4 0.--7. 1. "PARAM,"
line.long 0x4F8 "INST159_0,"
line.long 0x4FC "INST159_1,"
hexmask.long.byte 0x4FC 25.--31. 1. "NU2,"
rbitfld.long 0x4FC 24. "NU1," "0,1"
bitfld.long 0x4FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x4FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x4FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x4FC 0.--7. 1. "PARAM,"
line.long 0x500 "INST160_0,"
line.long 0x504 "INST160_1,"
hexmask.long.byte 0x504 25.--31. 1. "NU2,"
rbitfld.long 0x504 24. "NU1," "0,1"
bitfld.long 0x504 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x504 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x504 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x504 0.--7. 1. "PARAM,"
line.long 0x508 "INST161_0,"
line.long 0x50C "INST161_1,"
hexmask.long.byte 0x50C 25.--31. 1. "NU2,"
rbitfld.long 0x50C 24. "NU1," "0,1"
bitfld.long 0x50C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x50C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x50C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x50C 0.--7. 1. "PARAM,"
line.long 0x510 "INST162_0,"
line.long 0x514 "INST162_1,"
hexmask.long.byte 0x514 25.--31. 1. "NU2,"
rbitfld.long 0x514 24. "NU1," "0,1"
bitfld.long 0x514 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x514 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x514 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x514 0.--7. 1. "PARAM,"
line.long 0x518 "INST163_0,"
line.long 0x51C "INST163_1,"
hexmask.long.byte 0x51C 25.--31. 1. "NU2,"
rbitfld.long 0x51C 24. "NU1," "0,1"
bitfld.long 0x51C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x51C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x51C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x51C 0.--7. 1. "PARAM,"
line.long 0x520 "INST164_0,"
line.long 0x524 "INST164_1,"
hexmask.long.byte 0x524 25.--31. 1. "NU2,"
rbitfld.long 0x524 24. "NU1," "0,1"
bitfld.long 0x524 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x524 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x524 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x524 0.--7. 1. "PARAM,"
line.long 0x528 "INST165_0,"
line.long 0x52C "INST165_1,"
hexmask.long.byte 0x52C 25.--31. 1. "NU2,"
rbitfld.long 0x52C 24. "NU1," "0,1"
bitfld.long 0x52C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x52C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x52C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x52C 0.--7. 1. "PARAM,"
line.long 0x530 "INST166_0,"
line.long 0x534 "INST166_1,"
hexmask.long.byte 0x534 25.--31. 1. "NU2,"
rbitfld.long 0x534 24. "NU1," "0,1"
bitfld.long 0x534 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x534 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x534 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x534 0.--7. 1. "PARAM,"
line.long 0x538 "INST167_0,"
line.long 0x53C "INST167_1,"
hexmask.long.byte 0x53C 25.--31. 1. "NU2,"
rbitfld.long 0x53C 24. "NU1," "0,1"
bitfld.long 0x53C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x53C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x53C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x53C 0.--7. 1. "PARAM,"
line.long 0x540 "INST168_0,"
line.long 0x544 "INST168_1,"
hexmask.long.byte 0x544 25.--31. 1. "NU2,"
rbitfld.long 0x544 24. "NU1," "0,1"
bitfld.long 0x544 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x544 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x544 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x544 0.--7. 1. "PARAM,"
line.long 0x548 "INST169_0,"
line.long 0x54C "INST169_1,"
hexmask.long.byte 0x54C 25.--31. 1. "NU2,"
rbitfld.long 0x54C 24. "NU1," "0,1"
bitfld.long 0x54C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x54C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x54C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x54C 0.--7. 1. "PARAM,"
line.long 0x550 "INST170_0,"
line.long 0x554 "INST170_1,"
hexmask.long.byte 0x554 25.--31. 1. "NU2,"
rbitfld.long 0x554 24. "NU1," "0,1"
bitfld.long 0x554 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x554 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x554 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x554 0.--7. 1. "PARAM,"
line.long 0x558 "INST171_0,"
line.long 0x55C "INST171_1,"
hexmask.long.byte 0x55C 25.--31. 1. "NU2,"
rbitfld.long 0x55C 24. "NU1," "0,1"
bitfld.long 0x55C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x55C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x55C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x55C 0.--7. 1. "PARAM,"
line.long 0x560 "INST172_0,"
line.long 0x564 "INST172_1,"
hexmask.long.byte 0x564 25.--31. 1. "NU2,"
rbitfld.long 0x564 24. "NU1," "0,1"
bitfld.long 0x564 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x564 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x564 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x564 0.--7. 1. "PARAM,"
line.long 0x568 "INST173_0,"
line.long 0x56C "INST173_1,"
hexmask.long.byte 0x56C 25.--31. 1. "NU2,"
rbitfld.long 0x56C 24. "NU1," "0,1"
bitfld.long 0x56C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x56C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x56C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x56C 0.--7. 1. "PARAM,"
line.long 0x570 "INST174_0,"
line.long 0x574 "INST174_1,"
hexmask.long.byte 0x574 25.--31. 1. "NU2,"
rbitfld.long 0x574 24. "NU1," "0,1"
bitfld.long 0x574 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x574 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x574 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x574 0.--7. 1. "PARAM,"
line.long 0x578 "INST175_0,"
line.long 0x57C "INST175_1,"
hexmask.long.byte 0x57C 25.--31. 1. "NU2,"
rbitfld.long 0x57C 24. "NU1," "0,1"
bitfld.long 0x57C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x57C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x57C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x57C 0.--7. 1. "PARAM,"
line.long 0x580 "INST176_0,"
line.long 0x584 "INST176_1,"
hexmask.long.byte 0x584 25.--31. 1. "NU2,"
rbitfld.long 0x584 24. "NU1," "0,1"
bitfld.long 0x584 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x584 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x584 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x584 0.--7. 1. "PARAM,"
line.long 0x588 "INST177_0,"
line.long 0x58C "INST177_1,"
hexmask.long.byte 0x58C 25.--31. 1. "NU2,"
rbitfld.long 0x58C 24. "NU1," "0,1"
bitfld.long 0x58C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x58C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x58C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x58C 0.--7. 1. "PARAM,"
line.long 0x590 "INST178_0,"
line.long 0x594 "INST178_1,"
hexmask.long.byte 0x594 25.--31. 1. "NU2,"
rbitfld.long 0x594 24. "NU1," "0,1"
bitfld.long 0x594 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x594 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x594 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x594 0.--7. 1. "PARAM,"
line.long 0x598 "INST179_0,"
line.long 0x59C "INST179_1,"
hexmask.long.byte 0x59C 25.--31. 1. "NU2,"
rbitfld.long 0x59C 24. "NU1," "0,1"
bitfld.long 0x59C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x59C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x59C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x59C 0.--7. 1. "PARAM,"
line.long 0x5A0 "INST180_0,"
line.long 0x5A4 "INST180_1,"
hexmask.long.byte 0x5A4 25.--31. 1. "NU2,"
rbitfld.long 0x5A4 24. "NU1," "0,1"
bitfld.long 0x5A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5A4 0.--7. 1. "PARAM,"
line.long 0x5A8 "INST181_0,"
line.long 0x5AC "INST181_1,"
hexmask.long.byte 0x5AC 25.--31. 1. "NU2,"
rbitfld.long 0x5AC 24. "NU1," "0,1"
bitfld.long 0x5AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5AC 0.--7. 1. "PARAM,"
line.long 0x5B0 "INST182_0,"
line.long 0x5B4 "INST182_1,"
hexmask.long.byte 0x5B4 25.--31. 1. "NU2,"
rbitfld.long 0x5B4 24. "NU1," "0,1"
bitfld.long 0x5B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5B4 0.--7. 1. "PARAM,"
line.long 0x5B8 "INST183_0,"
line.long 0x5BC "INST183_1,"
hexmask.long.byte 0x5BC 25.--31. 1. "NU2,"
rbitfld.long 0x5BC 24. "NU1," "0,1"
bitfld.long 0x5BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5BC 0.--7. 1. "PARAM,"
line.long 0x5C0 "INST184_0,"
line.long 0x5C4 "INST184_1,"
hexmask.long.byte 0x5C4 25.--31. 1. "NU2,"
rbitfld.long 0x5C4 24. "NU1," "0,1"
bitfld.long 0x5C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5C4 0.--7. 1. "PARAM,"
line.long 0x5C8 "INST185_0,"
line.long 0x5CC "INST185_1,"
hexmask.long.byte 0x5CC 25.--31. 1. "NU2,"
rbitfld.long 0x5CC 24. "NU1," "0,1"
bitfld.long 0x5CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5CC 0.--7. 1. "PARAM,"
line.long 0x5D0 "INST186_0,"
line.long 0x5D4 "INST186_1,"
hexmask.long.byte 0x5D4 25.--31. 1. "NU2,"
rbitfld.long 0x5D4 24. "NU1," "0,1"
bitfld.long 0x5D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5D4 0.--7. 1. "PARAM,"
line.long 0x5D8 "INST187_0,"
line.long 0x5DC "INST187_1,"
hexmask.long.byte 0x5DC 25.--31. 1. "NU2,"
rbitfld.long 0x5DC 24. "NU1," "0,1"
bitfld.long 0x5DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5DC 0.--7. 1. "PARAM,"
line.long 0x5E0 "INST188_0,"
line.long 0x5E4 "INST188_1,"
hexmask.long.byte 0x5E4 25.--31. 1. "NU2,"
rbitfld.long 0x5E4 24. "NU1," "0,1"
bitfld.long 0x5E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5E4 0.--7. 1. "PARAM,"
line.long 0x5E8 "INST189_0,"
line.long 0x5EC "INST189_1,"
hexmask.long.byte 0x5EC 25.--31. 1. "NU2,"
rbitfld.long 0x5EC 24. "NU1," "0,1"
bitfld.long 0x5EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5EC 0.--7. 1. "PARAM,"
line.long 0x5F0 "INST190_0,"
line.long 0x5F4 "INST190_1,"
hexmask.long.byte 0x5F4 25.--31. 1. "NU2,"
rbitfld.long 0x5F4 24. "NU1," "0,1"
bitfld.long 0x5F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5F4 0.--7. 1. "PARAM,"
line.long 0x5F8 "INST191_0,"
line.long 0x5FC "INST191_1,"
hexmask.long.byte 0x5FC 25.--31. 1. "NU2,"
rbitfld.long 0x5FC 24. "NU1," "0,1"
bitfld.long 0x5FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x5FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x5FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x5FC 0.--7. 1. "PARAM,"
line.long 0x600 "INST192_0,"
line.long 0x604 "INST192_1,"
hexmask.long.byte 0x604 25.--31. 1. "NU2,"
rbitfld.long 0x604 24. "NU1," "0,1"
bitfld.long 0x604 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x604 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x604 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x604 0.--7. 1. "PARAM,"
line.long 0x608 "INST193_0,"
line.long 0x60C "INST193_1,"
hexmask.long.byte 0x60C 25.--31. 1. "NU2,"
rbitfld.long 0x60C 24. "NU1," "0,1"
bitfld.long 0x60C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x60C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x60C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x60C 0.--7. 1. "PARAM,"
line.long 0x610 "INST194_0,"
line.long 0x614 "INST194_1,"
hexmask.long.byte 0x614 25.--31. 1. "NU2,"
rbitfld.long 0x614 24. "NU1," "0,1"
bitfld.long 0x614 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x614 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x614 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x614 0.--7. 1. "PARAM,"
line.long 0x618 "INST195_0,"
line.long 0x61C "INST195_1,"
hexmask.long.byte 0x61C 25.--31. 1. "NU2,"
rbitfld.long 0x61C 24. "NU1," "0,1"
bitfld.long 0x61C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x61C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x61C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x61C 0.--7. 1. "PARAM,"
line.long 0x620 "INST196_0,"
line.long 0x624 "INST196_1,"
hexmask.long.byte 0x624 25.--31. 1. "NU2,"
rbitfld.long 0x624 24. "NU1," "0,1"
bitfld.long 0x624 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x624 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x624 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x624 0.--7. 1. "PARAM,"
line.long 0x628 "INST197_0,"
line.long 0x62C "INST197_1,"
hexmask.long.byte 0x62C 25.--31. 1. "NU2,"
rbitfld.long 0x62C 24. "NU1," "0,1"
bitfld.long 0x62C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x62C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x62C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x62C 0.--7. 1. "PARAM,"
line.long 0x630 "INST198_0,"
line.long 0x634 "INST198_1,"
hexmask.long.byte 0x634 25.--31. 1. "NU2,"
rbitfld.long 0x634 24. "NU1," "0,1"
bitfld.long 0x634 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x634 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x634 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x634 0.--7. 1. "PARAM,"
line.long 0x638 "INST199_0,"
line.long 0x63C "INST199_1,"
hexmask.long.byte 0x63C 25.--31. 1. "NU2,"
rbitfld.long 0x63C 24. "NU1," "0,1"
bitfld.long 0x63C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x63C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x63C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x63C 0.--7. 1. "PARAM,"
line.long 0x640 "INST200_0,"
line.long 0x644 "INST200_1,"
hexmask.long.byte 0x644 25.--31. 1. "NU2,"
rbitfld.long 0x644 24. "NU1," "0,1"
bitfld.long 0x644 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x644 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x644 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x644 0.--7. 1. "PARAM,"
line.long 0x648 "INST201_0,"
line.long 0x64C "INST201_1,"
hexmask.long.byte 0x64C 25.--31. 1. "NU2,"
rbitfld.long 0x64C 24. "NU1," "0,1"
bitfld.long 0x64C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x64C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x64C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x64C 0.--7. 1. "PARAM,"
line.long 0x650 "INST202_0,"
line.long 0x654 "INST202_1,"
hexmask.long.byte 0x654 25.--31. 1. "NU2,"
rbitfld.long 0x654 24. "NU1," "0,1"
bitfld.long 0x654 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x654 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x654 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x654 0.--7. 1. "PARAM,"
line.long 0x658 "INST203_0,"
line.long 0x65C "INST203_1,"
hexmask.long.byte 0x65C 25.--31. 1. "NU2,"
rbitfld.long 0x65C 24. "NU1," "0,1"
bitfld.long 0x65C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x65C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x65C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x65C 0.--7. 1. "PARAM,"
line.long 0x660 "INST204_0,"
line.long 0x664 "INST204_1,"
hexmask.long.byte 0x664 25.--31. 1. "NU2,"
rbitfld.long 0x664 24. "NU1," "0,1"
bitfld.long 0x664 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x664 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x664 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x664 0.--7. 1. "PARAM,"
line.long 0x668 "INST205_0,"
line.long 0x66C "INST205_1,"
hexmask.long.byte 0x66C 25.--31. 1. "NU2,"
rbitfld.long 0x66C 24. "NU1," "0,1"
bitfld.long 0x66C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x66C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x66C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x66C 0.--7. 1. "PARAM,"
line.long 0x670 "INST206_0,"
line.long 0x674 "INST206_1,"
hexmask.long.byte 0x674 25.--31. 1. "NU2,"
rbitfld.long 0x674 24. "NU1," "0,1"
bitfld.long 0x674 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x674 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x674 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x674 0.--7. 1. "PARAM,"
line.long 0x678 "INST207_0,"
line.long 0x67C "INST207_1,"
hexmask.long.byte 0x67C 25.--31. 1. "NU2,"
rbitfld.long 0x67C 24. "NU1," "0,1"
bitfld.long 0x67C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x67C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x67C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x67C 0.--7. 1. "PARAM,"
line.long 0x680 "INST208_0,"
line.long 0x684 "INST208_1,"
hexmask.long.byte 0x684 25.--31. 1. "NU2,"
rbitfld.long 0x684 24. "NU1," "0,1"
bitfld.long 0x684 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x684 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x684 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x684 0.--7. 1. "PARAM,"
line.long 0x688 "INST209_0,"
line.long 0x68C "INST209_1,"
hexmask.long.byte 0x68C 25.--31. 1. "NU2,"
rbitfld.long 0x68C 24. "NU1," "0,1"
bitfld.long 0x68C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x68C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x68C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x68C 0.--7. 1. "PARAM,"
line.long 0x690 "INST210_0,"
line.long 0x694 "INST210_1,"
hexmask.long.byte 0x694 25.--31. 1. "NU2,"
rbitfld.long 0x694 24. "NU1," "0,1"
bitfld.long 0x694 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x694 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x694 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x694 0.--7. 1. "PARAM,"
line.long 0x698 "INST211_0,"
line.long 0x69C "INST211_1,"
hexmask.long.byte 0x69C 25.--31. 1. "NU2,"
rbitfld.long 0x69C 24. "NU1," "0,1"
bitfld.long 0x69C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x69C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x69C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x69C 0.--7. 1. "PARAM,"
line.long 0x6A0 "INST212_0,"
line.long 0x6A4 "INST212_1,"
hexmask.long.byte 0x6A4 25.--31. 1. "NU2,"
rbitfld.long 0x6A4 24. "NU1," "0,1"
bitfld.long 0x6A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6A4 0.--7. 1. "PARAM,"
line.long 0x6A8 "INST213_0,"
line.long 0x6AC "INST213_1,"
hexmask.long.byte 0x6AC 25.--31. 1. "NU2,"
rbitfld.long 0x6AC 24. "NU1," "0,1"
bitfld.long 0x6AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6AC 0.--7. 1. "PARAM,"
line.long 0x6B0 "INST214_0,"
line.long 0x6B4 "INST214_1,"
hexmask.long.byte 0x6B4 25.--31. 1. "NU2,"
rbitfld.long 0x6B4 24. "NU1," "0,1"
bitfld.long 0x6B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6B4 0.--7. 1. "PARAM,"
line.long 0x6B8 "INST215_0,"
line.long 0x6BC "INST215_1,"
hexmask.long.byte 0x6BC 25.--31. 1. "NU2,"
rbitfld.long 0x6BC 24. "NU1," "0,1"
bitfld.long 0x6BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6BC 0.--7. 1. "PARAM,"
line.long 0x6C0 "INST216_0,"
line.long 0x6C4 "INST216_1,"
hexmask.long.byte 0x6C4 25.--31. 1. "NU2,"
rbitfld.long 0x6C4 24. "NU1," "0,1"
bitfld.long 0x6C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6C4 0.--7. 1. "PARAM,"
line.long 0x6C8 "INST217_0,"
line.long 0x6CC "INST217_1,"
hexmask.long.byte 0x6CC 25.--31. 1. "NU2,"
rbitfld.long 0x6CC 24. "NU1," "0,1"
bitfld.long 0x6CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6CC 0.--7. 1. "PARAM,"
line.long 0x6D0 "INST218_0,"
line.long 0x6D4 "INST218_1,"
hexmask.long.byte 0x6D4 25.--31. 1. "NU2,"
rbitfld.long 0x6D4 24. "NU1," "0,1"
bitfld.long 0x6D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6D4 0.--7. 1. "PARAM,"
line.long 0x6D8 "INST219_0,"
line.long 0x6DC "INST219_1,"
hexmask.long.byte 0x6DC 25.--31. 1. "NU2,"
rbitfld.long 0x6DC 24. "NU1," "0,1"
bitfld.long 0x6DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6DC 0.--7. 1. "PARAM,"
line.long 0x6E0 "INST220_0,"
line.long 0x6E4 "INST220_1,"
hexmask.long.byte 0x6E4 25.--31. 1. "NU2,"
rbitfld.long 0x6E4 24. "NU1," "0,1"
bitfld.long 0x6E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6E4 0.--7. 1. "PARAM,"
line.long 0x6E8 "INST221_0,"
line.long 0x6EC "INST221_1,"
hexmask.long.byte 0x6EC 25.--31. 1. "NU2,"
rbitfld.long 0x6EC 24. "NU1," "0,1"
bitfld.long 0x6EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6EC 0.--7. 1. "PARAM,"
line.long 0x6F0 "INST222_0,"
line.long 0x6F4 "INST222_1,"
hexmask.long.byte 0x6F4 25.--31. 1. "NU2,"
rbitfld.long 0x6F4 24. "NU1," "0,1"
bitfld.long 0x6F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6F4 0.--7. 1. "PARAM,"
line.long 0x6F8 "INST223_0,"
line.long 0x6FC "INST223_1,"
hexmask.long.byte 0x6FC 25.--31. 1. "NU2,"
rbitfld.long 0x6FC 24. "NU1," "0,1"
bitfld.long 0x6FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x6FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x6FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x6FC 0.--7. 1. "PARAM,"
line.long 0x700 "INST224_0,"
line.long 0x704 "INST224_1,"
hexmask.long.byte 0x704 25.--31. 1. "NU2,"
rbitfld.long 0x704 24. "NU1," "0,1"
bitfld.long 0x704 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x704 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x704 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x704 0.--7. 1. "PARAM,"
line.long 0x708 "INST225_0,"
line.long 0x70C "INST225_1,"
hexmask.long.byte 0x70C 25.--31. 1. "NU2,"
rbitfld.long 0x70C 24. "NU1," "0,1"
bitfld.long 0x70C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x70C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x70C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x70C 0.--7. 1. "PARAM,"
line.long 0x710 "INST226_0,"
line.long 0x714 "INST226_1,"
hexmask.long.byte 0x714 25.--31. 1. "NU2,"
rbitfld.long 0x714 24. "NU1," "0,1"
bitfld.long 0x714 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x714 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x714 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x714 0.--7. 1. "PARAM,"
line.long 0x718 "INST227_0,"
line.long 0x71C "INST227_1,"
hexmask.long.byte 0x71C 25.--31. 1. "NU2,"
rbitfld.long 0x71C 24. "NU1," "0,1"
bitfld.long 0x71C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x71C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x71C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x71C 0.--7. 1. "PARAM,"
line.long 0x720 "INST228_0,"
line.long 0x724 "INST228_1,"
hexmask.long.byte 0x724 25.--31. 1. "NU2,"
rbitfld.long 0x724 24. "NU1," "0,1"
bitfld.long 0x724 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x724 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x724 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x724 0.--7. 1. "PARAM,"
line.long 0x728 "INST229_0,"
line.long 0x72C "INST229_1,"
hexmask.long.byte 0x72C 25.--31. 1. "NU2,"
rbitfld.long 0x72C 24. "NU1," "0,1"
bitfld.long 0x72C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x72C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x72C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x72C 0.--7. 1. "PARAM,"
line.long 0x730 "INST230_0,"
line.long 0x734 "INST230_1,"
hexmask.long.byte 0x734 25.--31. 1. "NU2,"
rbitfld.long 0x734 24. "NU1," "0,1"
bitfld.long 0x734 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x734 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x734 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x734 0.--7. 1. "PARAM,"
line.long 0x738 "INST231_0,"
line.long 0x73C "INST231_1,"
hexmask.long.byte 0x73C 25.--31. 1. "NU2,"
rbitfld.long 0x73C 24. "NU1," "0,1"
bitfld.long 0x73C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x73C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x73C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x73C 0.--7. 1. "PARAM,"
line.long 0x740 "INST232_0,"
line.long 0x744 "INST232_1,"
hexmask.long.byte 0x744 25.--31. 1. "NU2,"
rbitfld.long 0x744 24. "NU1," "0,1"
bitfld.long 0x744 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x744 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x744 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x744 0.--7. 1. "PARAM,"
line.long 0x748 "INST233_0,"
line.long 0x74C "INST233_1,"
hexmask.long.byte 0x74C 25.--31. 1. "NU2,"
rbitfld.long 0x74C 24. "NU1," "0,1"
bitfld.long 0x74C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x74C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x74C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x74C 0.--7. 1. "PARAM,"
line.long 0x750 "INST234_0,"
line.long 0x754 "INST234_1,"
hexmask.long.byte 0x754 25.--31. 1. "NU2,"
rbitfld.long 0x754 24. "NU1," "0,1"
bitfld.long 0x754 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x754 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x754 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x754 0.--7. 1. "PARAM,"
line.long 0x758 "INST235_0,"
line.long 0x75C "INST235_1,"
hexmask.long.byte 0x75C 25.--31. 1. "NU2,"
rbitfld.long 0x75C 24. "NU1," "0,1"
bitfld.long 0x75C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x75C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x75C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x75C 0.--7. 1. "PARAM,"
line.long 0x760 "INST236_0,"
line.long 0x764 "INST236_1,"
hexmask.long.byte 0x764 25.--31. 1. "NU2,"
rbitfld.long 0x764 24. "NU1," "0,1"
bitfld.long 0x764 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x764 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x764 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x764 0.--7. 1. "PARAM,"
line.long 0x768 "INST237_0,"
line.long 0x76C "INST237_1,"
hexmask.long.byte 0x76C 25.--31. 1. "NU2,"
rbitfld.long 0x76C 24. "NU1," "0,1"
bitfld.long 0x76C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x76C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x76C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x76C 0.--7. 1. "PARAM,"
line.long 0x770 "INST238_0,"
line.long 0x774 "INST238_1,"
hexmask.long.byte 0x774 25.--31. 1. "NU2,"
rbitfld.long 0x774 24. "NU1," "0,1"
bitfld.long 0x774 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x774 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x774 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x774 0.--7. 1. "PARAM,"
line.long 0x778 "INST239_0,"
line.long 0x77C "INST239_1,"
hexmask.long.byte 0x77C 25.--31. 1. "NU2,"
rbitfld.long 0x77C 24. "NU1," "0,1"
bitfld.long 0x77C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x77C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x77C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x77C 0.--7. 1. "PARAM,"
line.long 0x780 "INST240_0,"
line.long 0x784 "INST240_1,"
hexmask.long.byte 0x784 25.--31. 1. "NU2,"
rbitfld.long 0x784 24. "NU1," "0,1"
bitfld.long 0x784 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x784 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x784 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x784 0.--7. 1. "PARAM,"
line.long 0x788 "INST241_0,"
line.long 0x78C "INST241_1,"
hexmask.long.byte 0x78C 25.--31. 1. "NU2,"
rbitfld.long 0x78C 24. "NU1," "0,1"
bitfld.long 0x78C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x78C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x78C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x78C 0.--7. 1. "PARAM,"
line.long 0x790 "INST242_0,"
line.long 0x794 "INST242_1,"
hexmask.long.byte 0x794 25.--31. 1. "NU2,"
rbitfld.long 0x794 24. "NU1," "0,1"
bitfld.long 0x794 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x794 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x794 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x794 0.--7. 1. "PARAM,"
line.long 0x798 "INST243_0,"
line.long 0x79C "INST243_1,"
hexmask.long.byte 0x79C 25.--31. 1. "NU2,"
rbitfld.long 0x79C 24. "NU1," "0,1"
bitfld.long 0x79C 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x79C 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x79C 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x79C 0.--7. 1. "PARAM,"
line.long 0x7A0 "INST244_0,"
line.long 0x7A4 "INST244_1,"
hexmask.long.byte 0x7A4 25.--31. 1. "NU2,"
rbitfld.long 0x7A4 24. "NU1," "0,1"
bitfld.long 0x7A4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7A4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7A4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7A4 0.--7. 1. "PARAM,"
line.long 0x7A8 "INST245_0,"
line.long 0x7AC "INST245_1,"
hexmask.long.byte 0x7AC 25.--31. 1. "NU2,"
rbitfld.long 0x7AC 24. "NU1," "0,1"
bitfld.long 0x7AC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7AC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7AC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7AC 0.--7. 1. "PARAM,"
line.long 0x7B0 "INST246_0,"
line.long 0x7B4 "INST246_1,"
hexmask.long.byte 0x7B4 25.--31. 1. "NU2,"
rbitfld.long 0x7B4 24. "NU1," "0,1"
bitfld.long 0x7B4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7B4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7B4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7B4 0.--7. 1. "PARAM,"
line.long 0x7B8 "INST247_0,"
line.long 0x7BC "INST247_1,"
hexmask.long.byte 0x7BC 25.--31. 1. "NU2,"
rbitfld.long 0x7BC 24. "NU1," "0,1"
bitfld.long 0x7BC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7BC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7BC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7BC 0.--7. 1. "PARAM,"
line.long 0x7C0 "INST248_0,"
line.long 0x7C4 "INST248_1,"
hexmask.long.byte 0x7C4 25.--31. 1. "NU2,"
rbitfld.long 0x7C4 24. "NU1," "0,1"
bitfld.long 0x7C4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7C4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7C4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7C4 0.--7. 1. "PARAM,"
line.long 0x7C8 "INST249_0,"
line.long 0x7CC "INST249_1,"
hexmask.long.byte 0x7CC 25.--31. 1. "NU2,"
rbitfld.long 0x7CC 24. "NU1," "0,1"
bitfld.long 0x7CC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7CC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7CC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7CC 0.--7. 1. "PARAM,"
line.long 0x7D0 "INST250_0,"
line.long 0x7D4 "INST250_1,"
hexmask.long.byte 0x7D4 25.--31. 1. "NU2,"
rbitfld.long 0x7D4 24. "NU1," "0,1"
bitfld.long 0x7D4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7D4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7D4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7D4 0.--7. 1. "PARAM,"
line.long 0x7D8 "INST251_0,"
line.long 0x7DC "INST251_1,"
hexmask.long.byte 0x7DC 25.--31. 1. "NU2,"
rbitfld.long 0x7DC 24. "NU1," "0,1"
bitfld.long 0x7DC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7DC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7DC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7DC 0.--7. 1. "PARAM,"
line.long 0x7E0 "INST252_0,"
line.long 0x7E4 "INST252_1,"
hexmask.long.byte 0x7E4 25.--31. 1. "NU2,"
rbitfld.long 0x7E4 24. "NU1," "0,1"
bitfld.long 0x7E4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7E4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7E4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7E4 0.--7. 1. "PARAM,"
line.long 0x7E8 "INST253_0,"
line.long 0x7EC "INST253_1,"
hexmask.long.byte 0x7EC 25.--31. 1. "NU2,"
rbitfld.long 0x7EC 24. "NU1," "0,1"
bitfld.long 0x7EC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7EC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7EC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7EC 0.--7. 1. "PARAM,"
line.long 0x7F0 "INST254_0,"
line.long 0x7F4 "INST254_1,"
hexmask.long.byte 0x7F4 25.--31. 1. "NU2,"
rbitfld.long 0x7F4 24. "NU1," "0,1"
bitfld.long 0x7F4 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7F4 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7F4 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7F4 0.--7. 1. "PARAM,"
line.long 0x7F8 "INST255_0,"
line.long 0x7FC "INST255_1,"
hexmask.long.byte 0x7FC 25.--31. 1. "NU2,"
rbitfld.long 0x7FC 24. "NU1," "0,1"
bitfld.long 0x7FC 23. "CHIRP_BRK," "0,1"
hexmask.long.byte 0x7FC 16.--22. 1. "SKIP_SAMPLES,"
hexmask.long.byte 0x7FC 8.--15. 1. "COLLECT_SAMPLES,"
hexmask.long.byte 0x7FC 0.--7. 1. "PARAM,"
width 0x0B
tree.end
tree "MSS_GPADC_REG (MSS GPADC REG Module Registers)"
base ad:0x3F79800
group.long 0x00++0x4F
line.long 0x00 "REG0,gpadc modes and enable"
hexmask.long.word 0x00 17.--31. 1. "NU3,TI reserved"
bitfld.long 0x00 16. "GPADC_DEBUG_MODE_ENABLE," "0,1"
rbitfld.long 0x00 12.--15. "NU2,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 9.--11. "GPADC2ADCBUF_PATH_EN,TI reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8. "GPADC_FSM_CLK_ENABLE,Enable the clock to gpadc fsm" "0,1"
rbitfld.long 0x00 2.--7. "NU1,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 0.--1. "DCBIST_MODE," "0,1,2,3"
line.long 0x04 "REG1,gpadc start trigger for Inter frame mode"
hexmask.long.byte 0x04 25.--31. 1. "NU4,TI reserved"
bitfld.long 0x04 24. "GPADC_START_BYP_VAL," "0,1"
hexmask.long.byte 0x04 17.--23. 1. "NU3,TI reserved"
bitfld.long 0x04 16. "GPADC_FSM_BYPASS," "0,1"
newline
hexmask.long.byte 0x04 9.--15. 1. "NU2,TI reserved"
bitfld.long 0x04 8. "GPADC_INIT,Resets the FSM and clears the data RAM" "0,1"
hexmask.long.byte 0x04 1.--7. 1. "NU1,TI reserved"
bitfld.long 0x04 0. "GPADC_TRIGGER,Generates a single cycle pulse to trigger the IFM mode" "0,1"
line.long 0x08 "REG2,gpadc config for IFM"
line.long 0x0C "REG3,gpadc param. skip samples and collect samples for IFM"
hexmask.long.word 0x0C 23.--31. 1. "NU,"
hexmask.long.byte 0x0C 16.--22. 1. "SKIP_SAMPLES_IFM,number of GPADC clocks to skip after trigger"
hexmask.long.byte 0x0C 8.--15. 1. "COLLECT_SAMPLES_IFM,number of GPADC readings to collect"
hexmask.long.byte 0x0C 0.--7. 1. "PARAM_VAL_IFM,Param value to be passed to analog in IFM mode(after one hot encoding)"
line.long 0x10 "REG4,Base address for Chirp profile 0 in instruction packet RAM"
hexmask.long.byte 0x10 24.--31. 1. "PKT_RAM_BASE_ADDR_CP3,TI reserved"
hexmask.long.byte 0x10 16.--23. 1. "PKT_RAM_BASE_ADDR_CP2,TI reserved"
hexmask.long.byte 0x10 8.--15. 1. "PKT_RAM_BASE_ADDR_CP1,(End-Address + 1) of instruction-ram in CTM mode"
hexmask.long.byte 0x10 0.--7. 1. "PKT_RAM_BASE_ADDR_CP0,Start Address of instruction-ram in CTM mode"
line.long 0x14 "REG5,Base address for Chirp profile 1 in instruction packet RAM"
hexmask.long.byte 0x14 24.--31. 1. "PKT_RAM_BASE_ADDR_CP7,TI reserved"
hexmask.long.byte 0x14 16.--23. 1. "PKT_RAM_BASE_ADDR_CP6,TI reserved"
hexmask.long.byte 0x14 8.--15. 1. "PKT_RAM_BASE_ADDR_CP5,TI reserved"
hexmask.long.byte 0x14 0.--7. 1. "PKT_RAM_BASE_ADDR_CP4,TI reserved"
line.long 0x18 "REG6,Base address for Chirp profile 2 in instruction packet RAM"
hexmask.long.byte 0x18 24.--31. 1. "PKT_RAM_BASE_ADDR_CP11,TI reserved"
hexmask.long.byte 0x18 16.--23. 1. "PKT_RAM_BASE_ADDR_CP10,TI reserved"
hexmask.long.byte 0x18 8.--15. 1. "PKT_RAM_BASE_ADDR_CP9,TI reserved"
hexmask.long.byte 0x18 0.--7. 1. "PKT_RAM_BASE_ADDR_CP8,TI reserved"
line.long 0x1C "REG7,Base address for Chirp profile 3 in instruction packet RAM"
hexmask.long.byte 0x1C 24.--31. 1. "PKT_RAM_BASE_ADDR_CP15,TI reserved"
hexmask.long.byte 0x1C 16.--23. 1. "PKT_RAM_BASE_ADDR_CP14,TI reserved"
hexmask.long.byte 0x1C 8.--15. 1. "PKT_RAM_BASE_ADDR_CP13,TI reserved"
hexmask.long.byte 0x1C 0.--7. 1. "PKT_RAM_BASE_ADDR_CP12,TI reserved"
line.long 0x20 "REG8,"
hexmask.long.tbyte 0x20 9.--31. 1. "NU,"
bitfld.long 0x20 8. "GPADC_CLK_ENABLE,TI reserved" "0,1"
hexmask.long.byte 0x20 0.--7. 1. "GPADC_CLK_DIV,TI reserved"
line.long 0x24 "REG9,"
line.long 0x28 "REG10,"
line.long 0x2C "REG11,"
line.long 0x30 "REG12,"
hexmask.long.byte 0x30 24.--31. 1. "DRAM_REPAIRED_BIT,TI reserved"
hexmask.long.byte 0x30 16.--23. 1. "DRAM_ECC_ERR_ADDR,TI reserved"
hexmask.long.byte 0x30 9.--15. 1. "NU2,TI reserved"
bitfld.long 0x30 8. "DRAM_ECC_ERR_CLR,TI reserved" "0,1"
newline
hexmask.long.byte 0x30 1.--7. 1. "NU1,TI reserved"
bitfld.long 0x30 0. "DRAM_ECC_ENABLE," "0,1"
line.long 0x34 "REG13,"
line.long 0x38 "REG14,Sum of GP ADC readings"
hexmask.long.word 0x38 20.--31. 1. "NU,TI reserved"
hexmask.long.tbyte 0x38 0.--19. 1. "SUM_IFM,Sum of GP ADC readings"
line.long 0x3C "REG15,Min and Max of GP ADC readings"
bitfld.long 0x3C 26.--31. "NU2,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x3C 16.--25. 1. "MAX_GPADC,Max of GPADC readings"
bitfld.long 0x3C 10.--15. "NU1,TI reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x3C 0.--9. 1. "MIN_GPADC,Min of GPADC readings"
line.long 0x40 "REG16,"
hexmask.long 0x40 1.--31. 1. "NU,TI reserved"
bitfld.long 0x40 0. "GPADC_MEM_INIT_DONE_STAT,Status for Data Mem init done.Used for FW polling .Will read '0' when init process is under progress" "0,1"
line.long 0x44 "REG17,"
hexmask.long 0x44 1.--31. 1. "NU,TI reserved"
bitfld.long 0x44 0. "GPADC_IFM_DONE_STATUS,Test completion status in IFM mode.Used for FW polling" "0,1"
line.long 0x48 "REG18,"
hexmask.long 0x48 1.--31. 1. "NU,TI reserved"
bitfld.long 0x48 0. "GPADC_IFM_DONE_CLR,Clear 'ifm_done_status'" "0,1"
line.long 0x4C "REG19,"
hexmask.long.word 0x4C 16.--31. 1. "NU,TI reserved"
hexmask.long.word 0x4C 0.--15. 1. "GPADC_SAMPLES_FRAME,Total number of GPADC samples collected in a frame"
group.long 0x58++0x03
line.long 0x00 "REG22,"
repeat 2. (list 20. 21. )(list 0x00 0x04 )
rgroup.long ($2+0x50)++0x03
line.long 0x00 "REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_I2C (MSS I2C Module Registers)"
base ad:0x2F7B000
group.long 0x00++0x3F
line.long 0x00 "ICOAR,I2C Own Address register"
hexmask.long.tbyte 0x00 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x00 0.--9. 1. "A9_A0,Own address"
line.long 0x04 "ICIMR,I2C Interrupt Mask/Status register"
hexmask.long 0x04 7.--31. 1. "NU,Reserved"
bitfld.long 0x04 6. "AAS,Address As Slave interrupt mask bit" "0,1"
newline
bitfld.long 0x04 5. "SCD,Stop Condition Detection mask bit" "0,1"
bitfld.long 0x04 4. "ICXRDY,Transmit Data Ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 3. "ICRRDY,Receive Data Ready interrupt mask bit" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 1. "NACK,No Acknowledgement interrupt mask bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration Lost interrupt mask bit" "0,1"
line.long 0x08 "ICSTR,I2C Interrupt Status register"
hexmask.long.tbyte 0x08 15.--31. 1. "NU2,Reserved"
bitfld.long 0x08 14. "SDIR,Slave Direction" "0,1"
newline
bitfld.long 0x08 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'" "0,1"
bitfld.long 0x08 12. "BB,Bus Busy" "0,1"
newline
bitfld.long 0x08 11. "RSFULL,Receive shift full" "0,1"
bitfld.long 0x08 10. "XSMT,Transmit shift empty not" "0,1"
newline
bitfld.long 0x08 9. "AAS,Address As Slave" "0,1"
bitfld.long 0x08 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call)" "0,1"
newline
bitfld.long 0x08 6.--7. "NU1,Reserved" "0,1,2,3"
bitfld.long 0x08 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition" "0,1"
newline
bitfld.long 0x08 4. "ICXRDY,Transmit Data Ready interrupt flag bit" "0,1"
bitfld.long 0x08 3. "ICRRDY,Receive Data Ready interrupt flag bit" "0,1"
newline
bitfld.long 0x08 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
bitfld.long 0x08 1. "NACK,No-Acknowledgement interrupt flag bit" "0,1"
newline
bitfld.long 0x08 0. "AL,Arbitration-Lost interrupt flag bit" "0,1"
line.long 0x0C "ICCLKL,I2C Clock Divider Low register"
hexmask.long.word 0x0C 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "ICCL15_ICCL0,Low time I2C SCL Clock Division Factor"
line.long 0x10 "ICCLKH,I2C Clock Divider High register"
hexmask.long.word 0x10 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I2C SCL Clock Division Factor"
line.long 0x14 "ICCNT,I2C Data Count register"
hexmask.long.word 0x14 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count"
line.long 0x18 "ICDRR,I2C Data Receive register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data"
line.long 0x1C "ICSAR,I2C Slave Address register"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address"
line.long 0x20 "ICDXR,I2C Data Transmit register"
hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data"
line.long 0x24 "ICMDR,I2C Mode register"
hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved"
bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode" "0,1"
newline
bitfld.long 0x24 14. "FREE,Free Running" "0,1"
bitfld.long 0x24 13. "STT,Start Condition (Master only mode)" "0,1"
newline
bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509)" "0,1"
bitfld.long 0x24 11. "STP,Stop Condition (Master mode only)" "0,1"
newline
bitfld.long 0x24 10. "MST,Master" "0,1"
bitfld.long 0x24 9. "TRX,Transmitter" "0,1"
newline
bitfld.long 0x24 8. "XA,Expanded Address" "0,1"
bitfld.long 0x24 7. "RM,Repeat Mode" "0,1"
newline
bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only)" "0,1"
bitfld.long 0x24 5. "IRS,I2C Reset Not" "0,1"
newline
bitfld.long 0x24 4. "STB,Start Byte (Master only mode)" "0,1"
bitfld.long 0x24 3. "FDF,Free Data Format" "0,1"
newline
bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted" "0,1,2,3,4,5,6,7"
line.long 0x28 "ICIVR,I2C Interrupt Vector register"
hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved"
bitfld.long 0x28 8.--11. "TESTMD,Reserved for internal testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 3.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--2. "INTCODE,Interrupt code" "0,1,2,3,4,5,6,7"
line.long 0x2C "ICEMDR,I2C Extended Mode register"
hexmask.long 0x2C 2.--31. 1. "NU,Reserved"
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave" "0,1"
newline
bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode" "0,1"
line.long 0x30 "ICPSC,I2C Prescaler register"
hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module"
line.long 0x34 "ICPID1,I2C Peripheral ID register 1"
hexmask.long.word 0x34 16.--31. 1. "NU,Reserved"
hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral"
newline
hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C"
line.long 0x38 "ICPID2,I2C Peripheral ID register 2"
hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral"
line.long 0x3C "ICDMAC,I2C DMA Control Register"
hexmask.long 0x3C 2.--31. 1. "NU,Reserved"
bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable" "0,1"
newline
bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable" "0,1"
group.long 0x48++0x1B
line.long 0x00 "ICPFUNC,I2C Pin Function register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved"
bitfld.long 0x00 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins" "Pins function as SCL and SDA,Pins functions as GPIO"
line.long 0x04 "ICPDIR,I2C Pin Direction register"
hexmask.long 0x04 2.--31. 1. "NU,Reserved"
bitfld.long 0x04 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO" "SDA pin functions as input,SDA pin functions as output"
newline
bitfld.long 0x04 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO" "SCL pin functions as input,SCL pin functions as output"
line.long 0x08 "ICPDIN,I2C Pin Data In register"
hexmask.long 0x08 2.--31. 1. "NU,Reserved"
bitfld.long 0x08 1. "PDIN1,Indicates the logic level present on the SDA pin" "Logic low present at SDA pin regardless of PFUNC..,Logic high present at SDA pin regardless of.."
newline
bitfld.long 0x08 0. "PDIN0,Indicates the logic level present on the SCL pin" "Logic low present at SCL pin regardless of PFUNC..,Logic high present at SCL pin regardless of.."
line.long 0x0C "ICPDOUT,I2C Pin Data Out register"
hexmask.long 0x0C 2.--31. 1. "NU,Reserved"
bitfld.long 0x0C 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output" "SDA pin driven low,SDA pin driven high"
newline
bitfld.long 0x0C 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output" "SCL pin driven low,SCL pin driven high"
line.long 0x10 "ICPDSET,I2C Pin Data Set register"
hexmask.long 0x10 2.--31. 1. "NU,Reserved"
bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin" "no effect,PDOUT[1] bit is set to.."
newline
bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin" "no effect,PDOUT[0] bit is set to.."
line.long 0x14 "ICPDCLR,I2C Pin Data Clear register"
hexmask.long 0x14 2.--31. 1. "NU,Reserved"
bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin" "no effect,PDOUT[1] bit is cleared.."
newline
bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin" "no effect,PDOUT[0] bit is cleared.."
line.long 0x18 "ICPDRV,I2C Pin Driver Mode Register"
hexmask.long 0x18 2.--31. 1. "NU,Reserved"
bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin" "I2C mode,GPIO mode"
newline
bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin" "I2C mode,GPIO mode"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "I2C_RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_IOMUX (MSS IOMUX Module Registers)"
base ad:0x20C0000
group.long 0x00++0x1DF
line.long 0x00 "PADAA_cfg_reg,"
hexmask.long.tbyte 0x00 11.--31. 1. "NU,Reserved"
bitfld.long 0x00 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x00 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x00 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x00 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x00 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x00 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x00 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x00 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PADAB_cfg_reg,"
hexmask.long.tbyte 0x04 11.--31. 1. "NU,Reserved"
bitfld.long 0x04 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x04 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x04 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x04 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x04 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x04 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x04 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x04 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "PADAC_cfg_reg,"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved"
bitfld.long 0x08 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x08 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x08 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x08 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x08 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x08 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x08 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x08 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "PADAD_cfg_reg,"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved"
bitfld.long 0x0C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x0C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x0C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x0C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x0C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x0C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x0C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x0C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "PADAE_cfg_reg,"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved"
bitfld.long 0x10 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x10 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x10 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x10 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x10 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x10 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x10 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x10 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "PADAF_cfg_reg,"
hexmask.long.tbyte 0x14 11.--31. 1. "NU,Reserved"
bitfld.long 0x14 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x14 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x14 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x14 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x14 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x14 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x14 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x14 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "PADAG_cfg_reg,"
hexmask.long.tbyte 0x18 11.--31. 1. "NU,Reserved"
bitfld.long 0x18 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x18 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x18 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x18 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x18 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x18 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x18 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x18 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "PADAH_cfg_reg,"
hexmask.long.tbyte 0x1C 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "PADAI_cfg_reg,"
hexmask.long.tbyte 0x20 11.--31. 1. "NU,Reserved"
bitfld.long 0x20 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x20 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x20 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x20 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x20 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x20 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x20 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x20 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "PADAJ_cfg_reg,"
hexmask.long.tbyte 0x24 11.--31. 1. "NU,Reserved"
bitfld.long 0x24 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x24 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x24 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x24 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x24 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x24 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x24 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x24 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "PADAK_cfg_reg,"
hexmask.long.tbyte 0x28 11.--31. 1. "NU,Reserved"
bitfld.long 0x28 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x28 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x28 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x28 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x28 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x28 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x28 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x28 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "PADAL_cfg_reg,"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU,Reserved"
bitfld.long 0x2C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x2C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x2C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x2C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x2C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x2C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x2C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x2C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "PADAM_cfg_reg,"
hexmask.long.tbyte 0x30 11.--31. 1. "NU,Reserved"
bitfld.long 0x30 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x30 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x30 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x30 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x30 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x30 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x30 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x30 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "PADAN_cfg_reg,"
hexmask.long.tbyte 0x34 11.--31. 1. "NU,Reserved"
bitfld.long 0x34 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x34 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x34 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x34 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x34 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x34 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x34 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x34 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "PADAO_cfg_reg,"
hexmask.long.tbyte 0x38 11.--31. 1. "NU,Reserved"
bitfld.long 0x38 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x38 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x38 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x38 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x38 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x38 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x38 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x38 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "PADAP_cfg_reg,"
hexmask.long.tbyte 0x3C 11.--31. 1. "NU,Reserved"
bitfld.long 0x3C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x3C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x3C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x3C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x3C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x3C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x3C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x3C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "PADAQ_cfg_reg,"
hexmask.long.tbyte 0x40 11.--31. 1. "NU,Reserved"
bitfld.long 0x40 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x40 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x40 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x40 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x40 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x40 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x40 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x40 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "PADAR_cfg_reg,"
hexmask.long.tbyte 0x44 11.--31. 1. "NU,Reserved"
bitfld.long 0x44 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x44 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x44 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x44 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x44 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x44 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x44 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x44 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "PADAS_cfg_reg,"
hexmask.long.tbyte 0x48 11.--31. 1. "NU,Reserved"
bitfld.long 0x48 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x48 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x48 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x48 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x48 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x48 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x48 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x48 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "PADAT_cfg_reg,"
hexmask.long.tbyte 0x4C 11.--31. 1. "NU,Reserved"
bitfld.long 0x4C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x4C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x4C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x4C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x4C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x4C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x4C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x4C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "PADAU_cfg_reg,"
hexmask.long.tbyte 0x50 11.--31. 1. "NU,Reserved"
bitfld.long 0x50 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x50 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x50 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x50 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x50 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x50 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x50 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x50 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "PADAV_cfg_reg,"
hexmask.long.tbyte 0x54 11.--31. 1. "NU,Reserved"
bitfld.long 0x54 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x54 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x54 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x54 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x54 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x54 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x54 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x54 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "PADAW_cfg_reg,"
hexmask.long.tbyte 0x58 11.--31. 1. "NU,Reserved"
bitfld.long 0x58 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x58 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x58 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x58 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x58 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x58 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x58 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x58 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "PADAX_cfg_reg,"
hexmask.long.tbyte 0x5C 11.--31. 1. "NU,Reserved"
bitfld.long 0x5C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x5C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x5C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x5C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x5C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x5C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x5C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x5C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x60 "PADAY_cfg_reg,"
hexmask.long.tbyte 0x60 11.--31. 1. "NU,Reserved"
bitfld.long 0x60 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x60 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x60 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x60 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x60 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x60 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x60 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x60 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "PADAZ_cfg_reg,"
hexmask.long.tbyte 0x64 11.--31. 1. "NU,Reserved"
bitfld.long 0x64 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x64 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x64 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x64 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x64 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x64 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x64 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x64 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "PADBA_cfg_reg,"
hexmask.long.tbyte 0x68 11.--31. 1. "NU,Reserved"
bitfld.long 0x68 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x68 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x68 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x68 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x68 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x68 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x68 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x68 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "PADBB_cfg_reg,"
hexmask.long.tbyte 0x6C 11.--31. 1. "NU,Reserved"
bitfld.long 0x6C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x6C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x6C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x6C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x6C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x6C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x6C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x6C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "PADBC_cfg_reg,"
hexmask.long.tbyte 0x70 11.--31. 1. "NU,Reserved"
bitfld.long 0x70 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x70 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x70 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x70 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x70 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x70 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x70 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x70 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x74 "PADBD_cfg_reg,"
hexmask.long.tbyte 0x74 11.--31. 1. "NU,Reserved"
bitfld.long 0x74 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x74 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x74 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x74 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x74 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x74 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x74 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x74 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x78 "PADBE_cfg_reg,"
hexmask.long.tbyte 0x78 11.--31. 1. "NU,Reserved"
bitfld.long 0x78 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x78 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x78 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x78 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x78 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x78 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x78 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x78 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x7C "PADBF_cfg_reg,"
hexmask.long.tbyte 0x7C 11.--31. 1. "NU,Reserved"
bitfld.long 0x7C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x7C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x7C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x7C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x7C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x7C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x7C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x7C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x80 "PADBG_cfg_reg,"
hexmask.long.tbyte 0x80 11.--31. 1. "NU,Reserved"
bitfld.long 0x80 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x80 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x80 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x80 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x80 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x80 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x80 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x80 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "PADBH_cfg_reg,"
hexmask.long.tbyte 0x84 11.--31. 1. "NU,Reserved"
bitfld.long 0x84 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x84 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x84 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x84 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x84 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x84 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x84 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x84 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "PADBI_cfg_reg,"
hexmask.long.tbyte 0x88 11.--31. 1. "NU,Reserved"
bitfld.long 0x88 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x88 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x88 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x88 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x88 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x88 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x88 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x88 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "PADBJ_cfg_reg,"
hexmask.long.tbyte 0x8C 11.--31. 1. "NU,Reserved"
bitfld.long 0x8C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x8C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x8C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x8C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x8C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x8C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x8C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x8C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "PADBK_cfg_reg,"
hexmask.long.tbyte 0x90 11.--31. 1. "NU,Reserved"
bitfld.long 0x90 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x90 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x90 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x90 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x90 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x90 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x90 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x90 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x94 "PADBL_cfg_reg,"
hexmask.long.tbyte 0x94 11.--31. 1. "NU,Reserved"
bitfld.long 0x94 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x94 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x94 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x94 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x94 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x94 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x94 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x94 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x98 "PADBM_cfg_reg,"
hexmask.long.tbyte 0x98 11.--31. 1. "NU,Reserved"
bitfld.long 0x98 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x98 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x98 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x98 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x98 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x98 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x98 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x98 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "PADBN_cfg_reg,"
hexmask.long.tbyte 0x9C 11.--31. 1. "NU,Reserved"
bitfld.long 0x9C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x9C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x9C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x9C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x9C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x9C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x9C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x9C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA0 "PADBO_cfg_reg,"
hexmask.long.tbyte 0xA0 11.--31. 1. "NU,Reserved"
bitfld.long 0xA0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xA0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xA0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xA0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xA0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xA0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xA0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xA0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "PADBP_cfg_reg,"
hexmask.long.tbyte 0xA4 11.--31. 1. "NU,Reserved"
bitfld.long 0xA4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xA4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xA4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xA4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xA4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xA4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xA4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xA4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA8 "PADBQ_cfg_reg,"
hexmask.long.tbyte 0xA8 11.--31. 1. "NU,Reserved"
bitfld.long 0xA8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xA8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xA8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xA8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xA8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xA8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xA8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xA8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xAC "PADBR_cfg_reg,"
hexmask.long.tbyte 0xAC 11.--31. 1. "NU,Reserved"
bitfld.long 0xAC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xAC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xAC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xAC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xAC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xAC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xAC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xAC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB0 "PADBS_cfg_reg,"
hexmask.long.tbyte 0xB0 11.--31. 1. "NU,Reserved"
bitfld.long 0xB0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xB0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xB0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xB0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xB0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xB0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xB0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xB0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB4 "PADBT_cfg_reg,"
hexmask.long.tbyte 0xB4 11.--31. 1. "NU,Reserved"
bitfld.long 0xB4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xB4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xB4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xB4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xB4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xB4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xB4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xB4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "PADBU_cfg_reg,"
hexmask.long.tbyte 0xB8 11.--31. 1. "NU,Reserved"
bitfld.long 0xB8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xB8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xB8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xB8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xB8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xB8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xB8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xB8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xBC "PADBV_cfg_reg,"
hexmask.long.tbyte 0xBC 11.--31. 1. "NU,Reserved"
bitfld.long 0xBC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xBC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xBC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xBC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xBC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xBC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xBC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xBC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC0 "PADBW_cfg_reg,"
hexmask.long.tbyte 0xC0 11.--31. 1. "NU,Reserved"
bitfld.long 0xC0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xC0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xC0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xC0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xC0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xC0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xC0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xC0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "PADBX_cfg_reg,"
hexmask.long.tbyte 0xC4 11.--31. 1. "NU,Reserved"
bitfld.long 0xC4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xC4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xC4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xC4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xC4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xC4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xC4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xC4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "PADBY_cfg_reg,"
hexmask.long.tbyte 0xC8 11.--31. 1. "NU,Reserved"
bitfld.long 0xC8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xC8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xC8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xC8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xC8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xC8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xC8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xC8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "PADBZ_cfg_reg,"
hexmask.long.tbyte 0xCC 11.--31. 1. "NU,Reserved"
bitfld.long 0xCC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xCC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xCC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xCC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xCC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xCC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xCC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xCC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD0 "PADCA_cfg_reg,"
hexmask.long.tbyte 0xD0 11.--31. 1. "NU,Reserved"
bitfld.long 0xD0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xD0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xD0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xD0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xD0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xD0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xD0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xD0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "PADCB_cfg_reg,"
hexmask.long.tbyte 0xD4 11.--31. 1. "NU,Reserved"
bitfld.long 0xD4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xD4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xD4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xD4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xD4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xD4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xD4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xD4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD8 "PADCC_cfg_reg,"
hexmask.long.tbyte 0xD8 11.--31. 1. "NU,Reserved"
bitfld.long 0xD8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xD8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xD8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xD8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xD8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xD8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xD8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xD8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "PADCD_cfg_reg,"
hexmask.long.tbyte 0xDC 11.--31. 1. "NU,Reserved"
bitfld.long 0xDC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xDC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xDC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xDC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xDC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xDC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xDC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xDC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE0 "PADCE_cfg_reg,"
hexmask.long.tbyte 0xE0 11.--31. 1. "NU,Reserved"
bitfld.long 0xE0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xE0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xE0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xE0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xE0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xE0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xE0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xE0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "PADCF_cfg_reg,"
hexmask.long.tbyte 0xE4 11.--31. 1. "NU,Reserved"
bitfld.long 0xE4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xE4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xE4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xE4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xE4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xE4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xE4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xE4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE8 "PADCG_cfg_reg,"
hexmask.long.tbyte 0xE8 11.--31. 1. "NU,Reserved"
bitfld.long 0xE8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xE8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xE8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xE8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xE8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xE8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xE8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xE8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "PADCH_cfg_reg,"
hexmask.long.tbyte 0xEC 11.--31. 1. "NU,Reserved"
bitfld.long 0xEC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xEC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xEC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xEC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xEC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xEC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xEC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xEC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF0 "PADCI_cfg_reg,"
hexmask.long.tbyte 0xF0 11.--31. 1. "NU,Reserved"
bitfld.long 0xF0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xF0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xF0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xF0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xF0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xF0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xF0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xF0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "PADCJ_cfg_reg,"
hexmask.long.tbyte 0xF4 11.--31. 1. "NU,Reserved"
bitfld.long 0xF4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xF4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xF4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xF4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xF4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xF4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xF4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xF4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF8 "PADCK_cfg_reg,"
hexmask.long.tbyte 0xF8 11.--31. 1. "NU,Reserved"
bitfld.long 0xF8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xF8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xF8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xF8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xF8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xF8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xF8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xF8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "PADCL_cfg_reg,"
hexmask.long.tbyte 0xFC 11.--31. 1. "NU,Reserved"
bitfld.long 0xFC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0xFC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0xFC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0xFC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0xFC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0xFC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0xFC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0xFC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x100 "PADCM_cfg_reg,"
hexmask.long.tbyte 0x100 11.--31. 1. "NU,Reserved"
bitfld.long 0x100 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x100 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x100 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x100 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x100 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x100 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x100 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x100 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "PADCN_cfg_reg,"
hexmask.long.tbyte 0x104 11.--31. 1. "NU,Reserved"
bitfld.long 0x104 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x104 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x104 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x104 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x104 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x104 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x104 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x104 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x108 "PADCO_cfg_reg,"
hexmask.long.tbyte 0x108 11.--31. 1. "NU,Reserved"
bitfld.long 0x108 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x108 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x108 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x108 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x108 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x108 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x108 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x108 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10C "PADCP_cfg_reg,"
hexmask.long.tbyte 0x10C 11.--31. 1. "NU,Reserved"
bitfld.long 0x10C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x10C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x10C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x10C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x10C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x10C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x10C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x10C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x110 "PADCQ_cfg_reg,"
hexmask.long.tbyte 0x110 11.--31. 1. "NU,Reserved"
bitfld.long 0x110 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x110 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x110 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x110 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x110 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x110 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x110 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x110 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x114 "PADCR_cfg_reg,"
hexmask.long.tbyte 0x114 11.--31. 1. "NU,Reserved"
bitfld.long 0x114 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x114 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x114 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x114 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x114 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x114 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x114 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x114 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x118 "PADCS_cfg_reg,"
hexmask.long.tbyte 0x118 11.--31. 1. "NU,Reserved"
bitfld.long 0x118 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x118 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x118 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x118 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x118 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x118 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x118 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x118 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x11C "PADCT_cfg_reg,"
hexmask.long.tbyte 0x11C 11.--31. 1. "NU,Reserved"
bitfld.long 0x11C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x11C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x11C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x11C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x11C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x11C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x11C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x11C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x120 "PADCU_cfg_reg,"
hexmask.long.tbyte 0x120 11.--31. 1. "NU,Reserved"
bitfld.long 0x120 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x120 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x120 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x120 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x120 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x120 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x120 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x120 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "PADCV_cfg_reg,"
hexmask.long.tbyte 0x124 11.--31. 1. "NU,Reserved"
bitfld.long 0x124 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x124 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x124 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x124 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x124 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x124 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x124 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x124 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x128 "PADCW_cfg_reg,"
hexmask.long.tbyte 0x128 11.--31. 1. "NU,Reserved"
bitfld.long 0x128 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x128 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x128 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x128 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x128 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x128 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x128 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x128 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x12C "PADCX_cfg_reg,"
hexmask.long.tbyte 0x12C 11.--31. 1. "NU,Reserved"
bitfld.long 0x12C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x12C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x12C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x12C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x12C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x12C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x12C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x12C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x130 "PADCY_cfg_reg,"
hexmask.long.tbyte 0x130 11.--31. 1. "NU,Reserved"
bitfld.long 0x130 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x130 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x130 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x130 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x130 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x130 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x130 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x130 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x134 "PADCZ_cfg_reg,"
hexmask.long.tbyte 0x134 11.--31. 1. "NU,Reserved"
bitfld.long 0x134 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x134 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x134 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x134 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x134 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x134 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x134 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x134 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x138 "PADDA_cfg_reg,"
hexmask.long.tbyte 0x138 11.--31. 1. "NU,Reserved"
bitfld.long 0x138 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x138 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x138 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x138 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x138 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x138 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x138 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x138 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x13C "PADDB_cfg_reg,"
hexmask.long.tbyte 0x13C 11.--31. 1. "NU,Reserved"
bitfld.long 0x13C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x13C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x13C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x13C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x13C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x13C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x13C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x13C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x140 "PADDC_cfg_reg,"
hexmask.long.tbyte 0x140 11.--31. 1. "NU,Reserved"
bitfld.long 0x140 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x140 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x140 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x140 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x140 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x140 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x140 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x140 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "PADDD_cfg_reg,"
hexmask.long.tbyte 0x144 11.--31. 1. "NU,Reserved"
bitfld.long 0x144 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x144 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x144 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x144 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x144 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x144 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x144 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x144 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x148 "PADDE_cfg_reg,"
hexmask.long.tbyte 0x148 11.--31. 1. "NU,Reserved"
bitfld.long 0x148 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x148 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x148 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x148 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x148 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x148 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x148 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x148 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14C "PADDF_cfg_reg,"
hexmask.long.tbyte 0x14C 11.--31. 1. "NU,Reserved"
bitfld.long 0x14C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x14C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x14C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x14C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x14C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x14C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x14C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x14C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x150 "PADDG_cfg_reg,"
hexmask.long.tbyte 0x150 11.--31. 1. "NU,Reserved"
bitfld.long 0x150 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x150 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x150 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x150 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x150 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x150 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x150 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x150 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x154 "PADDH_cfg_reg,"
hexmask.long.tbyte 0x154 11.--31. 1. "NU,Reserved"
bitfld.long 0x154 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x154 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x154 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x154 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x154 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x154 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x154 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x154 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x158 "PADDI_cfg_reg,"
hexmask.long.tbyte 0x158 11.--31. 1. "NU,Reserved"
bitfld.long 0x158 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x158 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x158 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x158 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x158 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x158 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x158 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x158 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x15C "PADDJ_cfg_reg,"
hexmask.long.tbyte 0x15C 11.--31. 1. "NU,Reserved"
bitfld.long 0x15C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x15C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x15C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x15C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x15C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x15C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x15C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x15C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x160 "PADDK_cfg_reg,"
hexmask.long.tbyte 0x160 11.--31. 1. "NU,Reserved"
bitfld.long 0x160 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x160 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x160 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x160 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x160 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x160 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x160 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x160 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "PADDL_cfg_reg,"
hexmask.long.tbyte 0x164 11.--31. 1. "NU,Reserved"
bitfld.long 0x164 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x164 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x164 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x164 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x164 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x164 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x164 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x164 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x168 "PADDM_cfg_reg,"
hexmask.long.tbyte 0x168 11.--31. 1. "NU,Reserved"
bitfld.long 0x168 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x168 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x168 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x168 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x168 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x168 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x168 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x168 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "PADDN_cfg_reg,"
hexmask.long.tbyte 0x16C 11.--31. 1. "NU,Reserved"
bitfld.long 0x16C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x16C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x16C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x16C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x16C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x16C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x16C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x16C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x170 "PADDO_cfg_reg,"
hexmask.long.tbyte 0x170 11.--31. 1. "NU,Reserved"
bitfld.long 0x170 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x170 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x170 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x170 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x170 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x170 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x170 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x170 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "PADDP_cfg_reg,"
hexmask.long.tbyte 0x174 11.--31. 1. "NU,Reserved"
bitfld.long 0x174 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x174 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x174 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x174 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x174 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x174 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x174 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x174 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x178 "PADDQ_cfg_reg,"
hexmask.long.tbyte 0x178 11.--31. 1. "NU,Reserved"
bitfld.long 0x178 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x178 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x178 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x178 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x178 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x178 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x178 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x178 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "PADDR_cfg_reg,"
hexmask.long.tbyte 0x17C 11.--31. 1. "NU,Reserved"
bitfld.long 0x17C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x17C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x17C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x17C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x17C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x17C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x17C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x17C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x180 "PADDS_cfg_reg,"
hexmask.long.tbyte 0x180 11.--31. 1. "NU,Reserved"
bitfld.long 0x180 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x180 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x180 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x180 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x180 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x180 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x180 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x180 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "PADDT_cfg_reg,"
hexmask.long.tbyte 0x184 11.--31. 1. "NU,Reserved"
bitfld.long 0x184 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x184 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x184 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x184 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x184 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x184 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x184 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x184 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x188 "PADDU_cfg_reg,"
hexmask.long.tbyte 0x188 11.--31. 1. "NU,Reserved"
bitfld.long 0x188 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x188 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x188 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x188 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x188 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x188 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x188 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x188 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "PADDV_cfg_reg,"
hexmask.long.tbyte 0x18C 11.--31. 1. "NU,Reserved"
bitfld.long 0x18C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x18C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x18C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x18C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x18C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x18C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x18C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x18C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "PADDW_cfg_reg,"
hexmask.long.tbyte 0x190 11.--31. 1. "NU,Reserved"
bitfld.long 0x190 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x190 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x190 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x190 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x190 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x190 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x190 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x190 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "PADDX_cfg_reg,"
hexmask.long.tbyte 0x194 11.--31. 1. "NU,Reserved"
bitfld.long 0x194 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x194 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x194 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x194 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x194 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x194 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x194 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x194 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x198 "PADDY_cfg_reg,"
hexmask.long.tbyte 0x198 11.--31. 1. "NU,Reserved"
bitfld.long 0x198 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x198 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x198 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x198 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x198 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x198 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x198 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x198 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "PADDZ_cfg_reg,"
hexmask.long.tbyte 0x19C 11.--31. 1. "NU,Reserved"
bitfld.long 0x19C 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x19C 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x19C 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x19C 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x19C 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x19C 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x19C 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x19C 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "PADEA_cfg_reg,"
hexmask.long.tbyte 0x1A0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1A0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1A0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1A0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1A0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1A0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1A0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1A0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1A0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "PADEB_cfg_reg,"
hexmask.long.tbyte 0x1A4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1A4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1A4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1A4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1A4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1A4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1A4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1A4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1A4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "PADEC_cfg_reg,"
hexmask.long.tbyte 0x1A8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1A8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1A8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1A8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1A8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1A8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1A8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1A8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1A8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "PADED_cfg_reg,"
hexmask.long.tbyte 0x1AC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1AC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1AC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1AC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1AC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1AC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1AC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1AC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1AC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "PADEE_cfg_reg,"
hexmask.long.tbyte 0x1B0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1B0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1B0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1B0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1B0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1B0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1B0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1B0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1B0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "PADEF_cfg_reg,"
hexmask.long.tbyte 0x1B4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1B4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1B4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1B4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1B4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1B4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1B4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1B4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1B4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B8 "PADEG_cfg_reg,"
hexmask.long.tbyte 0x1B8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1B8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1B8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1B8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1B8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1B8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1B8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1B8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1B8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "PADEH_cfg_reg,"
hexmask.long.tbyte 0x1BC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1BC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1BC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1BC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1BC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1BC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1BC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1BC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1BC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C0 "PADEI_cfg_reg,"
hexmask.long.tbyte 0x1C0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "PADEJ_cfg_reg,"
hexmask.long.tbyte 0x1C4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C8 "PADEK_cfg_reg,"
hexmask.long.tbyte 0x1C8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1C8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1C8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1C8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1C8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1C8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1C8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1C8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1C8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "PADEL_cfg_reg,"
hexmask.long.tbyte 0x1CC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1CC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1CC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1CC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1CC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1CC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1CC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1CC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1CC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "PADEM_cfg_reg,"
hexmask.long.tbyte 0x1D0 11.--31. 1. "NU,Reserved"
bitfld.long 0x1D0 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1D0 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1D0 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1D0 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1D0 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1D0 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1D0 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1D0 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "PADEN_cfg_reg,"
hexmask.long.tbyte 0x1D4 11.--31. 1. "NU,Reserved"
bitfld.long 0x1D4 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1D4 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1D4 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1D4 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1D4 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1D4 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1D4 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1D4 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D8 "PADEO_cfg_reg,"
hexmask.long.tbyte 0x1D8 11.--31. 1. "NU,Reserved"
bitfld.long 0x1D8 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1D8 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1D8 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1D8 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1D8 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1D8 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1D8 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1D8 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "PADEP_cfg_reg,"
hexmask.long.tbyte 0x1DC 11.--31. 1. "NU,Reserved"
bitfld.long 0x1DC 10. "sc1,IO Slew rate control" "higher slew rate,Lower slew rate"
bitfld.long 0x1DC 9. "pupdsel,Pullup/PullDown Selection 0 -- Pull Down" "0,1"
bitfld.long 0x1DC 8. "pi,Pull Inhibit/Pull Disable 0 -- Enable" "0,1"
bitfld.long 0x1DC 7. "oe_override,Active Low Output Override" "0,1"
bitfld.long 0x1DC 6. "oe_override_ctrl,Active Low Output Override Control : Write 1 to select Active low Output Override value to control IOs OE_N/GZ instead of the control from hardware" "0,1"
newline
bitfld.long 0x1DC 5. "ie_override,Active Low Input Override" "0,1"
bitfld.long 0x1DC 4. "ie_override_ctrl,Active Low Input Override Control : Write 1 to select Active low Input Override value to control IOs IE_N/RXACTIVE_N instead of the control from hardware" "0,1"
bitfld.long 0x1DC 0.--3. "func_sel,Function select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x1F0++0x0F
line.long 0x00 "USERMODEEN,"
line.long 0x04 "PADGLBLCFGREG,"
line.long 0x08 "IOCFGKICK0,"
line.long 0x0C "IOCFGKICK1,"
width 0x0B
tree.end
tree "MSS_MCANA_CFG (MSS MCANA Configuration Module Registers)"
base ad:0x2F7FC00
rgroup.long 0x00++0x2B
line.long 0x00 "SS_PID,SS_PID"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SS_CTRL,SS_CTRL"
hexmask.long 0x04 7.--31. 1. "NU0,Reserved"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
bitfld.long 0x04 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1"
newline
rbitfld.long 0x04 0.--2. "NU,Reserved" "0,1,2,3,4,5,6,7"
line.long 0x08 "SS_STAT,SS_STAT"
hexmask.long 0x08 3.--31. 1. "NU1,Reserved"
bitfld.long 0x08 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MMI_DONE," "0,1"
bitfld.long 0x08 0. "NU,Reserved" "0,1"
line.long 0x0C "SS_ICS,SS_ICS"
hexmask.long 0x0C 1.--31. 1. "NU2,Reserved"
bitfld.long 0x0C 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x10 "SS_IRS,SS_IRS"
hexmask.long 0x10 1.--31. 1. "NU3,Reserved"
bitfld.long 0x10 0. "IRS,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x14 "SS_IECS,SS_IECS"
hexmask.long 0x14 1.--31. 1. "NU4,Reserved"
bitfld.long 0x14 0. "IECS,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x18 "SS_IE,SS_IE"
hexmask.long 0x18 1.--31. 1. "NU5,Reserved"
bitfld.long 0x18 0. "IE,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x1C "SS_IES,SS_IES"
hexmask.long 0x1C 1.--31. 1. "NU6,Reserved"
bitfld.long 0x1C 0. "IES,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "SS_EOI,SS_EOI"
hexmask.long.tbyte 0x20 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targeted interrupt"
line.long 0x24 "SS_EXT_TS_PS,SS_EXT_TS_PS"
hexmask.long.byte 0x24 24.--31. 1. "NU8,Reserved"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value"
line.long 0x28 "SS_EXT_TS_USIC,SS_EXT_TS_USIC"
hexmask.long 0x28 5.--31. 1. "NU9,Reserved"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x200++0x2F
line.long 0x00 "CREL,CREL"
bitfld.long 0x00 28.--31. "REL,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month"
newline
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x04 "ENDN,ENDN"
line.long 0x08 "CUST,CUST"
line.long 0x0C "DBTP,DBTP"
hexmask.long.byte 0x0C 24.--31. 1. "NU13,Reserved"
bitfld.long 0x0C 23. "TDC,Transmitter Delay Compensation" "0,1"
rbitfld.long 0x0C 21.--22. "NU12,Reserved" "0,1,2,3"
bitfld.long 0x0C 16.--20. "DBRP,Data Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x0C 13.--15. "NU11,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8.--12. "DTSEG1,Data time segment before smaple point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "DSJW,Data resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "TEST,TEST"
hexmask.long.tbyte 0x10 8.--31. 1. "NU15,Reserved"
rbitfld.long 0x10 7. "RX,Receive Pin" "0,1"
bitfld.long 0x10 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x10 4. "LBCK,Loop Back Mode" "0,1"
rbitfld.long 0x10 0.--3. "NU14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "RWD,RWD"
hexmask.long.word 0x14 16.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x14 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x14 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x18 "CCCR,CCCR"
hexmask.long.tbyte 0x18 15.--31. 1. "NU18,Reserved"
bitfld.long 0x18 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x18 13. "EFBI,Edge Filtering durign Bus Integration" "0,1"
bitfld.long 0x18 12. "PXHD,Protocol Exception Handling Disable" "0,1"
rbitfld.long 0x18 10.--11. "NU17,Reserved" "0,1,2,3"
newline
bitfld.long 0x18 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x18 8. "FDOE,FD Operation Enable" "0,1"
bitfld.long 0x18 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x18 6. "DAR,Disable Automatic Regransmission" "0,1"
bitfld.long 0x18 5. "MON,Bus Monitoring Mode" "0,1"
newline
bitfld.long 0x18 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x18 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x18 2. "ASM,Restriced Operation Mode" "0,1"
bitfld.long 0x18 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x18 0. "INIT,Initialization" "0,1"
line.long 0x1C "NBTP,NBTP"
hexmask.long.byte 0x1C 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x1C 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x1C 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
rbitfld.long 0x1C 7. "NU19,Reserved" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x20 "TSCC,TSCC"
hexmask.long.word 0x20 20.--31. 1. "NU21,Reserved"
bitfld.long 0x20 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 2.--15. 1. "NU20,Reserved"
bitfld.long 0x20 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x24 "TSCV,TSCV"
hexmask.long.word 0x24 16.--31. 1. "NU22,Reserved"
hexmask.long.word 0x24 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x28 "TOCC,TOCC"
hexmask.long.word 0x28 16.--31. 1. "TOP,Timeout Period"
hexmask.long.word 0x28 3.--15. 1. "NU23,Reserved"
bitfld.long 0x28 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x28 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x2C "TOCV,TOCV"
hexmask.long.word 0x2C 16.--31. 1. "NU24,Reserved"
hexmask.long.word 0x2C 0.--15. 1. "TOC,Timeout Counter"
rgroup.long 0x240++0x0B
line.long 0x00 "ECR,ECR"
hexmask.long.byte 0x00 24.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x00 15. "RP,Recieve Error Passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Recieve Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x04 "PSR,PSR"
hexmask.long.word 0x04 23.--31. 1. "NU27,Reserved"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x04 15. "NU26,Reserved" "0,1"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x04 13. "RFDF,Recieved a CAN FD Message" "0,1"
newline
bitfld.long 0x04 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x04 6. "EW,Warning Status" "0,1"
newline
bitfld.long 0x04 5. "EP,Error Passive" "0,1"
bitfld.long 0x04 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
line.long 0x08 "TDCR,TDCR"
hexmask.long.tbyte 0x08 15.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
rbitfld.long 0x08 7. "NU28,Reserved" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x250++0x0F
line.long 0x00 "IR,IR"
rbitfld.long 0x00 30.--31. "NU30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0,1"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning Status" "0,1"
bitfld.long 0x00 23. "EP,Error Passive" "0,1"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0,1"
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0,1"
newline
bitfld.long 0x00 20. "BEC,Bit Error Corrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0,1"
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0,1"
newline
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0,1"
newline
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission Complete" "0,1"
bitfld.long 0x00 8. "HPM,High Priority Message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0,1"
newline
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0x04 "IE,IE"
rbitfld.long 0x04 30.--31. "NU31,Reserved" "0,1,2,3"
bitfld.long 0x04 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "0,1"
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
newline
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
newline
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
newline
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1"
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x04 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0x04 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
newline
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x08 "ILS,ILS"
rbitfld.long 0x08 30.--31. "NU32,Reserved" "0,1,2,3"
bitfld.long 0x08 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "0,1"
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
newline
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
newline
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
newline
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x08 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x08 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
newline
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x0C "ILE,ILE"
hexmask.long 0x0C 2.--31. 1. "NU33,Reserved"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "0,1"
group.long 0x280++0x0B
line.long 0x00 "GFC,GFC"
hexmask.long 0x00 6.--31. 1. "NU34,Reserved"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,reject Remote Frames Standard" "0,1"
bitfld.long 0x00 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x04 "SIDFC,SIDFC"
hexmask.long.byte 0x04 24.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "LSS_S,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA_S,Filter List Standard Start Address"
rbitfld.long 0x04 0.--1. "NU35,Reserved" "0,1,2,3"
line.long 0x08 "XIDFC,XIDFC"
hexmask.long.byte 0x08 24.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x08 16.--23. 1. "LSS_X,List Size Standard"
hexmask.long.word 0x08 2.--15. 1. "FLSSA_X,Filter List Standard Start Address"
rbitfld.long 0x08 0.--1. "NU37,Reserved" "0,1,2,3"
group.long 0x290++0x57
line.long 0x00 "XIDAM,XIDAM"
rbitfld.long 0x00 29.--31. "NU39,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
line.long 0x04 "HPMS,HPMS"
hexmask.long.word 0x04 16.--31. 1. "NU40,Reserved"
bitfld.long 0x04 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x04 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "NDAT1,NDAT1"
line.long 0x0C "NDAT2,NDAT2"
line.long 0x10 "RXF0C,RXF0C"
bitfld.long 0x10 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
rbitfld.long 0x10 23. "NU42_1,Reserved" "0,1"
hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size"
rbitfld.long 0x10 15. "NU42,Reserved" "0,1"
newline
hexmask.long.word 0x10 2.--14. 1. "F0SA,Rx FIFO 0 Start Address"
rbitfld.long 0x10 0.--1. "NU41,Reserved" "0,1,2,3"
line.long 0x14 "RXF0S,RXF0S"
bitfld.long 0x14 26.--31. "NU46,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x14 22.--23. "NU45,Reserved" "0,1,2,3"
bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 14.--15. "NU44,Reserved" "0,1,2,3"
bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 7. "NU43,Reserved" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
line.long 0x18 "RXF0A,RXF0A"
hexmask.long 0x18 6.--31. 1. "NU47,Reserved"
bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "RXBC,RXBC"
hexmask.long.word 0x1C 16.--31. 1. "NU49,Reserved"
hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address"
rbitfld.long 0x1C 0.--1. "NU48,Reserved" "0,1,2,3"
line.long 0x20 "RXF1C,RXF1C"
bitfld.long 0x20 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 0 Watermark"
rbitfld.long 0x20 23. "NU50_1,Reserved" "0,1"
hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 0 Size"
rbitfld.long 0x20 15. "NU50,Reserved" "0,1"
newline
hexmask.long.word 0x20 2.--14. 1. "F1SA,Rx FIFO 0 Start Address"
rbitfld.long 0x20 0.--1. "NU499,Reserved" "0,1,2,3"
line.long 0x24 "RXF1S,RXF1S"
bitfld.long 0x24 26.--31. "NU54,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 25. "RF1L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x24 24. "F1F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x24 22.--23. "NU53,Reserved" "0,1,2,3"
bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 14.--15. "NU52,Reserved" "0,1,2,3"
bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 7. "NU51,Reserved" "0,1"
hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level"
line.long 0x28 "RXF1A,RXF1A"
hexmask.long 0x28 6.--31. 1. "NU55,Reserved"
bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "RXESC,RXESC"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU58,Reserved"
bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 7. "NU57,Reserved" "0,1"
bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 3. "NU56,Reserved" "0,1"
newline
bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x30 "TXBC,TXBC"
bitfld.long 0x30 31. "NU61,Reserved" "0,1"
bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x30 22.--23. "NU60,Reserved" "0,1,2,3"
bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address"
bitfld.long 0x30 0.--1. "NU59,Reserved" "0,1,2,3"
line.long 0x34 "TXFQS,TXFQS"
hexmask.long.word 0x34 22.--31. 1. "NU64,Reserved"
bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "0,1"
bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 13.--15. "NU63,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x34 8.--12. "TFGI,Tx Queue Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 6.--7. "NU62,Reserved" "0,1,2,3"
bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "TXESC,TXESC"
hexmask.long 0x38 3.--31. 1. "NU65,Reserved"
bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x3C "TXBRP,TXBRP"
line.long 0x40 "TXBAR,TXBAR"
line.long 0x44 "TXBCR,TXBCR"
line.long 0x48 "TXBTO,TXBTO"
line.long 0x4C "TXBCF,TXBCF"
line.long 0x50 "TXBTIE,TXBTIE"
line.long 0x54 "TXBCIE,TXBCIE"
group.long 0x2F0++0x0F
line.long 0x00 "TXEFC,TXEFC"
bitfld.long 0x00 30.--31. "NU68,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 22.--23. "NU67,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
newline
bitfld.long 0x00 0.--1. "NU66,Reserved" "0,1,2,3"
line.long 0x04 "TXEFS,TXEFS"
bitfld.long 0x04 26.--31. "NU72,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x04 24. "EFF,Event FIFO Full" "0,1"
bitfld.long 0x04 21.--23. "NU71,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 13.--15. "NU70,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--7. "NU69,Reserved" "0,1,2,3"
bitfld.long 0x04 0.--5. "EFFL,Event FIFO FIll Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "TXEFA,TXEFA"
hexmask.long 0x08 5.--31. 1. "NU73,Reserved"
bitfld.long 0x08 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "RES16,RES16"
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C 0xB8 0xBC )
rgroup.long ($2+0x230)++0x03
line.long 0x00 "RES$1,RES00"
repeat.end
width 0x0B
tree.end
tree "MSS_MCANA_ECC (MSS MCANA ECC Module Registers)"
base ad:0x2F7F800
rgroup.long 0x00++0x03
line.long 0x00 "REV,Aggregator Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "VECTOR,ECC Vector Register"
hexmask.long.byte 0x00 25.--31. 1. "NU1,Reserved"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDR,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
rbitfld.long 0x00 11.--14. "NU0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "STAT,Misc Status"
hexmask.long.tbyte 0x04 11.--31. 1. "NU2,Reserved"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x14++0x17
line.long 0x00 "CTRL,CTRL"
hexmask.long.tbyte 0x00 9.--31. 1. "NU3,TI Internal : Reserved"
bitfld.long 0x00 8. "CHECK TIMEOUT,TI Internal : Check timeout" "0,1"
bitfld.long 0x00 7. "CHECK PARITY,TI Internal : Check Parity" "0,1"
bitfld.long 0x00 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1"
newline
bitfld.long 0x00 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM" "0,1"
bitfld.long 0x00 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1"
bitfld.long 0x00 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1"
bitfld.long 0x00 2. "EN_RMW,TI Internal : Enable rmw" "0,1"
newline
bitfld.long 0x00 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1"
bitfld.long 0x00 0. "ECC_EN,TI Internal : Enable ECC" "0,1"
line.long 0x04 "ERR_CTRL1,ERR_CTRL1"
line.long 0x08 "ERR_CTRL2,ERR_CTRL2"
hexmask.long.word 0x08 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x08 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set"
line.long 0x0C "ERR_STAT1,ERR_STAT1"
hexmask.long.word 0x0C 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error"
bitfld.long 0x0C 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status" "0,1"
bitfld.long 0x0C 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status" "0,1,2,3"
bitfld.long 0x0C 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status" "0,1"
newline
bitfld.long 0x0C 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt" "0,1"
bitfld.long 0x0C 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt" "0,1,2,3"
newline
bitfld.long 0x0C 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt" "0,1"
bitfld.long 0x0C 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt" "0,1,2,3"
bitfld.long 0x0C 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt" "0,1,2,3"
line.long 0x10 "ERR_STAT2,ERR_STAT2"
line.long 0x14 "ERR_STAT3,ERR_STAT3"
hexmask.long.tbyte 0x14 10.--31. 1. "NU6,TI Internal : Reserved"
bitfld.long 0x14 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1"
hexmask.long.byte 0x14 2.--8. 1. "NU5,TI Internal : Reserved"
bitfld.long 0x14 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1"
newline
rbitfld.long 0x14 0. "NU4,TI Internal : Reserved" "0,1"
group.long 0x3C++0x07
line.long 0x00 "SEC_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU7,Reserved"
bitfld.long 0x00 0. "SEC_EOI_WR,EOI Register" "0,1"
line.long 0x04 "SEC_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU8,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU9,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU10,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DED_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU11,Reserved"
bitfld.long 0x00 0. "DED_EOI_WR,EOI Register" "0,1"
line.long 0x04 "DED_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU12,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "DED_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU13,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU14,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "AGGR_ENABLE_SET,AGGR interrupt enable set Register"
hexmask.long 0x00 2.--31. 1. "NU15,Reserved"
bitfld.long 0x00 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt Enable Set Register for parity errors" "0,1"
line.long 0x04 "AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
hexmask.long 0x04 2.--31. 1. "NU16,Reserved"
bitfld.long 0x04 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt Enable Clear for parity errors" "0,1"
line.long 0x08 "AGGR_STATUS_SET,AGGR interrupt status set Register"
hexmask.long 0x08 4.--31. 1. "NU17,Reserved"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "AGGR_STATUS_CLR,AGGR interrupt status clear Register"
hexmask.long 0x0C 4.--31. 1. "NU18,Reserved"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_MCANB_CFG (MSS MCANB Configuration Module Registers)"
base ad:0x3F7FC00
rgroup.long 0x00++0x2B
line.long 0x00 "SS_PID,SS_PID"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "SS_CTRL,SS_CTRL"
hexmask.long 0x04 7.--31. 1. "NU0,Reserved"
bitfld.long 0x04 6. "EXT_TS_CNTR_EN,External TimeStamp Counter Enable" "0,1"
bitfld.long 0x04 5. "AUTOWAKEUP,Automatic Wakeup Enable" "0,1"
bitfld.long 0x04 4. "WAKEUPREGEN,Wakeup Request Enable" "0,1"
bitfld.long 0x04 3. "DBGSUSP_FREE,0-Honor Debug Suspend 1-Disregard debug suspend" "0,1"
newline
rbitfld.long 0x04 0.--2. "NU,Reserved" "0,1,2,3,4,5,6,7"
line.long 0x08 "SS_STAT,SS_STAT"
hexmask.long 0x08 3.--31. 1. "NU1,Reserved"
bitfld.long 0x08 2. "EN_FDOE,Reflects the value of mcanss_enable_fdoe configuration port x=mcanss_enable_fdoe" "0,1"
bitfld.long 0x08 1. "MMI_DONE," "0,1"
bitfld.long 0x08 0. "NU,Reserved" "0,1"
line.long 0x0C "SS_ICS,SS_ICS"
hexmask.long 0x0C 1.--31. 1. "NU2,Reserved"
bitfld.long 0x0C 0. "ICS,This bit contains the External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x10 "SS_IRS,SS_IRS"
hexmask.long 0x10 1.--31. 1. "NU3,Reserved"
bitfld.long 0x10 0. "IRS,External TimeStamp Counter Overflow Interrupt status" "0,1"
line.long 0x14 "SS_IECS,SS_IECS"
hexmask.long 0x14 1.--31. 1. "NU4,Reserved"
bitfld.long 0x14 0. "IECS,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x18 "SS_IE,SS_IE"
hexmask.long 0x18 1.--31. 1. "NU5,Reserved"
bitfld.long 0x18 0. "IE,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x1C "SS_IES,SS_IES"
hexmask.long 0x1C 1.--31. 1. "NU6,Reserved"
bitfld.long 0x1C 0. "IES,External TimeStamp Counter Overflow Interrupt" "0,1"
line.long 0x20 "SS_EOI,SS_EOI"
hexmask.long.tbyte 0x20 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "EOI,Write with bit position of targeted interrupt"
line.long 0x24 "SS_EXT_TS_PS,SS_EXT_TS_PS"
hexmask.long.byte 0x24 24.--31. 1. "NU8,Reserved"
hexmask.long.tbyte 0x24 0.--23. 1. "PRESCALE,External Timestamp Prescaler reload value"
line.long 0x28 "SS_EXT_TS_USIC,SS_EXT_TS_USIC"
hexmask.long 0x28 5.--31. 1. "NU9,Reserved"
bitfld.long 0x28 0.--4. "EXT_TS_INTR_CNTR,Number of unserviced rollover interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x200++0x2F
line.long 0x00 "CREL,CREL"
bitfld.long 0x00 28.--31. "REL,Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 24.--27. "STEP,Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 20.--23. "SUBSTEP,Sub-Step of Core Release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 16.--19. "YEAR,Time Stamp Year" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.byte 0x00 8.--15. 1. "MON,Time Stamp Month"
newline
hexmask.long.byte 0x00 0.--7. 1. "DAY,Time Stamp Day"
line.long 0x04 "ENDN,ENDN"
line.long 0x08 "CUST,CUST"
line.long 0x0C "DBTP,DBTP"
hexmask.long.byte 0x0C 24.--31. 1. "NU13,Reserved"
bitfld.long 0x0C 23. "TDC,Transmitter Delay Compensation" "0,1"
rbitfld.long 0x0C 21.--22. "NU12,Reserved" "0,1,2,3"
bitfld.long 0x0C 16.--20. "DBRP,Data Baud Rate Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rbitfld.long 0x0C 13.--15. "NU11,Reserved" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 8.--12. "DTSEG1,Data time segment before smaple point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x0C 4.--7. "DTSEG2,Data time segment after sample point" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 0.--3. "DSJW,Data resynchronization Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "TEST,TEST"
hexmask.long.tbyte 0x10 8.--31. 1. "NU15,Reserved"
rbitfld.long 0x10 7. "RX,Receive Pin" "0,1"
bitfld.long 0x10 5.--6. "TX,Control of Transmit Pin" "0,1,2,3"
bitfld.long 0x10 4. "LBCK,Loop Back Mode" "0,1"
rbitfld.long 0x10 0.--3. "NU14,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "RWD,RWD"
hexmask.long.word 0x14 16.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x14 8.--15. 1. "WDV,Watchdog Value"
hexmask.long.byte 0x14 0.--7. 1. "WDC,Watchdog Counter Value"
line.long 0x18 "CCCR,CCCR"
hexmask.long.tbyte 0x18 15.--31. 1. "NU18,Reserved"
bitfld.long 0x18 14. "TXP,Transmit Pause" "0,1"
bitfld.long 0x18 13. "EFBI,Edge Filtering durign Bus Integration" "0,1"
bitfld.long 0x18 12. "PXHD,Protocol Exception Handling Disable" "0,1"
rbitfld.long 0x18 10.--11. "NU17,Reserved" "0,1,2,3"
newline
bitfld.long 0x18 9. "BRSE,Bit Rate Switch Enable" "0,1"
bitfld.long 0x18 8. "FDOE,FD Operation Enable" "0,1"
bitfld.long 0x18 7. "TEST,Test Mode enable" "0,1"
bitfld.long 0x18 6. "DAR,Disable Automatic Regransmission" "0,1"
bitfld.long 0x18 5. "MON,Bus Monitoring Mode" "0,1"
newline
bitfld.long 0x18 4. "CSR,Clock Stop Request" "0,1"
rbitfld.long 0x18 3. "CSA,Clock Stop Acknowledge" "0,1"
bitfld.long 0x18 2. "ASM,Restriced Operation Mode" "0,1"
bitfld.long 0x18 1. "CCE,Configuration Change Enable" "0,1"
bitfld.long 0x18 0. "INIT,Initialization" "0,1"
line.long 0x1C "NBTP,NBTP"
hexmask.long.byte 0x1C 25.--31. 1. "NSJW,Nominal Resynchronization Jump Width"
hexmask.long.word 0x1C 16.--24. 1. "NBRP,Nominal Baud Rate Prescaler"
hexmask.long.byte 0x1C 8.--15. 1. "NTSEG1,Nominal Time segment before sample point"
rbitfld.long 0x1C 7. "NU19,Reserved" "0,1"
hexmask.long.byte 0x1C 0.--6. 1. "NTSEG2,Nominal Time segment after sample point"
line.long 0x20 "TSCC,TSCC"
hexmask.long.word 0x20 20.--31. 1. "NU21,Reserved"
bitfld.long 0x20 16.--19. "TCP,Timestamp Counter Prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x20 2.--15. 1. "NU20,Reserved"
bitfld.long 0x20 0.--1. "TSS,Timestamp Select" "0,1,2,3"
line.long 0x24 "TSCV,TSCV"
hexmask.long.word 0x24 16.--31. 1. "NU22,Reserved"
hexmask.long.word 0x24 0.--15. 1. "TSC,Timestamp Counter"
line.long 0x28 "TOCC,TOCC"
hexmask.long.word 0x28 16.--31. 1. "TOP,Timeout Period"
hexmask.long.word 0x28 3.--15. 1. "NU23,Reserved"
bitfld.long 0x28 1.--2. "TOS,Timeout Select" "0,1,2,3"
bitfld.long 0x28 0. "ETOC,Enable Timeout Counter" "0,1"
line.long 0x2C "TOCV,TOCV"
hexmask.long.word 0x2C 16.--31. 1. "NU24,Reserved"
hexmask.long.word 0x2C 0.--15. 1. "TOC,Timeout Counter"
rgroup.long 0x240++0x0B
line.long 0x00 "ECR,ECR"
hexmask.long.byte 0x00 24.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x00 16.--23. 1. "CEL,CAN Error Logging"
bitfld.long 0x00 15. "RP,Recieve Error Passive" "0,1"
hexmask.long.byte 0x00 8.--14. 1. "REC,Recieve Error Counter"
hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter"
line.long 0x04 "PSR,PSR"
hexmask.long.word 0x04 23.--31. 1. "NU27,Reserved"
hexmask.long.byte 0x04 16.--22. 1. "TDCV,Transmitter Delay Compensation Value"
bitfld.long 0x04 15. "NU26,Reserved" "0,1"
bitfld.long 0x04 14. "PXE,Protocol Exception Event" "0,1"
bitfld.long 0x04 13. "RFDF,Recieved a CAN FD Message" "0,1"
newline
bitfld.long 0x04 12. "RBRS,BRS flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 11. "RESI,ESI flag of last recieved CAN FD Message" "0,1"
bitfld.long 0x04 8.--10. "DLEC,Data Phase Last Error Code" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "BO,Bus_Off status" "0,1"
bitfld.long 0x04 6. "EW,Warning Status" "0,1"
newline
bitfld.long 0x04 5. "EP,Error Passive" "0,1"
bitfld.long 0x04 3.--4. "ACT,Activity" "0,1,2,3"
bitfld.long 0x04 0.--2. "LEC,Last Error Code" "0,1,2,3,4,5,6,7"
line.long 0x08 "TDCR,TDCR"
hexmask.long.tbyte 0x08 15.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x08 8.--14. 1. "TDCO,Transmitter Delay Compensation Offset"
rbitfld.long 0x08 7. "NU28,Reserved" "0,1"
hexmask.long.byte 0x08 0.--6. 1. "TDCF,Transmitter Delay Compensation Filter Window Length"
group.long 0x250++0x0F
line.long 0x00 "IR,IR"
rbitfld.long 0x00 30.--31. "NU30,Reserved" "0,1,2,3"
bitfld.long 0x00 29. "ARA,Access to Reserved Address" "0,1"
bitfld.long 0x00 28. "PED,Protocol Error in data Phase" "0,1"
bitfld.long 0x00 27. "PEA,Protocol Error in Arbitration Phase" "0,1"
bitfld.long 0x00 26. "WDI,Watchdog Interrupt" "0,1"
newline
bitfld.long 0x00 25. "BO,Bus_Off Status" "0,1"
bitfld.long 0x00 24. "EW,Warning Status" "0,1"
bitfld.long 0x00 23. "EP,Error Passive" "0,1"
bitfld.long 0x00 22. "ELO,Error Logging Overflow" "0,1"
bitfld.long 0x00 21. "BEU,Bit Error Uncorrected" "0,1"
newline
bitfld.long 0x00 20. "BEC,Bit Error Corrected" "0,1"
bitfld.long 0x00 19. "DRX,Message stored to Dedicated Rx Buffer" "0,1"
bitfld.long 0x00 18. "TOO,Timeout Occurred" "0,1"
bitfld.long 0x00 17. "MRAF,Message RAM Access Failure" "0,1"
bitfld.long 0x00 16. "TSW,Timestamp Wraparound" "0,1"
newline
bitfld.long 0x00 15. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x00 14. "TEFF,Tx Event FIFO Full" "0,1"
bitfld.long 0x00 13. "TEFW,Tx Event FIFO Watermark Reached" "0,1"
bitfld.long 0x00 12. "TEFN,Tx Event FIFO New Entry" "0,1"
bitfld.long 0x00 11. "TFE,Tx FIFO Empty" "0,1"
newline
bitfld.long 0x00 10. "TCF,Transmission Cancellation Finished" "0,1"
bitfld.long 0x00 9. "TC,Transmission Complete" "0,1"
bitfld.long 0x00 8. "HPM,High Priority Message" "0,1"
bitfld.long 0x00 7. "RF1L,Rx FIFO 1 Message Lost" "0,1"
bitfld.long 0x00 6. "RF1F,Rx FIFO 1 Full" "0,1"
newline
bitfld.long 0x00 5. "RF1W,Rx FIFO 1 Watermark Reached" "0,1"
bitfld.long 0x00 4. "RF1N,Rx FIFO 1 New Message" "0,1"
bitfld.long 0x00 3. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x00 2. "RF0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x00 1. "RF0W,Rx FIFO 0 Watermark Reached" "0,1"
newline
bitfld.long 0x00 0. "RF0N,Rx FIFO 0 New Message" "0,1"
line.long 0x04 "IE,IE"
rbitfld.long 0x04 30.--31. "NU31,Reserved" "0,1,2,3"
bitfld.long 0x04 29. "ARAE,Accees to Reserve Address Interrupt Enable" "0,1"
bitfld.long 0x04 28. "PEDE,Protocol Error in Data Phase Interrupt Enable" "0,1"
bitfld.long 0x04 27. "PEAE,Protocol Error in Arbitration Phase Interrupt Enable" "0,1"
bitfld.long 0x04 26. "WDIE,Watchdog Interrupt Enable" "0,1"
newline
bitfld.long 0x04 25. "BOE,Bus_Off Status Interrupt Enable" "0,1"
bitfld.long 0x04 24. "EWE,Warning Status Interrupt Enable" "0,1"
bitfld.long 0x04 23. "EPE,Error Passive Interrupt Enable" "0,1"
bitfld.long 0x04 22. "ELOE,Error Logging Overflow Interrupt Enable" "0,1"
bitfld.long 0x04 21. "BEUE,Bit Error Uncorrected Interrupt Enable" "0,1"
newline
bitfld.long 0x04 20. "BECE,Bit Error Corrected Interrupt Enable" "0,1"
bitfld.long 0x04 19. "DRX,Message stored to Dedicated Rx Buffer Interrupt Enable" "0,1"
bitfld.long 0x04 18. "TOOE,Timeout Occurred Interrupt Enable" "0,1"
bitfld.long 0x04 17. "MRAFE,Message RAM Access Failure Interrupt Enable" "0,1"
bitfld.long 0x04 16. "TSWE,Timestamp Wraparound Interrupt Enable" "0,1"
newline
bitfld.long 0x04 15. "TEFLE,Tx Event FIFO Event Lost Interrupt Enable" "0,1"
bitfld.long 0x04 14. "TEFFE,Tx Event FIFO Full Interrupt Enable" "0,1"
bitfld.long 0x04 13. "TEFWE,Tx Event FIFO Watermark Reached Interrupt enable" "0,1"
bitfld.long 0x04 12. "TEFNE,Tx Event FIFO New Entry Interrupt Enable" "0,1"
bitfld.long 0x04 11. "TFEE,Tx FIFO Empty Interrupt Enable" "0,1"
newline
bitfld.long 0x04 10. "TCFE,Transmission Cancellation Finishied Interrupt Enable" "0,1"
bitfld.long 0x04 9. "TCE,Transmission Completed Interrupt Enable" "0,1"
bitfld.long 0x04 8. "HPME,High Priority message Interrupt Enable" "0,1"
bitfld.long 0x04 7. "RF1LE,rx FIFO 1 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 6. "RF1FE,Rx FIFO 1 Full Interrupt Enable" "0,1"
newline
bitfld.long 0x04 5. "RF1WE,Rx FIFO 1 Watermark Reached Interrupt Enable" "0,1"
bitfld.long 0x04 4. "RF1NE,Rx FIFO 1 New Message Interrupt Enable" "0,1"
bitfld.long 0x04 3. "RF0LE,Rx FIFO 0 Message Lost Interrupt Enable" "0,1"
bitfld.long 0x04 2. "RF0FE,Rx FIFO 0 Full Interrupt Enable" "0,1"
bitfld.long 0x04 1. "RF0WE,Rx FIFO 0 Watermark Reached Interrupt Enable" "0,1"
newline
bitfld.long 0x04 0. "RF0NE,Rx FIFO 0 New Message Interrupt Enable" "0,1"
line.long 0x08 "ILS,ILS"
rbitfld.long 0x08 30.--31. "NU32,Reserved" "0,1,2,3"
bitfld.long 0x08 29. "ARAL,Accees to Reserve Address Interrupt Line" "0,1"
bitfld.long 0x08 28. "PEDL,Protocol Error in Data Phase Interrupt Line" "0,1"
bitfld.long 0x08 27. "PEAL,Protocol Error in Arbitration Phase Interrupt Line" "0,1"
bitfld.long 0x08 26. "WDIL,Watchdog Interrupt Line" "0,1"
newline
bitfld.long 0x08 25. "BOL,Bus_Off Status Interrupt Line" "0,1"
bitfld.long 0x08 24. "EWL,Warning Status Interrupt Line" "0,1"
bitfld.long 0x08 23. "EPL,Error Passive Interrupt Line" "0,1"
bitfld.long 0x08 22. "ELOL,Error Logging Overflow Interrupt Line" "0,1"
bitfld.long 0x08 21. "BEUL,Bit Error Uncorrected Interrupt Line" "0,1"
newline
bitfld.long 0x08 20. "BECL,Bit Error Corrected Interrupt Line" "0,1"
bitfld.long 0x08 19. "DRXL,Message stored to Dedicated Rx Buffer Interrupt Line" "0,1"
bitfld.long 0x08 18. "TOOL,Timeout Occurred Interrupt Line" "0,1"
bitfld.long 0x08 17. "MRAFL,Message RAM Access Failure Interrupt Line" "0,1"
bitfld.long 0x08 16. "TSWL,Timestamp Wraparound Interrupt Line" "0,1"
newline
bitfld.long 0x08 15. "TEFLL,Tx Event FIFO Event Lost Interrupt Line" "0,1"
bitfld.long 0x08 14. "TEFFL,Tx Event FIFO Full Interrupt Line" "0,1"
bitfld.long 0x08 13. "TEFWL,Tx Event FIFO Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 12. "TEFNL,Tx Event FIFO New Entry Interrupt Line" "0,1"
bitfld.long 0x08 11. "TFEL,Tx FIFO Empty Interrupt Line" "0,1"
newline
bitfld.long 0x08 10. "TCFL,Transmission Cancellation Finishied Interrupt Line" "0,1"
bitfld.long 0x08 9. "TCL,Transmission Completed Interrupt Line" "0,1"
bitfld.long 0x08 8. "HPML,High Priority message Interrupt Line" "0,1"
bitfld.long 0x08 7. "RF1LL,rx FIFO 1 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 6. "RF1FL,Rx FIFO 1 Full Interrupt Line" "0,1"
newline
bitfld.long 0x08 5. "RF1WL,Rx FIFO 1 Watermark Reached Interrupt Line" "0,1"
bitfld.long 0x08 4. "RF1NL,Rx FIFO 1 New Message Interrupt Line" "0,1"
bitfld.long 0x08 3. "RF0LL,Rx FIFO 0 Message Lost Interrupt Line" "0,1"
bitfld.long 0x08 2. "RF0FL,Rx FIFO 0 Full Interrupt Line" "0,1"
bitfld.long 0x08 1. "RF0WL,Rx FIFO 0 Watermark Reached Interrupt Line" "0,1"
newline
bitfld.long 0x08 0. "RF0NL,Rx FIFO 0 New Message Interrupt Line" "0,1"
line.long 0x0C "ILE,ILE"
hexmask.long 0x0C 2.--31. 1. "NU33,Reserved"
bitfld.long 0x0C 1. "EINT1,Enable Interrupt Line 1" "0,1"
bitfld.long 0x0C 0. "EINT0,Enable Interrupt Line 0" "0,1"
group.long 0x280++0x0B
line.long 0x00 "GFC,GFC"
hexmask.long 0x00 6.--31. 1. "NU34,Reserved"
bitfld.long 0x00 4.--5. "ANFS,Accept Non-matching Frames Standard" "0,1,2,3"
bitfld.long 0x00 2.--3. "ANFE,Accept Non-matching Frames Extended" "0,1,2,3"
bitfld.long 0x00 1. "RRFS,reject Remote Frames Standard" "0,1"
bitfld.long 0x00 0. "RRFE,reject Remote Frames Extended" "0,1"
line.long 0x04 "SIDFC,SIDFC"
hexmask.long.byte 0x04 24.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x04 16.--23. 1. "LSS_S,List Size Standard"
hexmask.long.word 0x04 2.--15. 1. "FLSSA_S,Filter List Standard Start Address"
rbitfld.long 0x04 0.--1. "NU35,Reserved" "0,1,2,3"
line.long 0x08 "XIDFC,XIDFC"
hexmask.long.byte 0x08 24.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x08 16.--23. 1. "LSS_X,List Size Standard"
hexmask.long.word 0x08 2.--15. 1. "FLSSA_X,Filter List Standard Start Address"
rbitfld.long 0x08 0.--1. "NU37,Reserved" "0,1,2,3"
group.long 0x290++0x57
line.long 0x00 "XIDAM,XIDAM"
rbitfld.long 0x00 29.--31. "NU39,Reserved" "0,1,2,3,4,5,6,7"
hexmask.long 0x00 0.--28. 1. "EIDM,Extended ID Mask"
line.long 0x04 "HPMS,HPMS"
hexmask.long.word 0x04 16.--31. 1. "NU40,Reserved"
bitfld.long 0x04 15. "FLST,Filter List" "0,1"
hexmask.long.byte 0x04 8.--14. 1. "FIDX,Filter Index"
bitfld.long 0x04 6.--7. "MSI,Message Storeage Indicator" "0,1,2,3"
bitfld.long 0x04 0.--5. "BIDX,Buffer Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "NDAT1,NDAT1"
line.long 0x0C "NDAT2,NDAT2"
line.long 0x10 "RXF0C,RXF0C"
bitfld.long 0x10 31. "F0OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x10 24.--30. 1. "F0WM,Rx FIFO 0 Watermark"
rbitfld.long 0x10 23. "NU42_1,Reserved" "0,1"
hexmask.long.byte 0x10 16.--22. 1. "F0S,Rx FIFO 0 Size"
rbitfld.long 0x10 15. "NU42,Reserved" "0,1"
newline
hexmask.long.word 0x10 2.--14. 1. "F0SA,Rx FIFO 0 Start Address"
rbitfld.long 0x10 0.--1. "NU41,Reserved" "0,1,2,3"
line.long 0x14 "RXF0S,RXF0S"
bitfld.long 0x14 26.--31. "NU46,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 25. "RF0L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x14 24. "F0F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x14 22.--23. "NU45,Reserved" "0,1,2,3"
bitfld.long 0x14 16.--21. "F0PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 14.--15. "NU44,Reserved" "0,1,2,3"
bitfld.long 0x14 8.--13. "F0GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x14 7. "NU43,Reserved" "0,1"
hexmask.long.byte 0x14 0.--6. 1. "F0FL,Rx FIFO 0 Fill Level"
line.long 0x18 "RXF0A,RXF0A"
hexmask.long 0x18 6.--31. 1. "NU47,Reserved"
bitfld.long 0x18 0.--5. "F0AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x1C "RXBC,RXBC"
hexmask.long.word 0x1C 16.--31. 1. "NU49,Reserved"
hexmask.long.word 0x1C 2.--15. 1. "RBSA,Rx Buffer Start Address"
rbitfld.long 0x1C 0.--1. "NU48,Reserved" "0,1,2,3"
line.long 0x20 "RXF1C,RXF1C"
bitfld.long 0x20 31. "F1OM,Rx FIFO 0 Operation Mode" "0,1"
hexmask.long.byte 0x20 24.--30. 1. "F1WM,Rx FIFO 0 Watermark"
rbitfld.long 0x20 23. "NU50_1,Reserved" "0,1"
hexmask.long.byte 0x20 16.--22. 1. "F1S,Rx FIFO 0 Size"
rbitfld.long 0x20 15. "NU50,Reserved" "0,1"
newline
hexmask.long.word 0x20 2.--14. 1. "F1SA,Rx FIFO 0 Start Address"
rbitfld.long 0x20 0.--1. "NU499,Reserved" "0,1,2,3"
line.long 0x24 "RXF1S,RXF1S"
bitfld.long 0x24 26.--31. "NU54,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 25. "RF1L,Rx FIFO 0 Message Lost" "0,1"
bitfld.long 0x24 24. "F1F,Rx FIFO 0 Full" "0,1"
bitfld.long 0x24 22.--23. "NU53,Reserved" "0,1,2,3"
bitfld.long 0x24 16.--21. "F1PI,Rx FIFO 0 Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x24 14.--15. "NU52,Reserved" "0,1,2,3"
bitfld.long 0x24 8.--13. "F1GI,Rx FIFO 0 Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x24 7. "NU51,Reserved" "0,1"
hexmask.long.byte 0x24 0.--6. 1. "F1FL,Rx FIFO 0 Fill Level"
line.long 0x28 "RXF1A,RXF1A"
hexmask.long 0x28 6.--31. 1. "NU55,Reserved"
bitfld.long 0x28 0.--5. "F1AI,Rx FIFO 0 Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "RXESC,RXESC"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU58,Reserved"
bitfld.long 0x2C 8.--10. "RBDS,Rx Buffer data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 7. "NU57,Reserved" "0,1"
bitfld.long 0x2C 4.--6. "F1DS,Rx FIFO 1 Data Field Size" "0,1,2,3,4,5,6,7"
rbitfld.long 0x2C 3. "NU56,Reserved" "0,1"
newline
bitfld.long 0x2C 0.--2. "F0DS,Rx FIFO 0 Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x30 "TXBC,TXBC"
bitfld.long 0x30 31. "NU61,Reserved" "0,1"
bitfld.long 0x30 30. "TFQM,Tx FIFO/Queue Mode" "0,1"
bitfld.long 0x30 24.--29. "TFQS,Transmit FIFO/Queue Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x30 22.--23. "NU60,Reserved" "0,1,2,3"
bitfld.long 0x30 16.--21. "NDTB,Number of Dedicated Transmit Buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
hexmask.long.word 0x30 2.--15. 1. "TBSA,Tx Buffers Start Address"
bitfld.long 0x30 0.--1. "NU59,Reserved" "0,1,2,3"
line.long 0x34 "TXFQS,TXFQS"
hexmask.long.word 0x34 22.--31. 1. "NU64,Reserved"
bitfld.long 0x34 21. "TFQF,Tx FIFO/Queue Full" "0,1"
bitfld.long 0x34 16.--20. "TFQPI,Tx FIFO/Queue Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x34 13.--15. "NU63,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x34 8.--12. "TFGI,Tx Queue Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x34 6.--7. "NU62,Reserved" "0,1,2,3"
bitfld.long 0x34 0.--5. "TFFL,Tx FIFO Free Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x38 "TXESC,TXESC"
hexmask.long 0x38 3.--31. 1. "NU65,Reserved"
bitfld.long 0x38 0.--2. "TBDS,Tx Buffer Data Field Size" "0,1,2,3,4,5,6,7"
line.long 0x3C "TXBRP,TXBRP"
line.long 0x40 "TXBAR,TXBAR"
line.long 0x44 "TXBCR,TXBCR"
line.long 0x48 "TXBTO,TXBTO"
line.long 0x4C "TXBCF,TXBCF"
line.long 0x50 "TXBTIE,TXBTIE"
line.long 0x54 "TXBCIE,TXBCIE"
group.long 0x2F0++0x0F
line.long 0x00 "TXEFC,TXEFC"
bitfld.long 0x00 30.--31. "NU68,Reserved" "0,1,2,3"
bitfld.long 0x00 24.--29. "EFWM,Event FIFO Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 22.--23. "NU67,Reserved" "0,1,2,3"
bitfld.long 0x00 16.--21. "EFS,Event FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x00 2.--15. 1. "EFSA,Event FIFO Start Address"
newline
bitfld.long 0x00 0.--1. "NU66,Reserved" "0,1,2,3"
line.long 0x04 "TXEFS,TXEFS"
bitfld.long 0x04 26.--31. "NU72,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "TEFL,Tx Event FIFO Element Lost" "0,1"
bitfld.long 0x04 24. "EFF,Event FIFO Full" "0,1"
bitfld.long 0x04 21.--23. "NU71,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 16.--20. "EFPI,Event FIFO Put Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 13.--15. "NU70,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 8.--12. "EFGI,Event FIFO Get Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 6.--7. "NU69,Reserved" "0,1,2,3"
bitfld.long 0x04 0.--5. "EFFL,Event FIFO FIll Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "TXEFA,TXEFA"
hexmask.long 0x08 5.--31. 1. "NU73,Reserved"
bitfld.long 0x08 0.--4. "EFAI,Event FIFO Acknowledge Index" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x0C "RES16,RES16"
repeat 16. (list 00. 01. 02. 03. 04. 05. 06. 07. 08. 09. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x1C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x5C 0xB8 0xBC )
rgroup.long ($2+0x230)++0x03
line.long 0x00 "RES$1,RES00"
repeat.end
width 0x0B
tree.end
tree "MSS_MCANB_ECC (MSS MCANB ECC Module Registers)"
base ad:0x3F7F800
rgroup.long 0x00++0x03
line.long 0x00 "REV,Aggregator Revision Register"
bitfld.long 0x00 30.--31. "SCHEME,Scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,bu" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "MODULE_ID,Module ID"
bitfld.long 0x00 11.--15. "REVRTL,RTL version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "REVMAJ,Major version" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom version" "0,1,2,3"
bitfld.long 0x00 0.--5. "REVMIN,Minor version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x07
line.long 0x00 "VECTOR,ECC Vector Register"
hexmask.long.byte 0x00 25.--31. 1. "NU1,Reserved"
bitfld.long 0x00 24. "RD_SVBUS_DONE,Status to indicate if read on serial VBUS is complete write of any value will clear this bit" "0,1"
hexmask.long.byte 0x00 16.--23. 1. "RD_SVBUS_ADDR,Read address"
bitfld.long 0x00 15. "RD_SVBUS,Write 1 to trigger a read on the serial VBUS" "0,1"
newline
rbitfld.long 0x00 11.--14. "NU0,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x00 0.--10. 1. "ECC_VEC,Value written to select the corresponding ECC RAM for control or status"
line.long 0x04 "STAT,Misc Status"
hexmask.long.tbyte 0x04 11.--31. 1. "NU2,Reserved"
hexmask.long.word 0x04 0.--10. 1. "NUM_RAMS,Indicates the number of RAMS serviced by the ECC aggregator"
group.long 0x14++0x17
line.long 0x00 "CTRL,CTRL"
hexmask.long.tbyte 0x00 9.--31. 1. "NU3,TI Internal : Reserved"
bitfld.long 0x00 8. "CHECK TIMEOUT,TI Internal : Check timeout" "0,1"
bitfld.long 0x00 7. "CHECK PARITY,TI Internal : Check Parity" "0,1"
bitfld.long 0x00 6. "ERROR_ONCE,TI Internal : Force Error only once" "0,1"
newline
bitfld.long 0x00 5. "FORCE_N_ROW,TI Internal : Force Error on any RAM" "0,1"
bitfld.long 0x00 4. "FORCE_DED,TI Internal : Force Double Bit Error" "0,1"
bitfld.long 0x00 3. "FORCE_SEC,TI Internal : Force Single Bit Error" "0,1"
bitfld.long 0x00 2. "EN_RMW,TI Internal : Enable rmw" "0,1"
newline
bitfld.long 0x00 1. "ECC_CHK,TI Internal : Enable ECC check" "0,1"
bitfld.long 0x00 0. "ECC_EN,TI Internal : Enable ECC" "0,1"
line.long 0x04 "ERR_CTRL1,ERR_CTRL1"
line.long 0x08 "ERR_CTRL2,ERR_CTRL2"
hexmask.long.word 0x08 16.--31. 1. "ECC_BIT2,TI Internal : Data bit that needs to be flipped if double bit error needs to be forced"
hexmask.long.word 0x08 0.--15. 1. "ECC_BIT1,TI Internal : Data bit that needs to be flipped when force_sec is set"
line.long 0x0C "ERR_STAT1,ERR_STAT1"
hexmask.long.word 0x0C 16.--31. 1. "ECC_BIT1_STS,TI Internal : Data bit that corresponds to the single-bit error"
bitfld.long 0x0C 15. "CLR_ECC_CTRL_REG,TI Internal : Clear Ctrl Reg Error Status" "0,1"
bitfld.long 0x0C 13.--14. "CLR_ECC_PAR,TI Internal : Clear Parity Error Status" "0,1,2,3"
bitfld.long 0x0C 12. "CLR_ECC_OTHER,TI Internal : Clear Other Error Status" "0,1"
newline
bitfld.long 0x0C 10.--11. "CLR_ECC_DED,TI Internal : Clear Double Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 8.--9. "CLR_ECC_SEC,TI Internal : Clear Single Bit Error Status" "0,1,2,3"
bitfld.long 0x0C 7. "ECC_CTRL_REG,TI Internal : Force ctrl reg pending interrupt" "0,1"
bitfld.long 0x0C 5.--6. "ECC_PAR,TI Internal : Force ECC parity pending interrupt" "0,1,2,3"
newline
bitfld.long 0x0C 4. "ECC_OTHER,TI Internal : Force ECC other pending interrupt" "0,1"
bitfld.long 0x0C 2.--3. "ECC_DED,TI Internal : Force ECC DED pending interrupt" "0,1,2,3"
bitfld.long 0x0C 0.--1. "ECC_SEC,TI Internal : Force ECC SEC pending interrupt" "0,1,2,3"
line.long 0x10 "ERR_STAT2,ERR_STAT2"
line.long 0x14 "ERR_STAT3,ERR_STAT3"
hexmask.long.tbyte 0x14 10.--31. 1. "NU6,TI Internal : Reserved"
bitfld.long 0x14 9. "CLR_TIMEOUT_PEND,TI Internal : Clear timeout pending" "0,1"
hexmask.long.byte 0x14 2.--8. 1. "NU5,TI Internal : Reserved"
bitfld.long 0x14 1. "TIMEOUT_PEND,TI Internal : Timeout pending" "0,1"
newline
rbitfld.long 0x14 0. "NU4,TI Internal : Reserved" "0,1"
group.long 0x3C++0x07
line.long 0x00 "SEC_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU7,Reserved"
bitfld.long 0x00 0. "SEC_EOI_WR,EOI Register" "0,1"
line.long 0x04 "SEC_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU8,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "SEC_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x80++0x03
line.long 0x00 "SEC_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU9,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0xC0++0x03
line.long 0x00 "SEC_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU10,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "SEC_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x13C++0x07
line.long 0x00 "DED_EOI_REG,EOI Register"
hexmask.long 0x00 1.--31. 1. "NU11,Reserved"
bitfld.long 0x00 0. "DED_EOI_WR,EOI Register" "0,1"
line.long 0x04 "DED_STATUS_REG0,Interrupt Status Register 0"
hexmask.long 0x04 2.--31. 1. "NU12,Reserved"
bitfld.long 0x04 1. "CTRL_EDC_VBUSS_PEND,Interrupt Pending Status for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x04 0. "DED_PEND,Interrupt Pending Status for msgmem_pend" "0,1"
group.long 0x180++0x03
line.long 0x00 "DED_ENABLE_SET_REG0,Interrupt Enable Set Register 0"
hexmask.long 0x00 2.--31. 1. "NU13,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_SET,Interrupt Enable Set Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_SET,Interrupt Enable Set Register for msgmem_pend" "0,1"
group.long 0x1C0++0x03
line.long 0x00 "DED_ENABLE_CLR_REG0,Interrupt Enable Clear Register 0"
hexmask.long 0x00 2.--31. 1. "NU14,Reserved"
bitfld.long 0x00 1. "CTRL_EDC_VBUSS_ENABLE_CLR,Interrupt Enable Clear Register for ctrl_edc_vbuss_pend" "0,1"
bitfld.long 0x00 0. "DED_EN_CLR,Interrupt Enable Clear Register for msgmem_pend" "0,1"
group.long 0x200++0x0F
line.long 0x00 "AGGR_ENABLE_SET,AGGR interrupt enable set Register"
hexmask.long 0x00 2.--31. 1. "NU15,Reserved"
bitfld.long 0x00 1. "TIMEOUT,Interrupt Enable Set Register for svbus timeout errors" "0,1"
bitfld.long 0x00 0. "PARITY,Interrupt Enable Set Register for parity errors" "0,1"
line.long 0x04 "AGGR_ENABLE_CLR,AGGR interrupt enable clear Register"
hexmask.long 0x04 2.--31. 1. "NU16,Reserved"
bitfld.long 0x04 1. "TIMEOUT,Interrupt Enable Clear for svbus timeout errors" "0,1"
bitfld.long 0x04 0. "PARITY,Interrupt Enable Clear for parity errors" "0,1"
line.long 0x08 "AGGR_STATUS_SET,AGGR interrupt status set Register"
hexmask.long 0x08 4.--31. 1. "NU17,Reserved"
bitfld.long 0x08 2.--3. "TIMEOUT,Interrupt status set for svbus timeout errors" "0,1,2,3"
bitfld.long 0x08 0.--1. "PARITY,Interrupt status set for parity errors" "0,1,2,3"
line.long 0x0C "AGGR_STATUS_CLR,AGGR interrupt status clear Register"
hexmask.long 0x0C 4.--31. 1. "NU18,Reserved"
bitfld.long 0x0C 2.--3. "TIMEOUT,Interrupt status clear for svbus timeout errors" "0,1,2,3"
bitfld.long 0x0C 0.--1. "PARITY,Interrupt status clear for parity errors" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_MCRC (MSS MCRC Module Registers)"
base ad:0xC5020000
group.long 0x00++0x03
line.long 0x00 "CRC_CTRL0,Contains sw reset control bit to reset PSA"
rbitfld.long 0x00 31. "NU12,Reserved" "0,1"
rbitfld.long 0x00 30. "NU11,Reserved" "0,1"
newline
rbitfld.long 0x00 29. "NU10,Reserved" "0,1"
rbitfld.long 0x00 27.--28. "NU9,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 25.--26. "NU8,Reserved" "0,1,2,3"
rbitfld.long 0x00 24. "NU7,Reserved" "0,1"
newline
rbitfld.long 0x00 23. "NU6,Reserved" "0,1"
rbitfld.long 0x00 22. "NU5,Reserved" "0,1"
newline
rbitfld.long 0x00 21. "NU4,Reserved" "0,1"
rbitfld.long 0x00 19.--20. "NU3,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 17.--18. "NU2,Reserved" "0,1,2,3"
rbitfld.long 0x00 16. "NU1,Reserved" "0,1"
newline
bitfld.long 0x00 15. "CH2_CRC_SEL2,Refer 'CH2_DW_SEL' field description" "0,1"
bitfld.long 0x00 14. "CH2_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 13. "CH2_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 11.--12. "CH2_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 9.--10. "CH2_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 8. "CH2_PSA_SWREST,Channel 2 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
newline
bitfld.long 0x00 7. "CH1_CRC_SEL2,Refer 'CH1_DW_SEL' field description" "0,1"
bitfld.long 0x00 6. "CH1_BYTE_SWAP,BYTE SWAP Enable across Data Size 0 - Byte Swap Disabled 1 - Byte Swap enabled" "0,1"
newline
bitfld.long 0x00 5. "CH1_BIT_SWAP,msb/lsb SWAPPING 0 - msb (most significant bit First) 1 - lsb (least significant bit First)" "0,1"
bitfld.long 0x00 3.--4. "CH1_CRC_SEL,CRC type select" "?,CRC-16 010 - CRC-32,?,E2E Profile 4"
newline
bitfld.long 0x00 1.--2. "CH1_DW_SEL,CRC Data Size select" "0,1,2,3"
bitfld.long 0x00 0. "CH1_PSA_SWREST,Channel 1 PSA Software Reset" "PSA Signature Register not reset,PSA Signature Register reset"
group.long 0x08++0x03
line.long 0x00 "CRC_CTRL1,Contains power down control bit"
hexmask.long 0x00 1.--31. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "PWDN,Power Down" "MCRC is not in power down mode,MCRC is in power down mode"
group.long 0x10++0x03
line.long 0x00 "CRC_CTRL2,Contains channel mode. data trace enable control bits"
rbitfld.long 0x00 26.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 24.--25. "NU14,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 18.--23. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 16.--17. "NU13,Reserved" "0,1,2,3"
newline
rbitfld.long 0x00 10.--15. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x00 8.--9. "CH2_MODE,Channel 2 Mode: 0" "reserved 1,Full-CPU mode,?..."
newline
rbitfld.long 0x00 5.--7. "Reserved2,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "CH1_TRACEEN,Channel 1 Data Trace Enable" "Data Trace disable,Data Trace enable"
newline
rbitfld.long 0x00 2.--3. "Reserved1,Reserved" "0,1,2,3"
bitfld.long 0x00 0.--1. "CH1_MODE,Channel 1 Mode: 0" "reserved 1,Full-CPU mode,?..."
group.long 0x18++0x03
line.long 0x00 "CRC_INTS,Write one to a bit to enable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU22,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU21,Reserved" "0,1"
rbitfld.long 0x00 26. "NU20,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU19,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU18,Reserved" "0,1"
rbitfld.long 0x00 19. "NU17,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU16,Reserved" "0,1"
rbitfld.long 0x00 17. "NU15,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENS,Channel 2 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
newline
bitfld.long 0x00 11. "CH2_UNDERENS,Channel 2 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
bitfld.long 0x00 10. "CH2_OVERENS,Channel 2 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENS,Channel 2 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENS,Channel 1 Timeout Interrupt Enable Bit" "Has no effect,Timeout Interrupt enable"
bitfld.long 0x00 3. "CH1_UNDERENS,Channel 1 Underrun Interrupt Enable Bit" "Has no effect,Underrun Interrupt enable"
newline
bitfld.long 0x00 2. "CH1_OVERENS,Channel 1 Overrun Interrupt Enable Bit" "Has no effect,Overrun Interrupt enable"
bitfld.long 0x00 1. "CH1_CRCFAILENS,Channel 1 CRC Fail Interrupt Enable Bit" "Has no effect,CRC Fail Interrupt enable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x20++0x03
line.long 0x00 "CRC_INTR,Write one to a bit to disable a interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU30,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU29,Reserved" "0,1"
rbitfld.long 0x00 26. "NU28,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU27,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU26,Reserved" "0,1"
rbitfld.long 0x00 19. "NU25,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU24,Reserved" "0,1"
rbitfld.long 0x00 17. "NU23,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUTENR,Channel 2 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
newline
bitfld.long 0x00 11. "CH2_UNDERENR,Channel 2 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
bitfld.long 0x00 10. "CH2_OVERENR,Channel 2 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
newline
bitfld.long 0x00 9. "CH2_CRCFAILENR,Channel 2 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUTENR,Channel 1 Timeout Interrupt Disable Bit" "Has no effect,Timeout Interrupt disable"
bitfld.long 0x00 3. "CH1_UNDERENR,Channel 1 Underrun Interrupt Disable Bit" "Has no effect,Underrun Interrupt disable"
newline
bitfld.long 0x00 2. "CH1_OVERENR,Channel 1 Overrun Interrupt Disable Bit" "Has no effect,Overrun Interrupt disable"
bitfld.long 0x00 1. "CH1_CRCFAILENR,Channel 1 CRC Fail Interrupt Disable Bit" "Has no effect,CRC Fail Interrupt disable"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x28++0x03
line.long 0x00 "CRC_STATUS_REG,Contains interrupt flags for different types of interrupt"
rbitfld.long 0x00 29.--31. "Reserved5,Reserved" "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 28. "NU38,Reserved" "0,1"
newline
rbitfld.long 0x00 27. "NU37,Reserved" "0,1"
rbitfld.long 0x00 26. "NU36,Reserved" "0,1"
newline
rbitfld.long 0x00 25. "NU35,Reserved" "0,1"
rbitfld.long 0x00 21.--24. "Reserved4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x00 20. "NU34,Reserved" "0,1"
rbitfld.long 0x00 19. "NU33,Reserved" "0,1"
newline
rbitfld.long 0x00 18. "NU32,Reserved" "0,1"
rbitfld.long 0x00 17. "NU31,Reserved" "0,1"
newline
rbitfld.long 0x00 13.--16. "Reserved3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 12. "CH2_TIMEOUT,Channel 2 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
newline
bitfld.long 0x00 11. "CH2_UNDER,Channel 2 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
bitfld.long 0x00 10. "CH2_OVER,Channel 2 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
newline
bitfld.long 0x00 9. "CH2_CRCFAIL,Channel 2 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
rbitfld.long 0x00 5.--8. "Reserved2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 4. "CH1_TIMEOUT,Channel 1 CRC Timeout Status Flag" "No timeout interrupt is active,Timeout interrupt is active"
bitfld.long 0x00 3. "CH1_UNDER,Channel 1 CRC Underrun Status Flag" "No underrun interrupt is active,Underrun interrupt is active"
newline
bitfld.long 0x00 2. "CH1_OVER,Channel 1 CRC Overrun Status Flag" "No overrun interrupt is active,Overrun interrupt is active"
bitfld.long 0x00 1. "CH1_CRCFAIL,Channel 1 CRC Compare Fail Status Flag" "No CRC compare fail interrupt is active,CRC compare fail interrupt is active"
newline
rbitfld.long 0x00 0. "Reserved1,Reserved" "0,1"
group.long 0x30++0x03
line.long 0x00 "CRC_INT_OFFSET_REG,Contains the interrupt offset vector address"
hexmask.long.tbyte 0x00 8.--31. 1. "Reserved1,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "OFSTREG,CRC Interrupt Offset"
rgroup.long 0x38++0x03
line.long 0x00 "CRC_BUSY,Contains the busy flag for each channel"
hexmask.long.byte 0x00 25.--31. 1. "Reserved4,Reserved"
bitfld.long 0x00 24. "NU40,Reserved" "0,1"
newline
hexmask.long.byte 0x00 17.--23. 1. "Reserved3,Reserved"
bitfld.long 0x00 16. "NU39,Reserved" "0,1"
newline
hexmask.long.byte 0x00 9.--15. 1. "Reserved2,Reserved"
bitfld.long 0x00 8. "Ch2_BUSY,Ch2_BUSY" "0,1"
newline
hexmask.long.byte 0x00 1.--7. 1. "Reserved1,Reserved"
bitfld.long 0x00 0. "CH1_BUSY,CH1_BUSY" "0,1"
group.long 0x40++0x13
line.long 0x00 "CRC_PCOUNT_REG1,Channel 1 preload register for the pattern count"
hexmask.long.word 0x00 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x00 0.--19. 1. "CRC_PAT_COUNT1,Channel 1 Pattern Counter Preload Register"
line.long 0x04 "CRC_SCOUNT_REG1,Channel 1 preload register for the sector count"
hexmask.long.word 0x04 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x04 0.--15. 1. "CRC_SEC_COUNT1,Channel 1 Sector Counter Preload Register"
line.long 0x08 "CRC_CURSEC_REG1,Channel 1 current sector register contains the sector number which causes CRC failure"
hexmask.long.word 0x08 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x08 0.--15. 1. "CRC_CURSEC1,Channel 1 Current Sector ID Register"
line.long 0x0C "CRC_WDTOPLD1,Channel 1 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x0C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x0C 0.--23. 1. "CRC_WDTOPLD1,Channel 1 Watchdog Timeout Counter Preload Register"
line.long 0x10 "CRC_BCTOPLD1,Channel 1 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x10 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x10 0.--23. 1. "CRC_BCTOPLD1,Channel 1 Block Complete Timeout Counter Preload Regis- ter"
group.long 0x60++0x33
line.long 0x00 "PSA_SIGREGL1,Channel 1 PSA signature low register"
line.long 0x04 "PSA_SIGREGH1,Channel 1 PSA signature high register"
line.long 0x08 "CRC_REGL1,Channel 1 CRC value low register"
line.long 0x0C "CRC_REGH1,Channel 1 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL1,Channel 1 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH1,Channel 1 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL1,Channel 1 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH1,Channel 1 un-compressed raw data high register"
line.long 0x20 "CRC_PCOUNT_REG2,Channel 2 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "CRC_PAT_COUNT2,Channel 2 Pattern Counter Preload Register"
line.long 0x24 "CRC_SCOUNT_REG2,Channel 2 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "CRC_SEC_COUNT2,Channel 2 Sector Counter Preload Register"
line.long 0x28 "CRC_CURSEC_REG2,Channel 2 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "CRC_CURSEC2,Channel 2 Current Sector ID Register"
line.long 0x2C "CRC_WDTOPLD2,Channel 2 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "CRC_WDTOPLD2,Channel 2 Watchdog Timeout Counter Preload Register"
line.long 0x30 "CRC_BCTOPLD2,Channel 2 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "CRC_BCTOPLD2,Channel 2 Block Complete Timeout Counter Preload Regis- ter"
group.long 0xA0++0x33
line.long 0x00 "PSA_SIGREGL2,Channel 2 PSA signature low register"
line.long 0x04 "PSA_SIGREGH2,Channel 2 PSA signature high register"
line.long 0x08 "CRC_REGL2,Channel 2 CRC value low register"
line.long 0x0C "CRC_REGH2,Channel 2 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL2,Channel 2 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH2,Channel 2 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL2,Channel 2 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH2,Channel 2 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG3,Channel 3 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU41,Reserved"
line.long 0x24 "CRC_SCOUNT_REG3,Channel 3 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU42,Reserved"
line.long 0x28 "CRC_CURSEC_REG3,Channel 3 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU43,Reserved"
line.long 0x2C "CRC_WDTOPLD3,Channel 3 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU44,Reserved"
line.long 0x30 "CRC_BCTOPLD3,Channel 3 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU45,Reserved"
rgroup.long 0xE0++0x33
line.long 0x00 "PSA_SIGREGL3,Channel 3 PSA signature low register"
line.long 0x04 "PSA_SIGREGH3,Channel 3 PSA signature high register"
line.long 0x08 "CRC_REGL3,Channel 3 CRC value low register"
line.long 0x0C "CRC_REGH3,Channel 3 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL3,Channel 3 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH3,Channel 3 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL3,Channel 3 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH3,Channel 3 un-compressed raw data high Register"
line.long 0x20 "CRC_PCOUNT_REG4,Channel 4 preload register for the pattern count"
hexmask.long.word 0x20 20.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x20 0.--19. 1. "NU54,Reserved"
line.long 0x24 "CRC_SCOUNT_REG4,Channel 4 preload register for the sector count"
hexmask.long.word 0x24 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x24 0.--15. 1. "NU55,Reserved"
line.long 0x28 "CRC_CURSEC_REG4,Channel 4 current sector register contains the sector number which causes CRC fail-ure"
hexmask.long.word 0x28 16.--31. 1. "Reserved1,Reserved"
hexmask.long.word 0x28 0.--15. 1. "NU56,Reserved"
line.long 0x2C "CRC_WDTOPLD4,Channel 4 timeout pre-load value to check if within a given time DMA initiates a block transfer"
hexmask.long.byte 0x2C 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x2C 0.--23. 1. "NU57,Reserved"
line.long 0x30 "CRC_BCTOPLD4,Channel 4 timeout pre-load value to check if one block of patterns are compressed with a given time"
hexmask.long.byte 0x30 24.--31. 1. "Reserved1,Reserved"
hexmask.long.tbyte 0x30 0.--23. 1. "NU58,Reserved"
rgroup.long 0x120++0x27
line.long 0x00 "PSA_SIGREGL4,Channel 4 PSA signature low register"
line.long 0x04 "PSA_SIGREGH4,Channel 4 PSA signature high register"
line.long 0x08 "CRC_REGL4,Channel 4 CRC value low register"
line.long 0x0C "CRC_REGH4,Channel 4 CRC value high register"
line.long 0x10 "PSA_SECSIGREGL4,Channel 4 PSA sector signature low regis-ter"
line.long 0x14 "PSA_SECSIGREGH4,Channel 4 PSA sector signature high regis-ter"
line.long 0x18 "RAW_DATAREGL4,Channel 4 un-compressed raw data low register"
line.long 0x1C "RAW_DATAREGH4,Channel 4 un-compressed raw data high Register"
line.long 0x20 "MCRC_BUS_SEL,Disables either or all tracing of data buses"
hexmask.long 0x20 3.--31. 1. "NU67,Reserved"
bitfld.long 0x20 2. "MEn,MEn" "Tracing of VBUSM master bus has been disabled,Tracing of VBUSM master bus has been enabled"
newline
bitfld.long 0x20 1. "DTCMEn,DTCMEn" "Tracing of DTCM_ODD and DTCM_EVEN buses have..,Tracing of DTCM_ODD and DTCM_EVEN buses have.."
bitfld.long 0x20 0. "ITCMEn,ITCMEn" "Tracing of ITCM bus has been disabled,Tracing of ITCM bus has been enabled"
line.long 0x24 "MCRC_RESERVED,0x144 to 0x1FF is reserved area"
width 0x0B
tree.end
tree "MSS_PCR1 (MSS PCR1 Module Registers)"
base ad:0x2F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "MSS_PCR2 (MSS PCR2 Module Registers)"
base ad:0x3F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
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abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "MSS_QSPI (MSS QSPI Module Registers)"
base ad:0xC8000000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID"
bitfld.long 0x00 30.--31. "SCHEME,The scheme of the register used" "0,1,2,3"
bitfld.long 0x00 28.--29. "Reserved,Always read as 0" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,The function of the module being used"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Release Version The PDR release number of this IP" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Release Number" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom IP" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Release Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x10++0x03
line.long 0x00 "SYSCONFIG,SYSCONFIG"
hexmask.long 0x00 6.--31. 1. "Reserved3,Always read as 0"
rbitfld.long 0x00 4.--5. "Reserved2,Always read as 0" "0,1,2,3"
bitfld.long 0x00 2.--3. "IDLEMODE,Configuration of the local target state management mode" "Force-idle mode,No-idle mode,Smart-idle mode,Smart-idle wakeup-capable mode"
newline
rbitfld.long 0x00 0.--1. "Reserved1,Always read as 0" "0,1,2,3"
group.long 0x20++0x13
line.long 0x00 "INTR_STATUS_RAW_SET,INTR Interrupt Status Raw/Set Register"
hexmask.long 0x00 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x00 1. "WIRQ_RAW,Word Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.."
bitfld.long 0x00 0. "FIRQ_RAW,Frame Interrupt Status Read indicates raw status" "inactive,active Writing 1 will.."
line.long 0x04 "INTR_STATUS_ENABLED_CLEAR,INTR Interrupt Status Enabled/Clear Register"
hexmask.long 0x04 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x04 1. "WIRQ_ENA,Word Interrupt Enabled Status Read indicates enabled status" "inactive,active Writing 1 will.."
bitfld.long 0x04 0. "FIRQ_ENA,Frame Interrupt Enabled Status Read indicates enabled status" "inactive,active Writing 1 will.."
line.long 0x08 "INTR_ENABLE_SET,INTR Interrupt Enable/Set Register"
hexmask.long 0x08 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x08 1. "WIRQ_ENA_SET,Word Interrupt Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
bitfld.long 0x08 0. "FIRQ_ENA_SET,Frame Interrupt Enable/Set Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
line.long 0x0C "INTR_ENABLE_CLEAR,INTR Interrupt Enable/Clear Register"
hexmask.long 0x0C 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x0C 1. "WIRQ_ENA_CLR,Word Interrupt Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
bitfld.long 0x0C 0. "FIRQ_ENA_CLR,Frame Interrupt Enable/Clear Read indicates interrupt enable" "disabled,enabled Writing 1 will.."
line.long 0x10 "INTC_EOI,EOI Register"
group.long 0x40++0x27
line.long 0x00 "SPI_CLOCK_CNTRL,SPI Clock Control Register (SPICC)"
bitfld.long 0x00 31. "CLKEN,Clock Enable" "0,1"
hexmask.long.word 0x00 16.--30. 1. "Reserved,Always read as 0"
hexmask.long.word 0x00 0.--15. 1. "DCLK_DIV,Serial data clock divide by ratio"
line.long 0x04 "SPI_DC,SPI Data Control Register (SPIDC)"
rbitfld.long 0x04 29.--31. "Reserved4,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 27.--28. "DD3,Data delay for chip select 3 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
bitfld.long 0x04 26. "CKPH3,Clock phase for chip select 3 If CKP0 = 0 0- Data shifted out on falling edge; input on rising edge 1- Data shifted out on rising edge; input on falling edge If CKP0 = 1 1- Data shifted out on falling edge; input on rising edge 0- Data shifted out.." "0,1"
newline
bitfld.long 0x04 25. "CSP3,Chip select polarity for chip select 3 0- Active low 1- Active high" "0,1"
bitfld.long 0x04 24. "CKP3,Clock polarity for chip select 3 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
rbitfld.long 0x04 21.--23. "Reserved3,Always read as 0" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x04 19.--20. "DD2,Data delay for chip select 2 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
bitfld.long 0x04 18. "CKPH2,Clock phase for chip select 2" "0,1"
bitfld.long 0x04 17. "CSP2,Chip select polarity for chip select 2 0- Active low 1- Active high" "0,1"
newline
bitfld.long 0x04 16. "CKP2,Clock polarity for chip select 2 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
rbitfld.long 0x04 13.--15. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11.--12. "DD1,Data delay for chip select 1 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
newline
bitfld.long 0x04 10. "CKPH1,Clock phase for chip select 1" "0,1"
bitfld.long 0x04 9. "CSP1,Chip select polarity for chip select 1 0- Active low 1- Active high" "0,1"
bitfld.long 0x04 8. "CKP1,Clock polarity for chip select 1 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
newline
rbitfld.long 0x04 5.--7. "Reserved1,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3.--4. "DD0,Data delay for chip select 0 00- Data is output on the same cycle as the CS_N goes active 01- Data is output 1 DCLK cycle after the CS_N goes active 10- Data is output 2 DCLK cycles after the CS_N goes active 11- Data is output 3 DCLK cycles after.." "0,1,2,3"
bitfld.long 0x04 2. "CKPH0,Clock phase for chip select 0" "0,1"
newline
bitfld.long 0x04 1. "CSP0,Chip select polarity for chip select 0 0- Active low 1- Active high" "0,1"
bitfld.long 0x04 0. "CKP0,Clock polarity for chip select 0 0- When data is not being transferred SCK = 0 1- When data is not being transferred SCK = 1" "0,1"
line.long 0x08 "SPI_CMD,SPI Command Register (SPICR)"
rbitfld.long 0x08 30.--31. "Reserved3,Always read as 0" "0,1,2,3"
bitfld.long 0x08 28.--29. "CSNUM,Device select" "0,1,2,3"
rbitfld.long 0x08 26.--27. "Reserved2,Always read as 0" "0,1,2,3"
newline
hexmask.long.byte 0x08 19.--25. 1. "WLEN,Word length"
bitfld.long 0x08 16.--18. "CMD,Transfer command 000- Reserved 001- 4 pin Read Single 010- 4 pin Write Single 011- 4 pin Read Dual 100 - Reserved 101 - 3 pin Read Single 110 - 3 pin Write Single 111 - 6 pin Read Quad" "0,1,2,3,4,5,6,7"
bitfld.long 0x08 15. "FIRQ,Frame count interrupt enable" "0,1"
newline
bitfld.long 0x08 14. "WIRQ,Word count interrupt enable" "0,1"
rbitfld.long 0x08 12.--13. "Reserved1,Always read as 0" "0,1,2,3"
hexmask.long.word 0x08 0.--11. 1. "FLEN,Frame Length 0- 1 word 1- 2 words ... 4095 - 4096 words"
line.long 0x0C "SPI_STATUS,SPI Status Register (SPISR)"
bitfld.long 0x0C 28.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hexmask.long.word 0x0C 16.--27. 1. "WDCNT,Word count"
hexmask.long.word 0x0C 3.--15. 1. "Reserved1,Always read as 0"
newline
bitfld.long 0x0C 2. "FC,Frame complete" "0,1"
bitfld.long 0x0C 1. "WC,Word complete" "0,1"
bitfld.long 0x0C 0. "BUSY,Busy bit" "0,1"
line.long 0x10 "SPI_DATA,SPI Data Register (SPIDR)"
line.long 0x14 "SPI_SETUP0,Memory Mapped SPI Setup0 Register"
rbitfld.long 0x14 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x14 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x14 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x14 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x14 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x14 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x14 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x14 0.--7. 1. "RCMD,Read Command"
line.long 0x18 "SPI_SETUP1,Memory Mapped SPI Setup1 Register"
rbitfld.long 0x18 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x18 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x18 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x18 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x18 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x18 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x18 0.--7. 1. "RCMD,Read Command"
line.long 0x1C "SPI_SETUP2,Memory Mapped SPI Setup2 Register"
rbitfld.long 0x1C 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x1C 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x1C 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x1C 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x1C 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x1C 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x1C 0.--7. 1. "RCMD,Read Command"
line.long 0x20 "SPI_SETUP3,Memory Mapped SPI Setup3 Register"
rbitfld.long 0x20 29.--31. "Reserved2,Always read as 0" "0,1,2,3,4,5,6,7"
bitfld.long 0x20 24.--28. "NUM_D_BITS,Number of dummy bits to use if NUM_D_BYTES = 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hexmask.long.byte 0x20 16.--23. 1. "WCMD,Write Command"
newline
rbitfld.long 0x20 14.--15. "Reserved1,Always read as 0" "0,1,2,3"
bitfld.long 0x20 12.--13. "READ_TYPE,Determines if the read command is a single dual or quad read mode command 00 - Normal read (all data input on spi_din) 01 - Dual read (odd bytes input on spi_din; even on spi_dout) 10 - Normal read (all data input on spi_din) 11 - Quad read.." "0,1,2,3"
bitfld.long 0x20 10.--11. "NUM_D_BYTES,Number of dummy bytes to be used for fast" "use the value in NUM_D_BITS,use 8 bits,use 16 bits,use 24 bits"
newline
bitfld.long 0x20 8.--9. "NUM_A_BYTES,Number of address bytes to be sent" "1 byte,2 bytes,3 bytes,4 bytes"
hexmask.long.byte 0x20 0.--7. 1. "RCMD,Read Command"
line.long 0x24 "SPI_SWITCH,Memory Mapped SPI Switch Register"
hexmask.long 0x24 2.--31. 1. "Reserved,Always read as 0"
bitfld.long 0x24 1. "MM_INT_EN,Memory Mapped mode interrupt enable" "0,1"
bitfld.long 0x24 0. "MMPT_S,MMPT select" "0,1"
repeat 3. (list 1. 2. 3. )(list 0x00 0x04 0x08 )
group.long ($2+0x68)++0x03
line.long 0x00 "SPI_DATA$1,SPI Data Register (SPIDR1)"
repeat.end
repeat 9. (list 1. 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x10 0x14 0x18 0x30 0x34 0x38 )
rgroup.long ($2+0x04)++0x03
line.long 0x00 "MSS_QSPI_Reserved$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_R5SS_STC (MSS R5SS STC Module Registers)"
base ad:0x2F79800
group.long 0x00++0x11B
line.long 0x00 "STCGCR0,Self test Global control Reg0"
hexmask.long.word 0x00 16.--31. 1. "INTCOUNT_B16,Number of intervals of the self test run (RWP - Read Priviledge Mode Write only) Count of intervals that need to be covered for a specific selftest run"
newline
rbitfld.long 0x00 11.--15. "NU0,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only) Idle Cycles before and after capture clock" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 5.--7. "SCANEN_HIGH_CAP_IDLE_CYCLE,Idle cycles before and after capture clock (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 2.--4. "NU1,Reserved bits" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--1. "RS_CNT_B1,Restart/Continue or preload (RWP - Read Priviledge Mode Write only) This bit specifies the selftest controller whether to continue the run from next interval onwards restart from ROM address 0 or preload from a prescribed interval" "Continue NSTC run from previous interval,Restart NSTC run from ROM address 0 1X = Start..,?..."
line.long 0x04 "STCGCR1,Self test Global control Reg1"
hexmask.long.tbyte 0x04 12.--31. 1. "NU2,Reserved bits"
newline
bitfld.long 0x04 8.--11. "SEG0_CORE_SEL,Selects the Segment0 CORE for self test (RWP - Read Priviledge Mode Write only) Select the Segment0 CORE for Self -Test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x04 7. "NU3,Reserved bits" "0,1"
newline
bitfld.long 0x04 6. "CODEC_SPREAD_MODE,Codec Spread Mode control signal (RWP - Read Priviledge Mode Write only) This bit is used to configure the codec in spread / X-OR mode" "XOR mode,Spread mode"
newline
bitfld.long 0x04 5. "LP_SCAN_MODE,LP scan mode (RWP - Read Priviledge Mode Write only) This bit is used to decide the scan configuration" "Operates in Normal Scan Mode,Operates in Low Power Scan Mode"
newline
bitfld.long 0x04 4. "ROM_ACCESS_INV,Rom access inversion mode (RWP - Read Priviledge Mode Write only) - NOT SUPPORTED" "0,1"
newline
bitfld.long 0x04 0.--3. "ST_ENA_B4,Self test enable key (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "STCTPR,Time out counter preload register"
line.long 0x0C "STC_CADDR,Current Address register for CORE1"
line.long 0x10 "STCCICR,Current Interval count register"
hexmask.long.word 0x10 16.--31. 1. "CORE2_ICOUNT,Specifies the last interval number for CORE2 This specifies the Last executed Interval number for CORE2 of Segment0 if self test is being executed for secondary core as well"
newline
hexmask.long.word 0x10 0.--15. 1. "CORE1_ICOUNT,Specifies the last interval number for CORE1 This specifies the Last executed Interval number of a self-test run"
line.long 0x14 "STCGSTAT,Global Status Register"
hexmask.long.tbyte 0x14 12.--31. 1. "NU4,Reserved bits"
newline
bitfld.long 0x14 8.--11. "ST_ACTIVE,Tells whether self test is currently active or not" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 2.--7. "NU5,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x14 1. "TEST_FAIL,Test_fail flag (RCP - Read Clear on Writing in Priviledge Mode)" "Self test run has not failed,SelfTest run has failed"
newline
bitfld.long 0x14 0. "TEST_DONE,Test_done_flag (RCP - Read Clear on Writing in Priviledge Mode)" "Not completed,SelfTest run Completed"
line.long 0x18 "STCFSTAT,Fail Status Register"
hexmask.long 0x18 5.--31. 1. "NU6,Reserved bits"
newline
bitfld.long 0x18 3.--4. "FSEG_ID,Failed Segment ID (RCP - Read Clear on Writing in Priviledge Mode) This field captures the Segment number for which any of the failures like TO_ER_B1 CPU1_FAIL_B1 and CPU2_FAIL_B1 occur" "Failure on Segment 0,Failure on Segment 1,Failure on Segment 2,Failure on Segment 3"
newline
bitfld.long 0x18 2. "TO_ER_B1,Tells whether self test failed because of time out error (RCP - Read Clear on Writing in Priviledge Mode)" "No time out error occurred,SelfTest run failed due to a timeout error"
newline
bitfld.long 0x18 1. "CPU2_FAIL_B1,Tells whether MISR mismatch happenned in CORE2 when in Segment0 mode (RCP - Read Clear on Writing in Priviledge Mode)" "No MISR mismatch for CORE2,Self test run failed due to MISR mismatch for.."
newline
bitfld.long 0x18 0. "CPU1_FAIL_B1,Tells whether MISR mismatch happenned in CORE1 (RCP - Read Clear on Writing in Priviledge Mode) Applicable to all segments" "No MISR mismatch for CORE1,Self test run failed due to MISR mismatch for.."
line.long 0x1C "STCSCSCR,Signature compare Self Check Register"
hexmask.long 0x1C 5.--31. 1. "NU7,Reserved bits"
newline
bitfld.long 0x1C 4. "FAULT_INS_B1,Fault Insertion bit (RWP - Read Priviledge Mode Write only)" "No fault insertion,Inserts fault in the logic unedr test which will.."
newline
bitfld.long 0x1C 0.--3. "SELF_CHECK_KEY_B4,Signature compare logic self check key enable/disable (RWP - Read Priviledge Mode Write only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "STC_CADDR2,Current Address register for CORE2"
line.long 0x24 "STC_CLKDIV,Clock Divider Register"
rbitfld.long 0x24 27.--31. "NU8,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 24.--26. "CLKDIV0,Clock division for Seg0 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 0" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 19.--23. "NU9,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 16.--18. "CLKDIV1,Clock division for Seg1 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 11.--15. "NU10,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 8.--10. "CLKDIV2,Clock division for Seg2 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x24 3.--7. "NU11,Reserved bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x24 0.--2. "CLKDIV3,Clock division for Seg3 (RWP - Read Priviledge Mode Write only) *NOT SUPPORTED X = Division ratio is X+1 for Segment 3" "0,1,2,3,4,5,6,7"
line.long 0x28 "STC_SEGPLR,Segment 1st interval Preload Register"
hexmask.long 0x28 2.--31. 1. "NU12,Reserved bits"
newline
bitfld.long 0x28 0.--1. "SEGID_PLOAD,Segment number for which preload is to be started (RWP - Read Priviledge Mode Write only) This specifies the segment for which the address of its First interval will be pre-loaded into the NSTC ROM address counter" "Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of..,Preload the address of the 1st interval of.."
line.long 0x2C "SEG0_START_ADDR,ROM Start address for Segment0"
hexmask.long.word 0x2C 20.--31. 1. "NU13,Reserved bits"
newline
hexmask.long.tbyte 0x2C 0.--19. 1. "SEG_START_ADDR,Segment 0 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x30 "SEG1_START_ADDR,ROM Start address for Segment1"
hexmask.long.word 0x30 20.--31. 1. "NU14,Reserved bits"
newline
hexmask.long.tbyte 0x30 0.--19. 1. "SEG_START_ADDR,Segment 1 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x34 "SEG2_START_ADDR,ROM Start address for Segment2"
hexmask.long.word 0x34 20.--31. 1. "NU15,Reserved bits"
newline
hexmask.long.tbyte 0x34 0.--19. 1. "SEG_START_ADDR,Segment 2 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x38 "SEG3_START_ADDR,ROM Start address for Segment3"
hexmask.long.word 0x38 20.--31. 1. "NU16,Reserved bits"
newline
hexmask.long.tbyte 0x38 0.--19. 1. "SEG_START_ADDR,Segment 3 Start Address (RWP - Read Priviledge Mode Write only) This register holds the ROM address for the start of first interval of the segment"
line.long 0x3C "CORE1_CURMISR_0,Holds the MISR signature for CORE1"
line.long 0x40 "CORE1_CURMISR_1,Holds the MISR signature for CORE1"
line.long 0x44 "CORE1_CURMISR_2,Holds the MISR signature for CORE1"
line.long 0x48 "CORE1_CURMISR_3,Holds the MISR signature for CORE1"
line.long 0x4C "CORE1_CURMISR_4,Holds the MISR signature for CORE1"
line.long 0x50 "CORE1_CURMISR_5,Holds the MISR signature for CORE1"
line.long 0x54 "CORE1_CURMISR_6,Holds the MISR signature for CORE1"
line.long 0x58 "CORE1_CURMISR_7,Holds the MISR signature for CORE1"
line.long 0x5C "CORE1_CURMISR_8,Holds the MISR signature for CORE1"
line.long 0x60 "CORE1_CURMISR_9,Holds the MISR signature for CORE1"
line.long 0x64 "CORE1_CURMISR_10,Holds the MISR signature for CORE1"
line.long 0x68 "CORE1_CURMISR_11,Holds the MISR signature for CORE1"
line.long 0x6C "CORE1_CURMISR_12,Holds the MISR signature for CORE1"
line.long 0x70 "CORE1_CURMISR_13,Holds the MISR signature for CORE1"
line.long 0x74 "CORE1_CURMISR_14,Holds the MISR signature for CORE1"
line.long 0x78 "CORE1_CURMISR_15,Holds the MISR signature for CORE1"
line.long 0x7C "CORE1_CURMISR_16,Holds the MISR signature for CORE1"
line.long 0x80 "CORE1_CURMISR_17,Holds the MISR signature for CORE1"
line.long 0x84 "CORE1_CURMISR_18,Holds the MISR signature for CORE1"
line.long 0x88 "CORE1_CURMISR_19,Holds the MISR signature for CORE1"
line.long 0x8C "CORE1_CURMISR_20,Holds the MISR signature for CORE1"
line.long 0x90 "CORE1_CURMISR_21,Holds the MISR signature for CORE1"
line.long 0x94 "CORE1_CURMISR_22,Holds the MISR signature for CORE1"
line.long 0x98 "CORE1_CURMISR_23,Holds the MISR signature for CORE1"
line.long 0x9C "CORE1_CURMISR_24,Holds the MISR signature for CORE1"
line.long 0xA0 "CORE1_CURMISR_25,Holds the MISR signature for CORE1"
line.long 0xA4 "CORE1_CURMISR_26,Holds the MISR signature for CORE1"
line.long 0xA8 "CORE1_CURMISR_27,Holds the MISR signature for CORE1"
line.long 0xAC "CORE2_CURMISR_0,Holds the MISR signature for CORE2"
line.long 0xB0 "CORE2_CURMISR_1,Holds the MISR signature for CORE2"
line.long 0xB4 "CORE2_CURMISR_2,Holds the MISR signature for CORE2"
line.long 0xB8 "CORE2_CURMISR_3,Holds the MISR signature for CORE2"
line.long 0xBC "CORE2_CURMISR_4,Holds the MISR signature for CORE2"
line.long 0xC0 "CORE2_CURMISR_5,Holds the MISR signature for CORE2"
line.long 0xC4 "CORE2_CURMISR_6,Holds the MISR signature for CORE2"
line.long 0xC8 "CORE2_CURMISR_7,Holds the MISR signature for CORE2"
line.long 0xCC "CORE2_CURMISR_8,Holds the MISR signature for CORE2"
line.long 0xD0 "CORE2_CURMISR_9,Holds the MISR signature for CORE2"
line.long 0xD4 "CORE2_CURMISR_10,Holds the MISR signature for CORE2"
line.long 0xD8 "CORE2_CURMISR_11,Holds the MISR signature for CORE2"
line.long 0xDC "CORE2_CURMISR_12,Holds the MISR signature for CORE2"
line.long 0xE0 "CORE2_CURMISR_13,Holds the MISR signature for CORE2"
line.long 0xE4 "CORE2_CURMISR_14,Holds the MISR signature for CORE2"
line.long 0xE8 "CORE2_CURMISR_15,Holds the MISR signature for CORE2"
line.long 0xEC "CORE2_CURMISR_16,Holds the MISR signature for CORE2"
line.long 0xF0 "CORE2_CURMISR_17,Holds the MISR signature for CORE2"
line.long 0xF4 "CORE2_CURMISR_18,Holds the MISR signature for CORE2"
line.long 0xF8 "CORE2_CURMISR_19,Holds the MISR signature for CORE2"
line.long 0xFC "CORE2_CURMISR_20,Holds the MISR signature for CORE2"
line.long 0x100 "CORE2_CURMISR_21,Holds the MISR signature for CORE2"
line.long 0x104 "CORE2_CURMISR_22,Holds the MISR signature for CORE2"
line.long 0x108 "CORE2_CURMISR_23,Holds the MISR signature for CORE2"
line.long 0x10C "CORE2_CURMISR_24,Holds the MISR signature for CORE2"
line.long 0x110 "CORE2_CURMISR_25,Holds the MISR signature for CORE2"
line.long 0x114 "CORE2_CURMISR_26,Holds the MISR signature for CORE2"
line.long 0x118 "CORE2_CURMISR_27,Holds the MISR signature for CORE2"
width 0x0B
tree.end
tree "MSS_RCM (MSS RCM Module Registers)"
base ad:0x2100000
rgroup.long 0x00++0x1CB
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MSS_RST_CAUSE_CLR,"
bitfld.long 0x04 0.--2. "clr,Write pulse bit field: Clear bit for rst cause register (writing '111' will clear the rst cause register)" "0,1,2,3,4,5,6,7"
line.long 0x08 "MSS_RST_STATUS,"
hexmask.long.word 0x08 0.--15. 1. "cause,Has the status because of which reset has happened"
line.long 0x0C "SYSRST_BY_DBG_RST,"
bitfld.long 0x0C 16.--18. "r5b,writing '000' will block debug reset request from CR5B toggling globally reset for CR5B" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0.--2. "r5a,writing '000' will block debug reset request from CR5A toggling globally reset for CR5A" "0,1,2,3,4,5,6,7"
line.long 0x10 "RST_ASSERDLY,"
hexmask.long.byte 0x10 0.--7. 1. "common,Value decides number of cycles reset should be asserted for CR5SS related resets"
line.long 0x14 "RST2ASSERTDLY,"
hexmask.long.byte 0x14 24.--31. 1. "r5b,Value decides number of cycles should be held before asserting reset for r5ss local reset for CR5B"
hexmask.long.byte 0x14 16.--23. 1. "r5a,Value decides number of cycles should be held before asserting reset for r5ss local reset for CR5A"
hexmask.long.byte 0x14 8.--15. 1. "r5ssb,Value decides number of cycles should be held before asserting reset for r5ss global reset for CR5B"
newline
hexmask.long.byte 0x14 0.--7. 1. "r5ssa,Value decides number of cycles should be held before asserting reset for r5ss global reset for CR5A"
line.long 0x18 "RST_WFICHECK,"
bitfld.long 0x18 24.--26. "r5b,writing '000' will disable check for WFI before local reset assertion of CR5A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 16.--18. "r5a,writing '000' will disable check for WFI before local reset assertion of CR5A" "0,1,2,3,4,5,6,7"
bitfld.long 0x18 8.--10. "r5ssb,writing '000' will disable check for WFI before global reset assertion of CR5B" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x18 0.--2. "r5ssa,writing '000' will disable check for WFI before global reset assertion of CR5A" "0,1,2,3,4,5,6,7"
line.long 0x1C "MSS_MCANA_CLK_SRC_SEL,"
hexmask.long.word 0x1C 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCANA.Data should be loaded as multibit"
line.long 0x20 "MSS_MCANB_CLK_SRC_SEL,"
hexmask.long.word 0x20 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCANB.Data should be loaded as multibit"
line.long 0x24 "MSS_QSPI_CLK_SRC_SEL,"
hexmask.long.word 0x24 0.--11. 1. "clksrcsel,Select line for selecting source clock for QSPI.Data should be loaded as multibit"
line.long 0x28 "MSS_RTIA_CLK_SRC_SEL,"
hexmask.long.word 0x28 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIA.Data should be loaded as multibit"
line.long 0x2C "MSS_RTIB_CLK_SRC_SEL,"
hexmask.long.word 0x2C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIB.Data should be loaded as multibit"
line.long 0x30 "MSS_RTIC_CLK_SRC_SEL,"
hexmask.long.word 0x30 0.--11. 1. "clksrcsel,Select line for selecting source clock for RTIC.Data should be loaded as multibit"
line.long 0x34 "MSS_WDT_CLK_SRC_SEL,"
hexmask.long.word 0x34 0.--11. 1. "clksrcsel,Select line for selecting source clock for WDT.Data should be loaded as multibit"
line.long 0x38 "MSS_SPIA_CLK_SRC_SEL,"
hexmask.long.word 0x38 0.--11. 1. "clksrcsel,Select line for selecting source clock for SPIA.Data should be loaded as multibit"
line.long 0x3C "MSS_SPIB_CLK_SRC_SEL,"
hexmask.long.word 0x3C 0.--11. 1. "clksrcsel,Select line for selecting source clock for SPIB.Data should be loaded as multibit"
line.long 0x40 "MSS_I2C_CLK_SRC_SEL,"
hexmask.long.word 0x40 0.--11. 1. "clksrcsel,Select line for selecting source clock for I2C.Data should be loaded as multibit"
line.long 0x44 "MSS_SCIA_CLK_SRC_SEL,"
hexmask.long.word 0x44 0.--11. 1. "clksrcsel,Select line for selecting source clock for SCIA.Data should be loaded as multibit"
line.long 0x48 "MSS_SCIB_CLK_SRC_SEL,"
hexmask.long.word 0x48 0.--11. 1. "clksrcsel,Select line for selecting source clock for SCIB.Data should be loaded as multibit"
line.long 0x4C "MSS_CPTS_CLK_SRC_SEL,"
hexmask.long.word 0x4C 0.--11. 1. "clksrcsel,Select line for selecting source clock for CPTS.Data should be loaded as multibit"
line.long 0x50 "MSS_CPSW_CLK_SRC_SEL,"
hexmask.long.word 0x50 0.--11. 1. "clksrcsel,Select line for selecting source clock for CPSW.Data should be loaded as multibit"
line.long 0x54 "MSS_MCANA_CLK_DIV_VAL,"
hexmask.long.word 0x54 0.--11. 1. "clkdivr,Divider value MCANA selected clock.Data should be loaded as multibit"
line.long 0x58 "MSS_MCANB_CLK_DIV_VAL,"
hexmask.long.word 0x58 0.--11. 1. "clkdivr,Divider value MCANB selected clock.Data should be loaded as multibit"
line.long 0x5C "MSS_QSPI_CLK_DIV_VAL,"
hexmask.long.word 0x5C 0.--11. 1. "clkdivr,Divider value QSPI selected clock.Data should be loaded as multibit"
line.long 0x60 "MSS_RTIA_CLK_DIV_VAL,"
hexmask.long.word 0x60 0.--11. 1. "clkdivr,Divider value RTIA selected clock.Data should be loaded as multibit"
line.long 0x64 "MSS_RTIB_CLK_DIV_VAL,"
hexmask.long.word 0x64 0.--11. 1. "clkdivr,Divider value RTIB selected clock.Data should be loaded as multibit"
line.long 0x68 "MSS_RTIC_CLK_DIV_VAL,"
hexmask.long.word 0x68 0.--11. 1. "clkdivr,Divider value RTIC selected clock.Data should be loaded as multibit"
line.long 0x6C "MSS_WDT_CLK_DIV_VAL,"
hexmask.long.word 0x6C 0.--11. 1. "clkdivr,Divider value WDT selected clock.Data should be loaded as multibit"
line.long 0x70 "MSS_SPIA_CLK_DIV_VAL,"
hexmask.long.word 0x70 0.--11. 1. "clkdivr,Divider value SPIA selected clock.Data should be loaded as multibit"
line.long 0x74 "MSS_SPIB_CLK_DIV_VAL,"
hexmask.long.word 0x74 0.--11. 1. "clkdivr,Divider value SPIB selected clock.Data should be loaded as multibit"
line.long 0x78 "MSS_I2C_CLK_DIV_VAL,"
hexmask.long.word 0x78 0.--11. 1. "clkdivr,Divider value I2C selected clock.Data should be loaded as multibit"
line.long 0x7C "MSS_SCIA_CLK_DIV_VAL,"
hexmask.long.word 0x7C 0.--11. 1. "clkdivr,Divider value SCIA selected clock.Data should be loaded as multibit"
line.long 0x80 "MSS_SCIB_CLK_DIV_VAL,"
hexmask.long.word 0x80 0.--11. 1. "clkdivr,Divider value SCIB selected clock.Data should be loaded as multibit"
line.long 0x84 "MSS_CPTS_CLK_DIV_VAL,"
hexmask.long.word 0x84 0.--11. 1. "clkdivr,Divider value CPTS selected clock.Data should be loaded as multibit"
line.long 0x88 "MSS_CPSW_CLK_DIV_VAL,"
hexmask.long.word 0x88 0.--11. 1. "clkdivr,Divider value CPSW selected clock.Data should be loaded as multibit"
line.long 0x8C "MSS_RGMII_CLK_DIV_VAL,"
hexmask.long.word 0x8C 0.--11. 1. "clkdivr,Divider value RGMII selected clock.Data should be loaded as multibit"
line.long 0x90 "MSS_MII100_CLK_DIV_VAL,"
hexmask.long.word 0x90 0.--11. 1. "clkdivr,Divider value MII100 selected clock.Data should be loaded as multibit"
line.long 0x94 "MSS_MII10_CLK_DIV_VAL,"
hexmask.long.tbyte 0x94 0.--23. 1. "clkdivr,Divider value MII10 selected clock.Data should be loaded as multibit"
line.long 0x98 "MSS_GPADC_CLK_DIV_VAL,"
hexmask.long.tbyte 0x98 0.--23. 1. "clkdivr,Divider value GPADC selected clock.Data should be loaded as multibit"
line.long 0x9C "MSS_MCANA_CLK_GATE,"
bitfld.long 0x9C 0.--2. "gated,writing '111' will gate clock for MCANA" "0,1,2,3,4,5,6,7"
line.long 0xA0 "MSS_MCANB_CLK_GATE,"
bitfld.long 0xA0 0.--2. "gated,writing '111' will gate clock for MCANB" "0,1,2,3,4,5,6,7"
line.long 0xA4 "MSS_QSPI_CLK_GATE,"
bitfld.long 0xA4 0.--2. "gated,writing '111' will gate clock for QSPI" "0,1,2,3,4,5,6,7"
line.long 0xA8 "MSS_RTIA_CLK_GATE,"
bitfld.long 0xA8 0.--2. "gated,writing '111' will gate clock for RTIA" "0,1,2,3,4,5,6,7"
line.long 0xAC "MSS_RTIB_CLK_GATE,"
bitfld.long 0xAC 0.--2. "gated,writing '111' will gate clock for RTIB" "0,1,2,3,4,5,6,7"
line.long 0xB0 "MSS_RTIC_CLK_GATE,"
bitfld.long 0xB0 0.--2. "gated,writing '111' will gate clock for RTIC" "0,1,2,3,4,5,6,7"
line.long 0xB4 "MSS_WDT_CLK_GATE,"
bitfld.long 0xB4 0.--2. "gated,writing '111' will gate clock for WDT" "0,1,2,3,4,5,6,7"
line.long 0xB8 "MSS_SPIA_CLK_GATE,"
bitfld.long 0xB8 0.--2. "gated,writing '111' will gate clock for SPIA" "0,1,2,3,4,5,6,7"
line.long 0xBC "MSS_SPIB_CLK_GATE,"
bitfld.long 0xBC 0.--2. "gated,writing '111' will gate clock for SPIB" "0,1,2,3,4,5,6,7"
line.long 0xC0 "MSS_I2C_CLK_GATE,"
bitfld.long 0xC0 0.--2. "gated,writing '111' will gate clock for I2C" "0,1,2,3,4,5,6,7"
line.long 0xC4 "MSS_SCIA_CLK_GATE,"
bitfld.long 0xC4 0.--2. "gated,writing '111' will gate clock for SCIA" "0,1,2,3,4,5,6,7"
line.long 0xC8 "MSS_SCIB_CLK_GATE,"
bitfld.long 0xC8 0.--2. "gated,writing '111' will gate clock for SCIB" "0,1,2,3,4,5,6,7"
line.long 0xCC "MSS_CPTS_CLK_GATE,"
bitfld.long 0xCC 0.--2. "gated,writing '111' will gate clock for CPTS" "0,1,2,3,4,5,6,7"
line.long 0xD0 "MSS_CPSW_CLK_GATE,"
bitfld.long 0xD0 0.--2. "gated,writing '111' will gate clock for CPSW" "0,1,2,3,4,5,6,7"
line.long 0xD4 "MSS_RGMII_CLK_GATE,"
bitfld.long 0xD4 0.--2. "gated,writing '111' will gate clock for RGMII" "0,1,2,3,4,5,6,7"
line.long 0xD8 "MSS_MII100_CLK_GATE,"
bitfld.long 0xD8 0.--2. "gated,writing '111' will gate clock for MII100" "0,1,2,3,4,5,6,7"
line.long 0xDC "MSS_MII10_CLK_GATE,"
bitfld.long 0xDC 0.--2. "gated,writing '111' will gate clock for MII10" "0,1,2,3,4,5,6,7"
line.long 0xE0 "MSS_GPADC_CLK_GATE,"
bitfld.long 0xE0 0.--2. "gated,writing '111' will gate clock for MSS GPADC" "0,1,2,3,4,5,6,7"
line.long 0xE4 "MSS_MCANA_CLK_STATUS,"
hexmask.long.byte 0xE4 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCANA"
hexmask.long.byte 0xE4 0.--7. 1. "clkinuse,Status shows the source clock slected for MCANA"
line.long 0xE8 "MSS_MCANB_CLK_STATUS,"
hexmask.long.byte 0xE8 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCANB"
hexmask.long.byte 0xE8 0.--7. 1. "clkinuse,Status shows the source clock slected for MCANB"
line.long 0xEC "MSS_QSPI_CLK_STATUS,"
hexmask.long.byte 0xEC 8.--15. 1. "currdivider,Status shows the current divider value choosen for QSPI"
hexmask.long.byte 0xEC 0.--7. 1. "clkinuse,Status shows the source clock slected for QSPI"
line.long 0xF0 "MSS_RTIA_CLK_STATUS,"
hexmask.long.byte 0xF0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIA"
hexmask.long.byte 0xF0 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIA"
line.long 0xF4 "MSS_RTIB_CLK_STATUS,"
hexmask.long.byte 0xF4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIB"
hexmask.long.byte 0xF4 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIB"
line.long 0xF8 "MSS_RTIC_CLK_STATUS,"
hexmask.long.byte 0xF8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RTIC"
hexmask.long.byte 0xF8 0.--7. 1. "clkinuse,Status shows the source clock slected for RTIC"
line.long 0xFC "MSS_WDT_CLK_STATUS,"
hexmask.long.byte 0xFC 8.--15. 1. "currdivider,Status shows the current divider value choosen for WDT"
hexmask.long.byte 0xFC 0.--7. 1. "clkinuse,Status shows the source clock slected for WDT"
line.long 0x100 "MSS_SPIA_CLK_STATUS,"
hexmask.long.byte 0x100 8.--15. 1. "currdivider,Status shows the current divider value choosen for SPIA"
hexmask.long.byte 0x100 0.--7. 1. "clkinuse,Status shows the source clock slected for SPIA"
line.long 0x104 "MSS_SPIB_CLK_STATUS,"
hexmask.long.byte 0x104 8.--15. 1. "currdivider,Status shows the current divider value choosen for SPIB"
hexmask.long.byte 0x104 0.--7. 1. "clkinuse,Status shows the source clock slected for SPIB"
line.long 0x108 "MSS_I2C_CLK_STATUS,"
hexmask.long.byte 0x108 8.--15. 1. "currdivider,Status shows the current divider value choosen for I2C"
hexmask.long.byte 0x108 0.--7. 1. "clkinuse,Status shows the source clock slected for I2C"
line.long 0x10C "MSS_SCIA_CLK_STATUS,"
hexmask.long.byte 0x10C 8.--15. 1. "currdivider,Status shows the current divider value choosen for SCIA"
hexmask.long.byte 0x10C 0.--7. 1. "clkinuse,Status shows the source clock slected for SCIA"
line.long 0x110 "MSS_SCIB_CLK_STATUS,"
hexmask.long.byte 0x110 8.--15. 1. "currdivider,Status shows the current divider value choosen for SCIB"
hexmask.long.byte 0x110 0.--7. 1. "clkinuse,Status shows the source clock slected for SCIB"
line.long 0x114 "MSS_CPTS_CLK_STATUS,"
hexmask.long.byte 0x114 8.--15. 1. "currdivider,Status shows the current divider value choosen for CPTS"
hexmask.long.byte 0x114 0.--7. 1. "clkinuse,Status shows the source clock slected for CPTS"
line.long 0x118 "MSS_CPSW_CLK_STATUS,"
hexmask.long.byte 0x118 8.--15. 1. "currdivider,Status shows the current divider value choosen for CPSW"
hexmask.long.byte 0x118 0.--7. 1. "clkinuse,Status shows the source clock slected for CPSW"
line.long 0x11C "MSS_RGMII_CLK_STATUS,"
hexmask.long.byte 0x11C 8.--15. 1. "currdivider,Status shows the current divider value choosen for RGMII"
line.long 0x120 "MSS_MII100_CLK_STATUS,"
hexmask.long.byte 0x120 8.--15. 1. "currdivider,Status shows the current divider value choosen for MII100"
line.long 0x124 "MSS_MII10_CLK_STATUS,"
hexmask.long.byte 0x124 8.--15. 1. "currdivider,Status shows the current divider value choosen for MII10"
line.long 0x128 "MSS_GPADC_CLK_STATUS,"
hexmask.long.byte 0x128 8.--15. 1. "currdivider,Status shows the current divider value choosen for GPADC"
line.long 0x12C "MSS_CR5SS_POR_RST_CTRL,"
bitfld.long 0x12C 0.--2. "assert,write pulse bit field: writing '111' will assert por reset to R5SS" "0,1,2,3,4,5,6,7"
line.long 0x130 "MSS_CR5SSA_RST_CTRL,"
bitfld.long 0x130 0.--2. "assert,write pulse bit field: writing '111' will reset CR5A and MSS_CR5A_VIM" "0,1,2,3,4,5,6,7"
line.long 0x134 "MSS_CR5SSB_RST_CTRL,"
bitfld.long 0x134 0.--2. "assert,write pulse bit field: writing '111' will reset CR5B and MSS_CR5B_VIM" "0,1,2,3,4,5,6,7"
line.long 0x138 "MSS_CR5A_RST_CTRL,"
bitfld.long 0x138 0.--2. "assert,write pulse bit field: writing '111' will reset CR5A only" "0,1,2,3,4,5,6,7"
line.long 0x13C "MSS_CR5B_RST_CTRL,"
bitfld.long 0x13C 0.--2. "assert,write pulse bit field: writing '111' will reset CR5B only" "0,1,2,3,4,5,6,7"
line.long 0x140 "MSS_VIMA_RST_CTRL,"
bitfld.long 0x140 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x144 "MSS_VIMB_RST_CTRL,"
bitfld.long 0x144 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x148 "MSS_CRC_RST_CTRL,"
bitfld.long 0x148 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x14C "MSS_RTIA_RST_CTRL,"
bitfld.long 0x14C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x150 "MSS_RTIB_RST_CTRL,"
bitfld.long 0x150 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x154 "MSS_RTIC_RST_CTRL,"
bitfld.long 0x154 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x158 "MSS_WDT_RST_CTRL,"
bitfld.long 0x158 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x15C "MSS_ESM_RST_CTRL,"
bitfld.long 0x15C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x160 "MSS_DCCA_RST_CTRL,"
bitfld.long 0x160 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x164 "MSS_DCCB_RST_CTRL,"
bitfld.long 0x164 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x168 "MSS_DCCC_RST_CTRL,"
bitfld.long 0x168 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x16C "MSS_DCCD_RST_CTRL,"
bitfld.long 0x16C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x170 "MSS_GIO_RST_CTRL,"
bitfld.long 0x170 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x174 "MSS_SPIA_RST_CTRL,"
bitfld.long 0x174 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x178 "MSS_SPIB_RST_CTRL,"
bitfld.long 0x178 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x17C "MSS_QSPI_RST_CTRL,"
bitfld.long 0x17C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x180 "MSS_PWM1_RST_CTRL,"
bitfld.long 0x180 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x184 "MSS_PWM2_RST_CTRL,"
bitfld.long 0x184 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x188 "MSS_PWM3_RST_CTRL,"
bitfld.long 0x188 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x18C "MSS_MCANA_RST_CTRL,"
bitfld.long 0x18C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x190 "MSS_MCANB_RST_CTRL,"
bitfld.long 0x190 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x194 "MSS_I2C_RST_CTRL,"
bitfld.long 0x194 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x198 "MSS_SCIA_RST_CTRL,"
bitfld.long 0x198 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x19C "MSS_SCIB_RST_CTRL,"
bitfld.long 0x19C 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1A0 "MSS_EDMA_RST_CTRL,"
bitfld.long 0x1A0 24.--26. "tptcb0_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 16.--18. "tpccb_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 12.--14. "tptca1_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
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bitfld.long 0x1A0 8.--10. "tptca0_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 4.--6. "tpcca_assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
bitfld.long 0x1A0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1A4 "MSS_INFRA_RST_CTRL,"
bitfld.long 0x1A4 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1A8 "MSS_CPSW_RST_CTRL,"
bitfld.long 0x1A8 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1AC "MSS_GPADC_RST_CTRL,"
bitfld.long 0x1AC 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1B0 "MSS_DMM_RST_CTRL,"
bitfld.long 0x1B0 0.--2. "assert,This feature is for debug purpose only" "0,1,2,3,4,5,6,7"
line.long 0x1B4 "R5_COREA_GATE,"
bitfld.long 0x1B4 0.--2. "clkgate,writing '111' will gate clock to CR5A related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7"
line.long 0x1B8 "R5_COREB_GATE,"
bitfld.long 0x1B8 0.--2. "clkgate,writing '111' will gate clock to CR5B related peripherals inside Cortexr5ss" "0,1,2,3,4,5,6,7"
line.long 0x1BC "MSS_L2_BANKA_PD_CTRL,"
bitfld.long 0x1BC 8.--10. "agoodin,SW control for power signal 'AGOODIN' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
bitfld.long 0x1BC 4.--6. "aonin,SW control for power signal 'AONIN' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
bitfld.long 0x1BC 0.--2. "iso,SW control for power signal 'ISO' for MSS_L2_BANKA" "0,1,2,3,4,5,6,7"
line.long 0x1C0 "MSS_L2_BANKB_PD_CTRL,"
bitfld.long 0x1C0 8.--10. "agoodin,SW control for power signal 'AGOODIN' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C0 4.--6. "aonin,SW control for power signal 'AONIN' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
bitfld.long 0x1C0 0.--2. "iso,SW control for power signal 'ISO' for MSS_L2_BANKB" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "MSS_L2_BANKA_PD_STATUS,"
bitfld.long 0x1C4 1. "agoodout,SW status indicating the 'pgoodin' of MSS_L2_BANKA" "0,1"
bitfld.long 0x1C4 0. "aonout,SW status indicating the 'ponin' of MSS_L2_BANKA" "0,1"
line.long 0x1C8 "MSS_L2_BANKB_PD_STATUS,"
bitfld.long 0x1C8 1. "agoodout,SW status indicating the 'pgoodin' of MSS_L2_BANKB" "0,1"
bitfld.long 0x1C8 0. "aonout,SW status indicating the 'ponin' of MSS_L2_BANKB" "0,1"
group.long 0x1D4++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x400++0x4F
line.long 0x00 "HSM_RTIA_CLK_SRC_SEL,"
hexmask.long.word 0x00 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_RTIA.Data should be loaded as multibit"
line.long 0x04 "HSM_WDT_CLK_SRC_SEL,"
hexmask.long.word 0x04 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_WDT.Data should be loaded as multibit"
line.long 0x08 "HSM_RTC_CLK_SRC_SEL,"
hexmask.long.word 0x08 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_RTC.Data should be loaded as multibit"
line.long 0x0C "HSM_DMTA_CLK_SRC_SEL,"
hexmask.long.word 0x0C 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_DMTA.Data should be loaded as multibit"
line.long 0x10 "HSM_DMTB_CLK_SRC_SEL,"
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSM_DMTB.Data should be loaded as multibit"
line.long 0x14 "HSM_RTI_CLK_DIV_VAL,"
hexmask.long.word 0x14 0.--11. 1. "clkdivr,Divider value HSM RTI selected clock.Data should be loaded as multibit"
line.long 0x18 "HSM_WDT_CLK_DIV_VAL,"
hexmask.long.word 0x18 0.--11. 1. "clkdivr,Divider value HSM WDT selected clock.Data should be loaded as multibit"
line.long 0x1C "HSM_RTC_CLK_DIV_VAL,"
hexmask.long.word 0x1C 0.--11. 1. "clkdivr,Divider value HSM RTC selected clock.Data should be loaded as multibit"
line.long 0x20 "HSM_DMTA_CLK_DIV_VAL,"
hexmask.long.word 0x20 0.--11. 1. "clkdivr,Divider value HSM DMTA selected clock.Data should be loaded as multibit"
line.long 0x24 "HSM_DMTB_CLK_DIV_VAL,"
hexmask.long.word 0x24 0.--11. 1. "clkdivr,Divider value HSM DMTB selected clock.Data should be loaded as multibit"
line.long 0x28 "HSM_RTI_CLK_GATE,"
bitfld.long 0x28 0.--2. "gated,writing '111' will gate clock for HSM RTI" "0,1,2,3,4,5,6,7"
line.long 0x2C "HSM_WDT_CLK_GATE,"
bitfld.long 0x2C 0.--2. "gated,writing '111' will gate clock for HSM WDT" "0,1,2,3,4,5,6,7"
line.long 0x30 "HSM_RTC_CLK_GATE,"
bitfld.long 0x30 0.--2. "gated,writing '111' will gate clock for HSM RTC" "0,1,2,3,4,5,6,7"
line.long 0x34 "HSM_DMTA_CLK_GATE,"
bitfld.long 0x34 0.--2. "gated,writing '111' will gate clock for HSM DMTA" "0,1,2,3,4,5,6,7"
line.long 0x38 "HSM_DMTB_CLK_GATE,"
bitfld.long 0x38 0.--2. "gated,writing '111' will gate clock for HSM DMTB" "0,1,2,3,4,5,6,7"
line.long 0x3C "HSM_RTI_CLK_STATUS,"
hexmask.long.byte 0x3C 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_RTI"
hexmask.long.byte 0x3C 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_RTI"
line.long 0x40 "HSM_WDT_CLK_STATUS,"
hexmask.long.byte 0x40 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_WDT"
hexmask.long.byte 0x40 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_WDT"
line.long 0x44 "HSM_RTC_CLK_STATUS,"
hexmask.long.byte 0x44 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_RTC"
hexmask.long.byte 0x44 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_RTC"
line.long 0x48 "HSM_DMTA_CLK_STATUS,"
hexmask.long.byte 0x48 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_DMTA"
hexmask.long.byte 0x48 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_DMTA"
line.long 0x4C "HSM_DMTB_CLK_STATUS,"
hexmask.long.byte 0x4C 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSM_DMTB"
hexmask.long.byte 0x4C 0.--7. 1. "clkinuse,Status shows the source clock slected for HSM_DMTB"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x1CC)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_RTIA (MSS RTIA Module Registers)"
base ad:0x2F7A000
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "MSS_RTIB (MSS RTIB Module Registers)"
base ad:0x2F7A100
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "MSS_RTIC (MSS RTIC Module Registers)"
base ad:0x2F7A200
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "MSS_SCIA (MSS SCIA Module Registers)"
base ad:0x2F7EC00
group.long 0x00++0x5F
line.long 0x00 "SCIGCR0,The SCIGCR0 register defines the module reset"
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
newline
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
line.long 0x04 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
rbitfld.long 0x04 26.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
newline
bitfld.long 0x04 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
newline
rbitfld.long 0x04 18.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
newline
bitfld.long 0x04 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
newline
rbitfld.long 0x04 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
newline
bitfld.long 0x04 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function" "0,1"
newline
bitfld.long 0x04 7. "SW_nRESET,Software reset (active low)" "0,1"
newline
rbitfld.long 0x04 6. "RESERVED1,Reserved" "0,1"
newline
bitfld.long 0x04 5. "CLOCK,SCI internal clock enable" "0,1"
newline
bitfld.long 0x04 4. "STOP,SCI number of stop bits" "0,1"
newline
bitfld.long 0x04 3. "PARITY,SCI parity odd/even selection" "0,1"
newline
bitfld.long 0x04 2. "PARITY_ENA,SCI parity enable" "0,1"
newline
bitfld.long 0x04 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0,1"
newline
bitfld.long 0x04 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0,1"
line.long 0x08 "RESERVED1,Reserved"
line.long 0x0C "SCISETINT,SCI Set Interrupt Register"
rbitfld.long 0x0C 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request for address and data frames"
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bitfld.long 0x0C 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set" "leaves the corresponding bit unchanged,enable DMA request"
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bitfld.long 0x0C 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 8. "SET_TX_INT,Set Transmitter interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 0. "SET_BRKDT_INT,Set Break-detect interrupt" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x10 "SCICLEARINT,SCI Clear Interrupt Register"
rbitfld.long 0x10 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 25. "CLR_OE_INT,Clear Overrun-Error Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 24. "CLR_PE_INT,Clear Parity Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x10 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 18. "CLR_RX_DMA_ALL,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request for address frames"
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bitfld.long 0x10 17. "CLR_RX_DMA,Clear RX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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bitfld.long 0x10 16. "CLR_TX_DMA,Clear TX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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rbitfld.long 0x10 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 9. "CLR_RX_INT,Clear Receiver interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 8. "CLR_TX_INT,Clear Transmitter interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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rbitfld.long 0x10 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 0. "CLR_BRKDT_INT,Clear Break-detect interrupt" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x14 "SCISETINTLVL,SCI Set Interrupt Level Register"
rbitfld.long 0x14 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read)" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x14 15. "SET_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x14 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
line.long 0x18 "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
rbitfld.long 0x18 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x18 15. "CLR_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x18 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x18 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
line.long 0x1C "SCIFLR,SCI Flags Register"
rbitfld.long 0x1C 27.--31. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 26. "FE,SCI framing error flag Read" "No effect,Clears this bit to 0"
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rbitfld.long 0x1C 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
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rbitfld.long 0x1C 24. "PE,SCI parity error flag" "0,1"
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hexmask.long.word 0x1C 13.--23. 1. "RESERVED2,Reserved"
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rbitfld.long 0x1C 12. "RXWAKE,Receiver wake-up detect flag" "0,1"
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rbitfld.long 0x1C 11. "TX_EMPTY,Transmitter empty flag" "0,1"
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bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wake-up method select" "0,1"
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rbitfld.long 0x1C 9. "RXRDY,SCI receiver ready flag" "0,1"
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rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag" "0,1"
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rbitfld.long 0x1C 4.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame" "0,1"
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rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state" "0,1"
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rbitfld.long 0x1C 1. "WAKEUP,Wake-up flag" "0,1"
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rbitfld.long 0x1C 0. "BRKDT,SCI break-detect flag" "0,1"
line.long 0x20 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x20 0.--3. "INTVECT0,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x24 0.--3. "INTVECT1,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "SCICHAR,SCI Character Control Register"
hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x28 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
line.long 0x2C "SCIBAUD,SCI Baud Rate Selection Register"
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED,Reserved"
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hexmask.long.tbyte 0x2C 0.--23. 1. "BAUD,SCI 24-bit baud selection"
line.long 0x30 "SCIED,Receiver Emulation Data Buffer"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x30 0.--7. 1. "ED,Receiver Emulation Data Buffer"
line.long 0x34 "SCIRD,Receiver Data Buffer"
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x34 0.--7. 1. "RD,Contains received data"
line.long 0x38 "SCITD,Transmit Data Buffer Register"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x38 0.--7. 1. "TD,Contains Data to be transmitted"
line.long 0x3C "SCIPIO0,SCI Pin I/O Control Register 0"
hexmask.long 0x3C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x3C 2. "TX_FUNC,Defines the function of pin SCITX" "SCIRX is a general-purpose digital I/O pin,SCIRX is the SCI receive pin"
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bitfld.long 0x3C 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x3C 0. "CLK_FUNC,Clock function" "SCICLK is a general-purpose digital I/O pin,SCICLK is the SCI serial clock pin"
line.long 0x40 "SCIPIO1,SCI Pin I/O Control Register 1"
hexmask.long 0x40 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x40 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0)" "SCITX is a general-purpose input pin,SCITX is a general-purpose output pin"
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bitfld.long 0x40 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x40 0. "CLK_DIR,Clock data direction" "0,1"
line.long 0x44 "SCIPIO2,SCI Pin I/O Control Register 2"
hexmask.long 0x44 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x44 2. "TX_DATA_IN,Contains current value on the SCITX pin" "SCITX value is logic low,SCITX value is logic high"
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bitfld.long 0x44 1. "RX_DATA_IN,Contains current value on the SCIRX pin" "SCIRX value is logic low,SCIRX value is logic high"
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bitfld.long 0x44 0. "CLK_DATA_IN,Contains the current value on pin SCICLK" "Pin SCICLK value is logic low,Pin SCICLK value is logic high"
line.long 0x48 "SCIPIO3,SCI Pin I/O Control Register 3"
hexmask.long 0x48 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x48 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "Output value on SCITX is a 0 (logic low),Output value on SCITX is a 1 (logic high)"
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bitfld.long 0x48 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "Output value on SCIRX is 0 (logic low),Output value on SCIRX is 1 (logic high)"
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bitfld.long 0x48 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "Output value on SCICLK is a 0 (logic low),Output value on SCICLK is a 1 (logic high)"
line.long 0x4C "SCIPIO4,SCI Pin I/O Control Register 4"
hexmask.long 0x4C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4C 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
line.long 0x50 "SCIPIO5,SCI Pin I/O Control Register 5"
hexmask.long 0x50 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x50 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
line.long 0x54 "SCIPIO6,SCI Pin I/O Control Register 6"
hexmask.long 0x54 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x54 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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bitfld.long 0x54 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x54 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
line.long 0x58 "SCIPIO7,SCI Pin I/O Control Register 7"
hexmask.long 0x58 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x58 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX" "Pull Control on SCITX pin is enabled,Pull Control on SCITX pin is disabled"
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bitfld.long 0x58 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX" "Pull Control on SCIRX pin is enabled,Pull Control on SCIRX pin is disabled"
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bitfld.long 0x58 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK" "Pull Control on SCICLK pin is enabled,Pull Control on SCICLK pin is disabled"
line.long 0x5C "SCIPIO8,SCI Pin I/O Control Register 8"
hexmask.long 0x5C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x5C 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX" "Pull-Down is on SCITX pin,Pull-Up is on SCITX pin"
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bitfld.long 0x5C 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX" "Pull-Down is on SCIRX pin,Pull-Up is on SCIRX pin"
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bitfld.long 0x5C 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK" "Pull-Down is on SCICLK pin,Pull-Up is on SCICLK pin"
group.long 0x80++0x03
line.long 0x00 "SCIPIO9,SCI Pin I/O Control Register 9"
hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 2. "TX_SL,This bit controls the slew rate for the SCITX pin" "The normal output buffer is used for SCITX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 1. "RX_SL,This bit controls the slew rate for the SCIRX pin" "The normal output buffer is used for SCIRX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin" "The normal output buffer is used for SCICLK pin,The output buffer with slew control is used for.."
group.long 0x90++0x03
line.long 0x00 "SCIIODCTRL,SCI IO DFT Control"
rbitfld.long 0x00 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 26. "FEN,Frame Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 25. "PEN,Parity Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 24. "BRKDT_ENA,Break Detect Error Enable" "No effect,This bit is used to.."
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rbitfld.long 0x00 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry" "0,1,2,3"
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bitfld.long 0x00 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 12.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "LBP_ENA,Module loopback enable" "Digital loopback is enabled,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x00 0. "RXP_ENA,Module Analog loopback through receive pin enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
repeat 8. (list 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_SCIB (MSS SCIB Module Registers)"
base ad:0x2F7ED00
group.long 0x00++0x5F
line.long 0x00 "SCIGCR0,The SCIGCR0 register defines the module reset"
hexmask.long 0x00 1.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
line.long 0x04 "SCIGCR1,The SCIGCR1 register defines the frame format. protocol. and communication mode used by the SCI"
rbitfld.long 0x04 26.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 25. "TXENA,Data is transferred from SCITD to SCITXSHF only when the TXENA bit is set" "0,1"
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bitfld.long 0x04 24. "RXENA,Allows the receiver to transfer data from the shift buffer to the receive buffer" "0,1"
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rbitfld.long 0x04 18.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 17. "CONT,This bit has an effect only when a program is being debugged with an emulator and it determines how the SCI operates when the program is suspended" "0,1"
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bitfld.long 0x04 16. "LOOP_BACK,Enable bit for loopback mode" "0,1"
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rbitfld.long 0x04 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 9. "POWERDOWN,When the POWERDOWN bit is set the SCI attempts to enter local low-power mode" "0,1"
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bitfld.long 0x04 8. "SLEEP,In a multiprocessor configuration this bit controls the receive sleep function" "0,1"
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bitfld.long 0x04 7. "SW_nRESET,Software reset (active low)" "0,1"
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rbitfld.long 0x04 6. "RESERVED1,Reserved" "0,1"
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bitfld.long 0x04 5. "CLOCK,SCI internal clock enable" "0,1"
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bitfld.long 0x04 4. "STOP,SCI number of stop bits" "0,1"
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bitfld.long 0x04 3. "PARITY,SCI parity odd/even selection" "0,1"
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bitfld.long 0x04 2. "PARITY_ENA,SCI parity enable" "0,1"
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bitfld.long 0x04 1. "TIMING_MODE,SCI timing mode bit (0=Isosynchronous timing 1=Asynchronous timing)" "0,1"
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bitfld.long 0x04 0. "COMM_MODE,SCI communication mode bit (0=Idle-line mode 1=Address-bit mode)" "0,1"
line.long 0x08 "RESERVED1,Reserved"
line.long 0x0C "SCISETINT,SCI Set Interrupt Register"
rbitfld.long 0x0C 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 26. "SET_FE_INT,Set Framing-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 25. "SET_OE_INT,Set Overrun-Error Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 24. "SET_PE_INT,Set Parity Interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 18. "SET_RX_DMA_ALL,Determines if a separate interrupt is generated for the address frames sent in multiprocessor communications User and privilege mode (read)" "leaves the corresponding bit unchanged,enable DMA request for address and data frames"
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bitfld.long 0x0C 17. "SET_RX_DMA,To select receiver DMA requests this bit must be set" "leaves the corresponding bit unchanged,enable DMA request"
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bitfld.long 0x0C 16. "SET_TX_DMA,To select DMA requests for the transmitter this bit must be set" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 9. "SET_RX_INT,Receiver interrupt enable:Setting this bit enables the SCI to generate a receive interrupt after a frame has been completely received and the data is being transferred from SCIRXSHF to SCIRD" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 8. "SET_TX_INT,Set Transmitter interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x0C 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 1. "SET_WAKEUP_INT,Set Wake-up interrupt User and privilege mode (read)" "leaves the corresponding bit unchanged,enable interrupt"
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bitfld.long 0x0C 0. "SET_BRKDT_INT,Set Break-detect interrupt" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x10 "SCICLEARINT,SCI Clear Interrupt Register"
rbitfld.long 0x10 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 26. "CLR_FE_INT,Clear Framing-Error Interrupt: Setting this bit disables the SCI module to generate an interrupt when there is a Framing error" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 25. "CLR_OE_INT,Clear Overrun-Error Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 24. "CLR_PE_INT,Clear Parity Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
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rbitfld.long 0x10 19.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 18. "CLR_RX_DMA_ALL,User and privilege mode (read)" "leaves the corresponding bit unchanged,disable DMA request for address frames"
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bitfld.long 0x10 17. "CLR_RX_DMA,Clear RX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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bitfld.long 0x10 16. "CLR_TX_DMA,Clear TX DMA request" "leaves the corresponding bit unchanged,disable DMA request"
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rbitfld.long 0x10 10.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 9. "CLR_RX_INT,Clear Receiver interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 8. "CLR_TX_INT,Clear Transmitter interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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rbitfld.long 0x10 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x10 1. "CLR_WAKEUP_INT,Clear Wake-up interrupt" "leaves the corresponding bit unchanged,disable interrupt"
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bitfld.long 0x10 0. "CLR_BRKDT_INT,Clear Break-detect interrupt" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x14 "SCISETINTLVL,SCI Set Interrupt Level Register"
rbitfld.long 0x14 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 26. "SET_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 25. "SET_OE_INT_LVL,Clear Overrun-Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 24. "SET_PE_INT_LVL,Clear Parity Error Interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 18. "SET_RX_DMA_ALL_INT_LVL,User and privilege mode (read)" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x14 15. "SET_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x14 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 9. "SET_RX_INT_LVL,Clear Receiver interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 8. "SET_TX_INT_LVL,Clear Transmitter interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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rbitfld.long 0x14 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x14 1. "SET_WAKEUP_INT_LVL,Clear Wake-up interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
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bitfld.long 0x14 0. "SET_BRKDT_INT_LVL,Clear Break-detect interrupt Level" "Leaves the corresponding bit unchanged,Clear interrupt level to line INT1"
line.long 0x18 "SCICLEARINTLVL,SCI Clear Interrupt Level Register"
rbitfld.long 0x18 27.--31. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "CLR_FE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 25. "CLR_OE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 24. "CLR_PE_INT_LVL,Clear Framing-Error Interrupt Level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 19.--23. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 18. "CLR_RX_DMA_ALL_INT_LVL,Clear receive DMA ALL interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 16.--17. "RESERVED3,Reserved" "0,1,2,3"
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bitfld.long 0x18 15. "CLR_INC_BR_INT_LVL," "0,1"
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rbitfld.long 0x18 10.--14. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 9. "CLR_RX_INT_LVL,Clear Receiver interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 8. "CLR_TX_INT_LVL,Clear Transmitter interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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rbitfld.long 0x18 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x18 1. "CLR_WAKEUP_INT_LVL,Clear Wake-up interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
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bitfld.long 0x18 0. "CLR_BRKDT_INT_LVL,Clear Break-detect interrupt level" "Leaves the corresponding bit unchanged,Reset interrupt level to line INT0"
line.long 0x1C "SCIFLR,SCI Flags Register"
rbitfld.long 0x1C 27.--31. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x1C 26. "FE,SCI framing error flag Read" "No effect,Clears this bit to 0"
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rbitfld.long 0x1C 25. "OE,SCI overrun error flag This bit is set when the transfer of data from SCIRXSHF to SCIRD overwrites unread data already in SCIRD" "0,1"
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rbitfld.long 0x1C 24. "PE,SCI parity error flag" "0,1"
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hexmask.long.word 0x1C 13.--23. 1. "RESERVED2,Reserved"
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rbitfld.long 0x1C 12. "RXWAKE,Receiver wake-up detect flag" "0,1"
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rbitfld.long 0x1C 11. "TX_EMPTY,Transmitter empty flag" "0,1"
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bitfld.long 0x1C 10. "TXWAKE,SCI transmitter wake-up method select" "0,1"
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rbitfld.long 0x1C 9. "RXRDY,SCI receiver ready flag" "0,1"
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rbitfld.long 0x1C 8. "TXRDY,Transmitter buffer register ready flag" "0,1"
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rbitfld.long 0x1C 4.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x1C 3. "Bus_busy_flag,This bit indicates whether the receiver is in the process of receiving a frame" "0,1"
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rbitfld.long 0x1C 2. "IDLE,SCI receiver in idle state" "0,1"
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rbitfld.long 0x1C 1. "WAKEUP,Wake-up flag" "0,1"
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rbitfld.long 0x1C 0. "BRKDT,SCI break-detect flag" "0,1"
line.long 0x20 "SCIINTVECT0,SCI Interrupt Offset Vector 0 Register"
hexmask.long 0x20 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x20 0.--3. "INTVECT0,Interrupt vector offset for INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "SCIINTVECT1,SCI Interrupt Offset Vector 1 Register"
hexmask.long 0x24 4.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x24 0.--3. "INTVECT1,Interrupt vector offset for INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "SCICHAR,SCI Character Control Register"
hexmask.long 0x28 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x28 0.--2. "CHAR,Sets the SCI data length from 1 to 8 bits" "0,1,2,3,4,5,6,7"
line.long 0x2C "SCIBAUD,SCI Baud Rate Selection Register"
hexmask.long.byte 0x2C 24.--31. 1. "RESERVED,Reserved"
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hexmask.long.tbyte 0x2C 0.--23. 1. "BAUD,SCI 24-bit baud selection"
line.long 0x30 "SCIED,Receiver Emulation Data Buffer"
hexmask.long.tbyte 0x30 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x30 0.--7. 1. "ED,Receiver Emulation Data Buffer"
line.long 0x34 "SCIRD,Receiver Data Buffer"
hexmask.long.tbyte 0x34 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x34 0.--7. 1. "RD,Contains received data"
line.long 0x38 "SCITD,Transmit Data Buffer Register"
hexmask.long.tbyte 0x38 8.--31. 1. "RESERVED,Reserved"
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hexmask.long.byte 0x38 0.--7. 1. "TD,Contains Data to be transmitted"
line.long 0x3C "SCIPIO0,SCI Pin I/O Control Register 0"
hexmask.long 0x3C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x3C 2. "TX_FUNC,Defines the function of pin SCITX" "SCIRX is a general-purpose digital I/O pin,SCIRX is the SCI receive pin"
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bitfld.long 0x3C 1. "RX_FUNC,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x3C 0. "CLK_FUNC,Clock function" "SCICLK is a general-purpose digital I/O pin,SCICLK is the SCI serial clock pin"
line.long 0x40 "SCIPIO1,SCI Pin I/O Control Register 1"
hexmask.long 0x40 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x40 2. "TX_DIR,Determines the data direction on the SCITX pin if it is configured with general-purpose I/O functionality (TX FUNC = 0)" "SCITX is a general-purpose input pin,SCITX is a general-purpose output pin"
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bitfld.long 0x40 1. "RX_DIR,Determines the data direction on the SCIRX pin if it is configured with general-purpose I/O functionality (RX FUNC = 0)" "SCIRX is a general-purpose input pin,SCIRX is a general-purpose output pin"
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bitfld.long 0x40 0. "CLK_DIR,Clock data direction" "0,1"
line.long 0x44 "SCIPIO2,SCI Pin I/O Control Register 2"
hexmask.long 0x44 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x44 2. "TX_DATA_IN,Contains current value on the SCITX pin" "SCITX value is logic low,SCITX value is logic high"
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bitfld.long 0x44 1. "RX_DATA_IN,Contains current value on the SCIRX pin" "SCIRX value is logic low,SCIRX value is logic high"
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bitfld.long 0x44 0. "CLK_DATA_IN,Contains the current value on pin SCICLK" "Pin SCICLK value is logic low,Pin SCICLK value is logic high"
line.long 0x48 "SCIPIO3,SCI Pin I/O Control Register 3"
hexmask.long 0x48 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x48 2. "TX_DATA_OUT,Contains the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "Output value on SCITX is a 0 (logic low),Output value on SCITX is a 1 (logic high)"
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bitfld.long 0x48 1. "RX_DATA_OUT,Contains the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "Output value on SCIRX is 0 (logic low),Output value on SCIRX is 1 (logic high)"
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bitfld.long 0x48 0. "CLK_DATA_OUT,Contains the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "Output value on SCICLK is a 0 (logic low),Output value on SCICLK is a 1 (logic high)"
line.long 0x4C "SCIPIO4,SCI Pin I/O Control Register 4"
hexmask.long 0x4C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x4C 2. "TX_DATA_SET,Sets the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 1. "RX_DATA_SET,Sets the data to be output on pin SCIRX if the following conditions are met: RX FUNC = 0 (SCIRX pin is a general-purpose I/O.) RX DATA DIR = 1 (SCIRX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x4C 0. "CLK_DATA_SET,Sets the data to be output on pin SCICLK if the following conditions are met: CLK FUNC = 0 (SCICLK pin is a general-purpose I/O.) CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.)" "0,1"
line.long 0x50 "SCIPIO5,SCI Pin I/O Control Register 5"
hexmask.long 0x50 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x50 2. "TX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 1. "RX_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
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bitfld.long 0x50 0. "CLK_DATA_CLR,Clears the data to be output on pin SCITX if the following conditions are met: TX FUNC = 0 (SCITX pin is a general-purpose I/O.) TX DATA DIR = 1 (SCITX pin is a general-purpose output.)" "0,1"
line.long 0x54 "SCIPIO6,SCI Pin I/O Control Register 6"
hexmask.long 0x54 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x54 2. "TX_PDR,TX Open Drain Enable Enables open-drain capability in the output pin SCITX if the following conditions are met: TX DATA DIR = 1 (SCITX pin is a general-purpose output.) TX DOUT = 1" "0,1"
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bitfld.long 0x54 1. "RX_PDR,RX Open Drain Enable Enables open-drain capability in the output pin SCIRX if the following conditions are met: RX DATA DIR = 1 (SCIRX pin is a general-purpose output.) RX DOUT = 1" "0,1"
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bitfld.long 0x54 0. "CLK_PDR,CLK Open Drain Enable Enables open-drain capability in the output pin SCICLK if the following conditions are met: CLK DATA DIR = 1 (SCICLK pin is a general-purpose output.) CLK DOUT = 1" "0,1"
line.long 0x58 "SCIPIO7,SCI Pin I/O Control Register 7"
hexmask.long 0x58 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x58 2. "TX_PD,TX pin Pull Control Disable Disables pull control capability in the output pin SCITX" "Pull Control on SCITX pin is enabled,Pull Control on SCITX pin is disabled"
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bitfld.long 0x58 1. "RX_PD,RX pin Pull Control Disable Disables pull control capability in the output pin SCIRX" "Pull Control on SCIRX pin is enabled,Pull Control on SCIRX pin is disabled"
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bitfld.long 0x58 0. "CLK_PD,CLK pin Pull Control Disable Disables pull control capability in the output pin SCICLK" "Pull Control on SCICLK pin is enabled,Pull Control on SCICLK pin is disabled"
line.long 0x5C "SCIPIO8,SCI Pin I/O Control Register 8"
hexmask.long 0x5C 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x5C 2. "TX_PSL ,TX pin Pull Select Selects pull type in the output pin SCITX" "Pull-Down is on SCITX pin,Pull-Up is on SCITX pin"
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bitfld.long 0x5C 1. "RX_PSL,RX pin Pull Select Selects pull type in the output pin SCIRX" "Pull-Down is on SCIRX pin,Pull-Up is on SCIRX pin"
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bitfld.long 0x5C 0. "CLK_PSL,CLK pin Pull Select Selects pull type in the output pin SCICLK" "Pull-Down is on SCICLK pin,Pull-Up is on SCICLK pin"
group.long 0x80++0x03
line.long 0x00 "SCIPIO9,SCI Pin I/O Control Register 9"
hexmask.long 0x00 3.--31. 1. "RESERVED,Reserved"
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bitfld.long 0x00 2. "TX_SL,This bit controls the slew rate for the SCITX pin" "The normal output buffer is used for SCITX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 1. "RX_SL,This bit controls the slew rate for the SCIRX pin" "The normal output buffer is used for SCIRX pin,The output buffer with slew control is used for.."
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bitfld.long 0x00 0. "CLK_SL,This bit controls the slew rate for the SCICLK pin" "The normal output buffer is used for SCICLK pin,The output buffer with slew control is used for.."
group.long 0x90++0x03
line.long 0x00 "SCIIODCTRL,SCI IO DFT Control"
rbitfld.long 0x00 27.--31. "RESERVED4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 26. "FEN,Frame Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 25. "PEN,Parity Error Enable" "No effect,This bit is used to.."
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bitfld.long 0x00 24. "BRKDT_ENA,Break Detect Error Enable" "No effect,This bit is used to.."
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rbitfld.long 0x00 21.--23. "RESERVED3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 19.--20. "PIN_SAMPLE_MASK,PIN SAMPLE MASK These bits define the sample number at which the TX Pin value that is being transmitted will be inverted to verify the receive pin samples majority detection circuitry" "0,1,2,3"
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bitfld.long 0x00 16.--18. "TX_SHIFT,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 12.--15. "RESERVED2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "IODFTENA,These bits define the delay by which the value on TX pin is delayed so that the value on RX Pin is asynchronous" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x00 2.--7. "RESERVED1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 1. "LBP_ENA,Module loopback enable" "Digital loopback is enabled,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x00 0. "RXP_ENA,Module Analog loopback through receive pin enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
repeat 8. (list 2. 3. 4. 5. 6. 7. 8. 9. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C )
rgroup.long ($2+0x60)++0x03
line.long 0x00 "RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "MSS_SPIA (MSS SPIA Module Registers)"
base ad:0x2F7E800
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
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rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
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bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
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bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
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bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
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rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
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abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
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rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
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abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
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abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
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abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
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bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
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abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
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rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
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bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
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bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
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rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
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rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
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bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
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bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
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hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
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bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
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rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "MSS_SPIB (MSS SPIB Module Registers)"
base ad:0x2F7EA00
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
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rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
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bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
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bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
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bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
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rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
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abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
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rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
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abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
newline
rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
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bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
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abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
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rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
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bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
newline
bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
newline
rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
newline
rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
newline
bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
newline
bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
newline
bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
newline
hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
newline
bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
newline
rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "MSS_TOPRCM (MSS TOPRCM Module Registers)"
base ad:0x2140000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x17
line.long 0x00 "HSI_CLK_SRC_SEL,"
hexmask.long.word 0x00 0.--11. 1. "clksrcsel,Select line for selecting source clock for HSI"
line.long 0x04 "CSIRX_CLK_SRC_SEL,"
hexmask.long.word 0x04 0.--11. 1. "clksrcsel,Select line for selecting source clock for CSI Rx Data should be loaded as multibit"
line.long 0x08 "MCUCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x08 0.--11. 1. "clksrcsel,Select line for selecting source clock for MCU Clkout Data should be loaded as multibit"
line.long 0x0C "PMICCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x0C 0.--11. 1. "clksrcsel,Select line for selecting source clock for PMIC Clkout Data should be loaded as multibit"
line.long 0x10 "OBSCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for OBS Clkout Data should be loaded as multibit"
line.long 0x14 "TRCCLKOUT_CLK_SRC_SEL,"
hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for TRC Clkout Data should be loaded as multibit"
group.long 0x40++0x17
line.long 0x00 "HSI_DIV_VAL,"
hexmask.long.word 0x00 0.--11. 1. "clkdiv,Divider value for HSI selected clock"
line.long 0x04 "CSIRX_DIV_VAL,"
hexmask.long.word 0x04 0.--11. 1. "clkdiv,Divider value for CSI Rx selected clock"
line.long 0x08 "MCUCLKOUT_DIV_VAL,"
hexmask.long.word 0x08 0.--11. 1. "clkdiv,Divider value for MCU Clkout selected clock"
line.long 0x0C "PMICCLKOUT_DIV_VAL,"
hexmask.long.word 0x0C 0.--11. 1. "clkdiv,Divider value for PMIC Clkout selected clock"
line.long 0x10 "OBSCLKOUT_DIV_VAL,"
hexmask.long.word 0x10 0.--11. 1. "clkdiv,Divider value for OBS Clkout selected clock"
line.long 0x14 "TRCCLKOUT_DIV_VAL,"
hexmask.long.word 0x14 0.--11. 1. "clkdiv,Divider value for TRC Clkout selected clock"
group.long 0x80++0x1B
line.long 0x00 "HSI_CLK_GATE,"
bitfld.long 0x00 0.--2. "gated,Clock gatring config for HSI" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x04 "CSIRX_CLK_GATE,"
bitfld.long 0x04 0.--2. "gated,Clock gatring config for CSI Rx" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x08 "MCUCLKOUT_CLK_GATE,"
bitfld.long 0x08 0.--2. "gated,Clock gatring config for MCU Clkout" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x0C "PMICCLKOUT_CLK_GATE,"
bitfld.long 0x0C 0.--2. "gated,Clock gatring config for PMIC Clkout Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x10 "OBSCLKOUT_CLK_GATE,"
bitfld.long 0x10 0.--2. "gated,Clock gatring config for OBS Clkout Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x14 "TRCCLKOUT_CLK_GATE,"
bitfld.long 0x14 0.--2. "gated,Clock gatring config for TRC Clkout Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x18 "DSS_CLK_GATE,"
bitfld.long 0x18 0.--2. "gated,Clock gatring config for DSP Subsystem System Clock Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
rgroup.long 0xC0++0x17
line.long 0x00 "HSI_CLK_STATUS,"
hexmask.long.byte 0x00 8.--15. 1. "currdivider,Status shows the current divider value choosen for CortexR5 Clock"
newline
hexmask.long.byte 0x00 0.--7. 1. "clkinuse,Status shows the source clock slected for CortexR5 Clock"
line.long 0x04 "CSIRX_CLK_STATUS,"
hexmask.long.byte 0x04 8.--15. 1. "currdivider,Status shows the current divider value choosen for HSI Clock"
newline
hexmask.long.byte 0x04 0.--7. 1. "clkinuse,Status shows the source clock slected for HSI Clock"
line.long 0x08 "MCUCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x08 8.--15. 1. "currdivider,Status shows the current divider value choosen for CSI Rx Clock"
newline
hexmask.long.byte 0x08 0.--7. 1. "clkinuse,Status shows the source clock slected for CSI Rx Clock"
line.long 0x0C "PMICCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x0C 8.--15. 1. "currdivider,Status shows the current divider value choosen for MCU Clkout Clock"
newline
hexmask.long.byte 0x0C 0.--7. 1. "clkinuse,Status shows the source clock slected for MCU Clkout Clock"
line.long 0x10 "OBSCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x10 8.--15. 1. "currdivider,Status shows the current divider value choosen for PMIC Clkout Clock"
newline
hexmask.long.byte 0x10 0.--7. 1. "clkinuse,Status shows the source clock slected for PMIC Clkout Clock"
line.long 0x14 "TRCCLKOUT_CLK_STATUS,"
hexmask.long.byte 0x14 8.--15. 1. "currdivider,Status shows the current divider value choosen for PMIC Clkout Clock"
newline
hexmask.long.byte 0x14 0.--7. 1. "clkinuse,Status shows the source clock slected for PMIC Clkout Clock"
group.long 0x100++0x0F
line.long 0x00 "WARM_RESET_CONFIG,"
bitfld.long 0x00 16.--18. "wdog_rst_en,Data should be loaded as multibit" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 8.--10. "sw_rst,Data should be loaded as multibit" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 0.--2. "pad_bypass,Bypass the Warm reset from Pad Input Data should be loaded as multibit" "Reset is not asserted by SW (multibit 000),?,?,?,?,?,?,Reset is asserted by SW (multibit 111)"
line.long 0x04 "SYS_RST_CAUSE,"
bitfld.long 0x04 0.--4. "cause,System Reset Cause register" "?,?,?,?,?,?,?,?,External Pad reset,POR reset,Warm reset due to MSS_WDT,?,Warm reset due to TOP_RMC,?,?,?,?,?,?,?,?,?,?,?,Warm reset due to HSM_WDT,?..."
line.long 0x08 "SYS_RST_CAUSE_CLR,"
bitfld.long 0x08 0. "clear,Write pulse bit field: System Reset Cause register Clear" "0,1"
line.long 0x0C "DSS_RST_CTRL,"
bitfld.long 0x0C 0.--2. "assert,Reset control for DSP Subsystem Data should be loaded as multibit" "Reset is not asserted by SW (multibit 000),?,?,?,?,?,?,Reset is asserted by SW (multibit 111)"
group.long 0x204++0x23
line.long 0x00 "RS232_BITINTERVAL,"
line.long 0x04 "LVDS_PAD_CTRL0,"
line.long 0x08 "LVDS_PAD_CTRL1,"
line.long 0x0C "DFT_DMLED_EXEC,"
line.long 0x10 "DFT_DMLED_STATUS,"
line.long 0x14 "LIMP_MODE_EN,"
bitfld.long 0x14 8.--10. "force_rcclk_en,Force the RCCLK on when limp mode is detected" "The RCCLK will not be forced on when limp mode..,?,?,?,?,?,?,The RCCLK will be forced on when limp mode is.."
newline
bitfld.long 0x14 4.--6. "ccca_en,Enable MSS_CCCA Error to generate Limp mode" "MSS_CCCA Error will not generate Limp mode..,?,?,?,?,?,?,MSS_CCCA Error will generate Limp mode (multibit.."
newline
bitfld.long 0x14 0.--2. "dcca_en,Enable MSS_DCCA Error to generate Limp mode" "MSS_DCCA Error will not generate Limp mode..,?,?,?,?,?,?,MSS_DCCA Error will generate Limp mode (multibit.."
line.long 0x18 "PMICCLKOUT_DCDC_CTRL,"
hexmask.long.byte 0x18 16.--23. 1. "max_freq_thr,PMIC Clockout DCDC Maximum Frequency Threshold"
newline
hexmask.long.byte 0x18 8.--15. 1. "min_freq_thr,PMIC Clockout DCDC Minimum Frequency Threshold"
newline
bitfld.long 0x18 4.--6. "reset_assert,Reset control for PMIC DCDC Data should be loaded as multibit" "Reset is not asserted by SW (multibit 000),?,?,?,?,?,?,Reset is asserted by SW (multibit 111)"
newline
bitfld.long 0x18 2. "freq_acc_mode,PMIC Clockout DCDC Freq Acc Enable" "0,1"
newline
bitfld.long 0x18 1. "dither_en,PMIC Clockout DCDC Clock Dither Enable" "0,1"
newline
bitfld.long 0x18 0. "dcdc_clk_en,PMIC Clockout DCDC Clock Enable" "0,1"
line.long 0x1C "PMICCLKOUT_DCDC_SLOPE,"
hexmask.long 0x1C 0.--26. 1. "slope_val,PMIC Clockout DCDC Slope Config Value"
line.long 0x20 "RCOSC32K_CTRL,"
bitfld.long 0x20 0.--2. "stoposc,Stop 32KHz RCOSC" "0,1,2,3,4,5,6,7"
group.long 0x400++0x5F
line.long 0x00 "PLL_CORE_PWRCTRL,"
bitfld.long 0x00 5. "PONIN,ON/OFF control of the weak power switch digital" "0,1"
newline
bitfld.long 0x00 4. "PGOODIN,ON/OFF control of the strong power switch digital" "0,1"
newline
bitfld.long 0x00 3. "RET,Save/Restore control for Retention mode" "0,1"
newline
bitfld.long 0x00 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
newline
bitfld.long 0x00 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins" "0,1"
newline
bitfld.long 0x00 0. "OFFMODE,Used to switch OFF the logic on VDDA" "0,1"
line.long 0x04 "PLL_CORE_CLKCTRL,"
bitfld.long 0x04 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK" "0,1"
newline
bitfld.long 0x04 30. "ENSSC,Controls Clock Spreading" "0,1"
newline
bitfld.long 0x04 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO" "synchronously disables CLKDCOLDO,synchronously enables CLKDCOLDO"
newline
bitfld.long 0x04 24.--28. "NWELLTRIM,Trim value for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 23. "IDLE,Sets PLL to Idle mode" "When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL.."
newline
bitfld.long 0x04 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module" "0,1"
newline
bitfld.long 0x04 21. "STBYRET,Standby retention control" "prepares ADPLLLJ for relock when out of..,prepares ADPLLLJ for retention by gating all the.."
newline
bitfld.long 0x04 20. "CLKOUTEN,CLKOUT enable or disable" "synchronously disables CLKOUT,synchronously enables CLKOUT"
newline
bitfld.long 0x04 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO" "synchronously disables CLKOUTLDO,synchronously enables CLKOUTLDO"
newline
bitfld.long 0x04 18. "ULOWCLKEN,Select CLKOUT source in bypass" "When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1),When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW"
newline
bitfld.long 0x04 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p" "0,1"
newline
bitfld.long 0x04 16. "M2PWDNZ,M2 divider power down mode" "Asynchronous power down for M2 divider,M2 divider is functional"
newline
bitfld.long 0x04 14. "STOPMODE,When in Lossclk/Stbyret" "Limp mode,Stopmode"
newline
bitfld.long 0x04 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector" "Reserved,?,HS2,Reserved,HS1,Reserved,?..."
newline
bitfld.long 0x04 8. "RELAXED_LOCK,Decides when FREQLOCK asserted" "FREQLOCK asserted when DC frequency error less..,FREQLOCK asserted when DC frequency error less.."
newline
bitfld.long 0x04 1. "SSCTYPE,SSC Type" "0,1"
newline
bitfld.long 0x04 0. "TINTZ,PLL core soft reset" "0,1"
line.long 0x08 "PLL_CORE_TENABLE,"
bitfld.long 0x08 0. "TENABLE,M N" "0,1"
line.long 0x0C "PLL_CORE_TENABLEDIV,"
bitfld.long 0x0C 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
line.long 0x10 "PLL_CORE_M2NDIV,"
hexmask.long.byte 0x10 16.--22. 1. "M2,Post-divider is REGM2"
newline
hexmask.long.byte 0x10 0.--7. 1. "N,Pre-divider is REGN+1"
line.long 0x14 "PLL_CORE_MN2DIV,"
bitfld.long 0x14 16.--19. "N2,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 0.--11. 1. "M,Feedback Multiplier is REGM"
line.long 0x18 "PLL_CORE_FRACDIV,"
hexmask.long.byte 0x18 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance"
newline
hexmask.long.tbyte 0x18 0.--17. 1. "FRACTIONALM,Fractional part of the M divider"
line.long 0x1C "PLL_CORE_BWCTRL,"
bitfld.long 0x1C 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
newline
bitfld.long 0x1C 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth" "decrease BW,increase BW"
line.long 0x20 "PLL_CORE_FRACCTRL,"
bitfld.long 0x20 31. "DOWNSPREAD,Controls frequency spread" "enables both side frequency spread about the..,enables low frequency spread only"
newline
bitfld.long 0x20 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x20 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
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bitfld.long 0x20 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
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hexmask.long.tbyte 0x20 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
line.long 0x24 "PLL_CORE_STATUS,"
bitfld.long 0x24 31. "PONOUT,Status of the weak power-switch" "indicates the/OFF status of the weak..,ndicates the ON status of the weak power-switch.."
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bitfld.long 0x24 30. "PGOODOUT,Status of the strong power-switch" "indicates the/OFF status of the strong..,ndicates the ON status of the strong.."
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bitfld.long 0x24 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down" "0,1"
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bitfld.long 0x24 28. "RECAL_BSTATUS3,Recalibration status flag" "0,1"
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bitfld.long 0x24 27. "RECAL_OPPIN,Recalibration status flag" "0,1"
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bitfld.long 0x24 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x24 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
newline
bitfld.long 0x24 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
newline
bitfld.long 0x24 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
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bitfld.long 0x24 7. "STBYRETACK,Standby and retention status" "indicates to SOC that all internal clocks in..,indicates to SOC that all internal clocks in.."
newline
bitfld.long 0x24 6. "LOSSREF,Reference input loss" "0,1"
newline
bitfld.long 0x24 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN" "CLKOUT gating completed,CLKOUT enabling completed"
newline
bitfld.long 0x24 4. "LOCK2,ADPLL internal loop lock status" "0,1"
newline
bitfld.long 0x24 3. "M2CHANGEACK,Acknowledge for change to M2 divider" "0,1"
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bitfld.long 0x24 2. "SSCACK,Spread Spectrum status" "Spread-spectrum Clocking is disabled on output..,Spread-spectrum Clocking is enabled on output.."
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bitfld.long 0x24 1. "HIGHJITTER,1 indicates jitter" "0,1"
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bitfld.long 0x24 0. "BYPASS,Bypass status signal" "0,1"
line.long 0x28 "PLL_CORE_HSDIVIDER,"
rbitfld.long 0x28 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
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rbitfld.long 0x28 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
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bitfld.long 0x28 2. "TENABLEDIV,Tenable Div" "0,1"
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bitfld.long 0x28 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x28 0. "BYPASS,HSDIVIDER Bypass" "0,1"
line.long 0x2C "PLL_CORE_HSDIVIDER_CLKOUT0,"
bitfld.long 0x2C 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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rbitfld.long 0x2C 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x2C 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x2C 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x2C 0.--4. "DIV,DPLL post-divider factor M4 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x30 "PLL_CORE_HSDIVIDER_CLKOUT1,"
bitfld.long 0x30 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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rbitfld.long 0x30 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x30 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x30 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x30 0.--4. "DIV,DPLL post-divider factor M5 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "PLL_CORE_HSDIVIDER_CLKOUT2,"
bitfld.long 0x34 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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rbitfld.long 0x34 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x34 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x34 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x34 0.--4. "DIV,DPLL post-divider factor M6 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "PLL_CORE_HSDIVIDER_CLKOUT3,"
bitfld.long 0x38 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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rbitfld.long 0x38 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x38 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x38 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x38 0.--4. "DIV,DPLL post-divider factor M7 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "MSS_CR5_CLK_SRC_SEL,"
hexmask.long.word 0x3C 0.--11. 1. "clksrcsel,Select line for selecting source clock for MSS Coretex R5 and System bus Clock"
line.long 0x40 "MSS_CR5_DIV_VAL,"
hexmask.long.word 0x40 0.--11. 1. "clkdiv,Divider value for Cortex R5 selected clock"
line.long 0x44 "SYS_CLK_DIV_VAL,"
hexmask.long.word 0x44 0.--11. 1. "clkdiv,Divider value for System Clock selected clock"
line.long 0x48 "MSS_CR5_CLK_GATE,"
bitfld.long 0x48 0.--2. "gated,Only for debug- Functionality not guaranteed Clock gating config for MSS Coretex R5" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x4C "SYS_CLK_GATE,"
bitfld.long 0x4C 0.--2. "gated,Only for debug- Functionality not guaranteed Clock gating config for System Clock Data should be loaded as multibit" "Clock is ungated (multibit 000),?,?,?,?,?,?,Clock is gated (multibit 111)"
line.long 0x50 "SYS_CLK_STATUS,"
hexmask.long.byte 0x50 8.--15. 1. "currdivider,Status shows the current divider value choosen for Sys Clock"
line.long 0x54 "MSS_CR5_CLK_STATUS,"
hexmask.long.byte 0x54 8.--15. 1. "currdivider,Status shows the current divider value choosen for CortexR5 Clock"
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hexmask.long.byte 0x54 0.--7. 1. "clkinuse,Status shows the source clock slected for CortexR5 Clock"
line.long 0x58 "PLL_CORE_RSTCTRL,"
bitfld.long 0x58 0.--2. "assert,SW Reset override for the PLL" "0,1,2,3,4,5,6,7"
line.long 0x5C "PLL_CORE_HSDIVIDER_RSTCTRL,"
bitfld.long 0x5C 0.--2. "assert,SW Reset override for the HSDIVIDER" "0,1,2,3,4,5,6,7"
group.long 0x800++0x87
line.long 0x00 "PLL_DSP_PWRCTRL,"
bitfld.long 0x00 5. "PONIN,ON/OFF control of the weak power switch digital" "0,1"
newline
bitfld.long 0x00 4. "PGOODIN,ON/OFF control of the strong power switch digital" "0,1"
newline
bitfld.long 0x00 3. "RET,Save/Restore control for Retention mode" "0,1"
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bitfld.long 0x00 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
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bitfld.long 0x00 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins" "0,1"
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bitfld.long 0x00 0. "OFFMODE,Used to switch OFF the logic on VDDA" "0,1"
line.long 0x04 "PLL_DSP_CLKCTRL,"
bitfld.long 0x04 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK" "0,1"
newline
bitfld.long 0x04 30. "ENSSC,Controls Clock Spreading" "0,1"
newline
bitfld.long 0x04 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO" "synchronously disables CLKDCOLDO,synchronously enables CLKDCOLDO"
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bitfld.long 0x04 24.--28. "NWELLTRIM,Trim value for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x04 23. "IDLE,Sets PLL to Idle mode" "When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL.."
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bitfld.long 0x04 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module" "0,1"
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bitfld.long 0x04 21. "STBYRET,Standby retention control" "prepares ADPLLLJ for relock when out of..,prepares ADPLLLJ for retention by gating all the.."
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bitfld.long 0x04 20. "CLKOUTEN,CLKOUT enable or disable" "synchronously disables CLKOUT,synchronously enables CLKOUT"
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bitfld.long 0x04 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO" "synchronously disables CLKOUTLDO,synchronously enables CLKOUTLDO"
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bitfld.long 0x04 18. "ULOWCLKEN,Select CLKOUT source in bypass" "When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1),When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW"
newline
bitfld.long 0x04 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p" "0,1"
newline
bitfld.long 0x04 16. "M2PWDNZ,M2 divider power down mode" "Asynchronous power down for M2 divider,M2 divider is functional"
newline
bitfld.long 0x04 14. "STOPMODE,When in Lossclk/Stbyret" "Limp mode,Stopmode"
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bitfld.long 0x04 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector" "Reserved,?,HS2,Reserved,HS1,Reserved,?..."
newline
bitfld.long 0x04 8. "RELAXED_LOCK,Decides when FREQLOCK asserted" "FREQLOCK asserted when DC frequency error less..,FREQLOCK asserted when DC frequency error less.."
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bitfld.long 0x04 1. "SSCTYPE,SSC Type" "0,1"
newline
bitfld.long 0x04 0. "TINTZ,PLL core soft reset" "0,1"
line.long 0x08 "PLL_DSP_TENABLE,"
bitfld.long 0x08 0. "TENABLE,M N" "0,1"
line.long 0x0C "PLL_DSP_TENABLEDIV,"
bitfld.long 0x0C 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
line.long 0x10 "PLL_DSP_M2NDIV,"
hexmask.long.byte 0x10 16.--22. 1. "M2,Post-divider is REGM2"
newline
hexmask.long.byte 0x10 0.--7. 1. "N,Pre-divider is REGN+1"
line.long 0x14 "PLL_DSP_MN2DIV,"
bitfld.long 0x14 16.--19. "N2,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
hexmask.long.word 0x14 0.--11. 1. "M,Feedback Multiplier is REGM"
line.long 0x18 "PLL_DSP_FRACDIV,"
hexmask.long.byte 0x18 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance"
newline
hexmask.long.tbyte 0x18 0.--17. 1. "FRACTIONALM,Fractional part of the M divider"
line.long 0x1C "PLL_DSP_BWCTRL,"
bitfld.long 0x1C 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
newline
bitfld.long 0x1C 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth" "decrease BW,increase BW"
line.long 0x20 "PLL_DSP_FRACCTRL,"
bitfld.long 0x20 31. "DOWNSPREAD,Controls frequency spread" "enables both side frequency spread about the..,enables low frequency spread only"
newline
bitfld.long 0x20 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency" "0,1,2,3,4,5,6,7"
newline
hexmask.long.byte 0x20 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
newline
bitfld.long 0x20 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
newline
hexmask.long.tbyte 0x20 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
line.long 0x24 "PLL_DSP_STATUS,"
bitfld.long 0x24 31. "PONOUT,Status of the weak power-switch" "indicates the/OFF status of the weak..,ndicates the ON status of the weak power-switch.."
newline
bitfld.long 0x24 30. "PGOODOUT,Status of the strong power-switch" "indicates the/OFF status of the strong..,ndicates the ON status of the strong.."
newline
bitfld.long 0x24 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down" "0,1"
newline
bitfld.long 0x24 28. "RECAL_BSTATUS3,Recalibration status flag" "0,1"
newline
bitfld.long 0x24 27. "RECAL_OPPIN,Recalibration status flag" "0,1"
newline
bitfld.long 0x24 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
newline
bitfld.long 0x24 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
newline
bitfld.long 0x24 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
newline
bitfld.long 0x24 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
newline
bitfld.long 0x24 7. "STBYRETACK,Standby and retention status" "indicates to SOC that all internal clocks in..,indicates to SOC that all internal clocks in.."
newline
bitfld.long 0x24 6. "LOSSREF,Reference input loss" "0,1"
newline
bitfld.long 0x24 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN" "CLKOUT gating completed,CLKOUT enabling completed"
newline
bitfld.long 0x24 4. "LOCK2,ADPLL internal loop lock status" "0,1"
newline
bitfld.long 0x24 3. "M2CHANGEACK,Acknowledge for change to M2 divider" "0,1"
newline
bitfld.long 0x24 2. "SSCACK,Spread Spectrum status" "Spread-spectrum Clocking is disabled on output..,Spread-spectrum Clocking is enabled on output.."
newline
bitfld.long 0x24 1. "HIGHJITTER,1 indicates jitter" "0,1"
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bitfld.long 0x24 0. "BYPASS,Bypass status signal" "0,1"
line.long 0x28 "PLL_DSP_HSDIVIDER,"
rbitfld.long 0x28 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
newline
rbitfld.long 0x28 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
newline
bitfld.long 0x28 2. "TENABLEDIV,Tenable Div" "0,1"
newline
bitfld.long 0x28 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x28 0. "BYPASS,HSDIVIDER Bypass" "0,1"
line.long 0x2C "PLL_DSP_HSDIVIDER_CLKOUT0,"
bitfld.long 0x2C 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
newline
rbitfld.long 0x2C 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x2C 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x2C 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x2C 0.--4. "DIV,DPLL post-divider factor M4 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x30 "PLL_DSP_HSDIVIDER_CLKOUT1,"
bitfld.long 0x30 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
newline
rbitfld.long 0x30 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
newline
bitfld.long 0x30 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x30 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
newline
bitfld.long 0x30 0.--4. "DIV,DPLL post-divider factor M5 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x34 "PLL_DSP_HSDIVIDER_CLKOUT2,"
bitfld.long 0x34 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
newline
rbitfld.long 0x34 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
newline
bitfld.long 0x34 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x34 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
newline
bitfld.long 0x34 0.--4. "DIV,DPLL post-divider factor M6 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x38 "PLL_DSP_HSDIVIDER_CLKOUT3,"
bitfld.long 0x38 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
newline
rbitfld.long 0x38 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
newline
bitfld.long 0x38 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
newline
rbitfld.long 0x38 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
newline
bitfld.long 0x38 0.--4. "DIV,DPLL post-divider factor M7 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "PLL_PER_PWRCTRL,"
bitfld.long 0x3C 5. "PONIN,ON/OFF control of the weak power switch digital" "0,1"
newline
bitfld.long 0x3C 4. "PGOODIN,ON/OFF control of the strong power switch digital" "0,1"
newline
bitfld.long 0x3C 3. "RET,Save/Restore control for Retention mode" "0,1"
newline
bitfld.long 0x3C 2. "ISORET,Save/Restore control for Isolation of output pins For functional mode it should be 0" "0,1"
newline
bitfld.long 0x3C 1. "ISOSCAN,Save/Restore control for Isolation of the Scanout pins" "0,1"
newline
bitfld.long 0x3C 0. "OFFMODE,Used to switch OFF the logic on VDDA" "0,1"
line.long 0x40 "PLL_PER_CLKCTRL,"
bitfld.long 0x40 31. "CYCLESLIPEN,FailSafe enable to trigger re-calibration in case CycleSlip occurs between REFCLK and FBCLK" "0,1"
newline
bitfld.long 0x40 30. "ENSSC,Controls Clock Spreading" "0,1"
newline
bitfld.long 0x40 29. "CLKDCOLDOEN,Synchronously enables/disables CLKDCOLDO" "synchronously disables CLKDCOLDO,synchronously enables CLKDCOLDO"
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bitfld.long 0x40 24.--28. "NWELLTRIM,Trim value for the PLL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x40 23. "IDLE,Sets PLL to Idle mode" "When SYSRESET = 0 and TINITZ = 1 IDLE = 0 PLL..,When SYSRESET = 0 and TINITZ = 1 IDLE = 1 PLL.."
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bitfld.long 0x40 22. "BYPASSACKZ,BYPASSACKZ is a special purpose input to the module" "0,1"
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bitfld.long 0x40 21. "STBYRET,Standby retention control" "prepares ADPLLLJ for relock when out of..,prepares ADPLLLJ for retention by gating all the.."
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bitfld.long 0x40 20. "CLKOUTEN,CLKOUT enable or disable" "synchronously disables CLKOUT,synchronously enables CLKOUT"
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bitfld.long 0x40 19. "CLKOUTLDOEN,Synchronously enables/disables CLKOUTLDO" "synchronously disables CLKOUTLDO,synchronously enables CLKOUTLDO"
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bitfld.long 0x40 18. "ULOWCLKEN,Select CLKOUT source in bypass" "When ADPLLLJ in bypass mode CLKOUT = CLKINP/(N2+1),When ADPLLLJ in bypass mode CLKOUT = CLKINPULOW"
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bitfld.long 0x40 17. "CLKDCOLDOPWDNZ,0 Asynchronous power down for CLKDCOLDO o/p" "0,1"
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bitfld.long 0x40 16. "M2PWDNZ,M2 divider power down mode" "Asynchronous power down for M2 divider,M2 divider is functional"
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bitfld.long 0x40 14. "STOPMODE,When in Lossclk/Stbyret" "Limp mode,Stopmode"
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bitfld.long 0x40 10.--12. "SELFREQDCO,DCO Clock (DCOCLK = CLKINP * [M/(N+1)]) frequency range selector" "Reserved,?,HS2,Reserved,HS1,Reserved,?..."
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bitfld.long 0x40 8. "RELAXED_LOCK,Decides when FREQLOCK asserted" "FREQLOCK asserted when DC frequency error less..,FREQLOCK asserted when DC frequency error less.."
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bitfld.long 0x40 1. "SSCTYPE,SSC Type" "0,1"
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bitfld.long 0x40 0. "TINTZ,PLL core soft reset" "0,1"
line.long 0x44 "PLL_PER_TENABLE,"
bitfld.long 0x44 0. "TENABLE,M N" "0,1"
line.long 0x48 "PLL_PER_TENABLEDIV,"
bitfld.long 0x48 0. "TENABLEDIV,M2 and N2 latch (active rise edge)" "0,1"
line.long 0x4C "PLL_PER_M2NDIV,"
hexmask.long.byte 0x4C 16.--22. 1. "M2,Post-divider is REGM2"
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hexmask.long.byte 0x4C 0.--7. 1. "N,Pre-divider is REGN+1"
line.long 0x50 "PLL_PER_MN2DIV,"
bitfld.long 0x50 16.--19. "N2,Bypass divider is REGN2+1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.word 0x50 0.--11. 1. "M,Feedback Multiplier is REGM"
line.long 0x54 "PLL_PER_FRACDIV,"
hexmask.long.byte 0x54 24.--31. 1. "REGSD,Sigma-Delta Divider Should be set by s/w to provide optimum jitter performance"
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hexmask.long.tbyte 0x54 0.--17. 1. "FRACTIONALM,Fractional part of the M divider"
line.long 0x58 "PLL_PER_BWCTRL,"
bitfld.long 0x58 1.--2. "BWCONTROL,Change Loop Bandwidth" "0,1,2,3"
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bitfld.long 0x58 0. "BW_INCR_DECRZ,Direction of Loop Bandwidth" "decrease BW,increase BW"
line.long 0x5C "PLL_PER_FRACCTRL,"
bitfld.long 0x5C 31. "DOWNSPREAD,Controls frequency spread" "enables both side frequency spread about the..,enables low frequency spread only"
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bitfld.long 0x5C 28.--30. "ModFreqDividerExponent,Exponent of the REFCLK divider to define the modulation frequency" "0,1,2,3,4,5,6,7"
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hexmask.long.byte 0x5C 21.--27. 1. "ModFreqDividerMantissa,Mantissa of the REFCLK divider to define the modulation frequency"
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bitfld.long 0x5C 18.--20. "DeltaMStepInteger,Integer part of Frequency Spread control" "0,1,2,3,4,5,6,7"
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hexmask.long.tbyte 0x5C 0.--17. 1. "DeltaMStepFraction,The fraction part of Frequency Spread control"
line.long 0x60 "PLL_PER_STATUS,"
bitfld.long 0x60 31. "PONOUT,Status of the weak power-switch" "indicates the/OFF status of the weak..,ndicates the ON status of the weak power-switch.."
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bitfld.long 0x60 30. "PGOODOUT,Status of the strong power-switch" "indicates the/OFF status of the strong..,ndicates the ON status of the strong.."
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bitfld.long 0x60 29. "LDOPWDN,1 indicates ADPLLLJ internal LDO is power down" "0,1"
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bitfld.long 0x60 28. "RECAL_BSTATUS3,Recalibration status flag" "0,1"
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bitfld.long 0x60 27. "RECAL_OPPIN,Recalibration status flag" "0,1"
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bitfld.long 0x60 11. "CLKDCOLDOACK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x60 10. "PHASELOCK,Status on PHASELOCK output pin" "0,1"
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bitfld.long 0x60 9. "FREQLOCK,Status on FREQLOCK output pin" "0,1"
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bitfld.long 0x60 8. "BYPASSACK,Status of BYPASSACK output pin" "0,1"
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bitfld.long 0x60 7. "STBYRETACK,Standby and retention status" "indicates to SOC that all internal clocks in..,indicates to SOC that all internal clocks in.."
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bitfld.long 0x60 6. "LOSSREF,Reference input loss" "0,1"
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bitfld.long 0x60 5. "CLKOUTENACK,Indicates the enable/disable condition of CLKOUTEN" "CLKOUT gating completed,CLKOUT enabling completed"
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bitfld.long 0x60 4. "LOCK2,ADPLL internal loop lock status" "0,1"
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bitfld.long 0x60 3. "M2CHANGEACK,Acknowledge for change to M2 divider" "0,1"
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bitfld.long 0x60 2. "SSCACK,Spread Spectrum status" "Spread-spectrum Clocking is disabled on output..,Spread-spectrum Clocking is enabled on output.."
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bitfld.long 0x60 1. "HIGHJITTER,1 indicates jitter" "0,1"
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bitfld.long 0x60 0. "BYPASS,Bypass status signal" "0,1"
line.long 0x64 "PLL_PER_HSDIVIDER,"
rbitfld.long 0x64 17. "LDOPWDNACK,LDO Power Down Ack" "0,1"
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rbitfld.long 0x64 16. "BYPASSACKZ,HSDIVIDER Bypass Ack" "0,1"
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bitfld.long 0x64 2. "TENABLEDIV,Tenable Div" "0,1"
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bitfld.long 0x64 1. "LDOPWDN,LDO Power Down" "0,1"
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bitfld.long 0x64 0. "BYPASS,HSDIVIDER Bypass" "0,1"
line.long 0x68 "PLL_PER_HSDIVIDER_CLKOUT0,"
bitfld.long 0x68 12. "PWDN,Power down for HSDIVIDER M4 divider and hence CLKOUT0 output 0h (R/W) = CLKOUT0 divider active 1h (R/W) = CLKOUT0 divider is powered down" "0,1"
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rbitfld.long 0x68 9. "STATUS,HSDIVIDER CLKOUT0 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x68 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT0 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x68 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT0_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x68 0.--4. "DIV,DPLL post-divider factor M4 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x6C "PLL_PER_HSDIVIDER_CLKOUT1,"
bitfld.long 0x6C 12. "PWDN,Power down for HSDIVIDER M5 divider and hence CLKOUT1 output 0h (R/W) = CLKOUT1 divider active 1h (R/W) = CLKOUT1 divider is powered down" "0,1"
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rbitfld.long 0x6C 9. "STATUS,HSDIVIDER CLKOUT1 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x6C 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT1 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x6C 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x6C 0.--4. "DIV,DPLL post-divider factor M5 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x70 "PLL_PER_HSDIVIDER_CLKOUT2,"
bitfld.long 0x70 12. "PWDN,Power down for HSDIVIDER M6 divider and hence CLKOUT2 output 0h (R/W) = CLKOUT2 divider active 1h (R/W) = CLKOUT2 divider is powered down" "0,1"
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rbitfld.long 0x70 9. "STATUS,HSDIVIDER CLKOUT2 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x70 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT2 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x70 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x70 0.--4. "DIV,DPLL post-divider factor M6 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x74 "PLL_PER_HSDIVIDER_CLKOUT3,"
bitfld.long 0x74 12. "PWDN,Power down for HSDIVIDER M7 divider and hence CLKOUT3 output 0h (R/W) = CLKOUT3 divider active 1h (R/W) = CLKOUT3 divider is powered down" "0,1"
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rbitfld.long 0x74 9. "STATUS,HSDIVIDER CLKOUT3 status 0h (R) = The clock output is gated 1h (R) = The clock output is enabled" "0,1"
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bitfld.long 0x74 8. "GATE_CTRL,Control gating of HSDIVIDER CLKOUT3 0h (R/W) = Automatically gate this clock when there is no dependency for it 1h (R/W) = Force this clock to stay enabled even if there is no request" "0,1"
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rbitfld.long 0x74 5. "DIVCHACK,Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect" "0,1"
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bitfld.long 0x74 0.--4. "DIV,DPLL post-divider factor M7 for internal clock generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x78 "PLL_DSP_RSTCTRL,"
bitfld.long 0x78 0.--2. "assert,SW Reset override for the PLL" "0,1,2,3,4,5,6,7"
line.long 0x7C "PLL_DSP_HSDIVIDER_RSTCTRL,"
bitfld.long 0x7C 0.--2. "assert,SW Reset override for the HSDIVIDER" "0,1,2,3,4,5,6,7"
line.long 0x80 "PLL_PER_RSTCTRL,"
bitfld.long 0x80 0.--2. "assert,SW Reset override for the PLL" "0,1,2,3,4,5,6,7"
line.long 0x84 "PLL_PER_HSDIVIDER_RSTCTRL,"
bitfld.long 0x84 0.--2. "assert,SW Reset override for the HSDIVIDER" "0,1,2,3,4,5,6,7"
group.long 0xC00++0x13
line.long 0x00 "ANA_REG_CLK_CTRL_REG1_XO_SLICER,"
bitfld.long 0x00 31. "OSC_CLKOUT_EN,OSC_CLKOUT Enable Enables the Slicer clock to drive the OSC_CLKOUT output buffer" "Functional Reset,Clock Enabled"
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bitfld.long 0x00 29.--30. "OSC_CLKOUT_FREQ_SEL,OSC_CLKOUT Frequency Selection Selects the output frequency as a division of the XTAL (or externally driven CLKP) frequency" "Functional Reset,?,XTAL/1,XTAL/4"
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bitfld.long 0x00 28. "OSC_CLKOUT_CLRZ_DIV,OSC_CLKOUT Divider ClearZ This active low signal permits the output frequency dividers to be properly cleared before enabling" "All dividers cleared,Functional Reset"
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bitfld.long 0x00 24.--27. "OSC_CLKOUT_DRV,OSC_CLKOUT Drive This bit controls the drive strength of the OSC_CLKOUT buffer" "No Test Output Hi-Z Output Drive Ctrl =..,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Functional Reset"
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hexmask.long.word 0x00 13.--23. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x00 12. "XTAL_DETECT_XO_SLICER,XTAL Detect Enable This bit connects a pullup and sense circuitry to CLKM to detect the presence or absence of a crystal" "Functional Reset,XTAL sense function enabled (pullup and sense.."
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bitfld.long 0x00 11. "SLICER_DCCPL_XO_SLICER,Slicer DC-Coupled Mode" "Functional Reset,DC-couple CLKP to internal slicer to CLKP"
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bitfld.long 0x00 10. "SLICER_HIPWR_XO_SLICER,Slicer High-power Mode This bit bypasses the input clock slicer current-starving/filtering circuitry to increase gain and reduce device phase-noise at the expense of power and reduced supply noise rejection" "Functional Reset,High-power/high-speed test mode"
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bitfld.long 0x00 9. "FASTCHARGEZ_BIAS_XO_SLICER,Bias Fast-charge Enable (Active Low) This bit bypasses the RC filtering on the XOSC/SLICER Bias to permit more rapid power-up" "Bias fast-charge,Functional Reset"
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bitfld.long 0x00 4.--8. "XOSC_DRIVE_XO_SLICER,Crystal Oscillator Output Drive Binary-weighted oscillator drive control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0.--3. "RTRIM_BIAS_XO_SLICER,Crystal Oscillator and Slicer Bias RTrim Binary-weighted bias control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "ANA_REG_CLK_CTRL_REG1_CLKTOP,"
hexmask.long 0x04 3.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x04 2. "ENABLE_XOSC,Enable Crystal Oscillator" "Disabled,Functional Reset"
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bitfld.long 0x04 1. "ENABLE_SLICER_CLKP,Enable CLKP Input Slicer" "Disabled,Functional Reset"
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bitfld.long 0x04 0. "ENABLE_BIAS_XO_SLICER,Enable Bias for Crystal Oscillator and Slicer" "Disabled,Functional Reset"
line.long 0x08 "ANA_REG_CLK_CTRL_REG2_CLKTOP,"
bitfld.long 0x08 31. "CTRL_DC_BIST_BUFEN,Disable for CLK_TOP DC BIST BUFFER" "Functional Reset,CLK TOP DC BIST BUFFER DISABLED"
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hexmask.long 0x08 0.--30. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
line.long 0x0C "ANA_REG_CLK_CTRL_REG1_LDO_CLKTOP,"
hexmask.long.tbyte 0x0C 8.--31. 1. "RESERVED1,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x0C 7. "CLK_BIST_DISABLE_LDO,DC BIST Disable for LDO" "Functional Reset,DC BIST Disabled"
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bitfld.long 0x0C 1.--6. "RESERVED0,Reserved Reads return 0x0 and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x0C 0. "EN_SLICER_LDO,Slicer LDO Enable" "Slicer LDO Disabled,Functional Reset"
line.long 0x10 "ANA_REG_CLK_CTRL_REG2_LDO_CLKTOP,"
hexmask.long.byte 0x10 24.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x10 20.--23. "BISTMUX_CTRL,SLICER LDO BIST MUX CONTROL (ONE HOT) Analog MUX enables to BIST output port" "HI-Z Output,VBG_0P9*10/9 =1.0 V,VDD18*0.5 = 0.9V,?,Functional Reset,?,?,?,Floating WARNING: Enabling more than one bit..,?..."
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bitfld.long 0x10 16.--19. "TESTMUX_CTRL,SLICER LDO TEST MUX CONTROL (ONE HOT) Analog MUX enables to test output port" "Functional Reset,0.6 * VLDO_OUT,VDD18*0.5 = 0.9V,?,VSSA,?,?,?,LDO Test Current (12.5uA) WARNING:..,?..."
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bitfld.long 0x10 13.--15. "TLOAD_CTRL,SLICER LDO TLOAD CONTROL updated description needed" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 12. "ENABLE_PMOS_PULLDOWN,SLICER LDO PMOS PULL DOWN ENABLE" "Functional Reset,Slicer LDO PMOS Pull Down enabled"
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bitfld.long 0x10 11. "SCPRT_IBIAS_CTRL,SLICER LDO SHORT CKT PROTECTION IBIAS CONTROL" "Functional Reset,2X Nominal short circuit bias with higher.."
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bitfld.long 0x10 8.--10. "LDO_BW_CTRL,SLICER LDO BANDWIDTH CONTROL need updated description" "0,1,2,3,4,5,6,7"
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bitfld.long 0x10 7. "EN_BYPASS,SLICER LDO BYPASS ENABLE" "Functional Reset,Slicer LDO Bypassed with external voltage"
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bitfld.long 0x10 6. "EN_SHRT_CKT,SLICER LDO SHORT CKT PROTECTION ENABLE" "Functional Reset,Slicer LDO Short Ckt Protection Enabled"
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bitfld.long 0x10 5. "EN_TEST_MODE,SLICER LDO TEST MODE ENABLE" "Functional Reset,Slicer LDO TEST MODE Enabled"
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bitfld.long 0x10 4. "ENZ_LOW_BW_CAP,SLICER LDO LOW BW MODE DISABLE" "Slicer LDO Low BW mode Disabled,Functional Reset"
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bitfld.long 0x10 0.--3. "LDO_VOUT_CTRL,SLICER LDO VOUT TRIM NEEDS updated description" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.long 0xC18++0x2F
line.long 0x00 "ANA_REG_CLK_STATUS_REG,"
hexmask.long 0x00 1.--31. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x00 0. "SLICER_LDO_SC_OUT,SLICER LDO SHORT CIRCUIT INDICATOR" "Normal operation,LDO Output Short Circuit Detected"
line.long 0x04 "ANA_REG_REFSYS_CTRL_REG_LOWV,"
bitfld.long 0x04 31. "RESERVED2,Reserved" "0,1"
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bitfld.long 0x04 27.--30. "FTRIM_3_0,Filter TRIM Control" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 26. "RESERVED1,<7> Unused" "0,1"
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bitfld.long 0x04 25. "IDIODE_EN,<6> Idiode Active Low Control --> Unused in TPR Reserved for AWR <0> - Enable <1> - Disable" "0,1"
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bitfld.long 0x04 24. "REFSYS_V2I_BYPASS_EN,<5> REFSYS V2I By-Pass Enable" "0,1"
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bitfld.long 0x04 23. "TX_TOP_IBIAS_EN,<4> TX TOP IBIAS EN--> Unused in TPR Reserved for AWR" "0,1"
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bitfld.long 0x04 22. "LODIST_IBIAS_EN,<3> LO DIST BIAS EN --> Unused in TPR Reserved for AWR" "0,1"
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bitfld.long 0x04 21. "CLKTOP_IBIAS_EN,<2> CLK TOP IBIAS EN" "0,1"
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bitfld.long 0x04 20. "V2I_STARTUP,<1> V2I Startup" "0,1"
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bitfld.long 0x04 19. "BGAP_ISW,<0> BGAP ISW STARTUP" "0,1"
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bitfld.long 0x04 14.--18. "IREF_TRIM_4_0,Default Resistor Trim for NOM LOT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 9.--13. "MAG_TRIM_4_0,Default Magnitude Trim for NOM LOT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 4.--8. "SLOPE_TRIM_4_0,Default Slope Trim for NOM LOT" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 3. "REFSYS_PRE_CHARGE,REFSYS Pre Charge Control" "Functional Reset,Enable Pre Charge Block"
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bitfld.long 0x04 2. "REFSYS_CAP_SW_CTRLZ,REFSYS Cap Switch Control" "Functional Reset,Disconnect External Cap to Reference output"
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bitfld.long 0x04 1. "REFSYS_V2I_EN_CTRL,REFSYS Enable Control" "Disable V2I REFSYS,Functional Reset"
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bitfld.long 0x04 0. "REFSYS_BGAP_EN_CTRL,REFSYS Enable Control" "Disable REFSYS,Functional Reset"
line.long 0x08 "ANA_REG_REFSYS_TMUX_CTRL_LOWV,"
bitfld.long 0x08 31. "REFSYS_CTRL_8,REFSYS Test Mux Enable" "Functional Reset,TMUX Enabled"
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hexmask.long.word 0x08 16.--30. 1. "RESERVED1,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x08 15. "LO_IBIASP_20u,<15> LO IBG BIASP 20uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 14. "TX_IBIASP_20u,<14> TX IBG BIASP 20uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 13. "BYPASS_MIRR_VPBIAS,VPBIAS Control for IREF Gen Test Mode V2I By-Pass Feature" "0,1"
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bitfld.long 0x08 12. "I2V_SENSE,Sense Voltage from the BIST I2V cinversion of 20u and 6u bias current paths Sense voltage of 1V for BIST select<6> Sense voltage of 0.3V for BIST select<7>" "0,1"
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bitfld.long 0x08 11. "VSSA_REF,<11> VSSA REF (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 10. "IREFP_10UA,<10> IREFP 10uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 9. "IDIODEP_100U,<9> Idiode BIASP 100uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 8. "RESERVED4,Unused" "0,1"
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bitfld.long 0x08 7. "IBIASP_TS_6U,<7> IBG BIASP TS 6uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 6. "IBIASP_20U,<6> CLK IBG BIASP 20uA (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 5. "RESERVED3,Unused" "0,1"
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bitfld.long 0x08 4. "VBE_WEAK,<4> - VBE Weak (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 3. "RESERVED2,Unused" "0,1"
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bitfld.long 0x08 2. "VBG_1P22V,<2> - VBG 1.22V (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 1. "VREF_0P9V,<1> - VREF 0P9V (Cap Node) (TMUX One-Hot)" "0,1"
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bitfld.long 0x08 0. "VREF_0P45V,<0> - VREF 0P45 (TMUX One-Hot)" "0,1"
line.long 0x0C "ANA_REG_REFSYS_SPARE_REG_LOWV,"
bitfld.long 0x0C 31. "ANALOGTEST_TMUX_ESD_CTRL,ANALOGTEST TMUX ESD CTRL in Pad-Frame (formerly RX_REFSYS_TMUX_SPARE_CTRL_LOWV<31> in AWR/IWR devices but RX does not exist in TPR)" "0,1"
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hexmask.long.word 0x0C 22.--30. 1. "REFSYS_SPARE_30_22,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x0C 21. "VDD_OV_RSET_EN,If asserted VDD_OV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 20. "VDD_UV_RSET_EN,If asserted VDD_UV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 19. "VDDA_OSC_UV_RSET_EN,If asserted VDDA_OSC_UV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 18. "VIOIN_UV_RSET_EN,If asserted VIOIN_UV will automatically reset the device through hardware control" "0,1"
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bitfld.long 0x0C 16.--17. "VDD_OV_SR_SEL,Final level of VDD 1.2V VMON OV Reference Selection See definition in REFSYS_SPARE_REG<15:14>" "0,1,2,3"
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bitfld.long 0x0C 14.--15. "VDD_OV_IR_DROP_COMP_SEL,VDD 1.2V VMON OV Reference Selection Reference selection is dependent on REFSYS_SPARE_REG<17:16> programming If REFSYS_SPARE_REG<17:16> = 0x0" "Functional..,0.58V,0.57V,0.56V"
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bitfld.long 0x0C 13. "RESERVED1,Reserved Reserved in case VIOIN OV VMON and self test is ever implemented" "0,1"
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bitfld.long 0x0C 12. "VDDS_3P3V_UV_SELF_TEST_SEL,Enable VIOIN Strict UV VMON Self Test If Self-test mode is enabled VIOIN UV VMON reference is programmed as follows for REFSYS_SPARE_REG<3:2>" "Functional..,0.64V"
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bitfld.long 0x0C 11. "RESERVED0,Reserved Reserved in case VDDA_OSC OV VMON and self test is ever implemented" "0,1"
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bitfld.long 0x0C 10. "VDDA_OSC_UV_SELF_TEST_SEL,Enable VDDA_OSC Strict UV VMON Self Test If Self-test mode is enabled VDDA_OSC UV VMON reference is programmed as follows for REFSYS_SPARE_REG<5:4>" "Functional..,0.64V"
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bitfld.long 0x0C 9. "VDD_OV_SELF_TEST_SEL,Enable 1.2V VDD Strict OV VMON Self Test If Self-test mode is enabled VDD 1.2V VMON OV reference is programmed based on REFSYS_SPARE_REG<1:0> as follows: If REFSYS_SPARE_REG<7:6> = 0x0 REFSYS_SPARE_REG<1:0>" "Functional..,0.5V"
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bitfld.long 0x0C 8. "VDD_UV_SELF_TEST_SEL,Enable 1.2V VDD Strict UV VMON Self Test If Self-test mode is enabled VDD 1.2V VMON UV reference is programmed based on REFSYS_SPARE_REG<15:14> as follows: If REFSYS_SPARE_REG<17:16> = 0x0 REFSYS_SPARE_REG<15:14>" "Functional..,0.58V"
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bitfld.long 0x0C 6.--7. "VDD_SR_SEL,Final level of VDD 1.2V VMON UV Reference Selection See definition in REFSYS_SPARE_REG<1:0>" "0,1,2,3"
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bitfld.long 0x0C 4.--5. "VDDA_OSC_IR_DROP_COMP_SEL,VDDA_OSC UV VMON Reference Selection" "Functional..,0.54V,0.52V,0.5V"
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bitfld.long 0x0C 2.--3. "VDDS_3P3V_IR_DROP_COMP_SEL,VIOIN VMON UV Reference Selection" "Functional..,0.54V,0.52V,0.5V"
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bitfld.long 0x0C 0.--1. "VDD_IR_DROP_COMP_SEL,VDD 1.2V VMON UV Reference Selection Reference selection is dependent on REFSYS_SPARE_REG<7:6> programming If REFSYS_SPARE_REG<7:6> = 0x0" "Functional..,0.5V,0.49V,0.48V"
line.long 0x10 "ANA_REG_WU_CTRL_REG_LOWV,"
bitfld.long 0x10 31. "RESERVED0,Reserved Reads return 0x0 and writes have no effect" "0,1"
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bitfld.long 0x10 29.--30. "WU_SPARE_IN_2,WU Spare Control" "0,1,2,3"
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bitfld.long 0x10 28. "WU_VDD_OV_VMON_EN,WU VDD OV VMON Enable Control" "Functional Reset,VDD OV Detect Enabled"
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bitfld.long 0x10 27. "WU_VDD_UV_VMON_EN,WU VDD UV VMON Enable Control" "Functional Reset,VDD UV Detect Enabled"
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bitfld.long 0x10 26. "WU_VDDA_OSC_UV_VMON_EN,WU VDDA OSC UV VMON Enable Control" "Functional Reset,VDDA OSC UV Detect Enabled"
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bitfld.long 0x10 25. "WU_VDDS_3P3V_UV_VMON_EN,WU VDDS 3.3V UV VMON Enable Control" "Functional Reset,VDDS 3.3V UV Detect Enabled"
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bitfld.long 0x10 23.--24. "WU_SPARE_IN,WU Spare Control Change for 1642 ES2P0 Change Name : Newly added OR gates to provide options to bypass crude VDD DET (also refer to <11>) Bit <0> of this field when HIGH over rides the crude VDD_DET this control is using firmware Bit<0> of.." "0,1,2,3"
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bitfld.long 0x10 22. "WU_SUPP_DET_CTRL,WU VMON Detect Status Override Disable in Functional Test SOP" "VMON Det Status Override Disabled,Functional Reset"
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bitfld.long 0x10 21. "WU_VRAM_VMON_EN,WU VRAM VMON Enable Control" "SRAM UV Detect Disabled,Functional Reset"
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bitfld.long 0x10 20. "WU_SUPP_VMON_EN,WU VMON Enable Control" "VMON Control Disabled,Functional Reset"
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bitfld.long 0x10 19. "WU_XTAL_DLY_CTRL,Introduce additional delay for XTAL settling" "Functional Reset,Introduce additional delay as per WU-SEQ"
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bitfld.long 0x10 18. "WU_OV_DET_CTRL,WU Over Voltage Detect Control Changed for 1243 ES3P0 (Metal only change from 1642 ES2P0) Change Name : FW control of VDD OV DET EN" "OV Detect is Enabled,Functional Reset"
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bitfld.long 0x10 17. "WU_UV_DET_CTRL,WU Under Voltage Detect Control" "UV Detect is disabled,Functional Reset"
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bitfld.long 0x10 16. "XTAL_EN_OVERRIDE,XTAL EN Override (WU-SEQ) Control" "Functional Reset,Override XTAL Enable if disabled by default"
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bitfld.long 0x10 15. "WU_CPU_CLK_CTRL,WU CLK Control" "CLK Monitor Function in Dig Sequencer is..,Functional Reset"
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bitfld.long 0x10 11.--14. "INT_CLK_FREQ_SEL_3_0,WU Internal Clock (RCOSC) Frequency Select Bit<3> is used as override for VMON on Untrimmed devices" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 3.--10. 1. "INT_CLK_TRIM_7_0,WU lnternal Clock (RCOSC) Trim"
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bitfld.long 0x10 2. "INT_CLK_SW_SEL,WU Internal Clock (RCOSC) SW_SEL" "TBD,.."
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bitfld.long 0x10 1. "INT_CLK_STOP,WU Internal Clock (RCOSC) STOP" "Functional Reset,Internal CLK is OFF"
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bitfld.long 0x10 0. "INT_CLK_EN,WU Internal Clock (RCOSC) ENABLE" "Internal CLK Disabled,Functional Reset"
line.long 0x14 "ANA_REG_WU_TMUX_CTRL_LOWV,"
bitfld.long 0x14 31. "WU_TMUX_EN,WU TMUX Enable" "Functional Reset,TMUX Enabled"
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hexmask.long.word 0x14 21.--30. 1. "RESERVED0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x14 20. "VDDSINT18,VIOIN scaled supply for VIOIN Detect Scaling Factor: VIOIN*(52/90)" "0,1"
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bitfld.long 0x14 19. "SCALED_VDDA_OSC,Scaled VDDA_OSC supply for crude supply detect Scaling Factor: VDDA_OSC*(22/39)" "0,1"
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bitfld.long 0x14 18. "VFB_0P85V,Scaled VDD 1.2V used as reference for VDDA_OSC crude supply detect" "0,1"
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bitfld.long 0x14 17. "VDDA_OSC_UV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 16. "VDD_SR_UV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 15. "VT_DIG_SIG_OV,Test Mux Control" "0,1"
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bitfld.long 0x14 14. "VT_DIG_SIG_UV,Test Mux Control" "0,1"
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bitfld.long 0x14 13. "VT_ANA_SIG,Test Mux Control" "0,1"
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bitfld.long 0x14 12. "VDDA14_2_INT,Test Mux Control" "0,1"
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bitfld.long 0x14 11. "SCALED_VDDA_LVDS_1P8V_1P2,Test Mux Control" "0,1"
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bitfld.long 0x14 10. "VDDA14_INT,Test Mux Control" "0,1"
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bitfld.long 0x14 9. "VIOIN_UV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 8. "SCALED_VDDA18,Test Mux Control" "0,1"
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bitfld.long 0x14 7. "VREF_0P9V,Test Mux Control" "0,1"
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bitfld.long 0x14 6. "VDD_SR_OV_VREF,Test Mux Control" "0,1"
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bitfld.long 0x14 5. "SCALED_VDDA_LVDS_1P8V,Test Mux Control" "0,1"
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bitfld.long 0x14 4. "SCALED_VIOIN,Test Mux Control" "0,1"
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bitfld.long 0x14 3. "VFB_0P6V,Test Mux Control" "0,1"
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bitfld.long 0x14 2. "SCALED_VDDS18,Test Mux Control" "0,1"
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bitfld.long 0x14 1. "SCALED_VIO3318,Test Mux Control" "0,1"
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bitfld.long 0x14 0. "SCALED_VDDA_OSC_UV,Test Mux Control" "0,1"
line.long 0x18 "ANA_REG_TW_CTRL_REG_LOWV,"
hexmask.long.word 0x18 20.--31. 1. "Reserved1,Reserved"
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bitfld.long 0x18 15.--19. "RTRIM_TW_4_0,RTRIM value to TW routed to BIST MUX IN REFSYS for I2V" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 14. "ANA_TMUX_BUF_EN,TW ANA TMUX Buffer Enabled" "Functional Reset,ANA TMUX Buffer Enabled"
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bitfld.long 0x18 13. "ANA_TMUX_BUF_BYPASS,TW ANA TMUX Buffer Bypass" "Functional Reset,ANA TMUX Buffer By-pass Enabled"
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bitfld.long 0x18 12. "VIN_EXT_CTRL,TW VIN Control from External Source" "Functional Reset,External VIN Control Enabled"
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bitfld.long 0x18 11. "VREF_EXT_CTRL,TW VREF Control from External SOurce" "Functional Reset,External VREF Control Enabled"
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bitfld.long 0x18 10. "IFORCE_EXT_CTRL,TW Iforce Control from External Source" "Functional Reset,IFORCE Control Enabled"
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bitfld.long 0x18 9. "TS_SE_INP_BUF_EN,TW ADC TS SE Inp Buffer Enable" "Functional Reset,Input Buffer Enabled"
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bitfld.long 0x18 8. "TS_DIFF_INP_BUF_EN,TW ADC TS DIFF Inp Buffer Enable" "Input Buffer disabled,Functional Reset"
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bitfld.long 0x18 5.--7. "ADC_REF_SEL_2_0,TW ADC Reference Select" "0,1,2,3,4,5,6,7"
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bitfld.long 0x18 4. "ADC_REF_BUF_EN,TW ADC Reference Buffer Enable" "Input Buffer disabled,Functional Reset"
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bitfld.long 0x18 3. "ADC_INP_BUF_EN,TW ADC Input Buffer Enable" "Input Buffer disabled,Functional Reset"
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bitfld.long 0x18 2. "ADC_RESET,TW ADC Reset (Active High)" "ADC Out of Reset,Functional Reset"
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bitfld.long 0x18 1. "ADC_START_CONV,TW ADC Start Conversion" "0,1"
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bitfld.long 0x18 0. "ADC_EN,TW ADC Control" "Functional Reset,ADC Enable"
line.long 0x1C "ANA_REG_TW_ANA_TMUX_CTRL_LOWV,"
bitfld.long 0x1C 31. "ANA_TEST_EN,TW ANA Test MUX Enabled" "Functional Reset,ANA TMUX Control Enabled"
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bitfld.long 0x1C 30. "CLK_TMUX_ESD_CTRL,CLK TMUX ESD CTRL in Pad-Frame" "0,1"
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hexmask.long.word 0x1C 19.--29. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x1C 18. "ATESTV_VSLDO,Enable Output of ATESTV of VSLDO" "0,1"
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bitfld.long 0x1C 17. "TMUX_BUF_OUT_EN,Enable Output of TMUX buffer" "0,1"
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bitfld.long 0x1C 16. "I2V_SENSE,I2V Sense Voltage of External IREF Forced" "0,1"
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bitfld.long 0x1C 15. "BIST_MUX_OUT_1P8V,BIST Mux output pre ADC input Buffer" "0,1"
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bitfld.long 0x1C 14. "ODP,Ibias current from Top Refsys for measurement on Test Pin" "0,1"
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bitfld.long 0x1C 13. "VBE_TS_WEAK,Single PNP Sense voltage for TSENSE selected" "0,1"
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bitfld.long 0x1C 12. "VBE_TS_STRONG,Multi PNP Sense voltage for TSENSE selected" "0,1"
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bitfld.long 0x1C 11. "DELVBE_BUFF_OUT,Difference TSENSE signal delVbe scaled and buffered for chosen TSENSE element" "0,1"
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bitfld.long 0x1C 10. "ADC_REF_BUF_OUT,ADC reference buffer out to Test Pin" "0,1"
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bitfld.long 0x1C 9. "ADC_BUF_OUT_1P8V,Buffered output of ADC inputs to GPADC" "0,1"
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bitfld.long 0x1C 8. "DC_BIST_BUF_INP_1P8V,DC BIST Buffered output of RX TX CLK LO (shorted on to this net)" "0,1"
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bitfld.long 0x1C 7. "VBE_W_BUFF,Buffered value of Weak PNP" "0,1"
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bitfld.long 0x1C 6. "VBE_S_BUFF,Buffered value of Strong PNP" "0,1"
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bitfld.long 0x1C 5. "PM_ANA_INP_5,CLK ANA Test Pin Mapped" "0,1"
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bitfld.long 0x1C 4. "PM_ANA_INP_4,RX ANA Test Mux Control" "0,1"
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bitfld.long 0x1C 3. "PM_ANA_INP_3,LODIST ANA Test Mux Control" "0,1"
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bitfld.long 0x1C 2. "PM_ANA_INP_2,TX PM ANA Test Mux Control" "0,1"
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bitfld.long 0x1C 1. "REFSYS_TEST_OUT_1P8V,Mux Output of Refsys Test Mux" "0,1"
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bitfld.long 0x1C 0. "WU_ANA_TEST_OUT_1P8V,Mux Output of WU Test Mux" "0,1"
line.long 0x20 "ANA_REG_TW_SPARE_LOWV,"
line.long 0x24 "ANA_REG_WU_MODE_REG_LOWV,"
hexmask.long 0x24 7.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x24 2.--6. "SOP_MODE_LAT_4_0,SOP Mode Latched Output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 1. "TEST_MODE_DET_SYNC,Latched Output of Test Mode Detect SOP" "0,1"
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bitfld.long 0x24 0. "FUNC_TEST_DET_SYNC,Latched Output of Functional Test Mode SOP" "0,1"
line.long 0x28 "ANA_REG_WU_STATUS_REG_LOWV,"
hexmask.long.word 0x28 19.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x28 18. "VDDS_3P3V_UVDET_LAT,New in TPR: Latched Value of 3.3V IO UV Detect" "UV Detect Not Triggered,UV Detect has Triggered"
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bitfld.long 0x28 17. "VDDA_OSC_UVDET_LAT,Latched value of UV detect of LOMULT 1.8V supply (AWR devices) For TPR Latched Value of UV Detect of VDDA_OSC" "UV Detect Not Triggered,UV Detect has Triggered"
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bitfld.long 0x28 16. "SUPP_OK_APLLVCO18,Supp Detect output of APLL VCO 1.8V" "Supply Not detected,Supply Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 15. "HVMODE,HVMODE Status from VMON" "1.8V VIO,3.3V VIO"
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bitfld.long 0x28 14. "LIMP_MODE_STATUS,Ref CLK status at Wake-up" "REF CLK is present,REF CLK is absent and CPU CLK Switched to RCOSC"
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bitfld.long 0x28 13. "XTAL_DET_STATUS,XTAL Detect status at Wake-up" "XTAL absent,XTAL Present"
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bitfld.long 0x28 12. "RCOSC_CLK_STATUS,RCOSC status at Wake-up" "RCOSC CLK absent,RCOSC CLK Present"
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bitfld.long 0x28 11. "REF_CLK_STATUS,Ref CLK status at Wake-up" "REF CLK absent,REF CLK Present"
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bitfld.long 0x28 10. "SUPP_OK_VDDD18,Supp Detect output of LVDS 1.8V" "Supply Not detected,Supply Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 9. "SUPP_OK_SRAM12,UV Detect Status of SRAM" "UV Not Detected,UV Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 8. "SUPP_OK_RF2_14,Supp Detect output of RF2 1.4V Pin" "Supply Not detected,Supply Detected Tied LO in TPR (Unused VMON)"
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bitfld.long 0x28 7. "SUPP_OK_RF14,Updated for 1642 ES2P0 Change name : Mux for VIN_13 OK in LDO bypass mode This output bit is always tied low Tied LO in TPR and AWR/IWR devices" "0,1"
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bitfld.long 0x28 6. "SUPP_OK_RF10,Updated for 1642 ES2P0 Change name : Mux for VIN_13 OK in LDO bypass mode When RF_LDO_BYPASS_EN = 1 this bit will be high when the supply is > 0.75 When RF_LDO_BYPASS_EN = 0 this bit will be high when the supply is > 1.05 Tied LO in TPR.." "0,1"
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bitfld.long 0x28 5. "SUPP_OK_IO33,Supp Detect output of IO 3.3V" "Supply Not detected,Supply Detected"
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bitfld.long 0x28 4. "SUPP_OK_IO18,Supp Detect output of IO 1.8V" "Supply Not detected,Supply Detected"
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bitfld.long 0x28 3. "SUPP_OK_CLK18,Supp Detect output of CLK 1.8V" "Supply Not detected,Supply Detected For TPR Crude detection of.."
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bitfld.long 0x28 2. "SUPP_OK_ANA18,Supp Detect output of Ana 1.8V Tied LO in TPR (unused VMON)" "Supply Not detected,Supply Detected"
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bitfld.long 0x28 1. "CORE_UVDET_LAT,Latched Value of UV Detect" "UV Detect Not Triggered,UV Detect has Triggered"
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bitfld.long 0x28 0. "CORE_OVDET_LAT,Latched Value of OV Detect" "OV Detect Not Triggered,OV Detect has Triggered"
line.long 0x2C "ANA_REG_WU_SPARE_OUT_LOWV,"
hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved0,Reserved Reads return 0x0 and writes have no effect"
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bitfld.long 0x2C 7. "CORE_UVDET_LOWV,UV Detect of Core Supply-Unlatched" "0,1"
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bitfld.long 0x2C 6. "CORE_OVDET_LOWV,OV Detect of Core Supply-Unlatched" "0,1"
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bitfld.long 0x2C 5. "INT_OSC_CTRL,Internal Oscillator Control" "0,1"
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bitfld.long 0x2C 4. "SUPPDET_OV_CTRL,Supply Detect Override Bit" "0,1"
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bitfld.long 0x2C 3. "HVMODE,Status of VIO supply" "0,1"
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bitfld.long 0x2C 2. "VDDS18DET,Status of 1.8V IO Bias Supply" "0,1"
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bitfld.long 0x2C 1. "VDDARF_DET,Status of 1.3V RF Supply" "0,1"
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bitfld.long 0x2C 0. "VDDCLK18DET,Status of 1.8V CLK Supply" "0,1"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "MSS_TPCC_A (MSS TPCCA Module Registers)"
base ad:0x3100000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
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bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
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bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
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bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
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bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
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bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
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bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
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bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
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hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
newline
bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
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hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
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bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
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bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
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bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
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bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
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bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
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bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
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bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
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bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
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bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
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bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
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bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
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bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
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bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
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bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
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bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
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bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
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bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
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bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
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bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
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bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
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bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
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bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
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bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
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bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
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bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
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bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
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bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
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bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
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bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
tree "MSS_TPCC_B (MSS TPCCB Module Registers)"
base ad:0x3120000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
newline
bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
newline
bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
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bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
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bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
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bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
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bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
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bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
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bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
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hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
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hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
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bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
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bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
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bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
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bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
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bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
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bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
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bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
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bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
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bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
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bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
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bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
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bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
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bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
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bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
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bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
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bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
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bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
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bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
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bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
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bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
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bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
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bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
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bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
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bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
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bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
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bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
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bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
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bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
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bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
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bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
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bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
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bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
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bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
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bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
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bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
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bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
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bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
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bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
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bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
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bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
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bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x3140000 ad:0x3160000 )
tree "MSS_TPTC_A$1 (MSS TPTC A0 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
tree "MSS_TPTC_B0 (MSS TPTC B0 Module Registers)"
base ad:0x3180000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
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bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
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bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
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bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
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bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
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bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
tree "MSS_VIM_R5A (MSS VIM CR5 CORE A)"
base ad:0x2080000
rgroup.long 0x00++0x27
line.long 0x00 "PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INFO,The Info Register gives the configuration Inforrmation of this VIM"
hexmask.long.tbyte 0x04 11.--31. 1. "RES1,RESERVE FIELD"
hexmask.long.word 0x04 0.--10. 1. "INTERRUPTS,Total number of Interrupts"
line.long 0x08 "PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ"
bitfld.long 0x08 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x08 20.--30. 1. "RES2,RESERVE FIELD"
bitfld.long 0x08 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 10.--15. "RES3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 0.--9. 1. "NUM,Number of the highest priority pending IRQ"
line.long 0x0C "PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ"
bitfld.long 0x0C 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x0C 20.--30. 1. "RES4,RESERVE FIELD"
bitfld.long 0x0C 16.--19. "PRI,Priority of the highest priority pending FIQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 10.--15. "RES5,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x0C 0.--9. 1. "NUM,Number of the highest priority pending FIQ"
line.long 0x10 "IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts"
line.long 0x14 "FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts"
line.long 0x18 "IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ"
hexmask.long 0x18 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x18 0.--1. "RES21,RESERVE FIELD" "0,1,2,3"
line.long 0x1C "FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ"
hexmask.long 0x1C 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x1C 0.--1. "RES22,RESERVE FIELD" "0,1,2,3"
line.long 0x20 "ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ"
bitfld.long 0x20 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x20 20.--30. 1. "RES6,RESERVE FIELD"
bitfld.long 0x20 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 10.--15. "RES7,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "NUM,Number of the currently active IRQ"
line.long 0x24 "ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ"
bitfld.long 0x24 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x24 20.--30. 1. "RES8,RESERVE FIELD"
bitfld.long 0x24 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 10.--15. "RES9,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x24 0.--9. 1. "NUM,Number of the currently active FIQ"
group.long 0x30++0x03
line.long 0x00 "DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ"
hexmask.long 0x00 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x00 0.--1. "RES23,RESERVE FIELD" "0,1,2,3"
group.long 0x400++0xFF
line.long 0x00 "RAW,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x04 "STS,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x08 "INTR_EN_SET,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x0C "INTER_EN_CLR,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x10 "IRQSTS,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x14 "FIQSTS,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x18 "INTMAP,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x1C "INTTYPE,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x20 "RAW_1,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x24 "STS_1,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x28 "INTR_EN_SET_1,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x2C "INTER_EN_CLR_1,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x30 "IRQSTS_1,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x34 "FIQSTS_1,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x38 "INTMAP_1,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x3C "INTTYPE_1,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x40 "RAW_2,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x44 "STS_2,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x48 "INTR_EN_SET_2,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x4C "INTER_EN_CLR_2,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x50 "IRQSTS_2,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x54 "FIQSTS_2,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x58 "INTMAP_2,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x5C "INTTYPE_2,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x60 "RAW_3,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x64 "STS_3,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x68 "INTR_EN_SET_3,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x6C "INTER_EN_CLR_3,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x70 "IRQSTS_3,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x74 "FIQSTS_3,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x78 "INTMAP_3,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x7C "INTTYPE_3,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x80 "RAW_4,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x84 "STS_4,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x88 "INTR_EN_SET_4,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x8C "INTER_EN_CLR_4,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x90 "IRQSTS_4,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x94 "FIQSTS_4,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x98 "INTMAP_4,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x9C "INTTYPE_4,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xA0 "RAW_5,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xA4 "STS_5,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xA8 "INTR_EN_SET_5,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xAC "INTER_EN_CLR_5,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xB0 "IRQSTS_5,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xB4 "FIQSTS_5,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xB8 "INTMAP_5,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xBC "INTTYPE_5,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xC0 "RAW_6,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xC4 "STS_6,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xC8 "INTR_EN_SET_6,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xCC "INTER_EN_CLR_6,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xD0 "IRQSTS_6,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xD4 "FIQSTS_6,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xD8 "INTMAP_6,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xDC "INTTYPE_6,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xE0 "RAW_7,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xE4 "STS_7,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xE8 "INTR_EN_SET_7,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xEC "INTER_EN_CLR_7,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xF0 "IRQSTS_7,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xF4 "FIQSTS_7,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xF8 "INTMAP_7,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xFC "INTTYPE_7,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
group.long 0x1000++0x3FF
line.long 0x00 "INTPRIORITY,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h4"
hexmask.long 0x00 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x00 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTPRIORITY_1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
hexmask.long 0x04 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x04 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "INTPRIORITY_2,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h6"
hexmask.long 0x08 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x08 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "INTPRIORITY_3,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h7"
hexmask.long 0x0C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x0C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "INTPRIORITY_4,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h8"
hexmask.long 0x10 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "INTPRIORITY_5,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h9"
hexmask.long 0x14 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "INTPRIORITY_6,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h10"
hexmask.long 0x18 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "INTPRIORITY_7,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h11"
hexmask.long 0x1C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "INTPRIORITY_8,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h12"
hexmask.long 0x20 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "INTPRIORITY_9,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h13"
hexmask.long 0x24 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "INTPRIORITY_10,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h14"
hexmask.long 0x28 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "INTPRIORITY_11,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h15"
hexmask.long 0x2C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "INTPRIORITY_12,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h16"
hexmask.long 0x30 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "INTPRIORITY_13,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h17"
hexmask.long 0x34 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "INTPRIORITY_14,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h18"
hexmask.long 0x38 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "INTPRIORITY_15,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h19"
hexmask.long 0x3C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "INTPRIORITY_16,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h20"
hexmask.long 0x40 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x40 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "INTPRIORITY_17,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h21"
hexmask.long 0x44 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x44 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "INTPRIORITY_18,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h22"
hexmask.long 0x48 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x48 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "INTPRIORITY_19,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h23"
hexmask.long 0x4C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x4C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "INTPRIORITY_20,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h24"
hexmask.long 0x50 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x50 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "INTPRIORITY_21,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h25"
hexmask.long 0x54 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x54 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "INTPRIORITY_22,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h26"
hexmask.long 0x58 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x58 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "INTPRIORITY_23,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h27"
hexmask.long 0x5C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x5C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x60 "INTPRIORITY_24,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h28"
hexmask.long 0x60 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x60 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "INTPRIORITY_25,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h29"
hexmask.long 0x64 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x64 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "INTPRIORITY_26,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h30"
hexmask.long 0x68 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x68 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "INTPRIORITY_27,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h31"
hexmask.long 0x6C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x6C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "INTPRIORITY_28,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h32"
hexmask.long 0x70 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x70 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x74 "INTPRIORITY_29,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h33"
hexmask.long 0x74 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x74 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x78 "INTPRIORITY_30,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h34"
hexmask.long 0x78 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x78 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x7C "INTPRIORITY_31,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h35"
hexmask.long 0x7C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x7C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x80 "INTPRIORITY_32,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h36"
hexmask.long 0x80 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x80 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "INTPRIORITY_33,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h37"
hexmask.long 0x84 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x84 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "INTPRIORITY_34,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h38"
hexmask.long 0x88 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x88 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "INTPRIORITY_35,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h39"
hexmask.long 0x8C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x8C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "INTPRIORITY_36,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h40"
hexmask.long 0x90 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x90 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x94 "INTPRIORITY_37,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h41"
hexmask.long 0x94 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x94 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x98 "INTPRIORITY_38,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h42"
hexmask.long 0x98 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x98 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "INTPRIORITY_39,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h43"
hexmask.long 0x9C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x9C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA0 "INTPRIORITY_40,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h44"
hexmask.long 0xA0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "INTPRIORITY_41,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h45"
hexmask.long 0xA4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA8 "INTPRIORITY_42,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h46"
hexmask.long 0xA8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xAC "INTPRIORITY_43,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h47"
hexmask.long 0xAC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xAC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB0 "INTPRIORITY_44,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h48"
hexmask.long 0xB0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB4 "INTPRIORITY_45,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h49"
hexmask.long 0xB4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "INTPRIORITY_46,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h50"
hexmask.long 0xB8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xBC "INTPRIORITY_47,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h51"
hexmask.long 0xBC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xBC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC0 "INTPRIORITY_48,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h52"
hexmask.long 0xC0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "INTPRIORITY_49,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h53"
hexmask.long 0xC4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "INTPRIORITY_50,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h54"
hexmask.long 0xC8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "INTPRIORITY_51,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h55"
hexmask.long 0xCC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xCC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD0 "INTPRIORITY_52,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h56"
hexmask.long 0xD0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "INTPRIORITY_53,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h57"
hexmask.long 0xD4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD8 "INTPRIORITY_54,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h58"
hexmask.long 0xD8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "INTPRIORITY_55,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h59"
hexmask.long 0xDC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xDC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE0 "INTPRIORITY_56,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h60"
hexmask.long 0xE0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "INTPRIORITY_57,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h61"
hexmask.long 0xE4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE8 "INTPRIORITY_58,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h62"
hexmask.long 0xE8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "INTPRIORITY_59,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h63"
hexmask.long 0xEC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xEC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF0 "INTPRIORITY_60,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h64"
hexmask.long 0xF0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "INTPRIORITY_61,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h65"
hexmask.long 0xF4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF8 "INTPRIORITY_62,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h66"
hexmask.long 0xF8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "INTPRIORITY_63,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h67"
hexmask.long 0xFC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xFC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x100 "INTPRIORITY_64,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h68"
hexmask.long 0x100 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x100 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "INTPRIORITY_65,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h69"
hexmask.long 0x104 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x104 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x108 "INTPRIORITY_66,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h70"
hexmask.long 0x108 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x108 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10C "INTPRIORITY_67,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h71"
hexmask.long 0x10C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x110 "INTPRIORITY_68,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h72"
hexmask.long 0x110 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x110 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x114 "INTPRIORITY_69,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h73"
hexmask.long 0x114 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x114 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x118 "INTPRIORITY_70,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h74"
hexmask.long 0x118 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x118 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x11C "INTPRIORITY_71,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h75"
hexmask.long 0x11C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x11C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x120 "INTPRIORITY_72,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h76"
hexmask.long 0x120 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x120 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "INTPRIORITY_73,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h77"
hexmask.long 0x124 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x124 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x128 "INTPRIORITY_74,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h78"
hexmask.long 0x128 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x128 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x12C "INTPRIORITY_75,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h79"
hexmask.long 0x12C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x12C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x130 "INTPRIORITY_76,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h80"
hexmask.long 0x130 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x130 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x134 "INTPRIORITY_77,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h81"
hexmask.long 0x134 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x134 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x138 "INTPRIORITY_78,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h82"
hexmask.long 0x138 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x138 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x13C "INTPRIORITY_79,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h83"
hexmask.long 0x13C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x13C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x140 "INTPRIORITY_80,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h84"
hexmask.long 0x140 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x140 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "INTPRIORITY_81,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h85"
hexmask.long 0x144 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x144 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x148 "INTPRIORITY_82,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h86"
hexmask.long 0x148 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x148 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14C "INTPRIORITY_83,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h87"
hexmask.long 0x14C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x150 "INTPRIORITY_84,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h88"
hexmask.long 0x150 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x150 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x154 "INTPRIORITY_85,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h89"
hexmask.long 0x154 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x154 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x158 "INTPRIORITY_86,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h90"
hexmask.long 0x158 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x158 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x15C "INTPRIORITY_87,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h91"
hexmask.long 0x15C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x15C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x160 "INTPRIORITY_88,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h92"
hexmask.long 0x160 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x160 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "INTPRIORITY_89,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h93"
hexmask.long 0x164 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x164 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x168 "INTPRIORITY_90,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h94"
hexmask.long 0x168 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x168 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "INTPRIORITY_91,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h95"
hexmask.long 0x16C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x16C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x170 "INTPRIORITY_92,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h96"
hexmask.long 0x170 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x170 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "INTPRIORITY_93,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h97"
hexmask.long 0x174 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x174 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x178 "INTPRIORITY_94,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h98"
hexmask.long 0x178 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x178 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "INTPRIORITY_95,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h99"
hexmask.long 0x17C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x17C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x180 "INTPRIORITY_96,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h100"
hexmask.long 0x180 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x180 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "INTPRIORITY_97,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h101"
hexmask.long 0x184 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x184 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x188 "INTPRIORITY_98,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h102"
hexmask.long 0x188 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x188 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "INTPRIORITY_99,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h103"
hexmask.long 0x18C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "INTPRIORITY_100,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h104"
hexmask.long 0x190 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x190 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "INTPRIORITY_101,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h105"
hexmask.long 0x194 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x194 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x198 "INTPRIORITY_102,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h106"
hexmask.long 0x198 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x198 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "INTPRIORITY_103,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h107"
hexmask.long 0x19C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x19C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "INTPRIORITY_104,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h108"
hexmask.long 0x1A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "INTPRIORITY_105,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h109"
hexmask.long 0x1A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "INTPRIORITY_106,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h110"
hexmask.long 0x1A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "INTPRIORITY_107,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h111"
hexmask.long 0x1AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "INTPRIORITY_108,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h112"
hexmask.long 0x1B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "INTPRIORITY_109,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h113"
hexmask.long 0x1B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B8 "INTPRIORITY_110,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h114"
hexmask.long 0x1B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "INTPRIORITY_111,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h115"
hexmask.long 0x1BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C0 "INTPRIORITY_112,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h116"
hexmask.long 0x1C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "INTPRIORITY_113,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h117"
hexmask.long 0x1C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C8 "INTPRIORITY_114,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h118"
hexmask.long 0x1C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "INTPRIORITY_115,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h119"
hexmask.long 0x1CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "INTPRIORITY_116,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h120"
hexmask.long 0x1D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "INTPRIORITY_117,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h121"
hexmask.long 0x1D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D8 "INTPRIORITY_118,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h122"
hexmask.long 0x1D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "INTPRIORITY_119,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h123"
hexmask.long 0x1DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E0 "INTPRIORITY_120,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h124"
hexmask.long 0x1E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "INTPRIORITY_121,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h125"
hexmask.long 0x1E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E8 "INTPRIORITY_122,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h126"
hexmask.long 0x1E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1EC "INTPRIORITY_123,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h127"
hexmask.long 0x1EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F0 "INTPRIORITY_124,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h128"
hexmask.long 0x1F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F4 "INTPRIORITY_125,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h129"
hexmask.long 0x1F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F8 "INTPRIORITY_126,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h130"
hexmask.long 0x1F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1FC "INTPRIORITY_127,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h131"
hexmask.long 0x1FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x200 "INTPRIORITY_128,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h132"
hexmask.long 0x200 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x200 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x204 "INTPRIORITY_129,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h133"
hexmask.long 0x204 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x204 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x208 "INTPRIORITY_130,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h134"
hexmask.long 0x208 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x208 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20C "INTPRIORITY_131,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h135"
hexmask.long 0x20C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "INTPRIORITY_132,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h136"
hexmask.long 0x210 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x210 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x214 "INTPRIORITY_133,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h137"
hexmask.long 0x214 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x214 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x218 "INTPRIORITY_134,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h138"
hexmask.long 0x218 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x218 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x21C "INTPRIORITY_135,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h139"
hexmask.long 0x21C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x21C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x220 "INTPRIORITY_136,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h140"
hexmask.long 0x220 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x220 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x224 "INTPRIORITY_137,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h141"
hexmask.long 0x224 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x224 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x228 "INTPRIORITY_138,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h142"
hexmask.long 0x228 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x228 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x22C "INTPRIORITY_139,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h143"
hexmask.long 0x22C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x22C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x230 "INTPRIORITY_140,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h144"
hexmask.long 0x230 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x230 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x234 "INTPRIORITY_141,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h145"
hexmask.long 0x234 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x234 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x238 "INTPRIORITY_142,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h146"
hexmask.long 0x238 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x238 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x23C "INTPRIORITY_143,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h147"
hexmask.long 0x23C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x23C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x240 "INTPRIORITY_144,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h148"
hexmask.long 0x240 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x240 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x244 "INTPRIORITY_145,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h149"
hexmask.long 0x244 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x244 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x248 "INTPRIORITY_146,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h150"
hexmask.long 0x248 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x248 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24C "INTPRIORITY_147,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h151"
hexmask.long 0x24C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x250 "INTPRIORITY_148,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h152"
hexmask.long 0x250 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x250 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x254 "INTPRIORITY_149,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h153"
hexmask.long 0x254 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x254 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x258 "INTPRIORITY_150,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h154"
hexmask.long 0x258 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x258 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x25C "INTPRIORITY_151,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h155"
hexmask.long 0x25C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x25C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x260 "INTPRIORITY_152,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h156"
hexmask.long 0x260 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x260 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x264 "INTPRIORITY_153,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h157"
hexmask.long 0x264 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x264 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x268 "INTPRIORITY_154,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h158"
hexmask.long 0x268 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x268 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x26C "INTPRIORITY_155,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h159"
hexmask.long 0x26C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x26C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x270 "INTPRIORITY_156,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h160"
hexmask.long 0x270 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x270 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x274 "INTPRIORITY_157,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h161"
hexmask.long 0x274 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x274 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x278 "INTPRIORITY_158,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h162"
hexmask.long 0x278 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x278 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x27C "INTPRIORITY_159,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h163"
hexmask.long 0x27C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x27C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x280 "INTPRIORITY_160,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h164"
hexmask.long 0x280 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x280 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x284 "INTPRIORITY_161,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h165"
hexmask.long 0x284 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x284 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x288 "INTPRIORITY_162,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h166"
hexmask.long 0x288 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x288 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28C "INTPRIORITY_163,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h167"
hexmask.long 0x28C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x290 "INTPRIORITY_164,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h168"
hexmask.long 0x290 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x290 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x294 "INTPRIORITY_165,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h169"
hexmask.long 0x294 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x294 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x298 "INTPRIORITY_166,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h170"
hexmask.long 0x298 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x298 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x29C "INTPRIORITY_167,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h171"
hexmask.long 0x29C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x29C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A0 "INTPRIORITY_168,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h172"
hexmask.long 0x2A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A4 "INTPRIORITY_169,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h173"
hexmask.long 0x2A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A8 "INTPRIORITY_170,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h174"
hexmask.long 0x2A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2AC "INTPRIORITY_171,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h175"
hexmask.long 0x2AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B0 "INTPRIORITY_172,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h176"
hexmask.long 0x2B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B4 "INTPRIORITY_173,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h177"
hexmask.long 0x2B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B8 "INTPRIORITY_174,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h178"
hexmask.long 0x2B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2BC "INTPRIORITY_175,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h179"
hexmask.long 0x2BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C0 "INTPRIORITY_176,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h180"
hexmask.long 0x2C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C4 "INTPRIORITY_177,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h181"
hexmask.long 0x2C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C8 "INTPRIORITY_178,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h182"
hexmask.long 0x2C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2CC "INTPRIORITY_179,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h183"
hexmask.long 0x2CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D0 "INTPRIORITY_180,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h184"
hexmask.long 0x2D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D4 "INTPRIORITY_181,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h185"
hexmask.long 0x2D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D8 "INTPRIORITY_182,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h186"
hexmask.long 0x2D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2DC "INTPRIORITY_183,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h187"
hexmask.long 0x2DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E0 "INTPRIORITY_184,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h188"
hexmask.long 0x2E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E4 "INTPRIORITY_185,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h189"
hexmask.long 0x2E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E8 "INTPRIORITY_186,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h190"
hexmask.long 0x2E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2EC "INTPRIORITY_187,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h191"
hexmask.long 0x2EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F0 "INTPRIORITY_188,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h192"
hexmask.long 0x2F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F4 "INTPRIORITY_189,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h193"
hexmask.long 0x2F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F8 "INTPRIORITY_190,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h194"
hexmask.long 0x2F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2FC "INTPRIORITY_191,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h195"
hexmask.long 0x2FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x300 "INTPRIORITY_192,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h196"
hexmask.long 0x300 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x300 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x304 "INTPRIORITY_193,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h197"
hexmask.long 0x304 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x304 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x308 "INTPRIORITY_194,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h198"
hexmask.long 0x308 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x308 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30C "INTPRIORITY_195,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h199"
hexmask.long 0x30C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x310 "INTPRIORITY_196,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h200"
hexmask.long 0x310 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x310 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x314 "INTPRIORITY_197,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h201"
hexmask.long 0x314 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x314 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x318 "INTPRIORITY_198,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h202"
hexmask.long 0x318 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x318 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x31C "INTPRIORITY_199,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h203"
hexmask.long 0x31C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x31C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x320 "INTPRIORITY_200,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h204"
hexmask.long 0x320 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x320 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x324 "INTPRIORITY_201,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h205"
hexmask.long 0x324 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x324 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x328 "INTPRIORITY_202,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h206"
hexmask.long 0x328 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x328 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x32C "INTPRIORITY_203,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h207"
hexmask.long 0x32C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x32C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x330 "INTPRIORITY_204,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h208"
hexmask.long 0x330 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x330 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x334 "INTPRIORITY_205,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h209"
hexmask.long 0x334 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x334 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x338 "INTPRIORITY_206,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h210"
hexmask.long 0x338 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x338 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x33C "INTPRIORITY_207,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h211"
hexmask.long 0x33C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x33C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x340 "INTPRIORITY_208,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h212"
hexmask.long 0x340 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x340 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x344 "INTPRIORITY_209,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h213"
hexmask.long 0x344 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x344 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x348 "INTPRIORITY_210,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h214"
hexmask.long 0x348 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x348 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34C "INTPRIORITY_211,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h215"
hexmask.long 0x34C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x350 "INTPRIORITY_212,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h216"
hexmask.long 0x350 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x350 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x354 "INTPRIORITY_213,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h217"
hexmask.long 0x354 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x354 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x358 "INTPRIORITY_214,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h218"
hexmask.long 0x358 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x358 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x35C "INTPRIORITY_215,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h219"
hexmask.long 0x35C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x35C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x360 "INTPRIORITY_216,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h220"
hexmask.long 0x360 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x360 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x364 "INTPRIORITY_217,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h221"
hexmask.long 0x364 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x364 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x368 "INTPRIORITY_218,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h222"
hexmask.long 0x368 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x368 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x36C "INTPRIORITY_219,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h223"
hexmask.long 0x36C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x36C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x370 "INTPRIORITY_220,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h224"
hexmask.long 0x370 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x370 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x374 "INTPRIORITY_221,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h225"
hexmask.long 0x374 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x374 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x378 "INTPRIORITY_222,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h226"
hexmask.long 0x378 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x378 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x37C "INTPRIORITY_223,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h227"
hexmask.long 0x37C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x37C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x380 "INTPRIORITY_224,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h228"
hexmask.long 0x380 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x380 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x384 "INTPRIORITY_225,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h229"
hexmask.long 0x384 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x384 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x388 "INTPRIORITY_226,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h230"
hexmask.long 0x388 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x388 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38C "INTPRIORITY_227,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h231"
hexmask.long 0x38C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x390 "INTPRIORITY_228,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h232"
hexmask.long 0x390 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x390 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x394 "INTPRIORITY_229,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h233"
hexmask.long 0x394 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x394 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x398 "INTPRIORITY_230,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h234"
hexmask.long 0x398 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x398 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x39C "INTPRIORITY_231,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h235"
hexmask.long 0x39C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x39C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A0 "INTPRIORITY_232,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h236"
hexmask.long 0x3A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A4 "INTPRIORITY_233,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h237"
hexmask.long 0x3A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A8 "INTPRIORITY_234,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h238"
hexmask.long 0x3A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3AC "INTPRIORITY_235,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h239"
hexmask.long 0x3AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B0 "INTPRIORITY_236,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h240"
hexmask.long 0x3B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B4 "INTPRIORITY_237,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h241"
hexmask.long 0x3B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B8 "INTPRIORITY_238,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h242"
hexmask.long 0x3B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3BC "INTPRIORITY_239,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h243"
hexmask.long 0x3BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C0 "INTPRIORITY_240,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h244"
hexmask.long 0x3C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C4 "INTPRIORITY_241,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h245"
hexmask.long 0x3C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C8 "INTPRIORITY_242,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h246"
hexmask.long 0x3C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3CC "INTPRIORITY_243,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h247"
hexmask.long 0x3CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D0 "INTPRIORITY_244,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h248"
hexmask.long 0x3D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D4 "INTPRIORITY_245,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h249"
hexmask.long 0x3D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D8 "INTPRIORITY_246,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h250"
hexmask.long 0x3D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3DC "INTPRIORITY_247,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h251"
hexmask.long 0x3DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E0 "INTPRIORITY_248,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h252"
hexmask.long 0x3E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E4 "INTPRIORITY_249,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h253"
hexmask.long 0x3E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E8 "INTPRIORITY_250,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h254"
hexmask.long 0x3E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3EC "INTPRIORITY_251,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h255"
hexmask.long 0x3EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F0 "INTPRIORITY_252,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h256"
hexmask.long 0x3F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F4 "INTPRIORITY_253,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h257"
hexmask.long 0x3F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F8 "INTPRIORITY_254,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h258"
hexmask.long 0x3F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3FC "INTPRIORITY_255,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h259"
hexmask.long 0x3FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x3FF
line.long 0x00 "INTVECTOR,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h4"
hexmask.long 0x00 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x00 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x04 "INTVECTOR_1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
hexmask.long 0x04 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x04 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x08 "INTVECTOR_2,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h6"
hexmask.long 0x08 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x08 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x0C "INTVECTOR_3,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h7"
hexmask.long 0x0C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x0C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10 "INTVECTOR_4,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h8"
hexmask.long 0x10 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14 "INTVECTOR_5,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h9"
hexmask.long 0x14 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18 "INTVECTOR_6,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h10"
hexmask.long 0x18 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C "INTVECTOR_7,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h11"
hexmask.long 0x1C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20 "INTVECTOR_8,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h12"
hexmask.long 0x20 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24 "INTVECTOR_9,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h13"
hexmask.long 0x24 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28 "INTVECTOR_10,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h14"
hexmask.long 0x28 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C "INTVECTOR_11,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h15"
hexmask.long 0x2C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30 "INTVECTOR_12,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h16"
hexmask.long 0x30 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34 "INTVECTOR_13,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h17"
hexmask.long 0x34 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38 "INTVECTOR_14,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h18"
hexmask.long 0x38 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C "INTVECTOR_15,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h19"
hexmask.long 0x3C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x40 "INTVECTOR_16,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h20"
hexmask.long 0x40 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x40 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x44 "INTVECTOR_17,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h21"
hexmask.long 0x44 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x44 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x48 "INTVECTOR_18,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h22"
hexmask.long 0x48 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x48 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x4C "INTVECTOR_19,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h23"
hexmask.long 0x4C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x4C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x50 "INTVECTOR_20,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h24"
hexmask.long 0x50 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x50 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x54 "INTVECTOR_21,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h25"
hexmask.long 0x54 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x54 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x58 "INTVECTOR_22,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h26"
hexmask.long 0x58 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x58 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x5C "INTVECTOR_23,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h27"
hexmask.long 0x5C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x5C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x60 "INTVECTOR_24,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h28"
hexmask.long 0x60 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x60 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x64 "INTVECTOR_25,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h29"
hexmask.long 0x64 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x64 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x68 "INTVECTOR_26,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h30"
hexmask.long 0x68 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x68 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x6C "INTVECTOR_27,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h31"
hexmask.long 0x6C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x6C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x70 "INTVECTOR_28,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h32"
hexmask.long 0x70 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x70 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x74 "INTVECTOR_29,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h33"
hexmask.long 0x74 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x74 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x78 "INTVECTOR_30,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h34"
hexmask.long 0x78 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x78 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x7C "INTVECTOR_31,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h35"
hexmask.long 0x7C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x7C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x80 "INTVECTOR_32,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h36"
hexmask.long 0x80 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x80 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x84 "INTVECTOR_33,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h37"
hexmask.long 0x84 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x84 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x88 "INTVECTOR_34,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h38"
hexmask.long 0x88 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x88 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x8C "INTVECTOR_35,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h39"
hexmask.long 0x8C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x8C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x90 "INTVECTOR_36,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h40"
hexmask.long 0x90 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x90 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x94 "INTVECTOR_37,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h41"
hexmask.long 0x94 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x94 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x98 "INTVECTOR_38,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h42"
hexmask.long 0x98 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x98 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x9C "INTVECTOR_39,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h43"
hexmask.long 0x9C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x9C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA0 "INTVECTOR_40,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h44"
hexmask.long 0xA0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA4 "INTVECTOR_41,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h45"
hexmask.long 0xA4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA8 "INTVECTOR_42,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h46"
hexmask.long 0xA8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xAC "INTVECTOR_43,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h47"
hexmask.long 0xAC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xAC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB0 "INTVECTOR_44,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h48"
hexmask.long 0xB0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB4 "INTVECTOR_45,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h49"
hexmask.long 0xB4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB8 "INTVECTOR_46,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h50"
hexmask.long 0xB8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xBC "INTVECTOR_47,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h51"
hexmask.long 0xBC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xBC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC0 "INTVECTOR_48,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h52"
hexmask.long 0xC0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC4 "INTVECTOR_49,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h53"
hexmask.long 0xC4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC8 "INTVECTOR_50,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h54"
hexmask.long 0xC8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xCC "INTVECTOR_51,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h55"
hexmask.long 0xCC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xCC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD0 "INTVECTOR_52,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h56"
hexmask.long 0xD0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD4 "INTVECTOR_53,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h57"
hexmask.long 0xD4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD8 "INTVECTOR_54,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h58"
hexmask.long 0xD8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xDC "INTVECTOR_55,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h59"
hexmask.long 0xDC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xDC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE0 "INTVECTOR_56,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h60"
hexmask.long 0xE0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE4 "INTVECTOR_57,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h61"
hexmask.long 0xE4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE8 "INTVECTOR_58,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h62"
hexmask.long 0xE8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xEC "INTVECTOR_59,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h63"
hexmask.long 0xEC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xEC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF0 "INTVECTOR_60,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h64"
hexmask.long 0xF0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF4 "INTVECTOR_61,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h65"
hexmask.long 0xF4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF8 "INTVECTOR_62,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h66"
hexmask.long 0xF8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xFC "INTVECTOR_63,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h67"
hexmask.long 0xFC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xFC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x100 "INTVECTOR_64,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h68"
hexmask.long 0x100 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x100 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x104 "INTVECTOR_65,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h69"
hexmask.long 0x104 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x104 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x108 "INTVECTOR_66,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h70"
hexmask.long 0x108 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x108 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10C "INTVECTOR_67,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h71"
hexmask.long 0x10C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x110 "INTVECTOR_68,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h72"
hexmask.long 0x110 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x110 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x114 "INTVECTOR_69,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h73"
hexmask.long 0x114 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x114 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x118 "INTVECTOR_70,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h74"
hexmask.long 0x118 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x118 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x11C "INTVECTOR_71,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h75"
hexmask.long 0x11C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x11C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x120 "INTVECTOR_72,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h76"
hexmask.long 0x120 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x120 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x124 "INTVECTOR_73,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h77"
hexmask.long 0x124 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x124 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x128 "INTVECTOR_74,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h78"
hexmask.long 0x128 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x128 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x12C "INTVECTOR_75,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h79"
hexmask.long 0x12C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x12C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x130 "INTVECTOR_76,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h80"
hexmask.long 0x130 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x130 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x134 "INTVECTOR_77,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h81"
hexmask.long 0x134 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x134 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x138 "INTVECTOR_78,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h82"
hexmask.long 0x138 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x138 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x13C "INTVECTOR_79,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h83"
hexmask.long 0x13C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x13C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x140 "INTVECTOR_80,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h84"
hexmask.long 0x140 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x140 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x144 "INTVECTOR_81,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h85"
hexmask.long 0x144 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x144 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x148 "INTVECTOR_82,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h86"
hexmask.long 0x148 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x148 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14C "INTVECTOR_83,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h87"
hexmask.long 0x14C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x150 "INTVECTOR_84,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h88"
hexmask.long 0x150 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x150 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x154 "INTVECTOR_85,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h89"
hexmask.long 0x154 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x154 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x158 "INTVECTOR_86,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h90"
hexmask.long 0x158 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x158 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x15C "INTVECTOR_87,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h91"
hexmask.long 0x15C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x15C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x160 "INTVECTOR_88,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h92"
hexmask.long 0x160 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x160 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x164 "INTVECTOR_89,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h93"
hexmask.long 0x164 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x164 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x168 "INTVECTOR_90,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h94"
hexmask.long 0x168 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x168 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x16C "INTVECTOR_91,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h95"
hexmask.long 0x16C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x16C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x170 "INTVECTOR_92,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h96"
hexmask.long 0x170 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x170 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x174 "INTVECTOR_93,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h97"
hexmask.long 0x174 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x174 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x178 "INTVECTOR_94,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h98"
hexmask.long 0x178 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x178 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x17C "INTVECTOR_95,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h99"
hexmask.long 0x17C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x17C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x180 "INTVECTOR_96,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h100"
hexmask.long 0x180 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x180 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x184 "INTVECTOR_97,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h101"
hexmask.long 0x184 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x184 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x188 "INTVECTOR_98,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h102"
hexmask.long 0x188 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x188 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18C "INTVECTOR_99,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h103"
hexmask.long 0x18C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x190 "INTVECTOR_100,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h104"
hexmask.long 0x190 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x190 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x194 "INTVECTOR_101,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h105"
hexmask.long 0x194 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x194 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x198 "INTVECTOR_102,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h106"
hexmask.long 0x198 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x198 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x19C "INTVECTOR_103,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h107"
hexmask.long 0x19C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x19C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A0 "INTVECTOR_104,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h108"
hexmask.long 0x1A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A4 "INTVECTOR_105,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h109"
hexmask.long 0x1A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A8 "INTVECTOR_106,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h110"
hexmask.long 0x1A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1AC "INTVECTOR_107,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h111"
hexmask.long 0x1AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B0 "INTVECTOR_108,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h112"
hexmask.long 0x1B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B4 "INTVECTOR_109,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h113"
hexmask.long 0x1B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B8 "INTVECTOR_110,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h114"
hexmask.long 0x1B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1BC "INTVECTOR_111,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h115"
hexmask.long 0x1BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C0 "INTVECTOR_112,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h116"
hexmask.long 0x1C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C4 "INTVECTOR_113,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h117"
hexmask.long 0x1C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C8 "INTVECTOR_114,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h118"
hexmask.long 0x1C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1CC "INTVECTOR_115,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h119"
hexmask.long 0x1CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D0 "INTVECTOR_116,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h120"
hexmask.long 0x1D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D4 "INTVECTOR_117,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h121"
hexmask.long 0x1D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D8 "INTVECTOR_118,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h122"
hexmask.long 0x1D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1DC "INTVECTOR_119,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h123"
hexmask.long 0x1DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E0 "INTVECTOR_120,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h124"
hexmask.long 0x1E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E4 "INTVECTOR_121,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h125"
hexmask.long 0x1E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E8 "INTVECTOR_122,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h126"
hexmask.long 0x1E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1EC "INTVECTOR_123,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h127"
hexmask.long 0x1EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F0 "INTVECTOR_124,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h128"
hexmask.long 0x1F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F4 "INTVECTOR_125,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h129"
hexmask.long 0x1F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F8 "INTVECTOR_126,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h130"
hexmask.long 0x1F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1FC "INTVECTOR_127,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h131"
hexmask.long 0x1FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x200 "INTVECTOR_128,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h132"
hexmask.long 0x200 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x200 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x204 "INTVECTOR_129,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h133"
hexmask.long 0x204 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x204 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x208 "INTVECTOR_130,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h134"
hexmask.long 0x208 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x208 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20C "INTVECTOR_131,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h135"
hexmask.long 0x20C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x210 "INTVECTOR_132,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h136"
hexmask.long 0x210 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x210 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x214 "INTVECTOR_133,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h137"
hexmask.long 0x214 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x214 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x218 "INTVECTOR_134,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h138"
hexmask.long 0x218 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x218 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x21C "INTVECTOR_135,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h139"
hexmask.long 0x21C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x21C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x220 "INTVECTOR_136,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h140"
hexmask.long 0x220 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x220 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x224 "INTVECTOR_137,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h141"
hexmask.long 0x224 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x224 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x228 "INTVECTOR_138,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h142"
hexmask.long 0x228 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x228 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x22C "INTVECTOR_139,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h143"
hexmask.long 0x22C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x22C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x230 "INTVECTOR_140,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h144"
hexmask.long 0x230 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x230 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x234 "INTVECTOR_141,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h145"
hexmask.long 0x234 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x234 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x238 "INTVECTOR_142,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h146"
hexmask.long 0x238 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x238 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x23C "INTVECTOR_143,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h147"
hexmask.long 0x23C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x23C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x240 "INTVECTOR_144,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h148"
hexmask.long 0x240 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x240 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x244 "INTVECTOR_145,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h149"
hexmask.long 0x244 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x244 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x248 "INTVECTOR_146,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h150"
hexmask.long 0x248 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x248 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24C "INTVECTOR_147,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h151"
hexmask.long 0x24C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x250 "INTVECTOR_148,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h152"
hexmask.long 0x250 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x250 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x254 "INTVECTOR_149,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h153"
hexmask.long 0x254 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x254 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x258 "INTVECTOR_150,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h154"
hexmask.long 0x258 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x258 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x25C "INTVECTOR_151,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h155"
hexmask.long 0x25C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x25C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x260 "INTVECTOR_152,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h156"
hexmask.long 0x260 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x260 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x264 "INTVECTOR_153,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h157"
hexmask.long 0x264 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x264 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x268 "INTVECTOR_154,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h158"
hexmask.long 0x268 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x268 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x26C "INTVECTOR_155,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h159"
hexmask.long 0x26C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x26C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x270 "INTVECTOR_156,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h160"
hexmask.long 0x270 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x270 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x274 "INTVECTOR_157,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h161"
hexmask.long 0x274 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x274 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x278 "INTVECTOR_158,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h162"
hexmask.long 0x278 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x278 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x27C "INTVECTOR_159,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h163"
hexmask.long 0x27C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x27C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x280 "INTVECTOR_160,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h164"
hexmask.long 0x280 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x280 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x284 "INTVECTOR_161,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h165"
hexmask.long 0x284 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x284 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x288 "INTVECTOR_162,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h166"
hexmask.long 0x288 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x288 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28C "INTVECTOR_163,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h167"
hexmask.long 0x28C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x290 "INTVECTOR_164,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h168"
hexmask.long 0x290 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x290 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x294 "INTVECTOR_165,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h169"
hexmask.long 0x294 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x294 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x298 "INTVECTOR_166,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h170"
hexmask.long 0x298 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x298 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x29C "INTVECTOR_167,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h171"
hexmask.long 0x29C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x29C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A0 "INTVECTOR_168,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h172"
hexmask.long 0x2A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A4 "INTVECTOR_169,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h173"
hexmask.long 0x2A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A8 "INTVECTOR_170,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h174"
hexmask.long 0x2A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2AC "INTVECTOR_171,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h175"
hexmask.long 0x2AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B0 "INTVECTOR_172,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h176"
hexmask.long 0x2B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B4 "INTVECTOR_173,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h177"
hexmask.long 0x2B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B8 "INTVECTOR_174,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h178"
hexmask.long 0x2B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2BC "INTVECTOR_175,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h179"
hexmask.long 0x2BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C0 "INTVECTOR_176,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h180"
hexmask.long 0x2C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C4 "INTVECTOR_177,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h181"
hexmask.long 0x2C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C8 "INTVECTOR_178,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h182"
hexmask.long 0x2C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2CC "INTVECTOR_179,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h183"
hexmask.long 0x2CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D0 "INTVECTOR_180,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h184"
hexmask.long 0x2D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D4 "INTVECTOR_181,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h185"
hexmask.long 0x2D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D8 "INTVECTOR_182,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h186"
hexmask.long 0x2D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2DC "INTVECTOR_183,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h187"
hexmask.long 0x2DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E0 "INTVECTOR_184,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h188"
hexmask.long 0x2E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E4 "INTVECTOR_185,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h189"
hexmask.long 0x2E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E8 "INTVECTOR_186,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h190"
hexmask.long 0x2E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2EC "INTVECTOR_187,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h191"
hexmask.long 0x2EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F0 "INTVECTOR_188,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h192"
hexmask.long 0x2F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F4 "INTVECTOR_189,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h193"
hexmask.long 0x2F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F8 "INTVECTOR_190,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h194"
hexmask.long 0x2F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2FC "INTVECTOR_191,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h195"
hexmask.long 0x2FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x300 "INTVECTOR_192,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h196"
hexmask.long 0x300 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x300 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x304 "INTVECTOR_193,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h197"
hexmask.long 0x304 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x304 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x308 "INTVECTOR_194,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h198"
hexmask.long 0x308 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x308 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30C "INTVECTOR_195,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h199"
hexmask.long 0x30C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x310 "INTVECTOR_196,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h200"
hexmask.long 0x310 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x310 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x314 "INTVECTOR_197,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h201"
hexmask.long 0x314 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x314 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x318 "INTVECTOR_198,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h202"
hexmask.long 0x318 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x318 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x31C "INTVECTOR_199,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h203"
hexmask.long 0x31C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x31C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x320 "INTVECTOR_200,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h204"
hexmask.long 0x320 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x320 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x324 "INTVECTOR_201,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h205"
hexmask.long 0x324 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x324 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x328 "INTVECTOR_202,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h206"
hexmask.long 0x328 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x328 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x32C "INTVECTOR_203,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h207"
hexmask.long 0x32C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x32C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x330 "INTVECTOR_204,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h208"
hexmask.long 0x330 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x330 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x334 "INTVECTOR_205,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h209"
hexmask.long 0x334 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x334 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x338 "INTVECTOR_206,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h210"
hexmask.long 0x338 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x338 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x33C "INTVECTOR_207,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h211"
hexmask.long 0x33C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x33C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x340 "INTVECTOR_208,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h212"
hexmask.long 0x340 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x340 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x344 "INTVECTOR_209,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h213"
hexmask.long 0x344 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x344 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x348 "INTVECTOR_210,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h214"
hexmask.long 0x348 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x348 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34C "INTVECTOR_211,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h215"
hexmask.long 0x34C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x350 "INTVECTOR_212,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h216"
hexmask.long 0x350 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x350 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x354 "INTVECTOR_213,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h217"
hexmask.long 0x354 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x354 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x358 "INTVECTOR_214,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h218"
hexmask.long 0x358 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x358 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x35C "INTVECTOR_215,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h219"
hexmask.long 0x35C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x35C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x360 "INTVECTOR_216,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h220"
hexmask.long 0x360 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x360 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x364 "INTVECTOR_217,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h221"
hexmask.long 0x364 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x364 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x368 "INTVECTOR_218,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h222"
hexmask.long 0x368 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x368 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x36C "INTVECTOR_219,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h223"
hexmask.long 0x36C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x36C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x370 "INTVECTOR_220,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h224"
hexmask.long 0x370 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x370 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x374 "INTVECTOR_221,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h225"
hexmask.long 0x374 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x374 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x378 "INTVECTOR_222,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h226"
hexmask.long 0x378 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x378 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x37C "INTVECTOR_223,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h227"
hexmask.long 0x37C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x37C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x380 "INTVECTOR_224,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h228"
hexmask.long 0x380 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x380 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x384 "INTVECTOR_225,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h229"
hexmask.long 0x384 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x384 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x388 "INTVECTOR_226,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h230"
hexmask.long 0x388 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x388 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38C "INTVECTOR_227,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h231"
hexmask.long 0x38C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x390 "INTVECTOR_228,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h232"
hexmask.long 0x390 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x390 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x394 "INTVECTOR_229,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h233"
hexmask.long 0x394 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x394 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x398 "INTVECTOR_230,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h234"
hexmask.long 0x398 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x398 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x39C "INTVECTOR_231,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h235"
hexmask.long 0x39C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x39C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A0 "INTVECTOR_232,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h236"
hexmask.long 0x3A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A4 "INTVECTOR_233,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h237"
hexmask.long 0x3A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A8 "INTVECTOR_234,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h238"
hexmask.long 0x3A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3AC "INTVECTOR_235,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h239"
hexmask.long 0x3AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B0 "INTVECTOR_236,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h240"
hexmask.long 0x3B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B4 "INTVECTOR_237,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h241"
hexmask.long 0x3B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B8 "INTVECTOR_238,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h242"
hexmask.long 0x3B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3BC "INTVECTOR_239,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h243"
hexmask.long 0x3BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C0 "INTVECTOR_240,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h244"
hexmask.long 0x3C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C4 "INTVECTOR_241,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h245"
hexmask.long 0x3C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C8 "INTVECTOR_242,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h246"
hexmask.long 0x3C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3CC "INTVECTOR_243,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h247"
hexmask.long 0x3CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D0 "INTVECTOR_244,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h248"
hexmask.long 0x3D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D4 "INTVECTOR_245,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h249"
hexmask.long 0x3D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D8 "INTVECTOR_246,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h250"
hexmask.long 0x3D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3DC "INTVECTOR_247,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h251"
hexmask.long 0x3DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E0 "INTVECTOR_248,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h252"
hexmask.long 0x3E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E4 "INTVECTOR_249,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h253"
hexmask.long 0x3E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E8 "INTVECTOR_250,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h254"
hexmask.long 0x3E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3EC "INTVECTOR_251,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h255"
hexmask.long 0x3EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F0 "INTVECTOR_252,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h256"
hexmask.long 0x3F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F4 "INTVECTOR_253,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h257"
hexmask.long 0x3F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F8 "INTVECTOR_254,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h258"
hexmask.long 0x3F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3FC "INTVECTOR_255,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h259"
hexmask.long 0x3FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3FC 0.--1. "RES20,Reserved" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_VIM_R5B (MSS VIM CR5 CORE B)"
base ad:0x20A0000
rgroup.long 0x00++0x27
line.long 0x00 "PID,The Revision Register contains the major and minor revisions for the module"
bitfld.long 0x00 30.--31. "SCHEME,PID register scheme" "0,1,2,3"
bitfld.long 0x00 28.--29. "BU,Business Unit" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Module ID"
bitfld.long 0x00 11.--15. "RTL,RTL revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "INFO,The Info Register gives the configuration Inforrmation of this VIM"
hexmask.long.tbyte 0x04 11.--31. 1. "RES1,RESERVE FIELD"
hexmask.long.word 0x04 0.--10. 1. "INTERRUPTS,Total number of Interrupts"
line.long 0x08 "PRIIRQ,The Prioritized IRQ Register shows the number of the highest priority pending IRQ"
bitfld.long 0x08 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x08 20.--30. 1. "RES2,RESERVE FIELD"
bitfld.long 0x08 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x08 10.--15. "RES3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x08 0.--9. 1. "NUM,Number of the highest priority pending IRQ"
line.long 0x0C "PRIFIQ,The Prioritized FIQ Register shows the number of the highest priority pending FIQ"
bitfld.long 0x0C 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x0C 20.--30. 1. "RES4,RESERVE FIELD"
bitfld.long 0x0C 16.--19. "PRI,Priority of the highest priority pending FIQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x0C 10.--15. "RES5,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x0C 0.--9. 1. "NUM,Number of the highest priority pending FIQ"
line.long 0x10 "IRQGSTS,The IRQ Group Status Register indicates which groups have pending IRQ interrupts"
line.long 0x14 "FIQGSTS,The FIQ Group Status Register indicates which groups have pending FIQ interrupts"
line.long 0x18 "IRQVEC,The IRQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind IRQ"
hexmask.long 0x18 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x18 0.--1. "RES21,RESERVE FIELD" "0,1,2,3"
line.long 0x1C "FIQVEC,The FIQ Vector Address Register contains the 32-bit address of the interrupt vector for the current pendind FIQ"
hexmask.long 0x1C 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x1C 0.--1. "RES22,RESERVE FIELD" "0,1,2,3"
line.long 0x20 "ACTIRQ,The Active IRQ Register shows the number of the currently active IRQ"
bitfld.long 0x20 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x20 20.--30. 1. "RES6,RESERVE FIELD"
bitfld.long 0x20 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x20 10.--15. "RES7,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x20 0.--9. 1. "NUM,Number of the currently active IRQ"
line.long 0x24 "ACTFIQ,The Active FIQ Register shows the number of the currently active FIQ"
bitfld.long 0x24 31. "VALID,Indicates that the num field is valid" "0,1"
hexmask.long.word 0x24 20.--30. 1. "RES8,RESERVE FIELD"
bitfld.long 0x24 16.--19. "PRI,Priority of the highest priority pending IRQ" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x24 10.--15. "RES9,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
hexmask.long.word 0x24 0.--9. 1. "NUM,Number of the currently active FIQ"
group.long 0x30++0x03
line.long 0x00 "DEDVEC,The DED Vector Address contains a default vector address for when an uncorrectable error is detected for an active IRQ or FIQ"
hexmask.long 0x00 2.--31. 1. "ADDR,Upper 30 bits of the 32-bit vector address"
rbitfld.long 0x00 0.--1. "RES23,RESERVE FIELD" "0,1,2,3"
group.long 0x400++0xFF
line.long 0x00 "RAW,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x04 "STS,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x08 "INTR_EN_SET,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x0C "INTER_EN_CLR,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x10 "IRQSTS,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x14 "FIQSTS,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x18 "INTMAP,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x1C "INTTYPE,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x20 "RAW_1,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x24 "STS_1,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x28 "INTR_EN_SET_1,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x2C "INTER_EN_CLR_1,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x30 "IRQSTS_1,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x34 "FIQSTS_1,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x38 "INTMAP_1,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x3C "INTTYPE_1,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x40 "RAW_2,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x44 "STS_2,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x48 "INTR_EN_SET_2,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x4C "INTER_EN_CLR_2,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x50 "IRQSTS_2,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x54 "FIQSTS_2,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x58 "INTMAP_2,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x5C "INTTYPE_2,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x60 "RAW_3,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x64 "STS_3,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x68 "INTR_EN_SET_3,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x6C "INTER_EN_CLR_3,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x70 "IRQSTS_3,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x74 "FIQSTS_3,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x78 "INTMAP_3,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x7C "INTTYPE_3,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0x80 "RAW_4,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0x84 "STS_4,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0x88 "INTR_EN_SET_4,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0x8C "INTER_EN_CLR_4,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0x90 "IRQSTS_4,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0x94 "FIQSTS_4,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0x98 "INTMAP_4,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0x9C "INTTYPE_4,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xA0 "RAW_5,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xA4 "STS_5,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xA8 "INTR_EN_SET_5,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xAC "INTER_EN_CLR_5,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xB0 "IRQSTS_5,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xB4 "FIQSTS_5,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xB8 "INTMAP_5,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xBC "INTTYPE_5,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xC0 "RAW_6,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xC4 "STS_6,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xC8 "INTR_EN_SET_6,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xCC "INTER_EN_CLR_6,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xD0 "IRQSTS_6,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xD4 "FIQSTS_6,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xD8 "INTMAP_6,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xDC "INTTYPE_6,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
line.long 0xE0 "RAW_7,Group M Interrupt Raw Status/Set Register (M is 0 to 7) h400 + M x h20 + h00"
line.long 0xE4 "STS_7,Group M Interrupt Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h04"
line.long 0xE8 "INTR_EN_SET_7,Group M Interrupt Enabled Set Register (M is 0 to 7) h400 + M x h20 + h08"
line.long 0xEC "INTER_EN_CLR_7,Group M Interrupt Enabled Clear Register (M is 0 to 7) h400 + M x h20 + h0C"
line.long 0xF0 "IRQSTS_7,Group M Interrupt IRQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h10"
line.long 0xF4 "FIQSTS_7,Group M Interrupt FIQ Enabled Status/Clear Register (M is 0 to 7) h400 + M x h20 + h14"
line.long 0xF8 "INTMAP_7,Group M Interrupt Map Register (M is 0 to 7) h400 + M x h20 + h18"
line.long 0xFC "INTTYPE_7,Group M Type Map Register (M is 0 to 7) h400 + M x h20 + 0x1C"
group.long 0x1000++0x3FF
line.long 0x00 "INTPRIORITY,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h4"
hexmask.long 0x00 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x00 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "INTPRIORITY_1,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h5"
hexmask.long 0x04 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x04 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "INTPRIORITY_2,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h6"
hexmask.long 0x08 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x08 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x0C "INTPRIORITY_3,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h7"
hexmask.long 0x0C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x0C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "INTPRIORITY_4,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h8"
hexmask.long 0x10 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14 "INTPRIORITY_5,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h9"
hexmask.long 0x14 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "INTPRIORITY_6,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h10"
hexmask.long 0x18 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C "INTPRIORITY_7,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h11"
hexmask.long 0x1C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "INTPRIORITY_8,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h12"
hexmask.long 0x20 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "INTPRIORITY_9,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h13"
hexmask.long 0x24 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28 "INTPRIORITY_10,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h14"
hexmask.long 0x28 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C "INTPRIORITY_11,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h15"
hexmask.long 0x2C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30 "INTPRIORITY_12,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h16"
hexmask.long 0x30 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34 "INTPRIORITY_13,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h17"
hexmask.long 0x34 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38 "INTPRIORITY_14,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h18"
hexmask.long 0x38 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C "INTPRIORITY_15,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h19"
hexmask.long 0x3C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x40 "INTPRIORITY_16,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h20"
hexmask.long 0x40 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x40 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x44 "INTPRIORITY_17,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h21"
hexmask.long 0x44 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x44 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x48 "INTPRIORITY_18,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h22"
hexmask.long 0x48 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x48 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x4C "INTPRIORITY_19,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h23"
hexmask.long 0x4C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x4C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "INTPRIORITY_20,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h24"
hexmask.long 0x50 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x50 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x54 "INTPRIORITY_21,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h25"
hexmask.long 0x54 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x54 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x58 "INTPRIORITY_22,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h26"
hexmask.long 0x58 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x58 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x5C "INTPRIORITY_23,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h27"
hexmask.long 0x5C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x5C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x60 "INTPRIORITY_24,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h28"
hexmask.long 0x60 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x60 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x64 "INTPRIORITY_25,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h29"
hexmask.long 0x64 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x64 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x68 "INTPRIORITY_26,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h30"
hexmask.long 0x68 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x68 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x6C "INTPRIORITY_27,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h31"
hexmask.long 0x6C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x6C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x70 "INTPRIORITY_28,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h32"
hexmask.long 0x70 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x70 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x74 "INTPRIORITY_29,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h33"
hexmask.long 0x74 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x74 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x78 "INTPRIORITY_30,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h34"
hexmask.long 0x78 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x78 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x7C "INTPRIORITY_31,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h35"
hexmask.long 0x7C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x7C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x80 "INTPRIORITY_32,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h36"
hexmask.long 0x80 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x80 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x84 "INTPRIORITY_33,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h37"
hexmask.long 0x84 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x84 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x88 "INTPRIORITY_34,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h38"
hexmask.long 0x88 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x88 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x8C "INTPRIORITY_35,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h39"
hexmask.long 0x8C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x8C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "INTPRIORITY_36,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h40"
hexmask.long 0x90 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x90 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x94 "INTPRIORITY_37,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h41"
hexmask.long 0x94 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x94 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x98 "INTPRIORITY_38,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h42"
hexmask.long 0x98 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x98 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x9C "INTPRIORITY_39,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h43"
hexmask.long 0x9C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x9C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA0 "INTPRIORITY_40,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h44"
hexmask.long 0xA0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA4 "INTPRIORITY_41,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h45"
hexmask.long 0xA4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xA8 "INTPRIORITY_42,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h46"
hexmask.long 0xA8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xA8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xAC "INTPRIORITY_43,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h47"
hexmask.long 0xAC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xAC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB0 "INTPRIORITY_44,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h48"
hexmask.long 0xB0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB4 "INTPRIORITY_45,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h49"
hexmask.long 0xB4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "INTPRIORITY_46,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h50"
hexmask.long 0xB8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xB8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xBC "INTPRIORITY_47,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h51"
hexmask.long 0xBC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xBC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC0 "INTPRIORITY_48,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h52"
hexmask.long 0xC0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC4 "INTPRIORITY_49,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h53"
hexmask.long 0xC4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xC8 "INTPRIORITY_50,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h54"
hexmask.long 0xC8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xC8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xCC "INTPRIORITY_51,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h55"
hexmask.long 0xCC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xCC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD0 "INTPRIORITY_52,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h56"
hexmask.long 0xD0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD4 "INTPRIORITY_53,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h57"
hexmask.long 0xD4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xD8 "INTPRIORITY_54,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h58"
hexmask.long 0xD8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xD8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xDC "INTPRIORITY_55,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h59"
hexmask.long 0xDC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xDC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE0 "INTPRIORITY_56,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h60"
hexmask.long 0xE0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE4 "INTPRIORITY_57,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h61"
hexmask.long 0xE4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xE8 "INTPRIORITY_58,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h62"
hexmask.long 0xE8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xE8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xEC "INTPRIORITY_59,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h63"
hexmask.long 0xEC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xEC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF0 "INTPRIORITY_60,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h64"
hexmask.long 0xF0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF4 "INTPRIORITY_61,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h65"
hexmask.long 0xF4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xF8 "INTPRIORITY_62,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h66"
hexmask.long 0xF8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xF8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xFC "INTPRIORITY_63,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h67"
hexmask.long 0xFC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0xFC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x100 "INTPRIORITY_64,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h68"
hexmask.long 0x100 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x100 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x104 "INTPRIORITY_65,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h69"
hexmask.long 0x104 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x104 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x108 "INTPRIORITY_66,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h70"
hexmask.long 0x108 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x108 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10C "INTPRIORITY_67,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h71"
hexmask.long 0x10C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x10C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x110 "INTPRIORITY_68,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h72"
hexmask.long 0x110 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x110 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x114 "INTPRIORITY_69,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h73"
hexmask.long 0x114 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x114 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x118 "INTPRIORITY_70,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h74"
hexmask.long 0x118 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x118 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x11C "INTPRIORITY_71,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h75"
hexmask.long 0x11C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x11C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x120 "INTPRIORITY_72,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h76"
hexmask.long 0x120 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x120 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x124 "INTPRIORITY_73,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h77"
hexmask.long 0x124 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x124 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x128 "INTPRIORITY_74,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h78"
hexmask.long 0x128 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x128 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x12C "INTPRIORITY_75,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h79"
hexmask.long 0x12C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x12C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x130 "INTPRIORITY_76,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h80"
hexmask.long 0x130 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x130 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x134 "INTPRIORITY_77,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h81"
hexmask.long 0x134 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x134 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x138 "INTPRIORITY_78,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h82"
hexmask.long 0x138 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x138 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x13C "INTPRIORITY_79,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h83"
hexmask.long 0x13C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x13C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x140 "INTPRIORITY_80,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h84"
hexmask.long 0x140 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x140 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x144 "INTPRIORITY_81,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h85"
hexmask.long 0x144 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x144 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x148 "INTPRIORITY_82,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h86"
hexmask.long 0x148 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x148 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x14C "INTPRIORITY_83,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h87"
hexmask.long 0x14C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x14C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x150 "INTPRIORITY_84,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h88"
hexmask.long 0x150 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x150 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x154 "INTPRIORITY_85,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h89"
hexmask.long 0x154 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x154 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x158 "INTPRIORITY_86,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h90"
hexmask.long 0x158 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x158 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x15C "INTPRIORITY_87,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h91"
hexmask.long 0x15C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x15C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x160 "INTPRIORITY_88,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h92"
hexmask.long 0x160 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x160 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x164 "INTPRIORITY_89,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h93"
hexmask.long 0x164 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x164 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x168 "INTPRIORITY_90,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h94"
hexmask.long 0x168 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x168 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x16C "INTPRIORITY_91,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h95"
hexmask.long 0x16C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x16C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x170 "INTPRIORITY_92,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h96"
hexmask.long 0x170 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x170 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x174 "INTPRIORITY_93,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h97"
hexmask.long 0x174 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x174 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x178 "INTPRIORITY_94,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h98"
hexmask.long 0x178 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x178 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x17C "INTPRIORITY_95,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h99"
hexmask.long 0x17C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x17C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x180 "INTPRIORITY_96,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h100"
hexmask.long 0x180 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x180 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x184 "INTPRIORITY_97,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h101"
hexmask.long 0x184 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x184 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x188 "INTPRIORITY_98,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h102"
hexmask.long 0x188 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x188 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18C "INTPRIORITY_99,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h103"
hexmask.long 0x18C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x18C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x190 "INTPRIORITY_100,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h104"
hexmask.long 0x190 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x190 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x194 "INTPRIORITY_101,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h105"
hexmask.long 0x194 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x194 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x198 "INTPRIORITY_102,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h106"
hexmask.long 0x198 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x198 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x19C "INTPRIORITY_103,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h107"
hexmask.long 0x19C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x19C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A0 "INTPRIORITY_104,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h108"
hexmask.long 0x1A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A4 "INTPRIORITY_105,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h109"
hexmask.long 0x1A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1A8 "INTPRIORITY_106,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h110"
hexmask.long 0x1A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1AC "INTPRIORITY_107,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h111"
hexmask.long 0x1AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B0 "INTPRIORITY_108,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h112"
hexmask.long 0x1B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B4 "INTPRIORITY_109,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h113"
hexmask.long 0x1B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1B8 "INTPRIORITY_110,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h114"
hexmask.long 0x1B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1BC "INTPRIORITY_111,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h115"
hexmask.long 0x1BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C0 "INTPRIORITY_112,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h116"
hexmask.long 0x1C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C4 "INTPRIORITY_113,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h117"
hexmask.long 0x1C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1C8 "INTPRIORITY_114,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h118"
hexmask.long 0x1C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1CC "INTPRIORITY_115,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h119"
hexmask.long 0x1CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D0 "INTPRIORITY_116,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h120"
hexmask.long 0x1D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D4 "INTPRIORITY_117,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h121"
hexmask.long 0x1D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1D8 "INTPRIORITY_118,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h122"
hexmask.long 0x1D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1DC "INTPRIORITY_119,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h123"
hexmask.long 0x1DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E0 "INTPRIORITY_120,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h124"
hexmask.long 0x1E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E4 "INTPRIORITY_121,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h125"
hexmask.long 0x1E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1E8 "INTPRIORITY_122,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h126"
hexmask.long 0x1E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1EC "INTPRIORITY_123,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h127"
hexmask.long 0x1EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F0 "INTPRIORITY_124,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h128"
hexmask.long 0x1F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F4 "INTPRIORITY_125,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h129"
hexmask.long 0x1F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1F8 "INTPRIORITY_126,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h130"
hexmask.long 0x1F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x1FC "INTPRIORITY_127,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h131"
hexmask.long 0x1FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x1FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x200 "INTPRIORITY_128,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h132"
hexmask.long 0x200 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x200 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x204 "INTPRIORITY_129,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h133"
hexmask.long 0x204 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x204 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x208 "INTPRIORITY_130,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h134"
hexmask.long 0x208 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x208 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20C "INTPRIORITY_131,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h135"
hexmask.long 0x20C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x20C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x210 "INTPRIORITY_132,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h136"
hexmask.long 0x210 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x210 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x214 "INTPRIORITY_133,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h137"
hexmask.long 0x214 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x214 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x218 "INTPRIORITY_134,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h138"
hexmask.long 0x218 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x218 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x21C "INTPRIORITY_135,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h139"
hexmask.long 0x21C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x21C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x220 "INTPRIORITY_136,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h140"
hexmask.long 0x220 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x220 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x224 "INTPRIORITY_137,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h141"
hexmask.long 0x224 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x224 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x228 "INTPRIORITY_138,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h142"
hexmask.long 0x228 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x228 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x22C "INTPRIORITY_139,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h143"
hexmask.long 0x22C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x22C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x230 "INTPRIORITY_140,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h144"
hexmask.long 0x230 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x230 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x234 "INTPRIORITY_141,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h145"
hexmask.long 0x234 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x234 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x238 "INTPRIORITY_142,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h146"
hexmask.long 0x238 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x238 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x23C "INTPRIORITY_143,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h147"
hexmask.long 0x23C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x23C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x240 "INTPRIORITY_144,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h148"
hexmask.long 0x240 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x240 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x244 "INTPRIORITY_145,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h149"
hexmask.long 0x244 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x244 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x248 "INTPRIORITY_146,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h150"
hexmask.long 0x248 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x248 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24C "INTPRIORITY_147,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h151"
hexmask.long 0x24C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x24C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x250 "INTPRIORITY_148,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h152"
hexmask.long 0x250 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x250 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x254 "INTPRIORITY_149,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h153"
hexmask.long 0x254 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x254 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x258 "INTPRIORITY_150,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h154"
hexmask.long 0x258 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x258 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x25C "INTPRIORITY_151,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h155"
hexmask.long 0x25C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x25C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x260 "INTPRIORITY_152,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h156"
hexmask.long 0x260 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x260 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x264 "INTPRIORITY_153,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h157"
hexmask.long 0x264 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x264 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x268 "INTPRIORITY_154,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h158"
hexmask.long 0x268 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x268 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x26C "INTPRIORITY_155,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h159"
hexmask.long 0x26C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x26C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x270 "INTPRIORITY_156,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h160"
hexmask.long 0x270 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x270 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x274 "INTPRIORITY_157,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h161"
hexmask.long 0x274 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x274 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x278 "INTPRIORITY_158,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h162"
hexmask.long 0x278 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x278 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x27C "INTPRIORITY_159,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h163"
hexmask.long 0x27C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x27C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x280 "INTPRIORITY_160,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h164"
hexmask.long 0x280 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x280 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x284 "INTPRIORITY_161,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h165"
hexmask.long 0x284 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x284 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x288 "INTPRIORITY_162,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h166"
hexmask.long 0x288 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x288 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x28C "INTPRIORITY_163,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h167"
hexmask.long 0x28C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x28C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x290 "INTPRIORITY_164,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h168"
hexmask.long 0x290 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x290 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x294 "INTPRIORITY_165,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h169"
hexmask.long 0x294 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x294 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x298 "INTPRIORITY_166,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h170"
hexmask.long 0x298 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x298 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x29C "INTPRIORITY_167,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h171"
hexmask.long 0x29C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x29C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A0 "INTPRIORITY_168,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h172"
hexmask.long 0x2A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A4 "INTPRIORITY_169,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h173"
hexmask.long 0x2A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2A8 "INTPRIORITY_170,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h174"
hexmask.long 0x2A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2AC "INTPRIORITY_171,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h175"
hexmask.long 0x2AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B0 "INTPRIORITY_172,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h176"
hexmask.long 0x2B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B4 "INTPRIORITY_173,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h177"
hexmask.long 0x2B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2B8 "INTPRIORITY_174,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h178"
hexmask.long 0x2B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2BC "INTPRIORITY_175,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h179"
hexmask.long 0x2BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C0 "INTPRIORITY_176,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h180"
hexmask.long 0x2C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C4 "INTPRIORITY_177,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h181"
hexmask.long 0x2C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2C8 "INTPRIORITY_178,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h182"
hexmask.long 0x2C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2CC "INTPRIORITY_179,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h183"
hexmask.long 0x2CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D0 "INTPRIORITY_180,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h184"
hexmask.long 0x2D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D4 "INTPRIORITY_181,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h185"
hexmask.long 0x2D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2D8 "INTPRIORITY_182,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h186"
hexmask.long 0x2D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2DC "INTPRIORITY_183,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h187"
hexmask.long 0x2DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E0 "INTPRIORITY_184,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h188"
hexmask.long 0x2E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E4 "INTPRIORITY_185,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h189"
hexmask.long 0x2E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2E8 "INTPRIORITY_186,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h190"
hexmask.long 0x2E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2EC "INTPRIORITY_187,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h191"
hexmask.long 0x2EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F0 "INTPRIORITY_188,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h192"
hexmask.long 0x2F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F4 "INTPRIORITY_189,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h193"
hexmask.long 0x2F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2F8 "INTPRIORITY_190,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h194"
hexmask.long 0x2F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x2FC "INTPRIORITY_191,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h195"
hexmask.long 0x2FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x2FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x300 "INTPRIORITY_192,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h196"
hexmask.long 0x300 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x300 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x304 "INTPRIORITY_193,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h197"
hexmask.long 0x304 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x304 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x308 "INTPRIORITY_194,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h198"
hexmask.long 0x308 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x308 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x30C "INTPRIORITY_195,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h199"
hexmask.long 0x30C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x30C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x310 "INTPRIORITY_196,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h200"
hexmask.long 0x310 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x310 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x314 "INTPRIORITY_197,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h201"
hexmask.long 0x314 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x314 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x318 "INTPRIORITY_198,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h202"
hexmask.long 0x318 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x318 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x31C "INTPRIORITY_199,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h203"
hexmask.long 0x31C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x31C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x320 "INTPRIORITY_200,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h204"
hexmask.long 0x320 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x320 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x324 "INTPRIORITY_201,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h205"
hexmask.long 0x324 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x324 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x328 "INTPRIORITY_202,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h206"
hexmask.long 0x328 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x328 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x32C "INTPRIORITY_203,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h207"
hexmask.long 0x32C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x32C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x330 "INTPRIORITY_204,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h208"
hexmask.long 0x330 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x330 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x334 "INTPRIORITY_205,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h209"
hexmask.long 0x334 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x334 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x338 "INTPRIORITY_206,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h210"
hexmask.long 0x338 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x338 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x33C "INTPRIORITY_207,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h211"
hexmask.long 0x33C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x33C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x340 "INTPRIORITY_208,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h212"
hexmask.long 0x340 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x340 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x344 "INTPRIORITY_209,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h213"
hexmask.long 0x344 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x344 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x348 "INTPRIORITY_210,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h214"
hexmask.long 0x348 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x348 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x34C "INTPRIORITY_211,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h215"
hexmask.long 0x34C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x34C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x350 "INTPRIORITY_212,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h216"
hexmask.long 0x350 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x350 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x354 "INTPRIORITY_213,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h217"
hexmask.long 0x354 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x354 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x358 "INTPRIORITY_214,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h218"
hexmask.long 0x358 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x358 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x35C "INTPRIORITY_215,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h219"
hexmask.long 0x35C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x35C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x360 "INTPRIORITY_216,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h220"
hexmask.long 0x360 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x360 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x364 "INTPRIORITY_217,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h221"
hexmask.long 0x364 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x364 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x368 "INTPRIORITY_218,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h222"
hexmask.long 0x368 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x368 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x36C "INTPRIORITY_219,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h223"
hexmask.long 0x36C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x36C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x370 "INTPRIORITY_220,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h224"
hexmask.long 0x370 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x370 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x374 "INTPRIORITY_221,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h225"
hexmask.long 0x374 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x374 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x378 "INTPRIORITY_222,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h226"
hexmask.long 0x378 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x378 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x37C "INTPRIORITY_223,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h227"
hexmask.long 0x37C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x37C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x380 "INTPRIORITY_224,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h228"
hexmask.long 0x380 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x380 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x384 "INTPRIORITY_225,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h229"
hexmask.long 0x384 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x384 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x388 "INTPRIORITY_226,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h230"
hexmask.long 0x388 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x388 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x38C "INTPRIORITY_227,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h231"
hexmask.long 0x38C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x38C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x390 "INTPRIORITY_228,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h232"
hexmask.long 0x390 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x390 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x394 "INTPRIORITY_229,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h233"
hexmask.long 0x394 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x394 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x398 "INTPRIORITY_230,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h234"
hexmask.long 0x398 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x398 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x39C "INTPRIORITY_231,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h235"
hexmask.long 0x39C 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x39C 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A0 "INTPRIORITY_232,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h236"
hexmask.long 0x3A0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A4 "INTPRIORITY_233,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h237"
hexmask.long 0x3A4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3A8 "INTPRIORITY_234,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h238"
hexmask.long 0x3A8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3A8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3AC "INTPRIORITY_235,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h239"
hexmask.long 0x3AC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3AC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B0 "INTPRIORITY_236,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h240"
hexmask.long 0x3B0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B4 "INTPRIORITY_237,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h241"
hexmask.long 0x3B4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3B8 "INTPRIORITY_238,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h242"
hexmask.long 0x3B8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3B8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3BC "INTPRIORITY_239,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h243"
hexmask.long 0x3BC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3BC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C0 "INTPRIORITY_240,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h244"
hexmask.long 0x3C0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C4 "INTPRIORITY_241,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h245"
hexmask.long 0x3C4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3C8 "INTPRIORITY_242,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h246"
hexmask.long 0x3C8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3C8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3CC "INTPRIORITY_243,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h247"
hexmask.long 0x3CC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3CC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D0 "INTPRIORITY_244,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h248"
hexmask.long 0x3D0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D4 "INTPRIORITY_245,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h249"
hexmask.long 0x3D4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3D8 "INTPRIORITY_246,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h250"
hexmask.long 0x3D8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3D8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3DC "INTPRIORITY_247,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h251"
hexmask.long 0x3DC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3DC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E0 "INTPRIORITY_248,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h252"
hexmask.long 0x3E0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E4 "INTPRIORITY_249,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h253"
hexmask.long 0x3E4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3E8 "INTPRIORITY_250,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h254"
hexmask.long 0x3E8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3E8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3EC "INTPRIORITY_251,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h255"
hexmask.long 0x3EC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3EC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F0 "INTPRIORITY_252,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h256"
hexmask.long 0x3F0 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F0 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F4 "INTPRIORITY_253,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h257"
hexmask.long 0x3F4 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F4 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3F8 "INTPRIORITY_254,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h258"
hexmask.long 0x3F8 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3F8 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x3FC "INTPRIORITY_255,Interrupt Q Priority Register (Q is 0 to 255 . Q= M+1 x 32) h1000 + Q x h259"
hexmask.long 0x3FC 4.--31. 1. "RES19,RESERVE FIELD"
bitfld.long 0x3FC 0.--3. "PRI,This is the priority for interrupt Q" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x2000++0x3FF
line.long 0x00 "INTVECTOR,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h4"
hexmask.long 0x00 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x00 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x04 "INTVECTOR_1,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h5"
hexmask.long 0x04 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x04 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x08 "INTVECTOR_2,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h6"
hexmask.long 0x08 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x08 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x0C "INTVECTOR_3,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h7"
hexmask.long 0x0C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x0C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10 "INTVECTOR_4,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h8"
hexmask.long 0x10 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14 "INTVECTOR_5,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h9"
hexmask.long 0x14 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18 "INTVECTOR_6,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h10"
hexmask.long 0x18 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C "INTVECTOR_7,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h11"
hexmask.long 0x1C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20 "INTVECTOR_8,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h12"
hexmask.long 0x20 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24 "INTVECTOR_9,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h13"
hexmask.long 0x24 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28 "INTVECTOR_10,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h14"
hexmask.long 0x28 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C "INTVECTOR_11,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h15"
hexmask.long 0x2C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30 "INTVECTOR_12,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h16"
hexmask.long 0x30 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34 "INTVECTOR_13,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h17"
hexmask.long 0x34 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38 "INTVECTOR_14,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h18"
hexmask.long 0x38 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C "INTVECTOR_15,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h19"
hexmask.long 0x3C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x40 "INTVECTOR_16,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h20"
hexmask.long 0x40 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x40 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x44 "INTVECTOR_17,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h21"
hexmask.long 0x44 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x44 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x48 "INTVECTOR_18,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h22"
hexmask.long 0x48 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x48 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x4C "INTVECTOR_19,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h23"
hexmask.long 0x4C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x4C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x50 "INTVECTOR_20,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h24"
hexmask.long 0x50 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x50 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x54 "INTVECTOR_21,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h25"
hexmask.long 0x54 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x54 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x58 "INTVECTOR_22,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h26"
hexmask.long 0x58 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x58 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x5C "INTVECTOR_23,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h27"
hexmask.long 0x5C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x5C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x60 "INTVECTOR_24,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h28"
hexmask.long 0x60 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x60 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x64 "INTVECTOR_25,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h29"
hexmask.long 0x64 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x64 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x68 "INTVECTOR_26,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h30"
hexmask.long 0x68 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x68 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x6C "INTVECTOR_27,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h31"
hexmask.long 0x6C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x6C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x70 "INTVECTOR_28,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h32"
hexmask.long 0x70 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x70 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x74 "INTVECTOR_29,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h33"
hexmask.long 0x74 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x74 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x78 "INTVECTOR_30,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h34"
hexmask.long 0x78 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x78 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x7C "INTVECTOR_31,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h35"
hexmask.long 0x7C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x7C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x80 "INTVECTOR_32,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h36"
hexmask.long 0x80 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x80 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x84 "INTVECTOR_33,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h37"
hexmask.long 0x84 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x84 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x88 "INTVECTOR_34,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h38"
hexmask.long 0x88 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x88 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x8C "INTVECTOR_35,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h39"
hexmask.long 0x8C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x8C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x90 "INTVECTOR_36,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h40"
hexmask.long 0x90 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x90 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x94 "INTVECTOR_37,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h41"
hexmask.long 0x94 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x94 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x98 "INTVECTOR_38,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h42"
hexmask.long 0x98 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x98 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x9C "INTVECTOR_39,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h43"
hexmask.long 0x9C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x9C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA0 "INTVECTOR_40,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h44"
hexmask.long 0xA0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA4 "INTVECTOR_41,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h45"
hexmask.long 0xA4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xA8 "INTVECTOR_42,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h46"
hexmask.long 0xA8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xA8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xAC "INTVECTOR_43,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h47"
hexmask.long 0xAC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xAC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB0 "INTVECTOR_44,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h48"
hexmask.long 0xB0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB4 "INTVECTOR_45,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h49"
hexmask.long 0xB4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xB8 "INTVECTOR_46,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h50"
hexmask.long 0xB8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xB8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xBC "INTVECTOR_47,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h51"
hexmask.long 0xBC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xBC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC0 "INTVECTOR_48,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h52"
hexmask.long 0xC0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC4 "INTVECTOR_49,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h53"
hexmask.long 0xC4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xC8 "INTVECTOR_50,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h54"
hexmask.long 0xC8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xC8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xCC "INTVECTOR_51,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h55"
hexmask.long 0xCC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xCC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD0 "INTVECTOR_52,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h56"
hexmask.long 0xD0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD4 "INTVECTOR_53,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h57"
hexmask.long 0xD4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xD8 "INTVECTOR_54,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h58"
hexmask.long 0xD8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xD8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xDC "INTVECTOR_55,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h59"
hexmask.long 0xDC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xDC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE0 "INTVECTOR_56,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h60"
hexmask.long 0xE0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE4 "INTVECTOR_57,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h61"
hexmask.long 0xE4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xE8 "INTVECTOR_58,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h62"
hexmask.long 0xE8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xE8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xEC "INTVECTOR_59,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h63"
hexmask.long 0xEC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xEC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF0 "INTVECTOR_60,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h64"
hexmask.long 0xF0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF4 "INTVECTOR_61,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h65"
hexmask.long 0xF4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xF8 "INTVECTOR_62,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h66"
hexmask.long 0xF8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xF8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0xFC "INTVECTOR_63,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h67"
hexmask.long 0xFC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0xFC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x100 "INTVECTOR_64,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h68"
hexmask.long 0x100 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x100 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x104 "INTVECTOR_65,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h69"
hexmask.long 0x104 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x104 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x108 "INTVECTOR_66,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h70"
hexmask.long 0x108 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x108 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x10C "INTVECTOR_67,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h71"
hexmask.long 0x10C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x10C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x110 "INTVECTOR_68,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h72"
hexmask.long 0x110 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x110 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x114 "INTVECTOR_69,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h73"
hexmask.long 0x114 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x114 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x118 "INTVECTOR_70,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h74"
hexmask.long 0x118 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x118 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x11C "INTVECTOR_71,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h75"
hexmask.long 0x11C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x11C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x120 "INTVECTOR_72,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h76"
hexmask.long 0x120 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x120 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x124 "INTVECTOR_73,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h77"
hexmask.long 0x124 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x124 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x128 "INTVECTOR_74,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h78"
hexmask.long 0x128 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x128 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x12C "INTVECTOR_75,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h79"
hexmask.long 0x12C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x12C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x130 "INTVECTOR_76,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h80"
hexmask.long 0x130 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x130 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x134 "INTVECTOR_77,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h81"
hexmask.long 0x134 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x134 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x138 "INTVECTOR_78,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h82"
hexmask.long 0x138 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x138 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x13C "INTVECTOR_79,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h83"
hexmask.long 0x13C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x13C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x140 "INTVECTOR_80,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h84"
hexmask.long 0x140 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x140 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x144 "INTVECTOR_81,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h85"
hexmask.long 0x144 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x144 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x148 "INTVECTOR_82,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h86"
hexmask.long 0x148 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x148 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x14C "INTVECTOR_83,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h87"
hexmask.long 0x14C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x14C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x150 "INTVECTOR_84,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h88"
hexmask.long 0x150 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x150 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x154 "INTVECTOR_85,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h89"
hexmask.long 0x154 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x154 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x158 "INTVECTOR_86,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h90"
hexmask.long 0x158 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x158 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x15C "INTVECTOR_87,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h91"
hexmask.long 0x15C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x15C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x160 "INTVECTOR_88,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h92"
hexmask.long 0x160 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x160 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x164 "INTVECTOR_89,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h93"
hexmask.long 0x164 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x164 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x168 "INTVECTOR_90,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h94"
hexmask.long 0x168 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x168 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x16C "INTVECTOR_91,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h95"
hexmask.long 0x16C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x16C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x170 "INTVECTOR_92,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h96"
hexmask.long 0x170 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x170 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x174 "INTVECTOR_93,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h97"
hexmask.long 0x174 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x174 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x178 "INTVECTOR_94,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h98"
hexmask.long 0x178 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x178 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x17C "INTVECTOR_95,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h99"
hexmask.long 0x17C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x17C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x180 "INTVECTOR_96,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h100"
hexmask.long 0x180 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x180 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x184 "INTVECTOR_97,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h101"
hexmask.long 0x184 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x184 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x188 "INTVECTOR_98,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h102"
hexmask.long 0x188 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x188 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x18C "INTVECTOR_99,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h103"
hexmask.long 0x18C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x18C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x190 "INTVECTOR_100,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h104"
hexmask.long 0x190 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x190 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x194 "INTVECTOR_101,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h105"
hexmask.long 0x194 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x194 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x198 "INTVECTOR_102,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h106"
hexmask.long 0x198 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x198 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x19C "INTVECTOR_103,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h107"
hexmask.long 0x19C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x19C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A0 "INTVECTOR_104,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h108"
hexmask.long 0x1A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A4 "INTVECTOR_105,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h109"
hexmask.long 0x1A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1A8 "INTVECTOR_106,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h110"
hexmask.long 0x1A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1AC "INTVECTOR_107,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h111"
hexmask.long 0x1AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B0 "INTVECTOR_108,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h112"
hexmask.long 0x1B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B4 "INTVECTOR_109,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h113"
hexmask.long 0x1B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1B8 "INTVECTOR_110,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h114"
hexmask.long 0x1B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1BC "INTVECTOR_111,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h115"
hexmask.long 0x1BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C0 "INTVECTOR_112,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h116"
hexmask.long 0x1C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C4 "INTVECTOR_113,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h117"
hexmask.long 0x1C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1C8 "INTVECTOR_114,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h118"
hexmask.long 0x1C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1CC "INTVECTOR_115,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h119"
hexmask.long 0x1CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D0 "INTVECTOR_116,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h120"
hexmask.long 0x1D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D4 "INTVECTOR_117,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h121"
hexmask.long 0x1D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1D8 "INTVECTOR_118,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h122"
hexmask.long 0x1D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1DC "INTVECTOR_119,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h123"
hexmask.long 0x1DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E0 "INTVECTOR_120,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h124"
hexmask.long 0x1E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E4 "INTVECTOR_121,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h125"
hexmask.long 0x1E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1E8 "INTVECTOR_122,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h126"
hexmask.long 0x1E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1EC "INTVECTOR_123,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h127"
hexmask.long 0x1EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F0 "INTVECTOR_124,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h128"
hexmask.long 0x1F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F4 "INTVECTOR_125,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h129"
hexmask.long 0x1F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1F8 "INTVECTOR_126,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h130"
hexmask.long 0x1F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x1FC "INTVECTOR_127,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h131"
hexmask.long 0x1FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x1FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x200 "INTVECTOR_128,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h132"
hexmask.long 0x200 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x200 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x204 "INTVECTOR_129,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h133"
hexmask.long 0x204 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x204 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x208 "INTVECTOR_130,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h134"
hexmask.long 0x208 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x208 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x20C "INTVECTOR_131,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h135"
hexmask.long 0x20C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x20C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x210 "INTVECTOR_132,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h136"
hexmask.long 0x210 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x210 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x214 "INTVECTOR_133,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h137"
hexmask.long 0x214 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x214 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x218 "INTVECTOR_134,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h138"
hexmask.long 0x218 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x218 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x21C "INTVECTOR_135,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h139"
hexmask.long 0x21C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x21C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x220 "INTVECTOR_136,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h140"
hexmask.long 0x220 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x220 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x224 "INTVECTOR_137,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h141"
hexmask.long 0x224 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x224 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x228 "INTVECTOR_138,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h142"
hexmask.long 0x228 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x228 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x22C "INTVECTOR_139,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h143"
hexmask.long 0x22C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x22C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x230 "INTVECTOR_140,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h144"
hexmask.long 0x230 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x230 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x234 "INTVECTOR_141,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h145"
hexmask.long 0x234 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x234 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x238 "INTVECTOR_142,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h146"
hexmask.long 0x238 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x238 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x23C "INTVECTOR_143,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h147"
hexmask.long 0x23C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x23C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x240 "INTVECTOR_144,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h148"
hexmask.long 0x240 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x240 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x244 "INTVECTOR_145,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h149"
hexmask.long 0x244 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x244 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x248 "INTVECTOR_146,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h150"
hexmask.long 0x248 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x248 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x24C "INTVECTOR_147,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h151"
hexmask.long 0x24C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x24C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x250 "INTVECTOR_148,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h152"
hexmask.long 0x250 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x250 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x254 "INTVECTOR_149,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h153"
hexmask.long 0x254 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x254 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x258 "INTVECTOR_150,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h154"
hexmask.long 0x258 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x258 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x25C "INTVECTOR_151,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h155"
hexmask.long 0x25C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x25C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x260 "INTVECTOR_152,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h156"
hexmask.long 0x260 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x260 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x264 "INTVECTOR_153,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h157"
hexmask.long 0x264 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x264 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x268 "INTVECTOR_154,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h158"
hexmask.long 0x268 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x268 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x26C "INTVECTOR_155,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h159"
hexmask.long 0x26C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x26C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x270 "INTVECTOR_156,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h160"
hexmask.long 0x270 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x270 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x274 "INTVECTOR_157,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h161"
hexmask.long 0x274 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x274 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x278 "INTVECTOR_158,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h162"
hexmask.long 0x278 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x278 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x27C "INTVECTOR_159,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h163"
hexmask.long 0x27C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x27C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x280 "INTVECTOR_160,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h164"
hexmask.long 0x280 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x280 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x284 "INTVECTOR_161,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h165"
hexmask.long 0x284 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x284 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x288 "INTVECTOR_162,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h166"
hexmask.long 0x288 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x288 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x28C "INTVECTOR_163,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h167"
hexmask.long 0x28C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x28C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x290 "INTVECTOR_164,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h168"
hexmask.long 0x290 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x290 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x294 "INTVECTOR_165,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h169"
hexmask.long 0x294 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x294 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x298 "INTVECTOR_166,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h170"
hexmask.long 0x298 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x298 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x29C "INTVECTOR_167,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h171"
hexmask.long 0x29C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x29C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A0 "INTVECTOR_168,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h172"
hexmask.long 0x2A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A4 "INTVECTOR_169,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h173"
hexmask.long 0x2A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2A8 "INTVECTOR_170,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h174"
hexmask.long 0x2A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2AC "INTVECTOR_171,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h175"
hexmask.long 0x2AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B0 "INTVECTOR_172,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h176"
hexmask.long 0x2B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B4 "INTVECTOR_173,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h177"
hexmask.long 0x2B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2B8 "INTVECTOR_174,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h178"
hexmask.long 0x2B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2BC "INTVECTOR_175,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h179"
hexmask.long 0x2BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C0 "INTVECTOR_176,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h180"
hexmask.long 0x2C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C4 "INTVECTOR_177,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h181"
hexmask.long 0x2C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2C8 "INTVECTOR_178,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h182"
hexmask.long 0x2C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2CC "INTVECTOR_179,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h183"
hexmask.long 0x2CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D0 "INTVECTOR_180,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h184"
hexmask.long 0x2D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D4 "INTVECTOR_181,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h185"
hexmask.long 0x2D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2D8 "INTVECTOR_182,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h186"
hexmask.long 0x2D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2DC "INTVECTOR_183,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h187"
hexmask.long 0x2DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E0 "INTVECTOR_184,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h188"
hexmask.long 0x2E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E4 "INTVECTOR_185,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h189"
hexmask.long 0x2E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2E8 "INTVECTOR_186,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h190"
hexmask.long 0x2E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2EC "INTVECTOR_187,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h191"
hexmask.long 0x2EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F0 "INTVECTOR_188,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h192"
hexmask.long 0x2F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F4 "INTVECTOR_189,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h193"
hexmask.long 0x2F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2F8 "INTVECTOR_190,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h194"
hexmask.long 0x2F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x2FC "INTVECTOR_191,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h195"
hexmask.long 0x2FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x2FC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x300 "INTVECTOR_192,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h196"
hexmask.long 0x300 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x300 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x304 "INTVECTOR_193,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h197"
hexmask.long 0x304 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x304 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x308 "INTVECTOR_194,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h198"
hexmask.long 0x308 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x308 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x30C "INTVECTOR_195,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h199"
hexmask.long 0x30C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x30C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x310 "INTVECTOR_196,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h200"
hexmask.long 0x310 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x310 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x314 "INTVECTOR_197,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h201"
hexmask.long 0x314 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x314 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x318 "INTVECTOR_198,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h202"
hexmask.long 0x318 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x318 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x31C "INTVECTOR_199,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h203"
hexmask.long 0x31C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x31C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x320 "INTVECTOR_200,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h204"
hexmask.long 0x320 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x320 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x324 "INTVECTOR_201,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h205"
hexmask.long 0x324 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x324 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x328 "INTVECTOR_202,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h206"
hexmask.long 0x328 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x328 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x32C "INTVECTOR_203,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h207"
hexmask.long 0x32C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x32C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x330 "INTVECTOR_204,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h208"
hexmask.long 0x330 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x330 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x334 "INTVECTOR_205,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h209"
hexmask.long 0x334 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x334 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x338 "INTVECTOR_206,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h210"
hexmask.long 0x338 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x338 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x33C "INTVECTOR_207,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h211"
hexmask.long 0x33C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x33C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x340 "INTVECTOR_208,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h212"
hexmask.long 0x340 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x340 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x344 "INTVECTOR_209,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h213"
hexmask.long 0x344 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x344 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x348 "INTVECTOR_210,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h214"
hexmask.long 0x348 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x348 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x34C "INTVECTOR_211,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h215"
hexmask.long 0x34C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x34C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x350 "INTVECTOR_212,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h216"
hexmask.long 0x350 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x350 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x354 "INTVECTOR_213,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h217"
hexmask.long 0x354 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x354 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x358 "INTVECTOR_214,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h218"
hexmask.long 0x358 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x358 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x35C "INTVECTOR_215,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h219"
hexmask.long 0x35C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x35C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x360 "INTVECTOR_216,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h220"
hexmask.long 0x360 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x360 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x364 "INTVECTOR_217,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h221"
hexmask.long 0x364 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x364 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x368 "INTVECTOR_218,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h222"
hexmask.long 0x368 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x368 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x36C "INTVECTOR_219,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h223"
hexmask.long 0x36C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x36C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x370 "INTVECTOR_220,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h224"
hexmask.long 0x370 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x370 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x374 "INTVECTOR_221,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h225"
hexmask.long 0x374 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x374 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x378 "INTVECTOR_222,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h226"
hexmask.long 0x378 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x378 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x37C "INTVECTOR_223,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h227"
hexmask.long 0x37C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x37C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x380 "INTVECTOR_224,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h228"
hexmask.long 0x380 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x380 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x384 "INTVECTOR_225,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h229"
hexmask.long 0x384 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x384 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x388 "INTVECTOR_226,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h230"
hexmask.long 0x388 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x388 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x38C "INTVECTOR_227,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h231"
hexmask.long 0x38C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x38C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x390 "INTVECTOR_228,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h232"
hexmask.long 0x390 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x390 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x394 "INTVECTOR_229,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h233"
hexmask.long 0x394 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x394 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x398 "INTVECTOR_230,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h234"
hexmask.long 0x398 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x398 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x39C "INTVECTOR_231,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h235"
hexmask.long 0x39C 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x39C 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A0 "INTVECTOR_232,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h236"
hexmask.long 0x3A0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A4 "INTVECTOR_233,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h237"
hexmask.long 0x3A4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3A8 "INTVECTOR_234,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h238"
hexmask.long 0x3A8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3A8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3AC "INTVECTOR_235,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h239"
hexmask.long 0x3AC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3AC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B0 "INTVECTOR_236,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h240"
hexmask.long 0x3B0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B4 "INTVECTOR_237,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h241"
hexmask.long 0x3B4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3B8 "INTVECTOR_238,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h242"
hexmask.long 0x3B8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3B8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3BC "INTVECTOR_239,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h243"
hexmask.long 0x3BC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3BC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C0 "INTVECTOR_240,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h244"
hexmask.long 0x3C0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C4 "INTVECTOR_241,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h245"
hexmask.long 0x3C4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3C8 "INTVECTOR_242,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h246"
hexmask.long 0x3C8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3C8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3CC "INTVECTOR_243,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h247"
hexmask.long 0x3CC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3CC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D0 "INTVECTOR_244,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h248"
hexmask.long 0x3D0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D4 "INTVECTOR_245,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h249"
hexmask.long 0x3D4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3D8 "INTVECTOR_246,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h250"
hexmask.long 0x3D8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3D8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3DC "INTVECTOR_247,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h251"
hexmask.long 0x3DC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3DC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E0 "INTVECTOR_248,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h252"
hexmask.long 0x3E0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E4 "INTVECTOR_249,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h253"
hexmask.long 0x3E4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3E8 "INTVECTOR_250,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h254"
hexmask.long 0x3E8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3E8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3EC "INTVECTOR_251,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h255"
hexmask.long 0x3EC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3EC 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F0 "INTVECTOR_252,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h256"
hexmask.long 0x3F0 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F0 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F4 "INTVECTOR_253,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h257"
hexmask.long 0x3F4 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F4 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3F8 "INTVECTOR_254,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h258"
hexmask.long 0x3F8 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3F8 0.--1. "RES20,Reserved" "0,1,2,3"
line.long 0x3FC "INTVECTOR_255,Interrupt Q Vector Register (Q is 0 to 255 . Q= M+1 x 32) h2000 + Q x h259"
hexmask.long 0x3FC 2.--31. 1. "ADDR,This is the 32-bit Vector Address associated with interrupt Q"
rbitfld.long 0x3FC 0.--1. "RES20,Reserved" "0,1,2,3"
width 0x0B
tree.end
tree "MSS_WDT (MSS WDT Module Registers)"
base ad:0x2F7A300
group.long 0x00++0x1B
line.long 0x00 "RTIGCTRL,Global Control Register starts / stops the counters"
hexmask.long.word 0x00 20.--31. 1. "RESERVED2,Reserved"
bitfld.long 0x00 16.--19. "NTUSEL,NTUSEL: Select NTU signal" "NTU0,?,?,?,?,NTU1,?,?,?,?,NTU2,?,?,?,?,NTU3 other.."
newline
bitfld.long 0x00 15. "COS,COS: Continue On Suspend" "stop counters in debug mode,continue counting in debug mode"
hexmask.long.word 0x00 2.--14. 1. "RESERVED1,Reserved"
newline
bitfld.long 0x00 1. "CNT1EN,CNT1EN: Counter 1 Enable" "stop counters,start counters Gives the absolute 32.."
bitfld.long 0x00 0. "CNT0EN,CNT0EN: Counter 0 Enable.The CNT0EN bit starts and stops the operation of counter block 0 (UC0 and FRC0)" "stop counters,start counters Gives the absolute 32.."
line.long 0x04 "RTITBCTRL,Timebase Control selection which source triggers free running counter 0"
hexmask.long 0x04 2.--31. 1. "RESERVED3,Reserved"
bitfld.long 0x04 1. "INC,INC: Increment Free Running Counter 0" "Do not increment FRC0 on failing external clock,Increment FRC0 on failing external clock"
newline
bitfld.long 0x04 0. "TBEXT,TBEXT: Timebase External" "MUX is switched to internal UC0 clocking scheme,MUX is switched to external NTUx clocking scheme"
line.long 0x08 "RTICAPCTRL,Capture Control controls the capture source for the counters"
hexmask.long 0x08 2.--31. 1. "RESERVED4,Reserved"
bitfld.long 0x08 1. "CAPCNTR1,CAPCNTR1: Capture Counter 1" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
newline
bitfld.long 0x08 0. "CAPCNTR0,CAPCNTR0: Capture Counter 0" "enable capture event triggered by Capture Event..,enable capture event triggered by Capture Event.."
line.long 0x0C "RTICOMPCTRL,Compare Control controls the source for the compare registers"
hexmask.long.tbyte 0x0C 13.--31. 1. "RESERVED8,Reserved"
bitfld.long 0x0C 12. "COMP3SEL,COMPSEL3: Compare Select 3" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 9.--11. "RESERVED7,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 8. "COMP2SEL,COMPSEL2: Compare Select 2" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 5.--7. "RESERVED6,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 4. "COMP1SEL,COMPSEL1: Compare Select 1" "enable compare with FRC 0,enable compare with FRC 1"
newline
bitfld.long 0x0C 1.--3. "RESERVED5,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x0C 0. "COMP0SEL,COMPSEL0: Compare Select 0" "enable compare with FRC 0,enable compare with FRC 1"
line.long 0x10 "RTIFRC0,Free Running Counter 0 current value of free running counter 0"
line.long 0x14 "RTIUC0,Up Counter 0 current value of prescale counter 0"
line.long 0x18 "RTICPUC0,Compare Up Counter 0 compare value compared with prescale counter 0"
group.long 0x20++0x07
line.long 0x00 "RTICAFRC0,Capture Free Running Counter 0 current value of free running counter 0 on external event"
line.long 0x04 "RTICAUC0,Capture Up Counter 0 current value of prescale counter 0 on external event"
group.long 0x30++0x0B
line.long 0x00 "RTIFRC1,Free Running Counter 1 current value of free running counter 1"
line.long 0x04 "RTIUC1,Up Counter 1 current value of prescale counter 1"
line.long 0x08 "RTICPUC1,Compare Up Counter 1 compare value compared with prescale counter 1"
group.long 0x40++0x07
line.long 0x00 "RTICAFRC1,Capture Free Running Counter 1 current value of free running counter 1 on external event"
line.long 0x04 "RTICAUC1,Capture Up Counter 1 current value of prescale counter 1 on external event"
group.long 0x50++0x27
line.long 0x00 "RTICOMP0,Compare 0 compare value to be compared with the counters"
line.long 0x04 "RTIUDCP0,Update Compare 0 value to be added to the compare register 0 value on compare match"
line.long 0x08 "RTICOMP1,Compare 1 compare value to be compared with the counters"
line.long 0x0C "RTIUDCP1,Update Compare 1 value to be added to the compare register 1 value on compare match"
line.long 0x10 "RTICOMP2,Compare 2 compare value to be compared with the counters"
line.long 0x14 "RTIUDCP2,Update Compare 2 value to be added to the compare register 2 value on compare match"
line.long 0x18 "RTICOMP3,Compare 3 compare value to be compared with the counters"
line.long 0x1C "RTIUDCP3,Update Compare 3 value to be added to the compare register 3 value on compare match"
line.long 0x20 "RTITBLCOMP,Timebase Low Compare compare value to activate edge detection circuit"
line.long 0x24 "RTITBHCOMP,Timebase High Compare compare value to deactivate edge detection circuit"
group.long 0x80++0x0B
line.long 0x00 "RTISETINT,Set Interrupt Enable sets interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x00 19.--31. 1. "RESERVED11,Reserved"
bitfld.long 0x00 18. "SETOVL1INT,SETOVL1INT: Set Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 17. "SETOVL0INT,SETOVL0INT: Set Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 16. "SETTBINT,SETTBINT: Set Timebase Interrupt" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 12.--15. "RESERVED10,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 11. "SETDMA3,SETDMA3: Set Compare DMA Request 3" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 10. "SETDMA2,SETDMA2: Set Compare DMA Request 2" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 9. "SETDMA1,SETDMA1: Set Compare DMA Request 1" "leaves the corresponding bit unchanged,enable DMA request"
newline
bitfld.long 0x00 8. "SETDMA0,SETDMA0: Set Compare DMA Request 0" "leaves the corresponding bit unchanged,enable DMA request"
bitfld.long 0x00 4.--7. "RESERVED9,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 3. "SETINT3,SETINT3: Set Compare Interrupt 3" "leaves the corresponding bit unchanged,interrupt is enabled Privilege mode (write)"
bitfld.long 0x00 2. "SETINT2,SETINT2: Set Compare Interrupt 2" "leaves the corresponding bit unchanged,enable interrupt"
newline
bitfld.long 0x00 1. "SETINT1,SETINT1: Set Compare Interrupt 1" "leaves the corresponding bit unchanged,enable interrupt"
bitfld.long 0x00 0. "SETINT0,SETINT0: Set Compare Interrupt 0" "leaves the corresponding bit unchanged,enable interrupt"
line.long 0x04 "RTICLEARINT,Clear Interrupt Enable clears interrupt enable bits int RTIINTCTRL without having to do a read-modify-write operation"
hexmask.long.word 0x04 19.--31. 1. "RESERVED14,Reserved"
bitfld.long 0x04 18. "CLEAROVL1INT,CLEAROVL1INT: CLEAR Free Running Counter 1 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 17. "CLEAROVL0INT,CLEAROVL0INT: CLEAR Free Running Counter 0 Overflow Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 16. "CLEARTBINT,CLEARTBINT: CLEAR Timebase Interrupt" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 12.--15. "RESERVED13,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 11. "CLEARDMA3,CLEARDMA3: CLEAR Compare DMA Request 3" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 10. "CLEARDMA2,CLEARDMA2: CLEAR Compare DMA Request 2" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 9. "CLEARDMA1,CLEARDMA1: CLEAR Compare DMA Request 1" "leaves the corresponding bit unchanged,disable DMA request"
newline
bitfld.long 0x04 8. "CLEARDMA0,CLEARDMA0: CLEAR Compare DMA Request 0" "leaves the corresponding bit unchanged,disable DMA request"
bitfld.long 0x04 4.--7. "RESERVED12,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 3. "CLEARINT3,CLEARINT3: CLEAR Compare Interrupt 3" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 2. "CLEARINT2,CLEARINT2: CLEAR Compare Interrupt 2" "leaves the corresponding bit unchanged,disable interrupt"
newline
bitfld.long 0x04 1. "CLEARINT1,CLEARINT1: CLEAR Compare Interrupt 1" "leaves the corresponding bit unchanged,disable interrupt"
bitfld.long 0x04 0. "CLEARINT0,CLEARINT0: CLEAR Compare Interrupt 0" "leaves the corresponding bit unchanged,disable interrupt"
line.long 0x08 "RTIINTFLAG,Interrupt Flags interrupt pending bits"
hexmask.long.word 0x08 19.--31. 1. "RESERVED16,Reserved"
bitfld.long 0x08 18. "OVL1INT,OVL1INT: Free Running Counter 1 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 17. "OVL0INT,OVL0INT: Free Running Counter 0 Overflow Interrupt Flag" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 16. "TBINT,User and privilege mode (read): this flag is set when the TBEXT bit is cleared by detection of a missing external clockedge" "leaves the bit unchanged,set the bit to 0"
newline
hexmask.long.word 0x08 4.--15. 1. "RESERVED15,Reserved"
bitfld.long 0x08 3. "INT3,INT3: Interrupt Flag 3" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 2. "INT2,INT2: Interrupt Flag 2" "leaves the bit unchanged,set the bit to 0"
bitfld.long 0x08 1. "INT1,INT1: Interrupt Flag 1" "leaves the bit unchanged,set the bit to 0"
newline
bitfld.long 0x08 0. "INT0,INT0: Interrupt Flag 0" "leaves the bit unchanged,set the bit to 0"
group.long 0x90++0x2F
line.long 0x00 "RTIDWDCTRL,Digital Watchdog Control Enables the Digital Watchdog"
line.long 0x04 "RTIDWDPRLD,Digital Watchdog Preload sets the experation time of the Digital Watchdog"
hexmask.long.tbyte 0x04 12.--31. 1. "RESERVED17,Reserved"
hexmask.long.word 0x04 0.--11. 1. "DWDPRLD,DWDPRLD: Digital Watchdog Preload Value"
line.long 0x08 "RTIWDSTATUS,Watchdog Status reflects the status of Analog and Digital Watchdog"
hexmask.long 0x08 6.--31. 1. "RESERVED18,Reserved"
bitfld.long 0x08 5. "DWWD_ST,DWWD ST: Windowed Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 4. "ENDTIMEVIOL,END TIME VIOL: Windowed Watchdog End Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 3. "STARTTIMEVIOL,START TIME VIOL: Windowed Watchdog Start Time Violation Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 2. "KEYST,KEYST: Watchdog KeyStatus" "leaves the current value unchanged,clears the bit to 0"
bitfld.long 0x08 1. "DWDST,DWDST: Digital Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
newline
bitfld.long 0x08 0. "AWDST,AWDST: Analog Watchdog Status" "leaves the current value unchanged,clears the bit to 0"
line.long 0x0C "RTIWDKEY,Watchdog Key correct written key values discharge the external capacitor"
hexmask.long.word 0x0C 16.--31. 1. "RESERVED19,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "WDKEY,WDKEY: Watchdog Key"
line.long 0x10 "RTIDWDCNTR,Digital Watchdog Down Counter current value of DWD down counter"
hexmask.long.byte 0x10 25.--31. 1. "RESERVED20,Reserved"
hexmask.long 0x10 0.--24. 1. "DWDCNTR,DWDCNTR: Digital Watchdog Down Counter"
line.long 0x14 "RTIWWDRXNCTRL,Windowed Watchdog Reaction Control configures the windowed watchdog to either generate a non-maskable interrupt to the CPU or to generate a system reset"
hexmask.long 0x14 4.--31. 1. "RESERVED21,Reserved"
bitfld.long 0x14 0.--3. "WWDRXN,WWDRXN: Digital Windowed Watchdog Reaction" "?,?,?,?,?,This is the default value,?,?,?,?,The windowed watchdog will generate a..,?..."
line.long 0x18 "RTIWWDSIZECTRL,Windowed Watchdog Size Control configures the size of the window for the digital windowed watchdog"
line.long 0x1C "RTIINTCLRENABLE,RTI Compare Interrupt Clear Enable enable the auto clear functionality for each of the compare interrupts"
bitfld.long 0x1C 28.--31. "RESERVED25,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 24.--27. "INTCLRENABLE3,INTCLRENABLE3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 20.--23. "RESERVED24,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 16.--19. "INTCLRENABLE2,INTCLRENABLE2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 12.--15. "RESERVED23,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 8.--11. "INTCLRENABLE1,INTCLRENABLE1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 4.--7. "RESERVED22,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x1C 0.--3. "INTCLRENABLE0,INTCLRENABLE0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x20 "RTICOMP0CLR,Compare 0 Clear compare value to be compared with the counter to clear the compare0 interrupt line"
line.long 0x24 "RTICOMP1CLR,Compare 1 Clear compare value to be compared with the counter to clear the compare1 interrupt line"
line.long 0x28 "RTICOMP2CLR,Compare 2 Clear compare value to be compared with the counter to clear the compare2 interrupt line"
line.long 0x2C "RTICOMP3CLR,Compare 3 Clear compare value to be compared with the counter to clear the compare3 interrupt line"
width 0x0B
tree.end
tree "RCSS_ATL (RCSS ATL Module Registers)"
base ad:0x5240000
rgroup.long 0x00++0x03
line.long 0x00 "REVISION,Peripheral Revision Register"
bitfld.long 0x00 30.--31. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x00 28.--29. "UNDEFINED_NAME," "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 11.--15. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "UNDEFINED_NAME," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x200++0x0B
line.long 0x00 "ATL0_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL0_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL0_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x210++0x0F
line.long 0x00 "ATL0_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL0_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL0_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL0_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
group.long 0x280++0x0B
line.long 0x00 "ATL1_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL1_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL1_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x290++0x0F
line.long 0x00 "ATL1_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL1_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL1_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL1_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
group.long 0x300++0x0B
line.long 0x00 "ATL2_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL2_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL2_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x310++0x0F
line.long 0x00 "ATL2_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL2_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL2_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL2_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
group.long 0x380++0x0B
line.long 0x00 "ATL3_PPMR,The PPM register is used by the Audio re-timing code"
bitfld.long 0x00 15. "UNDEFINED_NAME," "0,1"
hexmask.long.word 0x00 0.--8. 1. "UNDEFINED_NAME,This is the 9-bit parts-per-millon value in the adjusting circuit"
line.long 0x04 "ATL3_BBSR,The measuring circuit produces a 16-bit Sample Count"
hexmask.long.word 0x04 0.--15. 1. "UNDEFINED_NAME,This is the 16-bit sample count from the measuring circuit"
line.long 0x08 "ATL3_ATLCR,The modem Clock Divide Select bit is used during factory calibration of the radio to match latency between the analog and digital signal paths"
bitfld.long 0x08 5. "UNDEFINED_NAME," "0,1"
bitfld.long 0x08 0.--4. "UNDEFINED_NAME,Sets ratio of ATLPCLK to ATCLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x390++0x0F
line.long 0x00 "ATL3_SWEN,The software enable register is used to enable/disable the ATL"
bitfld.long 0x00 0. "UNDEFINED_NAME,When disabled the ATL registers are forced to known states for simulation purposes" "0,1"
line.long 0x04 "ATL3_BWSMUX,The Baseband IIS Word Select mux select control register"
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,BWS input select" "atl_io_port_bws[0],atl_io_port_bws[1],atl_io_port_bws[2],atl_io_port_bws[3],atl_io_port_bws[4],atl_io_port_bws[5],atl_io_port_bws[6],atl_io_port_bws[7],atl_io_port_bws[8],atl_io_port_bws[9],atl_io_port_bws[10],atl_io_port_bws[11],atl_io_port_bws[12],atl_io_port_bws[13],atl_io_port_bws[14],atl_io_port_bws[15]"
line.long 0x08 "ATL3_AWSMUX,The Audio IIS Word Select mux select control register"
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,AWS input select" "atl_io_port_aws[0],atl_io_port_aws[1],atl_io_port_aws[2],atl_io_port_aws[3],atl_io_port_aws[4],atl_io_port_aws[5],atl_io_port_aws[6],atl_io_port_aws[7],atl_io_port_aws[8],atl_io_port_aws[9],atl_io_port_aws[10],atl_io_port_aws[11],atl_io_port_aws[12],atl_io_port_aws[13],atl_io_port_aws[14],atl_io_port_aws[15]"
line.long 0x0C "ATL3_PCLKMUX,ATL core input clock mux select control register"
bitfld.long 0x0C 0. "UNDEFINED_NAME,ATL core clock select" "vbus_clk,atl_clk"
width 0x0B
tree.end
tree "RCSS_CSI2A (RCSS CSI2A Module Registers)"
base ad:0x5080000
rgroup.long 0x00++0x03
line.long 0x00 "CSI2_REVISION,MODULE REVISION This register contains the IP revision code in binary coded digital"
hexmask.long.tbyte 0x00 8.--31. 1. "RES1,RESERVE FIELD"
newline
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision"
group.long 0x10++0x0F
line.long 0x00 "CSI2_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES2,RESERVE FIELD"
newline
bitfld.long 0x00 12.--13. "MSTANDBY_MODE,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--11. 1. "RES3,RESERVE FIELD"
newline
bitfld.long 0x00 1. "SOFT_RESET,Software reset" "Normal mode,The module is reset"
newline
bitfld.long 0x00 0. "AUTO_IDLE,Internal OCP gating strategy" "OCP clock is free-running,Automatic OCP clock gating strategy is applied.."
line.long 0x04 "CSI2_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module excluding the interrupt status register"
hexmask.long 0x04 1.--31. 1. "RES4,RESERVE FIELD"
newline
bitfld.long 0x04 0. "RESET_DONE,Internal reset monitoring" "Internal module reset is on going,Reset completed"
line.long 0x08 "CSI2_IRQSTATUS,INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt"
hexmask.long.tbyte 0x08 15.--31. 1. "RES5,RESERVE FIELD"
newline
bitfld.long 0x08 14. "OCP_ERR_IRQ,OCP Error Interrupt" "READS,READS"
newline
bitfld.long 0x08 13. "SHORT_PACKET_IRQ,Short packet reception status (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "READS,READS"
newline
bitfld.long 0x08 12. "ECC_CORRECTION_IRQ,ECC has been used to do the correction of the only 1-bit error status (short packet only)" "READS,READS"
newline
bitfld.long 0x08 11. "ECC_NO_CORRECTION_IRQ,ECC error status (short and long packets)" "READS,READS"
newline
rbitfld.long 0x08 10. "COMPLEXIO2_ERR_IRQ,RESERVE FIELD" "0,1"
newline
bitfld.long 0x08 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: status of the PHY errors received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "READS,READS"
newline
bitfld.long 0x08 8. "FIFO_OVF_IRQ,FIFO overflow error status" "READS,READS"
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bitfld.long 0x08 7. "CONTEXT7,Context 7" "READS,READS"
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bitfld.long 0x08 6. "CONTEXT6,Context 6" "READS,READS"
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bitfld.long 0x08 5. "CONTEXT5,Context 5" "READS,READS"
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bitfld.long 0x08 4. "CONTEXT4,Context 4" "READS,READS"
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bitfld.long 0x08 3. "CONTEXT3,Context 3" "READS,READS"
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bitfld.long 0x08 2. "CONTEXT2,Context 2" "READS,READS"
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bitfld.long 0x08 1. "CONTEXT1,Context 1" "READS,READS"
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bitfld.long 0x08 0. "CONTEXT0,Context 0" "READS,READS"
line.long 0x0C "CSI2_IRQENABLE,INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually"
hexmask.long.tbyte 0x0C 15.--31. 1. "RES6,RESERVE FIELD"
newline
bitfld.long 0x0C 14. "OCP_ERR_IRQ,OCP Error Interrupt" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 13. "SHORT_PACKET_IRQ,Short packet reception (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 12. "ECC_CORRECTION_IRQ,ECC has been used to correct the only 1-bit error (short packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 11. "ECC_NO_CORRECTION_IRQ,ECC error (short and long packets)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 10. "COMPLEXIO2_ERR_IRQ,RESERVED" "0,1"
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bitfld.long 0x0C 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: the interrupt is triggered when any error is received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 8. "FIFO_OVF_IRQ,FIFO overflow enable" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 7. "CONTEXT7,Context 7" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 6. "CONTEXT6,Context 6" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 5. "CONTEXT5,Context 5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 4. "CONTEXT4,Context 4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 3. "CONTEXT3,Context 3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 2. "CONTEXT2,Context 2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 1. "CONTEXT1,Context 1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x0C 0. "CONTEXT0,Context 0" "Event is masked,Event generates an interrupt when it occurs"
group.long 0x40++0x14B
line.long 0x00 "CSI2_CTRL,GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module"
hexmask.long.word 0x00 23.--31. 1. "RES7,RESERVE FIELD"
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bitfld.long 0x00 20.--22. "MFLAG_LEVH,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 17.--19. "MFLAG_LEVL,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 16. "BURST_SIZE_EXPAND,Sets the DMA burst size on the L3 interconnect" "Use the burst size defined in the BURST_SIZE..,Allow generation of 16x64-bit bursts"
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bitfld.long 0x00 15. "VP_CLK_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 14. "STREAMING,Streaming mode" "Disable,Enable"
newline
bitfld.long 0x00 13. "NON_POSTED_WRITE,Not Posted Writes" "Disable,Enable"
newline
rbitfld.long 0x00 12. "RES8,RESERVE FIELD" "0,1"
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bitfld.long 0x00 11. "VP_ONLY_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 10. "STREAMING_32_BIT,Indicates if 64-bit or 32-bit streaming burst is used" "0,1"
newline
bitfld.long 0x00 8.--9. "VP_OUT_CTRL,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x00 7. "DBG_EN,Enables the debug mode" "Disable,Enable"
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bitfld.long 0x00 5.--6. "BURST_SIZE,Sets the DMA burst size on the L3 interconnect" "1x64 OCP writes,2x64 OCP writes,4x64 OCP writes,8x64 OCP writes"
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bitfld.long 0x00 4. "ENDIANNESS,Select endianness for YUV422 8 bit and YUV420 legacy formats" "Use native MIPI CSI2 endianness,Store all pixel formats little endian"
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bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "If IF_EN = 0 the interface is disabled immediately,If IF_EN = 1 the interface is disabled after all.."
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bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SECURE,RESERVE FIELD" "0,1"
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bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "The interface is disabled,The interface is enabled immediately the data.."
line.long 0x04 "CSI2_DBG_H,DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x08 "CSI2_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design"
hexmask.long 0x08 6.--31. 1. "RES9,RESERVE FIELD"
newline
bitfld.long 0x08 2.--5. "FIFODEPTH,Output FIFO size in multiple of 68 bits" "?,?,8x 68 bits,16x 68 bits,32x 68 bits,64x 68 bits,128 x 68 bits,256 x 68 bits,?..."
newline
bitfld.long 0x08 0.--1. "NBCONTEXTS,Number of contexts supported by the module" "1 Context,2 Contexts,4 Contexts,8 Contexts"
line.long 0x0C "CSI2_COMPLEXIO_CFG2,COMPLEX IO CONFIGURATION REGISTER for the complex IO #2 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x0C 31. "RES10,RESERVE FIELD" "0,1"
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bitfld.long 0x0C 30. "RESET_CTRL,RESERVE FIELD" "0,1"
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rbitfld.long 0x0C 29. "RESET_DONE,RESERVE FIELD" "0,1"
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bitfld.long 0x0C 27.--28. "PWR_CMD,RESERVE FIELD" "0,1,2,3"
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rbitfld.long 0x0C 25.--26. "PWR_STATUS,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x0C 24. "PWR_AUTO,RESERVE FIELD" "0,1"
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rbitfld.long 0x0C 20.--23. "RES11,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 19. "DATA4_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 16.--18. "DATA4_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 15. "DATA3_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 12.--14. "DATA3_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 11. "DATA2_POL,RESERVE FIELD" "0,1"
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bitfld.long 0x0C 8.--10. "DATA2_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x0C 7. "DATA1_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 4.--6. "DATA1_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 3. "CLOCK_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 0.--2. "CLOCK_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
line.long 0x10 "CSI2_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex IO #1 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x10 31. "RES12,RESERVE FIELD" "0,1"
newline
bitfld.long 0x10 30. "RESET_CTRL,Controls the reset of the complex IO" "Complex IO reset active,Complex IO reset de-asserted"
newline
bitfld.long 0x10 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io" "Internal module reset is on going,Reset completed"
newline
bitfld.long 0x10 27.--28. "PWR_CMD,Command for power control of the complex io" "Command to change to OFF state,Command to change to ON state,Command to change to Ultra Low Power state,?..."
newline
bitfld.long 0x10 25.--26. "PWR_STATUS,Status of the power control of the complex io" "Complex IO in OFF state,Complex IO in ON state,Complex IO in Ultra Low Power state,?..."
newline
bitfld.long 0x10 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "Disable,Enable"
newline
rbitfld.long 0x10 20.--23. "RES13,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "Not used/connected,Data lane 4 is at the position 1,Data lane 4 is at the position 2,Data lane 4 is at the position 3,Data lane 4 is at the position 4,Data lane 4 is at the position 5,?..."
newline
bitfld.long 0x10 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "Not used/connected,Data lane 3 is at the position 1,Data lane 3 is at the position 2,Data lane 3 is at the position 3,Data lane 3 is at the position 4,Data lane 3 is at the position 5,?..."
newline
bitfld.long 0x10 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "Not used/connected,Data lane 2 is at the position 1,Data lane 2 is at the position 2,Data lane 2 is at the position 3,Data lane 2 is at the position 4,Data lane 2 is at the position 5,?..."
newline
bitfld.long 0x10 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,Data lane 1 is at the position 1,Data lane 1 is at the position 2,Data lane 1 is at the position 3,Data lane 1 is at the position 4,Data lane 1 is at the position 5,?..."
newline
bitfld.long 0x10 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,Clock lane is at the position 1,Clock lane is at the position 2,Clock lane is at the position 3,Clock lane is at the position 4,Clock lane is at the position 5,?..."
line.long 0x14 "CSI2_COMPLEXIO1_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #1"
rbitfld.long 0x14 27.--31. "RES14,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x14 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "READS,READS"
newline
bitfld.long 0x14 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "READS,READS"
newline
bitfld.long 0x14 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "READS,READS"
newline
bitfld.long 0x14 19. "ERRCONTROL5,Control error for lane #5" "READS,READS"
newline
bitfld.long 0x14 18. "ERRCONTROL4,Control error for lane #4" "READS,READS"
newline
bitfld.long 0x14 17. "ERRCONTROL3,Control error for lane #3" "READS,READS"
newline
bitfld.long 0x14 16. "ERRCONTROL2,Control error for lane #2" "READS,READS"
newline
bitfld.long 0x14 15. "ERRCONTROL1,Control error for lane #1" "READS,READS"
newline
bitfld.long 0x14 14. "ERRESC5,Escape entry error for lane #5" "READS,READS"
newline
bitfld.long 0x14 13. "ERRESC4,Escape entry error for lane #4" "READS,READS"
newline
bitfld.long 0x14 12. "ERRESC3,Escape entry error for lane #3" "READS,READS"
newline
bitfld.long 0x14 11. "ERRESC2,Escape entry error for lane #2" "READS,READS"
newline
bitfld.long 0x14 10. "ERRESC1,Escape entry error for lane #1" "READS,READS"
newline
bitfld.long 0x14 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "READS,READS"
newline
bitfld.long 0x14 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "READS,READS"
newline
bitfld.long 0x14 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "READS,READS"
newline
bitfld.long 0x14 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "READS,READS"
newline
bitfld.long 0x14 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "READS,READS"
newline
bitfld.long 0x14 4. "ERRSOTHS5,Start of transmission error for lane #5" "READS,READS"
newline
bitfld.long 0x14 3. "ERRSOTHS4,Start of transmission error for lane #4" "READS,READS"
newline
bitfld.long 0x14 2. "ERRSOTHS3,Start of transmission error for lane #3" "READS,READS"
newline
bitfld.long 0x14 1. "ERRSOTHS2,Start of transmission error for lane #2" "READS,READS"
newline
bitfld.long 0x14 0. "ERRSOTHS1,Start of transmission error for lane #1" "READS,READS"
line.long 0x18 "CSI2_COMPLEXIO2_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #2"
rbitfld.long 0x18 27.--31. "RES15,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x18 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 24. "STATEULPM5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 23. "STATEULPM4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 21. "STATEULPM2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 20. "STATEULPM1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 14. "ERRESC5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 13. "ERRESC4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 12. "ERRESC3,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 11. "ERRESC2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 10. "ERRESC1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
newline
bitfld.long 0x18 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x1C "CSI2_SHORT_PACKET,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F"
hexmask.long.byte 0x1C 24.--31. 1. "RES16,RESERVE FIELD"
newline
hexmask.long.tbyte 0x1C 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD"
line.long 0x20 "CSI2_COMPLEXIO1_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #1"
rbitfld.long 0x20 27.--31. "RES17,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x20 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 19. "ERRCONTROL5,Control error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 18. "ERRCONTROL4,Control error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 17. "ERRCONTROL3,Control error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 16. "ERRCONTROL2,Control error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 15. "ERRCONTROL1,Control error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 14. "ERRESC5,Escape entry error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 13. "ERRESC4,Escape entry error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 12. "ERRESC3,Escape entry error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 11. "ERRESC2,Escape entry error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 10. "ERRESC1,Escape entry error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x20 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 4. "ERRSOTHS5,Start of transmission error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 3. "ERRSOTHS4,Start of transmission error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 2. "ERRSOTHS3,Start of transmission error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 1. "ERRSOTHS2,Start of transmission error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 0. "ERRSOTHS1,Start of transmission error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x24 "CSI2_COMPLEXIO2_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #2"
rbitfld.long 0x24 27.--31. "RES18,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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bitfld.long 0x24 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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bitfld.long 0x24 24. "STATEULPM5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 23. "STATEULPM4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 21. "STATEULPM2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 20. "STATEULPM1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 14. "ERRESC5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 13. "ERRESC4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 12. "ERRESC3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 11. "ERRESC2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 10. "ERRESC1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x28 "CSI2_DBG_P,DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x2C "CSI2_TIMING,TIMING REGISTER This register controls the CSI2 RECEIVER module"
bitfld.long 0x2C 31. "FORCE_RX_MODE_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 30. "STOP_STATE_X16_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 29. "STOP_STATE_X4_IO2,RESERVE FIELD" "0,1"
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hexmask.long.word 0x2C 16.--28. 1. "STOP_STATE_COUNTER_IO2,RESERVE FIELD"
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bitfld.long 0x2C 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal" "De-assertion of ForceRxMode,Assertion of ForceRxMode"
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bitfld.long 0x2C 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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bitfld.long 0x2C 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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hexmask.long.word 0x2C 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring"
line.long 0x30 "CSI2_CTX0_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x30 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x30 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x30 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x30 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x30 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x30 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x30 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x30 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x30 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x30 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x30 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x30 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x30 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x30 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x30 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x34 "CSI2_CTX0_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x34 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x34 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x34 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
newline
bitfld.long 0x34 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
newline
bitfld.long 0x34 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x34 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x38 "CSI2_CTX0_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x38 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x38 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
newline
rbitfld.long 0x38 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "CSI2_CTX0_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x3C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x3C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x40 "CSI2_CTX0_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x40 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x40 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "CSI2_CTX0_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x44 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x44 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x44 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x44 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x44 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x48 "CSI2_CTX0_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x48 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x48 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x48 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x48 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x48 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x48 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x48 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x48 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x48 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x48 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x4C "CSI2_CTX0_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x4C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x4C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x4C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x50 "CSI2_CTX1_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x50 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x50 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0x50 29. "RES19,RESERVE FIELD" "0,1"
newline
bitfld.long 0x50 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
newline
bitfld.long 0x50 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x50 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x50 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0x50 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0x50 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0x50 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0x50 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
newline
bitfld.long 0x50 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
newline
bitfld.long 0x50 2. "VP_FORCE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x50 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
newline
bitfld.long 0x50 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x54 "CSI2_CTX1_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x54 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x54 15. "RES20,RESERVE FIELD" "0,1"
newline
bitfld.long 0x54 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
newline
bitfld.long 0x54 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
newline
bitfld.long 0x54 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
newline
abitfld.long 0x54 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x58 "CSI2_CTX1_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x58 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x58 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x5C "CSI2_CTX1_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x5C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x5C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x60 "CSI2_CTX1_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x60 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x60 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "CSI2_CTX1_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x64 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x64 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x64 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x64 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x64 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x68 "CSI2_CTX1_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x68 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x68 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x68 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x68 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x68 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x68 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x68 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x68 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x68 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x68 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x6C "CSI2_CTX1_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x6C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x6C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x6C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x70 "CSI2_CTX2_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x70 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x70 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x70 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x70 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x70 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x70 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x70 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x70 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x70 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x70 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x70 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x70 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x70 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x70 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x70 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x74 "CSI2_CTX2_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x74 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x74 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x74 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x74 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x74 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x74 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x78 "CSI2_CTX2_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x78 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x78 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x7C "CSI2_CTX2_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x7C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x7C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x80 "CSI2_CTX2_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x80 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x80 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x84 "CSI2_CTX2_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x84 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x84 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x84 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x84 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x84 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x88 "CSI2_CTX2_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x88 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x88 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x88 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x88 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x88 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x88 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x88 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x88 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x88 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x88 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x8C "CSI2_CTX2_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x8C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x8C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x8C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x90 "CSI2_CTX3_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x90 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x90 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0x90 29. "RES19,RESERVE FIELD" "0,1"
newline
bitfld.long 0x90 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
newline
bitfld.long 0x90 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x90 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x90 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0x90 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0x90 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0x90 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0x90 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x90 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x90 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x90 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x90 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x94 "CSI2_CTX3_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x94 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x94 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x94 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x94 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x94 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x94 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x98 "CSI2_CTX3_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x98 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x98 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x9C "CSI2_CTX3_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x9C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x9C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA0 "CSI2_CTX3_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xA0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xA0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA4 "CSI2_CTX3_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xA4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0xA4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xA4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xA4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xA8 "CSI2_CTX3_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA8 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xA8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0xA8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0xA8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0xA8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0xA8 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xA8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0xA8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0xA8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0xA8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xAC "CSI2_CTX3_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xAC 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xAC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xAC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xB0 "CSI2_CTX4_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xB0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0xB0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xB0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xB0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xB0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xB0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xB0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xB0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xB0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xB0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xB0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xB0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xB0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xB4 "CSI2_CTX4_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xB4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xB4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xB4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xB4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xB4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xB4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xB8 "CSI2_CTX4_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xB8 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0xB8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xBC "CSI2_CTX4_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xBC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xBC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC0 "CSI2_CTX4_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xC0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xC0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC4 "CSI2_CTX4_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xC4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0xC4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xC4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xC4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xC8 "CSI2_CTX4_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC8 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0xC8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0xC8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0xC8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0xC8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0xC8 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0xC8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0xC8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0xC8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0xC8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xCC "CSI2_CTX4_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xCC 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0xCC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0xCC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xD0 "CSI2_CTX5_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xD0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0xD0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xD0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xD0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xD0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xD0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xD0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xD0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xD0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xD0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xD0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xD0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xD0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xD4 "CSI2_CTX5_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xD4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xD4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xD4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xD4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xD4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xD4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xD8 "CSI2_CTX5_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xD8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xD8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xDC "CSI2_CTX5_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xDC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xDC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE0 "CSI2_CTX5_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xE0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xE0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE4 "CSI2_CTX5_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xE4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0xE4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xE4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xE8 "CSI2_CTX5_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE8 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xE8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0xE8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0xE8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0xE8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0xE8 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xE8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0xE8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0xE8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0xE8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xEC "CSI2_CTX5_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xEC 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xEC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xEC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xF0 "CSI2_CTX6_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xF0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0xF0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xF0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xF0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xF0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xF0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xF0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xF0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xF0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xF0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xF0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xF0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xF0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xF0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xF0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xF4 "CSI2_CTX6_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xF4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xF4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xF4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xF4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xF4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xF4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xF8 "CSI2_CTX6_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xF8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xF8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xFC "CSI2_CTX6_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xFC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xFC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x100 "CSI2_CTX6_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x100 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x100 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x104 "CSI2_CTX6_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x104 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x104 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x104 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x104 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x108 "CSI2_CTX6_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x108 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x108 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x108 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x108 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x108 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x108 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x108 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x108 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x108 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x108 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x10C "CSI2_CTX6_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x10C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x10C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x10C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x110 "CSI2_CTX7_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x110 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x110 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x110 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x110 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x110 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x110 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x110 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x110 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x110 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x110 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x110 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x110 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x110 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x110 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x110 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x114 "CSI2_CTX7_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x114 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x114 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x114 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x114 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x114 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x114 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x118 "CSI2_CTX7_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x118 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x118 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x11C "CSI2_CTX7_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x11C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x11C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x120 "CSI2_CTX7_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x120 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x120 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x124 "CSI2_CTX7_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x124 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x124 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x124 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x124 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x124 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x128 "CSI2_CTX7_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x128 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x128 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x128 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x128 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x128 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x128 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x128 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x128 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x128 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x128 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x12C "CSI2_CTX7_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x12C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x12C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x12C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x130 "CSI2_PHY_CFG_REG0,"
hexmask.long.byte 0x130 24.--31. 1. "HS_CLK_CONFIG,Disable clock missing detector"
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hexmask.long.byte 0x130 16.--23. 1. "RESERVED,RESERVED"
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hexmask.long.byte 0x130 8.--15. 1. "THS_TERM,Ths-term timing parameter in multiples of DDR clock"
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hexmask.long.byte 0x130 0.--7. 1. "THS_SETTLE,THS-SETTLE timing parameter in multiples on DDR clock frequency"
line.long 0x134 "CSI2_PHY_CFG_REG1,"
bitfld.long 0x134 30.--31. "RSVD2,Reserved" "0,1,2,3"
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rbitfld.long 0x134 29. "RESETDONECTRLCLK,RESETDONECTRLCLK" "0,1"
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rbitfld.long 0x134 28. "RESETDONERXBYTECLK,RESETDONERXBYTECLK" "0,1"
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bitfld.long 0x134 26.--27. "RSVD1,Reserved" "0,1,2,3"
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rbitfld.long 0x134 25. "CLK_MISS_DET," "0,1"
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hexmask.long.byte 0x134 18.--24. 1. "TCLK_TERM,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + TCLK_TERM + ~ (1-15) ns Programmed value = ceil(9.5.."
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hexmask.long.byte 0x134 10.--17. 1. "D_PHY_HS_SYNC_PAT,DPHY mode HS sync pattern in byte order (reverse of RW 0xB8 received order) D-PHY mode sync pattern"
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bitfld.long 0x134 8.--9. "CTRLCLK_DIV_FACT,Divide factor for CTRLCLK for CLKMISS detector" "0,1,2,3"
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hexmask.long.byte 0x134 0.--7. 1. "TCLK_SETTLE,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~(1-2)* CTRLCLK + Tclk-settle + ~ (1 -15) ns Programmed value = max[3 ceil(155.."
line.long 0x138 "CSI2_PHY_CFG_REG2,"
bitfld.long 0x138 30.--31. "RXTRIGGERESC0,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "0,1,2,3"
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bitfld.long 0x138 28.--29. "RXTRIGGERESC1,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "0,1,2,3"
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bitfld.long 0x138 26.--27. "RXTRIGGERESC2,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2" "0,1,2,3"
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bitfld.long 0x138 24.--25. "RXTRIGGERESC3,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "0,1,2,3"
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hexmask.long.tbyte 0x138 0.--23. 1. "CCP2_SYNC_PAT,CCP2 mode sync pattern in byte order (reverse of received order)"
line.long 0x13C "CSI2_PHY_CFG_REG3,"
bitfld.long 0x13C 31. "OVR_ENHSRX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 26.--30. "ENHSRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 25. "OVR_ENRXTERM,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 20.--24. "ENRXTERM,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 19. "OVR_ENLPRX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 14.--18. "ENLPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 9.--13. "ENULPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x13C 8. "OVR_ENLDO,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 7. "ENLDO,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 6. "OVR_ENBIAS,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 5. "ENBIAS,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 4. "OVR_ENCCP_TO_ANAT,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 3. "OVR_ENCCP_TO_HSRX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 2. "RSVD1,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 1. "RECAL_HS_RX,RESERVE FIELD" "0,1"
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bitfld.long 0x13C 0. "RECAL_BIAS,RESERVE FIELD" "0,1"
line.long 0x140 "CSI2_PHY_CFG_REG4,"
bitfld.long 0x140 27.--31. "TRIM_BIAS_GEN,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 22.--26. "TRIM_TERM_LANE4,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 17.--21. "TRIM_TERM_LANE3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 12.--16. "TRIM_TERM_LANE2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 7.--11. "TRIM_TERM_LANE1,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 2.--6. "TRIM_TERM_LANE0,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x140 1. "BYPASS_EFUSE,RESERVE FIELD" "0,1"
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bitfld.long 0x140 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x144 "CSI2_PHY_CFG_REG5,"
bitfld.long 0x144 26.--31. "TRIM_OFFSET_LANE4_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 20.--25. "TRIM_OFFSET_LANE3_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 14.--19. "TRIM_OFFSET_LANE2_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 8.--13. "TRIM_OFFSET_LANE1_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 2.--7. "TRIM_OFFSET_LANE0_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x144 1. "BYPASS_CALIB_OFFSET,RESERVE FIELD" "0,1"
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bitfld.long 0x144 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x148 "CSI2_PHY_CFG_REG6,"
hexmask.long.word 0x148 21.--31. 1. "RSVD2,RESERVE FIELD"
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bitfld.long 0x148 20. "OVR_AFE_LANE_ADR_POL,RESERVE FIELD" "0,1"
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hexmask.long.byte 0x148 12.--19. 1. "AFE_LANE_SEL,RESERVE FIELD"
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bitfld.long 0x148 11. "AFE_LANE_POL,RESERVE FIELD" "0,1"
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bitfld.long 0x148 10. "HSCOMOOUT,RESERVE FIELD" "0,1"
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bitfld.long 0x148 9. "BYPASS_LDO_REG,RESERVE FIELD" "0,1"
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bitfld.long 0x148 8. "OBSV_LDO_VOLT_DYA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 7. "OBSV_BIAS_CURR_DXA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 6. "RSVD1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 5. "BIASGEN_CAL_OVR,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 0.--4. "BIASGEN_CAL_OVR_VAL,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C0++0x3F
line.long 0x00 "CSI2_CTX0_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x00 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x00 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x04 "CSI2_CTX0_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x04 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x04 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x08 "CSI2_CTX1_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x08 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x08 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x0C "CSI2_CTX1_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x0C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x0C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x10 "CSI2_CTX2_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x10 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x10 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x14 "CSI2_CTX2_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x14 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x14 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x18 "CSI2_CTX3_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x18 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x18 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x1C "CSI2_CTX3_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x1C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x1C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x20 "CSI2_CTX4_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x20 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x20 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x24 "CSI2_CTX4_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x24 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x24 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x28 "CSI2_CTX5_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x28 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x28 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x2C "CSI2_CTX5_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x2C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x2C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x30 "CSI2_CTX6_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x30 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x30 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x34 "CSI2_CTX6_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x34 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x34 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x38 "CSI2_CTX7_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x38 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x38 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x3C "CSI2_CTX7_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x3C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x3C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
width 0x0B
tree.end
tree "RCSS_CSI2B (RCSS CSI2B Module Registers)"
base ad:0x50A0000
rgroup.long 0x00++0x03
line.long 0x00 "CSI2_REVISION,MODULE REVISION This register contains the IP revision code in binary coded digital"
hexmask.long.tbyte 0x00 8.--31. 1. "RES1,RESERVE FIELD"
newline
hexmask.long.byte 0x00 0.--7. 1. "REV,IP revision [7:4] Major revision [3:0] Minor revision"
group.long 0x10++0x0F
line.long 0x00 "CSI2_SYSCONFIG,SYSTEM CONFIGURATION REGISTER This register is the OCP-socket system configuration register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES2,RESERVE FIELD"
newline
bitfld.long 0x00 12.--13. "MSTANDBY_MODE,RESERVE FIELD" "0,1,2,3"
newline
hexmask.long.word 0x00 2.--11. 1. "RES3,RESERVE FIELD"
newline
bitfld.long 0x00 1. "SOFT_RESET,Software reset" "Normal mode,The module is reset"
newline
bitfld.long 0x00 0. "AUTO_IDLE,Internal OCP gating strategy" "OCP clock is free-running,Automatic OCP clock gating strategy is applied.."
line.long 0x04 "CSI2_SYSSTATUS,SYSTEM STATUS REGISTER This register provides status information about the module excluding the interrupt status register"
hexmask.long 0x04 1.--31. 1. "RES4,RESERVE FIELD"
newline
bitfld.long 0x04 0. "RESET_DONE,Internal reset monitoring" "Internal module reset is on going,Reset completed"
line.long 0x08 "CSI2_IRQSTATUS,INTERRUPT STATUS REGISTER - All contexts This register associates one bit for each context in order to determine which context has generated the interrupt"
hexmask.long.tbyte 0x08 15.--31. 1. "RES5,RESERVE FIELD"
newline
bitfld.long 0x08 14. "OCP_ERR_IRQ,OCP Error Interrupt" "READS,READS"
newline
bitfld.long 0x08 13. "SHORT_PACKET_IRQ,Short packet reception status (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "READS,READS"
newline
bitfld.long 0x08 12. "ECC_CORRECTION_IRQ,ECC has been used to do the correction of the only 1-bit error status (short packet only)" "READS,READS"
newline
bitfld.long 0x08 11. "ECC_NO_CORRECTION_IRQ,ECC error status (short and long packets)" "READS,READS"
newline
rbitfld.long 0x08 10. "COMPLEXIO2_ERR_IRQ,RESERVE FIELD" "0,1"
newline
bitfld.long 0x08 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: status of the PHY errors received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "READS,READS"
newline
bitfld.long 0x08 8. "FIFO_OVF_IRQ,FIFO overflow error status" "READS,READS"
newline
bitfld.long 0x08 7. "CONTEXT7,Context 7" "READS,READS"
newline
bitfld.long 0x08 6. "CONTEXT6,Context 6" "READS,READS"
newline
bitfld.long 0x08 5. "CONTEXT5,Context 5" "READS,READS"
newline
bitfld.long 0x08 4. "CONTEXT4,Context 4" "READS,READS"
newline
bitfld.long 0x08 3. "CONTEXT3,Context 3" "READS,READS"
newline
bitfld.long 0x08 2. "CONTEXT2,Context 2" "READS,READS"
newline
bitfld.long 0x08 1. "CONTEXT1,Context 1" "READS,READS"
newline
bitfld.long 0x08 0. "CONTEXT0,Context 0" "READS,READS"
line.long 0x0C "CSI2_IRQENABLE,INTERRUPT ENABLE REGISTER - All contexts This register associates one bit for each context in order to enable/disable each context individually"
hexmask.long.tbyte 0x0C 15.--31. 1. "RES6,RESERVE FIELD"
newline
bitfld.long 0x0C 14. "OCP_ERR_IRQ,OCP Error Interrupt" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 13. "SHORT_PACKET_IRQ,Short packet reception (other than synch events: Line Start Line End Frame Start and Frame End: data type between 0x8 and x0F only shall be considered)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 12. "ECC_CORRECTION_IRQ,ECC has been used to correct the only 1-bit error (short packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 11. "ECC_NO_CORRECTION_IRQ,ECC error (short and long packets)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 10. "COMPLEXIO2_ERR_IRQ,RESERVED" "0,1"
newline
bitfld.long 0x0C 9. "COMPLEXIO1_ERR_IRQ,Error signaling from Complex IO #1: the interrupt is triggered when any error is received from the complex IO #1 (events are defined in CSI2_COMPLEXIO1_IRQSTATUS for the 1st complex IO)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 8. "FIFO_OVF_IRQ,FIFO overflow enable" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 7. "CONTEXT7,Context 7" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 6. "CONTEXT6,Context 6" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 5. "CONTEXT5,Context 5" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 4. "CONTEXT4,Context 4" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 3. "CONTEXT3,Context 3" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 2. "CONTEXT2,Context 2" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 1. "CONTEXT1,Context 1" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x0C 0. "CONTEXT0,Context 0" "Event is masked,Event generates an interrupt when it occurs"
group.long 0x40++0x14B
line.long 0x00 "CSI2_CTRL,GLOBAL CONTROL REGISTER This register controls the CSI2 RECEIVER module"
hexmask.long.word 0x00 23.--31. 1. "RES7,RESERVE FIELD"
newline
bitfld.long 0x00 20.--22. "MFLAG_LEVH,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 17.--19. "MFLAG_LEVL,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 16. "BURST_SIZE_EXPAND,Sets the DMA burst size on the L3 interconnect" "Use the burst size defined in the BURST_SIZE..,Allow generation of 16x64-bit bursts"
newline
bitfld.long 0x00 15. "VP_CLK_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 14. "STREAMING,Streaming mode" "Disable,Enable"
newline
bitfld.long 0x00 13. "NON_POSTED_WRITE,Not Posted Writes" "Disable,Enable"
newline
rbitfld.long 0x00 12. "RES8,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 11. "VP_ONLY_EN,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 10. "STREAMING_32_BIT,Indicates if 64-bit or 32-bit streaming burst is used" "0,1"
newline
bitfld.long 0x00 8.--9. "VP_OUT_CTRL,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x00 7. "DBG_EN,Enables the debug mode" "Disable,Enable"
newline
bitfld.long 0x00 5.--6. "BURST_SIZE,Sets the DMA burst size on the L3 interconnect" "1x64 OCP writes,2x64 OCP writes,4x64 OCP writes,8x64 OCP writes"
newline
bitfld.long 0x00 4. "ENDIANNESS,Select endianness for YUV422 8 bit and YUV420 legacy formats" "Use native MIPI CSI2 endianness,Store all pixel formats little endian"
newline
bitfld.long 0x00 3. "FRAME,Set the modality in which IF_EN works" "If IF_EN = 0 the interface is disabled immediately,If IF_EN = 1 the interface is disabled after all.."
newline
bitfld.long 0x00 2. "ECC_EN,Enables the Error Correction Code check for the received header (short and long packets for all virtual channel ids)" "Disabled,Enabled"
newline
bitfld.long 0x00 1. "SECURE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 0. "IF_EN,Enables the physical interface to the module" "The interface is disabled,The interface is enabled immediately the data.."
line.long 0x04 "CSI2_DBG_H,DEBUG REGISTER (Header) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x08 "CSI2_GNQ,GENERIC PARAMETER REGISTER This register provide a way to read the generic parameters used in the design"
hexmask.long 0x08 6.--31. 1. "RES9,RESERVE FIELD"
newline
bitfld.long 0x08 2.--5. "FIFODEPTH,Output FIFO size in multiple of 68 bits" "?,?,8x 68 bits,16x 68 bits,32x 68 bits,64x 68 bits,128 x 68 bits,256 x 68 bits,?..."
newline
bitfld.long 0x08 0.--1. "NBCONTEXTS,Number of contexts supported by the module" "1 Context,2 Contexts,4 Contexts,8 Contexts"
line.long 0x0C "CSI2_COMPLEXIO_CFG2,COMPLEX IO CONFIGURATION REGISTER for the complex IO #2 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x0C 31. "RES10,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 30. "RESET_CTRL,RESERVE FIELD" "0,1"
newline
rbitfld.long 0x0C 29. "RESET_DONE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 27.--28. "PWR_CMD,RESERVE FIELD" "0,1,2,3"
newline
rbitfld.long 0x0C 25.--26. "PWR_STATUS,RESERVE FIELD" "0,1,2,3"
newline
bitfld.long 0x0C 24. "PWR_AUTO,RESERVE FIELD" "0,1"
newline
rbitfld.long 0x0C 20.--23. "RES11,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x0C 19. "DATA4_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 16.--18. "DATA4_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 15. "DATA3_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 12.--14. "DATA3_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 11. "DATA2_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 8.--10. "DATA2_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 7. "DATA1_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 4.--6. "DATA1_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x0C 3. "CLOCK_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x0C 0.--2. "CLOCK_POSITION,RESERVE FIELD" "0,1,2,3,4,5,6,7"
line.long 0x10 "CSI2_COMPLEXIO_CFG1,COMPLEXIO CONFIGURATION REGISTER for the complex IO #1 This register contains the lane configuration for the order and position of the lanes (clock and data) and the polarity order for the control of the PHY differential signals in.."
rbitfld.long 0x10 31. "RES12,RESERVE FIELD" "0,1"
newline
bitfld.long 0x10 30. "RESET_CTRL,Controls the reset of the complex IO" "Complex IO reset active,Complex IO reset de-asserted"
newline
bitfld.long 0x10 29. "RESET_DONE,Internal reset monitoring of the power domain using the PPI byte clock from the complex io" "Internal module reset is on going,Reset completed"
newline
bitfld.long 0x10 27.--28. "PWR_CMD,Command for power control of the complex io" "Command to change to OFF state,Command to change to ON state,Command to change to Ultra Low Power state,?..."
newline
bitfld.long 0x10 25.--26. "PWR_STATUS,Status of the power control of the complex io" "Complex IO in OFF state,Complex IO in ON state,Complex IO in Ultra Low Power state,?..."
newline
bitfld.long 0x10 24. "PWR_AUTO,Automatic switch between ULP and ON states based on ULPM signals from complex iO" "Disable,Enable"
newline
rbitfld.long 0x10 20.--23. "RES13,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x10 19. "DATA4_POL,+/- differential pin order of DATA lane 4" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 16.--18. "DATA4_POSITION,Position and order of the DATA lane 4" "Not used/connected,Data lane 4 is at the position 1,Data lane 4 is at the position 2,Data lane 4 is at the position 3,Data lane 4 is at the position 4,Data lane 4 is at the position 5,?..."
newline
bitfld.long 0x10 15. "DATA3_POL,+/- differential pin order of DATA lane 3" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 12.--14. "DATA3_POSITION,Position and order of the DATA lane 3" "Not used/connected,Data lane 3 is at the position 1,Data lane 3 is at the position 2,Data lane 3 is at the position 3,Data lane 3 is at the position 4,Data lane 3 is at the position 5,?..."
newline
bitfld.long 0x10 11. "DATA2_POL,+/- differential pin order of DATA lane 2" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 8.--10. "DATA2_POSITION,Position and order of the DATA lane 2" "Not used/connected,Data lane 2 is at the position 1,Data lane 2 is at the position 2,Data lane 2 is at the position 3,Data lane 2 is at the position 4,Data lane 2 is at the position 5,?..."
newline
bitfld.long 0x10 7. "DATA1_POL,+/- differential pin order of DATA lane 1" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 4.--6. "DATA1_POSITION,Position and order of the DATA lane 1" "?,Data lane 1 is at the position 1,Data lane 1 is at the position 2,Data lane 1 is at the position 3,Data lane 1 is at the position 4,Data lane 1 is at the position 5,?..."
newline
bitfld.long 0x10 3. "CLOCK_POL,+/- differential pin order of CLOCK lane" "+/- pin order,-/+ pin order"
newline
bitfld.long 0x10 0.--2. "CLOCK_POSITION,Position and order of the CLOCK lane" "?,Clock lane is at the position 1,Clock lane is at the position 2,Clock lane is at the position 3,Clock lane is at the position 4,Clock lane is at the position 5,?..."
line.long 0x14 "CSI2_COMPLEXIO1_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #1"
rbitfld.long 0x14 27.--31. "RES14,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x14 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "READS,READS"
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bitfld.long 0x14 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "READS,READS"
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bitfld.long 0x14 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "READS,READS"
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bitfld.long 0x14 19. "ERRCONTROL5,Control error for lane #5" "READS,READS"
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bitfld.long 0x14 18. "ERRCONTROL4,Control error for lane #4" "READS,READS"
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bitfld.long 0x14 17. "ERRCONTROL3,Control error for lane #3" "READS,READS"
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bitfld.long 0x14 16. "ERRCONTROL2,Control error for lane #2" "READS,READS"
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bitfld.long 0x14 15. "ERRCONTROL1,Control error for lane #1" "READS,READS"
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bitfld.long 0x14 14. "ERRESC5,Escape entry error for lane #5" "READS,READS"
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bitfld.long 0x14 13. "ERRESC4,Escape entry error for lane #4" "READS,READS"
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bitfld.long 0x14 12. "ERRESC3,Escape entry error for lane #3" "READS,READS"
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bitfld.long 0x14 11. "ERRESC2,Escape entry error for lane #2" "READS,READS"
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bitfld.long 0x14 10. "ERRESC1,Escape entry error for lane #1" "READS,READS"
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bitfld.long 0x14 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "READS,READS"
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bitfld.long 0x14 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "READS,READS"
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bitfld.long 0x14 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "READS,READS"
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bitfld.long 0x14 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "READS,READS"
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bitfld.long 0x14 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "READS,READS"
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bitfld.long 0x14 4. "ERRSOTHS5,Start of transmission error for lane #5" "READS,READS"
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bitfld.long 0x14 3. "ERRSOTHS4,Start of transmission error for lane #4" "READS,READS"
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bitfld.long 0x14 2. "ERRSOTHS3,Start of transmission error for lane #3" "READS,READS"
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bitfld.long 0x14 1. "ERRSOTHS2,Start of transmission error for lane #2" "READS,READS"
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bitfld.long 0x14 0. "ERRSOTHS1,Start of transmission error for lane #1" "READS,READS"
line.long 0x18 "CSI2_COMPLEXIO2_IRQSTATUS,INTERRUPT STATUS REGISTER - All errors from complex IO #2"
rbitfld.long 0x18 27.--31. "RES15,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x18 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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bitfld.long 0x18 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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bitfld.long 0x18 24. "STATEULPM5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 23. "STATEULPM4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 21. "STATEULPM2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 20. "STATEULPM1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 14. "ERRESC5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 13. "ERRESC4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 12. "ERRESC3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 11. "ERRESC2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 10. "ERRESC1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
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bitfld.long 0x18 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x18 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x18 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x18 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x18 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x1C "CSI2_SHORT_PACKET,SHORT PACKET INFORMATION - This register sets the 24-bit DATA_ID + Short Packet Data Field when the data type is between 0x8 and x0F"
hexmask.long.byte 0x1C 24.--31. 1. "RES16,RESERVE FIELD"
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hexmask.long.tbyte 0x1C 0.--23. 1. "SHORT_PACKET,Short Packet information: DATA ID + DATA FIELD"
line.long 0x20 "CSI2_COMPLEXIO1_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #1"
rbitfld.long 0x20 27.--31. "RES17,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x20 26. "STATEALLULPMEXIT,At least one of the active lanes has exit the ULPM" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 25. "STATEALLULPMENTER,All active lanes are entering in ULPM" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 24. "STATEULPM5,Lane #5 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 23. "STATEULPM4,Lane #4 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 22. "STATEULPM3,Lane #3 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 21. "STATEULPM2,Lane #2 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 20. "STATEULPM1,Lane #1 in Ultra Low Power Mode" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 19. "ERRCONTROL5,Control error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 18. "ERRCONTROL4,Control error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 17. "ERRCONTROL3,Control error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 16. "ERRCONTROL2,Control error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 15. "ERRCONTROL1,Control error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 14. "ERRESC5,Escape entry error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 13. "ERRESC4,Escape entry error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 12. "ERRESC3,Escape entry error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 11. "ERRESC2,Escape entry error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 10. "ERRESC1,Escape entry error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 9. "ERRSOTSYNCHS5,Start of transmission sync error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 8. "ERRSOTSYNCHS4,Start of transmission sync error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 7. "ERRSOTSYNCHS3,Start of transmission sync error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 6. "ERRSOTSYNCHS2,Start of transmission sync error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 5. "ERRSOTSYNCHS1,Start of transmission sync error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 4. "ERRSOTHS5,Start of transmission error for lane #5" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 3. "ERRSOTHS4,Start of transmission error for lane #4" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 2. "ERRSOTHS3,Start of transmission error for lane #3" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 1. "ERRSOTHS2,Start of transmission error for lane #2" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x20 0. "ERRSOTHS1,Start of transmission error for lane #1" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x24 "CSI2_COMPLEXIO2_IRQENABLE,INTERRUPT ENABLE REGISTER - All errors from complex IO #2"
rbitfld.long 0x24 27.--31. "RES18,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x24 26. "STATEALLULPMEXIT,RESERVE FIELD" "0,1"
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bitfld.long 0x24 25. "STATEALLULPMENTER,RESERVE FIELD" "0,1"
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bitfld.long 0x24 24. "STATEULPM5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 23. "STATEULPM4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 22. "STATEULPM3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 21. "STATEULPM2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 20. "STATEULPM1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 19. "ERRCONTROL5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 18. "ERRCONTROL4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 17. "ERRCONTROL3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 16. "ERRCONTROL2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 15. "ERRCONTROL1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 14. "ERRESC5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 13. "ERRESC4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 12. "ERRESC3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 11. "ERRESC2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 10. "ERRESC1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 9. "ERRSOTSYNCHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 8. "ERRSOTSYNCHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 7. "ERRSOTSYNCHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 6. "ERRSOTSYNCHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 5. "ERRSOTSYNCHS1,RESERVE FIELD" "0,1"
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bitfld.long 0x24 4. "ERRSOTHS5,RESERVE FIELD" "0,1"
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bitfld.long 0x24 3. "ERRSOTHS4,RESERVE FIELD" "0,1"
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bitfld.long 0x24 2. "ERRSOTHS3,RESERVE FIELD" "0,1"
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bitfld.long 0x24 1. "ERRSOTHS2,RESERVE FIELD" "0,1"
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bitfld.long 0x24 0. "ERRSOTHS1,RESERVE FIELD" "0,1"
line.long 0x28 "CSI2_DBG_P,DEBUG REGISTER (Payload) This register provides a way to debug the CSI2 RECEIVER module with no image sensor connected to the module"
line.long 0x2C "CSI2_TIMING,TIMING REGISTER This register controls the CSI2 RECEIVER module"
bitfld.long 0x2C 31. "FORCE_RX_MODE_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 30. "STOP_STATE_X16_IO2,RESERVE FIELD" "0,1"
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bitfld.long 0x2C 29. "STOP_STATE_X4_IO2,RESERVE FIELD" "0,1"
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hexmask.long.word 0x2C 16.--28. 1. "STOP_STATE_COUNTER_IO2,RESERVE FIELD"
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bitfld.long 0x2C 15. "FORCE_RX_MODE_IO1,Control of ForceRxMode signal" "De-assertion of ForceRxMode,Assertion of ForceRxMode"
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bitfld.long 0x2C 14. "STOP_STATE_X16_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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bitfld.long 0x2C 13. "STOP_STATE_X4_IO1,Multiplication factor for the number of L3 cycles defined in STOP_STATE_COUNTER bit-field" "The number of L3 cycles defined in STOP_STATE..,The number of L3 cycles defined in STOP_STATE.."
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hexmask.long.word 0x2C 0.--12. 1. "STOP_STATE_COUNTER_IO1,Stop State counter for monitoring"
line.long 0x30 "CSI2_CTX0_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x30 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x30 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x30 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x30 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x30 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x30 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x30 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x30 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x30 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x30 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x30 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x30 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x30 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x30 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x30 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x34 "CSI2_CTX0_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x34 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x34 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x34 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x34 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x34 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x34 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x38 "CSI2_CTX0_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x38 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x38 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
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rbitfld.long 0x38 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x3C "CSI2_CTX0_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x3C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x3C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x40 "CSI2_CTX0_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x40 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x40 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x44 "CSI2_CTX0_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x44 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x44 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x44 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x44 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x44 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x48 "CSI2_CTX0_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x48 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x48 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x48 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x48 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x48 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x48 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x48 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x48 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x48 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x48 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x4C "CSI2_CTX0_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x4C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x4C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x4C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x50 "CSI2_CTX1_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x50 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x50 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x50 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x50 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x50 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x50 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x50 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x50 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x50 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x50 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x50 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x50 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x50 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x50 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x50 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x54 "CSI2_CTX1_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x54 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x54 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x54 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x54 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x54 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x54 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x58 "CSI2_CTX1_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x58 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x58 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x5C "CSI2_CTX1_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x5C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x5C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x60 "CSI2_CTX1_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x60 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x60 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "CSI2_CTX1_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x64 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x64 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x64 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x64 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x64 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x68 "CSI2_CTX1_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x68 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x68 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x68 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x68 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x68 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x68 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x68 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x68 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x68 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x68 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x6C "CSI2_CTX1_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x6C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x6C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x6C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x70 "CSI2_CTX2_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x70 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x70 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0x70 29. "RES19,RESERVE FIELD" "0,1"
newline
bitfld.long 0x70 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
newline
bitfld.long 0x70 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x70 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x70 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0x70 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0x70 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0x70 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0x70 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
newline
bitfld.long 0x70 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
newline
bitfld.long 0x70 2. "VP_FORCE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x70 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
newline
bitfld.long 0x70 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x74 "CSI2_CTX2_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x74 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x74 15. "RES20,RESERVE FIELD" "0,1"
newline
bitfld.long 0x74 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
newline
bitfld.long 0x74 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
newline
bitfld.long 0x74 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
newline
abitfld.long 0x74 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x78 "CSI2_CTX2_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x78 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x78 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x7C "CSI2_CTX2_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x7C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x7C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x80 "CSI2_CTX2_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x80 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x80 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x84 "CSI2_CTX2_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x84 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x84 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x84 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x84 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x84 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x88 "CSI2_CTX2_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x88 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x88 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x88 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x88 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x88 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x88 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x88 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x88 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x88 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x88 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x8C "CSI2_CTX2_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x8C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x8C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x8C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x90 "CSI2_CTX3_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x90 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0x90 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x90 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x90 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x90 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0x90 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0x90 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x90 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x90 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x90 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x90 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x90 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x90 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x90 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x90 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x94 "CSI2_CTX3_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x94 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0x94 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x94 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x94 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x94 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0x94 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x98 "CSI2_CTX3_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x98 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0x98 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x9C "CSI2_CTX3_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x9C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x9C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA0 "CSI2_CTX3_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xA0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xA0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xA4 "CSI2_CTX3_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xA4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0xA4 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0xA4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xA4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xA8 "CSI2_CTX3_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xA8 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0xA8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0xA8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0xA8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0xA8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0xA8 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0xA8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0xA8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0xA8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0xA8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xAC "CSI2_CTX3_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xAC 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0xAC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xAC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xB0 "CSI2_CTX4_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xB0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0xB0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
newline
rbitfld.long 0xB0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xB0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0xB0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0xB0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
newline
bitfld.long 0xB0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
newline
bitfld.long 0xB0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
newline
bitfld.long 0xB0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0xB0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xB0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xB0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xB0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xB0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xB4 "CSI2_CTX4_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xB4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xB4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xB4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xB4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xB4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xB4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xB8 "CSI2_CTX4_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xB8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xB8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xBC "CSI2_CTX4_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xBC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xBC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC0 "CSI2_CTX4_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xC0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xC0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xC4 "CSI2_CTX4_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xC4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0xC4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xC4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xC4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xC8 "CSI2_CTX4_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xC8 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0xC8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0xC8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0xC8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0xC8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0xC8 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0xC8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0xC8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0xC8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0xC8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xCC "CSI2_CTX4_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xCC 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0xCC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0xCC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xD0 "CSI2_CTX5_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xD0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
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bitfld.long 0xD0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xD0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xD0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
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hexmask.long.byte 0xD0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xD0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xD0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xD0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xD0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0xD0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xD0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xD0 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0xD0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xD0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xD4 "CSI2_CTX5_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xD4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xD4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xD4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xD4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xD4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xD4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xD8 "CSI2_CTX5_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xD8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xD8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xDC "CSI2_CTX5_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xDC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xDC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE0 "CSI2_CTX5_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xE0 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xE0 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0xE4 "CSI2_CTX5_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE4 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0xE4 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0xE4 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0xE4 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0xE4 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0xE4 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0xE8 "CSI2_CTX5_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0xE8 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0xE8 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0xE8 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0xE8 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0xE8 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0xE8 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0xE8 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0xE8 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0xE8 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0xE8 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0xEC "CSI2_CTX5_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0xEC 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0xEC 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0xEC 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0xF0 "CSI2_CTX6_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0xF0 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0xF0 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0xF0 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0xF0 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0xF0 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0xF0 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
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abitfld.long 0xF0 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0xF0 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0xF0 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0xF0 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
newline
bitfld.long 0xF0 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0xF0 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0xF0 2. "VP_FORCE,RESERVE FIELD" "0,1"
newline
bitfld.long 0xF0 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0xF0 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0xF4 "CSI2_CTX6_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0xF4 16.--31. 1. "FRAME,Frame number"
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rbitfld.long 0xF4 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0xF4 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0xF4 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0xF4 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
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abitfld.long 0xF4 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0xF8 "CSI2_CTX6_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0xF8 17.--31. 1. "RES21,RESERVE FIELD"
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hexmask.long.word 0xF8 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0xFC "CSI2_CTX6_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0xFC 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0xFC 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x100 "CSI2_CTX6_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x100 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
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rbitfld.long 0x100 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x104 "CSI2_CTX6_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x104 9.--31. 1. "RES22,RESERVE FIELD"
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bitfld.long 0x104 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x104 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x104 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
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rbitfld.long 0x104 4. "RES23,RESERVE FIELD" "0,1"
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bitfld.long 0x104 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
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bitfld.long 0x104 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x108 "CSI2_CTX6_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x108 9.--31. 1. "RES24,RESERVE FIELD"
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bitfld.long 0x108 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
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bitfld.long 0x108 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
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bitfld.long 0x108 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
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bitfld.long 0x108 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
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rbitfld.long 0x108 4. "RES25,RESERVE FIELD" "0,1"
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bitfld.long 0x108 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
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bitfld.long 0x108 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
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bitfld.long 0x108 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
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bitfld.long 0x108 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x10C "CSI2_CTX6_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x10C 30.--31. "Reserved,Reserved" "0,1,2,3"
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hexmask.long.word 0x10C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
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hexmask.long.word 0x10C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x110 "CSI2_CTX7_CTRL1,CONTROL REGISTER - Context This register controls the Context"
bitfld.long 0x110 31. "BYTESWAP,Allows swapping bytes two by two in the payload data" "Disabled,Enabled"
newline
bitfld.long 0x110 30. "GENERIC,Enables the generic mode" "Disabled,Enabled"
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rbitfld.long 0x110 29. "RES19,RESERVE FIELD" "0,1"
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bitfld.long 0x110 28. "HSCALE,Enable horizontal downscaling by a factor of two" "Disable,Enable"
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bitfld.long 0x110 24.--27. "TRANSCODE,Enables image transcoding" "Feature disabled,Outputs DPCM compressed RAW10 data,Outputs DPCM compressed RAW12 data,Outputs ALAW compressed RAW10 data,Outputs uncompressed RAW8 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW10 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW12 data,Outputs uncompressed RAW14 data,?..."
newline
hexmask.long.byte 0x110 16.--23. 1. "FEC_NUMBER,Number of FEC to receive between using swap of CSI2_CTX_DAT_PING_ADDR and CSI2_CTX_DAT_PONG_ADDR for the calculation of the address in memory"
newline
abitfld.long 0x110 8.--15. "COUNT,Sets the number of frame to acquire" "0x00=Infinite number of frames (no count),0x01=1 frame to acquire,0xFF=255 frames to acquire"
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bitfld.long 0x110 7. "EOF_EN,Indicates if the end of frame signal shall be asserted at the end of the frame" "The end of frame signal is not asserted at the..,The end of frame signal is asserted at the end.."
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bitfld.long 0x110 6. "EOL_EN,Indicates if the end of line signal shall be asserted at the end of the line" "The end of line signal is not asserted at the..,The end of line signal is asserted at the end of.."
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bitfld.long 0x110 5. "CS_EN,Enables the checksum check for the received payload (long packet only)" "Disabled,Enabled"
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bitfld.long 0x110 4. "COUNT_UNLOCK,Unlock writes to the COUNT bit field" "COUNT bit field is locked,COUNT bit field is unlocked"
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bitfld.long 0x110 3. "PING_PONG,Indicates whether the PING or PONG destination address (CSI2_CTX_DAT_PING_ADDR or CSI2_CTX_DAT_PONG_ADDR) was used to write the last frame" "PING buffer,PONG buffer"
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bitfld.long 0x110 2. "VP_FORCE,RESERVE FIELD" "0,1"
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bitfld.long 0x110 1. "LINE_MODULO,Line modulo configuration" "CSI2_CTX_CTRL3.LINE_NUMBER is used once per..,CSI2_CTX_CTRL3.LINE_NUMBER is used as a modulo.."
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bitfld.long 0x110 0. "CTX_EN,Enables the Context" "Disabled,Enabled"
line.long 0x114 "CSI2_CTX7_CTRL2,CONTROL REGISTER - Context This register controls the Context"
hexmask.long.word 0x114 16.--31. 1. "FRAME,Frame number"
newline
rbitfld.long 0x114 15. "RES20,RESERVE FIELD" "0,1"
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bitfld.long 0x114 13.--14. "USER_DEF_MAPPING,Selects the pixel format of USER_DEFINED in FORMAT" "RAW6,RAW7,RAW8 (not..,?..."
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bitfld.long 0x114 11.--12. "VIRTUAL_ID,Virtual channel ID" "Virtual Channel ID 0,Virtual Channel ID 1,Virtual Channel ID 2,Virtual Channel ID 3"
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bitfld.long 0x114 10. "DPCM_PRED,Selects the DPCM predictor" "The advanced predictor is used,The simple predictor is used"
newline
abitfld.long 0x114 0.--9. "FORMAT,Data format selection" "0x000=OTHERS (except NULL and BLANKING packets),0x012=Embedded 8-bit non-image data (e.g. JPEG),0x018=YUV420 8bit,0x019=YUV420 10bit,0x01A=YUV420 8bit legacy,0x01C=YUV420 8bit + CSPS,0x01D=YUV420 10bit + CSPS,0x01E=YUV422 8bit,0x01F=YUV422 10bit,0x022=RGB565,0x024=RGB888,0x028=RAW6,0x029=RAW7,0x02A=RAW8,0x02B=RAW10,0x02C=RAW12,0x02D=RAW14,0x033=RGB666 + EXP32_24,0x040=USER_DEFINED_8_BIT_DATA_TYPE_1,0x041=USER_DEFINED_8_BIT_DATA_TYPE_2,0x042=USER_DEFINED_8_BIT_DATA_TYPE_3,0x043=USER_DEFINED_8_BIT_DATA_TYPE_4,0x044=USER_DEFINED_8_BIT_DATA_TYPE_5,0x045=USER_DEFINED_8_BIT_DATA_TYPE_6,0x046=USER_DEFINED_8_BIT_DATA_TYPE_7,0x047=USER_DEFINED_8_BIT_DATA_TYPE_8,0x068=RAW6 + EXP8,0x069=RAW7 + EXP8,0x080=USER_DEFINED_8_BIT_DATA_TYPE_1 + EXP8,0x081=USER_DEFINED_8_BIT_DATA_TYPE_2 + EXP8,0x082=USER_DEFINED_8_BIT_DATA_TYPE_3 + EXP8,0x083=USER_DEFINED_8_BIT_DATA_TYPE_4 + EXP8,0x084=USER_DEFINED_8_BIT_DATA_TYPE_5 + EXP8,0x085=USER_DEFINED_8_BIT_DATA_TYPE_6 + EXP8,0x086=USER_DEFINED_8_BIT_DATA_TYPE_7 + EXP8,0x087=USER_DEFINED_8_BIT_DATA_TYPE_8 + EXP8,0x09E=YUV422 8bit + VP,0x0A0=RGB444 + EXP16,0x0A1=RGB555 + EXP16,0x0AB=RAW10 + EXP16,0x0AC=RAW12 + EXP16,0x0AD=RAW14 + EXP16,0x0DE=Same as YUV422 8bit + VP but data is send..,0x0E3=RGB666 + EXP32,0x0E4=RGB888 + EXP32,0x0E8=RAW6 + DPCM10 + VP,0x12A=RAW8 + VP,0x12C=RAW12 + VP,0x12D=RAW14 + VP,0x12F=RAW10 + VP,0x140=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_VP,0x141=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_VP,0x142=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_VP,0x143=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_VP,0x144=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_VP,0x145=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_VP,0x146=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_VP,0x147=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_VP,0x1C0=USER_DEFINED_8_BIT_DATA_TYPE_1_DPCM12_EXP16,0x1C1=USER_DEFINED_8_BIT_DATA_TYPE_2_DPCM12_EXP16,0x1C2=USER_DEFINED_8_BIT_DATA_TYPE_3_DPCM12_EXP16,0x1C3=USER_DEFINED_8_BIT_DATA_TYPE_4_DPCM12_EXP16,0x1C4=USER_DEFINED_8_BIT_DATA_TYPE_5_DPCM12_EXP16,0x1C5=USER_DEFINED_8_BIT_DATA_TYPE_6_DPCM12_EXP16,0x1C6=USER_DEFINED_8_BIT_DATA_TYPE_7_DPCM12_EXP16,0x1C7=USER_DEFINED_8_BIT_DATA_TYPE_8_DPCM12_EXP16,0x229=RAW7 + DPCM10 + EXP16,0x2A8=RAW6 + DPCM10 + EXP16,0x2AA=RAW8 + DPCM10 + EXP16,0x2C0=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 +..,0x2C1=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 +..,0x2C2=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 +..,0x2C3=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 +..,0x2C4=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 +..,0x2C5=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 +..,0x2C6=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 +..,0x2C7=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 +..,0x329=RAW7 + DPCM10 + VP,0x32A=RAW8 + DPCM10 + VP,0x340=USER_DEFINED_8_BIT_DATA_TYPE_1 + DPCM10 + VP,0x341=USER_DEFINED_8_BIT_DATA_TYPE_2 + DPCM10 + VP,0x342=USER_DEFINED_8_BIT_DATA_TYPE_3 + DPCM10 + VP,0x343=USER_DEFINED_8_BIT_DATA_TYPE_4 + DPCM10 + VP,0x344=USER_DEFINED_8_BIT_DATA_TYPE_5 + DPCM10 + VP,0x345=USER_DEFINED_8_BIT_DATA_TYPE_6 + DPCM10 + VP,0x346=USER_DEFINED_8_BIT_DATA_TYPE_7 + DPCM10 + VP,0x347=USER_DEFINED_8_BIT_DATA_TYPE_8 + DPCM10 + VP,0x368=RAW6 DPCM12 + VP,0x369=RAW7 DPCM12 + EXP16,0x36A=RAW8 DPCM12 + EXP16,0x3A8=RAW6 DPCM12 + EXP16,0x3A9=RAW7 DPCM12 + VP,0x3AA=RAW8 DPCM12 + VP"
line.long 0x118 "CSI2_CTX7_DAT_OFST,DATA MEM ADDRESS OFFSET REGISTER - Context This register sets the offset which is applied on the destination address after each line is written to memory"
hexmask.long.word 0x118 17.--31. 1. "RES21,RESERVE FIELD"
newline
hexmask.long.word 0x118 5.--16. 1. "OFST,Line offset programmed in bytes (signed value 2's complement)"
line.long 0x11C "CSI2_CTX7_DAT_PING_ADDR,DATA MEM PING ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x11C 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x11C 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x120 "CSI2_CTX7_DAT_PONG_ADDR,DATA MEM PONG ADDRESS REGISTER - Context This register sets the 32-bit memory address where the pixel data are stored"
hexmask.long 0x120 5.--31. 1. "ADDR,27 most significant bits of the 32-bit address"
newline
rbitfld.long 0x120 0.--4. "RES,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x124 "CSI2_CTX7_IRQENABLE,INTERRUPT ENABLE REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x124 9.--31. 1. "RES22,RESERVE FIELD"
newline
bitfld.long 0x124 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to correct the only 1-bit error (long packet only)" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 7. "LINE_NUMBER_IRQ,Context - Line number is reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 5. "CS_IRQ,Context - Check-Sum of the payload mismatch detection" "Event is masked,Event generates an interrupt when it occurs"
newline
rbitfld.long 0x124 4. "RES23,RESERVE FIELD" "0,1"
newline
bitfld.long 0x124 3. "LE_IRQ,Context - Line end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 2. "LS_IRQ,Context - Line start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 1. "FE_IRQ,Context - Frame end sync code detection" "Event is masked,Event generates an interrupt when it occurs"
newline
bitfld.long 0x124 0. "FS_IRQ,Context - Frame start sync code detection" "Event is masked,Event generates an interrupt when it occurs"
line.long 0x128 "CSI2_CTX7_IRQSTATUS,INTERRUPT STATUS REGISTER - Context This register regroups all the events related to Context"
hexmask.long.tbyte 0x128 9.--31. 1. "RES24,RESERVE FIELD"
newline
bitfld.long 0x128 8. "ECC_CORRECTION_IRQ,Context - ECC has been used to do the correction of the only 1-bit error status (long packet only)" "READS,READS"
newline
bitfld.long 0x128 7. "LINE_NUMBER_IRQ,Contexc - Line number reached status" "READS,READS"
newline
bitfld.long 0x128 6. "FRAME_NUMBER_IRQ,Context - Frame counter reached status" "READS,READS"
newline
bitfld.long 0x128 5. "CS_IRQ,Context - Check-Sum mismatch status" "READS,READS"
newline
rbitfld.long 0x128 4. "RES25,RESERVE FIELD" "0,1"
newline
bitfld.long 0x128 3. "LE_IRQ,Context - Line end sync code detection status" "READS,READS"
newline
bitfld.long 0x128 2. "LS_IRQ,Context - Line start sync code detection status" "READS,READS"
newline
bitfld.long 0x128 1. "FE_IRQ,Context - Frame end sync code detection status" "READS,READS"
newline
bitfld.long 0x128 0. "FS_IRQ,Context - Frame start sync code detection status" "READS,READS"
line.long 0x12C "CSI2_CTX7_CTRL3,CONTROL REGISTER - Context This register controls the Context"
rbitfld.long 0x12C 30.--31. "Reserved,Reserved" "0,1,2,3"
newline
hexmask.long.word 0x12C 16.--29. 1. "ALPHA,When TRANSCODE=0 Alpha value for RGB888 RGB666 and RBG444"
newline
hexmask.long.word 0x12C 0.--15. 1. "LINE_NUMBER,Line number for the interrupt generation"
line.long 0x130 "CSI2_PHY_CFG_REG0,"
hexmask.long.byte 0x130 24.--31. 1. "HS_CLK_CONFIG,Disable clock missing detector"
newline
hexmask.long.byte 0x130 16.--23. 1. "RESERVED,RESERVED"
newline
hexmask.long.byte 0x130 8.--15. 1. "THS_TERM,Ths-term timing parameter in multiples of DDR clock"
newline
hexmask.long.byte 0x130 0.--7. 1. "THS_SETTLE,THS-SETTLE timing parameter in multiples on DDR clock frequency"
line.long 0x134 "CSI2_PHY_CFG_REG1,"
bitfld.long 0x134 30.--31. "RSVD2,Reserved" "0,1,2,3"
newline
rbitfld.long 0x134 29. "RESETDONECTRLCLK,RESETDONECTRLCLK" "0,1"
newline
rbitfld.long 0x134 28. "RESETDONERXBYTECLK,RESETDONERXBYTECLK" "0,1"
newline
bitfld.long 0x134 26.--27. "RSVD1,Reserved" "0,1,2,3"
newline
rbitfld.long 0x134 25. "CLK_MISS_DET," "0,1"
newline
hexmask.long.byte 0x134 18.--24. 1. "TCLK_TERM,TCLK_TERM timing parameter in multiples of CTRLCLK Effective time for enabling of termination = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~ (1-2)* CTRLCLK + TCLK_TERM + ~ (1-15) ns Programmed value = ceil(9.5.."
newline
hexmask.long.byte 0x134 10.--17. 1. "D_PHY_HS_SYNC_PAT,DPHY mode HS sync pattern in byte order (reverse of RW 0xB8 received order) D-PHY mode sync pattern"
newline
bitfld.long 0x134 8.--9. "CTRLCLK_DIV_FACT,Divide factor for CTRLCLK for CLKMISS detector" "0,1,2,3"
newline
hexmask.long.byte 0x134 0.--7. 1. "TCLK_SETTLE,TCLK_SETTLE timing parameter in multiples of CTRLCLK Clock Effective TCLK_SETTLE = synchronizer delay + timer delay + LPRX delay + combinational routing delay ~(1-2)* CTRLCLK + Tclk-settle + ~ (1 -15) ns Programmed value = max[3 ceil(155.."
line.long 0x138 "CSI2_PHY_CFG_REG2,"
bitfld.long 0x138 30.--31. "RXTRIGGERESC0,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC0" "0,1,2,3"
newline
bitfld.long 0x138 28.--29. "RXTRIGGERESC1,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC1" "0,1,2,3"
newline
bitfld.long 0x138 26.--27. "RXTRIGGERESC2,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC2" "0,1,2,3"
newline
bitfld.long 0x138 24.--25. "RXTRIGGERESC3,Mapping of Trigger escape entry command to PPI output RXTRIGGERESC3" "0,1,2,3"
newline
hexmask.long.tbyte 0x138 0.--23. 1. "CCP2_SYNC_PAT,CCP2 mode sync pattern in byte order (reverse of received order)"
line.long 0x13C "CSI2_PHY_CFG_REG3,"
bitfld.long 0x13C 31. "OVR_ENHSRX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 26.--30. "ENHSRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 25. "OVR_ENRXTERM,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 20.--24. "ENRXTERM,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 19. "OVR_ENLPRX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 14.--18. "ENLPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 9.--13. "ENULPRX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x13C 8. "OVR_ENLDO,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 7. "ENLDO,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 6. "OVR_ENBIAS,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 5. "ENBIAS,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 4. "OVR_ENCCP_TO_ANAT,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 3. "OVR_ENCCP_TO_HSRX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 2. "RSVD1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 1. "RECAL_HS_RX,RESERVE FIELD" "0,1"
newline
bitfld.long 0x13C 0. "RECAL_BIAS,RESERVE FIELD" "0,1"
line.long 0x140 "CSI2_PHY_CFG_REG4,"
bitfld.long 0x140 27.--31. "TRIM_BIAS_GEN,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 22.--26. "TRIM_TERM_LANE4,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 17.--21. "TRIM_TERM_LANE3,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 12.--16. "TRIM_TERM_LANE2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 7.--11. "TRIM_TERM_LANE1,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 2.--6. "TRIM_TERM_LANE0,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x140 1. "BYPASS_EFUSE,RESERVE FIELD" "0,1"
newline
bitfld.long 0x140 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x144 "CSI2_PHY_CFG_REG5,"
bitfld.long 0x144 26.--31. "TRIM_OFFSET_LANE4_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 20.--25. "TRIM_OFFSET_LANE3_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 14.--19. "TRIM_OFFSET_LANE2_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 8.--13. "TRIM_OFFSET_LANE1_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 2.--7. "TRIM_OFFSET_LANE0_HS_RX,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x144 1. "BYPASS_CALIB_OFFSET,RESERVE FIELD" "0,1"
newline
bitfld.long 0x144 0. "RSVD1,RESERVE FIELD" "0,1"
line.long 0x148 "CSI2_PHY_CFG_REG6,"
hexmask.long.word 0x148 21.--31. 1. "RSVD2,RESERVE FIELD"
newline
bitfld.long 0x148 20. "OVR_AFE_LANE_ADR_POL,RESERVE FIELD" "0,1"
newline
hexmask.long.byte 0x148 12.--19. 1. "AFE_LANE_SEL,RESERVE FIELD"
newline
bitfld.long 0x148 11. "AFE_LANE_POL,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 10. "HSCOMOOUT,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 9. "BYPASS_LDO_REG,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 8. "OBSV_LDO_VOLT_DYA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 7. "OBSV_BIAS_CURR_DXA,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 6. "RSVD1,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 5. "BIASGEN_CAL_OVR,RESERVE FIELD" "0,1"
newline
bitfld.long 0x148 0.--4. "BIASGEN_CAL_OVR_VAL,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x1C0++0x3F
line.long 0x00 "CSI2_CTX0_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x00 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x00 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x00 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x04 "CSI2_CTX0_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x04 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x04 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x04 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x08 "CSI2_CTX1_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x08 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x08 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x08 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x0C "CSI2_CTX1_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x0C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x0C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x0C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x10 "CSI2_CTX2_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x10 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x10 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x10 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x14 "CSI2_CTX2_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x14 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x14 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x14 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x18 "CSI2_CTX3_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x18 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x18 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x18 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x1C "CSI2_CTX3_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x1C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x1C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x1C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x20 "CSI2_CTX4_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x20 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x20 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x20 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x24 "CSI2_CTX4_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x24 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x24 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x24 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x28 "CSI2_CTX5_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x28 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x28 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x28 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x2C "CSI2_CTX5_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x2C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x2C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x2C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x30 "CSI2_CTX6_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x30 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x30 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x30 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x34 "CSI2_CTX6_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x34 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x34 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x34 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
line.long 0x38 "CSI2_CTX7_TRANSCODEH,Transcode configuration register: defines horizontal frame cropping"
rbitfld.long 0x38 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 16.--28. 1. "HCOUNT,Pixels to output per line when the values is between 1 and 8191"
newline
rbitfld.long 0x38 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x38 0.--12. 1. "HSKIP,Pixel to skip horizontally"
line.long 0x3C "CSI2_CTX7_TRANSCODEV,Transcode configuration register: defines vertical frame cropping"
rbitfld.long 0x3C 29.--31. "RSVD2,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 16.--28. 1. "VCOUNT,Lines to output per frame when the values is between 1 and 8191"
newline
rbitfld.long 0x3C 13.--15. "RSVD1,Reserved" "0,1,2,3,4,5,6,7"
newline
hexmask.long.word 0x3C 0.--12. 1. "VSKIP,Pixel to skip vertically Valid values: 0-8191"
width 0x0B
tree.end
tree "RCSS_CTRL (RCSS Control Module Registers)"
base ad:0x5020000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
newline
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x08++0x257
line.long 0x00 "RCSS_TPCC_A_ERRAGG_MASK,"
bitfld.long 0x00 26. "tptc_a1_read_access_error,Mask Error from RCSS_TPTC_A1 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 25. "tptc_a0_read_access_error,Mask Error from RCSS_TPTC_A0 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 24. "tpcc_a_read_access_error,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 18. "tptc_a1_write_access_error,Mask Error from RCSS_TPTC_A1 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 17. "tptc_a0_write_access_error,Mask Error from RCSS_TPTC_A0 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 16. "tpcc_a_write_access_error,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 8. "tpcc_a_parity_err,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 3. "tptc_a1_err,Mask Error from RCSS_TPTC_A1 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 2. "tptc_a0_err,Mask Error from RCSS_TPTC_A0 to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 1. "tpcc_a_mpint,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
newline
bitfld.long 0x00 0. "tpcc_a_errint,Mask Error from RCSS_TPCC_A to aggregated Error RCSS_TPCC_A_ERRAGG" "Error is Unmasked,Error is Masked"
line.long 0x04 "RCSS_TPCC_A_ERRAGG_STATUS,"
bitfld.long 0x04 26. "tptc_a1_read_access_error,Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x04 25. "tptc_a0_read_access_error,Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x04 24. "tpcc_a_read_access_error,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 18. "tptc_a1_write_access_error,Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x04 17. "tptc_a0_write_access_error,Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x04 16. "tpcc_a_write_access_error,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 8. "tpcc_a_parity_err,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 3. "tptc_a1_err,Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x04 2. "tptc_a0_err,Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x04 1. "tpcc_a_mpint,Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x04 0. "tpcc_a_errint,Status of Error from RCSS_TPCC_A" "0,1"
line.long 0x08 "RCSS_TPCC_A_ERRAGG_STATUS_RAW,"
bitfld.long 0x08 26. "tptc_a1_read_access_error,Raw Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 25. "tptc_a0_read_access_error,Raw Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 24. "tpcc_a_read_access_error,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 18. "tptc_a1_write_access_error,Raw Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 17. "tptc_a0_write_access_error,Raw Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 16. "tpcc_a_write_access_error,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 8. "tpcc_a_parity_err,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 3. "tptc_a1_err,Raw Status of Error from RCSS_TPTC_A1" "0,1"
newline
bitfld.long 0x08 2. "tptc_a0_err,Raw Status of Error from RCSS_TPTC_A0" "0,1"
newline
bitfld.long 0x08 1. "tpcc_a_mpint,Raw Status of Error from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x08 0. "tpcc_a_errint,Raw Status of Error from RCSS_TPCC_A" "0,1"
line.long 0x0C "RCSS_TPCC_A_INTAGG_MASK,"
bitfld.long 0x0C 17. "tptc_a1,Mask Interrupt from TPTC A1 to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 16. "tptc_a0,Mask Interrupt from TPTC A0 to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 8. "tpcc_a_int7,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 7. "tpcc_a_int6,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 6. "tpcc_a_int5,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 5. "tpcc_a_int4,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 4. "tpcc_a_int3,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 3. "tpcc_a_int2,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 2. "tpcc_a_int1,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 1. "tpcc_a_int0,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x0C 0. "tpcc_a_intg,Mask Interrupt from RCSS_TPCC_A to aggregated Interrupt RCSS_TPCC_A_INTAGG" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x10 "RCSS_TPCC_A_INTAGG_STATUS,"
bitfld.long 0x10 17. "tptc_a1,Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x10 16. "tptc_a0,Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x10 8. "tpcc_a_int7,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 7. "tpcc_a_int6,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 6. "tpcc_a_int5,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 5. "tpcc_a_int4,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 4. "tpcc_a_int3,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 3. "tpcc_a_int2,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 2. "tpcc_a_int1,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 1. "tpcc_a_int0,Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x10 0. "tpcc_a_intg,Status of Interrupt from RCSS_TPCC_A" "0,1"
line.long 0x14 "RCSS_TPCC_A_INTAGG_STATUS_RAW,"
bitfld.long 0x14 17. "tptc_a1,Raw Status of Interrupt from TPTC A1" "0,1"
newline
bitfld.long 0x14 16. "tptc_a0,Raw Status of Interrupt from TPTC A0" "0,1"
newline
bitfld.long 0x14 8. "tpcc_a_int7,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 7. "tpcc_a_int6,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 6. "tpcc_a_int5,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 5. "tpcc_a_int4,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 4. "tpcc_a_int3,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 3. "tpcc_a_int2,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 2. "tpcc_a_int1,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 1. "tpcc_a_int0,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
newline
bitfld.long 0x14 0. "tpcc_a_intg,Raw Status of Interrupt from RCSS_TPCC_A" "0,1"
line.long 0x18 "RCSS_SPI_TRIG_SRC,"
hexmask.long.word 0x18 16.--27. 1. "trig_spib,Trigger sources for RCSS SPIB"
newline
hexmask.long.word 0x18 0.--11. 1. "trig_spia,Trigger sources for RCSS SPIA"
line.long 0x1C "RCSS_SPIA_MEMINIT,"
bitfld.long 0x1C 0. "mem0_init,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x20 "RCSS_SPIA_MEMINIT_DONE,"
bitfld.long 0x20 0. "mem0_done,Status field" "0,1"
line.long 0x24 "RCSS_SPIA_MEMINIT_STATUS,"
bitfld.long 0x24 0. "mem0_status,Status field" "0,1"
line.long 0x28 "RCSS_SPIB_MEMINIT,"
bitfld.long 0x28 0. "mem0_init,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x2C "RCSS_SPIB_MEMINIT_DONE,"
bitfld.long 0x2C 0. "mem0_done,Status field" "0,1"
line.long 0x30 "RCSS_SPIB_MEMINIT_STATUS,"
bitfld.long 0x30 0. "mem0_status,Status field" "0,1"
line.long 0x34 "RCSS_TPCC_MEMINIT_START,"
bitfld.long 0x34 0. "tpcc_a_meminit_start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x38 "RCSS_TPCC_MEMINIT_DONE,"
bitfld.long 0x38 0. "tpcc_a_meminit_done,Status field" "0,1"
line.long 0x3C "RCSS_TPCC_MEMINIT_STATUS,"
bitfld.long 0x3C 0. "tpcc_a_meminit_status,Status field" "0,1"
line.long 0x40 "RCSS_SPIA_CFG,"
bitfld.long 0x40 24. "spia_int_trig_polarity,Trigger source polarity select" "Polarity 0,Polarity 1"
newline
bitfld.long 0x40 16. "spia_trig_gate_en,Trigger Gate Enable" "0,1"
newline
bitfld.long 0x40 8. "spia_cs_trigsrc_en,Chip Select Trigger SRC enable Wrie 0x1 to Use CS as trigger source" "0,1"
newline
bitfld.long 0x40 0.--2. "spiasync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x44 "RCSS_SPIB_CFG,"
bitfld.long 0x44 24. "spib_int_trig_polarity,Trigger source polarity select" "Polarity 0,Polarity 1"
newline
bitfld.long 0x44 16. "spib_trig_gate_en,Trigger Gate Enable" "0,1"
newline
bitfld.long 0x44 8. "spib_cs_trigsrc_en,Chip Select Trigger SRC enable Wrie 0x1 to Use CS as trigger source" "0,1"
newline
bitfld.long 0x44 0.--2. "spibsync2sen,Donot touch the field" "0,1,2,3,4,5,6,7"
line.long 0x48 "RCSS_SPIA_IOCFG,"
bitfld.long 0x48 16.--18. "miso_oen_by_cs,SPI MISO Output Enable Control based on Chip select CS" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
newline
bitfld.long 0x48 8.--10. "cs_pol,SPI CS polarity-slave mode" "Active low,Active high,?..."
newline
bitfld.long 0x48 0.--2. "cs_deact,Chip Select Deactivate" "0,1,2,3,4,5,6,7"
line.long 0x4C "RCSS_SPIB_IOCFG,"
bitfld.long 0x4C 16.--18. "miso_oen_by_cs,SPI MISO Output Enable Control based on Chip select CS" "MISO OEN controlled by IP,MISO OEN controlled based on CS.When CS is..,?..."
newline
bitfld.long 0x4C 8.--10. "cs_pol,SPI CS polarity-slave mode" "Active low,Active high,?..."
newline
bitfld.long 0x4C 0.--2. "cs_deact,Chip Select Deactivate" "0,1,2,3,4,5,6,7"
line.long 0x50 "RCSS_SPI_HOST_IRQ,"
bitfld.long 0x50 0.--2. "host_irq,TI internal reserved for R&D" "0,1,2,3,4,5,6,7"
line.long 0x54 "TPTC_DBS_CFG,"
bitfld.long 0x54 2.--3. "tptc_a1,Max Burst size tieoff value for TPTC A1" "0,1,2,3"
newline
bitfld.long 0x54 0.--1. "tptc_a0,Max Burst size tieoff value for TPTC A0" "0,1,2,3"
line.long 0x58 "RCSS_TPCC_A_PARITY_CTRL,"
bitfld.long 0x58 2. "parity_err_clr,Write pulse bit field: Write 0x1 to clear the Parit Error status for TPCC" "0,1"
newline
bitfld.long 0x58 1. "parity_testen,Enable Parity Test for TPCC" "0,1"
newline
bitfld.long 0x58 0. "parity_en,Enable Parity for TPCC" "0,1"
line.long 0x5C "RCSS_TPCC_A_PARITY_STATUS,"
hexmask.long.byte 0x5C 8.--15. 1. "parity_addr,TPCC Error Address at which Parity Error occurred"
line.long 0x60 "RCSS_CSI2A_CFG,"
bitfld.long 0x60 28.--30. "sof_intr1_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2A_SOF_INT1" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x60 24.--26. "sof_intr0_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2A_SOF_INT0" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x60 20.--22. "eof_intr1_sel,Select the End of Frame Contx to be sent as RCSS_CSI2A_EOF_INT1" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x60 17.--19. "eof_intr0_sel,Select the End of Frame Contx to be sent as RCSS_CSI2A_EOF_INT0" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x60 16. "sign_ext_en,Sign Extention Enable for CSI2 A" "0,1"
newline
bitfld.long 0x60 8. "mwait,Power Idle Protocol related Mwait Port" "0,1"
newline
bitfld.long 0x60 0.--4. "lane_enable,Lane enable for CSI2 A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x64 "RCSS_CSI2B_CFG,"
bitfld.long 0x64 28.--30. "sof_intr1_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2B_SOF_INT1" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x64 24.--26. "sof_intr0_sel,Select the Start of Frame Contx to be sent as RCSS_CSI2B_SOF_INT0" "Start of Frame for Context 0 will be propagated..,?,?,?,?,?,?,Start of Frame for Context 7 will be propagated.."
newline
bitfld.long 0x64 20.--22. "eof_intr1_sel,Select the End of Frame Contx to be sent as RCSS_CSI2B_EOF_INT1" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x64 17.--19. "eof_intr0_sel,Select the End of Frame Contx to be sent as RCSS_CSI2B_EOF_INT0" "End of Frame for Context 0 will be propagated on..,?,?,?,?,?,?,End of Frame for Context 7 will be propagated on.."
newline
bitfld.long 0x64 16. "sign_ext_en,Sign Extention Enable for CSI2 B" "0,1"
newline
bitfld.long 0x64 8. "mwait,Power Idle Protocol related Mwait Port" "0,1"
newline
bitfld.long 0x64 0.--4. "lane_enable,Lane enable for CSI2 B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
line.long 0x68 "RCSS_CSI2A_CTX0_LINE_PING_PONG,"
bitfld.long 0x68 16. "enable,Enable line based ping pong toggle for Context 0" "Diabled,Enabled"
newline
hexmask.long.word 0x68 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 0"
line.long 0x6C "RCSS_CSI2A_CTX1_LINE_PING_PONG,"
bitfld.long 0x6C 16. "enable,Enable line based ping pong toggle for Context 1" "Diabled,Enabled"
newline
hexmask.long.word 0x6C 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 1"
line.long 0x70 "RCSS_CSI2A_CTX2_LINE_PING_PONG,"
bitfld.long 0x70 16. "enable,Enable line based ping pong toggle for Context 2" "Diabled,Enabled"
newline
hexmask.long.word 0x70 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 2"
line.long 0x74 "RCSS_CSI2A_CTX3_LINE_PING_PONG,"
bitfld.long 0x74 16. "enable,Enable line based ping pong toggle for Context 3" "Diabled,Enabled"
newline
hexmask.long.word 0x74 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 3"
line.long 0x78 "RCSS_CSI2A_CTX4_LINE_PING_PONG,"
bitfld.long 0x78 16. "enable,Enable line based ping pong toggle for Context 4" "Diabled,Enabled"
newline
hexmask.long.word 0x78 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 4"
line.long 0x7C "RCSS_CSI2A_CTX5_LINE_PING_PONG,"
bitfld.long 0x7C 16. "enable,Enable line based ping pong toggle for Context 5" "Diabled,Enabled"
newline
hexmask.long.word 0x7C 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 5"
line.long 0x80 "RCSS_CSI2A_CTX6_LINE_PING_PONG,"
bitfld.long 0x80 16. "enable,Enable line based ping pong toggle for Context 6" "Diabled,Enabled"
newline
hexmask.long.word 0x80 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 6"
line.long 0x84 "RCSS_CSI2A_CTX7_LINE_PING_PONG,"
bitfld.long 0x84 16. "enable,Enable line based ping pong toggle for Context 7" "Diabled,Enabled"
newline
hexmask.long.word 0x84 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 7"
line.long 0x88 "RCSS_CSI2A_PARITY_CTRL,"
bitfld.long 0x88 16. "fifo_parity_en,Enable Parity for CSI2 FIFO Memory" "0,1"
newline
bitfld.long 0x88 0. "ctx_parity_en,Enable Parity for CSI2 CTX Memory" "0,1"
line.long 0x8C "RCSS_CSI2A_PARITY_STATUS,"
hexmask.long.byte 0x8C 16.--22. 1. "fifo_parity_addr,CSI2 FIFO Memory Error Address at which Parity Error occurred"
newline
bitfld.long 0x8C 0.--3. "ctx_parity_addr,CSI2 CTX Memory Error Address at which Parity Error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x90 "RCSS_CSI2B_CTX0_LINE_PING_PONG,"
bitfld.long 0x90 16. "enable,Enable line based ping pong toggle for Context 0" "Diabled,Enabled"
newline
hexmask.long.word 0x90 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 0"
line.long 0x94 "RCSS_CSI2B_CTX1_LINE_PING_PONG,"
bitfld.long 0x94 16. "enable,Enable line based ping pong toggle for Context 1" "Diabled,Enabled"
newline
hexmask.long.word 0x94 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 1"
line.long 0x98 "RCSS_CSI2B_CTX2_LINE_PING_PONG,"
bitfld.long 0x98 16. "enable,Enable line based ping pong toggle for Context 2" "Diabled,Enabled"
newline
hexmask.long.word 0x98 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 2"
line.long 0x9C "RCSS_CSI2B_CTX3_LINE_PING_PONG,"
bitfld.long 0x9C 16. "enable,Enable line based ping pong toggle for Context 3" "Diabled,Enabled"
newline
hexmask.long.word 0x9C 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 3"
line.long 0xA0 "RCSS_CSI2B_CTX4_LINE_PING_PONG,"
bitfld.long 0xA0 16. "enable,Enable line based ping pong toggle for Context 4" "Diabled,Enabled"
newline
hexmask.long.word 0xA0 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 4"
line.long 0xA4 "RCSS_CSI2B_CTX5_LINE_PING_PONG,"
bitfld.long 0xA4 16. "enable,Enable line based ping pong toggle for Context 5" "Diabled,Enabled"
newline
hexmask.long.word 0xA4 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 5"
line.long 0xA8 "RCSS_CSI2B_CTX6_LINE_PING_PONG,"
bitfld.long 0xA8 16. "enable,Enable line based ping pong toggle for Context 6" "Diabled,Enabled"
newline
hexmask.long.word 0xA8 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 6"
line.long 0xAC "RCSS_CSI2B_CTX7_LINE_PING_PONG,"
bitfld.long 0xAC 16. "enable,Enable line based ping pong toggle for Context 7" "Diabled,Enabled"
newline
hexmask.long.word 0xAC 0.--15. 1. "num_lines,Configure the number of lines for ping pong toggle for Context 7"
line.long 0xB0 "RCSS_CSI2B_PARITY_CTRL,"
bitfld.long 0xB0 16. "fifo_parity_en,Enable Parity for CSI2 FIFO Memory" "0,1"
newline
bitfld.long 0xB0 0. "ctx_parity_en,Enable Parity for CSI2 CTX Memory" "0,1"
line.long 0xB4 "RCSS_CSI2B_PARITY_STATUS,"
hexmask.long.byte 0xB4 16.--22. 1. "fifo_parity_addr,CSI2 FIFO Memory Error Address at which Parity Error occurred"
newline
bitfld.long 0xB4 0.--3. "ctx_parity_addr,CSI2 CTX Memory Error Address at which Parity Error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0xB8 "RCSS_CSI2A_LANE0_CFG,"
rbitfld.long 0xB8 19. "dy0_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xB8 18. "dy0_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xB8 17. "dy0_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xB8 16. "dy0_in,Pad DY Input" "0,1"
newline
bitfld.long 0xB8 15. "dy0_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xB8 14. "dy0_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xB8 13. "dx0_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xB8 12. "dx0_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xB8 11. "dx0_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xB8 10. "dx0_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xB8 9. "dx0_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xB8 8. "dx0_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xB8 7. "dx0_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xB8 6. "dx0_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xB8 5. "dx0_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xB8 4. "dx0_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xB8 3. "dx0_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xB8 2. "dx0_in,Pad DX Input" "0,1"
newline
bitfld.long 0xB8 1. "dx0_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xB8 0. "dx0_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xBC "RCSS_CSI2A_LANE1_CFG,"
rbitfld.long 0xBC 19. "dy1_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xBC 18. "dy1_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xBC 17. "dy1_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xBC 16. "dy1_in,Pad DY Input" "0,1"
newline
bitfld.long 0xBC 15. "dy1_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xBC 14. "dy1_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xBC 13. "dx1_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xBC 12. "dx1_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xBC 11. "dx1_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xBC 10. "dx1_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xBC 9. "dx1_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xBC 8. "dx1_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xBC 7. "dx1_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xBC 6. "dx1_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xBC 5. "dx1_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xBC 4. "dx1_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xBC 3. "dx1_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xBC 2. "dx1_in,Pad DX Input" "0,1"
newline
bitfld.long 0xBC 1. "dx1_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xBC 0. "dx1_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xC0 "RCSS_CSI2A_LANE2_CFG,"
rbitfld.long 0xC0 19. "dy2_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xC0 18. "dy2_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xC0 17. "dy2_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC0 16. "dy2_in,Pad DY Input" "0,1"
newline
bitfld.long 0xC0 15. "dy2_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xC0 14. "dy2_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xC0 9. "dx2_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xC0 8. "dx2_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xC0 7. "dx2_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xC0 6. "dx2_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xC0 5. "dx2_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xC0 4. "dx2_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xC0 3. "dx2_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC0 2. "dx2_in,Pad DX Input" "0,1"
newline
bitfld.long 0xC0 1. "dx2_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xC0 0. "dx2_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xC4 "RCSS_CSI2A_LANE3_CFG,"
rbitfld.long 0xC4 19. "dy3_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xC4 18. "dy3_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xC4 17. "dy3_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC4 16. "dy3_in,Pad DY Input" "0,1"
newline
bitfld.long 0xC4 15. "dy3_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xC4 14. "dy3_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xC4 13. "dx3_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xC4 12. "dx3_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xC4 11. "dx3_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xC4 10. "dx3_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xC4 9. "dx3_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xC4 8. "dx3_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xC4 7. "dx3_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xC4 6. "dx3_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xC4 5. "dx3_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xC4 4. "dx3_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xC4 3. "dx3_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC4 2. "dx3_in,Pad DX Input" "0,1"
newline
bitfld.long 0xC4 1. "dx3_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xC4 0. "dx3_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xC8 "RCSS_CSI2A_LANE4_CFG,"
rbitfld.long 0xC8 19. "dy4_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xC8 18. "dy4_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xC8 17. "dy4_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC8 16. "dy4_in,Pad DY Input" "0,1"
newline
bitfld.long 0xC8 15. "dy4_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xC8 14. "dy4_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xC8 13. "dx4_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xC8 12. "dx4_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xC8 11. "dx4_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xC8 10. "dx4_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xC8 9. "dx4_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xC8 8. "dx4_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xC8 7. "dx4_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xC8 6. "dx4_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xC8 5. "dx4_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xC8 4. "dx4_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xC8 3. "dx4_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xC8 2. "dx4_in,Pad DX Input" "0,1"
newline
bitfld.long 0xC8 1. "dx4_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xC8 0. "dx4_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xCC "RCSS_CSI2B_LANE0_CFG,"
rbitfld.long 0xCC 19. "dy0_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xCC 18. "dy0_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xCC 17. "dy0_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xCC 16. "dy0_in,Pad DY Input" "0,1"
newline
bitfld.long 0xCC 15. "dy0_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xCC 14. "dy0_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xCC 13. "dx0_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xCC 12. "dx0_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xCC 11. "dx0_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xCC 10. "dx0_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xCC 9. "dx0_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xCC 8. "dx0_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xCC 7. "dx0_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xCC 6. "dx0_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xCC 5. "dx0_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xCC 4. "dx0_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xCC 3. "dx0_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xCC 2. "dx0_in,Pad DX Input" "0,1"
newline
bitfld.long 0xCC 1. "dx0_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xCC 0. "dx0_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xD0 "RCSS_CSI2B_LANE1_CFG,"
rbitfld.long 0xD0 19. "dy1_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xD0 18. "dy1_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xD0 17. "dy1_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD0 16. "dy1_in,Pad DY Input" "0,1"
newline
bitfld.long 0xD0 15. "dy1_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xD0 14. "dy1_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xD0 13. "dx1_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xD0 12. "dx1_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xD0 11. "dx1_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xD0 10. "dx1_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xD0 9. "dx1_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xD0 8. "dx1_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xD0 7. "dx1_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xD0 6. "dx1_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xD0 5. "dx1_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xD0 4. "dx1_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xD0 3. "dx1_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD0 2. "dx1_in,Pad DX Input" "0,1"
newline
bitfld.long 0xD0 1. "dx1_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xD0 0. "dx1_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xD4 "RCSS_CSI2B_LANE2_CFG,"
rbitfld.long 0xD4 19. "dy2_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xD4 18. "dy2_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xD4 17. "dy2_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD4 16. "dy2_in,Pad DY Input" "0,1"
newline
bitfld.long 0xD4 15. "dy2_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xD4 14. "dy2_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xD4 9. "dx2_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xD4 8. "dx2_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xD4 7. "dx2_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xD4 6. "dx2_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xD4 5. "dx2_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xD4 4. "dx2_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xD4 3. "dx2_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD4 2. "dx2_in,Pad DX Input" "0,1"
newline
bitfld.long 0xD4 1. "dx2_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xD4 0. "dx2_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xD8 "RCSS_CSI2B_LANE3_CFG,"
rbitfld.long 0xD8 19. "dy3_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xD8 18. "dy3_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xD8 17. "dy3_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD8 16. "dy3_in,Pad DY Input" "0,1"
newline
bitfld.long 0xD8 15. "dy3_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xD8 14. "dy3_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xD8 13. "dx3_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xD8 12. "dx3_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xD8 11. "dx3_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xD8 10. "dx3_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xD8 9. "dx3_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xD8 8. "dx3_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xD8 7. "dx3_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xD8 6. "dx3_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xD8 5. "dx3_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xD8 4. "dx3_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xD8 3. "dx3_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xD8 2. "dx3_in,Pad DX Input" "0,1"
newline
bitfld.long 0xD8 1. "dx3_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xD8 0. "dx3_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xDC "RCSS_CSI2B_LANE4_CFG,"
rbitfld.long 0xDC 19. "dy4_wuevnt,Pad DY Wakeup Event" "0,1"
newline
bitfld.long 0xDC 18. "dy4_wuen,Pad DY Wakeup Enable" "0,1"
newline
bitfld.long 0xDC 17. "dy4_ie,Pad DY Input Buffer Enable" "0,1"
newline
rbitfld.long 0xDC 16. "dy4_in,Pad DY Input" "0,1"
newline
bitfld.long 0xDC 15. "dy4_enbpd,Pad DY Enable Pull Down" "0,1"
newline
bitfld.long 0xDC 14. "dy4_enbpu,Pad DY Enable Pull Up" "0,1"
newline
rbitfld.long 0xDC 13. "dx4_wuclkout,Pad DX Wakeup Clkout" "0,1"
newline
rbitfld.long 0xDC 12. "dx4_wuout,Pad DX Wakeup Output" "0,1"
newline
rbitfld.long 0xDC 11. "dx4_isoclkout,Pad DX Isosaltion Clkout" "0,1"
newline
rbitfld.long 0xDC 10. "dx4_isoout,Pad DX Isosaltion Output" "0,1"
newline
rbitfld.long 0xDC 9. "dx4_wuevnt,Pad DX Wakeup Event" "0,1"
newline
bitfld.long 0xDC 8. "dx4_wuen,Pad DX Wakeup Enable" "0,1"
newline
bitfld.long 0xDC 7. "dx4_wuclkin,Pad DX Wakeup Clkin" "0,1"
newline
bitfld.long 0xDC 6. "dx4_wuin,Pad DX Wakeup Input" "0,1"
newline
bitfld.long 0xDC 5. "dx4_isoclkin,Pad DX Isolation Clkin" "0,1"
newline
bitfld.long 0xDC 4. "dx4_isoin,Pad DX Isosaltion Input" "0,1"
newline
bitfld.long 0xDC 3. "dx4_ie,Pad DX Input Buffer Enable" "0,1"
newline
rbitfld.long 0xDC 2. "dx4_in,Pad DX Input" "0,1"
newline
bitfld.long 0xDC 1. "dx4_enbpd,Pad DX Enable Pull Down" "0,1"
newline
bitfld.long 0xDC 0. "dx4_enbpu,Pad DX Enable Pull Up" "0,1"
line.long 0xE0 "RCSS_CSI2A_FIFO_MEMINIT,"
bitfld.long 0xE0 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0xE4 "RCSS_CSI2A_FIFO_MEMINIT_DONE,"
bitfld.long 0xE4 0. "done,Status field" "0,1"
line.long 0xE8 "RCSS_CSI2A_FIFO_MEMINIT_STATUS,"
bitfld.long 0xE8 0. "status,Status field" "0,1"
line.long 0xEC "RCSS_CSI2A_CTX_MEMINIT,"
bitfld.long 0xEC 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0xF0 "RCSS_CSI2A_CTX_MEMINIT_DONE,"
bitfld.long 0xF0 0. "done,Status field" "0,1"
line.long 0xF4 "RCSS_CSI2A_CTX_MEMINIT_STATUS,"
bitfld.long 0xF4 0. "status,Status field" "0,1"
line.long 0xF8 "RCSS_CSI2B_FIFO_MEMINIT,"
bitfld.long 0xF8 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0xFC "RCSS_CSI2B_FIFO_MEMINIT_DONE,"
bitfld.long 0xFC 0. "done,Status field" "0,1"
line.long 0x100 "RCSS_CSI2B_FIFO_MEMINIT_STATUS,"
bitfld.long 0x100 0. "status,Status field" "0,1"
line.long 0x104 "RCSS_CSI2B_CTX_MEMINIT,"
bitfld.long 0x104 0. "start,Write pulse bit field: Start Memory intialization of memory" "0,1"
line.long 0x108 "RCSS_CSI2B_CTX_MEMINIT_DONE,"
bitfld.long 0x108 0. "done,Status field" "0,1"
line.long 0x10C "RCSS_CSI2B_CTX_MEMINIT_STATUS,"
bitfld.long 0x10C 0. "status,Status field" "0,1"
line.long 0x110 "RCSS_BUS_SAFETY_CTRL,"
bitfld.long 0x110 4.--6. "clk_disable,Option to clock gate the safety infrastructure is Safety is disabled" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x110 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x114 "RCSS_BUS_SAFETY_SEC_ERR_STAT0,"
bitfld.long 0x114 9. "RCSS_TPTC_A1_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 8. "RCSS_TPTC_A0_WR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 7. "RCSS_TPTC_A1_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 6. "RCSS_TPTC_A0_RD,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 5. "RCSS_MCASPC,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 4. "RCSS_MCASPB,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 3. "RCSS_MCASPA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 2. "RCSS_PCR,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 1. "RCSS_CSI2B_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x114 0. "RCSS_CSI2A_MDMA,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x118 "RCSS_TPTCA0_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x118 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x118 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x118 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x11C "RCSS_TPTCA0_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x11C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x11C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x11C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x11C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x11C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x120 "RCSS_TPTCA0_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x120 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x120 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x120 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x120 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x124 "RCSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x124 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x124 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x128 "RCSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x12C "RCSS_TPTCA0_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x130 "RCSS_TPTCA1_RD_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x130 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x130 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x130 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x134 "RCSS_TPTCA1_RD_BUS_SAFETY_FI,"
hexmask.long.byte 0x134 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x134 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x134 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x134 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x134 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x138 "RCSS_TPTCA1_RD_BUS_SAFETY_ERR,"
hexmask.long.byte 0x138 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x138 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x138 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x138 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x13C "RCSS_TPTCA1_RD_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x13C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x13C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x140 "RCSS_TPTCA1_RD_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x144 "RCSS_TPTCA1_RD_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x148 "RCSS_TPTCA0_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x148 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x148 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x148 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x14C "RCSS_TPTCA0_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x14C 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14C 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x14C 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x14C 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x14C 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x150 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x150 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x150 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x150 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x150 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x154 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x154 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x154 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x158 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x15C "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x160 "RCSS_TPTCA0_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x164 "RCSS_TPTCA1_WR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x164 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x164 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x164 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x168 "RCSS_TPTCA1_WR_BUS_SAFETY_FI,"
hexmask.long.byte 0x168 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x168 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x168 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x168 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x168 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x16C "RCSS_TPTCA1_WR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x16C 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x16C 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x16C 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x16C 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x170 "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x170 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x170 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x174 "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x178 "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x17C "RCSS_TPTCA1_WR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x180 "RCSS_CSI2A_MDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x180 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x180 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x180 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x184 "RCSS_CSI2A_MDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x184 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x184 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x184 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x184 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x184 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x188 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x188 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x188 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x188 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x188 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x18C "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x18C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x18C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x190 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x194 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x198 "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x19C "RCSS_CSI2A_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1A0 "RCSS_CSI2B_MDMA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1A0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1A4 "RCSS_CSI2B_MDMA_BUS_SAFETY_FI,"
hexmask.long.byte 0x1A4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1A4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1A4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1A8 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1A8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1A8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1AC "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1AC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1AC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1B0 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1B4 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1B8 "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1BC "RCSS_CSI2B_MDMA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1C0 "RCSS_PCR_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1C0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1C4 "RCSS_PCR_BUS_SAFETY_FI,"
hexmask.long.byte 0x1C4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1C4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1C4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1C8 "RCSS_PCR_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1C8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1C8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1CC "RCSS_PCR_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1CC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1CC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1D0 "RCSS_PCR_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1D4 "RCSS_PCR_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1D8 "RCSS_PCR_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1DC "RCSS_PCR_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x1E0 "RCSS_MCASPA_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x1E0 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E0 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E0 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x1E4 "RCSS_MCASPA_BUS_SAFETY_FI,"
hexmask.long.byte 0x1E4 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E4 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E4 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x1E4 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x1E4 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x1E8 "RCSS_MCASPA_BUS_SAFETY_ERR,"
hexmask.long.byte 0x1E8 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1E8 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1EC "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x1EC 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x1EC 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x1F0 "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x1F4 "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x1F8 "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x1FC "RCSS_MCASPA_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x200 "RCSS_MCASPB_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x200 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x200 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x200 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x204 "RCSS_MCASPB_BUS_SAFETY_FI,"
hexmask.long.byte 0x204 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x204 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x204 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x204 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x208 "RCSS_MCASPB_BUS_SAFETY_ERR,"
hexmask.long.byte 0x208 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x208 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x20C "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x20C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x20C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x210 "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x214 "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x218 "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x21C "RCSS_MCASPB_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x220 "RCSS_MCASPC_BUS_SAFETY_CTRL,"
hexmask.long.byte 0x220 16.--23. 1. "type,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x220 8. "err_clear,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x220 0.--2. "enable,Refer to TPR12 Substem Microarch document for more details" "0,1,2,3,4,5,6,7"
line.long 0x224 "RCSS_MCASPC_BUS_SAFETY_FI,"
hexmask.long.byte 0x224 24.--31. 1. "safe,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 16.--23. 1. "main,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x224 8.--15. 1. "data,Refer to TPR12 Substem Microarch document for more details"
newline
bitfld.long 0x224 5. "ded,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 4. "sec,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 3. "global_safe_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 2. "global_main_req,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 1. "global_safe,Refer to TPR12 Substem Microarch document for more details" "0,1"
newline
bitfld.long 0x224 0. "global_main,Refer to TPR12 Substem Microarch document for more details" "0,1"
line.long 0x228 "RCSS_MCASPC_BUS_SAFETY_ERR,"
hexmask.long.byte 0x228 24.--31. 1. "ded,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 16.--23. 1. "sec,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 8.--15. 1. "comp_check,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x228 0.--7. 1. "comp_err,Refer to TPR12 Substem Microarch document for more details"
line.long 0x22C "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_DATA0,"
hexmask.long.byte 0x22C 8.--15. 1. "d1,Refer to TPR12 Substem Microarch document for more details"
newline
hexmask.long.byte 0x22C 0.--7. 1. "d0,Refer to TPR12 Substem Microarch document for more details"
line.long 0x230 "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_CMD,"
line.long 0x234 "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_WRITE,"
line.long 0x238 "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_READ,"
line.long 0x23C "RCSS_MCASPC_BUS_SAFETY_ERR_STAT_WRITERESP,"
line.long 0x240 "RCSS_SCIA_CTRL,"
bitfld.long 0x240 4. "DMA_RX_CLR,RCSS_SCIA RX DMA Clear" "0,1"
newline
bitfld.long 0x240 0. "DMA_TX_CLR,RCSS_SCIA TX DMA Clear" "0,1"
line.long 0x244 "RCSS_GIO_CFG,"
line.long 0x248 "RCSS_TPTC_BOUNDARY_CFG,"
bitfld.long 0x248 8.--13. "tptc_a1_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x248 0.--5. "tptc_a0_size,6 bit signal used for deciding the boundary crossing size for CID-RID-SID reordering of TPTC Example: writing 6'd19 decidies boundary to be 2^19 i.e" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24C "RCSS_TPTC_XID_REORDER_CFG,"
bitfld.long 0x24C 8. "tptc_a1_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
newline
bitfld.long 0x24C 0. "tptc_a0_disable,Writing 1'b1 will disable the CID-RID-SID reodering feature for the TPTC instance" "0,1"
line.long 0x250 "DBG_ACK_CPU_CTRL,"
bitfld.long 0x250 0. "sel,Select the Processor Suspend that is used to Suspend the DSS Peripehrals" "DSP,MSS CR5"
line.long 0x254 "DBG_ACK_CTL0,"
bitfld.long 0x254 8.--10. "RCSS_ECAP,Enable Suspend of the peripheral" "Peripheral not suspended,Peripehal Suspended,?..."
newline
bitfld.long 0x254 4.--6. "RCSS_I2CB,Enable Suspend of the peripheral" "Peripheral not suspended,Peripehal Suspended,?..."
newline
bitfld.long 0x254 0.--2. "RCSS_I2CA,Enable Suspend of the peripheral" "Peripheral not suspended,Peripehal Suspended,?..."
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
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bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
width 0x0B
tree.end
tree "RCSS_ECAP (RCSS ECAP Module Registers)"
base ad:0x5F79C00
group.long 0x00++0x17
line.long 0x00 "TSCTR,Time-Stamp Counter"
line.long 0x04 "CTRPHS,Counter Phase Offset Value Register"
line.long 0x08 "CAP1,Capture 1 Register"
line.long 0x0C "CAP2,Capture 2 Register"
line.long 0x10 "CAP3,Capture 3 Register"
line.long 0x14 "CAP4,Capture 4 Register"
group.long 0x24++0x0F
line.long 0x00 "ECCTL0,Capture Control Register 0"
hexmask.long 0x00 7.--31. 1. "NU_1,Reserved"
hexmask.long.byte 0x00 0.--6. 1. "INPUTSEL,Capture input source select bits[[br]]0000000 capture input is ECAPxINPUT[0] [[br]]0000001 capture input is ECAPxINPUT[1] [[br]]0000010 capture input is ECAPxINPUT[2][[br]]"
line.long 0x04 "ECCTL1_ECCTL2,Capture Control Register 1 & Capture Control Register 2"
rbitfld.long 0x04 30.--31. "MODCNTRSTS,This bit field reads current status on modulo counter[[br]]00b (R) = CAP1 register gets loaded on next capture event.[[br]]01b (R) = CAP2 register gets loaded on next capture event.[[br]]10b (R) = CAP3 register gets loaded on next capture.." "0,1,2,3"
bitfld.long 0x04 28.--29. "DMAEVTSEL,DMA event select[[br]]00b (R/W) = DMA interrupt source is CEVT1[[br]]01b (R/W) = DMA interrupt source is CEVT2[[br]]10b (R/W) = DMA interrupt source is CEVT3[[br]]11b (R/W) = DMA interrupt source is CEVT4" "0,1,2,3"
bitfld.long 0x04 27. "CTRFILTRESET,Reset Bit[[br]]0h (R) = No effect[[br]]1h (W) = Resets event filter counter modulo counter and CEVT[1 2 3 4] and CNTOVF HRERROR flags[[br]] [[br]]Note: This provides an ability start capture module from known state in case spurious inputs.." "0,1"
bitfld.long 0x04 26. "APWMPOL,APWM output polarity select" "0,1"
newline
bitfld.long 0x04 25. "CAP_APWM,CAP/APWM operating mode select 0 ECAP_MODULE ECAP module operates in capture mode" "0,1"
bitfld.long 0x04 24. "SWSYNC,Software-forced Counter (TSCTR) Synchronizer" "0,1"
bitfld.long 0x04 22.--23. "SYNCO_SEL,Sync-Out Select 0x0 SWSYNC sync out signal is SWSYNC 0x1 ECAP_CTR_PRD_TO_SYNCOUT Select CTR = PRD event to be the sync-out signal 0x2 ECAP_DISABLE_SYNC_OUT Disable sync out signal 0x3 ECAP_DISABLE_SYNC_OUT Disable sync out signal" "0,1,2,3"
bitfld.long 0x04 21. "SYNCI_EN,Counter (TSCTR) Sync-In select mode 0 ECAP_DISABLE_SYNC_IN Disable sync-in option 1 ECAP_ENABLE_COUNTER_REGISTER Enable counter (TSCTR) to be loaded from CTRPHS register upon either a SYNCI signal or a S/W force event" "0,1"
newline
bitfld.long 0x04 20. "TSCTRSTOP,Time Stamp (TSCTR) Counter Stop (freeze) Control 0 ECAP_TSCTR_STOPPED TSCTR stopped 1 ECAP_TSCTR_FREE_RUNNING TSCTR free-running" "0,1"
bitfld.long 0x04 19. "REARM,Re-Arming Control" "0,1"
bitfld.long 0x04 17.--18. "STOP_WRAP,Stop value for one-shot mode" "0,1,2,3"
bitfld.long 0x04 16. "CONT_ONESHT,Continuous or one-shot mode control (applicable only in capture mode) 0 ECAP_OPP_CONT Operate in continuous mode 1 ECAP_OPP_ONE Operate in one-Shot mode" "0,1"
newline
bitfld.long 0x04 14.--15. "FREE_SOFT,Emulation Control" "ECAP_STOP_EMU TSCTR counter stops immediately on..,ECAP_RUNS_UNTIL TSCTR counter runs until = 0,ECAP_UNAF_EMU_SUS TSCTR counter is unaffected by..,ECAP_UNAF_EMU_SUS2 TSCTR counter is unaffected.."
bitfld.long 0x04 9.--13. "PRESCALE,Event Filter prescale select 0x00 ECAP_DIV1 Divide by 1 (i.e . no prescale by-pass the prescaler) 0x01 ECAP_DIV2 Divide by 2 0x02 ECAP_DIV4 Divide by 4 0x03 ECAP_DIV6 Divide by 6 0x04 ECAP_DIV8 Divide by 8 0x05 ECAP_DIV10 Divide by 10 0x1E.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x04 8. "CAPLDEN,Enable Loading of CAP1-4 registers on a capture event" "0,1"
bitfld.long 0x04 7. "CTRRST4,Counter Reset on Capture Event 4 0 ECAP_DO_NOT_RESET_EVENT4 Do not reset counter on Capture Event 4 (absolute time stamp operation) 1 ECAP_RESET_EVENT4 Reset counter after Capture Event 4 time-stamp has been captured (used in difference mode.." "0,1"
newline
bitfld.long 0x04 6. "CAP4POL,Capture Event 4 Polarity select 0 ECAP_CAP_EVENT4_RISE Capture Event 4 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT4_FALL Capture Event 4 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x04 5. "CTRRST3,Counter Reset on Capture Event 3 0 ECAP_DO_NOT_RESET_EVENT3 Do not reset counter on Capture Event 3 (absolute time stamp) 1 ECAP_RESET_EVENT3 Reset counter after Event 3 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x04 4. "CAP3POL,Capture Event 3 Polarity select 0 ECAP_CAP_EVENT3_RISE Capture Event 3 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT3_FALL Capture Event 3 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x04 3. "CTRRST2,Counter Reset on Capture Event 2 0 ECAP_DO_NOT_RESET_EVENT2 Do not reset counter on Capture Event 2 (absolute time stamp) 1 ECAP_RESET_EVENT2 Reset counter after Event 2 time-stamp has been captured (used in difference mode operation)" "0,1"
newline
bitfld.long 0x04 2. "CAP2POL,Capture Event 2 Polarity select 0 ECAP_CAP_EVENT2_RISE Capture Event 2 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT2_FALL Capture Event 2 triggered on a falling edge (FE)" "0,1"
bitfld.long 0x04 1. "CTRRST1,Counter Reset on Capture Event 1 0 ECAP_DO_NOT_RESET_EVENT1 Do not reset counter on Capture Event 1 (absolute time stamp) 1 ECAP_RESET_EVENT1 Reset counter after Event 1 time-stamp has been captured (used in difference mode operation)" "0,1"
bitfld.long 0x04 0. "CAP1POL,Capture Event 1 Polarity select 0 ECAP_CAP_EVENT1_RISE Capture Event 1 triggered on a rising edge (RE) 1 ECAP_CAP_EVENT1_FALL Capture Event 1 triggered on a falling edge (FE)" "0,1"
line.long 0x08 "ECEINT_ECFLG,The interrupt enable bits (CEVT1. ...) block any of the selected events from generating an interrupt"
hexmask.long.byte 0x08 25.--31. 1. "NU_4,Reserved"
rbitfld.long 0x08 24. "HRERROR_FLG,High resolution error status flag Read 0 ECAP_INDICATE_NO_EVENT Indicates no event occurred Read 1 ECAP_INDICATE_HIGH_RESOLUTION_ERROR Indicates the High resolution Error occurred" "0,1"
rbitfld.long 0x08 23. "CTR_CMP_FLG,Compare Equal Compare Status Flag" "0,1"
rbitfld.long 0x08 22. "CTR_PRD_FLG,Counter Equal Period Status Flag" "0,1"
newline
rbitfld.long 0x08 21. "CTROVF_FLG,Counter Overflow Status Flag" "0,1"
rbitfld.long 0x08 20. "CEVT4_FLG,Capture Event 4 Status Flag This flag is only active in CAP mode" "0,1"
rbitfld.long 0x08 19. "CEVT3_FLG,Capture Event 3 Status Flag" "0,1"
rbitfld.long 0x08 18. "CEVT2_FLG,Capture Event 2 Status Flag" "0,1"
newline
rbitfld.long 0x08 17. "CEVT1_FLG,Capture Event 1 Status Flag" "0,1"
rbitfld.long 0x08 16. "INT_FLG,Global Interrupt Status Flag Read 0 ECAP_INDICATE_NO_EVENT Indicates no event occurred Read 1 ECAP_INDICATE_INTERRUPT Indicates that an interrupt was generated" "0,1"
hexmask.long.byte 0x08 9.--15. 1. "NU_3,Reserved"
bitfld.long 0x08 8. "HRERROR,High resolution error interrupt enable 0 ECAP_DISAB_HRERROR_INTERRUPT Disable High Resolution Error as an Interrupt source 1 ECAP_ENAB_HRERROR_INTERRUPT Enable High Resolution Error as an Interrupt source" "0,1"
newline
bitfld.long 0x08 7. "CTR_EQ_CMP,Counter Equal Compare Interrupt Enable 0 ECAP_DISAB_CE_INTERRUPT Disable Compare Equal as an Interrupt source 1 ECAP_ENAB_CE_INTERRUPT Enable Compare Equal as an Interrupt source" "0,1"
bitfld.long 0x08 6. "CTR_EQ_PRD,Counter Equal Period Interrupt Enable 0 ECAP_DISAB_PE_INTERRUPT Disable Period Equal as an Interrupt source 1 ECAP_ENAB_PE_INTERRUPT Enable Period Equal as an Interrupt source" "0,1"
bitfld.long 0x08 5. "CTROVF,Counter Overflow Interrupt Enable 0 ECAP_DISAB_CO_INTERRUPT Disabled counter Overflow as an Interrupt source 1 ECAP_ENAB_CO_INTERRUPT Enable counter Overflow as an Interrupt source" "0,1"
bitfld.long 0x08 4. "CEVT4,Capture Event 4 Interrupt Enable 0 ECAP_DISAB_CAP4_INTERRUPT Disable Capture Event 4 as an Interrupt source 1 ECAP_ENAB_CAP4_INTERRUPT Capture Event 4 Interrupt Enable" "0,1"
newline
bitfld.long 0x08 3. "CEVT3,Capture Event 3 Interrupt Enable 0 ECAP_DISAB_CAP3_INTERRUPT Disable Capture Event 3 as an Interrupt source 1 ECAP_ENAB_CAP3_INTERRUPT Enable Capture Event 3 as an Interrupt source" "0,1"
bitfld.long 0x08 2. "CEVT2,Capture Event 2 Interrupt Enable 0 ECAP_DISAB_CAP2_INTERRUPT Disable Capture Event 2 as an Interrupt source 1 ECAP_ENAB_CAP2_INTERRUPT Enable Capture Event 2 as an Interrupt source" "0,1"
bitfld.long 0x08 1. "CEVT1,Capture Event 1 Interrupt Enable 0 ECAP_DISAB_CAP1_INTERRUPT Disable Capture Event 1 as an Interrupt source 1 ECAP_ENAB_CAP1_INTERRUPT Enable Capture Event 1 as an Interrupt source" "0,1"
rbitfld.long 0x08 0. "NU_2,Reserved" "0,1"
line.long 0x0C "ECCLR_ECFRC,Capture Interrupt Clear Register & Capture Interrupt Force Register"
hexmask.long.byte 0x0C 25.--31. 1. "NU_6,Reserved"
bitfld.long 0x0C 24. "HRERROR_FRC,High resolution error Force interrupt 0 ECAP_NO_EFFECT_0 No effect" "0,1"
bitfld.long 0x0C 23. "CTR_CMP_FRC,Force Counter Equal Compare Interrupt" "0,1"
bitfld.long 0x0C 22. "CTR_PRD_FRC,Force Counter Equal Period Interrupt" "0,1"
newline
bitfld.long 0x0C 21. "CTROVF_FRC,Force Counter Overflow 0 ECAP_NO_EFFECT_0 No effect" "0,1"
bitfld.long 0x0C 20. "CEVT4_FRC,Force Capture Event 4" "0,1"
bitfld.long 0x0C 19. "CEVT3_FRC,Force Capture Event 3" "0,1"
bitfld.long 0x0C 18. "CEVT2_FRC,Force Capture Event 2" "0,1"
newline
bitfld.long 0x0C 17. "CEVT1_FRC,Force Capture Event 1" "0,1"
hexmask.long.byte 0x0C 9.--16. 1. "NU_5,Reserved"
bitfld.long 0x0C 8. "HRERROR,High resolution error status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 7. "CTR_CMP,Counter Equal Compare Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
newline
bitfld.long 0x0C 6. "CTR_PRD,Counter Equal Period Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 5. "CTROVF,Counter Overflow Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 4. "CEVT4,Capture Event 4 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 3. "CEVT3,Capture Event 3 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
newline
bitfld.long 0x0C 2. "CEVT2,Capture Event 2 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 1. "CEVT1,Capture Event 1 Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
bitfld.long 0x0C 0. "INT,ECAP Global Interrupt Status Clear 0 ECAP_0_NO_EFFECT Writing a 0 has no effect" "0,1"
group.long 0x3C++0x03
line.long 0x00 "ECAPSYNCINSEL,SYNC source select register"
hexmask.long 0x00 5.--31. 1. "NU_7,Reserved"
bitfld.long 0x00 0.--4. "SEL,These bits determines the source of SYNCIN signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
width 0x0B
tree.end
tree "RCSS_GIO (RCSS GIO Module Registers)"
base ad:0x5F7B400
group.long 0x00++0x03
line.long 0x00 "GIOGCR,GIO reset"
hexmask.long 0x00 1.--31. 1. "NU0,Reserved"
bitfld.long 0x00 0. "RESET,GIO reset" "0,1"
group.long 0x04++0x03
line.long 0x00 "GIOPWDN,GIO power down mode register"
bitfld.long 0x00 0. "GIOPWDN,Writing to the GIOPWDN bit is only allowed in privilege mode" "Normal operation; clocks enabled to GIO..,Power-down mode"
group.long 0x08++0x14B
line.long 0x00 "GIOINTDET,Interrupt detection select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x00 24.--31. 1. "GIOINTDET_3,Interrupt detection select for pins GIOD[7:0]"
hexmask.long.byte 0x00 16.--23. 1. "GIOINTDET_2,Interrupt detection select for pins GIOC[7:0]"
hexmask.long.byte 0x00 8.--15. 1. "GIOINTDET_1,Interrupt detection select for pins GIOB[7:0]"
hexmask.long.byte 0x00 0.--7. 1. "GIOINTDET_0,Interrupt detection select for pins GIOA[7:0]"
line.long 0x04 "GIOPOL,Interrupt polarity select for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x04 24.--31. 1. "GIOPOL_3,Interrupt polarity select for pins GIOD[7:0]"
hexmask.long.byte 0x04 16.--23. 1. "GIOPOL_2,Interrupt polarity select for pins GIOC[7:0]"
hexmask.long.byte 0x04 8.--15. 1. "GIOPOL_1,Interrupt polarity select for pins GIOB[7:0]"
hexmask.long.byte 0x04 0.--7. 1. "GIOPOL_0,Interrupt polarity select for pins GIOA[7:0]"
line.long 0x08 "GIOENASET,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x08 24.--31. 1. "GIOENASET_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x08 16.--23. 1. "GIOENASET_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x08 8.--15. 1. "GIOENASET_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x08 0.--7. 1. "GIOENASET_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x0C "GIOENACLR,Interrupt enable for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x0C 24.--31. 1. "GIOENACLR_3,Interrupt enable for pins GIOD [7:0]"
hexmask.long.byte 0x0C 16.--23. 1. "GIOENACLR_2,Interrupt enable for pins GIOC [7:0]"
hexmask.long.byte 0x0C 8.--15. 1. "GIOENACLR_1,Interrupt enable for pins GIOB [7:0]"
hexmask.long.byte 0x0C 0.--7. 1. "GIOENACLR_0,Interrupt enable for pins GIOA [7:0]"
line.long 0x10 "GIOLVLSET,GIO high priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x10 24.--31. 1. "GIOLVLSET_3,GIO high priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x10 16.--23. 1. "GIOLVLSET_2,GIO high priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x10 8.--15. 1. "GIOLVLSET_1,GIO high priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x10 0.--7. 1. "GIOLVLSET_0,GIO high priority interrupt for pins GIOA[7:0]"
line.long 0x14 "GIOLVLCLR,GIO low priority interrupt for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x14 24.--31. 1. "GIOLVLCLR_3,GIO low priority interrupt for pins GIOD[7:0]"
hexmask.long.byte 0x14 16.--23. 1. "GIOLVLCLR_2,GIO low priority interrupt for pins GIOC[7:0]"
hexmask.long.byte 0x14 8.--15. 1. "GIOLVLCLR_1,GIO low priority interrupt for pins GIOB[7:0]"
hexmask.long.byte 0x14 0.--7. 1. "GIOLVLCLR_0,GIO low priority interrupt for pins GIOA[7:0]"
line.long 0x18 "GIOFLG,GIO flag for pins [0:1] GIO[7:0]"
hexmask.long.byte 0x18 24.--31. 1. "GIOFLG_3,GIO flag for pins GIOD[7:0]"
hexmask.long.byte 0x18 16.--23. 1. "GIOFLG_2,GIO flag for pins GIOC[7:0]"
hexmask.long.byte 0x18 8.--15. 1. "GIOFLG_1,GIO flag for pins GIOB[7:0]"
hexmask.long.byte 0x18 0.--7. 1. "GIOFLG_0,GIO flag for pins GIOA[7:0]"
line.long 0x1C "GIOOFFA,Index bits for currently pending high-priority interrupt Register A"
hexmask.long 0x1C 6.--31. 1. "NU1,Reserved"
bitfld.long 0x1C 0.--5. "GIOOFFA,Index bits for currently pending high-priority interrupt Register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x20 "GIOOFFB,Index bits for currently pending high-priority interrupt Register B"
hexmask.long 0x20 6.--31. 1. "NU2,Reserved"
bitfld.long 0x20 0.--5. "GIOOFFB,Index bits for currently pending high-priority interrupt Register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x24 "GIOEMUA,GIO emulation register A"
hexmask.long 0x24 6.--31. 1. "NU3,Reserved"
bitfld.long 0x24 0.--5. "GIOEMUA,GIO emulation register A" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x28 "GIOEMUB,GIO emulation register B"
hexmask.long 0x28 6.--31. 1. "NU4,Reserved"
bitfld.long 0x28 0.--5. "GIOEMUB,GIO emulation register B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x2C "GIODIRA,GIO data direction of pins in Port A"
hexmask.long.tbyte 0x2C 8.--31. 1. "NU5,Reserved"
hexmask.long.byte 0x2C 0.--7. 1. "GIODIRA,GIO data direction of pins in Port A"
line.long 0x30 "GIODINA,GIO data input for pins in port A"
hexmask.long.tbyte 0x30 8.--31. 1. "NU11,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "GIODINA,GIO data input for pins in port A"
line.long 0x34 "GIODOUTA,GIO data output for pins in port A"
hexmask.long.tbyte 0x34 8.--31. 1. "NU17,Reserved"
hexmask.long.byte 0x34 0.--7. 1. "GIODOUTA,GIO data output for pins in port A"
line.long 0x38 "GIOSETA,GIO data set for port A"
hexmask.long.tbyte 0x38 8.--31. 1. "NU23,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "GIODSETA,GIO data set for port A"
line.long 0x3C "GIOCLRA,GIO data clear for port A"
hexmask.long.tbyte 0x3C 8.--31. 1. "NU29,Reserved"
hexmask.long.byte 0x3C 0.--7. 1. "GIODCLRA,GIO data clear for port A"
line.long 0x40 "GIOPDRA,GIO open drain for port A"
hexmask.long.tbyte 0x40 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x40 0.--7. 1. "GIOPDRA,GIO open drain for port A"
line.long 0x44 "GIOPULDISA,GIO pul disable for port A"
hexmask.long.tbyte 0x44 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x44 0.--7. 1. "GIOPULDISA,GIO pull disable for port A"
line.long 0x48 "GIOPSLA,GIO pul select for port A"
hexmask.long.tbyte 0x48 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x48 0.--7. 1. "GIOPSLA,GIO pull select for port A"
line.long 0x4C "GIODIRB,GIO data direction of pins in Port B"
hexmask.long.tbyte 0x4C 8.--31. 1. "NU6,Reserved"
hexmask.long.byte 0x4C 0.--7. 1. "GIODIRB,GIO data direction of pins in Port B"
line.long 0x50 "GIODINB,GIO data input for pins in port B"
hexmask.long.tbyte 0x50 8.--31. 1. "NU12,Reserved"
hexmask.long.byte 0x50 0.--7. 1. "GIODINB,GIO data input for pins in port B"
line.long 0x54 "GIODOUTB,GIO data output for pins in port B"
hexmask.long.tbyte 0x54 8.--31. 1. "NU18,Reserved"
hexmask.long.byte 0x54 0.--7. 1. "GIODOUTB,GIO data output for pins in port B"
line.long 0x58 "GIOSETB,GIO data set for port B"
hexmask.long.tbyte 0x58 8.--31. 1. "NU24,Reserved"
hexmask.long.byte 0x58 0.--7. 1. "GIODSETB,GIO data set for port B"
line.long 0x5C "GIOCLRB,GIO data clear for port B"
hexmask.long.tbyte 0x5C 8.--31. 1. "NU30,Reserved"
hexmask.long.byte 0x5C 0.--7. 1. "GIODCLRB,GIO data clear for port B"
line.long 0x60 "GIOPDRB,GIO open drain for port B"
hexmask.long.tbyte 0x60 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x60 0.--7. 1. "GIOPDRB,GIO open drain for port B"
line.long 0x64 "GIOPULDISB,GIO pul disable for port B"
hexmask.long.tbyte 0x64 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x64 0.--7. 1. "GIOPULDISB,GIO pull disable for port B"
line.long 0x68 "GIOPSLB,GIO pul select for port B"
hexmask.long.tbyte 0x68 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x68 0.--7. 1. "GIOPSLB,GIO pull select for port B"
line.long 0x6C "GIODIRC,GIO data direction of pins in Port C"
hexmask.long.tbyte 0x6C 8.--31. 1. "NU7,Reserved"
hexmask.long.byte 0x6C 0.--7. 1. "GIODIRC,GIO data direction of pins in Port C"
line.long 0x70 "GIODINC,GIO data input for pins in port C"
hexmask.long.tbyte 0x70 8.--31. 1. "NU13,Reserved"
hexmask.long.byte 0x70 0.--7. 1. "GIODINC,GIO data input for pins in port C"
line.long 0x74 "GIODOUTC,GIO data output for pins in port C"
hexmask.long.tbyte 0x74 8.--31. 1. "NU19,Reserved"
hexmask.long.byte 0x74 0.--7. 1. "GIODOUTC,GIO data output for pins in port C"
line.long 0x78 "GIOSETC,GIO data set for port C"
hexmask.long.tbyte 0x78 8.--31. 1. "NU25,Reserved"
hexmask.long.byte 0x78 0.--7. 1. "GIODSETC,GIO data set for port C"
line.long 0x7C "GIOCLRC,GIO data clear for port C"
hexmask.long.tbyte 0x7C 8.--31. 1. "NU31,Reserved"
hexmask.long.byte 0x7C 0.--7. 1. "GIODCLRC,GIO data clear for port C"
line.long 0x80 "GIOPDRC,GIO open drain for port C"
hexmask.long.tbyte 0x80 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x80 0.--7. 1. "GIOPDRC,GIO open drain for port C"
line.long 0x84 "GIOPULDISC,GIO pul disable for port C"
hexmask.long.tbyte 0x84 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x84 0.--7. 1. "GIOPULDISC,GIO pull disable for port C"
line.long 0x88 "GIOPSLC,GIO pul select for port C"
hexmask.long.tbyte 0x88 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x88 0.--7. 1. "GIOPSLC,GIO pull select for port C"
line.long 0x8C "GIODIRD,GIO data direction of pins in Port D"
hexmask.long.tbyte 0x8C 8.--31. 1. "NU8,Reserved"
hexmask.long.byte 0x8C 0.--7. 1. "GIODIRD,GIO data direction of pins in Port D"
line.long 0x90 "GIODIND,GIO data input for pins in port D"
hexmask.long.tbyte 0x90 8.--31. 1. "NU14,Reserved"
hexmask.long.byte 0x90 0.--7. 1. "GIODIND,GIO data input for pins in port D"
line.long 0x94 "GIODOUTD,GIO data output for pins in port D"
hexmask.long.tbyte 0x94 8.--31. 1. "NU20,Reserved"
hexmask.long.byte 0x94 0.--7. 1. "GIODOUTD,GIO data output for pins in port D"
line.long 0x98 "GIOSETD,GIO data set for port D"
hexmask.long.tbyte 0x98 8.--31. 1. "NU26,Reserved"
hexmask.long.byte 0x98 0.--7. 1. "GIODSETD,GIO data set for port D"
line.long 0x9C "GIOCLRD,GIO data clear for port D"
hexmask.long.tbyte 0x9C 8.--31. 1. "NU32,Reserved"
hexmask.long.byte 0x9C 0.--7. 1. "GIODCLRD,GIO data clear for port D"
line.long 0xA0 "GIOPDRD,GIO open drain for port D"
hexmask.long.tbyte 0xA0 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA0 0.--7. 1. "GIOPDRD,GIO open drain for port D"
line.long 0xA4 "GIOPULDISD,GIO pul disable for port D"
hexmask.long.tbyte 0xA4 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA4 0.--7. 1. "GIOPULDISD,GIO pull disable for port D"
line.long 0xA8 "GIOPSLD,GIO pul select for port D"
hexmask.long.tbyte 0xA8 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0xA8 0.--7. 1. "GIOPSLD,GIO pull select for port D"
line.long 0xAC "GIODIRE,GIO data direction of pins in Port E"
hexmask.long.tbyte 0xAC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xAC 0.--7. 1. "GIODIRE,GIO data direction of pins in Port E"
line.long 0xB0 "GIODINE,GIO data input for pins in port E"
hexmask.long.tbyte 0xB0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xB0 0.--7. 1. "GIODINE,GIO data input for pins in port E"
line.long 0xB4 "GIODOUTE,GIO data output for pins in port E"
hexmask.long.tbyte 0xB4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xB4 0.--7. 1. "GIODOUTE,GIO data output for pins in port E"
line.long 0xB8 "GIOSETE,GIO data set for port E"
hexmask.long.tbyte 0xB8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xB8 0.--7. 1. "GIODSETE,GIO data set for port E"
line.long 0xBC "GIOCLRE,GIO data clear for port E"
hexmask.long.tbyte 0xBC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xBC 0.--7. 1. "GIODCLRE,GIO data clear for port E"
line.long 0xC0 "GIOPDRE,GIO open drain for port E"
hexmask.long.tbyte 0xC0 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC0 0.--7. 1. "GIOPDRE,GIO open drain for port E"
line.long 0xC4 "GIOPULDISE,GIO pul disable for port E"
hexmask.long.tbyte 0xC4 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC4 0.--7. 1. "GIOPULDISE,GIO pull disable for port E"
line.long 0xC8 "GIOPSLE,GIO pul select for port E"
hexmask.long.tbyte 0xC8 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0xC8 0.--7. 1. "GIOPSLE,GIO pull select for port E"
line.long 0xCC "GIODIRF,GIO data direction of pins in Port F"
hexmask.long.tbyte 0xCC 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0xCC 0.--7. 1. "GIODIRF,GIO data direction of pins in Port F"
line.long 0xD0 "GIODINF,GIO data input for pins in Port F"
hexmask.long.tbyte 0xD0 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0xD0 0.--7. 1. "GIODINF,GIO data input for pins in port F"
line.long 0xD4 "GIODOUTF,GIO data output for pins in Port F"
hexmask.long.tbyte 0xD4 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0xD4 0.--7. 1. "GIODOUTF,GIO data output for pins in port F"
line.long 0xD8 "GIOSETF,GIO data set for Port F"
hexmask.long.tbyte 0xD8 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0xD8 0.--7. 1. "GIODSETF,GIO data set for port F"
line.long 0xDC "GIOCLRF,GIO data clear for Port F"
hexmask.long.tbyte 0xDC 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0xDC 0.--7. 1. "GIODCLRF,GIO data clear for port F"
line.long 0xE0 "GIOPDRF,GIO open drain for Port F"
hexmask.long.tbyte 0xE0 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE0 0.--7. 1. "GIOPDRF,GIO open drain for port F"
line.long 0xE4 "GIOPULDISF,GIO pul disable for port F"
hexmask.long.tbyte 0xE4 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE4 0.--7. 1. "GIOPULDISF,GIO pull disable for port F"
line.long 0xE8 "GIOPSLF,GIO pul select for port F"
hexmask.long.tbyte 0xE8 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0xE8 0.--7. 1. "GIOPSLF,GIO pull select for port F"
line.long 0xEC "GIODIRG,GIO data direction of pins in Port G"
hexmask.long.tbyte 0xEC 8.--31. 1. "NU9,Reserved"
hexmask.long.byte 0xEC 0.--7. 1. "GIODIRG,GIO data direction of pins in Port G"
line.long 0xF0 "GIODING,GIO data input for pins in port G"
hexmask.long.tbyte 0xF0 8.--31. 1. "NU15,Reserved"
hexmask.long.byte 0xF0 0.--7. 1. "GIODING,GIO data input for pins in port G"
line.long 0xF4 "GIODOUTG,GIO data output for pins in port G"
hexmask.long.tbyte 0xF4 8.--31. 1. "NU21,Reserved"
hexmask.long.byte 0xF4 0.--7. 1. "GIODOUTG,GIO data output for pins in port G"
line.long 0xF8 "GIOSETG,GIO data set for port G"
hexmask.long.tbyte 0xF8 8.--31. 1. "NU27,Reserved"
hexmask.long.byte 0xF8 0.--7. 1. "GIODSETG,GIO data set for port G"
line.long 0xFC "GIOCLRG,GIO data clear for port G"
hexmask.long.tbyte 0xFC 8.--31. 1. "NU33,Reserved"
hexmask.long.byte 0xFC 0.--7. 1. "GIODCLRG,GIO data clear for port G"
line.long 0x100 "GIOPDRG,GIO open drain for port G"
hexmask.long.tbyte 0x100 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x100 0.--7. 1. "GIOPDRG,GIO open drain for port G"
line.long 0x104 "GIOPULDISG,GIO pul disable for port G"
hexmask.long.tbyte 0x104 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x104 0.--7. 1. "GIOPULDISG,GIO pull disable for port G"
line.long 0x108 "GIOPSLG,GIO pul select for port G"
hexmask.long.tbyte 0x108 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x108 0.--7. 1. "GIOPSLG,GIO pull select for port G"
line.long 0x10C "GIODIRH,GIO data direction of pins in Port H"
hexmask.long.tbyte 0x10C 8.--31. 1. "NU10,Reserved"
hexmask.long.byte 0x10C 0.--7. 1. "GIODIRH,GIO data direction of pins in Port H"
line.long 0x110 "GIODINH,GIO data input for pins in Port H"
hexmask.long.tbyte 0x110 8.--31. 1. "NU16,Reserved"
hexmask.long.byte 0x110 0.--7. 1. "GIODINH,GIO data input for pins in port H"
line.long 0x114 "GIODOUTH,GIO data output for pins in Port H"
hexmask.long.tbyte 0x114 8.--31. 1. "NU22,Reserved"
hexmask.long.byte 0x114 0.--7. 1. "GIODOUTH,GIO data output for pins in port H"
line.long 0x118 "GIOSETH,GIO data set for Port H"
hexmask.long.tbyte 0x118 8.--31. 1. "NU28,Reserved"
hexmask.long.byte 0x118 0.--7. 1. "GIODSETH,GIO data set for port H"
line.long 0x11C "GIOCLRH,GIO data clear for Port H"
hexmask.long.tbyte 0x11C 8.--31. 1. "NU34,Reserved"
hexmask.long.byte 0x11C 0.--7. 1. "GIODCLRH,GIO data clear for port H"
line.long 0x120 "GIOPDRH,GIO open drain for Port H"
hexmask.long.tbyte 0x120 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x120 0.--7. 1. "GIOPDRH,GIO open drain for port H"
line.long 0x124 "GIOPULDISH,GIO pul disable for port H"
hexmask.long.tbyte 0x124 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x124 0.--7. 1. "GIOPULDISH,GIO pull disable for port H"
line.long 0x128 "GIOPSLH,GIO pul select for port H"
hexmask.long.tbyte 0x128 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x128 0.--7. 1. "GIOPSLH,GIO pull select for port H"
line.long 0x12C "GIOSRCA,GIO slew rate select for port A"
hexmask.long.tbyte 0x12C 8.--31. 1. "NU35,Reserved"
hexmask.long.byte 0x12C 0.--7. 1. "GIOSRCA,GIO slew rate control for port A"
line.long 0x130 "GIOSRCB,GIO slew rate select for port B"
hexmask.long.tbyte 0x130 8.--31. 1. "NU36,Reserved"
hexmask.long.byte 0x130 0.--7. 1. "GIOSRCB,GIO slew rate control for port B"
line.long 0x134 "GIOSRCC,GIO slew rate select for port C"
hexmask.long.tbyte 0x134 8.--31. 1. "NU37,Reserved"
hexmask.long.byte 0x134 0.--7. 1. "GIOSRCC,GIO slew rate control for port C"
line.long 0x138 "GIOSRCD,GIO slew rate select for port D"
hexmask.long.tbyte 0x138 8.--31. 1. "NU38,Reserved"
hexmask.long.byte 0x138 0.--7. 1. "GIOSRCD,GIO slew rate control for port D"
line.long 0x13C "GIOSRCE,GIO slew rate select for port E"
hexmask.long.tbyte 0x13C 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x13C 0.--7. 1. "GIOSRCE,GIO slew rate control for port E"
line.long 0x140 "GIOSRCF,GIO slew rate select for port F"
hexmask.long.tbyte 0x140 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x140 0.--7. 1. "GIOSRCF,GIO slew rate control for port F"
line.long 0x144 "GIOSRCG,GIO slew rate select for port G"
hexmask.long.tbyte 0x144 8.--31. 1. "NU39,Reserved"
hexmask.long.byte 0x144 0.--7. 1. "GIOSRCG,GIO slew rate control for port G"
line.long 0x148 "GIOSRCH,GIO slew rate select for port H"
hexmask.long.tbyte 0x148 8.--31. 1. "NU40,Reserved"
hexmask.long.byte 0x148 0.--7. 1. "GIOSRCH,GIO slew rate control for port H"
width 0x0B
tree.end
tree "RCSS_I2CA (RCSS I2CA Module Registers)"
base ad:0x5F7EC00
group.long 0x00++0x3F
line.long 0x00 "ICOAR,I2C Own Address register"
hexmask.long.tbyte 0x00 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x00 0.--9. 1. "A9_A0,Own address"
line.long 0x04 "ICIMR,I2C Interrupt Mask/Status register"
hexmask.long 0x04 7.--31. 1. "NU,Reserved"
bitfld.long 0x04 6. "AAS,Address As Slave interrupt mask bit" "0,1"
newline
bitfld.long 0x04 5. "SCD,Stop Condition Detection mask bit" "0,1"
bitfld.long 0x04 4. "ICXRDY,Transmit Data Ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 3. "ICRRDY,Receive Data Ready interrupt mask bit" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 1. "NACK,No Acknowledgement interrupt mask bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration Lost interrupt mask bit" "0,1"
line.long 0x08 "ICSTR,I2C Interrupt Status register"
hexmask.long.tbyte 0x08 15.--31. 1. "NU2,Reserved"
bitfld.long 0x08 14. "SDIR,Slave Direction" "0,1"
newline
bitfld.long 0x08 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'" "0,1"
bitfld.long 0x08 12. "BB,Bus Busy" "0,1"
newline
bitfld.long 0x08 11. "RSFULL,Receive shift full" "0,1"
bitfld.long 0x08 10. "XSMT,Transmit shift empty not" "0,1"
newline
bitfld.long 0x08 9. "AAS,Address As Slave" "0,1"
bitfld.long 0x08 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call)" "0,1"
newline
bitfld.long 0x08 6.--7. "NU1,Reserved" "0,1,2,3"
bitfld.long 0x08 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition" "0,1"
newline
bitfld.long 0x08 4. "ICXRDY,Transmit Data Ready interrupt flag bit" "0,1"
bitfld.long 0x08 3. "ICRRDY,Receive Data Ready interrupt flag bit" "0,1"
newline
bitfld.long 0x08 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
bitfld.long 0x08 1. "NACK,No-Acknowledgement interrupt flag bit" "0,1"
newline
bitfld.long 0x08 0. "AL,Arbitration-Lost interrupt flag bit" "0,1"
line.long 0x0C "ICCLKL,I2C Clock Divider Low register"
hexmask.long.word 0x0C 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "ICCL15_ICCL0,Low time I2C SCL Clock Division Factor"
line.long 0x10 "ICCLKH,I2C Clock Divider High register"
hexmask.long.word 0x10 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I2C SCL Clock Division Factor"
line.long 0x14 "ICCNT,I2C Data Count register"
hexmask.long.word 0x14 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count"
line.long 0x18 "ICDRR,I2C Data Receive register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data"
line.long 0x1C "ICSAR,I2C Slave Address register"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address"
line.long 0x20 "ICDXR,I2C Data Transmit register"
hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data"
line.long 0x24 "ICMDR,I2C Mode register"
hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved"
bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode" "0,1"
newline
bitfld.long 0x24 14. "FREE,Free Running" "0,1"
bitfld.long 0x24 13. "STT,Start Condition (Master only mode)" "0,1"
newline
bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509)" "0,1"
bitfld.long 0x24 11. "STP,Stop Condition (Master mode only)" "0,1"
newline
bitfld.long 0x24 10. "MST,Master" "0,1"
bitfld.long 0x24 9. "TRX,Transmitter" "0,1"
newline
bitfld.long 0x24 8. "XA,Expanded Address" "0,1"
bitfld.long 0x24 7. "RM,Repeat Mode" "0,1"
newline
bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only)" "0,1"
bitfld.long 0x24 5. "IRS,I2C Reset Not" "0,1"
newline
bitfld.long 0x24 4. "STB,Start Byte (Master only mode)" "0,1"
bitfld.long 0x24 3. "FDF,Free Data Format" "0,1"
newline
bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted" "0,1,2,3,4,5,6,7"
line.long 0x28 "ICIVR,I2C Interrupt Vector register"
hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved"
bitfld.long 0x28 8.--11. "TESTMD,Reserved for internal testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 3.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--2. "INTCODE,Interrupt code" "0,1,2,3,4,5,6,7"
line.long 0x2C "ICEMDR,I2C Extended Mode register"
hexmask.long 0x2C 2.--31. 1. "NU,Reserved"
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave" "0,1"
newline
bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode" "0,1"
line.long 0x30 "ICPSC,I2C Prescaler register"
hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module"
line.long 0x34 "ICPID1,I2C Peripheral ID register 1"
hexmask.long.word 0x34 16.--31. 1. "NU,Reserved"
hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral"
newline
hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C"
line.long 0x38 "ICPID2,I2C Peripheral ID register 2"
hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral"
line.long 0x3C "ICDMAC,I2C DMA Control Register"
hexmask.long 0x3C 2.--31. 1. "NU,Reserved"
bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable" "0,1"
newline
bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable" "0,1"
group.long 0x48++0x1B
line.long 0x00 "ICPFUNC,I2C Pin Function register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved"
bitfld.long 0x00 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins" "Pins function as SCL and SDA,Pins functions as GPIO"
line.long 0x04 "ICPDIR,I2C Pin Direction register"
hexmask.long 0x04 2.--31. 1. "NU,Reserved"
bitfld.long 0x04 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO" "SDA pin functions as input,SDA pin functions as output"
newline
bitfld.long 0x04 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO" "SCL pin functions as input,SCL pin functions as output"
line.long 0x08 "ICPDIN,I2C Pin Data In register"
hexmask.long 0x08 2.--31. 1. "NU,Reserved"
bitfld.long 0x08 1. "PDIN1,Indicates the logic level present on the SDA pin" "Logic low present at SDA pin regardless of PFUNC..,Logic high present at SDA pin regardless of.."
newline
bitfld.long 0x08 0. "PDIN0,Indicates the logic level present on the SCL pin" "Logic low present at SCL pin regardless of PFUNC..,Logic high present at SCL pin regardless of.."
line.long 0x0C "ICPDOUT,I2C Pin Data Out register"
hexmask.long 0x0C 2.--31. 1. "NU,Reserved"
bitfld.long 0x0C 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output" "SDA pin driven low,SDA pin driven high"
newline
bitfld.long 0x0C 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output" "SCL pin driven low,SCL pin driven high"
line.long 0x10 "ICPDSET,I2C Pin Data Set register"
hexmask.long 0x10 2.--31. 1. "NU,Reserved"
bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin" "no effect,PDOUT[1] bit is set to.."
newline
bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin" "no effect,PDOUT[0] bit is set to.."
line.long 0x14 "ICPDCLR,I2C Pin Data Clear register"
hexmask.long 0x14 2.--31. 1. "NU,Reserved"
bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin" "no effect,PDOUT[1] bit is cleared.."
newline
bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin" "no effect,PDOUT[0] bit is cleared.."
line.long 0x18 "ICPDRV,I2C Pin Driver Mode Register"
hexmask.long 0x18 2.--31. 1. "NU,Reserved"
bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin" "I2C mode,GPIO mode"
newline
bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin" "I2C mode,GPIO mode"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "I2C_RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "RCSS_I2CB (RCSS I2CB Module Registers)"
base ad:0x5F7F000
group.long 0x00++0x3F
line.long 0x00 "ICOAR,I2C Own Address register"
hexmask.long.tbyte 0x00 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x00 0.--9. 1. "A9_A0,Own address"
line.long 0x04 "ICIMR,I2C Interrupt Mask/Status register"
hexmask.long 0x04 7.--31. 1. "NU,Reserved"
bitfld.long 0x04 6. "AAS,Address As Slave interrupt mask bit" "0,1"
newline
bitfld.long 0x04 5. "SCD,Stop Condition Detection mask bit" "0,1"
bitfld.long 0x04 4. "ICXRDY,Transmit Data Ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 3. "ICRRDY,Receive Data Ready interrupt mask bit" "0,1"
bitfld.long 0x04 2. "ARDY,Register access ready interrupt mask bit" "0,1"
newline
bitfld.long 0x04 1. "NACK,No Acknowledgement interrupt mask bit" "0,1"
bitfld.long 0x04 0. "AL,Arbitration Lost interrupt mask bit" "0,1"
line.long 0x08 "ICSTR,I2C Interrupt Status register"
hexmask.long.tbyte 0x08 15.--31. 1. "NU2,Reserved"
bitfld.long 0x08 14. "SDIR,Slave Direction" "0,1"
newline
bitfld.long 0x08 13. "NACKSNT,A No Acknowledge is sent due to NACKMOD is set to a'1'" "0,1"
bitfld.long 0x08 12. "BB,Bus Busy" "0,1"
newline
bitfld.long 0x08 11. "RSFULL,Receive shift full" "0,1"
bitfld.long 0x08 10. "XSMT,Transmit shift empty not" "0,1"
newline
bitfld.long 0x08 9. "AAS,Address As Slave" "0,1"
bitfld.long 0x08 8. "AD0,Address Zero Status: This bit is set to 1 by device if it detects the address of all (8) zeros (i.e. general call)" "0,1"
newline
bitfld.long 0x08 6.--7. "NU1,Reserved" "0,1,2,3"
bitfld.long 0x08 5. "SCD,Stop Condition Detection bit SCD is set when the I2C sends or receives STOP condition" "0,1"
newline
bitfld.long 0x08 4. "ICXRDY,Transmit Data Ready interrupt flag bit" "0,1"
bitfld.long 0x08 3. "ICRRDY,Receive Data Ready interrupt flag bit" "0,1"
newline
bitfld.long 0x08 2. "ARDY,Register-access-ready interrupt flag bit" "0,1"
bitfld.long 0x08 1. "NACK,No-Acknowledgement interrupt flag bit" "0,1"
newline
bitfld.long 0x08 0. "AL,Arbitration-Lost interrupt flag bit" "0,1"
line.long 0x0C "ICCLKL,I2C Clock Divider Low register"
hexmask.long.word 0x0C 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x0C 0.--15. 1. "ICCL15_ICCL0,Low time I2C SCL Clock Division Factor"
line.long 0x10 "ICCLKH,I2C Clock Divider High register"
hexmask.long.word 0x10 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x10 0.--15. 1. "ICCH15_ICCLH0,High time I2C SCL Clock Division Factor"
line.long 0x14 "ICCNT,I2C Data Count register"
hexmask.long.word 0x14 16.--31. 1. "NU,Reserved"
hexmask.long.word 0x14 0.--15. 1. "ICDC15_ICDC0,Data count"
line.long 0x18 "ICDRR,I2C Data Receive register"
hexmask.long.tbyte 0x18 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x18 0.--7. 1. "D7_D0,Receive data"
line.long 0x1C "ICSAR,I2C Slave Address register"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU,Reserved"
hexmask.long.word 0x1C 0.--9. 1. "A9_A0,Slave address"
line.long 0x20 "ICDXR,I2C Data Transmit register"
hexmask.long.tbyte 0x20 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x20 0.--7. 1. "D7_D0,Transmit data"
line.long 0x24 "ICMDR,I2C Mode register"
hexmask.long.word 0x24 16.--31. 1. "NU2,Reserved"
bitfld.long 0x24 15. "NACKMOD,No Acknowledge (NACK) mode" "0,1"
newline
bitfld.long 0x24 14. "FREE,Free Running" "0,1"
bitfld.long 0x24 13. "STT,Start Condition (Master only mode)" "0,1"
newline
bitfld.long 0x24 12. "NU1,Reserved for IDLEEN (IDLE Enable on 5509)" "0,1"
bitfld.long 0x24 11. "STP,Stop Condition (Master mode only)" "0,1"
newline
bitfld.long 0x24 10. "MST,Master" "0,1"
bitfld.long 0x24 9. "TRX,Transmitter" "0,1"
newline
bitfld.long 0x24 8. "XA,Expanded Address" "0,1"
bitfld.long 0x24 7. "RM,Repeat Mode" "0,1"
newline
bitfld.long 0x24 6. "DLB,Digital Loop Back (in master transmit mode only)" "0,1"
bitfld.long 0x24 5. "IRS,I2C Reset Not" "0,1"
newline
bitfld.long 0x24 4. "STB,Start Byte (Master only mode)" "0,1"
bitfld.long 0x24 3. "FDF,Free Data Format" "0,1"
newline
bitfld.long 0x24 0.--2. "BC2_BC1_BC0,Bit Count : Bit Count 2 Bit Count 1 and Bit Count 0 define the number of bits starting from the lsb (excluding the acknowledge bit) of the next byte which are yet to be received or transmitted" "0,1,2,3,4,5,6,7"
line.long 0x28 "ICIVR,I2C Interrupt Vector register"
hexmask.long.tbyte 0x28 12.--31. 1. "NU2,Reserved"
bitfld.long 0x28 8.--11. "TESTMD,Reserved for internal testing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 3.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x28 0.--2. "INTCODE,Interrupt code" "0,1,2,3,4,5,6,7"
line.long 0x2C "ICEMDR,I2C Extended Mode register"
hexmask.long 0x2C 2.--31. 1. "NU,Reserved"
bitfld.long 0x2C 1. "IGNACK,Ignore NACK mode IGNACK=0 The master transmitter will operate normally discontinue the data transfer and set the ARDY and NACK status bits when a NACK signal is received from the slave" "0,1"
newline
bitfld.long 0x2C 0. "BCM,Backward Compatibility Mode" "0,1"
line.long 0x30 "ICPSC,I2C Prescaler register"
hexmask.long.tbyte 0x30 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x30 0.--7. 1. "IPSC7_IPSC0,8-bit prescaler to divide the system clock down to 4/8/12Mhz clock and used by the I2C module"
line.long 0x34 "ICPID1,I2C Peripheral ID register 1"
hexmask.long.word 0x34 16.--31. 1. "NU,Reserved"
hexmask.long.byte 0x34 8.--15. 1. "CLASS,Identifies the class of peripheral"
newline
hexmask.long.byte 0x34 0.--7. 1. "REVISION,Identifies the revision level of the I2C"
line.long 0x38 "ICPID2,I2C Peripheral ID register 2"
hexmask.long.tbyte 0x38 8.--31. 1. "NU,Reserved"
hexmask.long.byte 0x38 0.--7. 1. "TYPE,Identifies the type of peripheral"
line.long 0x3C "ICDMAC,I2C DMA Control Register"
hexmask.long 0x3C 2.--31. 1. "NU,Reserved"
bitfld.long 0x3C 1. "TXDMAEN,Transmit DMA enable" "0,1"
newline
bitfld.long 0x3C 0. "RXDMAEN,Receive DMA enable" "0,1"
group.long 0x48++0x1B
line.long 0x00 "ICPFUNC,I2C Pin Function register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved"
bitfld.long 0x00 0. "PFUNC0,Controls the function of the I2C SCL and SDA pins" "Pins function as SCL and SDA,Pins functions as GPIO"
line.long 0x04 "ICPDIR,I2C Pin Direction register"
hexmask.long 0x04 2.--31. 1. "NU,Reserved"
bitfld.long 0x04 1. "PDIR1,Controls the direction of the I2C SDA pin when configured as GPIO" "SDA pin functions as input,SDA pin functions as output"
newline
bitfld.long 0x04 0. "PDIR0,Controls the direction of the I2C SCL pin when configured as GPIO" "SCL pin functions as input,SCL pin functions as output"
line.long 0x08 "ICPDIN,I2C Pin Data In register"
hexmask.long 0x08 2.--31. 1. "NU,Reserved"
bitfld.long 0x08 1. "PDIN1,Indicates the logic level present on the SDA pin" "Logic low present at SDA pin regardless of PFUNC..,Logic high present at SDA pin regardless of.."
newline
bitfld.long 0x08 0. "PDIN0,Indicates the logic level present on the SCL pin" "Logic low present at SCL pin regardless of PFUNC..,Logic high present at SCL pin regardless of.."
line.long 0x0C "ICPDOUT,I2C Pin Data Out register"
hexmask.long 0x0C 2.--31. 1. "NU,Reserved"
bitfld.long 0x0C 1. "PDOUT1,Controls the level driven on the SDA pin when configured as GPIO output" "SDA pin driven low,SDA pin driven high"
newline
bitfld.long 0x0C 0. "PDOUT0,Controls the level driven on the SCL pin when configured as GPIO output" "SCL pin driven low,SCL pin driven high"
line.long 0x10 "ICPDSET,I2C Pin Data Set register"
hexmask.long 0x10 2.--31. 1. "NU,Reserved"
bitfld.long 0x10 1. "PDSET1,Used to set PDOUT[1] bit which corresponds to the SDA GPIO pin" "no effect,PDOUT[1] bit is set to.."
newline
bitfld.long 0x10 0. "PDSET0,Used to set PDOUT[0] bit which corresponds to the SCL GPIO pin" "no effect,PDOUT[0] bit is set to.."
line.long 0x14 "ICPDCLR,I2C Pin Data Clear register"
hexmask.long 0x14 2.--31. 1. "NU,Reserved"
bitfld.long 0x14 1. "PDCLR1,Used to clear PDOUT[1] bit which corresponds to the SDA pin" "no effect,PDOUT[1] bit is cleared.."
newline
bitfld.long 0x14 0. "PDCLR0,Used to clear PDOUT[0] bit which corresponds to the SCL pin" "no effect,PDOUT[0] bit is cleared.."
line.long 0x18 "ICPDRV,I2C Pin Driver Mode Register"
hexmask.long 0x18 2.--31. 1. "NU,Reserved"
bitfld.long 0x18 1. "PDRV1,Used to select driver mode of output buffer for SDA pin" "I2C mode,GPIO mode"
newline
bitfld.long 0x18 0. "PDRV0,Used to select driver mode of output buffer for SCL pin" "I2C mode,GPIO mode"
repeat 2. (list 1. 2. )(list 0x00 0x04 )
group.long ($2+0x40)++0x03
line.long 0x00 "I2C_RESERVED$1,Reserved"
repeat.end
width 0x0B
tree.end
tree "RCSS_MCASP_A (RCSS McASP A Module Registers)"
base ad:0x51E0000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 2.--5. "UNDEFINED_NAME,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Power management Configuration of the local target state management mode" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x10++0x13
line.long 0x00 "PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "UNDEFINED_NAME,Determines if AFSR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 28. "UNDEFINED_NAME,Determines if AFSX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x00 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x00 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x04 "PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "UNDEFINED_NAME,Determines if AFSR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 28. "UNDEFINED_NAME,Determines if AFSX pin functions as an input or output" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as an input or output" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x04 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x04 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as an input or output" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x08 "PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "UNDEFINED_NAME,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 30. "UNDEFINED_NAME,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x08 29. "UNDEFINED_NAME,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 28. "UNDEFINED_NAME,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x08 27. "UNDEFINED_NAME,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 26. "UNDEFINED_NAME,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x08 25. "UNDEFINED_NAME,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x08 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x08 0.--3. "UNDEFINED_NAME,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x0C "PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "UNDEFINED_NAME,Logic level on AFSR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 30. "UNDEFINED_NAME,Logic level on AHCLKR pin" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 29. "UNDEFINED_NAME,Logic level on ACLKR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 28. "UNDEFINED_NAME,Logic level on AFSX pin" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 27. "UNDEFINED_NAME,Logic level on AHCLKX pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 26. "UNDEFINED_NAME,Logic level on ACLKX pin" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 25. "UNDEFINED_NAME,Logic level on AMUTE pin" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x0C 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x0C 0.--3. "UNDEFINED_NAME,Logic level on AXR[n] pin" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x10 "PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "UNDEFINED_NAME,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 30. "UNDEFINED_NAME,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 29. "UNDEFINED_NAME,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 28. "UNDEFINED_NAME,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 27. "UNDEFINED_NAME,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 26. "UNDEFINED_NAME,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 25. "UNDEFINED_NAME,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x10 4.--24. 1. "UNDEFINED_NAME,"
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bitfld.long 0x10 0.--3. "UNDEFINED_NAME,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
group.long 0x44++0x0F
line.long 0x00 "GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 12. "UNDEFINED_NAME,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 11. "UNDEFINED_NAME,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 10. "UNDEFINED_NAME,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 9. "UNDEFINED_NAME,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 8. "UNDEFINED_NAME,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 7. "UNDEFINED_NAME,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 6. "UNDEFINED_NAME,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 5. "UNDEFINED_NAME,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x04 4. "UNDEFINED_NAME,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 3. "UNDEFINED_NAME,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2. "UNDEFINED_NAME,Audio mute in [AMUTEIN] polarity select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x04 0.--1. "UNDEFINED_NAME,AMUTE pin enable bit [unless overridden by GPIO registers]" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Loopback generator mode bits" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 1. "UNDEFINED_NAME,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Loopback mode enable bit" "en_1_0x0,en_2_0x1"
line.long 0x0C "DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Valid bit for odd time slots [DIT right subframe]" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 2. "UNDEFINED_NAME,Valid bit for even time slots [DIT left subframe]" "en_1_0x0,en_2_0x1"
rbitfld.long 0x0C 1. "UNDEFINED_NAME," "0,1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,DIT mode enable bit" "en_1_0x0,en_2_0x1"
group.long 0x60++0x2F
line.long 0x00 "RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "0,1"
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rbitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "0,1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Receive bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 15. "UNDEFINED_NAME,Receive serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to the word" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 8.--12. "UNDEFINED_NAME,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Receive slot size" "en_7_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_5_0xA,en_1_0xB,en_4_0xC,en_2_0xD,en_6_0xE,en_3_0xF"
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bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for receive rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Receive frame sync mode select bits"
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rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Receive frame sync generation select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,Receive frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Receive bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Receive bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Receive high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Receive bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Receive start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Receive data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Receive last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Receive DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Receive clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected receive frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Receiver overrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Receive DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Receive start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Receive data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Receive last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of RSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Receive clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected receive frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Receiver overrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--8. 1. "UNDEFINED_NAME,"
line.long 0x28 "RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Receive clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Receive clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Receive data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0xA0++0x2F
line.long 0x00 "XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "0,1"
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rbitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Transmit sync bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 15. "UNDEFINED_NAME,Transmit serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to word defined by XMASK" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 8.--12. "UNDEFINED_NAME,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Transmit slot size" "en_2_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_7_0xA,en_5_0xB,en_6_0xC,en_3_0xD,en_1_0xE,en_4_0xF"
newline
bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for transmit rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Transmit frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Transmit frame sync generation select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,Transmit frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Transmit bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 6. "UNDEFINED_NAME,Transmit/receive operation asynchronous enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Transmit bit clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Transmit high-frequency clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x14 14. "UNDEFINED_NAME,Transmit bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Transmit start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Transmit data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Transmit DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 2. "UNDEFINED_NAME,Transmit clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected transmit frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 0. "UNDEFINED_NAME,Transmitter underrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 7. "UNDEFINED_NAME,Transmit DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Transmit start of frame flag" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 5. "UNDEFINED_NAME,Transmit data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Transmit last slot flag" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of XSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Transmit clock failure flag" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected transmit frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Transmitter underrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--9. 1. "UNDEFINED_NAME,Current transmit time slot count"
line.long 0x28 "XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Transmit clock maximum boundary"
newline
hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Transmit clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Transmit data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
group.long 0x180++0x3F
line.long 0x00 "SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x00 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x00 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x04 "SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x04 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x04 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x08 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x08 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x08 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x0C "SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x0C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x0C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x0C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x10 "SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x10 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x10 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x10 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x10 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x14 "SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x14 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x14 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x14 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x14 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x14 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x18 "SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x18 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x18 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x18 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x18 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x18 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x1C "SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x1C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x1C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x1C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x20 "SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x20 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x20 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x20 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x20 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x24 "SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x24 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x24 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x24 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x24 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x24 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x28 "SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x28 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x28 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x28 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x28 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x28 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x2C "SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x2C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x2C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x2C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x2C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x2C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x30 "SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x30 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x30 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x30 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x30 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x30 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x34 "SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x34 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x34 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x34 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x34 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x34 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x38 "SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x38 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x38 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x38 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x38 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x38 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x3C "SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x3C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x3C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x3C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x3C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x3C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x1000++0x0F
line.long 0x00 "WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 16. "UNDEFINED_NAME,Write FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
hexmask.long.byte 0x00 8.--15. 1. "UNDEFINED_NAME,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "UNDEFINED_NAME,Write word count per transfer [32 bit words]"
line.long 0x04 "WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x04 0.--7. "UNDEFINED_NAME,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16. "UNDEFINED_NAME,Read FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
abitfld.long 0x08 8.--15. "UNDEFINED_NAME,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "UNDEFINED_NAME,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x0C 0.--7. "UNDEFINED_NAME,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
width 0x0B
tree.end
tree "RCSS_MCASP_B (RCSS McASP B Module Registers)"
base ad:0x5200000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 2.--5. "UNDEFINED_NAME,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Power management Configuration of the local target state management mode" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x10++0x13
line.long 0x00 "PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "UNDEFINED_NAME,Determines if AFSR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 28. "UNDEFINED_NAME,Determines if AFSX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x00 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x00 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x04 "PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "UNDEFINED_NAME,Determines if AFSR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 28. "UNDEFINED_NAME,Determines if AFSX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as an input or output" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x04 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as an input or output" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x08 "PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "UNDEFINED_NAME,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 30. "UNDEFINED_NAME,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 29. "UNDEFINED_NAME,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 28. "UNDEFINED_NAME,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 27. "UNDEFINED_NAME,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 26. "UNDEFINED_NAME,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 25. "UNDEFINED_NAME,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x08 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x0C "PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "UNDEFINED_NAME,Logic level on AFSR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 30. "UNDEFINED_NAME,Logic level on AHCLKR pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 29. "UNDEFINED_NAME,Logic level on ACLKR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 28. "UNDEFINED_NAME,Logic level on AFSX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 27. "UNDEFINED_NAME,Logic level on AHCLKX pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 26. "UNDEFINED_NAME,Logic level on ACLKX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 25. "UNDEFINED_NAME,Logic level on AMUTE pin" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x0C 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x0C 0.--3. "UNDEFINED_NAME,Logic level on AXR[n] pin" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x10 "PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "UNDEFINED_NAME,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 30. "UNDEFINED_NAME,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 29. "UNDEFINED_NAME,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 28. "UNDEFINED_NAME,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 27. "UNDEFINED_NAME,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 26. "UNDEFINED_NAME,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 25. "UNDEFINED_NAME,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x10 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x10 0.--3. "UNDEFINED_NAME,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
group.long 0x44++0x0F
line.long 0x00 "GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 12. "UNDEFINED_NAME,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 11. "UNDEFINED_NAME,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 10. "UNDEFINED_NAME,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 9. "UNDEFINED_NAME,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 8. "UNDEFINED_NAME,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 7. "UNDEFINED_NAME,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 6. "UNDEFINED_NAME,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 5. "UNDEFINED_NAME,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x04 4. "UNDEFINED_NAME,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 3. "UNDEFINED_NAME,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2. "UNDEFINED_NAME,Audio mute in [AMUTEIN] polarity select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,AMUTE pin enable bit [unless overridden by GPIO registers]" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Loopback generator mode bits" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 1. "UNDEFINED_NAME,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Loopback mode enable bit" "en_1_0x0,en_2_0x1"
line.long 0x0C "DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Valid bit for odd time slots [DIT right subframe]" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 2. "UNDEFINED_NAME,Valid bit for even time slots [DIT left subframe]" "en_1_0x0,en_2_0x1"
rbitfld.long 0x0C 1. "UNDEFINED_NAME," "0,1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,DIT mode enable bit" "en_1_0x0,en_2_0x1"
group.long 0x60++0x2F
line.long 0x00 "RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Receive bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 15. "UNDEFINED_NAME,Receive serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to the word" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 8.--12. "UNDEFINED_NAME,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Receive slot size" "en_7_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_5_0xA,en_1_0xB,en_4_0xC,en_2_0xD,en_6_0xE,en_3_0xF"
newline
bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for receive rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Receive frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Receive frame sync generation select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,Receive frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Receive bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x10 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Receive bit clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Receive high-frequency clock source bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x14 14. "UNDEFINED_NAME,Receive bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
newline
hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Receive start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Receive data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 4. "UNDEFINED_NAME,Receive last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Receive DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 2. "UNDEFINED_NAME,Receive clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected receive frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x1C 0. "UNDEFINED_NAME,Receiver overrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 7. "UNDEFINED_NAME,Receive DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Receive start of frame flag" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x20 5. "UNDEFINED_NAME,Receive data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Receive last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of RSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Receive clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected receive frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Receiver overrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--8. 1. "UNDEFINED_NAME,"
line.long 0x28 "RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Receive clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Receive clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Receive data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0xA0++0x2F
line.long 0x00 "XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "0,1"
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rbitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Transmit sync bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 15. "UNDEFINED_NAME,Transmit serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to word defined by XMASK" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 8.--12. "UNDEFINED_NAME,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Transmit slot size" "en_2_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_7_0xA,en_5_0xB,en_6_0xC,en_3_0xD,en_1_0xE,en_4_0xF"
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bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for transmit rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Transmit frame sync mode select bits"
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rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Transmit frame sync generation select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,Transmit frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Transmit bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 6. "UNDEFINED_NAME,Transmit/receive operation asynchronous enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Transmit bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Transmit high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Transmit bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Transmit start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Transmit data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Transmit DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Transmit clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected transmit frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Transmitter underrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Transmit DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Transmit start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Transmit data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Transmit last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of XSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Transmit clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected transmit frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Transmitter underrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--9. 1. "UNDEFINED_NAME,Current transmit time slot count"
line.long 0x28 "XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Transmit clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Transmit clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Transmit data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
group.long 0x180++0x3F
line.long 0x00 "SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x00 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x04 "SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x04 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x04 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x08 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x08 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x08 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x0C "SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x0C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x0C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x0C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x10 "SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x10 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x10 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x10 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x14 "SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x14 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x14 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x14 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x14 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x14 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x18 "SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x18 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x18 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x18 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x18 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x18 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x1C "SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x1C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x1C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x1C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x20 "SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x20 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x20 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x20 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x20 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x24 "SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x24 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x24 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x24 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x24 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x24 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x28 "SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x28 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x28 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x28 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x28 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x28 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x2C "SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x2C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x2C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x2C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x2C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x2C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x30 "SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x30 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x30 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x30 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x30 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x30 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x34 "SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x34 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x34 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x34 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x34 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x34 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x38 "SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x38 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x38 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x38 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x38 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x38 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x3C "SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x3C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x3C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x3C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x3C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x3C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x1000++0x0F
line.long 0x00 "WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 16. "UNDEFINED_NAME,Write FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
hexmask.long.byte 0x00 8.--15. 1. "UNDEFINED_NAME,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "UNDEFINED_NAME,Write word count per transfer [32 bit words]"
line.long 0x04 "WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x04 0.--7. "UNDEFINED_NAME,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16. "UNDEFINED_NAME,Read FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
abitfld.long 0x08 8.--15. "UNDEFINED_NAME,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "UNDEFINED_NAME,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x0C 0.--7. "UNDEFINED_NAME,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
width 0x0B
tree.end
tree "RCSS_MCASP_C (RCSS McASP C Module Registers)"
base ad:0x5220000
rgroup.long 0x00++0x07
line.long 0x00 "PID,The revision identification register (PID) contains identification data for the peripheral"
line.long 0x04 "PWRIDLESYSCONFIG,"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 2.--5. "UNDEFINED_NAME,Reserved for future programming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Power management Configuration of the local target state management mode" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x10++0x13
line.long 0x00 "PFUNC,The pin function register (PFUNC) specifies the function of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either a McASP pin or a general-purpose input/output (GPIO) pin"
bitfld.long 0x00 31. "UNDEFINED_NAME,Determines if AFSR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 28. "UNDEFINED_NAME,Determines if AFSX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x00 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x00 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as McASP or GPIO" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x04 "PDIR,The pin direction register (PDIR) specifies the direction of AXRn. ACLKX. AHCLKX. AFSX. ACLKR. AHCLKR. and AFSR pins as either an input or an output pin"
bitfld.long 0x04 31. "UNDEFINED_NAME,Determines if AFSR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 30. "UNDEFINED_NAME,Determines if AHCLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 29. "UNDEFINED_NAME,Determines if ACLKR pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 28. "UNDEFINED_NAME,Determines if AFSX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 27. "UNDEFINED_NAME,Determines if AHCLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 26. "UNDEFINED_NAME,Determines if ACLKX pin functions as an input or output" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 25. "UNDEFINED_NAME,Determines if AMUTE pin functions as an input or output" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x04 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x04 0.--3. "UNDEFINED_NAME,Determines if AXRn pin functions as an input or output" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x08 "PDOUT,The pin data output register (PDOUT) holds a value for data out at all times. and may be read back at all times"
bitfld.long 0x08 31. "UNDEFINED_NAME,Determines drive on AFSR output pin when the corresponding PFUNC[31] and PDIR[31] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 30. "UNDEFINED_NAME,Determines drive on AHCLKR output pin when the corresponding PFUNC[30] and PDIR[30] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 29. "UNDEFINED_NAME,Determines drive on ACLKR output pin when the corresponding PFUNC[29] and PDIR[29] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 28. "UNDEFINED_NAME,Determines drive on AFSX output pin when the corresponding PFUNC[28] and PDIR[28] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 27. "UNDEFINED_NAME,Determines drive on AHCLKX output pin when the corresponding PFUNC[27] and PDIR[27] bits are set to 1" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 26. "UNDEFINED_NAME,Determines drive on ACLKX output pin when the corresponding PFUNC[26] and PDIR[26] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x08 25. "UNDEFINED_NAME,Determines drive on AMUTE output pin when the corresponding PFUNC[25] and PDIR[25] bits are set to 1" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x08 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x08 0.--3. "UNDEFINED_NAME,Determines drive on AXR[n] output pin when the corresponding PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x0C "PDIN,The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins"
bitfld.long 0x0C 31. "UNDEFINED_NAME,Logic level on AFSR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 30. "UNDEFINED_NAME,Logic level on AHCLKR pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 29. "UNDEFINED_NAME,Logic level on ACLKR pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 28. "UNDEFINED_NAME,Logic level on AFSX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 27. "UNDEFINED_NAME,Logic level on AHCLKX pin" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 26. "UNDEFINED_NAME,Logic level on ACLKX pin" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 25. "UNDEFINED_NAME,Logic level on AMUTE pin" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x0C 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x0C 0.--3. "UNDEFINED_NAME,Logic level on AXR[n] pin" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x10 "PDCLR,The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only"
bitfld.long 0x10 31. "UNDEFINED_NAME,Allows the corresponding AFSR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 30. "UNDEFINED_NAME,Allows the corresponding AHCLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 29. "UNDEFINED_NAME,Allows the corresponding ACLKR bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 28. "UNDEFINED_NAME,Allows the corresponding AFSX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 27. "UNDEFINED_NAME,Allows the corresponding AHCLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 26. "UNDEFINED_NAME,Allows the corresponding ACLKX bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x10 25. "UNDEFINED_NAME,Allows the corresponding AMUTE bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1"
hexmask.long.tbyte 0x10 4.--24. 1. "UNDEFINED_NAME,"
newline
bitfld.long 0x10 0.--3. "UNDEFINED_NAME,Allows the corresponding AXR[n] bit in PDOUT to be cleared to a logic low without affecting other I/O pins controlled by the same port" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
group.long 0x44++0x0F
line.long 0x00 "GBLCTL,The global control register (GBLCTL) provides initialization of the transmit and receive sections"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "AMUTE,The audio mute control register (AMUTE) controls the McASP audio mute (AMUTE) output pin"
hexmask.long.tbyte 0x04 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x04 12. "UNDEFINED_NAME,If transmit DMA error [XDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 11. "UNDEFINED_NAME,If receive DMA error [RDMAERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 10. "UNDEFINED_NAME,If transmit clock failure [XCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 9. "UNDEFINED_NAME,If receive clock failure [RCKFAIL] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 8. "UNDEFINED_NAME,If unexpected transmit frame sync error [XSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 7. "UNDEFINED_NAME,If unexpected receive frame sync error [RSYNCERR] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 6. "UNDEFINED_NAME,If transmit underrun error [XUNDRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 5. "UNDEFINED_NAME,If receiver overrun error [ROVRN] drive AMUTE active enable bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x04 4. "UNDEFINED_NAME,Determines drive on AXRn pin when PFUNC[n] and PDIR[n] bits are set to 1" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 3. "UNDEFINED_NAME,Drive AMUTE active when AMUTEIN error is active [INSTAT = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2. "UNDEFINED_NAME,Audio mute in [AMUTEIN] polarity select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,AMUTE pin enable bit [unless overridden by GPIO registers]" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "DLBCTL,The digital loopback control register (DLBCTL) controls the internal loopback settings of the McASP in TDM mode"
hexmask.long 0x08 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Loopback generator mode bits" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 1. "UNDEFINED_NAME,Loopback order bit when loopback mode is enabled [DLBEN = 1]" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0. "UNDEFINED_NAME,Loopback mode enable bit" "en_1_0x0,en_2_0x1"
line.long 0x0C "DITCTL,The DIT mode control register (DITCTL) controls DIT operations of the McASP"
hexmask.long 0x0C 4.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x0C 3. "UNDEFINED_NAME,Valid bit for odd time slots [DIT right subframe]" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 2. "UNDEFINED_NAME,Valid bit for even time slots [DIT left subframe]" "en_1_0x0,en_2_0x1"
rbitfld.long 0x0C 1. "UNDEFINED_NAME," "0,1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,DIT mode enable bit" "en_1_0x0,en_2_0x1"
group.long 0x60++0x2F
line.long 0x00 "RGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "0,1"
newline
rbitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "0,1"
rbitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "0,1"
newline
rbitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "0,1"
newline
rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "en_1_0x0,en_2_0x1"
line.long 0x04 "RMASK,The receive format unit bit mask register (RMASK) determines which bits of the received data are masked off and padded with a known value before being read by the CPU or DMA"
line.long 0x08 "RFMT,The receive bit stream format register (RFMT) configures the receive data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Receive bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 15. "UNDEFINED_NAME,Receive serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to the word" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x08 8.--12. "UNDEFINED_NAME,RPBIT value determines which bit [as read by the CPU or DMA from RBUF[n]] is used to pad the extra bits" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Receive slot size" "en_7_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_5_0xA,en_1_0xB,en_4_0xC,en_2_0xD,en_6_0xE,en_3_0xF"
newline
bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether reads from serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for receive rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSRCTL,The receive frame sync control register (AFSRCTL) configures the receive frame sync (AFSR)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Receive frame sync mode select bits"
newline
rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Receive frame sync width select bit indicates the width of the receive frame sync [AFSR] during its active period" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Receive frame sync generation select bit" "en_1_0x0,en_2_0x1"
newline
bitfld.long 0x0C 0. "UNDEFINED_NAME,Receive frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKRCTL,The receive clock control register (ACLKRCTL) configures the receive bit clock (ACLKR) and the receive clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Receive bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Receive bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Receive bit clock divide ratio bits determine the divide-down ratio from AHCLKR to ACLKR" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKRCTL,The receive high-frequency clock control register (AHCLKRCTL) configures the receive high-frequency master clock (AHCLKR) and the receive clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Receive high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Receive bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Receive high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKR"
line.long 0x18 "RTDM,The receive TDM time slot register (RTDM) specifies which TDM time slot the receiver is active"
line.long 0x1C "RINTCTL,The receiver interrupt control register (RINTCTL) controls generation of the McASP receive interrupt (RINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Receive start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Receive data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Receive last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Receive DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Receive clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected receive frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Receiver overrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "RSTAT,The receiver status register (RSTAT) provides the receiver status and receive TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,RERR bit always returns a logic-OR of: ROVRN OR RSYNCERR OR RCKFAIL OR RDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Receive DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Receive start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Receive data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Receive last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of RSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Receive clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected receive frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Receiver overrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "RSLOT,The current receive TDM time slot register (RSLOT) indicates the current time slot for the receive data frame"
hexmask.long.tbyte 0x24 9.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--8. 1. "UNDEFINED_NAME,"
line.long 0x28 "RCLKCHK,The receive clock check control register (RCLKCHK) configures the receive clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Receive clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Receive clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Receive clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Receive clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "PIDTCTL,The receiver DMA event control register (PIDTCTL) contains a disable bit for the receiver DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Receive data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0xA0++0x2F
line.long 0x00 "XGBLCTL,Alias of the global control register (GBLCTL)"
hexmask.long.tbyte 0x00 13.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 12. "UNDEFINED_NAME,Transmit frame sync generator reset enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 11. "UNDEFINED_NAME,Transmit state machine reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 10. "UNDEFINED_NAME,Transmit serializer clear enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x00 9. "UNDEFINED_NAME,Transmit high-frequency clock divider reset enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 8. "UNDEFINED_NAME,Transmit clock divider reset enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 5.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7"
rbitfld.long 0x00 4. "UNDEFINED_NAME,Receive frame sync generator reset enable bit" "0,1"
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rbitfld.long 0x00 3. "UNDEFINED_NAME,Receive state machine reset enable bit" "0,1"
rbitfld.long 0x00 2. "UNDEFINED_NAME,Receive serializer clear enable bit" "0,1"
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rbitfld.long 0x00 1. "UNDEFINED_NAME,Receive high-frequency clock divider reset enable bit" "0,1"
rbitfld.long 0x00 0. "UNDEFINED_NAME,Receive clock divider reset enable bit" "0,1"
line.long 0x04 "XMASK,The transmit format unit bit mask register (XMASK) determines which bits of the transmitted data are masked off and padded with a known value before being shifted out the McASP"
line.long 0x08 "XFMT,The transmit bit stream format register (XFMT) configures the transmit data format"
hexmask.long.word 0x08 18.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16.--17. "UNDEFINED_NAME,Transmit sync bit delay" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 15. "UNDEFINED_NAME,Transmit serial bitstream order" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 13.--14. "UNDEFINED_NAME,Pad value for extra bits in slot not belonging to word defined by XMASK" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 8.--12. "UNDEFINED_NAME,XPBIT value determines which bit [as written by the CPU or DMA to XBUF[n]] is used to pad the extra bits before shifting" "en_1_0x0,en_2_0x1,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
bitfld.long 0x08 4.--7. "UNDEFINED_NAME,Transmit slot size" "en_2_0x0,en_8_0x1,en_9_0x2,en_10_0x3,en_11_0x4,en_12_0x5,en_13_0x6,en_14_0x7,en_15_0x8,en_16_0x9,en_7_0xA,en_5_0xB,en_6_0xC,en_3_0xD,en_1_0xE,en_4_0xF"
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bitfld.long 0x08 3. "UNDEFINED_NAME,Selects whether writes to serializer buffer XRBUF[n] originate from the configuration bus [CFG] or the data [DAT] port" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 0.--2. "UNDEFINED_NAME,Right-rotation value for transmit rotate right format unit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7"
line.long 0x0C "AFSXCTL,The transmit frame sync control register (AFSXCTL) configures the transmit frame sync (AFSX)"
hexmask.long.word 0x0C 16.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x0C 7.--15. 1. "UNDEFINED_NAME,Transmit frame sync mode select bits"
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rbitfld.long 0x0C 5.--6. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit frame sync width select bit indicates the width of the transmit frame sync [AFSX] during its active period" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 2.--3. "UNDEFINED_NAME," "0,1,2,3"
bitfld.long 0x0C 1. "UNDEFINED_NAME,Transmit frame sync generation select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x0C 0. "UNDEFINED_NAME,Transmit frame sync polarity select bit" "en_1_0x0,en_2_0x1"
line.long 0x10 "ACLKXCTL,The transmit clock control register (ACLKXCTL) configures the transmit bit clock (ACLKX) and the transmit clock generator"
hexmask.long.tbyte 0x10 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x10 7. "UNDEFINED_NAME,Transmit bitstream clock polarity select bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 6. "UNDEFINED_NAME,Transmit/receive operation asynchronous enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 5. "UNDEFINED_NAME,Transmit bit clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x10 0.--4. "UNDEFINED_NAME,Transmit bit clock divide ratio bits determine the divide-down ratio from AHCLKX to ACLKX" "en_1_0x0,en_2_0x1,en_3_0x2,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?"
line.long 0x14 "AHCLKXCTL,The transmit high-frequency clock control register (AHCLKXCTL) configures the transmit high-frequency master clock (AHCLKX) and the transmit clock generator"
hexmask.long.word 0x14 16.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x14 15. "UNDEFINED_NAME,Transmit high-frequency clock source bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x14 14. "UNDEFINED_NAME,Transmit bitstream high-frequency clock polarity select bit" "en_1_0x0,en_2_0x1"
rbitfld.long 0x14 12.--13. "UNDEFINED_NAME," "0,1,2,3"
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hexmask.long.word 0x14 0.--11. 1. "UNDEFINED_NAME,Transmit high-frequency clock divide ratio bits determine the divide-down ratio from AUXCLK to AHCLKX"
line.long 0x18 "XTDM,The transmit TDM time slot register (XTDM) specifies in which TDM time slot the transmitter is active"
line.long 0x1C "XINTCTL,The transmitter interrupt control register (XINTCTL) controls generation of the McASP transmit interrupt (XINT)"
hexmask.long.tbyte 0x1C 8.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x1C 7. "UNDEFINED_NAME,Transmit start of frame interrupt enable bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 6. "UNDEFINED_NAME," "0,1"
bitfld.long 0x1C 5. "UNDEFINED_NAME,Transmit data ready interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit last slot interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 3. "UNDEFINED_NAME,Transmit DMA error interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 2. "UNDEFINED_NAME,Transmit clock failure interrupt enable bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 1. "UNDEFINED_NAME,Unexpected transmit frame sync interrupt enable bit" "en_1_0x0,en_2_0x1"
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bitfld.long 0x1C 0. "UNDEFINED_NAME,Transmitter underrun interrupt enable bit" "en_1_0x0,en_2_0x1"
line.long 0x20 "XSTAT,The transmitter status register (XSTAT) provides the transmitter status and transmit TDM time slot number"
hexmask.long.tbyte 0x20 9.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x20 8. "UNDEFINED_NAME,XERR bit always returns a logic-OR of: XUNDRN OR XSYNCERR OR XCKFAIL OR XDMAERR" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 7. "UNDEFINED_NAME,Transmit DMA error flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 6. "UNDEFINED_NAME,Transmit start of frame flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 5. "UNDEFINED_NAME,Transmit data ready flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 4. "UNDEFINED_NAME,Transmit last slot flag" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 3. "UNDEFINED_NAME,Returns the LSB of XSLOT" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2. "UNDEFINED_NAME,Transmit clock failure flag" "en_1_0x0,en_2_0x1"
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bitfld.long 0x20 1. "UNDEFINED_NAME,Unexpected transmit frame sync flag" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 0. "UNDEFINED_NAME,Transmitter underrun flag" "en_1_0x0,en_2_0x1"
line.long 0x24 "XSLOT,The current transmit TDM time slot register (XSLOT) indicates the current time slot for the transmit data frame"
hexmask.long.tbyte 0x24 10.--31. 1. "UNDEFINED_NAME,"
hexmask.long.word 0x24 0.--9. 1. "UNDEFINED_NAME,Current transmit time slot count"
line.long 0x28 "XCLKCHK,The transmit clock check control register (XCLKCHK) configures the transmit clock failure detection circuit"
hexmask.long.byte 0x28 24.--31. 1. "UNDEFINED_NAME,Transmit clock count value [from previous measurement]"
hexmask.long.byte 0x28 16.--23. 1. "UNDEFINED_NAME,Transmit clock maximum boundary"
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hexmask.long.byte 0x28 8.--15. 1. "UNDEFINED_NAME,Transmit clock minimum boundary"
rbitfld.long 0x28 4.--7. "UNDEFINED_NAME," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 0.--3. "UNDEFINED_NAME,Transmit clock check prescaler value" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3,en_5_0x4,en_6_0x5,en_7_0x6,en_8_0x7,en_9_0x8,en_10_0x9,?,?,?,?,?,?"
line.long 0x2C "XEVTCTL,The transmitter DMA event control register (XEVTCTL) contains a disable bit for the transmit DMA event"
hexmask.long 0x2C 1.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x2C 0. "UNDEFINED_NAME,Transmit data DMA request enable bit" "en_1_0x0,en_2_0x1"
group.long 0x100++0x03
line.long 0x00 "DITCSRA0,The DIT left channel status registers (DITCSRA0) provide the status of each left channel (even TDM time slot)"
group.long 0x180++0x3F
line.long 0x00 "SRCTL0,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x00 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x00 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x00 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x00 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x00 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x04 "SRCTL1,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x04 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x04 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x04 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x04 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x04 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x08 "SRCTL2,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x08 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x08 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x08 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x08 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x08 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x0C "SRCTL3,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x0C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x0C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x0C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x0C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x0C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x10 "SRCTL4,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x10 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x10 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x10 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x10 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x10 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x14 "SRCTL5,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x14 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x14 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x14 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x14 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x14 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x18 "SRCTL6,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x18 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x18 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x18 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x18 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x18 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x1C "SRCTL7,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x1C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x1C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x1C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x1C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x1C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x20 "SRCTL8,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x20 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x20 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x20 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x20 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
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bitfld.long 0x20 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x24 "SRCTL9,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x24 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x24 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
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rbitfld.long 0x24 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x24 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x24 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x28 "SRCTL10,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x28 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x28 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x28 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x28 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x28 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x2C "SRCTL11,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x2C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x2C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x2C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x2C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x2C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x30 "SRCTL12,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x30 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x30 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x30 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x30 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x30 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x34 "SRCTL13,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x34 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x34 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x34 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x34 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x34 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x38 "SRCTL14,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x38 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x38 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x38 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x38 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x38 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
line.long 0x3C "SRCTL15,Each serializer on the McASP has a serializer control register (SRCTL0)"
hexmask.long 0x3C 6.--31. 1. "UNDEFINED_NAME,"
rbitfld.long 0x3C 5. "UNDEFINED_NAME,Receive buffer ready bit" "en_1_0x0,en_2_0x1"
newline
rbitfld.long 0x3C 4. "UNDEFINED_NAME,Transmit buffer ready bit" "en_1_0x0,en_2_0x1"
bitfld.long 0x3C 2.--3. "UNDEFINED_NAME,Serializer pin drive mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
newline
bitfld.long 0x3C 0.--1. "UNDEFINED_NAME,Serializer mode bit" "en_1_0x0,en_2_0x1,en_3_0x2,en_4_0x3"
group.long 0x1000++0x0F
line.long 0x00 "WFIFOCTL,The WNUMEVT and WNUMDMA values must be set prior to enabling the Write FIFO"
hexmask.long.word 0x00 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x00 16. "UNDEFINED_NAME,Write FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
hexmask.long.byte 0x00 8.--15. 1. "UNDEFINED_NAME,Write word count per DMA event [32 bit]"
hexmask.long.byte 0x00 0.--7. 1. "UNDEFINED_NAME,Write word count per transfer [32 bit words]"
line.long 0x04 "WFIFOSTS,"
hexmask.long.tbyte 0x04 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x04 0.--7. "UNDEFINED_NAME,Write level [read-only]" "0x40=3 to 64 words currently in Write FIFO from..,0xFF=Reserved from 41h to FFh"
line.long 0x08 "RFIFOCTL,The RNUMEVT and RNUMDMA values must be set prior to enabling the Read FIFO"
hexmask.long.word 0x08 17.--31. 1. "UNDEFINED_NAME,"
bitfld.long 0x08 16. "UNDEFINED_NAME,Read FIFO enable bit" "en_1_0x0,en_2_0x1"
newline
abitfld.long 0x08 8.--15. "UNDEFINED_NAME,Read word count per DMA event [32 bit]" "0x41=FFh,0xFF=.."
abitfld.long 0x08 0.--7. "UNDEFINED_NAME,Read word count per transfer [32 bit words]" "0x10=3 to 16 words from 3h to 10h,0xFF=Reserved from 11h to FFh"
line.long 0x0C "RFIFOSTS,"
hexmask.long.tbyte 0x0C 8.--31. 1. "UNDEFINED_NAME,"
abitfld.long 0x0C 0.--7. "UNDEFINED_NAME,Read level [read-only]" "0x40=3 to 64 words currently in Read FIFO from..,0xFF=Reserved from 41h to FFh"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x280)++0x03
line.long 0x00 "RBUF$1,The receive buffers for the serializers (RBUF0) hold data from the serializer before the data goes to the receive format unit"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x200)++0x03
line.long 0x00 "XBUF$1,The transmit buffers for the serializers (XBUF0) hold data from the transmit format unit"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x148)++0x03
line.long 0x00 "DITUDRB$1,The DIT right channel user data registers (DITUDRB0) provides the user data of each right channel (odd TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x130)++0x03
line.long 0x00 "DITUDRA$1,The DIT left channel user data registers (DITUDRA0) provides the user data of each left channel (even TDM time slot)"
repeat.end
repeat 6. (list 0. 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 )
group.long ($2+0x118)++0x03
line.long 0x00 "DITCSRB$1,The DIT right channel status registers (DITCSRB0) provide the status of each right channel (odd TDM time slot)"
repeat.end
repeat 5. (list 1. 2. 3. 4. 5. )(list 0x00 0x04 0x08 0x0C 0x10 )
group.long ($2+0x104)++0x03
line.long 0x00 "DITCSRA$1,The DIT left channel status registers (DITCSRA) provide the status of each left channel (even TDM time slot)"
repeat.end
width 0x0B
tree.end
tree "RCSS_PCR (RCSS PCR Module Registers)"
base ad:0x5F78000
group.long 0x00++0x07
line.long 0x00 "PMPROTSET0,Set-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 30. "PCS30_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 29. "PCS29_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 28. "PCS28_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 27. "PCS27_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 26. "PCS26_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 25. "PCS25_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 24. "PCS24_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 23. "PCS23_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 22. "PCS22_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 21. "PCS21_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 20. "PCS20_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 19. "PCS19_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 18. "PCS18_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 17. "PCS17_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 16. "PCS16_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 15. "PCS15_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 14. "PCS14_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 13. "PCS13_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 12. "PCS12_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 11. "PCS11_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 10. "PCS10_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 9. "PCS9_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 8. "PCS8_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 7. "PCS7_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 6. "PCS6_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 5. "PCS5_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 4. "PCS4_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 3. "PCS3_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 2. "PCS2_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 1. "PCS1_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
newline
bitfld.long 0x00 0. "PCS0_PROT_SET,Readable in user and privileged modes" "Has no effect Only those bits which have a slave..,Sets the corresponding bit in PMPROTSET0 and.."
line.long 0x04 "PMPROTSET1,Set-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x10++0x07
line.long 0x00 "PMPROTCLR0,Clear-only register to protect PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PMPROTCLR1,Clear-only register to protect PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PROT_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x20++0x0F
line.long 0x00 "PPROTSET_0,Set-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PPROTSET_1,Set-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PPROTSET_2,Set-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PPROTSET_3,Set-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x40++0x0F
line.long 0x00 "PPROTCLR0,Clear-only register to protect the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PPROTCLR1,Clear-only register to protect the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PPROTCLR2,Clear-only register to protect the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PPROTCLR3,Clear-only register to protect the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PROT_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x60++0x07
line.long 0x00 "PCSPWRDWNSET0,Set-only register to powerdown independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PCSPWRDWNSET1,Set-only register to powerdown independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_SET,Readable in user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0x70++0x07
line.long 0x00 "PCSPWRDWNCLR0,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 0 to 31"
bitfld.long 0x00 31. "PCS31_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PCS30_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PCS29_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PCS28_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PCS27_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PCS26_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PCS25_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PCS24_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PCS23_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PCS22_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PCS21_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PCS20_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PCS19_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PCS18_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PCS17_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PCS16_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PCS15_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PCS14_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PCS13_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PCS12_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PCS11_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PCS10_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PCS9_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PCS8_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PCS7_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PCS6_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PCS5_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PCS4_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PCS3_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PCS2_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PCS1_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PCS0_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PCSPWRDWNCLR1,Clear-only register to deassert powerdown bits of independent (non-shared) PCS frames 32 to 63"
bitfld.long 0x04 31. "PCS63_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PCS62_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PCS61_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PCS60_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PCS59_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PCS58_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PCS57_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PCS56_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PCS55_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PCS54_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PCS53_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PCS52_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PCS51_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PCS50_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PCS49_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PCS48_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PCS47_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PCS46_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PCS45_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PCS44_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PCS43_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PCS42_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PCS41_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PCS40_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PCS39_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PCS38_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PCS37_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PCS36_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PCS35_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PCS34_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PCS33_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PCS32_PWRDWN_CLR,Readable in user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0x80++0x0F
line.long 0x00 "PSPWRDWNSET0,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x04 "PSPWRDWNSET1,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x08 "PSPWRDWNSET2,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
line.long 0x0C "PSPWRDWNSET3,Set-only register to powerdown the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Sets the corresponding bit in.."
group.long 0xA0++0x0F
line.long 0x00 "PSPWRDWNCLR0,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS0 to PS7"
bitfld.long 0x00 31. "PS7_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 30. "PS7_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 29. "PS7_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 28. "PS7_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 27. "PS6_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 26. "PS6_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 25. "PS6_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 24. "PS6_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 23. "PS5_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 22. "PS5_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 21. "PS5_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 20. "PS5_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 19. "PS4_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 18. "PS4_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 17. "PS4_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 16. "PS4_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 15. "PS3_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 14. "PS3_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 13. "PS3_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 12. "PS3_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 11. "PS2_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 10. "PS2_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 9. "PS2_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 8. "PS2_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 7. "PS1_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 6. "PS1_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 5. "PS1_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 4. "PS1_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 3. "PS0_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 2. "PS0_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 1. "PS0_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x00 0. "PS0_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x04 "PSPWRDWNCLR1,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS8 to PS15"
bitfld.long 0x04 31. "PS15_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 30. "PS15_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 29. "PS15_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 28. "PS15_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 27. "PS14_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 26. "PS14_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 25. "PS14_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 24. "PS14_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 23. "PS13_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 22. "PS13_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 21. "PS13_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 20. "PS13_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 19. "PS12_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 18. "PS12_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 17. "PS12_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 16. "PS12_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 15. "PS11_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 14. "PS11_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 13. "PS11_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 12. "PS11_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 11. "PS10_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 10. "PS10_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 9. "PS10_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 8. "PS10_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 7. "PS9_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 6. "PS9_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 5. "PS9_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 4. "PS9_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 3. "PS8_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 2. "PS8_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 1. "PS8_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x04 0. "PS8_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x08 "PSPWRDWNCLR2,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS16 to PS23"
bitfld.long 0x08 31. "PS23_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 30. "PS23_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 29. "PS23_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 28. "PS23_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 27. "PS22_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 26. "PS22_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 25. "PS22_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 24. "PS22_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 23. "PS21_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 22. "PS21_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 21. "PS21_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 20. "PS21_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 19. "PS20_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 18. "PS20_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 17. "PS20_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 16. "PS20_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 15. "PS19_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 14. "PS19_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 13. "PS19_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 12. "PS19_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 11. "PS18_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 10. "PS18_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 9. "PS18_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 8. "PS18_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 7. "PS17_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 6. "PS17_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 5. "PS17_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 4. "PS17_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 3. "PS16_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 2. "PS16_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 1. "PS16_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x08 0. "PS16_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
line.long 0x0C "PSPWRDWNCLR3,Clear-only register to deassert powerdown bits of the applicable peripherals in the 32 quadrants of PS24 to PS31"
bitfld.long 0x0C 31. "PS31_QUAD3_PWRDWN_CLR," "0,1"
newline
bitfld.long 0x0C 30. "PS31_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 29. "PS31_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 28. "PS31_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 27. "PS30_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 26. "PS30_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 25. "PS30_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 24. "PS30_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 23. "PS29_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 22. "PS29_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 21. "PS29_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 20. "PS29_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 19. "PS28_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 18. "PS28_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 17. "PS28_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 16. "PS28_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 15. "PS27_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 14. "PS27_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 13. "PS27_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 12. "PS27_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 11. "PS26_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 10. "PS26_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 9. "PS26_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 8. "PS26_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 7. "PS25_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 6. "PS25_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 5. "PS25_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 4. "PS25_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 3. "PS24_QUAD3_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 2. "PS24_QUAD2_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 1. "PS24_QUAD1_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
newline
bitfld.long 0x0C 0. "PS24_QUAD0_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Clears the corresponding bit in.."
group.long 0xC0++0x07
line.long 0x00 "PDPWRDWNSET,Set-only register to powerdown the debug frame"
hexmask.long 0x00 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0. "PD_PWRDWN_SET,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get set in.."
line.long 0x04 "PDPWRDWNCLR,Clear-only register to deassert the debug frame's powerdown bit"
hexmask.long 0x04 1.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0. "PD_PWRDWN_CLR,Readable in both user and privileged modes" "Has no effect,Bit 0 when written 1 will get cleared.."
group.long 0x200++0x0B
line.long 0x00 "MSTIDWRENA,MasterID Protection Write Enable Register"
hexmask.long 0x00 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x00 0.--3. "MSTIDREG_WRENA,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "MSTIDENA,MasterID Protection Enable Register"
hexmask.long 0x04 4.--31. 1. "Reserved,Reserved"
newline
bitfld.long 0x04 0.--3. "MSTID_CHK_EN,Readable in both user and privileged modes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x08 "MSTIDDIAGCTRL,MasterID Diagnostic Control Register"
hexmask.long.tbyte 0x08 12.--31. 1. "Reserved2,Reserved"
newline
bitfld.long 0x08 8.--11. "DIAG_CMP_VALUE,MasterID diagnostic mode control register bits; 4-bit data which is compared with the master-id register of all defined frames during diagnostic mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
rbitfld.long 0x08 4.--7. "Reserved1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x08 0.--3. "DIAG_MODE_EN,MasterID compare logic diagnostic mode enable bits; 4-bit key for enabling the master-id registers compare logic" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x300++0x2E3
line.long 0x00 "PS0MSTID_L,Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x00 16.--31. "PS0_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x00 0.--15. "PS0_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x04 "PS0MSTID_H,Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x04 16.--31. "PS0_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x04 0.--15. "PS0_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x08 "PS1MSTID_L,Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x08 16.--31. "PS1_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x08 0.--15. "PS1_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x0C "PS1MSTID_H,Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x0C 16.--31. "PS1_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x0C 0.--15. "PS1_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10 "PS2MSTID_L,Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x10 16.--31. "PS2_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10 0.--15. "PS2_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14 "PS2MSTID_H,Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x14 16.--31. "PS2_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14 0.--15. "PS2_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18 "PS3MSTID_L,Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x18 16.--31. "PS3_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18 0.--15. "PS3_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C "PS3MSTID_H,Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x1C 16.--31. "PS3_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C 0.--15. "PS3_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20 "PS4MSTID_L,Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x20 16.--31. "PS4_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20 0.--15. "PS4_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24 "PS4MSTID_H,Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x24 16.--31. "PS4_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24 0.--15. "PS4_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28 "PS5MSTID_L,Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x28 16.--31. "PS5_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28 0.--15. "PS5_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C "PS5MSTID_H,Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x2C 16.--31. "PS5_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C 0.--15. "PS5_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x30 "PS6MSTID_L,Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x30 16.--31. "PS6_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x30 0.--15. "PS6_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x34 "PS6MSTID_H,Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x34 16.--31. "PS6_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x34 0.--15. "PS6_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x38 "PS7MSTID_L,Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x38 16.--31. "PS7_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x38 0.--15. "PS7_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x3C "PS7MSTID_H,Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x3C 16.--31. "PS7_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x3C 0.--15. "PS7_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x40 "PS8MSTID_L,Peripheral Frame Master-ID Protection Register8_L"
abitfld.long 0x40 16.--31. "PS8_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x40 0.--15. "PS8_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x44 "PS8MSTID_H,Peripheral Frame Master-ID Protection Register8_H"
abitfld.long 0x44 16.--31. "PS8_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x44 0.--15. "PS8_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x48 "PS9MSTID_L,Peripheral Frame Master-ID Protection Register9_L"
abitfld.long 0x48 16.--31. "PS9_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x48 0.--15. "PS9_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x4C "PS9MSTID_H,Peripheral Frame Master-ID Protection Register9_H"
abitfld.long 0x4C 16.--31. "PS9_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x4C 0.--15. "PS9_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x50 "PS10MSTID_L,Peripheral Frame Master-ID Protection Register10_L"
abitfld.long 0x50 16.--31. "PS10_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x50 0.--15. "PS10_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x54 "PS10MSTID_H,Peripheral Frame Master-ID Protection Register10_H"
abitfld.long 0x54 16.--31. "PS10_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x54 0.--15. "PS10_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x58 "PS11MSTID_L,Peripheral Frame Master-ID Protection Register11_L"
abitfld.long 0x58 16.--31. "PS11_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x58 0.--15. "PS11_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x5C "PS11MSTID_H,Peripheral Frame Master-ID Protection Register11_H"
abitfld.long 0x5C 16.--31. "PS11_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x5C 0.--15. "PS11_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x60 "PS12MSTID_L,Peripheral Frame Master-ID Protection Register12_L"
abitfld.long 0x60 16.--31. "PS12_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x60 0.--15. "PS12_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x64 "PS12MSTID_H,Peripheral Frame Master-ID Protection Register12_H"
abitfld.long 0x64 16.--31. "PS12_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x64 0.--15. "PS12_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x68 "PS13MSTID_L,Peripheral Frame Master-ID Protection Register13_L"
abitfld.long 0x68 16.--31. "PS13_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x68 0.--15. "PS13_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x6C "PS13MSTID_H,Peripheral Frame Master-ID Protection Register13_H"
abitfld.long 0x6C 16.--31. "PS13_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x6C 0.--15. "PS13_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x70 "PS14MSTID_L,Peripheral Frame Master-ID Protection Register14_L"
abitfld.long 0x70 16.--31. "PS14_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x70 0.--15. "PS14_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x74 "PS14MSTID_H,Peripheral Frame Master-ID Protection Register14_H"
abitfld.long 0x74 16.--31. "PS14_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x74 0.--15. "PS14_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x78 "PS15MSTID_L,Peripheral Frame Master-ID Protection Register15_L"
abitfld.long 0x78 16.--31. "PS15_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x78 0.--15. "PS15_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x7C "PS15MSTID_H,Peripheral Frame Master-ID Protection Register15_H"
abitfld.long 0x7C 16.--31. "PS15_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x7C 0.--15. "PS15_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x80 "PS16MSTID_L,Peripheral Frame Master-ID Protection Register16_L"
abitfld.long 0x80 16.--31. "PS16_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x80 0.--15. "PS16_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x84 "PS16MSTID_H,Peripheral Frame Master-ID Protection Register16_H"
abitfld.long 0x84 16.--31. "PS16_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x84 0.--15. "PS16_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x88 "PS17MSTID_L,Peripheral Frame Master-ID Protection Register17_L"
abitfld.long 0x88 16.--31. "PS17_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x88 0.--15. "PS17_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x8C "PS17MSTID_H,Peripheral Frame Master-ID Protection Register17_H"
abitfld.long 0x8C 16.--31. "PS17_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x8C 0.--15. "PS17_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x90 "PS18MSTID_L,Peripheral Frame Master-ID Protection Register18_L"
abitfld.long 0x90 16.--31. "PS18_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x90 0.--15. "PS18_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x94 "PS18MSTID_H,Peripheral Frame Master-ID Protection Register18_H"
abitfld.long 0x94 16.--31. "PS18_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x94 0.--15. "PS18_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x98 "PS19MSTID_L,Peripheral Frame Master-ID Protection Register19_L"
abitfld.long 0x98 16.--31. "PS19_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x98 0.--15. "PS19_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x9C "PS19MSTID_H,Peripheral Frame Master-ID Protection Register19_H"
abitfld.long 0x9C 16.--31. "PS19_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x9C 0.--15. "PS19_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA0 "PS20MSTID_L,Peripheral Frame Master-ID Protection Register20_L"
abitfld.long 0xA0 16.--31. "PS20_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA0 0.--15. "PS20_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA4 "PS20MSTID_H,Peripheral Frame Master-ID Protection Register20_H"
abitfld.long 0xA4 16.--31. "PS20_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA4 0.--15. "PS20_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xA8 "PS21MSTID_L,Peripheral Frame Master-ID Protection Register21_L"
abitfld.long 0xA8 16.--31. "PS21_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xA8 0.--15. "PS21_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xAC "PS21MSTID_H,Peripheral Frame Master-ID Protection Register21_H"
abitfld.long 0xAC 16.--31. "PS21_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xAC 0.--15. "PS21_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB0 "PS22MSTID_L,Peripheral Frame Master-ID Protection Register22_L"
abitfld.long 0xB0 16.--31. "PS22_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB0 0.--15. "PS22_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB4 "PS22MSTID_H,Peripheral Frame Master-ID Protection Register22_H"
abitfld.long 0xB4 16.--31. "PS22_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB4 0.--15. "PS22_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xB8 "PS23MSTID_L,Peripheral Frame Master-ID Protection Register23_L"
abitfld.long 0xB8 16.--31. "PS23_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xB8 0.--15. "PS23_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xBC "PS23MSTID_H,Peripheral Frame Master-ID Protection Register23_H"
abitfld.long 0xBC 16.--31. "PS23_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xBC 0.--15. "PS23_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC0 "PS24MSTID_L,Peripheral Frame Master-ID Protection Register24_L"
abitfld.long 0xC0 16.--31. "PS24_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC0 0.--15. "PS24_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC4 "PS24MSTID_H,Peripheral Frame Master-ID Protection Register24_H"
abitfld.long 0xC4 16.--31. "PS24_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC4 0.--15. "PS24_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xC8 "PS25MSTID_L,Peripheral Frame Master-ID Protection Register25_L"
abitfld.long 0xC8 16.--31. "PS25_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xC8 0.--15. "PS25_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xCC "PS25MSTID_H,Peripheral Frame Master-ID Protection Register25_H"
abitfld.long 0xCC 16.--31. "PS25_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xCC 0.--15. "PS25_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD0 "PS26MSTID_L,Peripheral Frame Master-ID Protection Register26_L"
abitfld.long 0xD0 16.--31. "PS26_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD0 0.--15. "PS26_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD4 "PS26MSTID_H,Peripheral Frame Master-ID Protection Register26_H"
abitfld.long 0xD4 16.--31. "PS26_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD4 0.--15. "PS26_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xD8 "PS27MSTID_L,Peripheral Frame Master-ID Protection Register27_L"
abitfld.long 0xD8 16.--31. "PS27_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xD8 0.--15. "PS27_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xDC "PS27MSTID_H,Peripheral Frame Master-ID Protection Register27_H"
abitfld.long 0xDC 16.--31. "PS27_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xDC 0.--15. "PS27_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE0 "PS28MSTID_L,Peripheral Frame Master-ID Protection Register28_L"
abitfld.long 0xE0 16.--31. "PS28_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE0 0.--15. "PS28_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE4 "PS28MSTID_H,Peripheral Frame Master-ID Protection Register28_H"
abitfld.long 0xE4 16.--31. "PS28_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE4 0.--15. "PS28_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xE8 "PS29MSTID_L,Peripheral Frame Master-ID Protection Register29_L"
abitfld.long 0xE8 16.--31. "PS29_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xE8 0.--15. "PS29_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xEC "PS29MSTID_H,Peripheral Frame Master-ID Protection Register29_H"
abitfld.long 0xEC 16.--31. "PS29_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xEC 0.--15. "PS29_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF0 "PS30MSTID_L,Peripheral Frame Master-ID Protection Register30_L"
abitfld.long 0xF0 16.--31. "PS30_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF0 0.--15. "PS30_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF4 "PS30MSTID_H,Peripheral Frame Master-ID Protection Register30_H"
abitfld.long 0xF4 16.--31. "PS30_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF4 0.--15. "PS30_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xF8 "PS31MSTID_L,Peripheral Frame Master-ID Protection Register31_L"
abitfld.long 0xF8 16.--31. "PS31_QUAD1_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xF8 0.--15. "PS31_QUAD0_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0xFC "PS31MSTID_H,Peripheral Frame Master-ID Protection Register31_H"
abitfld.long 0xFC 16.--31. "PS31_QUAD3_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0xFC 0.--15. "PS31_QUAD2_MSTID,There are 16 bits for each quadrant in PS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x100 "PPS0MSTID_L,Privileged Peripheral Frame Master-ID Protection Register0_L"
abitfld.long 0x100 16.--31. "PPS0_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x100 0.--15. "PPS0_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x104 "PPS0MSTID_H,Privileged Peripheral Frame Master-ID Protection Register0_H"
abitfld.long 0x104 16.--31. "PPS0_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x104 0.--15. "PPS0_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x108 "PPS1MSTID_L,Privileged Peripheral Frame Master-ID Protection Register1_L"
abitfld.long 0x108 16.--31. "PPS1_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x108 0.--15. "PPS1_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x10C "PPS1MSTID_H,Privileged Peripheral Frame Master-ID Protection Register1_H"
abitfld.long 0x10C 16.--31. "PPS1_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x10C 0.--15. "PPS1_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x110 "PPS2MSTID_L,Privileged Peripheral Frame Master-ID Protection Register2_L"
abitfld.long 0x110 16.--31. "PPS2_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x110 0.--15. "PPS2_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x114 "PPS2MSTID_H,Privileged Peripheral Frame Master-ID Protection Register2_H"
abitfld.long 0x114 16.--31. "PPS2_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x114 0.--15. "PPS2_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x118 "PPS3MSTID_L,Privileged Peripheral Frame Master-ID Protection Register3_L"
abitfld.long 0x118 16.--31. "PPS3_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x118 0.--15. "PPS3_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x11C "PPS3MSTID_H,Privileged Peripheral Frame Master-ID Protection Register3_H"
abitfld.long 0x11C 16.--31. "PPS3_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x11C 0.--15. "PPS3_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x120 "PPS4MSTID_L,Privileged Peripheral Frame Master-ID Protection Register4_L"
abitfld.long 0x120 16.--31. "PPS4_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x120 0.--15. "PPS4_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x124 "PPS4MSTID_H,Privileged Peripheral Frame Master-ID Protection Register4_H"
abitfld.long 0x124 16.--31. "PPS4_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x124 0.--15. "PPS4_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x128 "PPS5MSTID_L,Privileged Peripheral Frame Master-ID Protection Register5_L"
abitfld.long 0x128 16.--31. "PPS5_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x128 0.--15. "PPS5_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x12C "PPS5MSTID_H,Privileged Peripheral Frame Master-ID Protection Register5_H"
abitfld.long 0x12C 16.--31. "PPS5_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x12C 0.--15. "PPS5_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x130 "PPS6MSTID_L,Privileged Peripheral Frame Master-ID Protection Register6_L"
abitfld.long 0x130 16.--31. "PPS6_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x130 0.--15. "PPS6_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x134 "PPS6MSTID_H,Privileged Peripheral Frame Master-ID Protection Register6_H"
abitfld.long 0x134 16.--31. "PPS6_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x134 0.--15. "PPS6_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x138 "PPS7MSTID_L,Privileged Peripheral Frame Master-ID Protection Register7_L"
abitfld.long 0x138 16.--31. "PPS7_QUAD1_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x138 0.--15. "PPS7_QUAD0_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x13C "PPS7MSTID_H,Privileged Peripheral Frame Master-ID Protection Register7_H"
abitfld.long 0x13C 16.--31. "PPS7_QUAD3_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x13C 0.--15. "PPS7_QUAD2_MSTID,There are 16 bits for each quadrant in PPS frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x140 "PPSE0MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register0_L"
abitfld.long 0x140 16.--31. "PPSE0_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x140 0.--15. "PPSE0_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x144 "PPSE0MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register0_H"
abitfld.long 0x144 16.--31. "PPSE0_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x144 0.--15. "PPSE0_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x148 "PPSE1MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register1_L"
abitfld.long 0x148 16.--31. "PPSE1_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x148 0.--15. "PPSE1_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x14C "PPSE1MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register1_H"
abitfld.long 0x14C 16.--31. "PPSE1_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x14C 0.--15. "PPSE1_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x150 "PPSE2MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register2_L"
abitfld.long 0x150 16.--31. "PPSE2_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x150 0.--15. "PPSE2_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x154 "PPSE2MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register2_H"
abitfld.long 0x154 16.--31. "PPSE2_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x154 0.--15. "PPSE2_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x158 "PPSE3MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register3_L"
abitfld.long 0x158 16.--31. "PPSE3_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x158 0.--15. "PPSE3_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x15C "PPSE3MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register3_H"
abitfld.long 0x15C 16.--31. "PPSE3_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x15C 0.--15. "PPSE3_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x160 "PPSE4MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register4_L"
abitfld.long 0x160 16.--31. "PPSE4_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x160 0.--15. "PPSE4_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x164 "PPSE4MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register4_H"
abitfld.long 0x164 16.--31. "PPSE4_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x164 0.--15. "PPSE4_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x168 "PPSE5MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register5_L"
abitfld.long 0x168 16.--31. "PPSE5_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x168 0.--15. "PPSE5_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x16C "PPSE5MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register5_H"
abitfld.long 0x16C 16.--31. "PPSE5_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x16C 0.--15. "PPSE5_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x170 "PPSE6MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register6_L"
abitfld.long 0x170 16.--31. "PPSE6_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x170 0.--15. "PPSE6_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x174 "PPSE6MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register6_H"
abitfld.long 0x174 16.--31. "PPSE6_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x174 0.--15. "PPSE6_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x178 "PPSE7MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register7_L"
abitfld.long 0x178 16.--31. "PPSE7_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x178 0.--15. "PPSE7_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x17C "PPSE7MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register7_H"
abitfld.long 0x17C 16.--31. "PPSE7_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x17C 0.--15. "PPSE7_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x180 "PPSE8MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register8_L"
abitfld.long 0x180 16.--31. "PPSE8_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x180 0.--15. "PPSE8_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x184 "PPSE8MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register8_H"
abitfld.long 0x184 16.--31. "PPSE8_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x184 0.--15. "PPSE8_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x188 "PPSE9MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register9_L"
abitfld.long 0x188 16.--31. "PPSE9_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x188 0.--15. "PPSE9_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x18C "PPSE9MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register9_H"
abitfld.long 0x18C 16.--31. "PPSE9_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x18C 0.--15. "PPSE9_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x190 "PPSE10MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register10_L"
abitfld.long 0x190 16.--31. "PPSE10_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x190 0.--15. "PPSE10_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x194 "PPSE10MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register10_H"
abitfld.long 0x194 16.--31. "PPSE10_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x194 0.--15. "PPSE10_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x198 "PPSE11MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register11_L"
abitfld.long 0x198 16.--31. "PPSE11_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x198 0.--15. "PPSE11_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x19C "PPSE11MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register11_H"
abitfld.long 0x19C 16.--31. "PPSE11_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x19C 0.--15. "PPSE11_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A0 "PPSE12MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register12_L"
abitfld.long 0x1A0 16.--31. "PPSE12_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A0 0.--15. "PPSE12_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A4 "PPSE12MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register12_H"
abitfld.long 0x1A4 16.--31. "PPSE12_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A4 0.--15. "PPSE12_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1A8 "PPSE13MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register13_L"
abitfld.long 0x1A8 16.--31. "PPSE13_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1A8 0.--15. "PPSE13_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1AC "PPSE13MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register13_H"
abitfld.long 0x1AC 16.--31. "PPSE13_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1AC 0.--15. "PPSE13_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B0 "PPSE14MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register14_L"
abitfld.long 0x1B0 16.--31. "PPSE14_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B0 0.--15. "PPSE14_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B4 "PPSE14MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register14_H"
abitfld.long 0x1B4 16.--31. "PPSE14_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B4 0.--15. "PPSE14_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1B8 "PPSE15MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register15_L"
abitfld.long 0x1B8 16.--31. "PPSE15_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1B8 0.--15. "PPSE15_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1BC "PPSE15MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register15_H"
abitfld.long 0x1BC 16.--31. "PPSE15_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1BC 0.--15. "PPSE15_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C0 "PPSE16MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register16_L"
abitfld.long 0x1C0 16.--31. "PPSE16_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C0 0.--15. "PPSE16_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C4 "PPSE16MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register16_H"
abitfld.long 0x1C4 16.--31. "PPSE16_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C4 0.--15. "PPSE16_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1C8 "PPSE17MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register17_L"
abitfld.long 0x1C8 16.--31. "PPSE17_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1C8 0.--15. "PPSE17_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1CC "PPSE17MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register17_H"
abitfld.long 0x1CC 16.--31. "PPSE17_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1CC 0.--15. "PPSE17_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D0 "PPSE18MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register18_L"
abitfld.long 0x1D0 16.--31. "PPSE18_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D0 0.--15. "PPSE18_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D4 "PPSE18MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register18_H"
abitfld.long 0x1D4 16.--31. "PPSE18_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D4 0.--15. "PPSE18_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1D8 "PPSE19MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register19_L"
abitfld.long 0x1D8 16.--31. "PPSE19_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1D8 0.--15. "PPSE19_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1DC "PPSE19MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register19_H"
abitfld.long 0x1DC 16.--31. "PPSE19_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1DC 0.--15. "PPSE19_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E0 "PPSE20MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register20_L"
abitfld.long 0x1E0 16.--31. "PPSE20_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E0 0.--15. "PPSE20_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E4 "PPSE20MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register20_H"
abitfld.long 0x1E4 16.--31. "PPSE20_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E4 0.--15. "PPSE20_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1E8 "PPSE21MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register21_L"
abitfld.long 0x1E8 16.--31. "PPSE21_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1E8 0.--15. "PPSE21_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1EC "PPSE21MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register21_H"
abitfld.long 0x1EC 16.--31. "PPSE21_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1EC 0.--15. "PPSE21_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F0 "PPSE22MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register22_L"
abitfld.long 0x1F0 16.--31. "PPSE22_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F0 0.--15. "PPSE22_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F4 "PPSE22MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register22_H"
abitfld.long 0x1F4 16.--31. "PPSE22_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F4 0.--15. "PPSE22_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1F8 "PPSE23MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register23_L"
abitfld.long 0x1F8 16.--31. "PPSE23_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1F8 0.--15. "PPSE23_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x1FC "PPSE23MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register23_H"
abitfld.long 0x1FC 16.--31. "PPSE23_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x1FC 0.--15. "PPSE23_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x200 "PPSE24MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register24_L"
abitfld.long 0x200 16.--31. "PPSE24_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x200 0.--15. "PPSE24_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x204 "PPSE24MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register24_H"
abitfld.long 0x204 16.--31. "PPSE24_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x204 0.--15. "PPSE24_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x208 "PPSE25MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register25_L"
abitfld.long 0x208 16.--31. "PPSE25_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x208 0.--15. "PPSE25_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x20C "PPSE25MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register25_H"
abitfld.long 0x20C 16.--31. "PPSE25_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x20C 0.--15. "PPSE25_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x210 "PPSE26MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register26_L"
abitfld.long 0x210 16.--31. "PPSE26_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x210 0.--15. "PPSE26_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x214 "PPSE26MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register26_H"
abitfld.long 0x214 16.--31. "PPSE26_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x214 0.--15. "PPSE26_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x218 "PPSE27MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register27_L"
abitfld.long 0x218 16.--31. "PPSE27_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x218 0.--15. "PPSE27_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x21C "PPSE27MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register27_H"
abitfld.long 0x21C 16.--31. "PPSE27_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x21C 0.--15. "PPSE27_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x220 "PPSE28MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register28_L"
abitfld.long 0x220 16.--31. "PPSE28_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x220 0.--15. "PPSE28_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x224 "PPSE28MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register28_H"
abitfld.long 0x224 16.--31. "PPSE28_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x224 0.--15. "PPSE28_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x228 "PPSE29MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register29_L"
abitfld.long 0x228 16.--31. "PPSE29_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x228 0.--15. "PPSE29_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x22C "PPSE29MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register29_H"
abitfld.long 0x22C 16.--31. "PPSE29_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x22C 0.--15. "PPSE29_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x230 "PPSE30MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register30_L"
abitfld.long 0x230 16.--31. "PPSE30_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x230 0.--15. "PPSE30_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x234 "PPSE30MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register30_H"
abitfld.long 0x234 16.--31. "PPSE30_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x234 0.--15. "PPSE30_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x238 "PPSE31MSTID_L,Privileged Peripheral Extended Frame Master-ID Protection Register31_L"
abitfld.long 0x238 16.--31. "PPSE31_QUAD1_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x238 0.--15. "PPSE31_QUAD0_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x23C "PPSE31MSTID_H,Privileged Peripheral Extended Frame Master-ID Protection Register31_H"
abitfld.long 0x23C 16.--31. "PPSE31_QUAD3_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x23C 0.--15. "PPSE31_QUAD2_MSTID,There are 16 bits for each quadrant in PPSE frame" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x240 "PCS0MSTID,Memory Frame Master ID Protection Register0"
abitfld.long 0x240 16.--31. "PCS1MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x240 0.--15. "PCS0MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x244 "PCS1MSTID,Memory Frame Master ID Protection Register1"
abitfld.long 0x244 16.--31. "PCS3MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x244 0.--15. "PCS2MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x248 "PCS2MSTID,Memory Frame Master ID Protection Register2"
abitfld.long 0x248 16.--31. "PCS5MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x248 0.--15. "PCS4MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x24C "PCS3MSTID,Memory Frame Master ID Protection Register3"
abitfld.long 0x24C 16.--31. "PCS7MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x24C 0.--15. "PCS6MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x250 "PCS4MSTID,Memory Frame Master ID Protection Register4"
abitfld.long 0x250 16.--31. "PCS9MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x250 0.--15. "PCS8MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x254 "PCS5MSTID,Memory Frame Master ID Protection Register5"
abitfld.long 0x254 16.--31. "PCS11MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x254 0.--15. "PCS10MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x258 "PCS6MSTID,Memory Frame Master ID Protection Register6"
abitfld.long 0x258 16.--31. "PCS13MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x258 0.--15. "PCS12MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x25C "PCS7MSTID,Memory Frame Master ID Protection Register7"
abitfld.long 0x25C 16.--31. "PCS15MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x25C 0.--15. "PCS14MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x260 "PCS8MSTID,Memory Frame Master ID Protection Register8"
abitfld.long 0x260 16.--31. "PCS17MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x260 0.--15. "PCS16MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x264 "PCS9MSTID,Memory Frame Master ID Protection Register9"
abitfld.long 0x264 16.--31. "PCS19MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x264 0.--15. "PCS18MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x268 "PCS10MSTID,Memory Frame Master ID Protection Register10"
abitfld.long 0x268 16.--31. "PCS21MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x268 0.--15. "PCS20MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x26C "PCS11MSTID,Memory Frame Master ID Protection Register11"
abitfld.long 0x26C 16.--31. "PCS23MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x26C 0.--15. "PCS22MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x270 "PCS12MSTID,Memory Frame Master ID Protection Register12"
abitfld.long 0x270 16.--31. "PCS25MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x270 0.--15. "PCS24MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x274 "PCS13MSTID,Memory Frame Master ID Protection Register13"
abitfld.long 0x274 16.--31. "PCS27MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x274 0.--15. "PCS26MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x278 "PCS14MSTID,Memory Frame Master ID Protection Register14"
abitfld.long 0x278 16.--31. "PCS29MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x278 0.--15. "PCS28MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x27C "PCS15MSTID,Memory Frame Master ID Protection Register15"
abitfld.long 0x27C 16.--31. "PCS31MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x27C 0.--15. "PCS30MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x280 "PCS16MSTID,Memory Frame Master ID Protection Register16"
abitfld.long 0x280 16.--31. "PCS33MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x280 0.--15. "PCS32MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x284 "PCS17MSTID,Memory Frame Master ID Protection Register17"
abitfld.long 0x284 16.--31. "PCS35MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x284 0.--15. "PCS34MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x288 "PCS18MSTID,Memory Frame Master ID Protection Register18"
abitfld.long 0x288 16.--31. "PCS37MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x288 0.--15. "PCS36MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x28C "PCS19MSTID,Memory Frame Master ID Protection Register19"
abitfld.long 0x28C 16.--31. "PCS39MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x28C 0.--15. "PCS38MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x290 "PCS20MSTID,Memory Frame Master ID Protection Register20"
abitfld.long 0x290 16.--31. "PCS41MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x290 0.--15. "PCS40MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x294 "PCS21MSTID,Memory Frame Master ID Protection Register21"
abitfld.long 0x294 16.--31. "PCS43MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x294 0.--15. "PCS42MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x298 "PCS22MSTID,Memory Frame Master ID Protection Register22"
abitfld.long 0x298 16.--31. "PCS45MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x298 0.--15. "PCS44MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x29C "PCS23MSTID,Memory Frame Master ID Protection Register23"
abitfld.long 0x29C 16.--31. "PCS47MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x29C 0.--15. "PCS46MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A0 "PCS24MSTID,Memory Frame Master ID Protection Register24"
abitfld.long 0x2A0 16.--31. "PCS49MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A0 0.--15. "PCS48MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A4 "PCS25MSTID,Memory Frame Master ID Protection Register25"
abitfld.long 0x2A4 16.--31. "PCS51MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A4 0.--15. "PCS50MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2A8 "PCS26MSTID,Memory Frame Master ID Protection Register26"
abitfld.long 0x2A8 16.--31. "PCS53MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2A8 0.--15. "PCS52MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2AC "PCS27MSTID,Memory Frame Master ID Protection Register27"
abitfld.long 0x2AC 16.--31. "PCS55MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2AC 0.--15. "PCS54MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B0 "PCS28MSTID,Memory Frame Master ID Protection Register28"
abitfld.long 0x2B0 16.--31. "PCS57MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B0 0.--15. "PCS56MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B4 "PCS29MSTID,Memory Frame Master ID Protection Register29"
abitfld.long 0x2B4 16.--31. "PCS59MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B4 0.--15. "PCS58MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2B8 "PCS30MSTID,Memory Frame Master ID Protection Register30"
abitfld.long 0x2B8 16.--31. "PCS61MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2B8 0.--15. "PCS60MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2BC "PCS31MSTID,Memory Frame Master ID Protection Register31"
abitfld.long 0x2BC 16.--31. "PCS63MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2BC 0.--15. "PCS62MSTID,There are 16 bits for each frame in PCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C0 "PPCS0MSTID,Memory Frame Master ID Protection Register32"
abitfld.long 0x2C0 16.--31. "PPCS1MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C0 0.--15. "PPCS0MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C4 "PPCS1MSTID,Memory Frame Master ID Protection Register33"
abitfld.long 0x2C4 16.--31. "PPCS3MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C4 0.--15. "PPCS2MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2C8 "PPCS2MSTID,Memory Frame Master ID Protection Register34"
abitfld.long 0x2C8 16.--31. "PPCS5MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2C8 0.--15. "PPCS4MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2CC "PPCS3MSTID,Memory Frame Master ID Protection Register35"
abitfld.long 0x2CC 16.--31. "PPCS7MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2CC 0.--15. "PPCS6MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D0 "PPCS4MSTID,Memory Frame Master ID Protection Register36"
abitfld.long 0x2D0 16.--31. "PPCS9MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D0 0.--15. "PPCS8MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D4 "PPCS5MSTID,Memory Frame Master ID Protection Register37"
abitfld.long 0x2D4 16.--31. "PPCS11MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D4 0.--15. "PPCS10MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2D8 "PPCS6MSTID,Memory Frame Master ID Protection Register38"
abitfld.long 0x2D8 16.--31. "PPCS13MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2D8 0.--15. "PPCS12MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2DC "PPCS7MSTID,Memory Frame Master ID Protection Register39"
abitfld.long 0x2DC 16.--31. "PPCS15MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
newline
abitfld.long 0x2DC 0.--15. "PPCS14MSTID,There are 16 bits for each frame in PPCS" "0x0000=Clears the corresponding bit,0x0001=Sets the corresponding bit"
line.long 0x2E0 "PCREXTMSTID,Master-ID Protection Register for external PCR"
width 0x0B
tree.end
tree "RCSS_RCM (RCSS RCM Module Registers)"
base ad:0x5000000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x0C++0x03
line.long 0x00 "PREVIOUS_NAME,"
group.long 0x14++0x12F
line.long 0x00 "RCSS_I2CA_CLK_SRC_SEL,"
hexmask.long.word 0x00 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS_I2CA"
line.long 0x04 "RCSS_I2CB_CLK_SRC_SEL,"
hexmask.long.word 0x04 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS I2CB"
line.long 0x08 "RCSS_SCIA_CLK_SRC_SEL,"
hexmask.long.word 0x08 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS SCIA"
line.long 0x0C "RCSS_SPIA_CLK_SRC_SEL,"
hexmask.long.word 0x0C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS_SPIA"
line.long 0x10 "RCSS_SPIB_CLK_SRC_SEL,"
hexmask.long.word 0x10 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS SPIB"
line.long 0x14 "RCSS_ATL_CLK_SRC_SEL,"
hexmask.long.word 0x14 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS ATL CLK Data should be loaded as multibit"
line.long 0x18 "RCSS_MCASPA_REF0_CLK_SRC_SEL,"
hexmask.long.word 0x18 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPA REF0 CLK Data should be loaded as multibit"
line.long 0x1C "RCSS_MCASPA_REF1_CLK_SRC_SEL,"
hexmask.long.word 0x1C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPA REF1 CLK"
line.long 0x20 "RCSS_MCASPA_AUX_CLK_SRC_SEL,"
hexmask.long.word 0x20 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPA AUX CLK Data should be loaded as multibit"
line.long 0x24 "RCSS_MCASPB_REF0_CLK_SRC_SEL,"
hexmask.long.word 0x24 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPB REF0 CLK Data should be loaded as multibit"
line.long 0x28 "RCSS_MCASPB_REF1_CLK_SRC_SEL,"
hexmask.long.word 0x28 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPB REF1 CLK"
line.long 0x2C "RCSS_MCASPB_AUX_CLK_SRC_SEL,"
hexmask.long.word 0x2C 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPB AUX CLK Data should be loaded as multibit"
line.long 0x30 "RCSS_MCASPC_REF0_CLK_SRC_SEL,"
hexmask.long.word 0x30 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPC REF0 CLK Data should be loaded as multibit"
line.long 0x34 "RCSS_MCASPC_REF1_CLK_SRC_SEL,"
hexmask.long.word 0x34 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPC REF1 CLK"
line.long 0x38 "RCSS_MCASPC_AUX_CLK_SRC_SEL,"
hexmask.long.word 0x38 0.--11. 1. "clksrcsel,Select line for selecting source clock for RCSS MCASPC AUX CLK Data should be loaded as multibit"
line.long 0x3C "RCSS_I2CA_CLK_DIV_VAL,"
hexmask.long.word 0x3C 0.--11. 1. "clkdiv,Divider value for RCSS I2CA selected clock"
line.long 0x40 "RCSS_I2CB_CLK_DIV_VAL,"
hexmask.long.word 0x40 0.--11. 1. "clkdiv,Divider value for RCSS I2CB selected clock"
line.long 0x44 "RCSS_SCIA_CLK_DIV_VAL,"
hexmask.long.word 0x44 0.--11. 1. "clkdiv,Divider value for RCSS SCIA selected clock"
line.long 0x48 "RCSS_SPIA_CLK_DIV_VAL,"
hexmask.long.word 0x48 0.--11. 1. "clkdiv,Divider value for RCSS SPIA selected clock"
line.long 0x4C "RCSS_SPIB_CLK_DIV_VAL,"
hexmask.long.word 0x4C 0.--11. 1. "clkdiv,Divider value for RCSS SPIB selected clock"
line.long 0x50 "RCSS_ATL_CLK_DIV_VAL,"
hexmask.long.word 0x50 0.--11. 1. "clkdiv,Divider value for RCSS ATL CLK selected clock"
line.long 0x54 "RCSS_MCASPA_REF0_CLK_DIV_VAL,"
hexmask.long.word 0x54 0.--11. 1. "clkdiv,Divider value for RCSS MCASPA REF0 CLK selected clock"
line.long 0x58 "RCSS_MCASPA_REF1_CLK_DIV_VAL,"
hexmask.long.word 0x58 0.--11. 1. "clkdiv,Divider value for RCSS MCASPA REF1 CLK selected clock"
line.long 0x5C "RCSS_MCASPA_AUX_CLK_DIV_VAL,"
hexmask.long.word 0x5C 0.--11. 1. "clkdiv,Divider value for RCSS MCASPA AUX CLK selected clock"
line.long 0x60 "RCSS_MCASPB_REF0_CLK_DIV_VAL,"
hexmask.long.word 0x60 0.--11. 1. "clkdiv,Divider value for RCSS MCASPB REF0 CLK selected clock"
line.long 0x64 "RCSS_MCASPB_REF1_CLK_DIV_VAL,"
hexmask.long.word 0x64 0.--11. 1. "clkdiv,Divider value for RCSS MCASPB REF1 CLK selected clock"
line.long 0x68 "RCSS_MCASPB_AUX_CLK_DIV_VAL,"
hexmask.long.word 0x68 0.--11. 1. "clkdiv,Divider value for RCSS MCASPB AUX CLK selected clock"
line.long 0x6C "RCSS_MCASPC_REF0_CLK_DIV_VAL,"
hexmask.long.word 0x6C 0.--11. 1. "clkdiv,Divider value for RCSS MCASPC REF0 CLK selected clock"
line.long 0x70 "RCSS_MCASPC_REF1_CLK_DIV_VAL,"
hexmask.long.word 0x70 0.--11. 1. "clkdiv,Divider value for RCSS MCASPC REF1 CLK selected clock"
line.long 0x74 "RCSS_MCASPC_AUX_CLK_DIV_VAL,"
hexmask.long.word 0x74 0.--11. 1. "clkdiv,Divider value for RCSS MCASPC AUX CLK selected clock"
line.long 0x78 "RCSS_I2CA_CLK_GATE,"
bitfld.long 0x78 0.--2. "gated,Clock gatring config for RCSS I2CA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x7C "RCSS_I2CB_CLK_GATE,"
bitfld.long 0x7C 0.--2. "gated,Clock gatring config for RCSS I2CB Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x80 "RCSS_SCIA_CLK_GATE,"
bitfld.long 0x80 0.--2. "gated,Clock gatring config for RCSS SCIA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x84 "RCSS_SPIA_CLK_GATE,"
bitfld.long 0x84 0.--2. "gated,Clock gatring config for RCSS SPIA Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x88 "RCSS_SPIB_CLK_GATE,"
bitfld.long 0x88 0.--2. "gated,Clock gatring config for RCSS SPIB Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x8C "RCSS_ATL_CLK_GATE,"
bitfld.long 0x8C 0.--2. "gated,Clock gatring config for RCSS ATL CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x90 "RCSS_MCASPA_REF0_CLK_GATE,"
bitfld.long 0x90 0.--2. "gated,Clock gatring config for RCSS MCASPA REF0 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x94 "RCSS_MCASPA_REF1_CLK_GATE,"
bitfld.long 0x94 0.--2. "gated,Clock gatring config for RCSS MCASPA REF1 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x98 "RCSS_MCASPA_AUX_CLK_GATE,"
bitfld.long 0x98 0.--2. "gated,Clock gatring config for RCSS MCASPA AUX CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0x9C "RCSS_MCASPB_REF0_CLK_GATE,"
bitfld.long 0x9C 0.--2. "gated,Clock gatring config for RCSS MCASPB REF0 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xA0 "RCSS_MCASPB_REF1_CLK_GATE,"
bitfld.long 0xA0 0.--2. "gated,Clock gatring config for RCSS MCASPB REF1 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xA4 "RCSS_MCASPB_AUX_CLK_GATE,"
bitfld.long 0xA4 0.--2. "gated,Clock gatring config for RCSS MCASPB AUX CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xA8 "RCSS_MCASPC_REF0_CLK_GATE,"
bitfld.long 0xA8 0.--2. "gated,Clock gatring config for RCSS MCASPC REF0 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xAC "RCSS_MCASPC_REF1_CLK_GATE,"
bitfld.long 0xAC 0.--2. "gated,Clock gatring config for RCSS MCASPC REF1 CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xB0 "RCSS_MCASPC_AUX_CLK_GATE,"
bitfld.long 0xB0 0.--2. "gated,Clock gatring config for RCSS MCASPC AUX CLK Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xB4 "RCSS_ECAP_SYS_CLK_GATE,"
bitfld.long 0xB4 0.--2. "gated,Clock gatring config for RCSS ECAP Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xB8 "RCSS_CSI2A_SYS_CLK_GATE,"
bitfld.long 0xB8 0.--2. "gated,Clock gatring config for RCSS CSI2A Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xBC "RCSS_CSI2B_SYS_CLK_GATE,"
bitfld.long 0xBC 0.--2. "gated,Clock gatring config for RCSS CSI2B Data should be loaded as multibit" "Clock is ungated,?,?,?,?,?,?,Clock is gated"
line.long 0xC0 "RCSS_I2CA_CLK_STATUS,"
hexmask.long.byte 0xC0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS I2CA Clock"
hexmask.long.byte 0xC0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS I2CA Clock"
line.long 0xC4 "RCSS_I2CB_CLK_STATUS,"
hexmask.long.byte 0xC4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS I2CB Clock"
hexmask.long.byte 0xC4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS I2CB Clock"
line.long 0xC8 "RCSS_SCIA_CLK_STATUS,"
hexmask.long.byte 0xC8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS SCIA Clock"
hexmask.long.byte 0xC8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS SCIA Clock"
line.long 0xCC "RCSS_SPIA_CLK_STATUS,"
hexmask.long.byte 0xCC 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS SPIA Clock"
hexmask.long.byte 0xCC 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS SPIA Clock"
line.long 0xD0 "RCSS_SPIB_CLK_STATUS,"
hexmask.long.byte 0xD0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS SPIB Clock"
hexmask.long.byte 0xD0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS SPIB Clock"
line.long 0xD4 "RCSS_ATL_CLK_STATUS,"
hexmask.long.byte 0xD4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS ATL_CLK Clock"
hexmask.long.byte 0xD4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS ATL_CLK Clock"
line.long 0xD8 "RCSS_MCASPA_REF0_CLK_STATUS,"
hexmask.long.byte 0xD8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPA_REF0_CLK Clock"
hexmask.long.byte 0xD8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPA_REF0_CLK Clock"
line.long 0xDC "RCSS_MCASPA_REF1_CLK_STATUS,"
hexmask.long.byte 0xDC 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPA_REF1_CLK Clock"
hexmask.long.byte 0xDC 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPA_REF1_CLK Clock"
line.long 0xE0 "RCSS_MCASPA_AUX_CLK_STATUS,"
hexmask.long.byte 0xE0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPA_AUX_CLK Clock"
hexmask.long.byte 0xE0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPA_AUX_CLK Clock"
line.long 0xE4 "RCSS_MCASPB_REF0_CLK_STATUS,"
hexmask.long.byte 0xE4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPB_REF0_CLK Clock"
hexmask.long.byte 0xE4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPB_REF0_CLK Clock"
line.long 0xE8 "RCSS_MCASPB_REF1_CLK_STATUS,"
hexmask.long.byte 0xE8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPB_REF1_CLK Clock"
hexmask.long.byte 0xE8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPB_REF1_CLK Clock"
line.long 0xEC "RCSS_MCASPB_AUX_CLK_STATUS,"
hexmask.long.byte 0xEC 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPB_AUX_CLK Clock"
hexmask.long.byte 0xEC 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPB_AUX_CLK Clock"
line.long 0xF0 "RCSS_MCASPC_REF0_CLK_STATUS,"
hexmask.long.byte 0xF0 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPC_REF0_CLK Clock"
hexmask.long.byte 0xF0 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPC_REF0_CLK Clock"
line.long 0xF4 "RCSS_MCASPC_REF1_CLK_STATUS,"
hexmask.long.byte 0xF4 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPC_REF1_CLK Clock"
hexmask.long.byte 0xF4 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPC_REF1_CLK Clock"
line.long 0xF8 "RCSS_MCASPC_AUX_CLK_STATUS,"
hexmask.long.byte 0xF8 8.--15. 1. "currdivider,Status shows the current divider value choosen for RCSS MCASPC_AUX_CLK Clock"
hexmask.long.byte 0xF8 0.--7. 1. "clkinuse,Status shows the source clock slected for RCSS MCASPC_AUX_CLK Clock"
line.long 0xFC "RCSS_ECAP_RST_CTRL,"
bitfld.long 0xFC 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x100 "RCSS_CSI2A_RST_CTRL,"
bitfld.long 0x100 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x104 "RCSS_CSI2B_RST_CTRL,"
bitfld.long 0x104 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x108 "RCSS_I2CA_RST_CTRL,"
bitfld.long 0x108 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x10C "RCSS_I2CB_RST_CTRL,"
bitfld.long 0x10C 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x110 "RCSS_SCIA_RST_CTRL,"
bitfld.long 0x110 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x114 "RCSS_SPIA_RST_CTRL,"
bitfld.long 0x114 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x118 "RCSS_SPIB_RST_CTRL,"
bitfld.long 0x118 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x11C "RCSS_MCASPA_RST_CTRL,"
bitfld.long 0x11C 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x120 "RCSS_MCASPB_RST_CTRL,"
bitfld.long 0x120 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x124 "RCSS_MCASPC_RST_CTRL,"
bitfld.long 0x124 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x128 "RCSS_GIO_RST_CTRL,"
bitfld.long 0x128 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
line.long 0x12C "RCSS_EDMA_RST_CTRL,"
bitfld.long 0x12C 12.--14. "tptca1_assert,writing '111' will reset MSS_TPTCA0" "0,1,2,3,4,5,6,7"
bitfld.long 0x12C 8.--10. "tptca0_assert,writing '111' will reset MSS_TPCCA" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x12C 4.--6. "tpcca_assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
bitfld.long 0x12C 0.--2. "assert,This feature is for debug pupose only" "Reset is not asserted by SW,?,?,?,?,?,?,Reset is asserted by SW"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 3. (list 0. 1. 3. )(list 0x00 0x04 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "RCSS_SCI_A (RCSS SCIA Module Registers)"
base ad:0x50C0000
group.long 0x00++0x07
line.long 0x00 "UARTDR,Data Register. UARTDR"
hexmask.long.tbyte 0x00 12.--31. 1. "NU0,Reserved"
bitfld.long 0x00 11. "OE,Overrun error" "0,1"
newline
bitfld.long 0x00 10. "BE,Break error" "0,1"
bitfld.long 0x00 9. "PE,Parity error" "0,1"
newline
bitfld.long 0x00 8. "FE,Framing error" "0,1"
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive data character & Transmit data character"
line.long 0x04 "UARTRSR_ECR,Receive Status Register/Error Clear Register."
hexmask.long 0x04 4.--31. 1. "NU1,Reserved unpredictable when"
bitfld.long 0x04 3. "OE,Overrun error" "0,1"
newline
bitfld.long 0x04 2. "BE,Break error" "0,1"
bitfld.long 0x04 1. "PE,Parity error" "0,1"
newline
bitfld.long 0x04 0. "FE,Framing error" "0,1"
rgroup.long 0x18++0x03
line.long 0x00 "UARTFR,Flag Register. UARTFR"
hexmask.long.tbyte 0x00 9.--31. 1. "NU2,Reserved do not modify read as zero"
bitfld.long 0x00 8. "RI,Ring indicator" "0,1"
newline
bitfld.long 0x00 7. "TXFE,Transmit FIFO empty" "0,1"
bitfld.long 0x00 6. "RXFF,Receive FIFO full" "0,1"
newline
bitfld.long 0x00 5. "TXFF,Transmit FIFO full" "0,1"
bitfld.long 0x00 4. "RXFE,Receive FIFO empty" "0,1"
newline
bitfld.long 0x00 3. "BUSY,UART busy" "0,1"
bitfld.long 0x00 2. "DCD,Data carrier detect" "0,1"
newline
bitfld.long 0x00 1. "DSR,Data set ready" "0,1"
bitfld.long 0x00 0. "CTS,Clear to send" "0,1"
group.long 0x20++0x2B
line.long 0x00 "UARTILPR,IrDA Low-Power Counter Register. UARTILPR"
hexmask.long.tbyte 0x00 8.--31. 1. "NU3,Reserved"
hexmask.long.byte 0x00 0.--7. 1. "ILPDVSR,8-bit low-power divisor value"
line.long 0x04 "UARTIBRD,Integer Baud Rate Register. UARTIBRD"
hexmask.long.tbyte 0x04 8.--31. 1. "NU4,Reserved"
hexmask.long.byte 0x04 0.--7. 1. "BAUD_DIVINT,The fractional baud rate divisor"
line.long 0x08 "UARTFBRD,Fractional Baud Rate Register. UARTFBRD"
hexmask.long 0x08 6.--31. 1. "NU5,Reserved"
bitfld.long 0x08 0.--5. "BAUD_DIVFRAC,The fractional baud rate divisor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "UARTLCR_H,Line Control Register. UARTLCR_H"
hexmask.long.tbyte 0x0C 8.--31. 1. "NU6,Reserved do not modify read as zero"
bitfld.long 0x0C 7. "SPS,Stick parity select" "stick parity is disabled,if the EPS bit is 0 then the parity bit is.."
newline
bitfld.long 0x0C 5.--6. "WLEN,Word length" "5 bits,6 bits,7 bits,8 bits"
bitfld.long 0x0C 4. "FEN,Enable FIFOs" "FIFOs are disabled (character mode) that is the..,transmit and receive FIFO buffers are enabled.."
newline
bitfld.long 0x0C 3. "STP2,Two stop bits select" "0,1"
bitfld.long 0x0C 2. "EPS,Even parity select" "odd parity,even parity"
newline
bitfld.long 0x0C 1. "PEN,Parity enable" "parity is disabled and no parity bit added to..,parity checking and generation is enabled"
bitfld.long 0x0C 0. "BRK,Send break" "0,1"
line.long 0x10 "UARTCR,Control Register. UARTCR"
hexmask.long.word 0x10 16.--31. 1. "NU7,Reserved do not modify read as zero"
bitfld.long 0x10 15. "CTSEn,CTS hardware flow control enable" "0,1"
newline
bitfld.long 0x10 14. "RTSEn,RTS hardware flow control enable" "0,1"
bitfld.long 0x10 13. "Out2,This bit is the complement of the UART Out2 (nUARTOut2) modem status output" "0,1"
newline
bitfld.long 0x10 12. "Out1,This bit is the complement of the UART Out1 (nUARTOut1) modem status output" "0,1"
bitfld.long 0x10 11. "RTS,Request to send" "0,1"
newline
bitfld.long 0x10 10. "DTR,Data transmit ready" "0,1"
bitfld.long 0x10 9. "RXE,Receive enable" "0,1"
newline
bitfld.long 0x10 8. "TXE,Transmit enable" "0,1"
bitfld.long 0x10 7. "LBE,Loopback enable" "0,1"
newline
rbitfld.long 0x10 3.--6. "NU6,Reserved do not modify read as zero" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x10 2. "SIRLP,SIR low-power IrDA mode" "0,1"
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bitfld.long 0x10 1. "SIREN,SIR enable" "IrDA SIR ENDEC is disabled,IrDA SIR ENDEC is enabled"
bitfld.long 0x10 0. "UARTEN,UART enable" "UART is disabled,the UART is enabled"
line.long 0x14 "UARTIFLS,Interrupt FIFO Level Select Register. UARTIFLS"
hexmask.long 0x14 6.--31. 1. "NU8,Reserved do not modify read as zero"
bitfld.long 0x14 3.--5. "RXIFLSEL,Receive interrupt FIFO level select" "Receive FIFO becomes >= 1/8 full,Receive FIFO becomes >= 1/4 full,Receive FIFO becomes >= 1/2 full,Receive FIFO becomes >= 3/4 full,Receive FIFO becomes >= 7/8 full b101-b111 =..,?..."
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bitfld.long 0x14 0.--2. "TXIFLSEL,Transmit interrupt FIFO level select" "Transmit FIFO becomes <= 1/8 full,Transmit FIFO becomes <= 1/4 full,Transmit FIFO becomes <= 1/2 full,Transmit FIFO becomes <= 3/4 full,Transmit FIFO becomes <= 7/8 full b101-b111 =..,?..."
line.long 0x18 "UARTIMSC,Interrupt Mask Set/Clear Register. UARTIMSC"
hexmask.long.tbyte 0x18 11.--31. 1. "NU9,Reserved read as zero do not modify"
bitfld.long 0x18 10. "OEIM,Overrun error interrupt mask" "0,1"
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bitfld.long 0x18 9. "BEIM,Break error interrupt mask" "0,1"
bitfld.long 0x18 8. "PEIM,Parity error interrupt mask" "0,1"
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bitfld.long 0x18 7. "FEIM,Framing error interrupt mask" "0,1"
bitfld.long 0x18 6. "RTIM,Receive timeout interrupt mask" "0,1"
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bitfld.long 0x18 5. "TXIM,Transmit interrupt mask" "0,1"
bitfld.long 0x18 4. "RXIM,Receive interrupt mask" "0,1"
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bitfld.long 0x18 3. "DSRMIM,nUARTDSR modem interrupt mask" "0,1"
bitfld.long 0x18 2. "DCDMIM,nUARTDCD modem interrupt mask" "0,1"
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bitfld.long 0x18 1. "CTSMIM,nUARTCTS modem interrupt mask" "0,1"
bitfld.long 0x18 0. "RIMIM,nUARTRI modem interrupt mask" "0,1"
line.long 0x1C "UARTRIS,Raw Interrupt Status Register. UARTRIS"
hexmask.long.tbyte 0x1C 10.--31. 1. "NU10,Reserved read as zero do not modify"
bitfld.long 0x1C 9. "OERIS,Overrun error interrupt status" "0,1"
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bitfld.long 0x1C 8. "PERIS,Parity error interrupt status" "0,1"
bitfld.long 0x1C 7. "FERIS,Framing error interrupt status" "0,1"
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bitfld.long 0x1C 6. "RTRIS,Receive timeout interrupt status" "0,1"
bitfld.long 0x1C 5. "TXRIS,Transmit interrupt status" "0,1"
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bitfld.long 0x1C 4. "RXRIS,Receive interrupt status" "0,1"
bitfld.long 0x1C 3. "DSRRMIS,nUARTDSR modem interrupt status" "0,1"
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bitfld.long 0x1C 2. "DCDRMIS,nUARTDCD modem interrupt status" "0,1"
bitfld.long 0x1C 1. "CTSRMIS,nUARTCTS modem interrupt status" "0,1"
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bitfld.long 0x1C 0. "RIRMIS,nUARTRI modem interrupt status" "0,1"
line.long 0x20 "UARTMIS,Masked Interrupt Status Register. UARTMIS"
hexmask.long.tbyte 0x20 11.--31. 1. "NU11,Reserved read as zero do not modify"
bitfld.long 0x20 10. "OEMIS,Overrun error masked interrupt status" "0,1"
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bitfld.long 0x20 9. "BEMIS,Break error masked interrupt status" "0,1"
bitfld.long 0x20 8. "PEMIS,Parity error masked interrupt status" "0,1"
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bitfld.long 0x20 7. "FEMIS,Framing error masked interrupt status" "0,1"
bitfld.long 0x20 6. "RTMIS,Receive timeout masked interrupt status" "0,1"
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bitfld.long 0x20 5. "TXMIS,Transmit masked interrupt status" "0,1"
bitfld.long 0x20 4. "RXMIS,Receive masked interrupt status" "0,1"
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bitfld.long 0x20 3. "DSRMMIS,nUARTDSR modem masked interrupt status" "0,1"
bitfld.long 0x20 2. "DCDMMIS,nUARTDCD modem masked interrupt status" "0,1"
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bitfld.long 0x20 1. "CTSMMIS,nUARTCTS modem masked interrupt status" "0,1"
bitfld.long 0x20 0. "RIMMIS,nUARTRI modem masked" "0,1"
line.long 0x24 "UARTICR,Interrupt Clear Register. UARTICR"
hexmask.long.tbyte 0x24 11.--31. 1. "NU12,Reserved read as zero do not modify"
bitfld.long 0x24 10. "OEIC,Overrun error interrupt clear" "0,1"
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bitfld.long 0x24 9. "BEIC,Break error interrupt clear" "0,1"
bitfld.long 0x24 8. "PEIC,Parity error interrupt clear" "0,1"
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bitfld.long 0x24 7. "FEIC,Framing error interrupt clear" "0,1"
bitfld.long 0x24 6. "RTIC,Receive timeout interrupt clear" "0,1"
newline
bitfld.long 0x24 5. "TXIC,Transmit interrupt clear" "0,1"
bitfld.long 0x24 4. "RXIC,Receive interrupt clear" "0,1"
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bitfld.long 0x24 3. "DSRMIC,nUARTDSR modem interrupt clear" "0,1"
bitfld.long 0x24 2. "DCDMIC,nUARTDCD modem interrupt clear" "0,1"
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bitfld.long 0x24 1. "CTSMIC,nUARTCTS modem interrupt clear" "0,1"
bitfld.long 0x24 0. "RIMIC,nUARTRI modem interrupt clear" "0,1"
line.long 0x28 "UARTDMACR,DMA Control Register. UARTDMACR"
hexmask.long 0x28 3.--31. 1. "NU13,Reserved read as zero do not modify"
bitfld.long 0x28 2. "DMAONERR,DMA on error" "0,1"
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bitfld.long 0x28 1. "TXDMAE,Transmit DMA enable" "0,1"
bitfld.long 0x28 0. "RXDMAE,Receive DMA enable" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFF0)++0x03
line.long 0x00 "UARTPCellID$1,PrimeCell Identification Registers UARTPCellID0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "UARTPeriphID$1,Peripheral Identification Registers UARTPeriphID0"
repeat.end
width 0x0B
tree.end
tree "RCSS_SPIA (RCSS SPIA Module Registers)"
base ad:0x5F7E800
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
newline
rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
newline
bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
newline
bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
newline
bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
newline
rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
newline
rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
newline
bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
newline
bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
newline
hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
newline
bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
newline
bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
newline
rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
newline
bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
newline
rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
newline
bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
newline
bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
newline
bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
newline
bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
newline
bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
newline
abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
newline
rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
newline
bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
newline
bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
newline
bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
newline
abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
newline
abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
newline
rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
newline
bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
newline
bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
newline
bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
newline
abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
newline
bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
newline
bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
newline
bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
newline
bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
newline
abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
newline
rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
newline
bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
newline
bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
newline
bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
newline
abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
newline
rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
newline
bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
newline
bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
newline
bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
newline
abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
newline
rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
newline
bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
newline
bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
newline
bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
newline
abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
newline
abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
newline
rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
newline
bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
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bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
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rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
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rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
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bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
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bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
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hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
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bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
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rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "RCSS_SPIB (RCSS SPIB Module Registers)"
base ad:0x5F7EA00
group.long 0x00++0x2F
line.long 0x00 "SPIGCR0,SPI / MibSPI Global Control Register 0"
hexmask.long 0x00 1.--31. 1. "NU,Reserved Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "nRESET,This is the local reset control for the module" "SPI / MibSPI is in reset state,SPI / MibSPI is out of reset state"
line.long 0x04 "SPIGCR1,SPI / MibSPI Global control register 1"
hexmask.long.byte 0x04 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x04 24. "SPIEN,SPI enable" "SPI / MibSPI is not activated for transfers,Activates SPI / MibSPI"
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hexmask.long.byte 0x04 17.--23. 1. "NU3,Reserved"
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bitfld.long 0x04 16. "LOOPBACK,LOOP BACK" "Internal loop-back test mode disabled,Internal loop-back test mode enabled"
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hexmask.long.byte 0x04 9.--15. 1. "NU2,Reserved"
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bitfld.long 0x04 8. "POWERDOWN,POWERDOWN" "MibSPI in active mode,MibSPI in powerdown mode"
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rbitfld.long 0x04 2.--7. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "CLKMOD,CLKMOD" "Clock is external,Clock is internal"
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bitfld.long 0x04 0. "MASTER,MASTER: SPISIMO/SPISOMI pin direction determination" "SPISIMO pin an input SPISOMI pin an output,SPISOMI pin an input SPISIMO pin an output"
line.long 0x08 "SPIINT0,SPI / MibSPI Interrupt Enable Register"
hexmask.long.byte 0x08 25.--31. 1. "NU5,Reserved"
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bitfld.long 0x08 24. "ENABLEHIGHZ,SPIENA pin high-z enable" "SPIENA pin is pulled high when not active,SPIENA pin remains in high-z when not active"
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hexmask.long.byte 0x08 17.--23. 1. "NU4,Reserved"
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bitfld.long 0x08 16. "DMAREQEN,DMA request enable" "DMA is not used,DMA Requests will be generated"
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rbitfld.long 0x08 10.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x08 9. "TXINTENA,An interrupt is to be generated everytime data is written to the 'Shift Register' so that a new data can be written to TXBUF" "No interrupt will be generated upon TXINTFLG..,Interrupt will be generated upon TXINTFLG.."
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bitfld.long 0x08 8. "RXINTENA,An interrupt is to be generated when the RXINTFLAG bit (SPIFLG.8) is set by hardware" "Interrupt will not be generated,Interrupt will be generated Both Transmitter.."
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rbitfld.long 0x08 7. "NU2,Reserved" "0,1"
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bitfld.long 0x08 6. "OVRNINTENA,Overrun interrupt enable" "Overrun interrupt will not be generated,Overrun interrupt will be generated"
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rbitfld.long 0x08 5. "NU1,Reserved" "0,1"
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bitfld.long 0x08 4. "BITERRENA,Enables interrupt on bit error" "No interrupt asserted upon bit error,Enables an interrupt on a bit error (BITERR = 1)"
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bitfld.long 0x08 3. "DESYNCENA,Enables interrupt on de-synchronized slave" "No interrupt asserted upon de-synchronization..,Enables an interrupt on de-synchronization of.."
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bitfld.long 0x08 2. "PARERRENA,Enables interrupt on parity error" "No interrupt asserted upon parity error,Enables an interrupt on a parity error.."
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bitfld.long 0x08 1. "TIMEOUTENA,Enables interrupt on ENA signal time-out" "No interrupt asserted upon ENA signal time-out,Enables an interrupt on a time-out of the ENA.."
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bitfld.long 0x08 0. "DLENERRENA,Data Length Error interrupt Enable" "No interrupt is generated upon Data Length Error,Enables an interrupt when Data Length Error occurs"
line.long 0x0C "SPILVL,SPI / MibSPI Interrupt Level Register"
hexmask.long.tbyte 0x0C 10.--31. 1. "NU3,Reserved"
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bitfld.long 0x0C 9. "TXINTLVL,Transmit Interrupt Level" "Transmit interrupt is mapped to interrupt line..,Transmit interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 8. "RXINTLVL,Receive interrupt level" "Receive interrupt is mapped to interrupt line INT0,Receive interrupt is mapped to interrupt line INT1"
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rbitfld.long 0x0C 7. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 6. "OVRNINTLVL,Receive Overrun interrupt level" "Receive Overrun interrupt is mapped to interrupt..,Receive Overrun interrupt is mapped to interrupt.."
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rbitfld.long 0x0C 5. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 4. "BITERRLVL,Bit error interrupt level" "bit error interrupt is mapped to interrupt line..,bit error interrupt is mapped to interrupt line.."
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bitfld.long 0x0C 3. "DESYNCLVL,De-synchronized slave interrupt level" "An interrupt due to de-synchronization of the..,An interrupt due to de-synchronization of the.."
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bitfld.long 0x0C 2. "PARERRLVL,Parity error interrupt level" "A parity error interrupt (PARITYERR = 1) is..,A parity error interrupt (PARITYERR = 1) is.."
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bitfld.long 0x0C 1. "TIMEOUTLVL,SPIENA pin Time-out interrupt level" "An interrupt on a time-out of the ENA signal..,An interrupt on a time-out of the ENA signal.."
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bitfld.long 0x0C 0. "DLENERRLVL,Data Length Error interrupt Enable Level" "An interrupt on Data Length Error is mapped to..,An interrupt on Data Length Error is mapped to.."
line.long 0x10 "SPIFLG,SPI / MibSPI Flag Register"
hexmask.long.byte 0x10 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x10 24. "BUFINITACTIVE,Indicates the status of Multibuffer initialization process" "Multibuffer RAM initialization is complete,Multibuffer RAM is still being initialized"
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hexmask.long.word 0x10 10.--23. 1. "NU3,Reserved"
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bitfld.long 0x10 9. "TXINTFLG,Transmitter Empty Interrupt Flag" "Transmit Buffer is now full,Transmit Buffer is empty"
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bitfld.long 0x10 8. "RXINTFLG,Receiver Full Interrupt Flag" "No new received data pending,A newly received data is ready to be read"
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rbitfld.long 0x10 7. "NU2,Reserved" "0,1"
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bitfld.long 0x10 6. "OVRNINTFLG,Receiver overrun flag" "Overrun condition did not occur,Overrun condition has occurred In SPI or.."
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rbitfld.long 0x10 5. "NU1,Reserved" "0,1"
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bitfld.long 0x10 4. "BITERRFLG,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x10 3. "DESYNCFLG,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x10 2. "PARERRFLG,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x10 1. "TIMEOUTFLG,Time-out due to non-activation of ENA signal" "No ENA-signal time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x10 0. "DLENERRFLG,Data Length Error Flag" "No Data Length Error has occured,A Data Length Error has occured"
line.long 0x14 "SPIPC0,SPI / MibSPI Pin Control Register 0 (SPIPC0) - SPIFUN Note: Duplicate Control Bits for SIMO0 & SOMI0 Bit 24 is not physically implemented"
abitfld.long 0x14 24.--31. "SOMIFUN,Slave out master in function" "0x00=SPISOMIx pin is a GPIO,0x01=SPISOMIx pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 16.--23. "SIMOFUN,Slave in master out function" "0x00=SPISIMOx pin is a GPIO,0x01=SPISIMOx pin is a SPI / MibSPI functional pin"
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rbitfld.long 0x14 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 11. "SOMIFUN0,Slave out master in function" "SPISOMI0 pin is a GPIO,SPISOMI0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 10. "SIMOFUN0,Slave in master out function" "SPISIMO0 pin is a GPIO,SPISIMO0 pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 9. "CLKFUN,SPI / MibSPI clock function" "SPICLK pin is a GPIO,SPICLK pin is a SPI / MibSPI functional pin"
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bitfld.long 0x14 8. "ENAFUN,SPIENA function" "SPIENA pin is a GPIO,SPIENA pin is a SPI / MibSPI functional pin"
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abitfld.long 0x14 0.--7. "SCSFUN,SPISCS[7:0] function" "0x00=SPISCSx pin is a GPIO,0x01=SPISCSx pin is a SPI functional pin"
line.long 0x18 "SPIPC1,SPI / MibSPI Pin Control Register 1 (SPIPC1) - SPIDIR"
abitfld.long 0x18 24.--31. "SOMIDIR,SPISOMIx direction" "0x00=SPISOMIx pin is an input,0x01=SPISOMIx pin is an output"
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abitfld.long 0x18 16.--23. "SIMODIR,SPISIMOx direction" "0x00=SPISIMOx pin is an input,0x01=SPISIMOx pin is an output"
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rbitfld.long 0x18 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 11. "SOMIDIR0,SPISOMI0 direction" "SPISOMI0 pin is an input,SPISOMI0 pin is an output"
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bitfld.long 0x18 10. "SIMODIR0,SPISIMO0 direction" "SPISIMO0 pin is an input,SPISIMO0 pin is an output"
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bitfld.long 0x18 9. "CLKDIR,SPICLK direction" "SPICLK pin is an input,SPICLK pin is an output"
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bitfld.long 0x18 8. "ENADIR,SPIENA direction" "SPIENA pin is an input,SPIENA pin is an output"
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abitfld.long 0x18 0.--7. "SCSDIR,SPISCS[7:0] direction" "0x00=SPISCSx pin is an input,0x01=SPISCSx pin is an output"
line.long 0x1C "SPIPC2,SPI / MibSPI Pin Control Register 2 (SPIPC2) - SPIDIN"
abitfld.long 0x1C 24.--31. "SOMIDIN,SPISOMIx data in" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
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abitfld.long 0x1C 16.--23. "SIMODIN,SPISIMOx data in" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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bitfld.long 0x1C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 11. "SOMIDIN0,SPISOMI0 data in" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x1C 10. "SIMODIN0,SPISIMO0 data in" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x1C 9. "CLKDIN,Clock data in" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
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bitfld.long 0x1C 8. "ENADIN,SPIENA data in" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x1C 0.--7. "SCSDIN,SPISCS[7:0] data in" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x20 "SPIPC3,SPI / MibSPI Pin Control Register 3 (SPIPC3) - SPIDOUT"
abitfld.long 0x20 24.--31. "SOMIDOUT,SPISOMIx dataout" "0x00=Current value on SPISOMIx pin is logic 0,0x01=Current value on SPISOMIx pin is logic 1"
newline
abitfld.long 0x20 16.--23. "SIMODOUT,SPISIMOx dataout" "0x00=Current value on SPISIMOx pin is logic 0,0x01=Current value on SPISIMOx pin is logic 1"
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rbitfld.long 0x20 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 11. "SOMIDOUT0,SPISOMI0 dataout" "Current value on SPISOMI0 pin is logic 0,Current value on SPISOMI0 pin is logic 1"
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bitfld.long 0x20 10. "SIMODOUT0,SPISIMO0 dataout" "Current value on SPISIMO0 pin is logic 0,Current value on SPISIMO0 pin is logic 1"
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bitfld.long 0x20 9. "CLKDOUT,SPICLK dataout" "Current value on SPICLK pin is logic 0,Current value on SPICLK pin is logic 1"
newline
bitfld.long 0x20 8. "ENADOUT,SPIENA dataout" "Current value on SPIENA pin is logic 0,Current value on SPIENA pin is logic 1"
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abitfld.long 0x20 0.--7. "SCSDOUT,SPISCS[7:0] dataout" "0x00=Current value on SPISCSx pin is logic 0,0x01=Current value on SPISCSx pin is logic 1"
line.long 0x24 "SPIPC4,SPI / MibSPI Pin Control Register 4 (SPIPC4) - SPIDSET"
abitfld.long 0x24 24.--31. "SOMISET,SPISOMIx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
newline
abitfld.long 0x24 16.--23. "SIMOSET,SPISIMOx dataout set" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x24 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 11. "SOMISET0,SPISOMI0 dataout set" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x24 10. "SIMOSET0,SPISIMO0 dataout set" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x24 9. "CLKSET,SPICLK dataout set" "Current value on CLKDOUT pin is logic 0,Current value on CLKDOUT pin is logic 1"
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bitfld.long 0x24 8. "ENASET,SPIENA dataout set" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x24 0.--7. "SCSSET,SPISCS[7:0] dataout set" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x28 "SPIPC5,SPI / MibSPI Pin Control Register 5 (SPIPC5) - SPIDCLR"
abitfld.long 0x28 24.--31. "SOMICLR,SPISOMIx dataout clear" "0x00=Current value on SOMIDOUTx is 0,0x01=Current value on SOMIDOUTx is 1"
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abitfld.long 0x28 16.--23. "SIMOCLR,SPISIMOx dataout clear" "0x00=Current value on SIMODOUTx is 0,0x01=Current value on SIMODOUTx is 1"
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rbitfld.long 0x28 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x28 11. "SOMICLR0,SPISOMI0 dataout clear" "Current value on SOMIDOUT0 is 0,Current value on SOMIDOUT0 is 1"
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bitfld.long 0x28 10. "SIMOCLR0,SPISIMO0 dataout clear" "Current value on SIMODOUT0 is 0,Current value on SIMODOUT0 is 1"
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bitfld.long 0x28 9. "CLKCLR,SPICLK dataout clear" "Current value on CLKDOUT is 0,Current value on CLKDOUT is 1"
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bitfld.long 0x28 8. "ENACLR,SPIENA dataout clear" "Current value on ENADOUT is 0,Current value on ENADOUT is 1"
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abitfld.long 0x28 0.--7. "SCSCLR,SPISCS[7:0] dataout clear" "0x00=Current value on SCSDOUTx is 0,0x01=Current value on SCSDOUTx is 1"
line.long 0x2C "SPIPC6,SPI / MibSPI Pin Control Register 6 (SPIPC6) - SPIPDR"
abitfld.long 0x2C 24.--31. "SOMIPDR,SPISOMIx Open drain enable Enables Open drain capability for the pin SOMIx if the following conditions are met" "0x00=Output value on SPISOMIx pin is logic '1',0x01=Output pin SPISOMIx is Tri-stated"
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abitfld.long 0x2C 16.--23. "SIMOPDR,SPISIMOx Open drain enable Enables Open drain capability for the pin SPISIMOx if the following conditions are met" "0x00=Output value on SPISIMOx pin is logic '1',0x01=Output pin SPISIMOx is Tri-stated"
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rbitfld.long 0x2C 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x2C 11. "SOMIPDR0,SPISOMI0 Open drain enable Enables Open drain capability for the pin SPISOMI if the following conditions are met" "Output value on SPISOMI0 pin is logic '1',Output pin SPISOMI0 is Tri-stated"
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bitfld.long 0x2C 10. "SIMOPDR0,SPISIMO0 Open drain enable Enables Open drain capability for the pin SPISIMO0 if the following conditions are met" "Output value on SPISIMO0 pin is logic '1',Output pin SPISIMO0 is Tri-stated"
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bitfld.long 0x2C 9. "CLKPDR,SPICLK Open drain enable Enables Open drain capability for the pin CLK if the following conditions are met" "Output value on SPICLK pin is logic '1',Output pin SPICLK is Tri-stated"
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bitfld.long 0x2C 8. "ENAPDR,SPIENA Open drain enable Enables Open drain capability for the pin SPIENA if the following conditions are met" "Output value on SPIENA pin is logic '1',Output pin SPIENA is Tri-stated"
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abitfld.long 0x2C 0.--7. "SCSPDR,SPISCSx Open drain enable Enables Open drain capability for the pin SPISCSx if the following conditions are met" "0x00=Output value on SPISCSx pin is logic '1',0x01=Output pin SPISCSx is Tri-stated"
group.long 0x38++0x17
line.long 0x00 "SPIDAT0,SPI / MibSPI Transmit Data Register 0 Note: Accessibility of SPIDAT0 The SPIDAT0 register is not accessible in Multibuffer Mode of MibSPI"
hexmask.long.word 0x00 16.--31. 1. "NU,Reserved"
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hexmask.long.word 0x00 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x04 "SPIDAT1,SPI / MibSPI Transmit Data Register 1 When this register is read. contents of internal buffer register TXBUF which holds the latest written data will be returned"
rbitfld.long 0x04 29.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x04 28. "CSHOLD,Chip select hold mode" "The chip select signal is deactivated at the end..,The chip select signal is held active at the end.."
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rbitfld.long 0x04 27. "NU1,Reserved" "0,1"
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bitfld.long 0x04 26. "WDEL,Enable the delay counter at the end of the current transaction" "No delay will be inserted,After a transaction WDELAY of the corresponding.."
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bitfld.long 0x04 24.--25. "DFSEL,DFSEL1 DFSEL0 Description 0 0 Data word format 0 is selected 0 1 Data word format 1 is selected 1 0 Data word format 2 is selected 1 1 Data word format 3 is selected" "0,1,2,3"
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hexmask.long.byte 0x04 16.--23. 1. "CSNR,Chip select number"
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hexmask.long.word 0x04 0.--15. 1. "TXDATA,SPI / MibSPI Transmit Data"
line.long 0x08 "SPIBUF,SPI / MibSPI Receive Buffer Register"
bitfld.long 0x08 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x08 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x08 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x08 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x08 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x08 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x08 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x08 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x08 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x08 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x0C "SPIEMU,SPI / MibSPI Emulation Register Note: All the fields ot SPIEMU register are Read-Only"
bitfld.long 0x0C 31. "RXEMPTY,Receive data buffer empty" "A new Data is received and copied into SPIBUF..,No data received since last reading of SPIBUF.."
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bitfld.long 0x0C 30. "RXOVR,Receive data buffer overrun" "No receive data overrun condition occurred since..,A receive data overrun condition occurred since.."
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bitfld.long 0x0C 29. "TXFULL,Transmit data buffer full" "Transmit buffer is empty SPIDAT0/SPIDAT1 is..,Transmit buffer is full SPIDAT0/SPIDAT1 is not.."
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bitfld.long 0x0C 28. "BITERR,Mismatch of internal transmit data and transmitted data" "No bit error occurred,A bit error occurred"
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bitfld.long 0x0C 27. "DESYNC,De-synchronization of slave device" "No slave de-synchronization detected,A slave device is de-synchronized"
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bitfld.long 0x0C 26. "PARITYERR,Calculated parity differs from received parity bit" "No parity error detected,A parity error occurred"
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bitfld.long 0x0C 25. "TIMEOUT,Time-out due to non-activation of ENA pin" "No ENA-pin time-out occurred,An ENA signal time-out occurred"
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bitfld.long 0x0C 24. "DLENERR,Data Length Error flag" "No Data Length Error has occured,A Data Length Error has occured"
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hexmask.long.byte 0x0C 16.--23. 1. "LCSNR,Last Chip select number"
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hexmask.long.word 0x0C 0.--15. 1. "RXDATA,SPI Receive Data"
line.long 0x10 "SPIDELAY,SPI / MibSPI Delay Register"
hexmask.long.byte 0x10 24.--31. 1. "C2TDELAY,Chip-select-active-to-transmit-start-delay"
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hexmask.long.byte 0x10 16.--23. 1. "T2CDELAY,Transmit-end-to-chip-select-inactive-delay"
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hexmask.long.byte 0x10 8.--15. 1. "T2EDELAY,Transmit-data-finished-to-ENA-pin-inactive-time-out"
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hexmask.long.byte 0x10 0.--7. 1. "C2EDELAY,Chip-select-active-to-ENA-signal-active-time-out C2EDELAY is utilized only in master mode and it applies only if the addressed slave generates an ENA signal as a hardware handshake response"
line.long 0x14 "SPIDEF,SPI / MibSPI Default Chip select Register"
hexmask.long.tbyte 0x14 8.--31. 1. "NU,Reserved"
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abitfld.long 0x14 0.--7. "CSDEF0,Chip select default pattern" "0x00=If CSDEFx is set to '0' the corresponding..,0x01=If CSDEFx is set to '1' the corresponding.."
rgroup.long 0x60++0x27
line.long 0x00 "TGINTVECT0,SPI Interrupt Vector Register 0 / MibSPI Transfer Group Interrupt Vector Register 0"
hexmask.long 0x00 6.--31. 1. "NU,Reserved"
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bitfld.long 0x00 1.--5. "INTVECT0,Interrupt vector for interrupt line INT0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 0. "SUSPEND0,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI only) The SUSPEND0 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x04 "TGINTVECT1,SPI Interrupt Vector Register 1 / MibSPI Transfer Group Interrupt Vector Register 1"
hexmask.long 0x04 6.--31. 1. "NU,Reserved"
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bitfld.long 0x04 1.--5. "INTVECT1,Interrupt vector for interrupt line INT1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 0. "SUSPEND1,'Transfer suspended' or 'transfer finished' interrupt.(MibSPI Only) The SUSPEND1 flag is updated depending on the type of interrupt reflected by the VECTOR value field" "The interrupt type is a 'transfer finished'..,The interrupt type is a 'transfer suspended'.."
line.long 0x08 "SPIPC9,SPI/MibSPI Pin Control Register 9 (SPIPC9) - SPISRSEL"
abitfld.long 0x08 24.--31. "SOMISRS7,Each of these 7 bits controls the slew rate for the corresponding SPISOMIx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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abitfld.long 0x08 16.--23. "SIMOSRS7,Each of these 7 bits controls the slew rate for the corresponding SPISIMOx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
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rbitfld.long 0x08 12.--15. "NU,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 11. "SOMISRS0,This bit controls the slew rate for SPISOMI0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 10. "SIMOSRS0,This bit controls the slew rate for SPISIMO0 pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 9. "CLKSRS,This bit controls the slew rate for SPICLK pin" "Normal Buffer Select,Slow Buffer Select"
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bitfld.long 0x08 8. "ENASRS,This bit controls the slew rate for SPIENA pin" "Fast Buffer Select,Slow Buffer Select"
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abitfld.long 0x08 0.--7. "SCSSRS,Each of these 7 bits controls the slew rate for the corresponding SPISCSx pin" "0x00=Normal Buffer Select,0x01=Slow Buffer Select"
line.long 0x0C "SPIPMCTRL,SPI/MibSPI Parallel/Modulo Mode Control Register"
rbitfld.long 0x0C 31. "NU4,Reserved" "0,1"
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bitfld.long 0x0C 30. "HSM_MODE3,High Speed Modulo Mode control bit for Data Format 3" "Normal mode - Normal Parallel mode if PMODE3..,High Speed Modulo Mode"
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bitfld.long 0x0C 29. "MODCLKPOL3,Modulo mode SPICLK Polarity for Data Format 3 Determines the Polarity of the SPICLK in Modulo mode only" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 26.--28. "MMODE3,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format" "?,2-data line Mode..,3-data line mode..,4-data line mode..,5-data line mode..,6-data line mode..,Reserved,Reserved"
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bitfld.long 0x0C 24.--25. "PMODE3,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 3" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 23. "NU3,Reserved" "0,1"
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bitfld.long 0x0C 22. "HSM_MODE2,High Speed Modulo Mode control bit for Data Format 2" "Normal mode - Normal Parallel mode if PMODE2..,High Speed Modulo Mode"
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bitfld.long 0x0C 21. "MODCLKPOL2,Modulo mode SPICLK Polarity for Data Format 2" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 18.--20. "MMODE2,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 2" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 16.--17. "PMODE2,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 2" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to..,?,8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 15. "NU2,Reserved" "0,1"
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bitfld.long 0x0C 14. "HSM_MODE1,High Speed Modulo Mode control bit for Data Format 1" "Normal mode - Normal Parallel mode if PMODE1..,High Speed Modulo Mode"
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bitfld.long 0x0C 13. "MODCLKPOL1,Modulo mode SPICLK Polarity for Data Format 1" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 10.--12. "MMODE1,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 1" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 8.--9. "PMODE1,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 1" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
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rbitfld.long 0x0C 7. "NU1,Reserved" "0,1"
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bitfld.long 0x0C 6. "HSM_MODE0,High Speed Modulo Mode control bit for Data Format 0" "Normal mode - Normal Parallel mode if PMODE0..,High Speed Modulo Mode"
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bitfld.long 0x0C 5. "MODCLKPOL0,Modulo mode SPICLK Polarity for Data Format 0" "Normal SPICLK in all the modes,Polarity of the SPICLK will be inverted if.."
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bitfld.long 0x0C 2.--4. "MMODE0,These bits determine whether the SPI/MibSPI operates with 1 2 4 5 or 6 data lines (if Modulo Option is supported by the module) for Data Format 0" "1-data line Mode - Default (PMODE should be set..,2-data line Mode (PMODE should be set to '00'),3-data line mode (PMODE should be set to '00'),4-data line mode (PMODE should be set to '00'),5-data line mode (PMODE should be set to '00'),6-data line mode (PMODE should be set to '01'),Reserved,Reserved"
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bitfld.long 0x0C 0.--1. "PMODE0,Parallel mode bits determine whether the SPI/MibSPI operates with 1 2 4 or 8 data lines for Data Format 0" "normal operation / 1-data line (MMODE should be..,2-data line mode (MMODE should be set to '000'),4-data line mode (MMODE should be set to '000'),8-data line mode (MMODE should be set to '000')"
line.long 0x10 "MIBSPIE,MibSPI Enable Register"
hexmask.long.word 0x10 17.--31. 1. "NU3,Reserved"
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bitfld.long 0x10 16. "RXRAMACCESS,Receive RAM Access control Bit" "The RX portion of Multibuffer RAM is not..,The whole of Multibuffer RAM is fully accessible.."
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rbitfld.long 0x10 12.--15. "NU2,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 8.--11. "EXTENDED_BUF_ENA,Enables the support for 256 buffers" "?,?,?,?,?,Extended Buffer mode is disabled - MibSPI..,?,?,?,?,Extended Buffer mode is enabled - up to 256..,?..."
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hexmask.long.byte 0x10 1.--7. 1. "NU1,Reserved"
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bitfld.long 0x10 0. "MSPIENA,Multibuffer mode Enable" "The MibSPI runs in compatibility mode i.e,The MibSPI is configured to run in MibSPI mode.."
line.long 0x14 "TGITENST,MibSPI Transfer Group Interrupt Enable Set Register"
abitfld.long 0x14 16.--31. "SETINTENRDY,Transfer group interrupt set (enable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x14 0.--15. "SETINTENSUS,Transfer group interrupt set (enable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x18 "TGITENCR,MibSPI Transfer Group Interrupt Enable Clear Register"
abitfld.long 0x18 16.--31. "CLRINTENRDY,Transfer group interrupt clear (disable) when transfer finished" "0x0000='The Transfer group x completed'..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x18 0.--15. "CLRINTENSUS,Transfer group interrupt clear (disable) when transfer suspended Write" "0x0000='The Transfer group x suspended'..,0x0001='The Transfer group x suspended '.."
line.long 0x1C "TGITLVST,MibSPI Transfer Group Interrupt Level Set Register"
abitfld.long 0x1C 16.--31. "SETINTLVLRDY,Transfer group completed' Interrupt Level set register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x1C 0.--15. "SETINTLVLSUS,Transfer group suspended' interrupt Level set rigester Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x20 "TGITLVCR,MibSPI Transfer Group Interrupt Level Clear Register"
abitfld.long 0x20 16.--31. "CLRINTLVLRDY,Transfer group completed' Interrupt Level clear register Write" "0x0000='The Transfer group x completed '..,0x0001='The Transfer group x completed '.."
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abitfld.long 0x20 0.--15. "CLRINTLVLSUS,Transfer group suspended' interrupt Level clear register Write" "0x0000='The Transfer group x suspended '..,0x0001='The Transfer group x suspended '.."
line.long 0x24 "TGINTFLAG,Transfer Group Interrupt Flag Register"
abitfld.long 0x24 16.--31. "INTFLGRDY,Transfer group interrupt flag for 'transfer finished' interrupt" "0x0000=Has no effect,0x0001=Clears the corresponding bit flag"
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abitfld.long 0x24 0.--15. "INTFLGSUS,Transfer group interrupt flag for 'transfer suspend' interrupt" "0x0000=No 'transfer suspended' interrupt..,0x0001=A 'transfer suspended' interrupt from.."
group.long 0x90++0x27
line.long 0x00 "TICKCNT,Tick Count Register"
bitfld.long 0x00 31. "TICKENA,Tick counter enable" "The MibSPI internal tick counter is disabled,The MibSPI internal tick counter is enabled and.."
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rbitfld.long 0x00 30. "RELOAD,Re-load tick counter" "0,1"
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bitfld.long 0x00 28.--29. "CLKCTRL,Tick counter clock source control" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x00 0.--15. 1. "TICKVALUE,Initial value for tick counter"
line.long 0x04 "LTGPEND,Last Transfer Group End Pointer"
rbitfld.long 0x04 29.--31. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x04 24.--28. "TGINSERVICE,Transfer Group currently being serviced by the Sequencer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.byte 0x04 16.--23. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.byte 0x04 8.--15. 1. "LPEND,Last Transfer Group End Pointer Usually the transfer group end address (PEND) is inherently defined by the start value of the starting pointer of the subsequent transfer group (PSTART)"
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hexmask.long.byte 0x04 0.--7. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
line.long 0x08 "TG0CTRL,MibSPI Transfer Group Control Register The number of transfer groups is scalable by design up to a maximum of 16"
bitfld.long 0x08 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x08 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x08 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x08 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x08 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x08 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x08 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x0C "TG1CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x0C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x0C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x0C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x0C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x0C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x0C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x0C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x10 "TG2CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x10 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x10 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x10 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x10 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x10 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x10 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x10 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x14 "TG3CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x14 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x14 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x14 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x14 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x14 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x14 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x14 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x18 "TG4CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x18 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x18 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x18 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x18 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x18 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x18 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x18 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x18 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x1C "TG5CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x1C 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x1C 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x1C 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x1C 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x1C 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x1C 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x1C 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x1C 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x20 "TG6CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x20 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x20 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x20 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x20 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x20 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x20 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x20 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x20 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
line.long 0x24 "TG7CTRL,MibSPI Transfer Group Control Register"
bitfld.long 0x24 31. "TGENA,Transfer Group Enable" "The corresponding transfer group is disabled,The corresponding transfer group is enabled"
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bitfld.long 0x24 30. "ONESHOT,Single transfer for this Transfer Group group" "The corresponding transfer group initiates a..,A transfer from the corresponding transfer group.."
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bitfld.long 0x24 29. "PRST,transfer group Pointer Reset mode" "If a trigger event occurs during a transfer from..,The corresponding transfer group pointer.."
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bitfld.long 0x24 28. "TGTD,Transfer group triggered" "The corresponding transfer group has not been..,The transfer group has been triggered and is.."
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rbitfld.long 0x24 24.--27. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 20.--23. "TRIGEVT,Type of trigger event" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x24 16.--19. "TRIGSRC,Trigger source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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hexmask.long.byte 0x24 8.--15. 1. "PSTART,transfer group start address"
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hexmask.long.byte 0x24 0.--7. 1. "PCURRENT,transfer group pointer to current buffer"
group.long 0xD8++0x13
line.long 0x00 "DMA0CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x00 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x00 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x00 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x00 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x00 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x00 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x00 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x00 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "DMA1CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x04 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x04 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x04 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x04 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x04 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x04 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x04 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x04 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x04 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x08 "DMA2CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x08 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x08 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x08 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x08 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x08 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x08 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x08 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x08 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x08 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x08 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x0C "DMA3CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x0C 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x0C 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x0C 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x0C 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x0C 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x0C 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x0C 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x0C 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x0C 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x0C 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x10 "DMA4CTRL,MibSPI DMA Channel Control Register"
bitfld.long 0x10 31. "ONESHOT,Auto-disable of DMA channel after ICOUNT+1 transfers" "The length of the block transfer is fully..,ONESHOTx allows a block transfer of defined.."
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hexmask.long.byte 0x10 24.--30. 1. "BUFID,Buffer utilized for DMA transfer"
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bitfld.long 0x10 20.--23. "RXDMA_MAP,Receive data DMA Request Map Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 16.--19. "TXDMA_MAP,Transmit data DMA channel Each MibSPI DMA channel can be linked to two physical DMA Request lines of the DMA controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x10 15. "RXDMAENA,Receive data DMA channel enable" "No DMA request upon new receive data,The physical DMA Request line for the receive.."
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bitfld.long 0x10 14. "TXDMAENA,Transmit data DMA channel enable" "No DMA request upon new transmit data,The physical DMA Request line for the transmit.."
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bitfld.long 0x10 13. "NOBRK,Non-interleaved DMA block transfer(Master mode only)" "The DMA transfers through the buffer referenced..,NOBRKx ensures that ICOUNTx+1 data transfers are.."
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bitfld.long 0x10 8.--12. "ICOUNT,Initial Count of DMA transfers ICOUNTx[4:0] is used to preset the transfer counter COUNTx[4:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x10 7. "BUFID7,Extended bit of BUFIDx field when Extended Buffer feature is implemented" "0,1"
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rbitfld.long 0x10 6. "COUNTBIT17,The 17th bit of COUNT field of DMAxCOUNT register" "0,1"
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rbitfld.long 0x10 0.--5. "COUNT,Actual number of remaining DMA transfer COUNTx[5:0] is a read-only bit field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rgroup.word 0x100++0x01
line.word 0x00 "ICOUNT2,MibSPI DMAxCOUNT"
group.long 0x118++0x03
line.long 0x00 "DMACNTLEN,DMA LARGE COUNT register"
hexmask.long 0x00 1.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 0. "LARGE_COUNT," "0,1"
group.long 0x120++0x2F
line.long 0x00 "PAR_ECC_CTRL,Parity/ECC Control Register"
rbitfld.long 0x00 28.--31. "NU4,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 24.--27. "SBE_EVT_EN,Single Bit Error Event Enable This bit controls the generation of Error signaling (on MIBSPI_SBERR port) whenever a Single Bit Errors (SBE) is detected on TXRAM/RXRAM" "?,?,?,?,?,Disable Error Event indication upon detection of..,?,?,?,?,Enable Error Event upon detection of SBE on..,?..."
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rbitfld.long 0x00 20.--23. "NU3,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 16.--19. "EDAC_MODE,Error Detection And Correction Mode These bits determine whether Single Bit Errors (SBE) detected by the SECDED block will be corrected or not" "?,?,?,?,?,Disable correction of SBE detected by the SECDED..,?,?,?,?,Enable correction of SBE detected by the SECDED..,?..."
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hexmask.long.byte 0x00 9.--15. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x00 8. "PTESTEN,Parity/ECC memory Test Enable" "disable memory mapping of Parity/ECC locations,enable memory mapping of Parity/ECC locations"
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rbitfld.long 0x00 4.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "EDEN,Error Detection Enable These bits enable Parity/ECC Error Detection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x04 "PAR_ECC_STAT,Parity/ECC Status Register"
hexmask.long.tbyte 0x04 10.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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bitfld.long 0x04 9. "SBE_FLG1,Single Bit Error in RXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 8. "SBE_FLG0,Single Bit Error in TXRAM" "No effect,Clears the bit"
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bitfld.long 0x04 2.--7. "NU1,Reserved.Reads return '0' and writes have no effect" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x04 1. "UERR_FLG1,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or double bit ECC error ocurred on reading RXRAM When this bit is read" "No effect,Clears the bit"
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bitfld.long 0x04 0. "UERR_FLG0,Uncorrectable Parity or double bit ECC error detection flag This flag indicates if a Parity or ECC error ocurred on reading TXRAM When this bit is read" "No effect,Clears the bit"
line.long 0x08 "UERRADDR1,Uncorrectable Parity or double bit ECC error Address Register - RXRAM"
hexmask.long.tbyte 0x08 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x08 0.--10. 1. "UERRADDR1,Uncorrectable Parity or double bit ECC error address This register holds the address of the RAM location if a parity or double bit ECC error is detected when reading the MibSPI (Receive) RXRAM"
line.long 0x0C "UERRADDR0,Uncorrectable Parity or double bit ECC error address register - TXRAM"
hexmask.long.tbyte 0x0C 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x0C 0.--10. 1. "UERRADDR0,Uncorrectable Parity or double bit ECC error address This register holds the address when a parity error is generated while reading the MibSPI (Transmit) TXRAM"
line.long 0x10 "RXOVRN_BUF_ADDR,Receive RAM Overrun Buffer Address Register"
hexmask.long.tbyte 0x10 11.--31. 1. "NU,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x10 0.--10. 1. "RXOVRN_BUF_ADDR,Address of the RAM location of RXRAM for which an Overwrite occured"
line.long 0x14 "IOLPBKTSTCR,SPI/MibSPI IO Loopback Test Control Register This register controls test mode for I/O pins"
hexmask.long.byte 0x14 25.--31. 1. "NU4,Reserved"
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bitfld.long 0x14 24. "SCSFAILFLG,Bit indicating a failure on SPISCS pin compare during analog loopback during IO Loopback Test mode" "No effect,Clear this Flag bit"
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rbitfld.long 0x14 21.--23. "NU3,Reserved" "0,1,2,3,4,5,6,7"
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bitfld.long 0x14 20. "CTRLBITERR,Controls inducing of BITERR during IO Loopback Test mode" "No affect on BIT ERROR,The value of incoming data from the loopback.."
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bitfld.long 0x14 19. "CTRLDESYNC,Controls inducing of DESYNC Error during IO Loopback Test mode" "No affect on DESYNC Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 18. "CTRLPARERR,Controls inducing of Parity Error during IO Loopback Test mode" "No affect on Parity Error,Flips the Parity Polarity signal being used for.."
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bitfld.long 0x14 17. "CTRLTIMEOUT,Controls inducing of TIMEOUT Error during IO LoopbacK Test mode" "No affect on TIMEOUT Error,Forces the incoming SPIENA pin (if functional).."
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bitfld.long 0x14 16. "CTRLDLENERR,Controls inducing of Data Length Error during IO Loopback Test mode" "No affect on Data Length Error,When in Master mode forces the SPIENA pin(if.."
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rbitfld.long 0x14 12.--15. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x14 8.--11. "IOLPBKTSTENA,Module I/O Loopback Test Enable Key User and Privileged mode reads" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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rbitfld.long 0x14 6.--7. "NU1,Reserved" "0,1,2,3"
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bitfld.long 0x14 3.--5. "ERRSCSPIN,Inject Error on ChipSelect Pin" "Select SPISCS[0] for injecting error,Select SPISCS[1] for injecting error,?,?,?,?,?,Select SPISCS[7] for injecting error"
newline
bitfld.long 0x14 2. "CTRLSCSPINERR,Control bit to enable the injection of an error on SPISCS[7:0] pins" "Disable the error inducing logic,Enable the error inducing logic to the SPISCS pins"
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bitfld.long 0x14 1. "LPBKTYPE,Module IO Loopback Type (Analog/Digital)" "Digital loopback is enabled in module I/O DFT..,Analog loopback is enabled in module I/O DFT.."
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bitfld.long 0x14 0. "RXPENA,Module Analog loopback through Receive Pin Enable" "Analog loopback through transmit pin,Analog loopback through receive pin"
line.long 0x18 "EXTENDED_PRESCALE1,SPI/MibSPI Extended Prescale Register 1 (EXTENDED_PRESCALE1 for SPIFMT0 and SPIFMT1) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x18 27.--31. "NU2,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x18 16.--26. 1. "EPRESCLAE_FMT1,Extended Prescale value for SPIFMT1"
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rbitfld.long 0x18 11.--15. "NU1,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.word 0x18 0.--10. 1. "EPRESCLAE_FMT0,EPRESCALE_FMT0 can be modified in privilege mode only"
line.long 0x1C "EXTENDED_PRESCALE2,SPI/MibSPI Extended Prescale Register 2 (EXTENDED_PRESCALE2 for SPIFMT2 and SPIFMT3) This register provides an extended Prescale values for SPICLK generation to be able to interface with much slower SPI Slaves"
rbitfld.long 0x1C 27.--31. "NU4,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 16.--26. 1. "EPRESCLAE_FMT3,EPRESCALE_FMT3 can be modified in privilege mode only"
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rbitfld.long 0x1C 11.--15. "NU3,Reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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hexmask.long.word 0x1C 0.--10. 1. "EPRESCLAE_FMT2,EPRESCALE_FMT2 can be modified in privilege mode only"
line.long 0x20 "ECCDIAG_CTRL,ECC Diagnostic Control register"
hexmask.long 0x20 4.--31. 1. "NU,Reserved"
newline
bitfld.long 0x20 0.--3. "ECCDIAG_EN,ECC Diagnostic mode Enable Key bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x24 "ECCDIAG_STAT,ECC Diagnostic Status register"
hexmask.long.word 0x24 18.--31. 1. "NU2,Reserved"
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bitfld.long 0x24 17. "DEFLG1,Double bit error flag for RXRAM" "No error,A double bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 16. "DEFLG0,Double bit error flag for TXRAM" "No error,A double bit Error is detected for TXRAM bank.."
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hexmask.long.word 0x24 2.--15. 1. "NU1,Reserved"
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bitfld.long 0x24 1. "SEFLG1,Single bit error flag for RXRAM" "No error,A Single bit Error is detected for RXRAM bank.."
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bitfld.long 0x24 0. "SEFLG0,Single bit error flag for TXRAM" "No error,A Single bit Error is detected for TXRAM bank.."
line.long 0x28 "SBERRADDR1,Single Bit Error Address Register - RXRAM"
hexmask.long.tbyte 0x28 11.--31. 1. "NU1,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x28 0.--10. 1. "SBERRADDR1,Single Bit ECC Error Address This register holds the address of the RAM location when a single bit error is generated by SECDED block while reading the MibSPI (Receive) RXRAM"
line.long 0x2C "SBERRADDR0,Single Bit ECC Error Address Register - TXRAM"
hexmask.long.tbyte 0x2C 11.--31. 1. "NU2,Reserved.Reads return '0' and writes have no effect"
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hexmask.long.word 0x2C 0.--10. 1. "SBERRADDR0,Single Bit ECC Error Address This register holds the address when a single bit error is generated from SECDED block while reading the MibSPI (Transmit) TXRAM"
rgroup.long 0x1FC++0x03
line.long 0x00 "SPIREV,SPI / MibSPI Revision ID Register"
bitfld.long 0x00 30.--31. "SCHEME,Identification Scheme Used to distinguish different ID schemes" "0,1,2,3"
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bitfld.long 0x00 28.--29. "NU,Reserved.Reads return '0' and writes have no effect" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Indicates functionally equivalent module family Reads 0xA05"
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bitfld.long 0x00 11.--15. "RTL,RTL version number Read value will provide an approximate RTL revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision number Reads 0x3" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "CUSTOM,Indicates device specific implementation Reads 0x0" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision number Reads 0x8" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat 4. (list 0. 1. 3. 4. )(list 0x00 0x04 0x0C 0x10 )
group.long ($2+0xF8)++0x03
line.long 0x00 "ICOUNT$1,MibSPI DMAxCOUNT"
hexmask.long.word 0x00 16.--31. 1. "ICOUNT,Initial Number of DMA transfers"
hexmask.long.word 0x00 0.--15. 1. "COUNT,Actual number of remaining DMA transfer COUNTx is a read-only bit field"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x50)++0x03
line.long 0x00 "SPIFMT$1,SPI / MibSPI Data Format Register 0"
hexmask.long.byte 0x00 24.--31. 1. "WDELAY,Delay in between transmissions for data format x (x= 0 1 2 3)"
bitfld.long 0x00 23. "PARPOL,Parity polarity: even or odd" "An even parity flag is added at the end of the..,An odd parity flag is added at the end of the.."
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bitfld.long 0x00 22. "PARITYENA,Parity enable for data format x" "No parity generation/ verification is performed..,A parity is transmitted at the end of each.."
bitfld.long 0x00 21. "WAITENA,Master waits for ENA signal from slave for data format x" "The SPI / MibSPI does not wait for the ENA..,Before the SPI / MibSPI starts the data transfer.."
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bitfld.long 0x00 20. "SHIFTDIR,Shift direction for data format x" "Data format x shift direction,Data format x shift direction"
bitfld.long 0x00 19. "HDUPLEX_ENA,Half Duplex transfer mode enable for Data Format x" "Normal Full Duplex transfer,If MASTER = '1' SIMO pin will act as an RX pin.."
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bitfld.long 0x00 18. "DISCSTIMERS,Disable Chipselect Timers for this format register" "Both C2TDELAY & T2CDELAY counts are inserted for..,No C2TDELAY or T2CDELAY is inserted in the.."
bitfld.long 0x00 17. "POLARITY,SPI data format x clock polarity" "If POLARITYx is set to '0' the SPI clock signal..,If POLARITYx is set to '1' the SPI clock signal.."
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bitfld.long 0x00 16. "PHASE,SPI Data format x clock delay" "If PHASEx is set to '0' the SPI clock signal is..,If PHASEx is set to '1' the SPI clock signal is.."
hexmask.long.byte 0x00 8.--15. 1. "PRESCALE,SPI data format x prescaler"
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rbitfld.long 0x00 5.--7. "NU,Reserved" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "CHARLEN,SPI data format x data word length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
repeat.end
width 0x0B
tree.end
tree "RCSS_TPCC_A (RCSS TPCCA Module Registers)"
base ad:0x5100000
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
bitfld.long 0x00 28.--29. "RES1,RESERVE FIELD" "0,1,2,3"
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hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
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bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "CCCFG,CC Configuration Register"
bitfld.long 0x04 26.--31. "RES2,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x04 25. "MPEXIST,Memory Protection Existence MPEXIST =" "No memory protection,Memory Protection logic included"
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bitfld.long 0x04 24. "CHMAPEXIST,Channel Mapping Existence CHMAPEXIST =" "No Channel mapping,Channel mapping logic included"
bitfld.long 0x04 22.--23. "RES3,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x04 20.--21. "NUMREGN,Number of MP and Shadow regions" "0,1,2,3"
bitfld.long 0x04 19. "RES4,RESERVE FIELD" "0,1"
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bitfld.long 0x04 16.--18. "NUMTC,Number of Queues/Number of TCs" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 15. "RES5,RESERVE FIELD" "0,1"
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bitfld.long 0x04 12.--14. "NUMPAENTRY,Number of PaRAM entries" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 11. "RES6,RESERVE FIELD" "0,1"
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bitfld.long 0x04 8.--10. "NUMINTCH,Number of Interrupt Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 7. "RES7,RESERVE FIELD" "0,1"
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bitfld.long 0x04 4.--6. "NUMQDMACH,Number of QDMA Channels" "0,1,2,3,4,5,6,7"
bitfld.long 0x04 3. "RES8,RESERVE FIELD" "0,1"
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bitfld.long 0x04 0.--2. "NUMDMACH,Number of DMA Channels" "0,1,2,3,4,5,6,7"
group.long 0x200++0x03
line.long 0x00 "QCHMAPN,QDMA Channel N Mapping Register"
hexmask.long.tbyte 0x00 14.--31. 1. "RES10,RESERVE FIELD"
hexmask.long.word 0x00 5.--13. 1. "PAENTRY,PaRAM Entry number for QDMA Channel N"
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bitfld.long 0x00 2.--4. "TRWORD,TRWORD points to the specific trigger word of the PaRAM Entry defined by PAENTRY" "0,1,2,3,4,5,6,7"
group.long 0x240++0x03
line.long 0x00 "DMAQNUMN,DMA Queue Number Register n Contains the Event queue number to be used for the corresponding DMA Channel"
rbitfld.long 0x00 31. "RES11,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,DMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "RES12,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,DMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 23. "RES13,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,DMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 19. "RES14,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,DMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 15. "RES15,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,DMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 11. "RES16,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,DMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES17,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,DMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "RES18,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,DMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x260++0x03
line.long 0x00 "QDMAQNUM,QDMA Queue Number Register Contains the Event queue number to be used for the corresponding QDMA Channel"
rbitfld.long 0x00 31. "RES19,RESERVE FIELD" "0,1"
bitfld.long 0x00 28.--30. "E7,QDMA Queue Number for event #7" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 27. "RES20,RESERVE FIELD" "0,1"
bitfld.long 0x00 24.--26. "E6,QDMA Queue Number for event #6" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 23. "RES21,RESERVE FIELD" "0,1"
bitfld.long 0x00 20.--22. "E5,QDMA Queue Number for event #5" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 19. "RES22,RESERVE FIELD" "0,1"
bitfld.long 0x00 16.--18. "E4,QDMA Queue Number for event #4" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 15. "RES23,RESERVE FIELD" "0,1"
bitfld.long 0x00 12.--14. "E3,QDMA Queue Number for event #3" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 11. "RES24,RESERVE FIELD" "0,1"
bitfld.long 0x00 8.--10. "E2,QDMA Queue Number for event #2" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 7. "RES25,RESERVE FIELD" "0,1"
bitfld.long 0x00 4.--6. "E1,QDMA Queue Number for event #1" "0,1,2,3,4,5,6,7"
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rbitfld.long 0x00 3. "RES26,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "E0,QDMA Queue Number for event #0" "0,1,2,3,4,5,6,7"
group.long 0x280++0x07
line.long 0x00 "QUETCMAP,Queue to TC Mapping"
hexmask.long 0x00 7.--31. 1. "RES27,RESERVE FIELD"
bitfld.long 0x00 4.--6. "TCNUMQ1,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x00 3. "RES28,RESERVE FIELD" "0,1"
bitfld.long 0x00 0.--2. "TCNUMQ0,TC Number for Queue N: Defines the TC number that Event Queue N TRs are written to" "0,1,2,3,4,5,6,7"
line.long 0x04 "QUEPRI,Queue Priority"
hexmask.long 0x04 7.--31. 1. "RES29,RESERVE FIELD"
bitfld.long 0x04 4.--6. "PRIQ1,Priority Level for Queue 1 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
newline
rbitfld.long 0x04 3. "RES30,RESERVE FIELD" "0,1"
bitfld.long 0x04 0.--2. "PRIQ0,Priority Level for Queue 0 Dictates the priority level used for the OPTIONS field programmation for Qn TRs" "0,1,2,3,4,5,6,7"
rgroup.long 0x300++0x23
line.long 0x00 "EMR,Event Missed Register: The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x00 31. "E31,Event Missed #31" "0,1"
bitfld.long 0x00 30. "E30,Event Missed #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event Missed #29" "0,1"
bitfld.long 0x00 28. "E28,Event Missed #28" "0,1"
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bitfld.long 0x00 27. "E27,Event Missed #27" "0,1"
bitfld.long 0x00 26. "E26,Event Missed #26" "0,1"
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bitfld.long 0x00 25. "E25,Event Missed #25" "0,1"
bitfld.long 0x00 24. "E24,Event Missed #24" "0,1"
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bitfld.long 0x00 23. "E23,Event Missed #23" "0,1"
bitfld.long 0x00 22. "E22,Event Missed #22" "0,1"
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bitfld.long 0x00 21. "E21,Event Missed #21" "0,1"
bitfld.long 0x00 20. "E20,Event Missed #20" "0,1"
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bitfld.long 0x00 19. "E19,Event Missed #19" "0,1"
bitfld.long 0x00 18. "E18,Event Missed #18" "0,1"
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bitfld.long 0x00 17. "E17,Event Missed #17" "0,1"
bitfld.long 0x00 16. "E16,Event Missed #16" "0,1"
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bitfld.long 0x00 15. "E15,Event Missed #15" "0,1"
bitfld.long 0x00 14. "E14,Event Missed #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event Missed #13" "0,1"
bitfld.long 0x00 12. "E12,Event Missed #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event Missed #11" "0,1"
bitfld.long 0x00 10. "E10,Event Missed #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event Missed #9" "0,1"
bitfld.long 0x00 8. "E8,Event Missed #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event Missed #7" "0,1"
bitfld.long 0x00 6. "E6,Event Missed #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event Missed #5" "0,1"
bitfld.long 0x00 4. "E4,Event Missed #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event Missed #3" "0,1"
bitfld.long 0x00 2. "E2,Event Missed #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event Missed #1" "0,1"
bitfld.long 0x00 0. "E0,Event Missed #0" "0,1"
line.long 0x04 "EMRH,Event Missed Register (High Part): The Event Missed register is set if 2 events are received without the first event being cleared or if a Null TR is serviced"
bitfld.long 0x04 31. "E63,Event Missed #63" "0,1"
bitfld.long 0x04 30. "E62,Event Missed #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event Missed #61" "0,1"
bitfld.long 0x04 28. "E60,Event Missed #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event Missed #59" "0,1"
bitfld.long 0x04 26. "E58,Event Missed #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event Missed #57" "0,1"
bitfld.long 0x04 24. "E56,Event Missed #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event Missed #55" "0,1"
bitfld.long 0x04 22. "E54,Event Missed #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event Missed #53" "0,1"
bitfld.long 0x04 20. "E52,Event Missed #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event Missed #51" "0,1"
bitfld.long 0x04 18. "E50,Event Missed #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event Missed #49" "0,1"
bitfld.long 0x04 16. "E48,Event Missed #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event Missed #47" "0,1"
bitfld.long 0x04 14. "E46,Event Missed #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event Missed #45" "0,1"
bitfld.long 0x04 12. "E44,Event Missed #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event Missed #43" "0,1"
bitfld.long 0x04 10. "E42,Event Missed #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event Missed #41" "0,1"
bitfld.long 0x04 8. "E40,Event Missed #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event Missed #39" "0,1"
bitfld.long 0x04 6. "E38,Event Missed #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event Missed #37" "0,1"
bitfld.long 0x04 4. "E36,Event Missed #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event Missed #35" "0,1"
bitfld.long 0x04 2. "E34,Event Missed #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event Missed #33" "0,1"
bitfld.long 0x04 0. "E32,Event Missed #32" "0,1"
line.long 0x08 "EMCR,Event Missed Clear Register: CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event Missed Clear #31" "0,1"
bitfld.long 0x08 30. "E30,Event Missed Clear #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event Missed Clear #29" "0,1"
bitfld.long 0x08 28. "E28,Event Missed Clear #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event Missed Clear #27" "0,1"
bitfld.long 0x08 26. "E26,Event Missed Clear #26" "0,1"
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bitfld.long 0x08 25. "E25,Event Missed Clear #25" "0,1"
bitfld.long 0x08 24. "E24,Event Missed Clear #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event Missed Clear #23" "0,1"
bitfld.long 0x08 22. "E22,Event Missed Clear #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event Missed Clear #21" "0,1"
bitfld.long 0x08 20. "E20,Event Missed Clear #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event Missed Clear #19" "0,1"
bitfld.long 0x08 18. "E18,Event Missed Clear #18" "0,1"
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bitfld.long 0x08 17. "E17,Event Missed Clear #17" "0,1"
bitfld.long 0x08 16. "E16,Event Missed Clear #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event Missed Clear #15" "0,1"
bitfld.long 0x08 14. "E14,Event Missed Clear #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event Missed Clear #13" "0,1"
bitfld.long 0x08 12. "E12,Event Missed Clear #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event Missed Clear #11" "0,1"
bitfld.long 0x08 10. "E10,Event Missed Clear #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event Missed Clear #9" "0,1"
bitfld.long 0x08 8. "E8,Event Missed Clear #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event Missed Clear #7" "0,1"
bitfld.long 0x08 6. "E6,Event Missed Clear #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event Missed Clear #5" "0,1"
bitfld.long 0x08 4. "E4,Event Missed Clear #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event Missed Clear #3" "0,1"
bitfld.long 0x08 2. "E2,Event Missed Clear #2" "0,1"
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bitfld.long 0x08 1. "E1,Event Missed Clear #1" "0,1"
bitfld.long 0x08 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x0C "EMCRH,Event Missed Clear Register (High Part): CPU write of '1' to the EMCR.En bit causes the EMR.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event Missed Clear #63" "0,1"
bitfld.long 0x0C 30. "E62,Event Missed Clear #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event Missed Clear #61" "0,1"
bitfld.long 0x0C 28. "E60,Event Missed Clear #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event Missed Clear #59" "0,1"
bitfld.long 0x0C 26. "E58,Event Missed Clear #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event Missed Clear #57" "0,1"
bitfld.long 0x0C 24. "E56,Event Missed Clear #56" "0,1"
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bitfld.long 0x0C 23. "E55,Event Missed Clear #55" "0,1"
bitfld.long 0x0C 22. "E54,Event Missed Clear #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event Missed Clear #53" "0,1"
bitfld.long 0x0C 20. "E52,Event Missed Clear #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event Missed Clear #51" "0,1"
bitfld.long 0x0C 18. "E50,Event Missed Clear #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event Missed Clear #49" "0,1"
bitfld.long 0x0C 16. "E48,Event Missed Clear #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event Missed Clear #47" "0,1"
bitfld.long 0x0C 14. "E46,Event Missed Clear #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event Missed Clear #45" "0,1"
bitfld.long 0x0C 12. "E44,Event Missed Clear #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event Missed Clear #43" "0,1"
bitfld.long 0x0C 10. "E42,Event Missed Clear #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event Missed Clear #41" "0,1"
bitfld.long 0x0C 8. "E40,Event Missed Clear #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event Missed Clear #39" "0,1"
bitfld.long 0x0C 6. "E38,Event Missed Clear #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event Missed Clear #37" "0,1"
bitfld.long 0x0C 4. "E36,Event Missed Clear #36" "0,1"
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bitfld.long 0x0C 3. "E35,Event Missed Clear #35" "0,1"
bitfld.long 0x0C 2. "E34,Event Missed Clear #34" "0,1"
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bitfld.long 0x0C 1. "E33,Event Missed Clear #33" "0,1"
bitfld.long 0x0C 0. "E32,Event Missed Clear #32" "0,1"
line.long 0x10 "QEMR,QDMA Event Missed Register: The QDMA Event Missed register is set if 2 QDMA events are detected without the first event being cleared or if a Null TR is serviced"
hexmask.long.tbyte 0x10 8.--31. 1. "RES31,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event Missed #7" "0,1"
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bitfld.long 0x10 6. "E6,Event Missed #6" "0,1"
bitfld.long 0x10 5. "E5,Event Missed #5" "0,1"
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bitfld.long 0x10 4. "E4,Event Missed #4" "0,1"
bitfld.long 0x10 3. "E3,Event Missed #3" "0,1"
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bitfld.long 0x10 2. "E2,Event Missed #2" "0,1"
bitfld.long 0x10 1. "E1,Event Missed #1" "0,1"
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bitfld.long 0x10 0. "E0,Event Missed #0" "0,1"
line.long 0x14 "QEMCR,QDMA Event Missed Clear Register: CPU write of '1' to the QEMCR.En bit causes the QEMR.En bit to be cleared"
hexmask.long.tbyte 0x14 8.--31. 1. "RES32,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event Missed Clear #7" "0,1"
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bitfld.long 0x14 6. "E6,Event Missed Clear #6" "0,1"
bitfld.long 0x14 5. "E5,Event Missed Clear #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event Missed Clear #4" "0,1"
bitfld.long 0x14 3. "E3,Event Missed Clear #3" "0,1"
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bitfld.long 0x14 2. "E2,Event Missed Clear #2" "0,1"
bitfld.long 0x14 1. "E1,Event Missed Clear #1" "0,1"
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bitfld.long 0x14 0. "E0,Event Missed Clear #0" "0,1"
line.long 0x18 "CCERR,CC Error Register"
hexmask.long.word 0x18 17.--31. 1. "RES33,RESERVE FIELD"
bitfld.long 0x18 16. "TCERR,Transfer Completion Code Error: TCCERR =" "Total number of allowed TCCs outstanding has not..,Total number of allowed TCCs has been reached"
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hexmask.long.byte 0x18 8.--15. 1. "RES34,RESERVE FIELD"
bitfld.long 0x18 7. "QTHRXCD7,Queue Threshold Error for Q7: QTHRXCD7 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 6. "QTHRXCD6,Queue Threshold Error for Q6: QTHRXCD6 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 5. "QTHRXCD5,Queue Threshold Error for Q5: QTHRXCD5 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 4. "QTHRXCD4,Queue Threshold Error for Q4: QTHRXCD4 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 3. "QTHRXCD3,Queue Threshold Error for Q3: QTHRXCD3 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 2. "QTHRXCD2,Queue Threshold Error for Q2: QTHRXCD2 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
bitfld.long 0x18 1. "QTHRXCD1,Queue Threshold Error for Q1: QTHRXCD1 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
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bitfld.long 0x18 0. "QTHRXCD0,Queue Threshold Error for Q0: QTHRXCD0 =" "Watermark/threshold has not been exceeded,Watermark/threshold has been exceeded"
line.long 0x1C "CCERRCLR,CC Error Clear Register"
hexmask.long.word 0x1C 17.--31. 1. "RES35,RESERVE FIELD"
bitfld.long 0x1C 16. "TCERR,Clear Error for CCERR.TCERR: Write of '1' clears the value of CCERR bit N" "0,1"
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hexmask.long.byte 0x1C 8.--15. 1. "RES36,RESERVE FIELD"
bitfld.long 0x1C 7. "QTHRXCD7,Clear error for CCERR.QTHRXCD7: Write of '1' clears the values of QSTAT7.WM QSTAT7.THRXCD CCERR.QTHRXCD7 Writes of '0' have no affect" "0,1"
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bitfld.long 0x1C 6. "QTHRXCD6,Clear error for CCERR.QTHRXCD6: Write of '1' clears the values of QSTAT6.WM QSTAT6.THRXCD CCERR.QTHRXCD6 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 5. "QTHRXCD5,Clear error for CCERR.QTHRXCD5: Write of '1' clears the values of QSTAT5.WM QSTAT5.THRXCD CCERR.QTHRXCD5 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 4. "QTHRXCD4,Clear error for CCERR.QTHRXCD4: Write of '1' clears the values of QSTAT4.WM QSTAT4.THRXCD CCERR.QTHRXCD4 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 3. "QTHRXCD3,Clear error for CCERR.QTHRXCD3: Write of '1' clears the values of QSTAT3.WM QSTAT3.THRXCD CCERR.QTHRXCD3 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 2. "QTHRXCD2,Clear error for CCERR.QTHRXCD2: Write of '1' clears the values of QSTAT2.WM QSTAT2.THRXCD CCERR.QTHRXCD2 Writes of '0' have no affect" "0,1"
bitfld.long 0x1C 1. "QTHRXCD1,Clear error for CCERR.QTHRXCD1: Write of '1' clears the values of QSTAT1.WM QSTAT1.THRXCD CCERR.QTHRXCD1 Writes of '0' have no affect" "0,1"
newline
bitfld.long 0x1C 0. "QTHRXCD0,Clear error for CCERR.QTHRXCD0: Write of '1' clears the values of QSTAT0.WM QSTAT0.THRXCD CCERR.QTHRXCD0 Writes of '0' have no affect" "0,1"
line.long 0x20 "EEVAL,Error Eval Register"
hexmask.long 0x20 2.--31. 1. "RES37,RESERVE FIELD"
bitfld.long 0x20 1. "SET,Error Interrupt Set: CPU write of '1' to the SET bit causes the TPCC error interrupt to be pulsed regardless of state of EMR/EMRH QEMR or CCERR" "0,1"
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bitfld.long 0x20 0. "EVAL,Error Interrupt Evaluate: CPU write of '1' to the EVAL bit causes the TPCC error interrupt to be pulsed if any errors have not been cleared in the EMR/EMRH QEMR or CCERR registers" "0,1"
group.long 0x340++0x07
line.long 0x00 "DRAEM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x00 31. "E31,DMA Region Access enable for Region M bit #31" "0,1"
bitfld.long 0x00 30. "E30,DMA Region Access enable for Region M bit #30" "0,1"
newline
bitfld.long 0x00 29. "E29,DMA Region Access enable for Region M bit #29" "0,1"
bitfld.long 0x00 28. "E28,DMA Region Access enable for Region M bit #28" "0,1"
newline
bitfld.long 0x00 27. "E27,DMA Region Access enable for Region M bit #27" "0,1"
bitfld.long 0x00 26. "E26,DMA Region Access enable for Region M bit #26" "0,1"
newline
bitfld.long 0x00 25. "E25,DMA Region Access enable for Region M bit #25" "0,1"
bitfld.long 0x00 24. "E24,DMA Region Access enable for Region M bit #24" "0,1"
newline
bitfld.long 0x00 23. "E23,DMA Region Access enable for Region M bit #23" "0,1"
bitfld.long 0x00 22. "E22,DMA Region Access enable for Region M bit #22" "0,1"
newline
bitfld.long 0x00 21. "E21,DMA Region Access enable for Region M bit #21" "0,1"
bitfld.long 0x00 20. "E20,DMA Region Access enable for Region M bit #20" "0,1"
newline
bitfld.long 0x00 19. "E19,DMA Region Access enable for Region M bit #19" "0,1"
bitfld.long 0x00 18. "E18,DMA Region Access enable for Region M bit #18" "0,1"
newline
bitfld.long 0x00 17. "E17,DMA Region Access enable for Region M bit #17" "0,1"
bitfld.long 0x00 16. "E16,DMA Region Access enable for Region M bit #16" "0,1"
newline
bitfld.long 0x00 15. "E15,DMA Region Access enable for Region M bit #15" "0,1"
bitfld.long 0x00 14. "E14,DMA Region Access enable for Region M bit #14" "0,1"
newline
bitfld.long 0x00 13. "E13,DMA Region Access enable for Region M bit #13" "0,1"
bitfld.long 0x00 12. "E12,DMA Region Access enable for Region M bit #12" "0,1"
newline
bitfld.long 0x00 11. "E11,DMA Region Access enable for Region M bit #11" "0,1"
bitfld.long 0x00 10. "E10,DMA Region Access enable for Region M bit #10" "0,1"
newline
bitfld.long 0x00 9. "E9,DMA Region Access enable for Region M bit #9" "0,1"
bitfld.long 0x00 8. "E8,DMA Region Access enable for Region M bit #8" "0,1"
newline
bitfld.long 0x00 7. "E7,DMA Region Access enable for Region M bit #7" "0,1"
bitfld.long 0x00 6. "E6,DMA Region Access enable for Region M bit #6" "0,1"
newline
bitfld.long 0x00 5. "E5,DMA Region Access enable for Region M bit #5" "0,1"
bitfld.long 0x00 4. "E4,DMA Region Access enable for Region M bit #4" "0,1"
newline
bitfld.long 0x00 3. "E3,DMA Region Access enable for Region M bit #3" "0,1"
bitfld.long 0x00 2. "E2,DMA Region Access enable for Region M bit #2" "0,1"
newline
bitfld.long 0x00 1. "E1,DMA Region Access enable for Region M bit #1" "0,1"
bitfld.long 0x00 0. "E0,DMA Region Access enable for Region M bit #0" "0,1"
line.long 0x04 "DRAEHM,DMA Region Access enable for bit N in Region M: En ="
bitfld.long 0x04 31. "E63,DMA Region Access enable for Region M bit #63" "0,1"
bitfld.long 0x04 30. "E62,DMA Region Access enable for Region M bit #62" "0,1"
newline
bitfld.long 0x04 29. "E61,DMA Region Access enable for Region M bit #61" "0,1"
bitfld.long 0x04 28. "E60,DMA Region Access enable for Region M bit #60" "0,1"
newline
bitfld.long 0x04 27. "E59,DMA Region Access enable for Region M bit #59" "0,1"
bitfld.long 0x04 26. "E58,DMA Region Access enable for Region M bit #58" "0,1"
newline
bitfld.long 0x04 25. "E57,DMA Region Access enable for Region M bit #57" "0,1"
bitfld.long 0x04 24. "E56,DMA Region Access enable for Region M bit #56" "0,1"
newline
bitfld.long 0x04 23. "E55,DMA Region Access enable for Region M bit #55" "0,1"
bitfld.long 0x04 22. "E54,DMA Region Access enable for Region M bit #54" "0,1"
newline
bitfld.long 0x04 21. "E53,DMA Region Access enable for Region M bit #53" "0,1"
bitfld.long 0x04 20. "E52,DMA Region Access enable for Region M bit #52" "0,1"
newline
bitfld.long 0x04 19. "E51,DMA Region Access enable for Region M bit #51" "0,1"
bitfld.long 0x04 18. "E50,DMA Region Access enable for Region M bit #50" "0,1"
newline
bitfld.long 0x04 17. "E49,DMA Region Access enable for Region M bit #49" "0,1"
bitfld.long 0x04 16. "E48,DMA Region Access enable for Region M bit #48" "0,1"
newline
bitfld.long 0x04 15. "E47,DMA Region Access enable for Region M bit #47" "0,1"
bitfld.long 0x04 14. "E46,DMA Region Access enable for Region M bit #46" "0,1"
newline
bitfld.long 0x04 13. "E45,DMA Region Access enable for Region M bit #45" "0,1"
bitfld.long 0x04 12. "E44,DMA Region Access enable for Region M bit #44" "0,1"
newline
bitfld.long 0x04 11. "E43,DMA Region Access enable for Region M bit #43" "0,1"
bitfld.long 0x04 10. "E42,DMA Region Access enable for Region M bit #42" "0,1"
newline
bitfld.long 0x04 9. "E41,DMA Region Access enable for Region M bit #41" "0,1"
bitfld.long 0x04 8. "E40,DMA Region Access enable for Region M bit #40" "0,1"
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bitfld.long 0x04 7. "E39,DMA Region Access enable for Region M bit #39" "0,1"
bitfld.long 0x04 6. "E38,DMA Region Access enable for Region M bit #38" "0,1"
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bitfld.long 0x04 5. "E37,DMA Region Access enable for Region M bit #37" "0,1"
bitfld.long 0x04 4. "E36,DMA Region Access enable for Region M bit #36" "0,1"
newline
bitfld.long 0x04 3. "E35,DMA Region Access enable for Region M bit #35" "0,1"
bitfld.long 0x04 2. "E34,DMA Region Access enable for Region M bit #34" "0,1"
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bitfld.long 0x04 1. "E33,DMA Region Access enable for Region M bit #33" "0,1"
bitfld.long 0x04 0. "E32,DMA Region Access enable for Region M bit #32" "0,1"
group.long 0x380++0x03
line.long 0x00 "QRAEN,QDMA Region Access enable for bit N in Region M: En ="
hexmask.long.tbyte 0x00 8.--31. 1. "RES38,RESERVE FIELD"
bitfld.long 0x00 7. "E7,QDMA Region Access enable for Region M bit #7" "0,1"
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bitfld.long 0x00 6. "E6,QDMA Region Access enable for Region M bit #6" "0,1"
bitfld.long 0x00 5. "E5,QDMA Region Access enable for Region M bit #5" "0,1"
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bitfld.long 0x00 4. "E4,QDMA Region Access enable for Region M bit #4" "0,1"
bitfld.long 0x00 3. "E3,QDMA Region Access enable for Region M bit #3" "0,1"
newline
bitfld.long 0x00 2. "E2,QDMA Region Access enable for Region M bit #2" "0,1"
bitfld.long 0x00 1. "E1,QDMA Region Access enable for Region M bit #1" "0,1"
newline
bitfld.long 0x00 0. "E0,QDMA Region Access enable for Region M bit #0" "0,1"
rgroup.long 0x600++0x03
line.long 0x00 "QSTATN,QSTATn Register Set"
hexmask.long.byte 0x00 25.--31. 1. "RES55,RESERVE FIELD"
bitfld.long 0x00 24. "THRXCD,Threshold Exceeded: THRXCD =" "Threshold specified by QWMTHR(A B).Qn has not..,Threshold specified by QWMTHR(A B).Qn has been.."
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bitfld.long 0x00 21.--23. "RES56,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 16.--20. "WM,Watermark for Maximum Queue Usage: Watermark tracks the most entries that have been in QueueN since reset or since the last time that the watermark (WM) was cleared" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 13.--15. "RES57,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 8.--12. "NUMVAL,Number of Valid Entries in QueueN: Represents the total number of entries residing in the Queue Manager FIFO at a given instant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 4.--7. "RES58,RESERVE FIELD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 0.--3. "STRTPTR,Start Pointer: Represents the offset to the head entry of QueueN in units of entries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x620++0x03
line.long 0x00 "QWMTHRA,Queue Threshold A for Q[3:0]: CCERR.QTHRXCDn and QSTATn.THRXCD error bit is set when the number of Events in QueueN at an instant in time (visible via QSTATn.NUMVAL) equals or exceeds the value specified by QWMTHRA.Qn"
hexmask.long.tbyte 0x00 13.--31. 1. "RES59,RESERVE FIELD"
bitfld.long 0x00 8.--12. "Q1,Queue Threshold for Q1 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
rbitfld.long 0x00 5.--7. "RES60,RESERVE FIELD" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 0.--4. "Q0,Queue Threshold for Q0 value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
rgroup.long 0x640++0x03
line.long 0x00 "CCSTAT,CC Status Register"
hexmask.long.byte 0x00 24.--31. 1. "RES61,RESERVE FIELD"
bitfld.long 0x00 23. "QUEACTV7,Queue 7 Active QUEACTV7 =" "No Evts are queued in Q7,At least one TR is queued in Q7"
newline
bitfld.long 0x00 22. "QUEACTV6,Queue 6 Active QUEACTV6 =" "No Evts are queued in Q6,At least one TR is queued in Q6"
bitfld.long 0x00 21. "QUEACTV5,Queue 5 Active QUEACTV5 =" "No Evts are queued in Q5,At least one TR is queued in Q5"
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bitfld.long 0x00 20. "QUEACTV4,Queue 4 Active QUEACTV4 =" "No Evts are queued in Q4,At least one TR is queued in Q4"
bitfld.long 0x00 19. "QUEACTV3,Queue 3 Active QUEACTV3 =" "No Evts are queued in Q3,At least one TR is queued in Q3"
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bitfld.long 0x00 18. "QUEACTV2,Queue 2 Active QUEACTV2 =" "No Evts are queued in Q2,At least one TR is queued in Q2"
bitfld.long 0x00 17. "QUEACTV1,Queue 1 Active QUEACTV1 =" "No Evts are queued in Q1,At least one TR is queued in Q1"
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bitfld.long 0x00 16. "QUEACTV0,Queue 0 Active QUEACTV0 =" "No Evts are queued in Q0,At least one TR is queued in Q0"
bitfld.long 0x00 14.--15. "RES62,RESERVE FIELD" "0,1,2,3"
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bitfld.long 0x00 8.--13. "COMPACTV,Completion Request Active: Counter that tracks the total number of completion requests submitted to the TC" "No completion requests outstanding,Total of '1' completion request outstanding,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Total of 63 completion requests are outstanding"
bitfld.long 0x00 5.--7. "RES63,RESERVE FIELD" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 4. "ACTV,Channel Controller Active: Channel Controller Active is a logical-OR of each of the ACTV signals" "Channel is idle,Channel is busy"
bitfld.long 0x00 3. "RES64,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 2. "TRACTV,Transfer Request Active: TRACTV =" "Transfer Request processing/submission logic is..,Transfer Request processing/submission logic is.."
bitfld.long 0x00 1. "QEVTACTV,QDMA Event Active: QEVTACTV =" "No enabled QDMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
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bitfld.long 0x00 0. "EVTACTV,DMA Event Active: EVTACTV =" "No enabled DMA Events are active within the CC,At least one enabled DMA Event (ER & EER ESR.."
group.long 0x700++0x0B
line.long 0x00 "AETCTL,Advanced Event Trigger Control"
bitfld.long 0x00 31. "EN,AET Enable: EN =" "AET event generation is disabled,AET event generation is enabled"
hexmask.long.tbyte 0x00 14.--30. 1. "RES65,RESERVE FIELD"
newline
bitfld.long 0x00 8.--13. "ENDINT,AET End Interrupt: Dictates the completion interrupt number that will force the tpcc_aet signal to be deasserted (low)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
rbitfld.long 0x00 7. "RES66,RESERVE FIELD" "0,1"
newline
bitfld.long 0x00 6. "TYPE,AET Event Type: TYPE =" "Event specified by STARTEVT applies to DMA..,Event specified by STARTEVT applies to QDMA Events"
bitfld.long 0x00 0.--5. "STRTEVT,AET Start Event: Dictates the Event Number that will force the tpcc_aet signal to be asserted (high)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "AETSTAT,Advanced Event Trigger Stat"
hexmask.long 0x04 1.--31. 1. "RES67,RESERVE FIELD"
bitfld.long 0x04 0. "STAT,AET Status: AETSTAT =" "tpcc_aet is currently low,tpcc_aet is currently high"
line.long 0x08 "AETCMD,AET Command"
hexmask.long 0x08 1.--31. 1. "RES68,RESERVE FIELD"
bitfld.long 0x08 0. "CLR,AET Clear command: CPU write of '1' to the CLR bit causes the tpcc_aet output signal and AETSTAT.STAT register to be cleared" "0,1"
rgroup.long 0x1000++0x47
line.long 0x00 "ER,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
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bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
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bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
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bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x1050++0x2B
line.long 0x00 "IER,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES69,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x1080++0x17
line.long 0x00 "QER,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES70,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES71,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES72,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES73,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES74,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES75,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
rgroup.long 0x2000++0x47
line.long 0x00 "ER_RN,Event Register: If ER.En bit is set and the EER.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x00 31. "E31,Event #31" "0,1"
bitfld.long 0x00 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x00 29. "E29,Event #29" "0,1"
bitfld.long 0x00 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x00 27. "E27,Event #27" "0,1"
bitfld.long 0x00 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x00 25. "E25,Event #25" "0,1"
bitfld.long 0x00 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x00 23. "E23,Event #23" "0,1"
bitfld.long 0x00 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x00 21. "E21,Event #21" "0,1"
bitfld.long 0x00 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x00 19. "E19,Event #19" "0,1"
bitfld.long 0x00 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x00 17. "E17,Event #17" "0,1"
bitfld.long 0x00 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x00 15. "E15,Event #15" "0,1"
bitfld.long 0x00 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x00 13. "E13,Event #13" "0,1"
bitfld.long 0x00 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x00 11. "E11,Event #11" "0,1"
bitfld.long 0x00 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x00 9. "E9,Event #9" "0,1"
bitfld.long 0x00 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x00 7. "E7,Event #7" "0,1"
bitfld.long 0x00 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x00 5. "E5,Event #5" "0,1"
bitfld.long 0x00 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x00 3. "E3,Event #3" "0,1"
bitfld.long 0x00 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x00 1. "E1,Event #1" "0,1"
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "ERH_RN,Event Register (High Part): If ERH.En bit is set and the EERH.En bit is also set then the corresponding DMA channel is prioritized vs"
bitfld.long 0x04 31. "E63,Event #63" "0,1"
bitfld.long 0x04 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x04 29. "E61,Event #61" "0,1"
bitfld.long 0x04 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x04 27. "E59,Event #59" "0,1"
bitfld.long 0x04 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x04 25. "E57,Event #57" "0,1"
bitfld.long 0x04 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x04 23. "E55,Event #55" "0,1"
bitfld.long 0x04 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x04 21. "E53,Event #53" "0,1"
bitfld.long 0x04 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x04 19. "E51,Event #51" "0,1"
bitfld.long 0x04 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x04 17. "E49,Event #49" "0,1"
bitfld.long 0x04 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x04 15. "E47,Event #47" "0,1"
bitfld.long 0x04 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x04 13. "E45,Event #45" "0,1"
bitfld.long 0x04 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x04 11. "E43,Event #43" "0,1"
bitfld.long 0x04 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x04 9. "E41,Event #41" "0,1"
bitfld.long 0x04 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x04 7. "E39,Event #39" "0,1"
bitfld.long 0x04 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x04 5. "E37,Event #37" "0,1"
bitfld.long 0x04 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x04 3. "E35,Event #35" "0,1"
bitfld.long 0x04 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x04 1. "E33,Event #33" "0,1"
bitfld.long 0x04 0. "E32,Event #32" "0,1"
line.long 0x08 "ECR_RN,Event Clear Register: CPU write of '1' to the ECR.En bit causes the ER.En bit to be cleared"
bitfld.long 0x08 31. "E31,Event #31" "0,1"
bitfld.long 0x08 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x08 29. "E29,Event #29" "0,1"
bitfld.long 0x08 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x08 27. "E27,Event #27" "0,1"
bitfld.long 0x08 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x08 25. "E25,Event #25" "0,1"
bitfld.long 0x08 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x08 23. "E23,Event #23" "0,1"
bitfld.long 0x08 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x08 21. "E21,Event #21" "0,1"
bitfld.long 0x08 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x08 19. "E19,Event #19" "0,1"
bitfld.long 0x08 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x08 17. "E17,Event #17" "0,1"
bitfld.long 0x08 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x08 15. "E15,Event #15" "0,1"
bitfld.long 0x08 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x08 13. "E13,Event #13" "0,1"
bitfld.long 0x08 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x08 11. "E11,Event #11" "0,1"
bitfld.long 0x08 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x08 9. "E9,Event #9" "0,1"
bitfld.long 0x08 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x08 7. "E7,Event #7" "0,1"
bitfld.long 0x08 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x08 5. "E5,Event #5" "0,1"
bitfld.long 0x08 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x08 3. "E3,Event #3" "0,1"
bitfld.long 0x08 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x08 1. "E1,Event #1" "0,1"
bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "ECRH_RN,Event Clear Register (High Part): CPU write of '1' to the ECRH.En bit causes the ERH.En bit to be cleared"
bitfld.long 0x0C 31. "E63,Event #63" "0,1"
bitfld.long 0x0C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x0C 29. "E61,Event #61" "0,1"
bitfld.long 0x0C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x0C 27. "E59,Event #59" "0,1"
bitfld.long 0x0C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x0C 25. "E57,Event #57" "0,1"
bitfld.long 0x0C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x0C 23. "E55,Event #55" "0,1"
bitfld.long 0x0C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x0C 21. "E53,Event #53" "0,1"
bitfld.long 0x0C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x0C 19. "E51,Event #51" "0,1"
bitfld.long 0x0C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x0C 17. "E49,Event #49" "0,1"
bitfld.long 0x0C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x0C 15. "E47,Event #47" "0,1"
bitfld.long 0x0C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x0C 13. "E45,Event #45" "0,1"
bitfld.long 0x0C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x0C 11. "E43,Event #43" "0,1"
bitfld.long 0x0C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x0C 9. "E41,Event #41" "0,1"
bitfld.long 0x0C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x0C 7. "E39,Event #39" "0,1"
bitfld.long 0x0C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x0C 5. "E37,Event #37" "0,1"
bitfld.long 0x0C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x0C 3. "E35,Event #35" "0,1"
bitfld.long 0x0C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x0C 1. "E33,Event #33" "0,1"
bitfld.long 0x0C 0. "E32,Event #32" "0,1"
line.long 0x10 "ESR_RN,Event Set Register: CPU write of '1' to the ESR.En bit causes the ER.En bit to be set"
bitfld.long 0x10 31. "E31,Event #31" "0,1"
bitfld.long 0x10 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x10 29. "E29,Event #29" "0,1"
bitfld.long 0x10 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x10 27. "E27,Event #27" "0,1"
bitfld.long 0x10 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x10 25. "E25,Event #25" "0,1"
bitfld.long 0x10 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x10 23. "E23,Event #23" "0,1"
bitfld.long 0x10 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x10 21. "E21,Event #21" "0,1"
bitfld.long 0x10 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x10 19. "E19,Event #19" "0,1"
bitfld.long 0x10 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x10 17. "E17,Event #17" "0,1"
bitfld.long 0x10 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x10 15. "E15,Event #15" "0,1"
bitfld.long 0x10 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x10 13. "E13,Event #13" "0,1"
bitfld.long 0x10 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x10 11. "E11,Event #11" "0,1"
bitfld.long 0x10 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x10 9. "E9,Event #9" "0,1"
bitfld.long 0x10 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x10 7. "E7,Event #7" "0,1"
bitfld.long 0x10 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x10 5. "E5,Event #5" "0,1"
bitfld.long 0x10 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x10 3. "E3,Event #3" "0,1"
bitfld.long 0x10 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x10 1. "E1,Event #1" "0,1"
bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "ESRH_RN,Event Set Register (High Part) CPU write of '1' to the ESRH.En bit causes the ERH.En bit to be set"
bitfld.long 0x14 31. "E63,Event #63" "0,1"
bitfld.long 0x14 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x14 29. "E61,Event #61" "0,1"
bitfld.long 0x14 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x14 27. "E59,Event #59" "0,1"
bitfld.long 0x14 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x14 25. "E57,Event #57" "0,1"
bitfld.long 0x14 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x14 23. "E55,Event #55" "0,1"
bitfld.long 0x14 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x14 21. "E53,Event #53" "0,1"
bitfld.long 0x14 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x14 19. "E51,Event #51" "0,1"
bitfld.long 0x14 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x14 17. "E49,Event #49" "0,1"
bitfld.long 0x14 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x14 15. "E47,Event #47" "0,1"
bitfld.long 0x14 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x14 13. "E45,Event #45" "0,1"
bitfld.long 0x14 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x14 11. "E43,Event #43" "0,1"
bitfld.long 0x14 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x14 9. "E41,Event #41" "0,1"
bitfld.long 0x14 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x14 7. "E39,Event #39" "0,1"
bitfld.long 0x14 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x14 5. "E37,Event #37" "0,1"
bitfld.long 0x14 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x14 3. "E35,Event #35" "0,1"
bitfld.long 0x14 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x14 1. "E33,Event #33" "0,1"
bitfld.long 0x14 0. "E32,Event #32" "0,1"
line.long 0x18 "CER_RN,Chained Event Register: If CER.En bit is set (regardless of state of EER.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x18 31. "E31,Event #31" "0,1"
bitfld.long 0x18 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x18 29. "E29,Event #29" "0,1"
bitfld.long 0x18 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x18 27. "E27,Event #27" "0,1"
bitfld.long 0x18 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x18 25. "E25,Event #25" "0,1"
bitfld.long 0x18 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x18 23. "E23,Event #23" "0,1"
bitfld.long 0x18 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x18 21. "E21,Event #21" "0,1"
bitfld.long 0x18 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x18 19. "E19,Event #19" "0,1"
bitfld.long 0x18 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x18 17. "E17,Event #17" "0,1"
bitfld.long 0x18 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x18 15. "E15,Event #15" "0,1"
bitfld.long 0x18 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x18 13. "E13,Event #13" "0,1"
bitfld.long 0x18 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x18 11. "E11,Event #11" "0,1"
bitfld.long 0x18 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x18 9. "E9,Event #9" "0,1"
bitfld.long 0x18 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x18 7. "E7,Event #7" "0,1"
bitfld.long 0x18 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x18 5. "E5,Event #5" "0,1"
bitfld.long 0x18 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x18 3. "E3,Event #3" "0,1"
bitfld.long 0x18 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x18 1. "E1,Event #1" "0,1"
bitfld.long 0x18 0. "E0,Event #0" "0,1"
line.long 0x1C "CERH_RN,Chained Event Register (High Part): If CERH.En bit is set (regardless of state of EERH.En) then the corresponding DMA channel is prioritized vs"
bitfld.long 0x1C 31. "E63,Event #63" "0,1"
bitfld.long 0x1C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x1C 29. "E61,Event #61" "0,1"
bitfld.long 0x1C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x1C 27. "E59,Event #59" "0,1"
bitfld.long 0x1C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x1C 25. "E57,Event #57" "0,1"
bitfld.long 0x1C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x1C 23. "E55,Event #55" "0,1"
bitfld.long 0x1C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x1C 21. "E53,Event #53" "0,1"
bitfld.long 0x1C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x1C 19. "E51,Event #51" "0,1"
bitfld.long 0x1C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x1C 17. "E49,Event #49" "0,1"
bitfld.long 0x1C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x1C 15. "E47,Event #47" "0,1"
bitfld.long 0x1C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x1C 13. "E45,Event #45" "0,1"
bitfld.long 0x1C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x1C 11. "E43,Event #43" "0,1"
bitfld.long 0x1C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x1C 9. "E41,Event #41" "0,1"
bitfld.long 0x1C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x1C 7. "E39,Event #39" "0,1"
bitfld.long 0x1C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x1C 5. "E37,Event #37" "0,1"
bitfld.long 0x1C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x1C 3. "E35,Event #35" "0,1"
bitfld.long 0x1C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x1C 1. "E33,Event #33" "0,1"
bitfld.long 0x1C 0. "E32,Event #32" "0,1"
line.long 0x20 "EER_RN,Event Enable Register: Enables DMA transfers for ER.En pending events"
bitfld.long 0x20 31. "E31,Event #31" "0,1"
bitfld.long 0x20 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x20 29. "E29,Event #29" "0,1"
bitfld.long 0x20 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x20 27. "E27,Event #27" "0,1"
bitfld.long 0x20 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x20 25. "E25,Event #25" "0,1"
bitfld.long 0x20 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x20 23. "E23,Event #23" "0,1"
bitfld.long 0x20 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x20 21. "E21,Event #21" "0,1"
bitfld.long 0x20 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x20 19. "E19,Event #19" "0,1"
bitfld.long 0x20 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x20 17. "E17,Event #17" "0,1"
bitfld.long 0x20 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x20 15. "E15,Event #15" "0,1"
bitfld.long 0x20 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x20 13. "E13,Event #13" "0,1"
bitfld.long 0x20 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x20 11. "E11,Event #11" "0,1"
bitfld.long 0x20 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x20 9. "E9,Event #9" "0,1"
bitfld.long 0x20 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x20 7. "E7,Event #7" "0,1"
bitfld.long 0x20 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x20 5. "E5,Event #5" "0,1"
bitfld.long 0x20 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x20 3. "E3,Event #3" "0,1"
bitfld.long 0x20 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x20 1. "E1,Event #1" "0,1"
bitfld.long 0x20 0. "E0,Event #0" "0,1"
line.long 0x24 "EERH_RN,Event Enable Register (High Part): Enables DMA transfers for ERH.En pending events"
bitfld.long 0x24 31. "E63,Event #63" "0,1"
bitfld.long 0x24 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x24 29. "E61,Event #61" "0,1"
bitfld.long 0x24 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x24 27. "E59,Event #59" "0,1"
bitfld.long 0x24 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x24 25. "E57,Event #57" "0,1"
bitfld.long 0x24 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x24 23. "E55,Event #55" "0,1"
bitfld.long 0x24 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x24 21. "E53,Event #53" "0,1"
bitfld.long 0x24 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x24 19. "E51,Event #51" "0,1"
bitfld.long 0x24 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x24 17. "E49,Event #49" "0,1"
bitfld.long 0x24 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x24 15. "E47,Event #47" "0,1"
bitfld.long 0x24 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x24 13. "E45,Event #45" "0,1"
bitfld.long 0x24 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x24 11. "E43,Event #43" "0,1"
bitfld.long 0x24 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x24 9. "E41,Event #41" "0,1"
bitfld.long 0x24 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x24 7. "E39,Event #39" "0,1"
bitfld.long 0x24 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x24 5. "E37,Event #37" "0,1"
bitfld.long 0x24 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x24 3. "E35,Event #35" "0,1"
bitfld.long 0x24 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x24 1. "E33,Event #33" "0,1"
bitfld.long 0x24 0. "E32,Event #32" "0,1"
line.long 0x28 "EECR_RN,Event Enable Clear Register: CPU write of '1' to the EECR.En bit causes the EER.En bit to be cleared"
bitfld.long 0x28 31. "E31,Event #31" "0,1"
bitfld.long 0x28 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x28 29. "E29,Event #29" "0,1"
bitfld.long 0x28 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x28 27. "E27,Event #27" "0,1"
bitfld.long 0x28 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x28 25. "E25,Event #25" "0,1"
bitfld.long 0x28 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x28 23. "E23,Event #23" "0,1"
bitfld.long 0x28 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x28 21. "E21,Event #21" "0,1"
bitfld.long 0x28 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x28 19. "E19,Event #19" "0,1"
bitfld.long 0x28 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x28 17. "E17,Event #17" "0,1"
bitfld.long 0x28 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x28 15. "E15,Event #15" "0,1"
bitfld.long 0x28 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x28 13. "E13,Event #13" "0,1"
bitfld.long 0x28 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x28 11. "E11,Event #11" "0,1"
bitfld.long 0x28 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x28 9. "E9,Event #9" "0,1"
bitfld.long 0x28 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x28 7. "E7,Event #7" "0,1"
bitfld.long 0x28 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x28 5. "E5,Event #5" "0,1"
bitfld.long 0x28 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x28 3. "E3,Event #3" "0,1"
bitfld.long 0x28 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x28 1. "E1,Event #1" "0,1"
bitfld.long 0x28 0. "E0,Event #0" "0,1"
line.long 0x2C "EECRH_RN,Event Enable Clear Register (High Part): CPU write of '1' to the EECRH.En bit causes the EERH.En bit to be cleared"
bitfld.long 0x2C 31. "E63,Event #63" "0,1"
bitfld.long 0x2C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x2C 29. "E61,Event #61" "0,1"
bitfld.long 0x2C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x2C 27. "E59,Event #59" "0,1"
bitfld.long 0x2C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x2C 25. "E57,Event #57" "0,1"
bitfld.long 0x2C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x2C 23. "E55,Event #55" "0,1"
bitfld.long 0x2C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x2C 21. "E53,Event #53" "0,1"
bitfld.long 0x2C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x2C 19. "E51,Event #51" "0,1"
bitfld.long 0x2C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x2C 17. "E49,Event #49" "0,1"
bitfld.long 0x2C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x2C 15. "E47,Event #47" "0,1"
bitfld.long 0x2C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x2C 13. "E45,Event #45" "0,1"
bitfld.long 0x2C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x2C 11. "E43,Event #43" "0,1"
bitfld.long 0x2C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x2C 9. "E41,Event #41" "0,1"
bitfld.long 0x2C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x2C 7. "E39,Event #39" "0,1"
bitfld.long 0x2C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x2C 5. "E37,Event #37" "0,1"
bitfld.long 0x2C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x2C 3. "E35,Event #35" "0,1"
bitfld.long 0x2C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x2C 1. "E33,Event #33" "0,1"
bitfld.long 0x2C 0. "E32,Event #32" "0,1"
line.long 0x30 "EESR_RN,Event Enable Set Register: CPU write of '1' to the EESR.En bit causes the EER.En bit to be set"
bitfld.long 0x30 31. "E31,Event #31" "0,1"
bitfld.long 0x30 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x30 29. "E29,Event #29" "0,1"
bitfld.long 0x30 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x30 27. "E27,Event #27" "0,1"
bitfld.long 0x30 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x30 25. "E25,Event #25" "0,1"
bitfld.long 0x30 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x30 23. "E23,Event #23" "0,1"
bitfld.long 0x30 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x30 21. "E21,Event #21" "0,1"
bitfld.long 0x30 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x30 19. "E19,Event #19" "0,1"
bitfld.long 0x30 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x30 17. "E17,Event #17" "0,1"
bitfld.long 0x30 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x30 15. "E15,Event #15" "0,1"
bitfld.long 0x30 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x30 13. "E13,Event #13" "0,1"
bitfld.long 0x30 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x30 11. "E11,Event #11" "0,1"
bitfld.long 0x30 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x30 9. "E9,Event #9" "0,1"
bitfld.long 0x30 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x30 7. "E7,Event #7" "0,1"
bitfld.long 0x30 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x30 5. "E5,Event #5" "0,1"
bitfld.long 0x30 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x30 3. "E3,Event #3" "0,1"
bitfld.long 0x30 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x30 1. "E1,Event #1" "0,1"
bitfld.long 0x30 0. "E0,Event #0" "0,1"
line.long 0x34 "EESRH_RN,Event Enable Set Register (High Part): CPU write of '1' to the EESRH.En bit causes the EERH.En bit to be set"
bitfld.long 0x34 31. "E63,Event #63" "0,1"
bitfld.long 0x34 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x34 29. "E61,Event #61" "0,1"
bitfld.long 0x34 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x34 27. "E59,Event #59" "0,1"
bitfld.long 0x34 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x34 25. "E57,Event #57" "0,1"
bitfld.long 0x34 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x34 23. "E55,Event #55" "0,1"
bitfld.long 0x34 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x34 21. "E53,Event #53" "0,1"
bitfld.long 0x34 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x34 19. "E51,Event #51" "0,1"
bitfld.long 0x34 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x34 17. "E49,Event #49" "0,1"
bitfld.long 0x34 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x34 15. "E47,Event #47" "0,1"
bitfld.long 0x34 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x34 13. "E45,Event #45" "0,1"
bitfld.long 0x34 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x34 11. "E43,Event #43" "0,1"
bitfld.long 0x34 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x34 9. "E41,Event #41" "0,1"
bitfld.long 0x34 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x34 7. "E39,Event #39" "0,1"
bitfld.long 0x34 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x34 5. "E37,Event #37" "0,1"
bitfld.long 0x34 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x34 3. "E35,Event #35" "0,1"
bitfld.long 0x34 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x34 1. "E33,Event #33" "0,1"
bitfld.long 0x34 0. "E32,Event #32" "0,1"
line.long 0x38 "SER_RN,Secondary Event Register: The secondary event register is used along with the Event Register (ER) to provide information on the state of an Event"
bitfld.long 0x38 31. "E31,Event #31" "0,1"
bitfld.long 0x38 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x38 29. "E29,Event #29" "0,1"
bitfld.long 0x38 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x38 27. "E27,Event #27" "0,1"
bitfld.long 0x38 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x38 25. "E25,Event #25" "0,1"
bitfld.long 0x38 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x38 23. "E23,Event #23" "0,1"
bitfld.long 0x38 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x38 21. "E21,Event #21" "0,1"
bitfld.long 0x38 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x38 19. "E19,Event #19" "0,1"
bitfld.long 0x38 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x38 17. "E17,Event #17" "0,1"
bitfld.long 0x38 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x38 15. "E15,Event #15" "0,1"
bitfld.long 0x38 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x38 13. "E13,Event #13" "0,1"
bitfld.long 0x38 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x38 11. "E11,Event #11" "0,1"
bitfld.long 0x38 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x38 9. "E9,Event #9" "0,1"
bitfld.long 0x38 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x38 7. "E7,Event #7" "0,1"
bitfld.long 0x38 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x38 5. "E5,Event #5" "0,1"
bitfld.long 0x38 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x38 3. "E3,Event #3" "0,1"
bitfld.long 0x38 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x38 1. "E1,Event #1" "0,1"
bitfld.long 0x38 0. "E0,Event #0" "0,1"
line.long 0x3C "SERH_RN,Secondary Event Register (High Part): The secondary event register is used along with the Event Register (ERH) to provide information on the state of an Event"
bitfld.long 0x3C 31. "E63,Event #63" "0,1"
bitfld.long 0x3C 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x3C 29. "E61,Event #61" "0,1"
bitfld.long 0x3C 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x3C 27. "E59,Event #59" "0,1"
bitfld.long 0x3C 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x3C 25. "E57,Event #57" "0,1"
bitfld.long 0x3C 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x3C 23. "E55,Event #55" "0,1"
bitfld.long 0x3C 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x3C 21. "E53,Event #53" "0,1"
bitfld.long 0x3C 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x3C 19. "E51,Event #51" "0,1"
bitfld.long 0x3C 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x3C 17. "E49,Event #49" "0,1"
bitfld.long 0x3C 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x3C 15. "E47,Event #47" "0,1"
bitfld.long 0x3C 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x3C 13. "E45,Event #45" "0,1"
bitfld.long 0x3C 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x3C 11. "E43,Event #43" "0,1"
bitfld.long 0x3C 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x3C 9. "E41,Event #41" "0,1"
bitfld.long 0x3C 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x3C 7. "E39,Event #39" "0,1"
bitfld.long 0x3C 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x3C 5. "E37,Event #37" "0,1"
bitfld.long 0x3C 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x3C 3. "E35,Event #35" "0,1"
bitfld.long 0x3C 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x3C 1. "E33,Event #33" "0,1"
bitfld.long 0x3C 0. "E32,Event #32" "0,1"
line.long 0x40 "SECR_RN,Secondary Event Clear Register: The secondary event clear register is used to clear the status of the SER registers"
bitfld.long 0x40 31. "E31,Event #31" "0,1"
bitfld.long 0x40 30. "E30,Event #30" "0,1"
newline
bitfld.long 0x40 29. "E29,Event #29" "0,1"
bitfld.long 0x40 28. "E28,Event #28" "0,1"
newline
bitfld.long 0x40 27. "E27,Event #27" "0,1"
bitfld.long 0x40 26. "E26,Event #26" "0,1"
newline
bitfld.long 0x40 25. "E25,Event #25" "0,1"
bitfld.long 0x40 24. "E24,Event #24" "0,1"
newline
bitfld.long 0x40 23. "E23,Event #23" "0,1"
bitfld.long 0x40 22. "E22,Event #22" "0,1"
newline
bitfld.long 0x40 21. "E21,Event #21" "0,1"
bitfld.long 0x40 20. "E20,Event #20" "0,1"
newline
bitfld.long 0x40 19. "E19,Event #19" "0,1"
bitfld.long 0x40 18. "E18,Event #18" "0,1"
newline
bitfld.long 0x40 17. "E17,Event #17" "0,1"
bitfld.long 0x40 16. "E16,Event #16" "0,1"
newline
bitfld.long 0x40 15. "E15,Event #15" "0,1"
bitfld.long 0x40 14. "E14,Event #14" "0,1"
newline
bitfld.long 0x40 13. "E13,Event #13" "0,1"
bitfld.long 0x40 12. "E12,Event #12" "0,1"
newline
bitfld.long 0x40 11. "E11,Event #11" "0,1"
bitfld.long 0x40 10. "E10,Event #10" "0,1"
newline
bitfld.long 0x40 9. "E9,Event #9" "0,1"
bitfld.long 0x40 8. "E8,Event #8" "0,1"
newline
bitfld.long 0x40 7. "E7,Event #7" "0,1"
bitfld.long 0x40 6. "E6,Event #6" "0,1"
newline
bitfld.long 0x40 5. "E5,Event #5" "0,1"
bitfld.long 0x40 4. "E4,Event #4" "0,1"
newline
bitfld.long 0x40 3. "E3,Event #3" "0,1"
bitfld.long 0x40 2. "E2,Event #2" "0,1"
newline
bitfld.long 0x40 1. "E1,Event #1" "0,1"
bitfld.long 0x40 0. "E0,Event #0" "0,1"
line.long 0x44 "SECRH_RN,Secondary Event Clear Register (High Part): The secondary event clear register is used to clear the status of the SERH registers"
bitfld.long 0x44 31. "E63,Event #63" "0,1"
bitfld.long 0x44 30. "E62,Event #62" "0,1"
newline
bitfld.long 0x44 29. "E61,Event #61" "0,1"
bitfld.long 0x44 28. "E60,Event #60" "0,1"
newline
bitfld.long 0x44 27. "E59,Event #59" "0,1"
bitfld.long 0x44 26. "E58,Event #58" "0,1"
newline
bitfld.long 0x44 25. "E57,Event #57" "0,1"
bitfld.long 0x44 24. "E56,Event #56" "0,1"
newline
bitfld.long 0x44 23. "E55,Event #55" "0,1"
bitfld.long 0x44 22. "E54,Event #54" "0,1"
newline
bitfld.long 0x44 21. "E53,Event #53" "0,1"
bitfld.long 0x44 20. "E52,Event #52" "0,1"
newline
bitfld.long 0x44 19. "E51,Event #51" "0,1"
bitfld.long 0x44 18. "E50,Event #50" "0,1"
newline
bitfld.long 0x44 17. "E49,Event #49" "0,1"
bitfld.long 0x44 16. "E48,Event #48" "0,1"
newline
bitfld.long 0x44 15. "E47,Event #47" "0,1"
bitfld.long 0x44 14. "E46,Event #46" "0,1"
newline
bitfld.long 0x44 13. "E45,Event #45" "0,1"
bitfld.long 0x44 12. "E44,Event #44" "0,1"
newline
bitfld.long 0x44 11. "E43,Event #43" "0,1"
bitfld.long 0x44 10. "E42,Event #42" "0,1"
newline
bitfld.long 0x44 9. "E41,Event #41" "0,1"
bitfld.long 0x44 8. "E40,Event #40" "0,1"
newline
bitfld.long 0x44 7. "E39,Event #39" "0,1"
bitfld.long 0x44 6. "E38,Event #38" "0,1"
newline
bitfld.long 0x44 5. "E37,Event #37" "0,1"
bitfld.long 0x44 4. "E36,Event #36" "0,1"
newline
bitfld.long 0x44 3. "E35,Event #35" "0,1"
bitfld.long 0x44 2. "E34,Event #34" "0,1"
newline
bitfld.long 0x44 1. "E33,Event #33" "0,1"
bitfld.long 0x44 0. "E32,Event #32" "0,1"
rgroup.long 0x2050++0x2B
line.long 0x00 "IER_RN,Int Enable Register: IER.In is not directly writeable"
bitfld.long 0x00 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x00 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x00 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x00 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x00 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x00 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x00 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x00 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x00 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x00 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x00 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x00 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x00 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x00 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x00 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x00 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x00 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x00 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x00 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x00 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x00 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x00 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x00 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x00 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x00 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x00 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x00 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x00 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x00 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x00 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x00 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x00 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x04 "IERH_RN,Int Enable Register (High Part): IERH.In is not directly writeable"
bitfld.long 0x04 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x04 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x04 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x04 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x04 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x04 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x04 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x04 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x04 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x04 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x04 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x04 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x04 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x04 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x04 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x04 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x04 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x04 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x04 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x04 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x04 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x04 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x04 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x04 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x04 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x04 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x04 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x04 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x04 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x04 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x04 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x04 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x08 "IECR_RN,Int Enable Clear Register: CPU write of '1' to the IECR.In bit causes the IER.In bit to be cleared"
bitfld.long 0x08 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x08 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x08 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x08 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x08 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x08 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x08 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x08 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x08 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x08 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x08 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x08 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x08 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x08 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x08 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x08 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x08 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x08 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x08 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x08 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x08 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x08 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x08 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x08 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x08 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x08 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x08 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x08 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x08 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x08 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x08 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x08 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x0C "IECRH_RN,Int Enable Clear Register (High Part): CPU write of '1' to the IECRH.In bit causes the IERH.In bit to be cleared"
bitfld.long 0x0C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x0C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x0C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x0C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x0C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x0C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x0C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x0C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x0C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x0C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x0C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x0C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x0C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x0C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x0C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x0C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x0C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x0C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x0C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x0C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x0C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x0C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x0C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x0C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x0C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x0C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x0C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x0C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x0C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x0C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x0C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x0C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x10 "IESR_RN,Int Enable Set Register: CPU write of '1' to the IESR.In bit causes the IESR.In bit to be set"
bitfld.long 0x10 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x10 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x10 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x10 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x10 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x10 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x10 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x10 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x10 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x10 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x10 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x10 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x10 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x10 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x10 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x10 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x10 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x10 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x10 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x10 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x10 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x10 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x10 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x10 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x10 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x10 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x10 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x10 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x10 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x10 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x10 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x10 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x14 "IESRH_RN,Int Enable Set Register (High Part): CPU write of '1' to the IESRH.In bit causes the IESRH.In bit to be set"
bitfld.long 0x14 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x14 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x14 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x14 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x14 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x14 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x14 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x14 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x14 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x14 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x14 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x14 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x14 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x14 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x14 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x14 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x14 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x14 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x14 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x14 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x14 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x14 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x14 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x14 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x14 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x14 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x14 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x14 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x14 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x14 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x14 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x14 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x18 "IPR_RN,Interrupt Pending Register: IPR.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x18 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x18 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x18 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x18 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x18 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x18 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x18 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x18 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x18 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x18 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x18 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x18 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x18 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x18 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x18 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x18 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x18 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x18 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x18 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x18 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x18 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x18 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x18 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x18 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x18 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x18 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x18 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x18 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x18 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x18 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x18 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x18 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x1C "IPRH_RN,Interrupt Pending Register (High Part): IPRH.In bit is set when a interrupt completion code with TCC of N is detected"
bitfld.long 0x1C 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x1C 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x1C 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x1C 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x1C 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x1C 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x1C 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x1C 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x1C 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x1C 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x1C 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x1C 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x1C 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x1C 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x1C 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x1C 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x1C 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x1C 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x1C 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x1C 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x1C 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x1C 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x1C 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x1C 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x1C 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x1C 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x1C 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x1C 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x1C 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x1C 2. "I34,Interrupt associated with TCC #34" "0,1"
newline
bitfld.long 0x1C 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x1C 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x20 "ICR_RN,Interrupt Clear Register: CPU write of '1' to the ICR.In bit causes the IPR.In bit to be cleared"
bitfld.long 0x20 31. "I31,Interrupt associated with TCC #31" "0,1"
bitfld.long 0x20 30. "I30,Interrupt associated with TCC #30" "0,1"
newline
bitfld.long 0x20 29. "I29,Interrupt associated with TCC #29" "0,1"
bitfld.long 0x20 28. "I28,Interrupt associated with TCC #28" "0,1"
newline
bitfld.long 0x20 27. "I27,Interrupt associated with TCC #27" "0,1"
bitfld.long 0x20 26. "I26,Interrupt associated with TCC #26" "0,1"
newline
bitfld.long 0x20 25. "I25,Interrupt associated with TCC #25" "0,1"
bitfld.long 0x20 24. "I24,Interrupt associated with TCC #24" "0,1"
newline
bitfld.long 0x20 23. "I23,Interrupt associated with TCC #23" "0,1"
bitfld.long 0x20 22. "I22,Interrupt associated with TCC #22" "0,1"
newline
bitfld.long 0x20 21. "I21,Interrupt associated with TCC #21" "0,1"
bitfld.long 0x20 20. "I20,Interrupt associated with TCC #20" "0,1"
newline
bitfld.long 0x20 19. "I19,Interrupt associated with TCC #19" "0,1"
bitfld.long 0x20 18. "I18,Interrupt associated with TCC #18" "0,1"
newline
bitfld.long 0x20 17. "I17,Interrupt associated with TCC #17" "0,1"
bitfld.long 0x20 16. "I16,Interrupt associated with TCC #16" "0,1"
newline
bitfld.long 0x20 15. "I15,Interrupt associated with TCC #15" "0,1"
bitfld.long 0x20 14. "I14,Interrupt associated with TCC #14" "0,1"
newline
bitfld.long 0x20 13. "I13,Interrupt associated with TCC #13" "0,1"
bitfld.long 0x20 12. "I12,Interrupt associated with TCC #12" "0,1"
newline
bitfld.long 0x20 11. "I11,Interrupt associated with TCC #11" "0,1"
bitfld.long 0x20 10. "I10,Interrupt associated with TCC #10" "0,1"
newline
bitfld.long 0x20 9. "I9,Interrupt associated with TCC #9" "0,1"
bitfld.long 0x20 8. "I8,Interrupt associated with TCC #8" "0,1"
newline
bitfld.long 0x20 7. "I7,Interrupt associated with TCC #7" "0,1"
bitfld.long 0x20 6. "I6,Interrupt associated with TCC #6" "0,1"
newline
bitfld.long 0x20 5. "I5,Interrupt associated with TCC #5" "0,1"
bitfld.long 0x20 4. "I4,Interrupt associated with TCC #4" "0,1"
newline
bitfld.long 0x20 3. "I3,Interrupt associated with TCC #3" "0,1"
bitfld.long 0x20 2. "I2,Interrupt associated with TCC #2" "0,1"
newline
bitfld.long 0x20 1. "I1,Interrupt associated with TCC #1" "0,1"
bitfld.long 0x20 0. "I0,Interrupt associated with TCC #0" "0,1"
line.long 0x24 "ICRH_RN,Interrupt Clear Register (High Part): CPU write of '1' to the ICRH.In bit causes the IPRH.In bit to be cleared"
bitfld.long 0x24 31. "I63,Interrupt associated with TCC #63" "0,1"
bitfld.long 0x24 30. "I62,Interrupt associated with TCC #62" "0,1"
newline
bitfld.long 0x24 29. "I61,Interrupt associated with TCC #61" "0,1"
bitfld.long 0x24 28. "I60,Interrupt associated with TCC #60" "0,1"
newline
bitfld.long 0x24 27. "I59,Interrupt associated with TCC #59" "0,1"
bitfld.long 0x24 26. "I58,Interrupt associated with TCC #58" "0,1"
newline
bitfld.long 0x24 25. "I57,Interrupt associated with TCC #57" "0,1"
bitfld.long 0x24 24. "I56,Interrupt associated with TCC #56" "0,1"
newline
bitfld.long 0x24 23. "I55,Interrupt associated with TCC #55" "0,1"
bitfld.long 0x24 22. "I54,Interrupt associated with TCC #54" "0,1"
newline
bitfld.long 0x24 21. "I53,Interrupt associated with TCC #53" "0,1"
bitfld.long 0x24 20. "I52,Interrupt associated with TCC #52" "0,1"
newline
bitfld.long 0x24 19. "I51,Interrupt associated with TCC #51" "0,1"
bitfld.long 0x24 18. "I50,Interrupt associated with TCC #50" "0,1"
newline
bitfld.long 0x24 17. "I49,Interrupt associated with TCC #49" "0,1"
bitfld.long 0x24 16. "I48,Interrupt associated with TCC #48" "0,1"
newline
bitfld.long 0x24 15. "I47,Interrupt associated with TCC #47" "0,1"
bitfld.long 0x24 14. "I46,Interrupt associated with TCC #46" "0,1"
newline
bitfld.long 0x24 13. "I45,Interrupt associated with TCC #45" "0,1"
bitfld.long 0x24 12. "I44,Interrupt associated with TCC #44" "0,1"
newline
bitfld.long 0x24 11. "I43,Interrupt associated with TCC #43" "0,1"
bitfld.long 0x24 10. "I42,Interrupt associated with TCC #42" "0,1"
newline
bitfld.long 0x24 9. "I41,Interrupt associated with TCC #41" "0,1"
bitfld.long 0x24 8. "I40,Interrupt associated with TCC #40" "0,1"
newline
bitfld.long 0x24 7. "I39,Interrupt associated with TCC #39" "0,1"
bitfld.long 0x24 6. "I38,Interrupt associated with TCC #38" "0,1"
newline
bitfld.long 0x24 5. "I37,Interrupt associated with TCC #37" "0,1"
bitfld.long 0x24 4. "I36,Interrupt associated with TCC #36" "0,1"
newline
bitfld.long 0x24 3. "I35,Interrupt associated with TCC #35" "0,1"
bitfld.long 0x24 2. "I34,Interrupt associated with TCC #34" "0,1"
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bitfld.long 0x24 1. "I33,Interrupt associated with TCC #33" "0,1"
bitfld.long 0x24 0. "I32,Interrupt associated with TCC #32" "0,1"
line.long 0x28 "IEVAL_RN,Interrupt Eval Register"
hexmask.long 0x28 2.--31. 1. "RES76,RESERVE FIELD"
bitfld.long 0x28 1. "SET,Interrupt Set: CPU write of '1' to the SETn bit causes the tpcc_intN output signal to be pulsed egardless of state of interrupts enable (IERn) and status (IPRn)" "0,1"
newline
bitfld.long 0x28 0. "EVAL,Interrupt Evaluate: CPU write of '1' to the EVALn bit causes the tpcc_intN output signal to be pulsed if any enabled interrupts (IERn) are still pending (IPRn)" "0,1"
rgroup.long 0x2080++0x17
line.long 0x00 "QER_RN,QDMA Event Register: If QER.En bit is set then the corresponding QDMA channel is prioritized vs"
hexmask.long.tbyte 0x00 8.--31. 1. "RES77,RESERVE FIELD"
bitfld.long 0x00 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x00 6. "E6,Event #6" "0,1"
bitfld.long 0x00 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x00 4. "E4,Event #4" "0,1"
bitfld.long 0x00 3. "E3,Event #3" "0,1"
newline
bitfld.long 0x00 2. "E2,Event #2" "0,1"
bitfld.long 0x00 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x00 0. "E0,Event #0" "0,1"
line.long 0x04 "QEER_RN,QDMA Event Enable Register: Enabled/disabled QDMA address comparator for QDMA Channel N"
hexmask.long.tbyte 0x04 8.--31. 1. "RES78,RESERVE FIELD"
bitfld.long 0x04 7. "E7,Event #7" "0,1"
newline
bitfld.long 0x04 6. "E6,Event #6" "0,1"
bitfld.long 0x04 5. "E5,Event #5" "0,1"
newline
bitfld.long 0x04 4. "E4,Event #4" "0,1"
bitfld.long 0x04 3. "E3,Event #3" "0,1"
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bitfld.long 0x04 2. "E2,Event #2" "0,1"
bitfld.long 0x04 1. "E1,Event #1" "0,1"
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bitfld.long 0x04 0. "E0,Event #0" "0,1"
line.long 0x08 "QEECR_RN,QDMA Event Enable Clear Register: CPU write of '1' to the QEECR.En bit causes the QEER.En bit to be cleared"
hexmask.long.tbyte 0x08 8.--31. 1. "RES79,RESERVE FIELD"
bitfld.long 0x08 7. "E7,Event #7" "0,1"
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bitfld.long 0x08 6. "E6,Event #6" "0,1"
bitfld.long 0x08 5. "E5,Event #5" "0,1"
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bitfld.long 0x08 4. "E4,Event #4" "0,1"
bitfld.long 0x08 3. "E3,Event #3" "0,1"
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bitfld.long 0x08 2. "E2,Event #2" "0,1"
bitfld.long 0x08 1. "E1,Event #1" "0,1"
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bitfld.long 0x08 0. "E0,Event #0" "0,1"
line.long 0x0C "QEESR_RN,QDMA Event Enable Set Register: CPU write of '1' to the QEESR.En bit causes the QEESR.En bit to be set"
hexmask.long.tbyte 0x0C 8.--31. 1. "RES80,RESERVE FIELD"
bitfld.long 0x0C 7. "E7,Event #7" "0,1"
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bitfld.long 0x0C 6. "E6,Event #6" "0,1"
bitfld.long 0x0C 5. "E5,Event #5" "0,1"
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bitfld.long 0x0C 4. "E4,Event #4" "0,1"
bitfld.long 0x0C 3. "E3,Event #3" "0,1"
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bitfld.long 0x0C 2. "E2,Event #2" "0,1"
bitfld.long 0x0C 1. "E1,Event #1" "0,1"
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bitfld.long 0x0C 0. "E0,Event #0" "0,1"
line.long 0x10 "QSER_RN,QDMA Secondary Event Register: The QDMA secondary event register is used along with the QDMA Event Register (QER) to provide information on the state of a QDMA Event"
hexmask.long.tbyte 0x10 8.--31. 1. "RES81,RESERVE FIELD"
bitfld.long 0x10 7. "E7,Event #7" "0,1"
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bitfld.long 0x10 6. "E6,Event #6" "0,1"
bitfld.long 0x10 5. "E5,Event #5" "0,1"
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bitfld.long 0x10 4. "E4,Event #4" "0,1"
bitfld.long 0x10 3. "E3,Event #3" "0,1"
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bitfld.long 0x10 2. "E2,Event #2" "0,1"
bitfld.long 0x10 1. "E1,Event #1" "0,1"
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bitfld.long 0x10 0. "E0,Event #0" "0,1"
line.long 0x14 "QSECR_RN,QDMA Secondary Event Clear Register: The secondary event clear register is used to clear the status of the QSER and QER register (note that this is slightly different than the SER operation which does not clear the ER.En register)"
hexmask.long.tbyte 0x14 8.--31. 1. "RES82,RESERVE FIELD"
bitfld.long 0x14 7. "E7,Event #7" "0,1"
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bitfld.long 0x14 6. "E6,Event #6" "0,1"
bitfld.long 0x14 5. "E5,Event #5" "0,1"
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bitfld.long 0x14 4. "E4,Event #4" "0,1"
bitfld.long 0x14 3. "E3,Event #3" "0,1"
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bitfld.long 0x14 2. "E2,Event #2" "0,1"
bitfld.long 0x14 1. "E1,Event #1" "0,1"
newline
bitfld.long 0x14 0. "E0,Event #0" "0,1"
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
rgroup.long ($2+0x400)++0x03
line.long 0x00 "QNE$1,Event Queue Entry Diagram for Queue n - Entry 0"
hexmask.long.tbyte 0x00 8.--31. 1. "RES39,RESERVE FIELD"
bitfld.long 0x00 6.--7. "ETYPE,Event Type: Specifies the specific Event Type for the given entry in the Event Queue" "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "ENUM,Event Number: Specifies the specific Event Number for the given entry in the Event Queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
repeat.end
width 0x0B
tree.end
repeat 2. (list 0. 1. )(list ad:0x5160000 ad:0x5180000 )
tree "RCSS_TPTC_A$1 (RCSS TPTC A0 Module Registers)"
base $2
rgroup.long 0x00++0x07
line.long 0x00 "PID,Peripheral ID Register"
bitfld.long 0x00 30.--31. "SCHEME,PID Scheme: Used to distinguish between old ID scheme and current" "0,1,2,3"
hexmask.long.word 0x00 16.--27. 1. "FUNC,Function indicates a software compatible module family"
newline
bitfld.long 0x00 11.--15. "RTL,RTL Version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
bitfld.long 0x00 8.--10. "MAJOR,Major Revision" "0,1,2,3,4,5,6,7"
newline
bitfld.long 0x00 6.--7. "CUSTOM,Custom revision field: Not used on this version of EDMA" "0,1,2,3"
bitfld.long 0x00 0.--5. "MINOR,Minor Revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "TCCFG,TC Configuration Register"
bitfld.long 0x04 8.--9. "DREGDEPTH,Dst Register FIFO Depth Parameterization" "0,1,2,3"
bitfld.long 0x04 4.--5. "BUSWIDTH,Bus Width Parameterization" "0,1,2,3"
newline
bitfld.long 0x04 0.--2. "FIFOSIZE,Fifo Size Parameterization" "0,1,2,3,4,5,6,7"
rgroup.long 0x100++0x13
line.long 0x00 "TCSTAT,TC Status Register"
bitfld.long 0x00 12.--13. "DFSTRTPTR,Dst FIFO Start Pointer Represents the offset to the head entry of Dst Register FIFO in units of entries" "0,1,2,3"
bitfld.long 0x00 8. "ACTV,Channel Active Channel Active is a logical-OR of each of the BUSY/ACTV signals" "Channel is idle,Channel is busy"
newline
bitfld.long 0x00 4.--6. "DSTACTV,Destination Active State Specifies the number of TRs that are resident in the Dst Register FIFO at a given instant. Legal values are constrained by the DSTREGDEPTH parameter" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 2. "WSACTV,Write Status Active WSACTV =" "Write status is not pending,Write Status is pending"
newline
bitfld.long 0x00 1. "SRCACTV,Source Active State SRCACTV =" "Source Active set is idle,Source Active set is busy either performing read.."
bitfld.long 0x00 0. "PROGBUSY,Program Register Set Busy PROGBUSY =" "Prog set idle and is available for programming,Prog set busy"
line.long 0x04 "INTSTAT,Interrupt Status Register"
bitfld.long 0x04 1. "TRDONE,TR Done Event Status: TRDONE =" "Condition not detected,Set when TC has completed a Transfer Request"
bitfld.long 0x04 0. "PROGEMPTY,Program Set Empty Event Status: PROGEMPTY =" "Condition not detected,Set when Program Register set transitions to.."
line.long 0x08 "INTEN,Interrupt Enable Register"
bitfld.long 0x08 1. "TRDONE,TR Done Event Enable: INTEN.TRDONE =" "TRDONE Event is disabled,TRDONE Event is enabled and contributes to.."
bitfld.long 0x08 0. "PROGEMPTY,Program Set Empty Event Enable: INTEN.PROGEMPTY =" "PROGEMPTY Event is disabled,PROGEMPTY Event is enabled and contributes to.."
line.long 0x0C "INTCLR,Interrupt Clear Register"
bitfld.long 0x0C 1. "TRDONE,TR Done Event Clear: INTCLR.TRDONE =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.TRDONE bit"
bitfld.long 0x0C 0. "PROGEMPTY,Program Set Empty Event Clear: INTCLR.PROGEMPTY =" "Writes of '0' have no effect,Write of '1' clears INTSTAT.PROGEMPTY bit"
line.long 0x10 "INTCMD,Interrupt Command Register"
bitfld.long 0x10 1. "SET,Set TPTC interrupt: Write of '1' to SET causes TPTC interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC interrupt Write of '1' to EVAL causes TPTC interrupt to be pulsed if any of the INTSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
rgroup.long 0x120++0x13
line.long 0x00 "ERRSTAT,Error Status Register"
bitfld.long 0x00 3. "MMRAERR,MMR Address Error: MMRAERR =" "Condition not detected,User attempted to read or write to invalid.."
bitfld.long 0x00 2. "TRERR,TR Error: TR detected that violates FIFO Mode transfer [SAM or DAM is '1'] alignment rules or has ACNT or BCNT == 0" "0,1"
newline
bitfld.long 0x00 0. "BUSERR,Bus Error Event: BUSERR =" "Condition not detected,TC has detected an error code on the write.."
line.long 0x04 "ERREN,Error Enable Register"
bitfld.long 0x04 3. "MMRAERR,Interrupt enable for ERRSTAT.MMRAERR: ERREN.MMRAERR =" "BUSERR is disabled,MMRAERR is enabled and contributes to the TPTC.."
bitfld.long 0x04 2. "TRERR,Interrupt enable for ERRSTAT.TRERR: ERREN.TRERR =" "BUSERR is disabled,TRERR is enabled and contributes to the TPTC.."
newline
bitfld.long 0x04 0. "BUSERR,Interrupt enable for ERRSTAT.BUSERR: ERREN.BUSERR =" "BUSERR is disabled,BUSERR is enabled and contributes to the TPTC.."
line.long 0x08 "ERRCLR,Error Clear Register"
bitfld.long 0x08 3. "MMRAERR,Interrupt clear for ERRSTAT.MMRAERR: ERRCLR.MMRAERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.MMRAERR bit"
bitfld.long 0x08 2. "TRERR,Interrupt clear for ERRSTAT.TRERR: ERRCLR.TRERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.TRERR bit"
newline
bitfld.long 0x08 0. "BUSERR,Interrupt clear for ERRSTAT.BUSERR: ERRCLR.BUSERR =" "Writes of '0' have no effect,Write of '1' clears ERRSTAT.BUSERR bit"
line.long 0x0C "ERRDET,Error Details Register"
bitfld.long 0x0C 17. "TCCHEN,Contains the OPT.TCCHEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
bitfld.long 0x0C 16. "TCINTEN,Contains the OPT.TCINTEN value programmed by the user for the Read or Write transaction that resulted in an error" "0,1"
newline
bitfld.long 0x0C 8.--13. "TCC,Transfer Complete Code: Contains the OPT.TCC value programmed by the user for the Read or Write transaction that resulted in an error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x0C 0.--3. "STAT,Transaction Status: Stores the non-zero status/error code that was detected on the read status or write status bus. MS-bit effectively serves as the read vs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x10 "ERRCMD,Error Command Register"
bitfld.long 0x10 1. "SET,Set TPTC error interrupt: Write of '1' to SET causes TPTC error interrupt to be pulsed unconditionally. Writes of '0' have no affect" "0,1"
bitfld.long 0x10 0. "EVAL,Evaluate state of TPTC error interrupt Write of '1' to EVAL causes TPTC error interrupt to be pulsed if any of the ERRSTAT bits are set to '1'. Writes of '0' have no affect" "0,1"
group.long 0x140++0x03
line.long 0x00 "RDRATE,Read Rate Register"
bitfld.long 0x00 0.--2. "RDRATE,Read Rate Control: Controls the number of cycles between read commands" "0,1,2,3,4,5,6,7"
group.long 0x200++0x17
line.long 0x00 "POPT,Prog Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "PSRC,Prog Set Src Address"
line.long 0x08 "PCNT,Prog Set Count"
hexmask.long.word 0x08 16.--31. 1. "BCNT,B-Dimension count"
hexmask.long.word 0x08 0.--15. 1. "ACNT,A-Dimension count"
line.long 0x0C "PDST,Prog Set Dst Address"
line.long 0x10 "PBIDX,Prog Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Program Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Program Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "PMPPRXY,Prog Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.long 0x240++0x27
line.long 0x00 "SAOPT,Src Actv Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "SASRC,Src Actv Set Src Address"
line.long 0x08 "SACNT,Src Actv Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "SADST,Src Actv Set Dst Address"
line.long 0x10 "SABIDX,Src Actv Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Source Active Register Set: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT elements]"
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Source B-Idx for Source Active Register Set: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements]"
line.long 0x14 "SAMPPRXY,Src Actv Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
newline
bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "SACNTRLD,Src Actv Set Cnt Reload"
hexmask.long.word 0x18 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Source Active Register set"
line.long 0x1C "SASRCBREF,Src Actv Set Src Addr B-Reference"
line.long 0x20 "SADSTBREF,Src Actv Set Dst Addr B-Reference"
line.long 0x24 "SABCNT,Src Actv Set B-Count"
hexmask.long.word 0x24 0.--15. 1. "BCNT,B-Dimension count: Number of arrays to be transferred where each array is ACNT in length. Count Remaining for Src Active Register Set"
rgroup.long 0x280++0x07
line.long 0x00 "DFCNTRLD,Dst FIFO Set Cnt Reload"
hexmask.long.word 0x00 0.--15. 1. "ACNTRLD,A-Cnt Reload value for Destination FIFO Register set"
line.long 0x04 "DFSRCBREF,Dst FIFO Set Src Addr B-Reference"
repeat 2. (list 0x0 0x1 )(list 0x0 0x40 )
group.long ($2+0x300)++0x1B
line.long 0x00 "DFOPT$1,Dst FIFO Set Options"
bitfld.long 0x00 28.--29. "DBG_ID,Debug ID Value driven on the read (tptc_r_dbg_channel_id) and write (tptc_w_dbg_channel_id) command bus. Used at system level for trace/profiling of user selected transfers in systems that include this feature" "0,1,2,3"
bitfld.long 0x00 22. "TCCHEN,Transfer complete chaining enable: 0: Transfer complete chaining is disabled. 1: Transfer complete chaining is enabled" "0,1"
newline
bitfld.long 0x00 20. "TCINTEN,Transfer complete interrupt enable: 0: Transfer complete interrupt is disabled. 1: Transfer complete interrupt is enabled" "0,1"
bitfld.long 0x00 12.--17. "TCC,Transfer Complete Code: The 6-bit code is used to set the relevant bit in CER or IPR of the TPCC module" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
newline
bitfld.long 0x00 8.--10. "FWID,FIFO width control: Applies if either SAM or DAM is set to FIFO mode" "0,1,2,3,4,5,6,7"
bitfld.long 0x00 4.--6. "PRI,Transfer Priority: 0: Priority" "Highest priority 1,?,?,?,?,?,?,Lowest priority"
newline
bitfld.long 0x00 1. "DAM,Destination Address Mode within an array: 0: INCR Dst addressing within an array increments. 1: FIFO Dst addressing within an array wraps around upon reaching FIFO width" "0,1"
bitfld.long 0x00 0. "SAM,Source Address Mode within an array: 0: INCR Src addressing within an array increments. 1: FIFO Src addressing within an array wraps around upon reaching FIFO width" "0,1"
line.long 0x04 "DFSRC$1,Dst FIFO Set Src Address"
line.long 0x08 "DFACNT$1,Dst FIFO Set A-Count"
hexmask.long.tbyte 0x08 0.--22. 1. "ACNT,A-Dimension count"
line.long 0x0C "DFDST$1,Dst FIFO Set Dst Address"
line.long 0x10 "DFBIDX$1,Dst FIFO Set B-Dim Idx"
hexmask.long.word 0x10 16.--31. 1. "DBIDX,Dest B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Destination arrays: Represents the offset in bytes between the starting address of each destination array [recall that there are BCNT arrays of ACNT.."
hexmask.long.word 0x10 0.--15. 1. "SBIDX,Src B-Idx for Dest FIFO Register Set. Value copied from PBIDX: B-Idx offset between Source arrays: Represents the offset in bytes between the starting address of each source array [recall that there are BCNT arrays of ACNT elements].."
line.long 0x14 "DFMPPRXY$1,Dst FIFO Set Mem Protect Proxy"
bitfld.long 0x14 9. "SECURE,Secure Level: Deprecated always read as 0" "0,1"
bitfld.long 0x14 8. "PRIV,Privilege Level: PRIV =" "User level privilege PRIV =,Supervisor level privilege PMPPRXY.PRIV is.."
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bitfld.long 0x14 0.--3. "PRIVID,Privilege ID: PMPPRXY.PRIVID is always updated with the value from configuration bus privilege ID field on any/every write to Program Set BIDX Register [trigger register]. The PRIVID value for the SA Set and DF Set are copied from the.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "DFBCNT$1,Dst FIFO Set B-Count"
hexmask.long.word 0x18 0.--15. 1. "BCNT,B-Count Remaining for Dst Register Set: Number of arrays to be transferred where each array is ACNT in length. Represents the amount of data remaining to be written. Initial value is copied from PCNT. TC decrements ACNT and BCNT as.."
repeat.end
width 0x0B
tree.end
repeat.end
tree "TOP_AURORA_TX (TOP AURORA TX Module Registers)"
base ad:0x3060000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
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bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
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bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x0F
line.long 0x00 "AURORA_TX_CONFIG,"
bitfld.long 0x00 16.--18. "NUM_LANES,Selects the number of lanes for trasnmission" "1 Lane,2 Lanes,?,?,?,?,?,8Lanes"
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bitfld.long 0x00 2. "STRICT_ALIGN,Enable Aurora Strict Alingment Rules" "0,1"
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bitfld.long 0x00 1. "PROTOCOL_SEL,Selects if the IP is in 8b/10b OR 64b/66b mode" "8b/10b,64b/66b"
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bitfld.long 0x00 0. "ENABLE,Selects if the IP is in 8b/10b OR 64b/66b mode" "8b/10b,64b/66b"
line.long 0x04 "AURORA_TX_LANE_MAP,"
bitfld.long 0x04 28.--31. "LANE7_MAP,These 3 bits determine the logical lane that is transported over the physical lane 7" "Logical lane 0 is transported over physical lane 7,Logical lane 1 is transported over physical lane 7,?,?,?,?,?,Logical lane 7 is transported over physical lane 7,?..."
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bitfld.long 0x04 24.--27. "LANE6_MAP,These 3 bits determine the logical lane that is transported over the physical lane 6" "Logical lane 0 is transported over physical lane 6,Logical lane 1 is transported over physical lane 6,?,?,?,?,?,Logical lane 7 is transported over physical lane 6,?..."
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bitfld.long 0x04 20.--23. "LANE5_MAP,These 3 bits determine the logical lane that is transported over the physical lane 5" "Logical lane 0 is transported over physical lane 5,Logical lane 1 is transported over physical lane 5,?,?,?,?,?,Logical lane 7 is transported over physical lane 5,?..."
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bitfld.long 0x04 16.--19. "LANE4_MAP,These 3 bits determine the logical lane that is transported over the physical lane 4" "Logical lane 0 is transported over physical lane 4,Logical lane 1 is transported over physical lane 4,?,?,?,?,?,Logical lane 7 is transported over physical lane 4,?..."
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bitfld.long 0x04 12.--15. "LANE3_MAP,These 3 bits determine the logical lane that is transported over the physical lane 3" "Logical lane 0 is transported over physical lane 3,Logical lane 1 is transported over physical lane 3,?,?,?,?,?,Logical lane 7 is transported over physical lane 3,?..."
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bitfld.long 0x04 8.--11. "LANE2_MAP,These 3 bits determine the logical lane that is transported over the physical lane 2" "Logical lane 0 is transported over physical lane 2,Logical lane 1 is transported over physical lane 2,?,?,?,?,?,Logical lane 7 is transported over physical lane 2,?..."
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bitfld.long 0x04 4.--7. "LANE1_MAP,These 3 bits determine the logical lane that is transported over the physical lane 1" "Logical lane 0 is transported over physical lane 1,Logical lane 1 is transported over physical lane 1,?,?,?,?,?,Logical lane 7 is transported over physical lane 1,?..."
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bitfld.long 0x04 0.--3. "LANE0_MAP,These 3 bits determine the logical lane that is transported over the physical lane 0" "Logical lane 0 is transported over physical lane 0,Logical lane 0 is transported over physical lane 1,?,?,?,?,?,Logical lane 7 is transported over physical lane 0,?..."
line.long 0x08 "AURORA_TX_UDP_CONFIG,"
bitfld.long 0x08 16.--20. "FRAME_HEADER_EN,Header Enable configuration" "Disable Header transmission,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Number of 32 bit Header to be transmmited,?..."
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bitfld.long 0x08 8. "BYPASS_EN,Writing a value of" "Normal Mode - Framing is done as per aurora..,Bypass the aurora protocol"
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bitfld.long 0x08 7. "TEST_PATTERN_EN,Writing a value of" "0,1"
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bitfld.long 0x08 6. "TWP_SYNC_COMPRESSION_EN,Writing a value of" "Disable the TWP padding packet filter,Enables the compression of incoming.."
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bitfld.long 0x08 5. "CRC_EN,Writing a value of" "Disable UDP CRC calculation,Enable the UDP CRC calculation"
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bitfld.long 0x08 4. "TWP_IDLE_FILTER_EN,Writing a value of" "Disable the TWP padding packet filter,Filters out the incoming TWP Padding Packet from.."
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bitfld.long 0x08 0.--1. "PACK_MODE_SEL,Configure to select AURORATX_UDP_SIZE format" "Number of TWP Packets,Number of Bytes,?,SW only"
line.long 0x0C "AURORA_TX_UDP_SIZE,"
group.long 0x64++0x0F
line.long 0x00 "AURORA_TX_UFC_MSG_CTRL,"
bitfld.long 0x00 0. "UFC_MSG_SENT_STS,This bit indicates that the message send triggered by the SEND_MSG bit has been completed" "No effect,Clears this bit"
line.long 0x04 "AURORA_TX_UFC_MESSAGE0,"
line.long 0x08 "AURORA_TX_UFC_MESSAGE1,"
line.long 0x0C "AURORA_TX_TWP_SYNC_CNT,"
hexmask.long.word 0x0C 0.--9. 1. "SYNC_CNT,Number of TWP Sync Packet that would be sent if AURORA_TX_UDP_CONFIG::A_TX_UDP_CONFIG_TWP_SYNC_COMPRESSION_EN is 0x1"
group.long 0x80++0x1F
line.long 0x00 "AURORA_TX_INITIALIZE_REQ,"
bitfld.long 0x00 1. "TX_INIT,The single bit input to trigger the initialization sequence" "0,1"
line.long 0x04 "AURORA_TX_UFC_MSG_REQ,"
bitfld.long 0x04 0. "SEND_MSG,The bit that triggers the controller to send the MESSAGE0 and MESSAGE1 register contents as a UFC packet" "0,1"
line.long 0x08 "AURORA_TX_FLUSH_REQ,"
bitfld.long 0x08 0. "TRIGGER,Selects the number of lanes for trasnmission" "1 Lane,2 Lanes"
line.long 0x0C "AURORA_TX_EOP_REQ,"
bitfld.long 0x0C 0. "TRIGGER,SW End of Packet trigger to aurora dataframer" "0,1"
line.long 0x10 "AURORA_TX_DATA_START_REQ,"
bitfld.long 0x10 1. "DATA_START,The single bit input to trigger the initialization sequence" "0,1"
line.long 0x14 "AURORA_TX_DATA_STOP_REQ,"
bitfld.long 0x14 1. "DATA_STOP,The single bit input to trigger the Start of Data Transmission" "0,1"
line.long 0x18 "AURORA_TX_TESTPATTERN_START_REQ,"
bitfld.long 0x18 1. "TEST_PATTERN_START,The single bit input to trigger the Stop of Data Transmission" "0,1"
line.long 0x1C "AURORA_TX_TESTPATTERN_STOP_REQ,"
bitfld.long 0x1C 1. "TEST_PATTERN_STOP,The single bit input to trigger the Start of TestPattern Transmission" "0,1"
group.long 0x100++0x1F
line.long 0x00 "AURORA_TX_OVERRIDE,"
bitfld.long 0x00 22. "CC1_OVR_TYP,This read write bit indicates whether the CC1_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 21. "CC0_OVR_TYP,This read write bit indicates whether the CC0_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 20. "INIT_V3_OVR_TYP,This read write bit indicates whether the INIT_V3_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 19. "INIT_V2_OVR_TYP,This read write bit indicates whether the INIT_V2_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 18. "INIT_V1_OVR_TYP,This read write bit indicates whether the INIT_V1_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 17. "INIT_V0_OVR_TYP,This read write bit indicates whether the INIT_V0_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 16. "INIT_SP3_OVR_TYP,This read write bit indicates whether the INIT_SP3_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 15. "INIT_SP2_OVR_TYP,This read write bit indicates whether the INIT_SP2_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 14. "INIT_SP1_OVR_TYP,This read write bit indicates whether the INIT_SP1_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 13. "INIT_SP0_OVR_TYP,This read write bit indicates whether the INIT_SP0_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 12. "UFC_SUF_OVR_TYP,This read write bit indicates whether the UFC_SUF_OVR_TYP symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 11. "I2_OVR_TYP,This read write bit indicates whether the I2_OVR symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 10. "I1_OVR_TYP,This read write bit indicates whether the I1_OVR symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 9. "I0_OVR_TYP,This read write bit indicates whether the I0_OVR symbol is a /D/ octet or /K/ octet" "Indicates a /D/ octet,Indicates a /K/ octet"
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bitfld.long 0x00 8. "SYM_OVR_EN,This read write bit allows the symbols used in the various sequences to be overridden with the values used in the AURORA_TX_SYM register" "0,1"
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bitfld.long 0x00 4.--7. "TX_STATE_OVR_VAL,These bits take effect to enforce a certain transmission state if the TX_ST_OVR_EN bit is set" "Reset no transmission,Initialization,Clock Compensation,Idle,UFC,Run (data),Test (data),Reserved,?,?,?,?,?,?,?,Reserved"
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bitfld.long 0x00 0. "TX_STATE_OVR_EN,This read write bit allows the user to force the IP to remain in a given transmission state" "0,1"
line.long 0x04 "AURORA_TX_8B10B_OVERRIDE0,"
hexmask.long.byte 0x04 24.--31. 1. "UFC_SUF,The 8B/10B protocol defines Start of User Flow Control PDU symbol /SUF/"
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hexmask.long.byte 0x04 16.--23. 1. "I2,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence"
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hexmask.long.byte 0x04 8.--15. 1. "I1,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence"
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hexmask.long.byte 0x04 0.--7. 1. "I0,The 8B/10B protocol defines three symbols - /K/ /R/ and /A/ that can be used in the Idle (/I/) sequence"
line.long 0x08 "AURORA_TX_8B10B_OVERRIDE1,"
hexmask.long.byte 0x08 24.--31. 1. "SP3,The 8B/10B protocol defines the /D10.2/ as the fourth octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
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hexmask.long.byte 0x08 16.--23. 1. "SP2,The 8B/10B protocol defines the /D10.2/ as the third octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
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hexmask.long.byte 0x08 8.--15. 1. "SP1,The 8B/10B protocol defines the /D10.2/ as the second octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
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hexmask.long.byte 0x08 0.--7. 1. "SP0,The 8B/10B protocol defines the /K28.5/ as the first octet to be used in the Sync Polarity (/SP/) sequence during lane initialization"
line.long 0x0C "AURORA_TX_8B10B_OVERRIDE2,"
hexmask.long.byte 0x0C 24.--31. 1. "V3,The 8B/10B protocol defines the /D8.7/ as the fourth octet to be used in the Verification sequence during lane initialization"
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hexmask.long.byte 0x0C 16.--23. 1. "V2,The 8B/10B protocol defines the /D8.7/ as the third octet to be used in the Verification sequence during lane initialization"
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hexmask.long.byte 0x0C 8.--15. 1. "V1,The 8B/10B protocol defines the /D8.7/ as the second octet to be used in the Verification sequence during lane inititialization"
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hexmask.long.byte 0x0C 0.--7. 1. "V0,The 8B/10B protocol defines the /K28.5/ as the first octet to be used in the Verification sequence during lane inititialization"
line.long 0x10 "AURORA_TX_8B10B_OVERRIDE3,"
hexmask.long.byte 0x10 8.--15. 1. "CC1,The 8B/10B protocol defines the /K23.7/ as the second octet to be used in the Clock Compensation sequence"
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hexmask.long.byte 0x10 0.--7. 1. "CC0,The 8B/10B protocol defines the /K23.7/ as the first octet to be used in the Clock Compensation sequence"
line.long 0x14 "AURORA_TX_64B66B_OVERRIDE1,"
hexmask.long.byte 0x14 24.--31. 1. "CB_BITS,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Idle Blocks"
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hexmask.long.byte 0x14 16.--23. 1. "CB_BTF,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks"
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hexmask.long.byte 0x14 8.--15. 1. "IDLE_BITS,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Idle Blocks"
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hexmask.long.byte 0x14 0.--7. 1. "IDLE_BTF,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks"
line.long 0x18 "AURORA_TX_64B66B_OVERRIDE2,"
hexmask.long.byte 0x18 16.--23. 1. "CC_BITS,The 64B/66B protocol defines the CC CB NR SA bits for all the type of Channel Bonding Blocks"
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hexmask.long.byte 0x18 8.--15. 1. "CC_BTF,The 64B/66B protocol defines the value of 0x78 as the BTF for all the types of Idle code blocks"
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hexmask.long.byte 0x18 0.--7. 1. "UFC_BTF,The 64B/66B protocol defines the value of 0x2D as the BTF for the UFC code block"
line.long 0x1C "AURORA_TX_64B66B_OVERRIDE2,"
hexmask.long.byte 0x1C 8.--15. 1. "SEP7_BTF,The 64B/66B protocol defines the value of 0xE1 as the BTF for the Separator-7"
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hexmask.long.byte 0x1C 0.--7. 1. "SEP_BTF,The 64B/66B protocol defines the value of 0x1E as the BTF for the Separator"
group.long 0x124++0x57
line.long 0x00 "AURORA_TX_INIT_CNT_LRC,"
line.long 0x04 "AURORA_TX_INIT_CNT_ALIGN,"
bitfld.long 0x04 16.--19. "ALIGN_MUL,Alignment pattern multiplier" "Alignment pattern multiplier is 32,Reserved,Reserved,Reserved,Reserved,?..."
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hexmask.long.word 0x04 0.--12. 1. "ALIGN_LEN,The number of times the Aurora alignment pattern is sent"
line.long 0x08 "AURORA_TX_INIT_CNT_BONDING,"
abitfld.long 0x08 20.--27. "rw,The 64B standard mentions that There must be at least four Idle blocks between each Channel Bonding block" "0x01=No of Idle Blocks between Channel Bonding..,0x02=No of Idle Blocks between Channel Bonding..,0xFF=No of Idle Blocks between Channel Bonding.."
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bitfld.long 0x08 16.--19. "BOND_MUL,Bond pattern multiplier" "Bond pattern multiplier is 4,Reserved,?..."
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hexmask.long.word 0x08 0.--8. 1. "BOND_LEN,The number of times the Aurora bonding pattern is sent"
line.long 0x0C "AURORA_TX_INIT_CNT_VERIFY,"
bitfld.long 0x0C 16.--19. "VERIFY_MUL,Verify pattern multiplier" "Verify pattern multiplier is 4,Reserved,?..."
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hexmask.long.word 0x0C 0.--8. 1. "VERIFY_LEN,The number of times the Aurora verification pattern is sent"
line.long 0x10 "AURORA_TX_INIT_CTRL,"
bitfld.long 0x10 2. "TX_VERIFIED,The single bit input to trigger the transition from the verification state to the channel ready state" "0,1"
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bitfld.long 0x10 1. "TX_BONDED,The single bit input to trigger the transition from the bonding to the verification state" "0,1"
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bitfld.long 0x10 0. "TX_ALIGNED,The single bit input to trigger the Stop of TestPattern Transmission" "0,1"
line.long 0x14 "AURORA_TX_IDLE_CTRL,"
bitfld.long 0x14 2.--5. "SEED,The 4-bit value used to seed the pseudo random integer used in the idle sequence generator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x18 "AURORA_TX_IDLE_REQ,"
bitfld.long 0x18 0. "SEND_IDLE,This bit is used to trigger the insertion of the IDLE sequence by the software" "0,1"
line.long 0x1C "AURORA_TX_CC_REQ,"
bitfld.long 0x1C 1. "SEND_CC,The single bit input that can trigger a CC sequence" "0,1"
line.long 0x20 "AURORA_TX_CC_CNT,"
hexmask.long.word 0x20 0.--15. 1. "SYNC_COUNT,The 16-bit count value used to indicate the number of code group octets after which the CC sequence should be transmitted"
line.long 0x24 "AURORA_TX_CB_STATUS,"
bitfld.long 0x24 0. "CB_COMP,This bit reflects the state of the Channel Bonding FSM" "No effect,Clears the bit"
line.long 0x28 "AURORA_TX_CB_REQ,"
bitfld.long 0x28 1. "SEND_CB,The single bit input that can trigger a Channel Bonding Block" "0,1"
line.long 0x2C "AURORA_TX_CB_CNT,"
hexmask.long.word 0x2C 0.--15. 1. "CB_COUNT,The 16-bit count value used to indicate the number of data blocks after which the Channel Bonding sequence should be transmitted"
line.long 0x30 "AURORA_TX_RESET_REQ,"
bitfld.long 0x30 0. "TX_RESET,The single bit input to reset the Tx process" "0,1"
line.long 0x34 "AURORA_TX_SERIALIZER_OVERRIDE0,"
line.long 0x38 "AURORA_TX_SERIALIZER_OVERRIDE1,"
line.long 0x3C "AURORA_TX_DATA_BYTE_REVERSE,"
bitfld.long 0x3C 1. "crc_byte_reverse_en,Enable Byte reversal on the CRC value" "0,1"
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bitfld.long 0x3C 0. "byte_reverse_en,Enable Byte reversal on the input data" "0,1"
line.long 0x40 "AURORA_TX_64B66B_SCRAMBLER_INIT0,"
line.long 0x44 "AURORA_TX_64B66B_SCRAMBLER_INIT1,"
bitfld.long 0x44 31. "load,Write 0x1 to loaf the scrambler lfsr init value" "0,1"
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hexmask.long 0x44 0.--25. 1. "val,Initial value in the LFSR scrambler bits[57:32]"
line.long 0x48 "AURORA_TX_TESTPATTERN_CTRL,"
bitfld.long 0x48 0. "ramp_en,Enable a ramp patten as the testpattern" "0,1"
line.long 0x4C "AURORA_TX_CC_SEQ_CNT,"
bitfld.long 0x4C 16.--19. "count_64b66b,Configure the number of 64b66b Clock Compensation block to be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x4C 0.--3. "count_8b10b,Configure the number of 8b10b Clock Compensation octets to be sent" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
line.long 0x50 "AURORA_TX_EOP_DELAY,"
bitfld.long 0x50 16. "enable,Write 0x1 to this fiel to enable the delay configured in AURORA_TX_EOP_DEALY::DELAY" "0,1"
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hexmask.long.word 0x50 0.--15. 1. "delay,Internal Delay between the Data Framer and the Controller Block to stall data to the controller and force IDLES to be inserted by the controller after an ECP of a UDP"
line.long 0x54 "AURORA_TX_FLUSH_DELAY,"
hexmask.long.byte 0x54 0.--7. 1. "delay,Write 0x1 to this fiel to enable the delay configured in AURORA_TX_EOP_DEALY::DELAY"
rgroup.long 0x200++0x27
line.long 0x00 "AURORA_TX_STATUS,"
abitfld.long 0x00 16.--31. "DATAFRAMER,Dataframer Status fields Bit" "0x0000=OFF,0x0001=INIT DONE,0x000A=TEST MODE,0x000B=DATA MODE,0x0010=Write on Full FIFO Bit,0x0011=Read on Empty FIFO Bits [20:18],0x0064=WAITING FOR GLOBAL FLUSH DONE,0x0065=FLUSH IN PROGRESS Bits [26:21]"
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bitfld.long 0x00 0.--3. "TX_STATE,These read only bits indicate the state of the transmitter in 8B/10B and 64B/66B" "Reset no transmission,Initialization,Clock Compensation,Idle,UFC,Run (data),Test (data),Reserved,?,?,?,?,?,?,?,Reserved The user must note.."
line.long 0x04 "AURORA_TX_INIT_STATUS,"
bitfld.long 0x04 4. "TX_CH_RDY,The status bit that indicates that the channel ready state has been reached" "0,1"
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bitfld.long 0x04 3. "TX_TXCB0,The status bit that indicates that the TX_ TXCB0 state has been completed" "0,1"
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bitfld.long 0x04 2. "TX_INIT0,The status bit that indicates that the TX_INIT0 state has been completed" "0,1"
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bitfld.long 0x04 1. "TX_RESET1,The status bit that indicates that the TX_RESET1 state has been completed" "0,1"
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bitfld.long 0x04 0. "TX_RESET0,The status bit that indicates that the TX_RESET0 state has been completed" "0,1"
line.long 0x08 "AURORA_TX_CC_STATUS,"
bitfld.long 0x08 0. "CC_COMP,This bit reflects the state of the CC FSM" "No effect,Clears the bit"
line.long 0x0C "AURORA_TX_IDLE_STATUS,"
bitfld.long 0x0C 0. "IDLE_COMP,This bit reflects the state of the IDLE FSM" "No effect,Clears the bit"
line.long 0x10 "AURORA_TX_INTAGG_MASK,"
bitfld.long 0x10 15. "int15,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 14. "int14,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 13. "int13,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 12. "int12,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 11. "int11,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 10. "int10,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 9. "int9,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 8. "int8,Mask the the corresponding event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x10 7. "int7,Mask Interrupt AURORA_TX_HEADER_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 6. "int6,Mask Interrupt AURORA_TX_EOP_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 5. "int5,Mask Interrupt DATA_STOP_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 4. "int4,Mask Interrupt AURORA_TX_CC_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 3. "int3,Mask Interrupt AURORA_TX_UFC_SENT" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 2. "int2,Mask Interrupt AURORA_TX_EXT_FLUSH_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 1. "int1,Mask Interrupt AURORA_TX_FLUSH_DONE" "Interrupt is Unmasked,Interrupt is Masked"
newline
bitfld.long 0x10 0. "int0,Mask Interrupt AURORA_TX_INIT_DONE" "Interrupt is Unmasked,Interrupt is Masked"
line.long 0x14 "AURORA_TX_INTAGG_STATUS,"
bitfld.long 0x14 15. "int15,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 14. "int14,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 13. "int13,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 12. "int12,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 11. "int11,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 10. "int10,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 9. "int9,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 8. "int8,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 7. "int7,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 6. "int6,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 5. "int5,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 4. "int4,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 3. "int3,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 2. "int2,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 1. "int1,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x14 0. "int0,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
line.long 0x18 "AURORA_TX_INTAGG_STATUS_RAW,"
bitfld.long 0x18 15. "int15,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 14. "int14,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 13. "int13,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 12. "int12,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 11. "int11,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 10. "int10,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 9. "int9,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 8. "int8,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 7. "int7,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 6. "int6,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 5. "int5,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 4. "int4,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 3. "int3,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 2. "int2,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 1. "int1,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
newline
bitfld.long 0x18 0. "int0,Read of 0x1 indicates a rising edge was detected on the corresponding event line" "0,1"
line.long 0x1C "AURORA_TX_ERRAGG_MASK,"
bitfld.long 0x1C 15. "err15,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 14. "err14,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 13. "err13,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 12. "err12,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 11. "err11,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 10. "err10,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 9. "err9,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 8. "err8,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 7. "err7,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 6. "err6,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 5. "err5,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 4. "err4,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 3. "err3,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 2. "err2,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 1. "err1,Mask the the corresponding Error event line from generating an Interrupt" "0,1"
newline
bitfld.long 0x1C 0. "err0,Mask error AURORA_TX_UFC_ERR" "Error is Unmasked,Error is Masked"
line.long 0x20 "AURORA_TX_ERRAGG_STATUS,"
bitfld.long 0x20 15. "err15,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 14. "err14,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 13. "err13,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 12. "err12,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 11. "err11,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 10. "err10,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 9. "err9,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 8. "err8,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 7. "err7,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 6. "err6,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 5. "err5,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 4. "err4,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 3. "err3,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 2. "err2,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 1. "err1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x20 0. "err0,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
line.long 0x24 "AURORA_TX_ERRAGG_STATUS_RAW,"
bitfld.long 0x24 15. "err15,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 14. "err14,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 13. "err13,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 12. "err12,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 11. "err11,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 10. "err10,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 9. "err9,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 8. "err8,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 7. "err7,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 6. "err6,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 5. "err5,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 4. "err4,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 3. "err3,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 2. "err2,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 1. "err1,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
newline
bitfld.long 0x24 0. "err0,Read of 0x1 indicates a rising edge was detected on the corresponding Error event line" "0,1"
rgroup.long 0x230++0x03
line.long 0x00 "AURORA_TX_TPIU_DATA_PACKED,"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
newline
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
newline
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
newline
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
newline
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
newline
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
newline
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "EOI_VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
newline
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
newline
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
rgroup.long ($2+0x228)++0x03
line.long 0x00 "AURORA_TX_SERIALIZER_STATUS$1,"
repeat.end
repeat 16. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
group.long ($2+0x24)++0x03
line.long 0x00 "AURORA_TX_UDP_FRAME_HEADER$1,"
repeat.end
width 0x0B
tree.end
tree "TOP_CTRL (TOP Control Module Registers)"
base ad:0x30E0000
rgroup.long 0x00++0x0F
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "MSB16,"
bitfld.long 0x00 11.--15. "MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
line.long 0x04 "MDO_CTRL,"
bitfld.long 0x04 4. "SRC_SELECT,Select the source IP of LVDS Data" "Aurora on LVDS,CBUFF on LVDS"
bitfld.long 0x04 0. "AURORATX_SRC_SELECT,Select the TPIU source to TOP_AURORATX IP" "Measurement Data,Trace Data"
line.long 0x08 "PROBE_BUS_SEL0,"
line.long 0x0C "PROBE_BUS_SEL1,"
rgroup.long 0x21C++0x0B
line.long 0x00 "EFUSE_UID3,"
hexmask.long.tbyte 0x00 0.--23. 1. "val,EFUSE UID[120:96]"
line.long 0x04 "EFUSE_DEVICE_TYPE,"
hexmask.long.word 0x04 0.--15. 1. "val,EFUSE Device Type"
line.long 0x08 "EFUSE_FROM0_CHECKSUM,"
rgroup.long 0x400++0xA7
line.long 0x00 "EFUSE0_ROW_61,"
hexmask.long 0x00 0.--25. 1. "EFUSE0_ROW_61,Captures the EFUSE Value"
line.long 0x04 "EFUSE0_ROW_62,"
hexmask.long 0x04 0.--25. 1. "EFUSE0_ROW_62,Captures the EFUSE Value"
line.long 0x08 "EFUSE0_ROW_63,"
hexmask.long 0x08 0.--25. 1. "EFUSE0_ROW_63,Captures the EFUSE Value"
line.long 0x0C "EFUSE1_ROW_5,"
hexmask.long 0x0C 0.--25. 1. "EFUSE1_ROW_5,Captures the EFUSE Value"
line.long 0x10 "EFUSE1_ROW_6,"
hexmask.long 0x10 0.--25. 1. "EFUSE1_ROW_6,Captures the EFUSE Value"
line.long 0x14 "EFUSE1_ROW_7,"
hexmask.long 0x14 0.--25. 1. "EFUSE1_ROW_7,Captures the EFUSE Value"
line.long 0x18 "EFUSE1_ROW_8,"
hexmask.long 0x18 0.--25. 1. "EFUSE1_ROW_8,Captures the EFUSE Value"
line.long 0x1C "EFUSE1_ROW_9,"
hexmask.long 0x1C 0.--25. 1. "EFUSE1_ROW_9,Captures the EFUSE Value"
line.long 0x20 "EFUSE1_ROW_10,"
hexmask.long 0x20 0.--25. 1. "EFUSE1_ROW_10,Captures the EFUSE Value"
line.long 0x24 "EFUSE1_ROW_11,"
hexmask.long 0x24 0.--25. 1. "EFUSE1_ROW_11,Captures the EFUSE Value"
line.long 0x28 "EFUSE1_ROW_12,"
hexmask.long 0x28 0.--25. 1. "EFUSE1_ROW_12,Captures the EFUSE Value"
line.long 0x2C "EFUSE1_ROW_13,"
hexmask.long 0x2C 0.--25. 1. "EFUSE1_ROW_13,Captures the EFUSE Value"
line.long 0x30 "EFUSE1_ROW_14,"
hexmask.long 0x30 0.--25. 1. "EFUSE1_ROW_14,Captures the EFUSE Value"
line.long 0x34 "EFUSE1_ROW_15,"
hexmask.long 0x34 0.--25. 1. "EFUSE1_ROW_15,Captures the EFUSE Value"
line.long 0x38 "EFUSE1_ROW_16,"
hexmask.long 0x38 0.--25. 1. "EFUSE1_ROW_16,Captures the EFUSE Value"
line.long 0x3C "EFUSE1_ROW_17,"
hexmask.long 0x3C 0.--25. 1. "EFUSE1_ROW_17,Captures the EFUSE Value"
line.long 0x40 "EFUSE1_ROW_18,"
hexmask.long 0x40 0.--25. 1. "EFUSE1_ROW_18,Captures the EFUSE Value"
line.long 0x44 "EFUSE1_ROW_19,"
hexmask.long 0x44 0.--25. 1. "EFUSE1_ROW_19,Captures the EFUSE Value"
line.long 0x48 "EFUSE1_ROW_20,"
hexmask.long 0x48 0.--25. 1. "EFUSE1_ROW_20,Captures the EFUSE Value"
line.long 0x4C "EFUSE1_ROW_21,"
hexmask.long 0x4C 0.--25. 1. "EFUSE1_ROW_21,Captures the EFUSE Value"
line.long 0x50 "EFUSE1_ROW_22,"
hexmask.long 0x50 0.--25. 1. "EFUSE1_ROW_22,Captures the EFUSE Value"
line.long 0x54 "EFUSE1_ROW_23,"
hexmask.long 0x54 0.--25. 1. "EFUSE1_ROW_23,Captures the EFUSE Value"
line.long 0x58 "EFUSE1_ROW_24,"
hexmask.long 0x58 0.--25. 1. "EFUSE1_ROW_24,Captures the EFUSE Value"
line.long 0x5C "EFUSE1_ROW_25,"
hexmask.long 0x5C 0.--25. 1. "EFUSE1_ROW_25,Captures the EFUSE Value"
line.long 0x60 "EFUSE1_ROW_26,"
hexmask.long 0x60 0.--25. 1. "EFUSE1_ROW_26,Captures the EFUSE Value"
line.long 0x64 "EFUSE1_ROW_27,"
hexmask.long 0x64 0.--25. 1. "EFUSE1_ROW_27,Captures the EFUSE Value"
line.long 0x68 "EFUSE1_ROW_28,"
hexmask.long 0x68 0.--25. 1. "EFUSE1_ROW_28,Captures the EFUSE Value"
line.long 0x6C "EFUSE1_ROW_29,"
hexmask.long 0x6C 0.--25. 1. "EFUSE1_ROW_29,Captures the EFUSE Value"
line.long 0x70 "EFUSE1_ROW_30,"
hexmask.long 0x70 0.--25. 1. "EFUSE1_ROW_30,Captures the EFUSE Value"
line.long 0x74 "EFUSE1_ROW_31,"
hexmask.long 0x74 0.--25. 1. "EFUSE1_ROW_31,Captures the EFUSE Value"
line.long 0x78 "EFUSE1_ROW_32,"
hexmask.long 0x78 0.--25. 1. "EFUSE1_ROW_32,Captures the EFUSE Value"
line.long 0x7C "EFUSE1_ROW_33,"
hexmask.long 0x7C 0.--25. 1. "EFUSE1_ROW_33,Captures the EFUSE Value"
line.long 0x80 "EFUSE1_ROW_34,"
hexmask.long 0x80 0.--25. 1. "EFUSE1_ROW_34,Captures the EFUSE Value"
line.long 0x84 "EFUSE1_ROW_35,"
hexmask.long 0x84 0.--25. 1. "EFUSE1_ROW_35,Captures the EFUSE Value"
line.long 0x88 "EFUSE1_ROW_36,"
hexmask.long 0x88 0.--25. 1. "EFUSE1_ROW_36,Captures the EFUSE Value"
line.long 0x8C "EFUSE1_ROW_37,"
hexmask.long 0x8C 0.--25. 1. "EFUSE1_ROW_37,Captures the EFUSE Value"
line.long 0x90 "EFUSE1_ROW_38,"
hexmask.long 0x90 0.--25. 1. "EFUSE1_ROW_38,Captures the EFUSE Value"
line.long 0x94 "EFUSE1_ROW_39,"
hexmask.long 0x94 0.--25. 1. "EFUSE1_ROW_39,Captures the EFUSE Value"
line.long 0x98 "EFUSE1_ROW_40,"
hexmask.long 0x98 0.--25. 1. "EFUSE1_ROW_40,Captures the EFUSE Value"
line.long 0x9C "EFUSE1_ROW_41,"
hexmask.long 0x9C 0.--25. 1. "EFUSE1_ROW_41,Captures the EFUSE Value"
line.long 0xA0 "EFUSE1_ROW_42,"
hexmask.long 0xA0 0.--25. 1. "EFUSE1_ROW_42,Captures the EFUSE Value"
line.long 0xA4 "EFUSE1_ROW_43,"
hexmask.long 0xA4 0.--25. 1. "EFUSE1_ROW_43,Captures the EFUSE Value"
group.long 0x800++0x4B
line.long 0x00 "EFUSE_OVERRIDE_HSM_HALT_ON_ROM_ECC_ERR_EN,"
bitfld.long 0x00 4. "override_val,Override MMR value" "0,1"
bitfld.long 0x00 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x04 "EFUSE_OVERRIDE_MEM_MARGINCTRL,"
bitfld.long 0x04 28.--29. "brg_margin,Override MMR value" "0,1,2,3"
bitfld.long 0x04 24.--26. "brg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
newline
bitfld.long 0x04 20.--21. "byg_margin,Override MMR value" "0,1,2,3"
bitfld.long 0x04 16.--18. "byg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
newline
bitfld.long 0x04 12.--15. "gwg_margin,Override MMR value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x04 8.--10. "gwg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
newline
bitfld.long 0x04 4.--5. "glg_margin,Override MMR value" "0,1,2,3"
bitfld.long 0x04 0.--2. "glg_margin_override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x08 "EFUSE_OVERRIDE_LVDS_BGAP_TRIM,"
bitfld.long 0x08 4.--9. "override_val,Override MMR value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
bitfld.long 0x08 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x0C "EFUSE_OVERRIDE_XTAL_STABLIZATION_WAIT,"
bitfld.long 0x0C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x10 "EFUSE_OVERRIDE_SLICER_BIAS_RTRIM,"
bitfld.long 0x10 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x14 "EFUSE_OVERRIDE_XO_OUTPUT_DRIVE,"
bitfld.long 0x14 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x18 "EFUSE_OVERRIDE_RCOSC_TRIM_CODE,"
bitfld.long 0x18 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x1C "EFUSE_OVERRIDE_IP1_BG1_RTRIM,"
bitfld.long 0x1C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x20 "EFUSE_OVERRIDE_IP1_BG1_SLOPE,"
bitfld.long 0x20 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x24 "EFUSE_OVERRIDE_IP1_BG1_MAG,"
bitfld.long 0x24 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x28 "EFUSE_OVERRIDE_RS232_CLKMODE,"
bitfld.long 0x28 4. "override_val,Override value for RS232 Clock Mode" "Autobaud,Fixed Interval"
bitfld.long 0x28 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x2C "EFUSE_OVERRIDE_VMON_VDD_OV_UV_TRIM,"
bitfld.long 0x2C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x30 "EFUSE_OVERRIDE_VMON_VDDS_3P3_UV_TRIM,"
bitfld.long 0x30 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x34 "EFUSE_OVERRIDE_VMON_VDDA_OSC_TRIM,"
bitfld.long 0x34 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x38 "EFUSE_OVERRIDE_VDD_VT_DET,"
bitfld.long 0x38 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x3C "EFUSE_OVERRIDE_MASK_CPU_CLK_OUT_CTRL_LOWV_VAL,"
bitfld.long 0x3C 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x40 "EFUSE_OVERRIDE_MASK_CPU_CLK_OUT_CTRL_LOWV_SEL,"
bitfld.long 0x40 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x44 "EFUSE_OVERRIDE_EN_VOL_MON_FUNC,"
bitfld.long 0x44 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
line.long 0x48 "EFUSE_OVERRIDE_BYPASS_HOLDBUFFER_ENABLE,"
bitfld.long 0x48 4. "override_val,Override value for Hold Buffer Enable" "Disabled,Enabled"
bitfld.long 0x48 0.--2. "override,Override EFUSE Value with SW Value" "EFUSE Value,?,?,?,?,?,?,MMR Value"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x08 0. "PROT_ERR,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "ENABLED_PROXY_ERR,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "ENABLED_KICK_ERR,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "ENABLED_ADDR_ERR,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "ENABLED_PROT_ERR,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "PROXY_ERR_EN,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "KICK_ERR_EN,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "ADDR_ERR_EN,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "PROT_ERR_EN,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "PROXY_ERR_EN_CLR,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "KICK_ERR_EN_CLR,Kick access violation error enable clear" "0,1"
newline
bitfld.long 0x14 1. "ADDR_ERR_EN_CLR,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "PROT_ERR_EN_CLR,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "VECTOR,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "FAULT_NS,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "FAULT_TYPE,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "FAULT_XID,XID"
hexmask.long.word 0x24 8.--19. 1. "FAULT_ROUTEID,Route ID"
newline
hexmask.long.byte 0x24 0.--7. 1. "FAULT_PRIVID,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "FAULT_CLR,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 9. (list 0. 1. 2. 3. 4. 5. 6. 7. 8. )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
rgroup.long ($2+0x228)++0x03
line.long 0x00 "EFUSE_ROM_SEQ_UPDATE$1,"
repeat.end
repeat 3. (list 0. 1. 2. )(list 0x00 0x04 0x08 )
rgroup.long ($2+0x210)++0x03
line.long 0x00 "EFUSE_UID$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0x200)++0x03
line.long 0x00 "EFUSE_DIEID$1,"
repeat.end
width 0x0B
tree.end
tree "TOP_MDO_INFRA (TOP MDO INFRA Module Registers)"
base ad:0x3080000
rgroup.long 0x00++0x03
line.long 0x00 "PID,PID register"
hexmask.long.word 0x00 16.--31. 1. "PID_MSB16,"
bitfld.long 0x00 11.--15. "PID_MISC," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
bitfld.long 0x00 8.--10. "PID_MAJOR," "0,1,2,3,4,5,6,7"
bitfld.long 0x00 6.--7. "PID_CUSTOM," "0,1,2,3"
newline
bitfld.long 0x00 0.--5. "PID_MINOR," "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
group.long 0x14++0x14F
line.long 0x00 "SRC0_CTRL,"
bitfld.long 0x00 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x00 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x00 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x00 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x00 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x00 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x00 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x04 "SRC0_RANGE_START0,"
line.long 0x08 "SRC0_RANGE_END0,"
line.long 0x0C "SRC0_RANGE_START1,"
line.long 0x10 "SRC0_RANGE_END1,"
line.long 0x14 "SRC0_RANGE_START2,"
line.long 0x18 "SRC0_RANGE_END2,"
line.long 0x1C "SRC0_RANGE_START3,"
line.long 0x20 "SRC0_RANGE_END3,"
line.long 0x24 "SRC0_SW_TRIGGER,"
bitfld.long 0x24 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x24 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x28 "SRC0_THRESHOLD,"
hexmask.long.word 0x28 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x2C "SRC0_BW_CTRL,"
bitfld.long 0x2C 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x2C 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x2C 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x2C 0. "write_mode," "0,1"
line.long 0x30 "SRC0_CHANNEL,"
line.long 0x34 "SRC0_CHANNEL_CFG,"
bitfld.long 0x34 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x34 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x34 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x34 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x34 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0x38 "SRC1_CTRL,"
bitfld.long 0x38 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x38 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x38 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x38 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x38 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x38 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x38 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x3C "SRC1_RANGE_START0,"
line.long 0x40 "SRC1_RANGE_END0,"
line.long 0x44 "SRC1_RANGE_START1,"
line.long 0x48 "SRC1_RANGE_END1,"
line.long 0x4C "SRC1_RANGE_START2,"
line.long 0x50 "SRC1_RANGE_END2,"
line.long 0x54 "SRC1_RANGE_START3,"
line.long 0x58 "SRC1_RANGE_END3,"
line.long 0x5C "SRC1_SW_TRIGGER,"
bitfld.long 0x5C 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x5C 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x60 "SRC1_THRESHOLD,"
hexmask.long.word 0x60 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x64 "SRC1_BW_CTRL,"
bitfld.long 0x64 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x64 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x64 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x64 0. "write_mode," "0,1"
line.long 0x68 "SRC1_CHANNEL,"
line.long 0x6C "SRC1_CHANNEL_CFG,"
bitfld.long 0x6C 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x6C 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x6C 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x6C 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x6C 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0x70 "SRC2_CTRL,"
bitfld.long 0x70 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x70 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x70 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x70 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x70 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x70 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x70 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x74 "SRC2_RANGE_START0,"
line.long 0x78 "SRC2_RANGE_END0,"
line.long 0x7C "SRC2_RANGE_START1,"
line.long 0x80 "SRC2_RANGE_END1,"
line.long 0x84 "SRC2_RANGE_START2,"
line.long 0x88 "SRC2_RANGE_END2,"
line.long 0x8C "SRC2_RANGE_START3,"
line.long 0x90 "SRC2_RANGE_END3,"
line.long 0x94 "SRC2_SW_TRIGGER,"
bitfld.long 0x94 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x94 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x98 "SRC2_THRESHOLD,"
hexmask.long.word 0x98 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x9C "SRC2_BW_CTRL,"
bitfld.long 0x9C 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x9C 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x9C 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x9C 0. "write_mode," "0,1"
line.long 0xA0 "SRC2_CHANNEL,"
line.long 0xA4 "SRC2_CHANNEL_CFG,"
bitfld.long 0xA4 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xA4 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0xA4 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xA4 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0xA4 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0xA8 "SRC3_CTRL,"
bitfld.long 0xA8 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0xA8 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0xA8 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xA8 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0xA8 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0xA8 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0xA8 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0xAC "SRC3_RANGE_START0,"
line.long 0xB0 "SRC3_RANGE_END0,"
line.long 0xB4 "SRC3_RANGE_START1,"
line.long 0xB8 "SRC3_RANGE_END1,"
line.long 0xBC "SRC3_RANGE_START2,"
line.long 0xC0 "SRC3_RANGE_END2,"
line.long 0xC4 "SRC3_RANGE_START3,"
line.long 0xC8 "SRC3_RANGE_END3,"
line.long 0xCC "SRC3_SW_TRIGGER,"
bitfld.long 0xCC 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0xCC 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0xD0 "SRC3_THRESHOLD,"
hexmask.long.word 0xD0 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0xD4 "SRC3_BW_CTRL,"
bitfld.long 0xD4 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0xD4 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0xD4 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0xD4 0. "write_mode," "0,1"
line.long 0xD8 "SRC3_CHANNEL,"
line.long 0xDC "SRC3_CHANNEL_CFG,"
bitfld.long 0xDC 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xDC 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0xDC 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0xDC 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0xDC 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0xE0 "SRC4_CTRL,"
bitfld.long 0xE0 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0xE0 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0xE0 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0xE0 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0xE0 4. "port_sel,Select which bus to capture" "DSS_HWA_DMA0,DSS_HWA_DMA1"
bitfld.long 0xE0 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
newline
bitfld.long 0xE0 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
bitfld.long 0xE0 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0xE4 "SRC4_RANGE_START0,"
line.long 0xE8 "SRC4_RANGE_END0,"
line.long 0xEC "SRC4_RANGE_START1,"
line.long 0xF0 "SRC4_RANGE_END1,"
line.long 0xF4 "SRC4_RANGE_START2,"
line.long 0xF8 "SRC4_RANGE_END2,"
line.long 0xFC "SRC4_RANGE_START3,"
line.long 0x100 "SRC4_RANGE_END3,"
line.long 0x104 "SRC4_SW_TRIGGER,"
bitfld.long 0x104 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x104 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x108 "SRC4_THRESHOLD,"
hexmask.long.word 0x108 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x10C "SRC4_BW_CTRL,"
bitfld.long 0x10C 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x10C 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x10C 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x10C 0. "write_mode," "0,1"
line.long 0x110 "SRC4_CHANNEL,"
line.long 0x114 "SRC4_CHANNEL_CFG,"
bitfld.long 0x114 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x114 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x114 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x114 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x114 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
line.long 0x118 "SRC5_CTRL,"
bitfld.long 0x118 20. "gen_marker_on_flush,Write 0x1 to generate a marker on Flush trigger" "0,1"
bitfld.long 0x118 16.--19. "range_en,Enable the corresponding range for data capture" "Range 0 is disabled,Range 0 is enableld,?..."
newline
bitfld.long 0x118 12.--15. "hw_flush_en,Write 0x1 to enable HW Marker trigger to generate a Flush" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
bitfld.long 0x118 8.--11. "hw_marker_en,Write 0x1 to enable HW Marker trigger to generate a Marker" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
newline
bitfld.long 0x118 2. "crop_en,Chop of the sign extension bits [15:12] for every 16 bits of data" "Send all 16 bits,Send lower 12 of 16 bits"
bitfld.long 0x118 1. "snif_mode,Select which bus to capture" "Read Bus,Write Bus"
newline
bitfld.long 0x118 0. "enable,Indicates is the sniffer block is active or inactive" "Captuere is Disabled,Sniffer Enabled"
line.long 0x11C "SRC5_RANGE_START0,"
line.long 0x120 "SRC5_RANGE_END0,"
line.long 0x124 "SRC5_RANGE_START1,"
line.long 0x128 "SRC5_RANGE_END1,"
line.long 0x12C "SRC5_RANGE_START2,"
line.long 0x130 "SRC5_RANGE_END2,"
line.long 0x134 "SRC5_RANGE_START3,"
line.long 0x138 "SRC5_RANGE_END3,"
line.long 0x13C "SRC5_SW_TRIGGER,"
bitfld.long 0x13C 4. "flush,Write 0x1 to trigger a Flush" "0,1"
bitfld.long 0x13C 0. "marker,Write 0x1 to insert a Marker" "0,1"
line.long 0x140 "SRC5_THRESHOLD,"
hexmask.long.word 0x140 0.--9. 1. "threshold,The FIFO threshold to trigger writes from the Source FIFO"
line.long 0x144 "SRC5_BW_CTRL,"
bitfld.long 0x144 28.--30. "priority," "0,1,2,3,4,5,6,7"
bitfld.long 0x144 16.--20. "burst_size,The burst_size is the minimum size for which the SRC will keep arbitration once it wins" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
newline
hexmask.long.byte 0x144 4.--11. 1. "burst_num,The FIFO threshold to trigger writes from the Source FIFO"
bitfld.long 0x144 0. "write_mode," "0,1"
line.long 0x148 "SRC5_CHANNEL,"
line.long 0x14C "SRC5_CHANNEL_CFG,"
bitfld.long 0x14C 4. "NONDATA_TIMESTAMPED,Selects whether the Non Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x14C 3. "NONDATA_GUARANTEED,Selects whether the Non Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
newline
bitfld.long 0x14C 2. "DATA_TIMESTAMPED,Selects whether the Data access for the Source is timestamped" "No Timestamp,Timestamped"
bitfld.long 0x14C 1. "DATA_MARKED,Selects whether the Data access for the Source is marked" "Un-Marked,Marked"
newline
bitfld.long 0x14C 0. "DATA_GUARANTEED,Selects whether the Data access for the Source is Guaranteed or Invariant Timing" "Time Invariant,Guaranteed"
group.long 0x1D4++0x1B
line.long 0x00 "SRC0_STATUS,"
hexmask.long.word 0x00 16.--31. 1. "status,Status of the Sniffer for Source 0"
bitfld.long 0x00 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x00 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x00 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x00 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x04 "SRC1_STATUS,"
hexmask.long.word 0x04 16.--31. 1. "status,Status of the Sniffer for Source 1"
bitfld.long 0x04 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x04 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x04 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x04 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x08 "SRC2_STATUS,"
hexmask.long.word 0x08 16.--31. 1. "status,Status of the Sniffer for Source 2"
bitfld.long 0x08 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x08 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x08 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x08 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x0C "SRC3_STATUS,"
hexmask.long.word 0x0C 16.--31. 1. "status,Status of the Sniffer for Source 3"
bitfld.long 0x0C 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x0C 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x0C 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x0C 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x10 "SRC4_STATUS,"
hexmask.long.word 0x10 16.--31. 1. "status,Status of the Sniffer for Source 4"
bitfld.long 0x10 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x10 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x10 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x10 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x14 "SRC5_STATUS,"
hexmask.long.word 0x14 16.--31. 1. "status,Status of the Sniffer for Source 5"
bitfld.long 0x14 3. "overflow_err,Source Overflow Error is generated with the Source FIFO is full and there is no space to write the sniffed data" "0,1"
newline
bitfld.long 0x14 2. "flush_err,Flush Err is generated on Multiple Flush requests" "0,1"
bitfld.long 0x14 1. "data_miss,Data Miss Erro is generated when a Flush or Marker Requested causes Miss in the Sniffer data" "0,1"
newline
bitfld.long 0x14 0. "flush_done,Flush Done is generated on completion of a flush request" "0,1"
line.long 0x18 "INTERRUPT_MASK,"
group.long 0xFF0++0x07
line.long 0x00 "HW_SPARE_WPH,"
line.long 0x04 "HW_SPARE_REC,"
bitfld.long 0x04 31. "hw_spare_rec31,Reserved for HW R&D" "0,1"
bitfld.long 0x04 30. "hw_spare_rec30,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 29. "hw_spare_rec29,Reserved for HW R&D" "0,1"
bitfld.long 0x04 28. "hw_spare_rec28,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 27. "hw_spare_rec27,Reserved for HW R&D" "0,1"
bitfld.long 0x04 26. "hw_spare_rec26,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 25. "hw_spare_rec25,Reserved for HW R&D" "0,1"
bitfld.long 0x04 24. "hw_spare_rec24,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 23. "hw_spare_rec23,Reserved for HW R&D" "0,1"
bitfld.long 0x04 22. "hw_spare_rec22,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 21. "hw_spare_rec21,Reserved for HW R&D" "0,1"
bitfld.long 0x04 20. "hw_spare_rec20,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 19. "hw_spare_rec19,Reserved for HW R&D" "0,1"
bitfld.long 0x04 18. "hw_spare_rec18,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 17. "hw_spare_rec17,Reserved for HW R&D" "0,1"
bitfld.long 0x04 16. "hw_spare_rec16,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 15. "hw_spare_rec15,Reserved for HW R&D" "0,1"
bitfld.long 0x04 14. "hw_spare_rec14,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 13. "hw_spare_rec13,Reserved for HW R&D" "0,1"
bitfld.long 0x04 12. "hw_spare_rec12,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 11. "hw_spare_rec11,Reserved for HW R&D" "0,1"
bitfld.long 0x04 10. "hw_spare_rec10,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 9. "hw_spare_rec9,Reserved for HW R&D" "0,1"
bitfld.long 0x04 8. "hw_spare_rec8,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 7. "hw_spare_rec7,Reserved for HW R&D" "0,1"
bitfld.long 0x04 6. "hw_spare_rec6,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 5. "hw_spare_rec5,Reserved for HW R&D" "0,1"
bitfld.long 0x04 4. "hw_spare_rec4,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 3. "hw_spare_rec3,Reserved for HW R&D" "0,1"
bitfld.long 0x04 2. "hw_spare_rec2,Reserved for HW R&D" "0,1"
newline
bitfld.long 0x04 1. "hw_spare_rec1,Reserved for HW R&D" "0,1"
bitfld.long 0x04 0. "hw_spare_rec0,Reserved for HW R&D" "0,1"
group.long 0x1008++0x2B
line.long 0x00 "LOCK0_KICK0,- KICK0 component"
line.long 0x04 "LOCK0_KICK1,- KICK1 component"
line.long 0x08 "intr_raw_status,Interrupt Raw Status/Set Register"
bitfld.long 0x08 3. "proxy_err,Proxy0 access violation error" "0,1"
bitfld.long 0x08 2. "kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x08 1. "addr_err,Addressing violation error" "0,1"
bitfld.long 0x08 0. "prot_err,Protection violation error" "0,1"
line.long 0x0C "intr_enabled_status_clear,Interrupt Enabled Status/Clear register"
bitfld.long 0x0C 3. "enabled_proxy_err,Proxy0 access violation error" "0,1"
bitfld.long 0x0C 2. "enabled_kick_err,Kick access violation error" "0,1"
newline
bitfld.long 0x0C 1. "enabled_addr_err,Addressing violation error" "0,1"
bitfld.long 0x0C 0. "enabled_prot_err,Protection violation error" "0,1"
line.long 0x10 "intr_enable,Interrupt Enable register"
bitfld.long 0x10 3. "proxy_err_en,Proxy0 access violation error enable" "0,1"
bitfld.long 0x10 2. "kick_err_en,Kick access violation error enable" "0,1"
newline
bitfld.long 0x10 1. "addr_err_en,Addressing violation error enable" "0,1"
bitfld.long 0x10 0. "prot_err_en,Protection violation error enable" "0,1"
line.long 0x14 "intr_enable_clear,Interrupt Enable Clear register"
bitfld.long 0x14 3. "proxy_err_en_clr,Proxy0 access violation error enable clear" "0,1"
bitfld.long 0x14 2. "kick_err_en_clr,Kick access violation error enable clear" "0,1"
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bitfld.long 0x14 1. "addr_err_en_clr,Addressing violation error enable clear" "0,1"
bitfld.long 0x14 0. "prot_err_en_clr,Protection violation error enable clear" "0,1"
line.long 0x18 "eoi,EOI register"
hexmask.long.byte 0x18 0.--7. 1. "eoi_vector,EOI vector value"
line.long 0x1C "fault_address,Fault Address register"
line.long 0x20 "fault_type_status,Fault Type Status register"
bitfld.long 0x20 6. "fault_ns,Non-secure access" "0,1"
bitfld.long 0x20 0.--5. "fault_type,Fault Type" "No fault,User execute fault - priv = 0 dir = 1 dtype = 1,User write fault - priv = 0 dir = 0,?,User read fault - priv = 0 dir = 1 dtype = 1,?,?,?,Supervisor execute fault - priv = 1 dir = 1..,?,?,?,?,?,?,?,Supervisor write fault - priv = 1 dir = 0,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,Supervisor read fault - priv = 1 dir = 1 dtype..,?..."
line.long 0x24 "fault_attr_status,Fault Attribute Status register"
hexmask.long.word 0x24 20.--31. 1. "fault_xid,XID"
hexmask.long.word 0x24 8.--19. 1. "fault_routeid,Route ID"
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hexmask.long.byte 0x24 0.--7. 1. "fault_privid,Privilege ID"
line.long 0x28 "fault_clear,Fault Clear register"
bitfld.long 0x28 0. "fault_clr,Fault clear" "0,1"
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
rgroup.long ($2+0xFE0)++0x03
line.long 0x00 "HW_SPARE_RO$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0xFD0)++0x03
line.long 0x00 "HW_SPARE_RW$1,"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
group.long ($2+0x04)++0x03
line.long 0x00 "HW_REG$1,"
repeat.end
width 0x0B
tree.end
tree "TOP_PBIST (TOP PBIST Module Registers)"
base ad:0x2F79400
hgroup.long 0x120++0x07
hide.long 0x00 "PBIST_DD10,DD0 Data Register 16 (D0)"
hide.long 0x04 "PBIST_DE10,DE0 Data Register 16 (D0)"
group.long 0x160++0x03
line.long 0x00 "PBIST_RAMT,RAM Configuration (RAMT -RAM)"
hexmask.long.byte 0x00 24.--31. 1. "RGS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 16.--23. 1. "RDS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 8.--15. 1. "DWR,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
hexmask.long.byte 0x00 0.--7. 1. "RAM,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset"
group.word 0x164++0x01
line.word 0x00 "PBIST_DLR,Datalogger 0"
hexmask.word.byte 0x00 8.--15. 1. "DLR1,Datalogger Register [8] : Reserevd [9] : Default Testing Mode"
hexmask.word.byte 0x00 0.--7. 1. "DLR0,Datalogger Register [1:0] : Reserved [2] : ROM-based testing mode"
group.byte 0x168++0x00
line.byte 0x00 "PBIST_CMS,Clock mux select"
bitfld.byte 0x00 0.--3. "PBIST_CMS,TI Internal Register.Reserved for HW RnD These registers do not have a default value after reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
group.byte 0x16C++0x00
line.byte 0x00 "PBIST_PC,Program Control"
bitfld.byte 0x00 0.--4. "PBIST_PC,TI Internal Register.Reserved for HW RnD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
group.long 0x178++0x03
line.long 0x00 "PBIST_CS,Chip Select 0"
hexmask.long.byte 0x00 24.--31. 1. "CS3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "CS2,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 8.--15. 1. "CS1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "CS0,TI Internal Register.Reserved for HW RnD"
group.byte 0x17C++0x00
line.byte 0x00 "PBIST_FDLY,Fail Delay"
group.byte 0x180++0x00
line.byte 0x00 "PBIST_PACT,Pbist Active"
bitfld.byte 0x00 0. "PBIST_PACT,Pbist Active/ROM Clock Enable Register [0]: This bit must be set to turn on internal PBIST clocks" "Disable internal PBIST clocks Value,Enable internal PBIST clocks"
group.byte 0x184++0x00
line.byte 0x00 "PBIST_ID,PBIST ID"
bitfld.byte 0x00 0.--4. "PBIST_ID,PBIST ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
hgroup.long 0x188++0x03
hide.long 0x00 "PBIST_OVR,PBIST Overrides"
rgroup.byte 0x190++0x00
line.byte 0x00 "PBIST_FSFR0,Fail status fail - port 0"
bitfld.byte 0x00 0. "PBIST_FSFR0,Fail Status Fail Register- Port 0 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x194++0x00
line.byte 0x00 "PBIST_FSFR1,Fail status fail - port 1"
bitfld.byte 0x00 0. "PBIST_FSFR1,Fail Status Fail Register- Port 1 This register indicates if a failure occurred during a memory self-test" "No failure occurred Value,Indicates a failure"
rgroup.byte 0x198++0x00
line.byte 0x00 "PBIST_FSRCR0,Fail Count fail - port 0"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR0,Fail Status Count - Port 0 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
rgroup.byte 0x19C++0x00
line.byte 0x00 "PBIST_FSRCR1,Fail Count fail - port 1"
bitfld.byte 0x00 0.--3. "PBIST_FSRCR1,Fail Status Count - Port 1 These registers keep count of the number of failures observed during the memory self-test" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
hgroup.long 0x1A0++0x03
hide.long 0x00 "PBIST_FSRA0,Fail status address - port 0"
rgroup.word 0x1A4++0x01
line.word 0x00 "PBIST_FSRA1,Fail status address - port 1"
hgroup.long 0x1B4++0x0B
hide.long 0x00 "PBIST_MARGIN,Margin Mode"
hide.long 0x04 "PBIST_WRENZ,WRENZ"
hide.long 0x08 "PBIST_PGS,PAGE/PGS"
group.byte 0x1C0++0x00
line.byte 0x00 "PBIST_ROM,Rom Mask"
bitfld.byte 0x00 0.--1. "PBIST_ROM,Rom Mask" "No information is used from ROM Value,Only RAM Group information from ROM Vaule,Only Algorithm information from ROM Value,Both Algorithm and RAM information from ROM"
group.long 0x1C4++0x0B
line.long 0x00 "PBIST_ALGO,ROM Algorithm Mask 0"
hexmask.long.byte 0x00 24.--31. 1. "ALGO3,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 16.--23. 1. "ALGO2,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 8.--15. 1. "ALGO1,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
hexmask.long.byte 0x00 0.--7. 1. "ALGO0,This register is used to indicate the algorithm(s) to be used for the memory self-test routine"
line.long 0x04 "PBIST_RINFOL,RAM Info Mask Lower 0"
hexmask.long.byte 0x04 24.--31. 1. "RINFOL3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 16.--23. 1. "RINFOL2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 8.--15. 1. "RINFOL1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x04 0.--7. 1. "RINFOL0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
line.long 0x08 "PBIST_RINFOU,RAM Info Mask Upper 0"
hexmask.long.byte 0x08 24.--31. 1. "RINFOU3,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 16.--23. 1. "RINFOU2,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 8.--15. 1. "RINFOU1,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
hexmask.long.byte 0x08 0.--7. 1. "RINFOU0,This register is to select memory groups to run the algorithms selected in the PBIST_ALGO register"
repeat 2. (list 0. 1. )(list 0x00 0x08 )
rgroup.long ($2+0x1A8)++0x03
line.long 0x00 "PBIST_FSRDL$1,Fail status Data - port 0"
repeat.end
repeat 2. (list 1. 4. )(list 0x00 0x04 )
group.long ($2+0x170)++0x03
line.long 0x00 "PBIST_SCR$1,Address Scramble 0 -3"
hexmask.long.byte 0x00 24.--31. 1. "SCR3,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 16.--23. 1. "SCR2,TI Internal Register.Reserved for HW RnD"
newline
hexmask.long.byte 0x00 8.--15. 1. "SCR1,TI Internal Register.Reserved for HW RnD"
hexmask.long.byte 0x00 0.--7. 1. "SCR0,TI Internal Register.Reserved for HW RnD"
repeat.end
repeat 2. (list 2. 3. )(list 0x00 0x04 )
group.word ($2+0x158)++0x01
line.word 0x00 "PBIST_CI$1,Constant Increment Register2"
repeat.end
repeat 2. (list 0. 1. )(list 0x00 0x04 )
hgroup.long ($2+0x150)++0x03
hide.long 0x00 "PBIST_CI$1,Constant Increment Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x140)++0x03
hide.long 0x00 "PBIST_CL$1,Constant Loop Count Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x130)++0x03
hide.long 0x00 "PBIST_CA$1,Constant Address Register0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x110)++0x03
hide.long 0x00 "PBIST_L$1,Variable Loop Count Register L0"
repeat.end
repeat 4. (list 0. 1. 2. 3. )(list 0x00 0x04 0x08 0x0C )
hgroup.long ($2+0x100)++0x03
hide.long 0x00 "PBIST_A$1,Variable Address Register0"
repeat.end
width 0x0B
tree.end
endif
autoindent.off
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